riscv-rt: Adjustments to run picorv32 #367
Description
I'm trying to use riscv-rt on https://github.com/YosysHQ/picorv32
I managed to get it to work with the following hack:
diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
index b3041bf..01f8d73 100644
--- a/riscv-rt/src/asm.rs
+++ b/riscv-rt/src/asm.rs
@@ -63,22 +63,8 @@ _start:",
_abs_start:
.option norelax
.cfi_startproc
- .cfi_undefined ra",
- // Disable interrupts
- #[cfg(all(feature = "s-mode", not(feature = "no-xie-xip")))]
- "csrw sie, 0
- csrw sip, 0",
- #[cfg(all(not(feature = "s-mode"), not(feature = "no-xie-xip")))]
- "csrw mie, 0
- csrw mip, 0",
- #[cfg(not(feature = "s-mode"))]
- "csrr a0, mhartid", // Make sure that the hart ID is in a0 in M-mode
- // Set pre-init trap vector
- "la t0, _pre_init_trap",
- #[cfg(feature = "s-mode")]
- "csrw stvec, t0",
- #[cfg(not(feature = "s-mode"))]
- "csrw mtvec, t0",
+ .cfi_undefined ra
+ li a0, 0",
// If multi-hart, assert that hart ID is valid
#[cfg(not(feature = "single-hart"))]
"lui t0, %hi(_max_hart_id)And in my main.rs I added the following to avoid calling any CSR instructions:
#[unsafe(export_name = "_setup_interrupts")]
pub fn setup_interrupts() {}Maybe we could put interrupts under a feature?