|
8736 | 8736 | "@ |
8737 | 8737 | cvtsd2ss\t{%2, %0|%0, %2} |
8738 | 8738 | cvtsd2ss\t{%2, %0|%0, %q2} |
8739 | | - vcvtsd2ss\t{<round_mask_op3>%2, %1, %0<mask_operand3>|<mask_operand3>%0, %1, %q2<round_mask_op3>}" |
| 8739 | + vcvtsd2ss\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %q2<round_mask_op3>}" |
8740 | 8740 | [(set_attr "isa" "noavx,noavx,avx") |
8741 | 8741 | (set_attr "type" "ssecvt") |
8742 | 8742 | (set_attr "athlon_decode" "vector,double,*") |
|
8780 | 8780 | "@ |
8781 | 8781 | cvtss2sd\t{%2, %0|%0, %2} |
8782 | 8782 | cvtss2sd\t{%2, %0|%0, %k2} |
8783 | | - vcvtss2sd\t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>|<mask_operand3>%0, %1, %k2<round_saeonly_mask_op3>}" |
| 8783 | + vcvtss2sd\t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %k2<round_saeonly_mask_op3>}" |
8784 | 8784 | [(set_attr "isa" "noavx,noavx,avx") |
8785 | 8785 | (set_attr "type" "ssecvt") |
8786 | 8786 | (set_attr "amdfam10_decode" "vector,double,*") |
|
14167 | 14167 | "TARGET_AVX512VL" |
14168 | 14168 | { |
14169 | 14169 | if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 4) |
14170 | | - return "vpmov<trunsuffix><pmov_suff_4>\t{%1, %0%{%2%}|%0%{%2%}, %t1}"; |
14171 | | - return "vpmov<trunsuffix><pmov_suff_4>\t{%1, %0%{%2%}|%0%{%2%}, %g1}"; |
| 14170 | + return "vpmov<trunsuffix><pmov_suff_4>\t{%1, %0%{%2%}|%0%{%2%}, %1}"; |
| 14171 | + return "vpmov<trunsuffix><pmov_suff_4>\t{%1, %0%{%2%}|%0%{%2%}, %1}"; |
14172 | 14172 | } |
14173 | 14173 | [(set_attr "type" "ssemov") |
14174 | 14174 | (set_attr "memory" "store") |
|
14267 | 14267 | (match_dup 0) |
14268 | 14268 | (match_operand:QI 2 "register_operand" "Yk")))] |
14269 | 14269 | "TARGET_AVX512VL" |
14270 | | - "vpmov<trunsuffix>qw\t{%1, %0%{%2%}|%0%{%2%}, %g1}" |
| 14270 | + "vpmov<trunsuffix>qw\t{%1, %0%{%2%}|%0%{%2%}, %1}" |
14271 | 14271 | [(set_attr "type" "ssemov") |
14272 | 14272 | (set_attr "memory" "store") |
14273 | 14273 | (set_attr "prefix" "evex") |
|
0 commit comments