rustc_target: RISC-V: feature addition batch 2

This commit adds unprivileged ratified extensions that are either
dicoverable from the `riscv_hwprobe` syscall of the Linux kernel (as of
version 6.14) plus 1 minus 2 extensions.

Plus 1:

*   "B"
    This is a combination of "Zba", "Zbb" and "Zbs".
    Note:
    Although not required by the RISC-V specification, it is convenient to
    imply "B" from its three members (will be implemented in LLVM 21/22) but
    this is not yet implemented in Rust due to current implication handling.
    It still implies three members *from* "B".

Minus 2:

*   "Zcf" (target_arch = "riscv32" only)
    This is the compression instruction subset corresponding "F".
    This is implied from RV32 + "C" + "F" but this complex handling is
    not yet supported by Rust's feature handling.
*   "Zcd"
    This is the compression instruction subset corresponding "D".
    This is implied from "C" + "D" but this complex handling is
    not yet supported by Rust's feature handling.

Notes:

*   Because this commit adds the "Zca" extension (an integer subset of the
    "C" extension), the "C" extension is modified to imply "Zca".
*   The "Supm" extension requires LLVM 20 yet it should not affect codegen
    on LLVM 19 because this extension does not specify any mechanism to
    control pointer masking (just tells the availability from the user mode
    and *some* way to control pointer masking like a system call).

Author: a4lg

compiler/rustc_codegen_llvm/src/llvm_util.rs

@@ -272,6 +272,7 @@ pub(crate) fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> Option<LLVMFea
         ("aarch64", "fpmr") => None, // only existed in 18
         ("arm", "fp16") => Some(LLVMFeature::new("fullfp16")),
         // Filter out features that are not supported by the current LLVM version
+        ("riscv32" | "riscv64", "supm") if get_version().0 < 20 => None,
         ("riscv32" | "riscv64", "zacas") if get_version().0 < 20 => None,
         // Enable the evex512 target feature if an avx512 target feature is enabled.
         ("x86", s) if s.starts_with("avx512") => {

compiler/rustc_target/src/target_features.rs

@@ -491,7 +491,8 @@ const MIPS_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
 static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
     // tidy-alphabetical-start
     ("a", Stable, &["zaamo", "zalrsc"]),
-    ("c", Stable, &[]),
+    ("b", Unstable(sym::riscv_target_feature), &["zba", "zbb", "zbs"]),
+    ("c", Stable, &["zca"]),
     ("d", Unstable(sym::riscv_target_feature), &["f"]),
     ("e", Unstable(sym::riscv_target_feature), &[]),
     ("f", Unstable(sym::riscv_target_feature), &["zicsr"]),
@@ -502,6 +503,7 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
     ),
     ("m", Stable, &[]),
     ("relax", Unstable(sym::riscv_target_feature), &[]),
+    ("supm", Unstable(sym::riscv_target_feature), &[]),
     ("unaligned-scalar-mem", Unstable(sym::riscv_target_feature), &[]),
     ("unaligned-vector-mem", Unstable(sym::riscv_target_feature), &[]),
     ("v", Unstable(sym::riscv_target_feature), &["zvl128b", "zve64d"]),
@@ -520,17 +522,25 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
     ("zbkc", Stable, &[]),
     ("zbkx", Stable, &[]),
     ("zbs", Stable, &[]),
+    ("zca", Unstable(sym::riscv_target_feature), &[]),
+    ("zcb", Unstable(sym::riscv_target_feature), &["zca"]),
+    ("zcmop", Unstable(sym::riscv_target_feature), &["zca"]),
     ("zdinx", Unstable(sym::riscv_target_feature), &["zfinx"]),
+    ("zfa", Unstable(sym::riscv_target_feature), &["f"]),
     ("zfh", Unstable(sym::riscv_target_feature), &["zfhmin"]),
     ("zfhmin", Unstable(sym::riscv_target_feature), &["f"]),
     ("zfinx", Unstable(sym::riscv_target_feature), &["zicsr"]),
     ("zhinx", Unstable(sym::riscv_target_feature), &["zhinxmin"]),
     ("zhinxmin", Unstable(sym::riscv_target_feature), &["zfinx"]),
+    ("zicboz", Unstable(sym::riscv_target_feature), &[]),
     ("zicntr", Unstable(sym::riscv_target_feature), &["zicsr"]),
+    ("zicond", Unstable(sym::riscv_target_feature), &[]),
     ("zicsr", Unstable(sym::riscv_target_feature), &[]),
     ("zifencei", Unstable(sym::riscv_target_feature), &[]),
+    ("zihintntl", Unstable(sym::riscv_target_feature), &[]),
     ("zihintpause", Unstable(sym::riscv_target_feature), &[]),
     ("zihpm", Unstable(sym::riscv_target_feature), &["zicsr"]),
+    ("zimop", Unstable(sym::riscv_target_feature), &[]),
     ("zk", Stable, &["zkn", "zkr", "zkt"]),
     ("zkn", Stable, &["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"]),
     ("zknd", Stable, &[]),
@@ -541,6 +551,7 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
     ("zksed", Stable, &[]),
     ("zksh", Stable, &[]),
     ("zkt", Stable, &[]),
+    ("ztso", Unstable(sym::riscv_target_feature), &[]),
     ("zvbb", Unstable(sym::riscv_target_feature), &["zvkb"]),
     ("zvbc", Unstable(sym::riscv_target_feature), &["zve64x"]),
     ("zve32f", Unstable(sym::riscv_target_feature), &["zve32x", "f"]),

tests/ui/check-cfg/target_feature.stderr

@@ -49,6 +49,7 @@ LL |     cfg!(target_feature = "_UNEXPECTED_VALUE");
 `avxvnni`
 `avxvnniint16`
 `avxvnniint8`
+`b`
 `backchain`
 `bf16`
 `bmi1`
@@ -233,6 +234,7 @@ LL |     cfg!(target_feature = "_UNEXPECTED_VALUE");
 `ssve-fp8dot2`
 `ssve-fp8dot4`
 `ssve-fp8fma`
+`supm`
 `sve`
 `sve-b16b16`
 `sve2`
@@ -318,17 +320,25 @@ LL |     cfg!(target_feature = "_UNEXPECTED_VALUE");
 `zbkc`
 `zbkx`
 `zbs`
+`zca`
+`zcb`
+`zcmop`
 `zdinx`
+`zfa`
 `zfh`
 `zfhmin`
 `zfinx`
 `zhinx`
 `zhinxmin`
+`zicboz`
 `zicntr`
+`zicond`
 `zicsr`
 `zifencei`
+`zihintntl`
 `zihintpause`
 `zihpm`
+`zimop`
 `zk`
 `zkn`
 `zknd`
@@ -339,6 +349,7 @@ LL |     cfg!(target_feature = "_UNEXPECTED_VALUE");
 `zksed`
 `zksh`
 `zkt`
+`ztso`
 `zvbb`
 `zvbc`
 `zve32f`