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@jhpratt jhpratt commented Jul 20, 2025

Successful merges:

r? @ghost
@rustbot modify labels: rollup

Create a similar rollup

GuillaumeGomez and others added 30 commits July 16, 2025 14:27
This should have used build-pass rather than check-pass.
This is no longer implied by -wasm-enable-eh.
The presence of `@add-core-stubs` indicates that this was already
intended.
According to
https://discourse.llvm.org/t/rfc-volatile-access-to-non-dereferenceable-memory-may-be-well-defined/86303/4,
LLVM allows volatile operations on null and handles it correctly. This
should be allowed in Rust as well, because I/O memory may be hard-coded
to address 0 in some cases, like the AVR chip ATtiny1626.

A test case that ensured a failure when passing null to volatile was
removed, since it's now valid.

Due to the addition of `maybe_is_aligned` to `ub_checks`,
`maybe_is_aligned_and_not_null` was refactored to use it.

docs: revise restrictions on volatile operations

A distinction between usage on Rust memory vs. non-Rust memory was
introduced. Documentation was reworded to explain what that means, and
make explicit that:

- No trapping can occur from volatile operations;
- On Rust memory, all safety rules must be respected;
- On Rust memory, the primary difference from regular access is that
  volatile always involves a memory dereference;
- On Rust memory, the only data affected by an operation is the one
  pointed to in the argument(s) of the function;
- On Rust memory, provenance follows the same rules as non-volatile
  access;
- On non-Rust memory, any address known to not contain Rust memory is
  valid (including 0 and usize::MAX);
- On non-Rust memory, no Rust memory may be affected (it is implicit
  that any other non-Rust memory may be affected, though, even if not
  referenced by the pointer). This should be relevant when, for example,
  reading register A causes a flag to change in register B, or writing
  to A causes B to change in some way. Everything affected mustn't be
  inside an allocation.
- On non-Rust memory, provenance is irrelevant and a pointer with none
  can be used in a valid way.

fix: don't lint null as UB for volatile

Also remove a now-unneeded `allow` line.

fix: additional wording nits
Allow volatile access to non-Rust memory, including address 0

This PR relaxes the `ub_check` in the `read_volatile`/`write_volatile` pointer operations to allow passing null. This is needed to support processors which hard-code peripheral registers on address 0, like the AVR chip ATtiny1626. LLVM understands this as valid and handles it correctly, as tested in my [PR to add a note about it](llvm/llvm-project@6387c82#diff-81bbb96298c32fa901beb82ab3b97add27a410c01d577c1f8c01000ed2055826) (rustc generates the same LLVM IR as expected there when this PR is applied, and consequently the same AVR assembly).

Follow-up and implementation of the discussions in:
- https://internals.rust-lang.org/t/pre-rfc-conditionally-supported-volatile-access-to-address-0/12881/7
- Rahix/avr-device#185;
- [#t-lang > Adding the possibility of volatile access to address 0](https://rust-lang.zulipchat.com/#narrow/channel/213817-t-lang/topic/Adding.20the.20possibility.20of.20volatile.20access.20to.20address.200/with/513303502)
- https://discourse.llvm.org/t/rfc-volatile-access-to-non-dereferenceable-memory-may-be-well-defined/86303

r? ``@RalfJung``

Also fixes rust-lang/unsafe-code-guidelines#29 (about as good as it'll get, null will likely never be a "normal" address in Rust)
… r=RalfJung

Stabilize `const_float_round_methods`

Closes rust-lang#141555, waiting for FCP.
…-errors

Ban projecting into SIMD types [MCP838]

Closes rust-lang/compiler-team#838

The actual compiler change here is tiny; there's just a bazillion tests to update.

~~Since I'm sure I've missed some, for now~~
~~r ghost~~

try-job: test-various
…lbinarycat

[rustdoc] Make aliases search support partial matching

Fixes rust-lang#140782.

To make this work, I moved aliases into the `searchIndex` like any other item. It links to the "original" item with a new `original` field. No so great part is that we need to have some fields like `bitIndex` to be set on the alias to make the description load to work but I consider it minor enough to be ok.

This PR voluntarily doesn't handle de-prioritization of aliases as `@lolbinarycat` wished to work on this so I'll leave them this part. 😉

cc `@lolbinarycat`
Fix debuginfo-lto-alloc.rs test

This should have used build-pass rather than check-pass.
jhpratt added 8 commits July 19, 2025 23:56
…d, r=jhpratt

Remove deprecated `MaybeUninit` slice methods

These were left in to make migration a bit easier, although they should be removed now since they were never stable.
Fixes for LLVM 21

This fixes compatibility issues with LLVM 21 without performing the actual upgrade. Split out from rust-lang#143684.

This fixes three issues:
 * Updates the AMDGPU data layout for address space 8.
 * Makes emit-arity-indicator.rs a no_core test, so it doesn't fail on non-x86 hosts.
 * Explicitly sets the exception model for wasm, as this is no longer implied by `-wasm-enable-eh`.
Make bit ops traits const

tracking issue: rust-lang#144119

r? `@fee1-dead`
…=Mark-Simulacrum

Cleanup unicode table gen

Fixing clippy warnings and moving to edition 2024.
Add implicit sized bound to trait ascription types

r? `@fmease` or reassign

Thanks for catching this :)

Fixes rust-lang#144135
…r=lqd

Remove pretty print hack for async blocks

I introduced this hack 3 years ago, but it's not needed anymore, probably due to rust-lang#104321.
interpret: fix TypeId pointers being considered data pointers

Fixes rust-lang/miri#4477
r? ``@oli-obk``
@rustbot rustbot added A-CI Area: Our Github Actions CI A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-rustdoc-search Area: Rustdoc's search feature A-testsuite Area: The testsuite used to check the correctness of rustc S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-infra Relevant to the infrastructure team, which will review and decide on the PR/issue. T-libs Relevant to the library team, which will review and decide on the PR/issue. T-rustdoc Relevant to the rustdoc team, which will review and decide on the PR/issue. T-rustdoc-frontend Relevant to the rustdoc-frontend team, which will review and decide on the web UI/UX output. rollup A PR which is a rollup labels Jul 20, 2025
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jhpratt commented Jul 20, 2025

@bors r+ rollup=never p=5

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bors commented Jul 20, 2025

📌 Commit 43f7387 has been approved by jhpratt

It is now in the queue for this repository.

@bors bors added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Jul 20, 2025
@oli-obk oli-obk closed this Jul 20, 2025
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oli-obk commented Jul 20, 2025

#144120 was closed

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I created one at #144204

@jhpratt jhpratt deleted the rollup-vho1a34 branch July 20, 2025 05:24
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A-CI Area: Our Github Actions CI A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-rustdoc-search Area: Rustdoc's search feature A-testsuite Area: The testsuite used to check the correctness of rustc rollup A PR which is a rollup S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-infra Relevant to the infrastructure team, which will review and decide on the PR/issue. T-libs Relevant to the library team, which will review and decide on the PR/issue. T-rustdoc Relevant to the rustdoc team, which will review and decide on the PR/issue. T-rustdoc-frontend Relevant to the rustdoc-frontend team, which will review and decide on the web UI/UX output.
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