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Merge pull request #1908 from sayantn/make-safe
Make some remaining X86 intrinsics safe
2 parents d6ba187 + b73a76f commit e3accfc

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11 files changed

+174
-185
lines changed

11 files changed

+174
-185
lines changed

crates/core_arch/src/x86/adx.rs

Lines changed: 62 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@ unsafe extern "unadjusted" {
1717
#[inline]
1818
#[cfg_attr(test, assert_instr(adc))]
1919
#[stable(feature = "simd_x86_adx", since = "1.33.0")]
20-
pub unsafe fn _addcarry_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
21-
let (a, b) = llvm_addcarry_u32(c_in, a, b);
20+
pub fn _addcarry_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
21+
let (a, b) = unsafe { llvm_addcarry_u32(c_in, a, b) };
2222
*out = b;
2323
a
2424
}
@@ -32,7 +32,7 @@ pub unsafe fn _addcarry_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
3232
#[target_feature(enable = "adx")]
3333
#[cfg_attr(test, assert_instr(adc))]
3434
#[stable(feature = "simd_x86_adx", since = "1.33.0")]
35-
pub unsafe fn _addcarryx_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
35+
pub fn _addcarryx_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
3636
_addcarry_u32(c_in, a, b, out)
3737
}
3838

@@ -44,8 +44,8 @@ pub unsafe fn _addcarryx_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
4444
#[inline]
4545
#[cfg_attr(test, assert_instr(sbb))]
4646
#[stable(feature = "simd_x86_adx", since = "1.33.0")]
47-
pub unsafe fn _subborrow_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
48-
let (a, b) = llvm_subborrow_u32(c_in, a, b);
47+
pub fn _subborrow_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
48+
let (a, b) = unsafe { llvm_subborrow_u32(c_in, a, b) };
4949
*out = b;
5050
a
5151
}
@@ -58,38 +58,36 @@ mod tests {
5858

5959
#[test]
6060
fn test_addcarry_u32() {
61-
unsafe {
62-
let a = u32::MAX;
63-
let mut out = 0;
64-
65-
let r = _addcarry_u32(0, a, 1, &mut out);
66-
assert_eq!(r, 1);
67-
assert_eq!(out, 0);
68-
69-
let r = _addcarry_u32(0, a, 0, &mut out);
70-
assert_eq!(r, 0);
71-
assert_eq!(out, a);
72-
73-
let r = _addcarry_u32(1, a, 1, &mut out);
74-
assert_eq!(r, 1);
75-
assert_eq!(out, 1);
76-
77-
let r = _addcarry_u32(1, a, 0, &mut out);
78-
assert_eq!(r, 1);
79-
assert_eq!(out, 0);
80-
81-
let r = _addcarry_u32(0, 3, 4, &mut out);
82-
assert_eq!(r, 0);
83-
assert_eq!(out, 7);
84-
85-
let r = _addcarry_u32(1, 3, 4, &mut out);
86-
assert_eq!(r, 0);
87-
assert_eq!(out, 8);
88-
}
61+
let a = u32::MAX;
62+
let mut out = 0;
63+
64+
let r = _addcarry_u32(0, a, 1, &mut out);
65+
assert_eq!(r, 1);
66+
assert_eq!(out, 0);
67+
68+
let r = _addcarry_u32(0, a, 0, &mut out);
69+
assert_eq!(r, 0);
70+
assert_eq!(out, a);
71+
72+
let r = _addcarry_u32(1, a, 1, &mut out);
73+
assert_eq!(r, 1);
74+
assert_eq!(out, 1);
75+
76+
let r = _addcarry_u32(1, a, 0, &mut out);
77+
assert_eq!(r, 1);
78+
assert_eq!(out, 0);
79+
80+
let r = _addcarry_u32(0, 3, 4, &mut out);
81+
assert_eq!(r, 0);
82+
assert_eq!(out, 7);
83+
84+
let r = _addcarry_u32(1, 3, 4, &mut out);
85+
assert_eq!(r, 0);
86+
assert_eq!(out, 8);
8987
}
9088

9189
#[simd_test(enable = "adx")]
92-
unsafe fn test_addcarryx_u32() {
90+
fn test_addcarryx_u32() {
9391
let a = u32::MAX;
9492
let mut out = 0;
9593

@@ -119,44 +117,39 @@ mod tests {
119117
}
120118

121119
#[simd_test(enable = "adx")]
122-
unsafe fn test_addcarryx_u32_2() {
123-
unsafe fn add_1_2_3() -> u32 {
124-
let mut out = 0;
125-
_addcarryx_u32(1, 2, 3, &mut out);
126-
out
127-
}
128-
assert_eq!(6, add_1_2_3());
120+
fn test_addcarryx_u32_2() {
121+
let mut out = 0;
122+
_addcarryx_u32(1, 2, 3, &mut out);
123+
assert_eq!(6, out);
129124
}
130125

131126
#[test]
132127
fn test_subborrow_u32() {
133-
unsafe {
134-
let a = u32::MAX;
135-
let mut out = 0;
136-
137-
let r = _subborrow_u32(0, 0, 1, &mut out);
138-
assert_eq!(r, 1);
139-
assert_eq!(out, a);
140-
141-
let r = _subborrow_u32(0, 0, 0, &mut out);
142-
assert_eq!(r, 0);
143-
assert_eq!(out, 0);
144-
145-
let r = _subborrow_u32(1, 0, 1, &mut out);
146-
assert_eq!(r, 1);
147-
assert_eq!(out, a - 1);
148-
149-
let r = _subborrow_u32(1, 0, 0, &mut out);
150-
assert_eq!(r, 1);
151-
assert_eq!(out, a);
152-
153-
let r = _subborrow_u32(0, 7, 3, &mut out);
154-
assert_eq!(r, 0);
155-
assert_eq!(out, 4);
156-
157-
let r = _subborrow_u32(1, 7, 3, &mut out);
158-
assert_eq!(r, 0);
159-
assert_eq!(out, 3);
160-
}
128+
let a = u32::MAX;
129+
let mut out = 0;
130+
131+
let r = _subborrow_u32(0, 0, 1, &mut out);
132+
assert_eq!(r, 1);
133+
assert_eq!(out, a);
134+
135+
let r = _subborrow_u32(0, 0, 0, &mut out);
136+
assert_eq!(r, 0);
137+
assert_eq!(out, 0);
138+
139+
let r = _subborrow_u32(1, 0, 1, &mut out);
140+
assert_eq!(r, 1);
141+
assert_eq!(out, a - 1);
142+
143+
let r = _subborrow_u32(1, 0, 0, &mut out);
144+
assert_eq!(r, 1);
145+
assert_eq!(out, a);
146+
147+
let r = _subborrow_u32(0, 7, 3, &mut out);
148+
assert_eq!(r, 0);
149+
assert_eq!(out, 4);
150+
151+
let r = _subborrow_u32(1, 7, 3, &mut out);
152+
assert_eq!(r, 0);
153+
assert_eq!(out, 3);
161154
}
162155
}

crates/core_arch/src/x86/avx512fp16.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11202,7 +11202,7 @@ pub fn _mm256_reduce_mul_ph(a: __m256h) -> f16 {
1120211202
#[inline]
1120311203
#[target_feature(enable = "avx512fp16")]
1120411204
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11205-
pub unsafe fn _mm512_reduce_mul_ph(a: __m512h) -> f16 {
11205+
pub fn _mm512_reduce_mul_ph(a: __m512h) -> f16 {
1120611206
unsafe {
1120711207
let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
1120811208
let q = simd_shuffle!(

crates/core_arch/src/x86/bswap.rs

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ use stdarch_test::assert_instr;
1010
#[inline]
1111
#[cfg_attr(test, assert_instr(bswap))]
1212
#[stable(feature = "simd_x86", since = "1.27.0")]
13-
pub unsafe fn _bswap(x: i32) -> i32 {
13+
pub fn _bswap(x: i32) -> i32 {
1414
x.swap_bytes()
1515
}
1616

@@ -20,9 +20,7 @@ mod tests {
2020

2121
#[test]
2222
fn test_bswap() {
23-
unsafe {
24-
assert_eq!(_bswap(0x0EADBE0F), 0x0FBEAD0E);
25-
assert_eq!(_bswap(0x00000000), 0x00000000);
26-
}
23+
assert_eq!(_bswap(0x0EADBE0F), 0x0FBEAD0E);
24+
assert_eq!(_bswap(0x00000000), 0x00000000);
2725
}
2826
}

crates/core_arch/src/x86/rdrand.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -26,8 +26,8 @@ use stdarch_test::assert_instr;
2626
#[target_feature(enable = "rdrand")]
2727
#[cfg_attr(test, assert_instr(rdrand))]
2828
#[stable(feature = "simd_x86", since = "1.27.0")]
29-
pub unsafe fn _rdrand16_step(val: &mut u16) -> i32 {
30-
let (v, flag) = x86_rdrand16_step();
29+
pub fn _rdrand16_step(val: &mut u16) -> i32 {
30+
let (v, flag) = unsafe { x86_rdrand16_step() };
3131
*val = v;
3232
flag
3333
}
@@ -40,8 +40,8 @@ pub unsafe fn _rdrand16_step(val: &mut u16) -> i32 {
4040
#[target_feature(enable = "rdrand")]
4141
#[cfg_attr(test, assert_instr(rdrand))]
4242
#[stable(feature = "simd_x86", since = "1.27.0")]
43-
pub unsafe fn _rdrand32_step(val: &mut u32) -> i32 {
44-
let (v, flag) = x86_rdrand32_step();
43+
pub fn _rdrand32_step(val: &mut u32) -> i32 {
44+
let (v, flag) = unsafe { x86_rdrand32_step() };
4545
*val = v;
4646
flag
4747
}
@@ -54,8 +54,8 @@ pub unsafe fn _rdrand32_step(val: &mut u32) -> i32 {
5454
#[target_feature(enable = "rdseed")]
5555
#[cfg_attr(test, assert_instr(rdseed))]
5656
#[stable(feature = "simd_x86", since = "1.27.0")]
57-
pub unsafe fn _rdseed16_step(val: &mut u16) -> i32 {
58-
let (v, flag) = x86_rdseed16_step();
57+
pub fn _rdseed16_step(val: &mut u16) -> i32 {
58+
let (v, flag) = unsafe { x86_rdseed16_step() };
5959
*val = v;
6060
flag
6161
}
@@ -68,8 +68,8 @@ pub unsafe fn _rdseed16_step(val: &mut u16) -> i32 {
6868
#[target_feature(enable = "rdseed")]
6969
#[cfg_attr(test, assert_instr(rdseed))]
7070
#[stable(feature = "simd_x86", since = "1.27.0")]
71-
pub unsafe fn _rdseed32_step(val: &mut u32) -> i32 {
72-
let (v, flag) = x86_rdseed32_step();
71+
pub fn _rdseed32_step(val: &mut u32) -> i32 {
72+
let (v, flag) = unsafe { x86_rdseed32_step() };
7373
*val = v;
7474
flag
7575
}

crates/core_arch/src/x86/sse.rs

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1445,8 +1445,8 @@ pub fn _mm_move_ss(a: __m128, b: __m128) -> __m128 {
14451445
#[target_feature(enable = "sse")]
14461446
#[cfg_attr(test, assert_instr(sfence))]
14471447
#[stable(feature = "simd_x86", since = "1.27.0")]
1448-
pub unsafe fn _mm_sfence() {
1449-
sfence()
1448+
pub fn _mm_sfence() {
1449+
unsafe { sfence() }
14501450
}
14511451

14521452
/// Gets the unsigned 32-bit value of the MXCSR control and status register.
@@ -1887,6 +1887,8 @@ pub const _MM_HINT_ET1: i32 = 6;
18871887
/// * Prefetching may also fail if there are not enough memory-subsystem
18881888
/// resources (e.g., request buffers).
18891889
///
1890+
/// Note: this intrinsic is safe to use even though it takes a raw pointer argument. In general, this
1891+
/// cannot change the behavior of the program, including not trapping on invalid pointers.
18901892
///
18911893
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_prefetch)
18921894
#[inline]
@@ -1897,11 +1899,13 @@ pub const _MM_HINT_ET1: i32 = 6;
18971899
#[cfg_attr(test, assert_instr(prefetchnta, STRATEGY = _MM_HINT_NTA))]
18981900
#[rustc_legacy_const_generics(1)]
18991901
#[stable(feature = "simd_x86", since = "1.27.0")]
1900-
pub unsafe fn _mm_prefetch<const STRATEGY: i32>(p: *const i8) {
1902+
pub fn _mm_prefetch<const STRATEGY: i32>(p: *const i8) {
19011903
static_assert_uimm_bits!(STRATEGY, 3);
19021904
// We use the `llvm.prefetch` intrinsic with `cache type` = 1 (data cache).
19031905
// `locality` and `rw` are based on our `STRATEGY`.
1904-
prefetch(p, (STRATEGY >> 2) & 1, STRATEGY & 3, 1);
1906+
unsafe {
1907+
prefetch(p, (STRATEGY >> 2) & 1, STRATEGY & 3, 1);
1908+
}
19051909
}
19061910

19071911
/// Returns vector of type __m128 with indeterminate elements.with indetermination elements.

crates/core_arch/src/x86/sse2.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,10 @@ use crate::{
1919
#[inline]
2020
#[cfg_attr(all(test, target_feature = "sse2"), assert_instr(pause))]
2121
#[stable(feature = "simd_x86", since = "1.27.0")]
22-
pub unsafe fn _mm_pause() {
22+
pub fn _mm_pause() {
2323
// note: `pause` is guaranteed to be interpreted as a `nop` by CPUs without
2424
// the SSE2 target-feature - therefore it does not require any target features
25-
pause()
25+
unsafe { pause() }
2626
}
2727

2828
/// Invalidates and flushes the cache line that contains `p` from all levels of
@@ -49,8 +49,8 @@ pub unsafe fn _mm_clflush(p: *const u8) {
4949
#[target_feature(enable = "sse2")]
5050
#[cfg_attr(test, assert_instr(lfence))]
5151
#[stable(feature = "simd_x86", since = "1.27.0")]
52-
pub unsafe fn _mm_lfence() {
53-
lfence()
52+
pub fn _mm_lfence() {
53+
unsafe { lfence() }
5454
}
5555

5656
/// Performs a serializing operation on all load-from-memory and store-to-memory
@@ -65,8 +65,8 @@ pub unsafe fn _mm_lfence() {
6565
#[target_feature(enable = "sse2")]
6666
#[cfg_attr(test, assert_instr(mfence))]
6767
#[stable(feature = "simd_x86", since = "1.27.0")]
68-
pub unsafe fn _mm_mfence() {
69-
mfence()
68+
pub fn _mm_mfence() {
69+
unsafe { mfence() }
7070
}
7171

7272
/// Adds packed 8-bit integers in `a` and `b`.
@@ -3149,7 +3149,7 @@ mod tests {
31493149

31503150
#[test]
31513151
fn test_mm_pause() {
3152-
unsafe { _mm_pause() }
3152+
_mm_pause()
31533153
}
31543154

31553155
#[simd_test(enable = "sse2")]

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