FFTcore_inst.v

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// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
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// to the terms and conditions of the Intel Program License 
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// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
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// Generated by Quartus Prime Version 17.1 (Build Build 590 10/25/2017)
// Created on Sat Apr 27 00:10:17 2019

FFTcore FFTcore_inst
(
	.MCLK(MCLK_sig) ,	// input  MCLK_sig
	.sink_real(sink_real_sig) ,	// input [23:0] sink_real_sig
	.sink_imag(sink_imag_sig) ,	// input [23:0] sink_imag_sig
	.sink_valid(sink_valid_sig) ,	// input  sink_valid_sig
	.sink_sop(sink_sop_sig) ,	// input  sink_sop_sig
	.sink_eop(sink_eop_sig) ,	// input  sink_eop_sig
	.reset(reset_sig) ,	// input  reset_sig
	.sink_ready(sink_ready_sig) ,	// output  sink_ready_sig
	.source_error(source_error_sig) ,	// output [1:0] source_error_sig
	.source_valid(source_valid_sig) ,	// output  source_valid_sig
	.source_sop(source_sop_sig) ,	// output  source_sop_sig
	.source_eop(source_eop_sig) ,	// output  source_eop_sig
	.source_real(source_real_sig) ,	// output [23:0] source_real_sig
	.source_imag(source_imag_sig) ,	// output [23:0] source_imag_sig
	.source_exp(source_exp_sig) 	// output [5:0] source_exp_sig
);