We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 75f3b5a commit 73edaf0Copy full SHA for 73edaf0
Makefile
@@ -1,5 +1,3 @@
1
-SBT = sbt
2
-
3
# Generate Verilog code
4
doit:
5
sbt run
0 commit comments