diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index f91220496082bd..b1b03d8b30fa0c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -42,24 +42,19 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = { .name = "ctl_0", .id = CTL_0, .base = 0x1000, .len = 0x94, .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x1200, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x1400, .len = 0x94, .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, .base = 0x1600, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name = "ctl_4", .id = CTL_4, .base = 0x1800, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 8f9a097147c02b..64df4e80ea43de 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -37,24 +37,19 @@ static const struct dpu_ctl_cfg sdm660_ctl[] = { .name = "ctl_0", .id = CTL_0, .base = 0x1000, .len = 0x94, .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x1200, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x1400, .len = 0x94, .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, .base = 0x1600, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name = "ctl_4", .id = CTL_4, .base = 0x1800, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 0ad18bd273ff8c..b409af89991820 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -36,24 +36,19 @@ static const struct dpu_ctl_cfg sdm630_ctl[] = { .name = "ctl_0", .id = CTL_0, .base = 0x1000, .len = 0x94, .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x1200, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x1400, .len = 0x94, .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, .base = 0x1600, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name = "ctl_4", .id = CTL_4, .base = 0x1800, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 0ec6d67c7c70b1..93db1484f60698 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -681,10 +681,11 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done( if (!dpu_encoder_phys_cmd_is_master(phys_enc)) return 0; - if (phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl)) - return dpu_encoder_phys_cmd_wait_for_tx_complete(phys_enc); + if (phys_enc->irq[INTR_IDX_CTL_START] && + !phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl)) + return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); - return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); + return dpu_encoder_phys_cmd_wait_for_tx_complete(phys_enc); } static void dpu_encoder_phys_cmd_handle_post_kickoff( diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index df464f7c05bfa1..69fef034d0df10 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -1097,310 +1097,6 @@ static const struct mdp5_cfg_hw msm8937_config = { .max_clk = 320000000, }; -static const struct mdp5_cfg_hw msm8998_config = { - .name = "msm8998", - .mdp = { - .count = 1, - .caps = MDP_CAP_DSC | - MDP_CAP_CDM | - MDP_CAP_SRC_SPLIT | - 0, - }, - .ctl = { - .count = 5, - .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, - .flush_hw_mask = 0xf7ffffff, - }, - .pipe_vig = { - .count = 4, - .base = { 0x04000, 0x06000, 0x08000, 0x0a000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_CSC | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_rgb = { - .count = 4, - .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_dma = { - .count = 2, /* driver supports max of 2 currently */ - .base = { 0x24000, 0x26000, 0x28000, 0x2a000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_cursor = { - .count = 2, - .base = { 0x34000, 0x36000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - MDP_PIPE_CAP_CURSOR | - 0, - }, - - .lm = { - .count = 6, - .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, - .instances = { - { .id = 0, .pp = 0, .dspp = 0, - .caps = MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id = 1, .pp = 1, .dspp = 1, - .caps = MDP_LM_CAP_DISPLAY, }, - { .id = 2, .pp = 2, .dspp = -1, - .caps = MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id = 3, .pp = -1, .dspp = -1, - .caps = MDP_LM_CAP_WB, }, - { .id = 4, .pp = -1, .dspp = -1, - .caps = MDP_LM_CAP_WB, }, - { .id = 5, .pp = 3, .dspp = -1, - .caps = MDP_LM_CAP_DISPLAY, }, - }, - .nb_stages = 8, - .max_width = 2560, - .max_height = 0xFFFF, - }, - .dspp = { - .count = 2, - .base = { 0x54000, 0x56000 }, - }, - .ad = { - .count = 3, - .base = { 0x78000, 0x78800, 0x79000 }, - }, - .pp = { - .count = 4, - .base = { 0x70000, 0x70800, 0x71000, 0x71800 }, - }, - .cdm = { - .count = 1, - .base = { 0x79200 }, - }, - .dsc = { - .count = 2, - .base = { 0x80000, 0x80400 }, - }, - .intf = { - .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, - .connect = { - [0] = INTF_eDP, - [1] = INTF_DSI, - [2] = INTF_DSI, - [3] = INTF_HDMI, - }, - }, - .max_clk = 412500000, -}; - -static const struct mdp5_cfg_hw sdm630_config = { - .name = "sdm630", - .mdp = { - .count = 1, - .caps = MDP_CAP_CDM | - MDP_CAP_SRC_SPLIT | - 0, - }, - .ctl = { - .count = 5, - .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, - .flush_hw_mask = 0xf4ffffff, - }, - .pipe_vig = { - .count = 1, - .base = { 0x04000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_CSC | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_rgb = { - .count = 4, - .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_dma = { - .count = 2, /* driver supports max of 2 currently */ - .base = { 0x24000, 0x26000, 0x28000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_cursor = { - .count = 1, - .base = { 0x34000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - MDP_PIPE_CAP_CURSOR | - 0, - }, - - .lm = { - .count = 2, - .base = { 0x44000, 0x46000 }, - .instances = { - { .id = 0, .pp = 0, .dspp = 0, - .caps = MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id = 1, .pp = 1, .dspp = -1, - .caps = MDP_LM_CAP_WB, }, - }, - .nb_stages = 8, - .max_width = 2048, - .max_height = 0xFFFF, - }, - .dspp = { - .count = 1, - .base = { 0x54000 }, - }, - .ad = { - .count = 2, - .base = { 0x78000, 0x78800 }, - }, - .pp = { - .count = 3, - .base = { 0x70000, 0x71000, 0x72000 }, - }, - .cdm = { - .count = 1, - .base = { 0x79200 }, - }, - .intf = { - .base = { 0x6a000, 0x6a800 }, - .connect = { - [0] = INTF_DISABLED, - [1] = INTF_DSI, - }, - }, - .max_clk = 412500000, -}; - -static const struct mdp5_cfg_hw sdm660_config = { - .name = "sdm660", - .mdp = { - .count = 1, - .caps = MDP_CAP_DSC | - MDP_CAP_CDM | - MDP_CAP_SRC_SPLIT | - 0, - }, - .ctl = { - .count = 5, - .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, - .flush_hw_mask = 0xf4ffffff, - }, - .pipe_vig = { - .count = 2, - .base = { 0x04000, 0x6000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_CSC | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_rgb = { - .count = 4, - .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_dma = { - .count = 2, /* driver supports max of 2 currently */ - .base = { 0x24000, 0x26000, 0x28000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_cursor = { - .count = 1, - .base = { 0x34000 }, - .caps = MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - MDP_PIPE_CAP_CURSOR | - 0, - }, - - .lm = { - .count = 4, - .base = { 0x44000, 0x45000, 0x46000, 0x49000 }, - .instances = { - { .id = 0, .pp = 0, .dspp = 0, - .caps = MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id = 1, .pp = 1, .dspp = 1, - .caps = MDP_LM_CAP_DISPLAY, }, - { .id = 2, .pp = 2, .dspp = -1, - .caps = MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id = 3, .pp = 3, .dspp = -1, - .caps = MDP_LM_CAP_WB, }, - }, - .nb_stages = 8, - .max_width = 2560, - .max_height = 0xFFFF, - }, - .dspp = { - .count = 2, - .base = { 0x54000, 0x56000 }, - }, - .ad = { - .count = 2, - .base = { 0x78000, 0x78800 }, - }, - .pp = { - .count = 5, - .base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 }, - }, - .cdm = { - .count = 1, - .base = { 0x79200 }, - }, - .dsc = { - .count = 2, - .base = { 0x80000, 0x80400 }, - }, - .intf = { - .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 }, - .connect = { - [0] = INTF_DISABLED, - [1] = INTF_DSI, - [2] = INTF_DSI, - [3] = INTF_HDMI, - }, - }, - .max_clk = 412500000, -}; - static const struct mdp5_cfg_handler cfg_handlers_v1[] = { { .revision = 0, .config = { .hw = &msm8x74v1_config } }, { .revision = 1, .config = { .hw = &msm8x26_config } }, @@ -1416,12 +1112,6 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[] = { { .revision = 16, .config = { .hw = &msm8x53_config } }, }; -static const struct mdp5_cfg_handler cfg_handlers_v3[] = { - { .revision = 0, .config = { .hw = &msm8998_config } }, - { .revision = 2, .config = { .hw = &sdm660_config } }, - { .revision = 3, .config = { .hw = &sdm630_config } }, -}; - const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler) { return cfg_handler->config.hw; @@ -1455,10 +1145,6 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms, cfg_handlers = cfg_handlers_v1; num_handlers = ARRAY_SIZE(cfg_handlers_v1); break; - case 3: - cfg_handlers = cfg_handlers_v3; - num_handlers = ARRAY_SIZE(cfg_handlers_v3); - break; default: DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n", major, minor); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 7e977fec410079..abee7149a9e874 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -960,23 +960,33 @@ static bool prefer_mdp5 = true; MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred"); module_param(prefer_mdp5, bool, 0444); +/* list all platforms that have been migrated from mdp5 to dpu driver */ +static const char *const msm_mdp5_dpu_migrated[] = { + /* there never was qcom,msm8998-mdp5 */ + "qcom,sdm630-mdp5", + "qcom,sdm660-mdp5", + NULL +}; + /* list all platforms supported by both mdp5 and dpu drivers */ static const char *const msm_mdp5_dpu_migration[] = { "qcom,msm8917-mdp5", "qcom,msm8937-mdp5", "qcom,msm8953-mdp5", "qcom,msm8996-mdp5", - "qcom,sdm630-mdp5", - "qcom,sdm660-mdp5", NULL, }; bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver) { - /* If it is not an MDP5 device, do not try MDP5 driver */ + /* If it is not an MDP5 device, use DPU */ if (!of_device_is_compatible(dev->of_node, "qcom,mdp5")) return dpu_driver; + /* If it is no longer supported by MDP5, use DPU */ + if (of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migrated)) + return dpu_driver; + /* If it is not in the migration list, use MDP5 */ if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration)) return !dpu_driver;