capctl.json5

{
  definitions: {
    ports: {
      t_ctrl_awvalid: 1,
      t_ctrl_awready: -1,
      t_ctrl_awaddr: 32,
      t_ctrl_awprot: 3,
      t_ctrl_wvalid: 1,
      t_ctrl_wready: -1,
      t_ctrl_wdata: 32,
      t_ctrl_wstrb: 1,
      t_ctrl_bvalid: -1,
      t_ctrl_bready: 1,
      t_ctrl_bresp: -2,
      t_ctrl_arvalid: 1,
      t_ctrl_arready: -1,
      t_ctrl_araddr: 32,
      t_ctrl_arprot: 3,
      t_ctrl_rvalid: -1,
      t_ctrl_rready: 1,
      t_ctrl_rdata: -32,
      t_ctrl_rresp: -2,
      odata: -6,
      oenable: -6,
      clk: 1,
      reset_n: 1,
    },
    ctrlPortMap: {
      "ACLK"		: 'clk',
      // "ACLKEN"	: '',
      "ARESETn"	: 'reset_n',
      // "AWUSER"	: '',
      // "WUSER"		: '',
      // "BUSER"		: '',
      // "ARUSER"	: '',
      // "RUSER"		: '',
      
      "ARPROT": "t_ctrl_arprot",
      "BREADY": "t_ctrl_bready",
      "BVALID": "t_ctrl_bvalid",
      "BRESP": "t_ctrl_bresp",
      "WREADY": "t_ctrl_wready",
      "RRESP": "t_ctrl_rresp",
      "ARVALID": "t_ctrl_arvalid",
      "ARREADY": "t_ctrl_arready",
      "AWPROT": "t_ctrl_awprot",
      "RREADY": "t_ctrl_rready",
      "WSTRB": "t_ctrl_wstrb",
      "RVALID": "t_ctrl_rvalid",
      "AWADDR": "t_ctrl_awaddr",
      "WVALID": "t_ctrl_wvalid",
      "RDATA": "t_ctrl_rdata",
      "ARADDR": "t_ctrl_araddr",
      "AWREADY": "t_ctrl_awready",
      "WDATA": "t_ctrl_wdata",
      "AWVALID": "t_ctrl_awvalid"
    }
  },
  component: {
    vendor: 'sifive',
    library: 'blocks',
    name: 'capctl',
    version: '0.1.0',
    busInterfaces: [{
        "name": "t_ctrl",
        "interfaceMode": "slave",
        "busType": {
            "version": "r0p0_0", "name": "AXI4Lite", "vendor": "amba.com", "library": "AMBA4"
        },
        "abstractionTypes": [
            {
                "viewRef": "RTLview",
                portMaps: {$ref: '#/definitions/ctrlPortMap'},
            }
        ],
        connectionRequired: true,
        props: {
          write_interleaving_depth: 1,
          // lock_support: false,
          read_reordering_depth: 1,
          write_reordering_depth: 1,
          outstanding_reads: 1, // optional
          outstanding_writes: 1, // optional
          outstanding_transactions: 1 // optional
          }
        }],
        addressSpaces: [{
          name: 'capctrlAddressSpace',
          range: 1024,
          width: 32
        }],
        memoryMaps: [],
        model: {
          views: [{
            name: 'RTLview',
            displayName: 'RTL View',
            description: 'Simple RTL view of a component.',
            envIdentifier: '*Synthesis:',
            componentInstantiationRef: 'VerilogModel'
          }],
          instantiations: [],
          ports: {$ref: '#/definitions/ports'}
        },
        componentGenerators: [],
        fileSets: {
          VerilogFiles: ['capctl.v']
        },
        pSchema: {},
  }
}