diff --git a/VSI/audio/driver/audio_drv.c b/VSI/audio/driver/audio_drv.c index fac7fa3..7791a54 100644 --- a/VSI/audio/driver/audio_drv.c +++ b/VSI/audio/driver/audio_drv.c @@ -34,7 +34,7 @@ static AudioDrv_Event_t CB_Event = NULL; /* Audio Input Interrupt Handler */ void AudioIn_Handler (void) { - AudioIn->IRQ = 0U; /* Clear IRQ */ + AudioIn->IRQ.Clear = 0x00000001U; __ISB(); __DSB(); if (CB_Event != NULL) { @@ -49,7 +49,8 @@ int32_t AudioDrv_Initialize (AudioDrv_Event_t cb_event) { AudioIn->Timer.Control = 0U; AudioIn->DMA.Control = 0U; - AudioIn->IRQ = 0U; + AudioIn->IRQ.Clear = 0x00000001U; + AudioIn->IRQ.Enable = 0x00000001U; AudioIn->CONTROL = 0U; //NVIC_EnableIRQ(AudioIn_IRQn); @@ -72,7 +73,8 @@ int32_t AudioDrv_Uninitialize (void) { AudioIn->Timer.Control = 0U; AudioIn->DMA.Control = 0U; - AudioIn->IRQ = 0U; + AudioIn->IRQ.Clear = 0x00000001U; + AudioIn->IRQ.Enable = 0x00000000U; AudioIn->CONTROL = 0U; Initialized = 0U; @@ -160,6 +162,9 @@ int32_t AudioDrv_Control (uint32_t control) { AudioIn->DMA.Control = 0U; AudioIn->CONTROL = 0U; } else if ((control & AUDIO_DRV_CONTROL_RX_ENABLE) != 0U) { + AudioIn->CONTROL = CONTROL_ENABLE_Msk; + AudioIn->DMA.Control = ARM_VSI_DMA_Direction_P2M | + ARM_VSI_DMA_Enable_Msk; sample_size = AudioIn->CHANNELS * ((AudioIn->SAMPLE_BITS + 7U) / 8U); sample_rate = AudioIn->SAMPLE_RATE; if ((sample_size == 0U) || (sample_rate == 0U)) { @@ -168,10 +173,8 @@ int32_t AudioDrv_Control (uint32_t control) { block_size = AudioIn->DMA.BlockSize; AudioIn->Timer.Interval = (1000000U * (block_size / sample_size)) / sample_rate; } - AudioIn->DMA.Control = ARM_VSI_DMA_Direction_P2M | - ARM_VSI_DMA_Enable_Msk; - AudioIn->CONTROL = CONTROL_ENABLE_Msk; - AudioIn->Timer.Control = ARM_VSI_Timer_Trig_IRQ_Msk | + AudioIn->Timer.Control = ARM_VSI_Timer_Trig_DMA_Msk | + ARM_VSI_Timer_Trig_IRQ_Msk | ARM_VSI_Timer_Periodic_Msk | ARM_VSI_Timer_Run_Msk; } diff --git a/VSI/audio/python/arm_vsi0.py b/VSI/audio/python/arm_vsi0.py index 050d9b2..1b3d6bf 100644 --- a/VSI/audio/python/arm_vsi0.py +++ b/VSI/audio/python/arm_vsi0.py @@ -2,34 +2,30 @@ # Virtual Streaming Interface instance 0 Python script: Audio Input +##@addtogroup arm_vsi_py_audio_in +# @{ +# +##@package arm_vsi0_audio_in +#Documentation for VSI Audio Input module. +# +#More details. + import logging import wave -# Set verbosity level + +## Set verbosity level #verbosity = logging.DEBUG -#verbosity = logging.INFO verbosity = logging.ERROR # [debugging] Verbosity settings level = { 10: "DEBUG", 20: "INFO", 30: "WARNING", 40: "ERROR" } -logging.basicConfig(format='Py: [%(levelname)s]\t%(message)s', level = verbosity) +logging.basicConfig(format='Py: VSI0: [%(levelname)s]\t%(message)s', level = verbosity) logging.info("Verbosity level is set to " + level[verbosity]) -# Data, user registers and IRQ -Data = [0] * 0x2000 # Data buffer -Regs = [0] * 32 # User registers -IRQ = 0 # Interrupt request - -# DMA registers -DMA_Control = 0 -DMA_BlockSize = 0 - -# DMA Control register definitions -DMA_Control_Enable_Msk = 1<<0 -DMA_Control_Direction_Msk = 1<<1 -DMA_Control_Direction_P2M = 0<<1 -DMA_Control_Direction_M2P = 1<<1 +# IRQ registers +IRQ_Status = 0 # Timer registers Timer_Control = 0 @@ -39,8 +35,20 @@ Timer_Control_Run_Msk = 1<<0 Timer_Control_Periodic_Msk = 1<<1 Timer_Control_Trig_IRQ_Msk = 1<<2 +Timer_Control_Trig_DMA_Msk = 1<<3 + +# DMA registers +DMA_Control = 0 + +# DMA Control register definitions +DMA_Control_Enable_Msk = 1<<0 +DMA_Control_Direction_Msk = 1<<1 +DMA_Control_Direction_P2M = 0<<1 +DMA_Control_Direction_M2P = 1<<1 # User registers +Regs = [0] * 64 + CONTROL = 0 # Regs[0] CHANNELS = 0 # Regs[1] SAMPLE_BITS = 0 # Regs[2] @@ -49,43 +57,16 @@ # User CONTROL register definitions CONTROL_ENABLE_Msk = 1<<0 - -# Write CONTROL register -def wrCONTROL(data): - global CONTROL - if ((data ^ CONTROL) & CONTROL_ENABLE_Msk) != 0: - if (data & CONTROL_ENABLE_Msk) != 0: - logging.info("Enable Receiver") - openWAVE('test.wav') - if ((DMA_Control & DMA_Control_Enable_Msk) != 0): - loadAudioFrames(DMA_BlockSize) - else: - logging.info("Disable Receiver") - closeWAVE() - CONTROL = data - -# Write CHANNELS register -def wrCHANNELS(data): - global CHANNELS - CHANNELS = data - logging.info("Number of channels: {}".format(data)) - -# Write SAMPLE_BITS register -def wrSAMPLE_BITS(data): - global SAMPLE_BITS - SAMPLE_BITS = data - logging.info("Sample bits: {}".format(data)) - -# Write SAMPLE_RATE register -def wrSAMPLE_RATE(data): - global SAMPLE_RATE - SAMPLE_RATE = data - logging.info("Sample rate: {}".format(data)) +# Data buffer +Data = bytearray() +# Audio Frames AudioFrames = bytearray() -# Open WAVE file + +## Open WAVE file (store object into global WAVE object) +# @param name name of WAVE file to open def openWAVE(name): global WAVE logging.info("Open WAVE file: {}".format(name)) @@ -95,140 +76,199 @@ def openWAVE(name): logging.info(" Sample rate: {}".format(WAVE.getframerate())) logging.info(" Number of frames: {}".format(WAVE.getnframes())) -# Read WAVE frames +## Read WAVE frames (global WAVE object) into global AudioFrames object +# @param n number of frames to read def readWAVE(n): global WAVE, AudioFrames logging.info("Read WAVE frames") AudioFrames = WAVE.readframes(n) -# Close WAVE file +## Close WAVE file (global WAVE object) def closeWAVE(): global WAVE logging.info("Close WAVE file") WAVE.close() -# Load audio frames into data buffer +## Load audio frames (global AudioFrames object) into global Data buffer +# @param block_size size of block to load (in bytes) def loadAudioFrames(block_size): - global Data + global AudioFrames, Data logging.info("Load audio frames into data buffer") frame_size = CHANNELS * ((SAMPLE_BITS + 7) // 8) frames_max = block_size // frame_size readWAVE(frames_max) - n = len(AudioFrames) - for i in range(n>>2): - Data[i] = ((AudioFrames[(4*i) + 0] << 0) | - (AudioFrames[(4*i) + 1] << 8) | - (AudioFrames[(4*i) + 2] << 16) | - (AudioFrames[(4*i) + 3] << 24)) - for i in range(n>>2, block_size>>2): - Data[i] = 0 + Data = AudioFrames -# Initialize +## Initialize def init(): logging.info("Python function init() called") -# Read/Write data buffer -def rwData(cmd, addr, data): - global Data - logging.info("Python function rwData() called") +## Read interrupt request (the VSI IRQ Status Register) +# @return value value read (32-bit) +def rdIRQ(): + global IRQ_Status + logging.info("Python function rdIRQ() called") - if cmd == "read": - data = Data[addr] - logging.debug("Read at index {}: {}".format(addr, data)) - elif cmd == "write": - Data[addr] = data - logging.debug("Write at index {}: {}".format(addr, data)) - else: - logging.error("Unknown command {}".format(cmd)) + value = IRQ_Status + logging.debug("Read interrupt request: {}".format(value)) - return data + return value -# Read/Write user registers -def rwRegs(cmd, addr, data): - global Regs - logging.info("Python function rwRegs() called") - - if cmd == "read": - data = Regs[addr] - logging.debug("Read at index {}: {}".format(addr, data)) - elif cmd == "write": - if addr == 0: - wrCONTROL(data) - elif addr == 1: - wrCHANNELS(data) - elif addr == 2: - wrSAMPLE_BITS(data) - elif addr == 3: - wrSAMPLE_RATE(data) - Regs[addr] = data - logging.debug("Write at index {}: {}".format(addr, data)) - else: - logging.error("Unknown command {}".format(cmd)) +## Write interrupt request (the VSI IRQ Status Register) +# @param value value to write (32-bit) +# @return value value written (32-bit) +def wrIRQ(value): + global IRQ_Status + logging.info("Python function wrIRQ() called") + + IRQ_Status = value + logging.debug("Write interrupt request: {}".format(value)) + + return value - return data +## Write Timer registers (the VSI Timer Registers) +# @param index Timer register index (zero based) +# @param value value to write (32-bit) +# @return value value written (32-bit) +def wrTimer(index, value): + global Timer_Control, Timer_Interval + logging.info("Python function wrTimer() called") -# Read/Write interrupt request -def rwIRQ(cmd, addr, data): - global IRQ - logging.info("Python function rwIRQ() called") + if index == 0: + Timer_Control = value + logging.debug("Write Timer_Control: {}".format(value)) + elif index == 1: + Timer_Interval = value + logging.debug("Write Timer_Interval: {}".format(value)) - if cmd == "read": - data = IRQ - logging.debug("Read interrupt request: {}".format(data)) - elif cmd == "write": - IRQ = data - logging.debug("Write interrupt request: {}".format(data)) - else: - logging.error("Unknown command {}".format(cmd)) + return value - return data + +## Timer event (called at Timer Overflow) +def timerEvent(): + logging.info("Python function timerEvent() called") -# Write DMA registers -def wrDMA(cmd, addr, data): - global DMA_Control, DMA_BlockSize +## Write DMA registers (the VSI DMA Registers) +# @param index DMA register index (zero based) +# @param value value to write (32-bit) +# @return value value written (32-bit) +def wrDMA(index, value): + global DMA_Control logging.info("Python function wrDMA() called") - if addr == 0: - DMA_Control = data - logging.debug("Write DMA_Control: {}".format(data)) - elif addr == 2: - DMA_BlockSize = data - logging.debug("Write DMA_BlockSize: {}".format(data)) - else: - logging.error("Unknown address {}".format(addr)) + if index == 0: + DMA_Control = value + logging.debug("Write DMA_Control: {}".format(value)) - return data + return value -# Write Timer registers -def wrTimer(cmd, addr, data): - global Timer_Control, Timer_Interval - logging.info("Python function wrTimer() called") +## Read data from peripheral for DMA P2M transfer (VSI DMA) +# @param size size of data to read (in bytes, multiple of 4) +# @return data data read (bytearray) +def rdDataDMA(size): + global Data + logging.info("Python function rdDataDMA() called") + + loadAudioFrames(size) - if addr == 0: - Timer_Control = data - logging.debug("Write Timer_Control: {}".format(data)) - elif addr == 1: - Timer_Interval = data - logging.debug("Write Timer_Interval: {}".format(data)) - else: - logging.error("Unknown address {}".format(addr)) + n = len(Data) + data = bytearray(size) + data[0:n] = Data[0:n] + logging.debug("Read data ({} bytes)".format(size)) return data -# Timer event -def timerEvent(cmd, addr, data): - logging.info("Python function timerEvent() called") +## Write data to peripheral for DMA M2P transfer (VSI DMA) +# @param data data to write (bytearray) +# @param size size of data to write (in bytes, multiple of 4) +def wrDataDMA(data, size): + global Data + logging.info("Python function wrDataDMA() called") - if ((DMA_Control & DMA_Control_Enable_Msk) != 0): - loadAudioFrames(DMA_BlockSize) + Data = data + logging.debug("Write data ({} bytes)".format(size)) - return data + return + + +## Write CONTROL register (user register) +# @param value value to write (32-bit) +def wrCONTROL(value): + global CONTROL + if ((value ^ CONTROL) & CONTROL_ENABLE_Msk) != 0: + if (value & CONTROL_ENABLE_Msk) != 0: + logging.info("Enable Receiver") + openWAVE('test.wav') + else: + logging.info("Disable Receiver") + closeWAVE() + CONTROL = value + +## Write CHANNELS register (user register) +# @param value value to write (32-bit) +def wrCHANNELS(value): + global CHANNELS + CHANNELS = value + logging.info("Number of channels: {}".format(value)) + +## Write SAMPLE_BITS register (user register) +# @param value value to write (32-bit) +def wrSAMPLE_BITS(value): + global SAMPLE_BITS + SAMPLE_BITS = value + logging.info("Sample bits: {}".format(value)) + +## Write SAMPLE_RATE register (user register) +# @param value value to write (32-bit) +def wrSAMPLE_RATE(value): + global SAMPLE_RATE + SAMPLE_RATE = value + logging.info("Sample rate: {}".format(value)) + + +## Read user registers (the VSI User Registers) +# @param index user register index (zero based) +# @return value value read (32-bit) +def rdRegs(index): + global Regs + logging.info("Python function rdRegs() called") + + value = Regs[index] + logging.debug("Read user register at index {}: {}".format(index, value)) + + return value + + +## Write user registers (the VSI User Registers) +# @param index user register index (zero based) +# @param value value to write (32-bit) +# @return value value written (32-bit) +def wrRegs(index, value): + global Regs + logging.info("Python function wrRegs() called") + + if index == 0: + wrCONTROL(value) + elif index == 1: + wrCHANNELS(value) + elif index == 2: + wrSAMPLE_BITS(value) + elif index == 3: + wrSAMPLE_RATE(value) + + Regs[index] = value + logging.debug("Write user register at index {}: {}".format(index, value)) + + return value + + +## @} diff --git a/VSI/include/arm_vsi.h b/VSI/include/arm_vsi.h index 14cfd32..c56e8b4 100644 --- a/VSI/include/arm_vsi.h +++ b/VSI/include/arm_vsi.h @@ -43,21 +43,28 @@ extern "C" { */ typedef struct { - __IOM uint32_t Data[0x2000]; /*!< Offset: 0x0000 (R/W) Data Buffer (32KB) */ - __IOM uint32_t Regs[32]; /*!< Offset: 0x8000 (R/W) User Registers */ struct { - __IOM uint32_t Control; /*!< Offset: 0x8080 (R/W) Timer Control Register */ - __IOM uint32_t Interval; /*!< Offset: 0x8084 (R/W) Timer Interval Value (in microseconds) */ - __IM uint32_t Count; /*!< Offset: 0x8088 (R/ ) Timer Overflow Count */ - } Timer; /*!< Time counter with 1MHz input frequency */ + __IOM uint32_t Enable; /*!< Offset: 0x0000 (R/W) IRQ Enable */ + __OM uint32_t Set; /*!< Offset: 0x0004 (-/W) IRQ Set */ + __OM uint32_t Clear; /*!< Offset: 0x0008 (-/W) IRQ Clear */ + __IM uint32_t Status; /*!< Offset: 0x000C (R/-) IRQ Status */ + } IRQ; /*!< Interrupt Request (IRQ) */ + uint32_t reserved1[60]; struct { - __IOM uint32_t Control; /*!< Offset: 0x808C (R/W) DMA Control */ - __IOM uint32_t Address; /*!< Offset: 0x8090 (R/W) DMA Memory Start Address */ - __IOM uint32_t BlockSize; /*!< Offset: 0x8094 (R/W) DMA Block Size (in bytes) */ - __IOM uint32_t BlockNum; /*!< Offset: 0x8098 (R/W) DMA Number of Blocks (must be 2^n) */ - __IM uint32_t BlockIndex; /*!< Offset: 0x809C (R/ ) DMA Block Index */ - } DMA; /*!< DMA Controller */ - __IOM uint32_t IRQ; /*!< Offset: 0x80A0 (R/W) Interrupt Request */ + __IOM uint32_t Control; /*!< Offset: 0x0100 (R/W) Timer Control */ + __IOM uint32_t Interval; /*!< Offset: 0x0104 (R/W) Timer Interval Value (in microseconds) */ + __IM uint32_t Count; /*!< Offset: 0x0108 (R/-) Timer Overflow Count */ + } Timer; /*!< Time counter with 1MHz input frequency */ + uint32_t reserved2[61]; + struct { + __IOM uint32_t Control; /*!< Offset: 0x0200 (R/W) DMA Control */ + __IOM uint32_t Address; /*!< Offset: 0x0204 (R/W) DMA Memory Start Address */ + __IOM uint32_t BlockSize; /*!< Offset: 0x0208 (R/W) DMA Block Size (in bytes, multiple of 4) */ + __IOM uint32_t BlockNum; /*!< Offset: 0x020C (R/W) DMA Number of Blocks (must be 2^n) */ + __IM uint32_t BlockIndex; /*!< Offset: 0x0210 (R/-) DMA Block Index */ + } DMA; /*!< Direct Memory Access (DMA) Controller */ + uint32_t reserved3[59]; + __IOM uint32_t Regs[64]; /*!< Offset: 0x0300 (R/W) User Registers */ } ARM_VSI_Type; /* VSI Timer Control Definitions for Timer.Control register */ @@ -67,6 +74,8 @@ typedef struct #define ARM_VSI_Timer_Periodic_Msk (1UL << ARM_VSI_Timer_Periodic_Pos) /*!< Timer Control: Periodic Mask */ #define ARM_VSI_Timer_Trig_IRQ_Pos 2U /*!< Timer Control: Trig_IRQ Position */ #define ARM_VSI_Timer_Trig_IRQ_Msk (1UL << ARM_VSI_Timer_Trig_IRQ_Pos) /*!< Timer Control: Trig_IRQ Mask */ +#define ARM_VSI_Timer_Trig_DMA_Pos 3U /*!< Timer Control: Trig_DAM Position */ +#define ARM_VSI_Timer_Trig_DMA_Msk (1UL << ARM_VSI_Timer_Trig_DMA_Pos) /*!< Timer Control: Trig_DMA Mask */ /* VSI DMA Control Definitions for DMA.Control register */ #define ARM_VSI_DMA_Enable_Pos 0U /*!< DMA Control: Enable Position */ @@ -77,22 +86,38 @@ typedef struct #define ARM_VSI_DMA_Direction_M2P (1UL*ARM_VSI_DMA_Direction_Msk) /*!< DMA Control: Direction M2P */ /* Memory mapping of 8 VSI peripherals */ -#define ARM_VSI0_BASE (0x5FF00000UL) /*!< VSI 0 Base Address */ -#define ARM_VSI1_BASE (0x5FF10000UL) /*!< VSI 1 Base Address */ -#define ARM_VSI2_BASE (0x5FF20000UL) /*!< VSI 2 Base Address */ -#define ARM_VSI3_BASE (0x5FF30000UL) /*!< VSI 3 Base Address */ -#define ARM_VSI4_BASE (0x5FF40000UL) /*!< VSI 4 Base Address */ -#define ARM_VSI5_BASE (0x5FF50000UL) /*!< VSI 5 Base Address */ -#define ARM_VSI6_BASE (0x5FF60000UL) /*!< VSI 6 Base Address */ -#define ARM_VSI7_BASE (0x5FF70000UL) /*!< VSI 7 Base Address */ -#define ARM_VSI0 ((ARM_VSI_Type *)ARM_VSI0_BASE) /*!< VSI 0 struct */ -#define ARM_VSI1 ((ARM_VSI_Type *)ARM_VSI1_BASE) /*!< VSI 1 struct */ -#define ARM_VSI2 ((ARM_VSI_Type *)ARM_VSI2_BASE) /*!< VSI 2 struct */ -#define ARM_VSI3 ((ARM_VSI_Type *)ARM_VSI3_BASE) /*!< VSI 3 struct */ -#define ARM_VSI4 ((ARM_VSI_Type *)ARM_VSI4_BASE) /*!< VSI 4 struct */ -#define ARM_VSI5 ((ARM_VSI_Type *)ARM_VSI5_BASE) /*!< VSI 5 struct */ -#define ARM_VSI6 ((ARM_VSI_Type *)ARM_VSI6_BASE) /*!< VSI 6 struct */ -#define ARM_VSI7 ((ARM_VSI_Type *)ARM_VSI7_BASE) /*!< VSI 7 struct */ +#define ARM_VSI0_BASE (0x5FF00000UL) /*!< VSI 0 Base Address */ +#define ARM_VSI1_BASE (0x5FF10000UL) /*!< VSI 1 Base Address */ +#define ARM_VSI2_BASE (0x5FF20000UL) /*!< VSI 2 Base Address */ +#define ARM_VSI3_BASE (0x5FF30000UL) /*!< VSI 3 Base Address */ +#define ARM_VSI4_BASE (0x5FF40000UL) /*!< VSI 4 Base Address */ +#define ARM_VSI5_BASE (0x5FF50000UL) /*!< VSI 5 Base Address */ +#define ARM_VSI6_BASE (0x5FF60000UL) /*!< VSI 6 Base Address */ +#define ARM_VSI7_BASE (0x5FF70000UL) /*!< VSI 7 Base Address */ +#define ARM_VSI0_BASE_NS (0x4FF00000UL) /*!< VSI 0 Base Address (non-secure address space) */ +#define ARM_VSI1_BASE_NS (0x4FF10000UL) /*!< VSI 1 Base Address (non-secure address space) */ +#define ARM_VSI2_BASE_NS (0x4FF20000UL) /*!< VSI 2 Base Address (non-secure address space) */ +#define ARM_VSI3_BASE_NS (0x4FF30000UL) /*!< VSI 3 Base Address (non-secure address space) */ +#define ARM_VSI4_BASE_NS (0x4FF40000UL) /*!< VSI 4 Base Address (non-secure address space) */ +#define ARM_VSI5_BASE_NS (0x4FF50000UL) /*!< VSI 5 Base Address (non-secure address space) */ +#define ARM_VSI6_BASE_NS (0x4FF60000UL) /*!< VSI 6 Base Address (non-secure address space) */ +#define ARM_VSI7_BASE_NS (0x4FF70000UL) /*!< VSI 7 Base Address (non-secure address space) */ +#define ARM_VSI0 ((ARM_VSI_Type *)ARM_VSI0_BASE) /*!< VSI 0 struct */ +#define ARM_VSI1 ((ARM_VSI_Type *)ARM_VSI1_BASE) /*!< VSI 1 struct */ +#define ARM_VSI2 ((ARM_VSI_Type *)ARM_VSI2_BASE) /*!< VSI 2 struct */ +#define ARM_VSI3 ((ARM_VSI_Type *)ARM_VSI3_BASE) /*!< VSI 3 struct */ +#define ARM_VSI4 ((ARM_VSI_Type *)ARM_VSI4_BASE) /*!< VSI 4 struct */ +#define ARM_VSI5 ((ARM_VSI_Type *)ARM_VSI5_BASE) /*!< VSI 5 struct */ +#define ARM_VSI6 ((ARM_VSI_Type *)ARM_VSI6_BASE) /*!< VSI 6 struct */ +#define ARM_VSI7 ((ARM_VSI_Type *)ARM_VSI7_BASE) /*!< VSI 7 struct */ +#define ARM_VSI0_NS ((ARM_VSI_Type *)ARM_VSI0_BASE_NS) /*!< VSI 0 struct (non-secure address space) */ +#define ARM_VSI1_NS ((ARM_VSI_Type *)ARM_VSI1_BASE_NS) /*!< VSI 1 struct (non-secure address space) */ +#define ARM_VSI2_NS ((ARM_VSI_Type *)ARM_VSI2_BASE_NS) /*!< VSI 2 struct (non-secure address space) */ +#define ARM_VSI3_NS ((ARM_VSI_Type *)ARM_VSI3_BASE_NS) /*!< VSI 3 struct (non-secure address space) */ +#define ARM_VSI4_NS ((ARM_VSI_Type *)ARM_VSI4_BASE_NS) /*!< VSI 4 struct (non-secure address space) */ +#define ARM_VSI5_NS ((ARM_VSI_Type *)ARM_VSI5_BASE_NS) /*!< VSI 5 struct (non-secure address space) */ +#define ARM_VSI6_NS ((ARM_VSI_Type *)ARM_VSI6_BASE_NS) /*!< VSI 6 struct (non-secure address space) */ +#define ARM_VSI7_NS ((ARM_VSI_Type *)ARM_VSI7_BASE_NS) /*!< VSI 7 struct (non-secure address space) */ #ifdef __cplusplus