Compile modules with different flags?

[keithZmudzinski]

I'd like to compile my testbench using the -g2012 flag, but not the modules that the testbench is testing.
I'd like to restrict the modules that are getting tested to an older version of verilog, specifically -g2009.
Is this something I can do?

[martinwhitaker]

Not really. What you can do is use the begin_keywords and end_keywords compiler directives to control which keywords are recognised in different sections of your code.

Apart from recognising some additional keywords, AFAICT the only difference at the moment between compiling with -g2009 and -g2012 is the availability of the $countbits system function.

[keithZmudzinski]

Ooooh, thanks for letting me know about those directives, they may be useful 👍

Follow up question:
Let's say that I have a module I want to test. I want to ensure this module only uses basic Verilog, no System Verilog.
In my testbench though, I want to make use of assert, from System Verilog.

One approach to this would be to first compile just the module I want tested with the -g2005 flag. If there are no errors, I then compile both the module to be tested and my testbench with the -g2012 flag. Voila, I've ensured the module to be tested is using the correct version of Verilog, but still let my testbench use the fancy stuff in newer editions.

My question is this: Could there be a difference in behavior between the tested module when it is compiled under the -g2005 flag, vs when it is compiled under the -g2012 flag?
I guess that question could be further boiled down to: Does System Verilog, as far as you know, introduce breaking changes to Verilog, or is System Verilog just a superset of Verilog, and only add functionality?

[martinwhitaker]

As far as I know, the only behavioural difference between Verilog and SystemVerilog is in the scheduling semantics. But if your Verilog design is sensitive to this difference, it is probably also sensitive to the permitted differences between two different simulators (e.g. you have a subtle race condition). In any case, Icarus Verilog only implements the original Verilog scheduling semantics. I am pretty sure that there will be no difference in behaviour if you compile with -g2012 instead of -g2005.

[keithZmudzinski]

Thanks so much! This has really helped me out.

…

On Sun, Aug 1, 2021 at 2:03 AM martinwhitaker ***@***.***> wrote: As far as I know, the only behavioural difference between Verilog and SystemVerilog is in the scheduling semantics. But if your Verilog design is sensitive to this difference, it is probably also sensitive to the permitted differences between two different simulators (e.g. you have a subtle race condition). In any case, Icarus Verilog only implements the original Verilog scheduling semantics. I am pretty sure that there will be no difference in behaviour if you compile with -g2012 instead of -g2005. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#534 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AEC3DC42SZEUXTUMQHE2XFLT2UEWVANCNFSM5BI4WXNA> .