Iverilog as a parser verilog to a graph structure

[fabiosur]

Hi! I have a question for my project I hope you will be able to help me!
I want to generate a graph structure of Verilog netlist. I would like the atomic logic gates as the vertices and all the links between these logic gates as the edges.
First of all, does this kind of project already exist?
If not, I have a problem managing the 'super gates' ( ivl_net_logic_t with a size ivl_logic_width()>1).
How can I get through the graph, I mean how can I reach the ivl_net_logic_t targets from an ivl_net_logic_t source which is a 'super gate'?
In the same way, is there an easier way to manage the Verilog arrays ( ivl_signal_t with ivl_signal_width()>1) than using ivl_lpm_t structure?

[caryr]

I would suggest looking at the verilog-95 target since it parses the data structures and produces Verilog that you are likely familiar with.