Apply clippy suggestions (#347)

Author: Sh3Rm4n

CHANGELOG.md

@@ -28,6 +28,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Added
 
 - Add missing ADC channels ([#337])
+- Add many `#[must_use]` instances ([#347])
 
 ### Fixed
 
@@ -598,6 +599,7 @@ let clocks = rcc
 [filter]: https://defmt.ferrous-systems.com/filtering.html
 
 [#346]: https://github.com/stm32-rs/stm32f3xx-hal/pull/346
+[#347]: https://github.com/stm32-rs/stm32f3xx-hal/pull/347
 [#340]: https://github.com/stm32-rs/stm32f3xx-hal/pull/340
 [#338]: https://github.com/stm32-rs/stm32f3xx-hal/pull/338
 [#337]: https://github.com/stm32-rs/stm32f3xx-hal/pull/337

build.rs

@@ -63,7 +63,8 @@ fn check_device_feature() {
         std::process::exit(1);
     }
 
-    let device_variants: HashSet<String> = DEVICE_VARIANTS.iter().map(|s| s.to_string()).collect();
+    let device_variants: HashSet<String> =
+        DEVICE_VARIANTS.iter().map(|s| (*s).to_string()).collect();
 
     // get all selected features via env variables
     let selected_features: HashSet<String> = env::vars()
@@ -90,7 +91,7 @@ fn check_device_feature() {
         // pretty print all avaliable devices
         for line in device_variants {
             for device in line {
-                eprint!("{} ", device);
+                eprint!("{device} ");
             }
             eprintln!();
         }
@@ -185,24 +186,17 @@ This may be due to incorrect feature configuration in Cargo.toml or stm32f3xx-ha
     writeln!(file, "MEMORY {{").unwrap();
     writeln!(
         file,
-        "    FLASH (rx) : ORIGIN = 0x8000000, LENGTH = {}K",
-        flash
+        "    FLASH (rx) : ORIGIN = 0x8000000, LENGTH = {flash}K"
     )
     .unwrap();
     if ccmram > 0 {
         writeln!(
             file,
-            "    CCMRAM (rwx) : ORIGIN = 0x10000000, LENGTH = {}K",
-            ccmram
+            "    CCMRAM (rwx) : ORIGIN = 0x10000000, LENGTH = {ccmram}K"
         )
         .unwrap();
     }
-    writeln!(
-        file,
-        "    RAM (rwx) : ORIGIN = 0x20000000, LENGTH = {}K",
-        ram
-    )
-    .unwrap();
+    writeln!(file, "    RAM (rwx) : ORIGIN = 0x20000000, LENGTH = {ram}K").unwrap();
     writeln!(file, "}}").unwrap();
     println!("cargo:rustc-link-search={}", out_dir.display());
 }

src/adc.rs

@@ -4,7 +4,7 @@
 //!
 //! Check out [examples/adc.rs].
 //!
-//! It can be built for the STM32F3Discovery running
+//! It can be built for the `STM32F3Discovery` running
 //! `cargo build --example adc --features=stm32f303xc`
 //!
 //! [examples/adc.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.9.1/examples/adc.rs
@@ -97,6 +97,7 @@ pub struct TemperatureSensor<ADC> {
 ///
 /// This peripheral can control different parts, like enabling internal sensors (like temperature sensor)
 /// or enable dual channel mode (which is not supported yet.)
+#[allow(clippy::module_name_repetitions)]
 pub struct CommonAdc<ADC> {
     reg: ADC,
 }
@@ -348,7 +349,7 @@ where
     // TODO(Sh3Rm4n): Check against and integrate to DMA
     #[inline]
     pub fn data_register_address(&self) -> u32 {
-        &self.reg.dr as *const _ as u32
+        core::ptr::addr_of!(self.reg.dr) as u32
     }
 
     /// Manually start a conversion sequence.
@@ -629,8 +630,9 @@ where
     /// Get the current configured DMA mode.
     #[inline]
     pub fn dma_mode(&self) -> config::DmaMode {
-        let cfgr = self.reg.cfgr.read();
         use adc1::cfgr::{DMACFG_A, DMAEN_A};
+
+        let cfgr = self.reg.cfgr.read();
         match (cfgr.dmaen().variant(), cfgr.dmacfg().variant()) {
             (DMAEN_A::Disabled, _) => config::DmaMode::Disabled,
             (DMAEN_A::Enabled, DMACFG_A::OneShot) => config::DmaMode::OneShot,
@@ -872,7 +874,7 @@ where
     /// Set the overrun mode
     #[inline]
     pub fn set_overrun_mode(&mut self, mode: config::OverrunMode) {
-        self.reg.cfgr.modify(|_, w| w.ovrmod().variant(mode.into()))
+        self.reg.cfgr.modify(|_, w| w.ovrmod().variant(mode.into()));
     }
 
     /// Sets the sampling resolution.
@@ -1090,7 +1092,7 @@ where
     /// the end of a single conversion of a "slot" is notfied via [`Event::EndOfConversion`].
     #[inline]
     pub fn set_sequence_length(&mut self, sequence: config::Sequence) {
-        self.reg.sqr1.modify(|_, w| w.l().bits(sequence.into()))
+        self.reg.sqr1.modify(|_, w| w.l().bits(sequence.into()));
     }
 
     // TODO(Sh3Rm4n): Implement, when injection mode is implemented.
@@ -1125,16 +1127,16 @@ where
             Event::EndOfSequence => self.reg.ier.modify(|_, w| w.eosie().bit(enable)),
             Event::Overrun => self.reg.ier.modify(|_, w| w.ovrie().bit(enable)),
             Event::InjectedChannelEndOfConversion => {
-                self.reg.ier.modify(|_, w| w.jeocie().bit(enable))
+                self.reg.ier.modify(|_, w| w.jeocie().bit(enable));
             }
             Event::InjectedChannelEndOfSequence => {
-                self.reg.ier.modify(|_, w| w.jeosie().bit(enable))
+                self.reg.ier.modify(|_, w| w.jeosie().bit(enable));
             }
             Event::AnalogWatchdog1 => self.reg.ier.modify(|_, w| w.awd1ie().bit(enable)),
             Event::AnalogWatchdog2 => self.reg.ier.modify(|_, w| w.awd2ie().bit(enable)),
             Event::AnalogWatchdog3 => self.reg.ier.modify(|_, w| w.awd3ie().bit(enable)),
             Event::InjectedContextQueueOverfow => {
-                self.reg.ier.modify(|_, w| w.jqovfie().bit(enable))
+                self.reg.ier.modify(|_, w| w.jqovfie().bit(enable));
             }
         };
     }
@@ -1266,8 +1268,8 @@ where
         #[cfg(feature = "svd-f373")]
         self.set_scan(config::Scan::Disabled);
 
-        let is_eoc_enabled = self.is_interrupt_configured(Event::EndOfConversion);
-        let is_eos_enabled = self.is_interrupt_configured(Event::EndOfSequence);
+        let is_end_of_conversion_enabled = self.is_interrupt_configured(Event::EndOfConversion);
+        let is_end_of_sequence_enabled = self.is_interrupt_configured(Event::EndOfSequence);
         self.disable_interrupt(Event::EndOfConversion);
         self.disable_interrupt(Event::EndOfSequence);
 
@@ -1297,8 +1299,8 @@ where
         }
         self.set_sequence_length(seq_len);
 
-        self.configure_interrupt(Event::EndOfSequence, is_eos_enabled);
-        self.configure_interrupt(Event::EndOfConversion, is_eoc_enabled);
+        self.configure_interrupt(Event::EndOfSequence, is_end_of_sequence_enabled);
+        self.configure_interrupt(Event::EndOfConversion, is_end_of_conversion_enabled);
 
         #[cfg(feature = "svd-f373")]
         self.set_scan(config::Scan::Disabled);

src/adc/config.rs

@@ -464,7 +464,7 @@ impl Default for OverrunMode {
 /// Each channel can be sampled with a different sample time.
 /// There is always an overhead of 13 ADC clock cycles.
 ///
-/// E.g. For SampleTime::T19C5 the total conversion time (in ADC clock cycles) is
+/// E.g. For `SampleTime::T19C5` the total conversion time (in ADC clock cycles) is
 /// 13 + 19 = 32 ADC Clock Cycles
 ///
 /// # Related functions
@@ -834,12 +834,14 @@ pub struct Config {
 
 impl Config {
     /// Change the resolution
+    #[must_use]
     pub fn resolution(mut self, resolution: Resolution) -> Self {
         self.resolution = resolution;
         self
     }
 
     /// Set the align mode
+    #[must_use]
     pub fn align(mut self, align: DataAlignment) -> Self {
         self.data_alignment = align;
         self
@@ -853,24 +855,28 @@ impl Config {
     }
 
     /// Set the overrun mode
+    #[must_use]
     pub fn overrun_mode(mut self, mode: OverrunMode) -> Self {
         self.overrun = mode;
         self
     }
 
     /// Set the conversion mode
+    #[must_use]
     pub fn conversion_mode(mut self, mode: ConversionMode) -> Self {
         self.conversion = mode;
         self
     }
 
     /// Enable external trigger and the trigger source
+    #[must_use]
     pub fn external_trigger(mut self, trigger: Option<ExternalTrigger>) -> Self {
         self.external_trigger = trigger;
         self
     }
 
     /// Enable DMA and the operation mode, in which DMA will transfer data from the ADC peripheral.
+    #[must_use]
     pub fn dma_mode(mut self, dma: DmaMode) -> Self {
         self.dma = dma;
         self

src/dac.rs

@@ -32,6 +32,6 @@ impl Dac {
             unsafe {
                 w.dacc1dhr().bits(data)
             }
-        })
+        });
     }
 }

src/delay.rs

@@ -16,7 +16,7 @@ use crate::rcc::Clocks;
 use crate::time::duration::{Microseconds, Milliseconds};
 use crate::time::fixed_point::FixedPoint;
 
-/// System timer (SysTick) as a delay provider
+/// System timer (`SysTick`) as a delay provider
 pub struct Delay {
     clocks: Clocks,
     syst: SYST,
@@ -39,7 +39,7 @@ impl fmt::Debug for Delay {
 }
 
 impl Delay {
-    /// Configures the system timer (SysTick) as a delay provider
+    /// Configures the system timer (`SysTick`) as a delay provider
     ///
     /// # Limitations
     ///
@@ -49,6 +49,7 @@ impl Delay {
     ///
     /// For accuracy purposes and because this is a blocking, busy-waiting function,
     /// if delays in the second to minute range are needed, use timers instead.
+    #[must_use]
     pub fn new(mut syst: SYST, clocks: Clocks) -> Self {
         syst.set_clock_source(SystClkSource::Core);
 
@@ -68,7 +69,8 @@ impl Delay {
         &mut self.syst
     }
 
-    /// Releases the system timer (SysTick) resource
+    /// Releases the system timer (`SysTick`) resource
+    #[must_use]
     pub fn free(self) -> SYST {
         self.syst
     }
@@ -131,13 +133,13 @@ impl DelayUs<u32> for Delay {
 
 impl DelayUs<u16> for Delay {
     fn delay_us(&mut self, us: u16) {
-        self.delay_us(u32::from(us))
+        self.delay_us(u32::from(us));
     }
 }
 
 impl DelayUs<u8> for Delay {
     fn delay_us(&mut self, us: u8) {
-        self.delay_us(u32::from(us))
+        self.delay_us(u32::from(us));
     }
 }
 

src/dma.rs

@@ -28,6 +28,7 @@ use core::{
 use enumset::EnumSetType;
 
 /// Extension trait to split a DMA peripheral into independent channels
+#[allow(clippy::module_name_repetitions)]
 pub trait DmaExt {
     /// The type to split the DMA into
     type Channels;
@@ -134,12 +135,20 @@ impl<B, C: Channel, T: Target> Transfer<B, C, T> {
     }
 
     /// Is this transfer complete?
+    ///
+    /// # Panics
+    ///
+    /// Panics if no transfer is ongoing.
     pub fn is_complete(&self) -> bool {
         let inner = crate::unwrap!(self.inner.as_ref());
         inner.channel.is_event_triggered(Event::TransferComplete)
     }
 
     /// Stop this transfer and return ownership over its parts
+    ///
+    /// # Panics
+    ///
+    /// Panics no transfer is ongoing.
     pub fn stop(mut self) -> (B, C, T) {
         let mut inner = crate::unwrap!(self.inner.take());
         inner.stop();
@@ -349,7 +358,7 @@ pub trait Channel: private::Channel {
     ///
     /// Panics if the word size is not one of 8, 16, or 32 bits.
     fn set_word_size<W>(&mut self) {
-        use cr::PSIZE_A::*;
+        use cr::PSIZE_A::{Bits16, Bits32, Bits8};
 
         let psize = match mem::size_of::<W>() {
             1 => Bits8,

src/flash.rs

@@ -7,6 +7,7 @@ use crate::pac::{flash, FLASH};
 impl crate::private::Sealed for FLASH {}
 
 /// Extension trait to constrain the [`FLASH`] peripheral
+#[allow(clippy::module_name_repetitions)]
 pub trait FlashExt: crate::private::Sealed {
     /// Constrains the [`FLASH`] peripheral.
     ///
@@ -38,6 +39,7 @@ pub struct ACR {
 }
 
 impl ACR {
+    #[allow(clippy::unused_self)]
     pub(crate) fn acr(&mut self) -> &flash::ACR {
         // SAFETY: This proxy grants exclusive access to this register
         unsafe { &(*FLASH::ptr()).acr }