Skip to content

Commit 269401c

Browse files
authored
Merge pull request #788 from stm32-rs/spi-dr
update to staging 0.16.1
2 parents eca5943 + 1864d6b commit 269401c

File tree

2 files changed

+21
-11
lines changed

2 files changed

+21
-11
lines changed

Cargo.toml

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,14 +58,13 @@ atomic-polyfill = { version = "1.0.3", optional = true }
5858

5959
enumflags2 = "0.7.8"
6060
embedded-storage = "0.3"
61-
vcell = "0.1.3"
6261
document-features = "0.2"
6362

6463
micromath = { version = "2.1.0", optional = true }
6564

6665
[dependencies.stm32f4]
6766
package = "stm32f4-staging"
68-
version = "0.16.0"
67+
version = "0.16.1"
6968
features = ["defmt", "atomics"]
7069

7170
[dependencies.time]

src/spi.rs

Lines changed: 20 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ pub type NoMosi = NoPin;
6767
#[enumflags2::bitflags]
6868
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
6969
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
70-
#[repr(u32)]
70+
#[repr(u16)]
7171
pub enum Event {
7272
/// An error occurred.
7373
///
@@ -90,7 +90,7 @@ pub enum Event {
9090
#[enumflags2::bitflags]
9191
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9292
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
93-
#[repr(u32)]
93+
#[repr(u16)]
9494
pub enum Flag {
9595
/// Receive buffer not empty
9696
RxNotEmpty = 1 << 0,
@@ -127,14 +127,30 @@ pub const TransferModeBidi: bool = true;
127127

128128
pub trait FrameSize: Copy + Default {
129129
const DFF: bool;
130+
#[doc(hidden)]
131+
fn read_data(spi: &spi1::RegisterBlock) -> Self;
132+
#[doc(hidden)]
133+
fn write_data(self, spi: &spi1::RegisterBlock);
130134
}
131135

132136
impl FrameSize for u8 {
133137
const DFF: bool = false;
138+
fn read_data(spi: &spi1::RegisterBlock) -> Self {
139+
spi.dr8().read().dr().bits()
140+
}
141+
fn write_data(self, spi: &spi1::RegisterBlock) {
142+
spi.dr8().write(|w| w.dr().set(self))
143+
}
134144
}
135145

136146
impl FrameSize for u16 {
137147
const DFF: bool = true;
148+
fn read_data(spi: &spi1::RegisterBlock) -> Self {
149+
spi.dr().read().dr().bits()
150+
}
151+
fn write_data(self, spi: &spi1::RegisterBlock) {
152+
spi.dr().write(|w| w.dr().set(self))
153+
}
138154
}
139155

140156
/// The bit format to send the data in
@@ -747,16 +763,11 @@ impl<SPI: Instance> Inner<SPI> {
747763
}
748764

749765
fn read_data_reg<W: FrameSize>(&mut self) -> W {
750-
// NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
751-
// reading a half-word)
752-
unsafe { (*(self.spi.dr() as *const pac::spi1::DR).cast::<vcell::VolatileCell<W>>()).get() }
766+
W::read_data(&self.spi)
753767
}
754768

755769
fn write_data_reg<W: FrameSize>(&mut self, data: W) {
756-
// NOTE(write_volatile) see note above
757-
unsafe {
758-
(*(self.spi.dr() as *const pac::spi1::DR).cast::<vcell::VolatileCell<W>>()).set(data)
759-
}
770+
data.write_data(&self.spi)
760771
}
761772

762773
#[inline(always)]

0 commit comments

Comments
 (0)