From 6e1dff393efaef60319ad39308f4bf917c378e6d Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Sun, 19 Mar 2023 13:00:37 -0700 Subject: [PATCH 01/10] Add the G0B1 feature --- .vscode/settings.json | 4 ++-- Cargo.toml | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.vscode/settings.json b/.vscode/settings.json index 6b17def..ba27f95 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -3,6 +3,6 @@ "rust-analyzer.cargo.target": "thumbv6m-none-eabi", "rust-analyzer.cargo.features": [ "rt", - "stm32g071" + "stm32g0b1" ] -} +} \ No newline at end of file diff --git a/Cargo.toml b/Cargo.toml index 4b9654c..393f0b5 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -21,7 +21,7 @@ nb = "1.0.0" fugit = "0.3.5" [dependencies.stm32g0] -version = "0.14.0" +version = "0.15.0" features = ["rt"] [dependencies.bare-metal] @@ -41,7 +41,7 @@ cortex-m-rtic = "1.0.0" cortex-m-semihosting = "0.3.5" embedded-graphics = "0.5" embedded-sdmmc = "0.2.1" -infrared = "0.11.0" +infrared = "0.11.0" panic-halt = "0.2.0" panic-semihosting = "0.5.3" smart-leds = "0.3.0" @@ -58,6 +58,7 @@ stm32g031 = ["stm32g0/stm32g031", "stm32g0x1", "device-selected"] stm32g041 = ["stm32g0/stm32g041", "stm32g0x1", "device-selected"] stm32g071 = ["stm32g0/stm32g071", "stm32g0x1", "device-selected"] stm32g081 = ["stm32g0/stm32g081", "stm32g0x1", "device-selected"] +stm32g0b1 = ["stm32g0/stm32g0b1", "stm32g0x1", "device-selected"] stm32g0x0 = [] stm32g0x1 = [] From b58f413ef03813054540358c2b7b985f9c9934e7 Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Sun, 19 Mar 2023 13:01:35 -0700 Subject: [PATCH 02/10] Add feature-gate to DMA Channel trait for dual-channel deivces --- src/dma.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/dma.rs b/src/dma.rs index 7c29812..4649ba7 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -90,8 +90,12 @@ mod private { /// Channel methods private to this module pub trait Channel { + // FIXME B1 and C1 have two DMA channels, defaulting to CH1 for now /// Return the register block for this channel + #[cfg(not(feature = "stm32g0b1"))] fn ch(&self) -> &stm32::dma::CH; + #[cfg(feature = "stm32g0b1")] + fn ch(&self) -> &stm32::dma1::CH; } } From 76286c43bc43c53fc03bf34384ebce51959a1788 Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Sun, 19 Mar 2023 13:01:56 -0700 Subject: [PATCH 03/10] Add the new DMAMUX entries --- src/dmamux.rs | 122 +++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 102 insertions(+), 20 deletions(-) diff --git a/src/dmamux.rs b/src/dmamux.rs index d129f7a..78666e7 100644 --- a/src/dmamux.rs +++ b/src/dmamux.rs @@ -66,9 +66,19 @@ pub enum DmaMuxIndex { TIM3_CH4 = 35, TIM3_TRIG = 36, TIM3_UP = 37, - #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" + ))] TIM6_UP = 38, - #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" + ))] TIM7_UP = 39, TIM15_CH1 = 40, TIM15_CH2 = 41, @@ -85,23 +95,80 @@ pub enum DmaMuxIndex { USART1_TX = 51, USART2_RX = 52, USART2_TX = 53, - #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" + ))] USART3_RX = 54, - #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" + ))] USART3_TX = 55, - #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" + ))] USART4_RX = 56, - #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" + ))] USART4_TX = 57, - #[cfg(any(feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] UCPD1_RX = 58, - #[cfg(any(feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] UCPD1_TX = 59, - #[cfg(any(feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] UCPD2_RX = 60, - #[cfg(any(feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] UCPD2_TX = 61, + + #[cfg(feature = "stm32g0b1")] + I2C3_RX = 62, + #[cfg(feature = "stm32g0b1")] + I2C3_TX = 63, + + #[cfg(feature = "stm32g0b1")] + LPUART2_RX = 64, + #[cfg(feature = "stm32g0b1")] + LPUART2_TX = 65, + + #[cfg(feature = "stm32g0b1")] + SPI3_RX = 66, + #[cfg(feature = "stm32g0b1")] + SPI3_TX = 67, + + #[cfg(feature = "stm32g0b1")] + TIM4_CH1 = 68, + #[cfg(feature = "stm32g0b1")] + TIM4_CH2 = 69, + #[cfg(feature = "stm32g0b1")] + TIM4_CH3 = 70, + #[cfg(feature = "stm32g0b1")] + TIM4_CH4 = 71, + #[cfg(feature = "stm32g0b1")] + TIM4_TRIG = 72, + #[cfg(feature = "stm32g0b1")] + TIM4_UP = 73, + + #[cfg(feature = "stm32g0b1")] + USART5_RX = 74, + #[cfg(feature = "stm32g0b1")] + USART5_TX = 75, + #[cfg(feature = "stm32g0b1")] + USART6_RX = 76, + #[cfg(feature = "stm32g0b1")] + USART6_TX = 77, } impl DmaMuxIndex { @@ -182,16 +249,21 @@ macro_rules! dma_mux { } } -#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" +))] dma_mux!( channels: { - C0: (ch0, dmamux_c0cr), - C1: (ch1, dmamux_c1cr), - C2: (ch2, dmamux_c2cr), - C3: (ch3, dmamux_c3cr), - C4: (ch4, dmamux_c4cr), - C5: (ch5, dmamux_c5cr), - C6: (ch6, dmamux_c6cr), + C0: (ch0, c0cr), + C1: (ch1, c1cr), + C2: (ch2, c2cr), + C3: (ch3, c3cr), + C4: (ch4, c4cr), + C5: (ch5, c5cr), + C6: (ch6, c6cr), }, ); @@ -216,9 +288,19 @@ impl DmaMuxExt for DMAMUX { ch2: C2 { _0: () }, ch3: C3 { _0: () }, ch4: C4 { _0: () }, - #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" + ))] ch5: C5 { _0: () }, - #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" + ))] ch6: C6 { _0: () }, } } From bb4811eed51954e2f8808b9d9be2ea748b335383 Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Sun, 19 Mar 2023 13:02:35 -0700 Subject: [PATCH 04/10] Add G0B1 features in EXTI --- src/exti.rs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/exti.rs b/src/exti.rs index 83cbb6f..d15177b 100644 --- a/src/exti.rs +++ b/src/exti.rs @@ -22,24 +22,24 @@ pub enum Event { GPIO14 = 14, GPIO15 = 15, PVD = 16, - #[cfg(any(feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] COMP1 = 17, - #[cfg(any(feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] COMP2 = 18, RTC = 19, TAMP = 21, I2C1 = 23, USART1 = 25, USART2 = 26, - #[cfg(any(feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] CEC = 27, LPUART1 = 28, LPTIM1 = 29, LPTIM2 = 30, LSE_CSS = 31, - #[cfg(any(feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] UCPD1 = 32, - #[cfg(any(feature = "stm32g071", feature = "stm32g081"))] + #[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] UCPD2 = 33, } From 9cbc27b8d3d49bdd6a0f356d903ad511da3ef02d Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Sun, 19 Mar 2023 13:02:59 -0700 Subject: [PATCH 05/10] Add the remaining address families and GPIOE --- src/gpio.rs | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/gpio.rs b/src/gpio.rs index c77dc65..15ce2cf 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -170,6 +170,9 @@ pub enum SignalEdge { All, } +// Confusingly, RM0444 7.2 states "at most 8 AFs possible per I/O" but +// the datasheet for the STM32G0B1 clearly lists AF8 to AF15 + #[allow(dead_code)] pub(crate) enum AltFunction { AF0 = 0, @@ -180,6 +183,14 @@ pub(crate) enum AltFunction { AF5 = 5, AF6 = 6, AF7 = 7, + AF8 = 8, + AF9 = 9, + AF10 = 10, + AF11 = 11, + AF12 = 12, + AF13 = 13, + AF14 = 14, + AF15 = 15, } macro_rules! gpio { @@ -715,6 +726,25 @@ gpio!(GPIOD, gpiod, PD, 3, [ PD15: (pd15, 15), ]); +gpio!(GPIOE, gpioe, PE, 4, [ + PE0: (pe0, 0), + PE1: (pe1, 1), + PE2: (pe2, 2), + PE3: (pe3, 3), + PE4: (pe4, 4), + PE5: (pe5, 5), + PE6: (pe6, 6), + PE7: (pe7, 7), + PE8: (pe8, 8), + PE9: (pe9, 9), + PE10: (pe10, 10), + PE11: (pe11, 11), + PE12: (pe12, 12), + PE13: (pe13, 13), + PE14: (pe14, 14), + PE15: (pe15, 15), +]); + gpio!(GPIOF, gpiof, PF, 5, [ PF0: (pf0, 0), PF1: (pf1, 1), From 3034bdc6a7c8739a785d108a7a8a5e671c3436ca Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Sun, 19 Mar 2023 13:03:48 -0700 Subject: [PATCH 06/10] Feature-gate selection of PowerMode register --- src/power.rs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/power.rs b/src/power.rs index 9dcb32b..e440a2c 100644 --- a/src/power.rs +++ b/src/power.rs @@ -118,7 +118,10 @@ impl Power { while !self.rb.sr2.read().reglpf().bit_is_clear() {} } PowerMode::LowPower(sm) => { + #[cfg(not(feature = "stm32g0b1"))] self.rb.cr3.modify(|_, w| w.ulpen().clear_bit()); + #[cfg(feature = "stm32g0b1")] + self.rb.cr3.modify(|_, w| w.enb_ulp().clear_bit()); self.rb .cr1 .modify(|_, w| unsafe { w.lpr().set_bit().lpms().bits(sm as u8) }); @@ -127,7 +130,10 @@ impl Power { {} } PowerMode::UltraLowPower(sm) => { + #[cfg(not(feature = "stm32g0b1"))] self.rb.cr3.modify(|_, w| w.ulpen().set_bit()); + #[cfg(feature = "stm32g0b1")] + self.rb.cr3.modify(|_, w| w.enb_ulp().set_bit()); self.rb .cr1 .modify(|_, w| unsafe { w.lpr().set_bit().lpms().bits(sm as u8) }); From 603da46cae5b85d2f5aacc4a4a58008e087d9e6d Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Sun, 19 Mar 2023 13:04:13 -0700 Subject: [PATCH 07/10] Start work on SPI --- src/spi.rs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/spi.rs b/src/spi.rs index bab5130..998321d 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -186,7 +186,7 @@ macro_rules! spi { .set_bit() .rxonly() .clear_bit() - .dff() + .crcl() .clear_bit() .bidimode() .clear_bit() @@ -279,6 +279,8 @@ macro_rules! spi { } } +// TODO Add Port E mappings for SP1 on stm32g0b1 + spi!( SPI1, spi1, @@ -332,3 +334,5 @@ spi!( (PD4, AltFunction::AF1), ], ); + +// TODO - Implement SPI3 on STM32G0B1 utilizing the extended alternate functions (AF9) From f2038902ba4e6d363a0c1cabe3f1ab647d38a399 Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Sun, 19 Mar 2023 13:04:54 -0700 Subject: [PATCH 08/10] Add more feature-gates to RCC clock enables for additional devices in G0B1 --- src/rcc/enable.rs | 49 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 5 deletions(-) diff --git a/src/rcc/enable.rs b/src/rcc/enable.rs index cfe9a7f..3699405 100644 --- a/src/rcc/enable.rs +++ b/src/rcc/enable.rs @@ -103,7 +103,6 @@ macro_rules! bus { bus! { CRC => (AHB, crcen, crcsmen, crcrst), // 12 FLASH => (AHB, flashen, flashsmen, flashrst), // 8 - DMA => (AHB, dmaen, dmasmen, dmarst), // 0 DBG => (APB1, dbgen, dbgsmen, dbgrst), // 27 I2C1 => (APB1, i2c1en, i2c1smen, i2c1rst), // 21 @@ -122,7 +121,11 @@ bus! { TIM16 => (APB2, tim16en, tim16smen, tim16rst), // 17 TIM17 => (APB2, tim17en, tim17smen, tim17rst), // 18 USART1 => (APB2, usart1en, usart1smen, usart1rst), // 14 +} +#[cfg(not(feature = "stm32g0b1"))] +bus! { + DMA => (AHB, dmaen, dmasmen, dmarst), // 0 GPIOA => (IOP, iopaen, iopasmen, ioparst), // 0 GPIOB => (IOP, iopben, iopbsmen, iopbrst), // 1 GPIOC => (IOP, iopcen, iopcsmen, iopcrst), // 2 @@ -130,7 +133,29 @@ bus! { GPIOF => (IOP, iopfen, iopfsmen, iopfrst), // 5 } -#[cfg(any(feature = "stm32g030", feature = "stm32g031", feature = "stm32g041"))] +#[cfg(feature = "stm32g0b1")] +bus! { + DMA1 => (AHB, dma1en, dma1smen, dma1rst), // 0 + DMA2 => (AHB, dma2en, dma2smen, dma2rst), // 1 + + GPIOA => (IOP, gpioaen, gpioasmen, gpioarst), // 0 + GPIOB => (IOP, gpioben, gpiobsmen, gpiobrst), // 1 + GPIOC => (IOP, gpiocen, gpiocsmen, gpiocrst), // 2 + GPIOD => (IOP, gpioden, gpiodsmen, gpiodrst), // 3 + GPIOE => (IOP, gpioeen, gpioesmen, gpioerst) , // 4 + GPIOF => (IOP, gpiofen, gpiofsmen, gpiofrst), // 5 + + LPUART1 => (APB1, lpuart1en, lpuart1smen, lpuart1rst), // 20 + LPUART2 => (APB1, lpuart2en, lpuart2smen, lpuart2rst), // 7 + USART5 => (APB1, usart5en, usart5smen, usart5rst), // 8 + USART6 => (APB1, usart6en, usart6smen, usart6rst), // 9 + + SPI3 => (APB1, spi3en, spi3smen, spi3rst), // 15 + + I2C3 => (APB1, i2c3en, i2c3smen, i2c3rst), // 23 +} + +#[cfg(any(feature = "stm32g030", feature = "stm32g031", feature = "stm32g041",))] bus! { SYSCFG => (APB2, syscfgen, syscfgsmen, syscfgrst), // 0 } @@ -141,7 +166,7 @@ bus! { RNG => (AHB, rngen, rngsmen, rngrst), // 18 } -#[cfg(any(feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] bus! { HDMI_CEC => (APB1, cecen, cecsmen, cecrst), // 24 DAC => (APB1, dac1en, dac1smen, dac1rst), // 29 @@ -153,11 +178,25 @@ bus! { bus! { LPTIM1 => (APB1, lptim1en, lptim1smen, lptim1rst), // 31 LPTIM2 => (APB1, lptim2en, lptim2smen, lptim2rst), // 30 - LPUART => (APB1, lpuart1en, lpuart1smen, lpuart1rst), // 20 TIM2 => (APB1, tim2en, tim2smen, tim2rst), // 0 } -#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any( + feature = "stm32g031", + feature = "stm32g041", + feature = "stm32g071", + feature = "stm32g081" +))] +bus! { + LPUART => (APB1, lpuarten, lpuartsmen, lpuartrst), // 20 +} + +#[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" +))] bus! { TIM6 => (APB1, tim6en, tim6smen, tim6rst), // 4 TIM7 => (APB1, tim7en, tim7smen, tim7rst), // 5 From 1d755d556706d718c8d458441d3a0adf0e09d80e Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Sun, 19 Mar 2023 13:05:25 -0700 Subject: [PATCH 09/10] Add G0B1 to several import and includes --- src/analog/mod.rs | 4 ++-- src/lib.rs | 5 ++++- src/prelude.rs | 10 +++++----- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/analog/mod.rs b/src/analog/mod.rs index a6088b3..59c4035 100644 --- a/src/analog/mod.rs +++ b/src/analog/mod.rs @@ -1,5 +1,5 @@ pub mod adc; -#[cfg(any(feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] pub mod comparator; -#[cfg(any(feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] pub mod dac; diff --git a/src/lib.rs b/src/lib.rs index 9e6f157..d2349c7 100755 --- a/src/lib.rs +++ b/src/lib.rs @@ -3,7 +3,7 @@ #[cfg(not(feature = "device-selected"))] compile_error!( - "This crate requires one of the following features enabled: stm32g030, stm32g070, stm32g031, stm32g041, stm32g071, stm32g081" + "This crate requires one of the following features enabled: stm32g030, stm32g070, stm32g031, stm32g041, stm32g071, stm32g081, stm32g0b1" ); extern crate bare_metal; @@ -37,6 +37,9 @@ pub use stm32g0::stm32g081 as stm32; #[cfg(feature = "stm32g070")] pub use stm32g0::stm32g070 as stm32; +#[cfg(feature = "stm32g0b1")] +pub use stm32g0::stm32g0b1 as stm32; + #[cfg(feature = "rt")] pub use crate::stm32::interrupt; diff --git a/src/prelude.rs b/src/prelude.rs index c5980d9..6e5af78 100644 --- a/src/prelude.rs +++ b/src/prelude.rs @@ -5,15 +5,15 @@ pub use hal::watchdog::Watchdog as _; pub use hal::watchdog::WatchdogEnable as _; pub use crate::analog::adc::AdcExt as _; -#[cfg(any(feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] pub use crate::analog::comparator::ComparatorExt as _; -#[cfg(any(feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] pub use crate::analog::comparator::ComparatorSplit as _; -#[cfg(any(feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] pub use crate::analog::comparator::WindowComparatorExt as _; -#[cfg(any(feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] pub use crate::analog::dac::DacExt as _; -#[cfg(any(feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any(feature = "stm32g071", feature = "stm32g081", feature = "stm32g0b1"))] pub use crate::analog::dac::DacOut as _; pub use crate::crc::CrcExt as _; pub use crate::timer::delay::DelayExt as _; From d2268cc3a0b6495144a76822dac8e1d3916df1dc Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Sun, 19 Mar 2023 13:06:56 -0700 Subject: [PATCH 10/10] Started new pins and devices for G0B1 --- src/serial/usart.rs | 149 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 142 insertions(+), 7 deletions(-) diff --git a/src/serial/usart.rs b/src/serial/usart.rs index 10ad4e4..24e1fcd 100644 --- a/src/serial/usart.rs +++ b/src/serial/usart.rs @@ -204,6 +204,10 @@ where } } +// NOTE: There is some added complexity here for G0x1 devices where CR1 and ISR +// both have FIFO enabled/disabled variants. Worst still, the LPUARTs have a different +// name for that field + macro_rules! uart_shared { ($USARTX:ident, $dmamux_rx:ident, $dmamux_tx:ident, tx: [ $(($PTX:ident, $TAF:expr),)+ ], @@ -734,6 +738,25 @@ macro_rules! uart_full { }; } +#[cfg(not(feature = "stm32g0b1"))] +uart_shared!(USART1, USART1_RX, USART1_TX, + tx: [ + (PA9, AltFunction::AF1), + (PB6, AltFunction::AF0), + (PC4, AltFunction::AF1), + ], + rx: [ + (PA10, AltFunction::AF1), + (PB7, AltFunction::AF0), + (PC5, AltFunction::AF1), + ], + de: [ + (PA12, AltFunction::AF1), + (PB3, AltFunction::AF4), + ] +); + +#[cfg(feature = "stm32g0b1")] uart_shared!(USART1, USART1_RX, USART1_TX, tx: [ (PA9, AltFunction::AF1), @@ -768,7 +791,12 @@ uart_shared!(USART2, USART2_RX, USART2_TX, ] ); -#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" +))] uart_shared!(USART3, USART3_RX, USART3_TX, tx: [ (PA5, AltFunction::AF4), @@ -796,7 +824,14 @@ uart_shared!(USART3, USART3_RX, USART3_TX, ] ); -#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] +// TODO Add Port E pins for 0b1 +#[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g081", + feature = "stm32g0b1", +))] uart_shared!(USART4, USART4_RX, USART4_TX, tx: [ (PA0, AltFunction::AF4), @@ -811,7 +846,39 @@ uart_shared!(USART4, USART4_RX, USART4_TX, ] ); -#[cfg(feature = "stm32g0x1")] +#[cfg(feature = "stm32g0b1")] +uart_shared!(USART5, USART5_RX, USART5_TX, + tx: [ + (PE10, AltFunction::AF3), + ], + rx: [ + (PE11, AltFunction::AF3), + ], + de: [ + (PE7, AltFunction::AF3), + ] +); + +#[cfg(feature = "stm32g0b1")] +uart_shared!(USART6, USART6_RX, USART6_TX, + tx: [ + (PF9, AltFunction::AF3), + ], + rx: [ + (PF10, AltFunction::AF3), + ], + de: [ + (PF3, AltFunction::AF3), + (PF11, AltFunction::AF3), + ] +); + +#[cfg(any( + feature = "stm32g031", + feature = "stm32g041", + feature = "stm32g071", + feature = "stm32g081" +))] uart_shared!(LPUART, LPUART_RX, LPUART_TX, tx: [ (PA2, AltFunction::AF6), @@ -829,22 +896,90 @@ uart_shared!(LPUART, LPUART_RX, LPUART_TX, ] ); +#[cfg(any(feature = "stm32g0b1",))] +uart_shared!(LPUART1, LPUART_RX, LPUART_TX, + tx: [ + (PA2, AltFunction::AF6), + (PB11, AltFunction::AF1), + (PC1, AltFunction::AF1), + (PF4, AltFunction::AF1), + ], + rx: [ + (PA3, AltFunction::AF6), + (PB10, AltFunction::AF1), + (PC0, AltFunction::AF1), + (PF5, AltFunction::AF1), + ], + de: [ + (PB1, AltFunction::AF6), + (PB12, AltFunction::AF1), + (PD15, AltFunction::AF1), + (PF6, AltFunction::AF1), + ] +); + +#[cfg(any(feature = "stm32g0b1",))] +uart_shared!(LPUART2, LPUART2_RX, LPUART2_TX, + tx: [ + (PF2, AltFunction::AF1), + (PC6, AltFunction::AF3), + ], + rx: [ + (PF3, AltFunction::AF1), + (PC7, AltFunction::AF3), + ], + de: [ + (PD15, AltFunction::AF1), + (PC9, AltFunction::AF3), + ] +); + uart_full!(USART1, usart1, 1); -#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" +))] uart_full!(USART2, usart2, 1); +#[cfg(feature = "stm32g0b1")] +uart_full!(USART3, usart3, 1); + #[cfg(any(feature = "stm32g030", feature = "stm32g031", feature = "stm32g041"))] uart_basic!(USART2, usart2, 1); -#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081",))] uart_basic!(USART3, usart3, 1); -#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))] +#[cfg(any( + feature = "stm32g070", + feature = "stm32g071", + feature = "stm32g081", + feature = "stm32g0b1" +))] uart_basic!(USART4, usart4, 1); +#[cfg(feature = "stm32g0b1")] +uart_basic!(USART5, usart5, 1); + +#[cfg(feature = "stm32g0b1")] +uart_basic!(USART6, usart6, 1); + // LPUART Should be given its own implementation when it needs to be used with features not present on // the basic feature set such as: Dual clock domain, FIFO or prescaler. // Or when Synchronous mode is implemented for the basic feature set, since the LP feature set does not have support. -#[cfg(feature = "stm32g0x1")] +#[cfg(any( + feature = "stm32g031", + feature = "stm32g041", + feature = "stm32g071", + feature = "stm32g081" +))] uart_basic!(LPUART, lpuart, 256); + +#[cfg(feature = "stm32g0b1")] +uart_basic!(LPUART1, lpuart1, 256); + +#[cfg(feature = "stm32g0b1")] +uart_basic!(LPUART2, lpuart2, 256);