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Potential DMA overhaul/rethink/cleanup discussion #170

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usbalbin opened this issue Jan 13, 2025 · 9 comments
Open

Potential DMA overhaul/rethink/cleanup discussion #170

usbalbin opened this issue Jan 13, 2025 · 9 comments

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@usbalbin
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usbalbin commented Jan 13, 2025

Thought I would make an issue to have somewhere to discuss

Some prior art

Doc

cc @AdinAck

@usbalbin
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I have quite limited experiance with DMA so take this with a grain of salt but here are some of the use cases I think might be nice to support:

  1. DMA for collecting ADC samples. Might for example be useful when the ADC is triggered by hardware and timing is very important like measuring at specific points in the switch period of a DC/DC converter, still letting the processor do other things at the same time.
  2. UART Tx. Send an entire message asyncronously
  3. UART Rx. Receive an entire message asyncronously (how do we know when to stop? timeout, msg len, etc?)
  4. more?

@AdinAck
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AdinAck commented Jan 13, 2025

  1. Yes I believe G0 has an example of this.
  2. To be a bit more specific, send messages of differing lengths one after the next.
  3. There are two ways (Embassy has both):
    • Receive until idle line
    • Receive until receive buffer full
  4. A peripheral to peripheral example would be nice. (ADC -> FMAC ?)

@usbalbin
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usbalbin commented Jan 13, 2025

  1. A peripheral to peripheral example would be nice. (ADC -> FMAC ?)

Would that mean that you could have the entire control loop running in FMAC? So for example ADC -> FMAC(for example pid IIR regulator) -> PWM-duty, with the help of DMA?

Something along those lines might be done in AN5788

@AdinAck
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AdinAck commented Jan 13, 2025

Interesting idea! I have never used the FMAC so I don't know if this is within it's capabilities. I was just thinking denoising an ADC signal before serving it to the CPU, but if the FMAC can facilitate a PID loop for the duty cycle of a timer that would be an awesome example to provide!

@usbalbin
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usbalbin commented Jan 13, 2025

Reading an5497 page 51 they seem to "only" have the DMA transfer from ADC to FMAC and then trigger an interrupt which does some clamping and then passes the value along.

@usbalbin
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Table 9 of AN5788 gives some performance numbers on regulator in software vs in FMAC

@AdinAck
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AdinAck commented Jan 13, 2025

Yeah those numbers make sense, I kind of expected the performance improvement to be much greater (like CORDIC) but I guess filtering takes a long time even when done by a dedicated co-processor. Still would be a good DMA example.

@usbalbin
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  1. To be a bit more specific, send messages of differing lengths one after the next.

Could something like next_transfer described in #171 solve this use case?

@AdinAck
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AdinAck commented Jan 15, 2025

I really don't have enough information to say right now. It might be some time before I have enough experience with DMA to speak to any design choices. I am thinking on it but I don't have any answers yet.

It likely would be a step in the right direction, though.

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