diff --git a/Cargo.toml b/Cargo.toml
index eb55bbfa..d4b3465d 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -12,7 +12,7 @@ repository = "https://github.com/stm32-rs/stm32g4xx-hal"
 version = "0.0.2"
 
 [dependencies]
-nb = "0.1.1"
+nb = "1"
 stm32g4 = "0.15.1"
 paste = "1.0"
 bitflags = "1.2"
@@ -21,6 +21,7 @@ static_assertions = "1.1"
 fugit = "0.3.7"
 stm32-usbd = { version = "0.7.0", optional = true }
 fixed = { version = "1.28.0", optional = true }
+embedded-io = "0.6"
 
 [dependencies.cortex-m]
 version = "0.7.7"
@@ -38,9 +39,13 @@ default-features = false
 features = ["const-fn"]
 version = "0.2.5"
 
-[dependencies.embedded-hal]
+[dependencies.embedded-hal-old]
+package = "embedded-hal"
 features = ["unproven"]
-version = "0.2.4"
+version = "0.2.7"
+
+[dependencies.embedded-hal]
+version = "1.0.0"
 
 [dependencies.embedded-dma]
 version = "0.1.2"
@@ -93,7 +98,7 @@ stm32g4a1 = ["stm32g4/stm32g4a1"]
 log-itm = ["cortex-m-log/itm"]
 log-rtt = []
 log-semihost = ["cortex-m-log/semihosting"]
-defmt = ["dep:defmt", "fugit/defmt"]
+defmt = ["dep:defmt", "fugit/defmt", "nb/defmt-0-3", "embedded-hal/defmt-03", "embedded-io/defmt-03"]
 cordic = ["dep:fixed"]
 
 [profile.dev]
diff --git a/examples/adc-continious-dma.rs b/examples/adc-continious-dma.rs
index e7ceb824..9788af0e 100644
--- a/examples/adc-continious-dma.rs
+++ b/examples/adc-continious-dma.rs
@@ -2,6 +2,7 @@
 #![no_main]
 
 mod utils;
+use utils::logger::info;
 
 use crate::hal::{
     adc::{
@@ -20,7 +21,6 @@ use crate::hal::{
 use stm32g4xx_hal as hal;
 
 use cortex_m_rt::entry;
-use utils::logger::info;
 
 #[entry]
 fn main() -> ! {
@@ -48,6 +48,7 @@ fn main() -> ! {
 
     info!("Setup Adc1");
     let mut delay = cp.SYST.delay(&rcc.clocks);
+
     let mut adc = dp
         .ADC1
         .claim(ClockSource::SystemClock, &rcc, &mut delay, true);
diff --git a/examples/adc-one-shot-dma.rs b/examples/adc-one-shot-dma.rs
index 898e7f02..7226f6a2 100644
--- a/examples/adc-one-shot-dma.rs
+++ b/examples/adc-one-shot-dma.rs
@@ -17,10 +17,9 @@ use crate::hal::{
 };
 use stm32g4xx_hal as hal;
 
-use log::info;
-
 #[macro_use]
 mod utils;
+use utils::logger::info;
 
 #[entry]
 fn main() -> ! {
@@ -49,6 +48,7 @@ fn main() -> ! {
 
     info!("Setup Adc1");
     let mut delay = cp.SYST.delay(&rcc.clocks);
+
     let mut adc = dp
         .ADC1
         .claim(ClockSource::SystemClock, &rcc, &mut delay, true);
diff --git a/examples/adc-one-shot.rs b/examples/adc-one-shot.rs
index 7e727430..43f36ecb 100644
--- a/examples/adc-one-shot.rs
+++ b/examples/adc-one-shot.rs
@@ -3,7 +3,6 @@
 
 use crate::hal::{
     adc::{config::SampleTime, AdcClaim},
-    delay::SYSTDelayExt,
     pwr::PwrExt,
     rcc::Config,
     stm32::Peripherals,
@@ -13,10 +12,9 @@ use stm32g4xx_hal as hal;
 
 use cortex_m_rt::entry;
 
-use log::info;
-
 #[macro_use]
 mod utils;
+use utils::logger::info;
 
 #[entry]
 fn main() -> ! {
diff --git a/examples/blinky_delay.rs b/examples/blinky_delay.rs
index 7e815c4c..8b55119f 100644
--- a/examples/blinky_delay.rs
+++ b/examples/blinky_delay.rs
@@ -3,7 +3,6 @@
 #![no_main]
 #![no_std]
 
-use hal::delay::DelayFromCountDownTimer;
 use hal::prelude::*;
 use hal::pwr::PwrExt;
 use hal::rcc::Config;
@@ -37,7 +36,7 @@ fn main() -> ! {
 
     info!("Init Timer2 delay");
     let timer2 = Timer::new(dp.TIM2, &rcc.clocks);
-    let mut delay_tim2 = DelayFromCountDownTimer::new(timer2.start_count_down(100.millis()));
+    let mut delay_tim2 = timer2.start_count_down(100.millis()).delay();
 
     loop {
         info!("Toggle");
@@ -47,6 +46,6 @@ fn main() -> ! {
         info!("Toggle");
         led.toggle().unwrap();
         info!("TIM2 delay");
-        delay_tim2.delay_ms(1000_u16);
+        delay_tim2.delay_ms(1000);
     }
 }
diff --git a/examples/button.rs b/examples/button.rs
index f119b6a8..ef7990ec 100644
--- a/examples/button.rs
+++ b/examples/button.rs
@@ -14,7 +14,7 @@ use core::cell::RefCell;
 use core::sync::atomic::{AtomicBool, Ordering};
 use cortex_m::{asm::wfi, interrupt::Mutex};
 use cortex_m_rt::entry;
-use embedded_hal::digital::v2::OutputPin;
+use embedded_hal::digital::OutputPin;
 
 type ButtonPin = gpioc::PC13<Input<PullDown>>;
 
diff --git a/examples/can-echo.rs b/examples/can-echo.rs
index a0d81fee..3126e0d4 100644
--- a/examples/can-echo.rs
+++ b/examples/can-echo.rs
@@ -22,10 +22,9 @@ use core::num::{NonZeroU16, NonZeroU8};
 
 use cortex_m_rt::entry;
 
-use log::info;
-
 #[macro_use]
 mod utils;
+use utils::logger::info;
 
 #[entry]
 fn main() -> ! {
@@ -116,7 +115,7 @@ fn main() -> ! {
         bit_rate_switching: false,
         marker: None,
     };
-    info!("Initial Header: {:#X?}", &header);
+    info!("Initial Header: {:#?}", &header);
 
     info!("Transmit initial message");
     block!(can.transmit(header, &buffer)).unwrap();
diff --git a/examples/comp_w_dac.rs b/examples/comp_w_dac.rs
index 20600068..a2a3d703 100644
--- a/examples/comp_w_dac.rs
+++ b/examples/comp_w_dac.rs
@@ -10,7 +10,6 @@ use rt::entry;
 
 #[entry]
 fn main() -> ! {
-    use embedded_hal::Direction;
     use hal::comparator::{self, ComparatorExt, ComparatorSplit};
     use hal::dac::{Dac1IntSig1, DacExt, DacOut};
     use hal::delay::SYSTDelayExt;
@@ -49,6 +48,11 @@ fn main() -> ! {
     comp.output_pin(led2);
     let _comp1 = comp.enable().lock();
 
+    enum Direction {
+        Upcounting,
+        Downcounting,
+    }
+
     let mut dir = Direction::Upcounting;
     let mut val = 0;
 
diff --git a/examples/dac.rs b/examples/dac.rs
index 7348f703..45552572 100644
--- a/examples/dac.rs
+++ b/examples/dac.rs
@@ -8,7 +8,6 @@
 #![no_main]
 #![no_std]
 
-use embedded_hal::Direction;
 use hal::dac::{DacExt, DacOut, GeneratorConfig};
 use hal::delay::SYSTDelayExt;
 use hal::gpio::GpioExt;
@@ -37,6 +36,11 @@ fn main() -> ! {
     // dac_generator will have its value set automatically from its internal noise generator
     let mut dac_generator = dac1ch2.enable_generator(GeneratorConfig::noise(11));
 
+    enum Direction {
+        Upcounting,
+        Downcounting,
+    }
+
     let mut dir = Direction::Upcounting;
     let mut val = 0;
 
diff --git a/examples/i2c-bme680.rs b/examples/i2c-bme680.rs
index 2fa8a9c0..f3f18033 100644
--- a/examples/i2c-bme680.rs
+++ b/examples/i2c-bme680.rs
@@ -5,7 +5,7 @@
 
 use bme680::*;
 use core::time::Duration;
-use embedded_hal::blocking::delay::DelayMs;
+use embedded_hal::delay::DelayNs;
 use hal::delay::DelayFromCountDownTimer;
 use hal::i2c::Config;
 use hal::prelude::*;
@@ -15,10 +15,10 @@ use hal::timer::Timer;
 use stm32g4xx_hal as hal;
 
 use cortex_m_rt::entry;
-use log::info;
 
 #[macro_use]
 mod utils;
+use utils::logger::info;
 
 #[entry]
 fn main() -> ! {
diff --git a/examples/i2c-mpu6050.rs b/examples/i2c-mpu6050.rs
index a0be9c10..a9bf69ad 100644
--- a/examples/i2c-mpu6050.rs
+++ b/examples/i2c-mpu6050.rs
@@ -10,11 +10,11 @@ use hal::time::{ExtU32, RateExtU32};
 use stm32g4xx_hal as hal;
 
 use cortex_m_rt::entry;
-use log::info;
 use mpu6050::*;
 
 #[macro_use]
 mod utils;
+use utils::logger::info;
 
 #[entry]
 fn main() -> ! {
diff --git a/examples/i2c.rs b/examples/i2c.rs
index 78104767..beea9ae2 100644
--- a/examples/i2c.rs
+++ b/examples/i2c.rs
@@ -10,10 +10,10 @@ use hal::time::RateExtU32;
 use stm32g4xx_hal as hal;
 
 use cortex_m_rt::entry;
-use log::info;
 
 #[macro_use]
 mod utils;
+use utils::logger::info;
 
 #[entry]
 fn main() -> ! {
@@ -35,7 +35,7 @@ fn main() -> ! {
 
     let buf: [u8; 1] = [0];
     loop {
-        match i2c.write(0x3c, &buf) {
+        match i2c.write(0x3Cu8, &buf) {
             Ok(_) => info!("ok"),
             Err(err) => info!("error: {:?}", err),
         }
diff --git a/examples/pwm.rs b/examples/pwm.rs
index 9d2ca8e8..cee8f7d7 100644
--- a/examples/pwm.rs
+++ b/examples/pwm.rs
@@ -11,6 +11,7 @@ use hal::stm32;
 use hal::time::RateExtU32;
 use stm32g4xx_hal as hal;
 extern crate cortex_m_rt as rt;
+use hal::prelude::SetDutyCycle;
 
 #[macro_use]
 mod utils;
@@ -26,7 +27,7 @@ fn main() -> ! {
 
     let mut pwm = dp.TIM1.pwm(pin, 100.Hz(), &mut rcc);
 
-    pwm.set_duty(pwm.get_max_duty() / 2);
+    let _ = pwm.set_duty_cycle_percent(50);
     pwm.enable();
 
     loop {
diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs
index 04533e3f..dcfff763 100644
--- a/examples/spi-dma.rs
+++ b/examples/spi-dma.rs
@@ -28,6 +28,7 @@ use stm32g4xx_hal::dma::TransferExt;
 
 #[macro_use]
 mod utils;
+// use utils::logger::info;
 
 const BUFFER_SIZE: usize = 254;
 
@@ -68,6 +69,6 @@ fn main() -> ! {
             .into_memory_to_peripheral_transfer(spi.enable_tx_dma(), &mut dma_buf[..], config);
     transfer_dma.start(|_spi| {});
     loop {
-        delay_tim2.delay_ms(1000_u16);
+        delay_tim2.delay_ms(1000);
     }
 }
diff --git a/examples/spi-example.rs b/examples/spi-example.rs
index 2543e3fc..a661e248 100644
--- a/examples/spi-example.rs
+++ b/examples/spi-example.rs
@@ -5,14 +5,14 @@
 #![no_main]
 #![no_std]
 
-use crate::hal::{
-    block,
+use hal::{
     delay::DelayFromCountDownTimer,
     gpio::gpioa::PA5,
     gpio::gpioa::PA6,
     gpio::gpioa::PA7,
     gpio::Alternate,
     gpio::AF5,
+    hal_02::spi::FullDuplex,
     prelude::*,
     pwr::PwrExt,
     rcc::Config,
@@ -59,11 +59,11 @@ fn main() -> ! {
         for byte in message.iter() {
             cs.set_low().unwrap();
             spi.send(*byte as u8).unwrap();
-            received_byte = block!(spi.read()).unwrap();
+            received_byte = nb::block!(FullDuplex::read(&mut spi)).unwrap();
             cs.set_high().unwrap();
 
             info!("{}", received_byte as char);
         }
-        delay_tim2.delay_ms(1000_u16);
+        delay_tim2.delay_ms(1000);
     }
 }
diff --git a/examples/uart-dma-tx.rs b/examples/uart-dma-tx.rs
index 78abeb4f..bc92922a 100644
--- a/examples/uart-dma-tx.rs
+++ b/examples/uart-dma-tx.rs
@@ -16,10 +16,10 @@ use hal::{rcc, stm32};
 use stm32g4xx_hal as hal;
 
 use cortex_m_rt::entry;
-use log::info;
 
 #[macro_use]
 mod utils;
+use utils::logger::info;
 
 #[entry]
 fn main() -> ! {
diff --git a/examples/uart-fifo.rs b/examples/uart-fifo.rs
index eb6ddb88..801ae471 100644
--- a/examples/uart-fifo.rs
+++ b/examples/uart-fifo.rs
@@ -7,6 +7,7 @@ extern crate cortex_m_rt as rt;
 
 use core::fmt::Write;
 
+use embedded_io::{Read, ReadReady};
 use hal::prelude::*;
 use hal::pwr::PwrExt;
 use hal::serial::*;
@@ -14,10 +15,10 @@ use hal::{rcc, stm32};
 use stm32g4xx_hal as hal;
 
 use cortex_m_rt::entry;
-use log::info;
 
 #[macro_use]
 mod utils;
+use utils::logger::info;
 
 #[entry]
 fn main() -> ! {
@@ -50,23 +51,24 @@ fn main() -> ! {
 
     let (mut tx1, mut rx1) = usart.split();
 
+    let mut buffer = [0; 4];
     let mut cnt = 0;
     loop {
         if rx1.fifo_threshold_reached() {
             loop {
-                match rx1.read() {
-                    Err(nb::Error::WouldBlock) => {
-                        // no more data available in fifo
-                        break;
-                    }
-                    Err(nb::Error::Other(_err)) => {
+                match rx1.read_ready() {
+                    Ok(true) => (),
+                    Ok(false) => break, // no more data available in fifo
+                    Err(e) => {
                         // Handle other error Overrun, Framing, Noise or Parity
-                    }
-                    Ok(byte) => {
-                        writeln!(tx1, "{}: {}\r", cnt, byte).unwrap();
-                        cnt += 1;
+                        utils::logger::error!("Error: {:?}", e);
                     }
                 }
+
+                let count = rx1.read(&mut buffer).unwrap();
+                let bytes = &buffer[count];
+                writeln!(tx1, "{}: {}\r", cnt, bytes).unwrap();
+                cnt += count;
             }
         }
     }
diff --git a/examples/uart.rs b/examples/uart.rs
index 883ef3b7..e4ec6519 100644
--- a/examples/uart.rs
+++ b/examples/uart.rs
@@ -3,8 +3,7 @@
 #![no_main]
 #![no_std]
 
-use core::fmt::Write;
-
+use embedded_io::{Read, Write};
 use hal::prelude::*;
 use hal::pwr::PwrExt;
 use hal::serial::FullConfig;
@@ -12,7 +11,6 @@ use hal::{rcc, stm32};
 use stm32g4xx_hal as hal;
 
 use cortex_m_rt::entry;
-use nb::block;
 use utils::logger::info;
 
 #[macro_use]
@@ -54,11 +52,15 @@ fn main() -> ! {
         .unwrap();
 
     writeln!(usart, "Hello USART3, yay!!\r\n").unwrap();
+    let mut read_buf = [0u8; 8];
+    usart.read_exact(&mut read_buf).unwrap();
+    usart.write_all(&read_buf).unwrap();
 
+    let mut single_byte_buffer = [0; 1];
     let mut cnt = 0;
     loop {
-        match block!(usart.read()) {
-            Ok(byte) => writeln!(usart, "{}: {}\r", cnt, byte).unwrap(),
+        match usart.read_exact(&mut single_byte_buffer) {
+            Ok(()) => writeln!(usart, "{}: {}\r", cnt, single_byte_buffer[0]).unwrap(),
             Err(e) => writeln!(usart, "E: {:?}\r", e).unwrap(),
         };
         cnt += 1;
diff --git a/src/adc.rs b/src/adc.rs
index b40df49a..e2ed773d 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -1,5 +1,5 @@
 //! Analog to digital converter configuration.
-//! https://github.com/stm32-rs/stm32l4xx-hal/blob/master/src/adc.rs
+//! <https://github.com/stm32-rs/stm32l4xx-hal/blob/master/src/adc.rs>
 
 #![deny(missing_docs)]
 
@@ -20,10 +20,8 @@ use crate::{
 };
 use core::fmt;
 use core::marker::PhantomData;
-use embedded_hal::{
-    adc::{Channel, OneShot},
-    blocking::delay::DelayUs,
-};
+use embedded_hal::delay::DelayNs;
+use embedded_hal_old::adc::{Channel, OneShot};
 
 use self::config::ExternalTrigger12;
 
@@ -172,7 +170,7 @@ macro_rules! adc_opamp {
 
 /// Contains types related to ADC configuration
 pub mod config {
-    use embedded_hal::adc::Channel;
+    use embedded_hal_old::adc::Channel;
 
     /// The place in the sequence a given channel should be captured
     #[derive(Debug, PartialEq, PartialOrd, Copy, Clone)]
@@ -316,7 +314,8 @@ pub mod config {
     pub enum ClockMode {
         /// (Asynchronous clock mode), adc_ker_ck. generated at product level (refer to Section 6: Reset and clock control (RCC)
         Asynchronous,
-        /// (Synchronous clock mode). adc_hclk/1 This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock has a 50% duty cycle.
+        /// (Synchronous clock mode). adc_hclk/1
+        /// This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE\[3:0\] = 0xxx in RCC_CFGR register) and if the system clock has a 50% duty cycle.
         Synchronous_Div_1,
         /// Synchronous clock mode. adc_hclk/2
         Synchronous_Div_2,
@@ -1172,9 +1171,9 @@ impl<ADC: TriggerType> Conversion<ADC> {
         !self.is_active()
     }
 
-    /// Converts from Conversion<C, E> to Option<C>.
+    /// Converts from `Conversion<C, E>` to `Option<C>`.
     ///
-    /// Converts self into an Option<C>, consuming self, and discarding the adc, if it is stopped.
+    /// Converts self into an `Option<C>`, consuming self, and discarding the adc, if it is stopped.
     #[inline(always)]
     pub fn active(self) -> Option<Adc<ADC, Active>> {
         match self {
@@ -1183,9 +1182,9 @@ impl<ADC: TriggerType> Conversion<ADC> {
         }
     }
 
-    /// Converts from Conversion<C, E> to Option<E>.
+    /// Converts from `Conversion<C, E>` to `Option<E>`.
     ///
-    /// Converts self into an Option<E>, consuming self, and discarding the adc, if it is still active.
+    /// Converts self into an `Option<E>`, consuming self, and discarding the adc, if it is still active.
     #[inline(always)]
     pub fn stopped(self) -> Option<Adc<ADC, Configured>> {
         match self {
@@ -1385,7 +1384,7 @@ pub trait AdcClaim<TYPE: TriggerType> {
         self,
         cs: ClockSource,
         rcc: &Rcc,
-        delay: &mut impl DelayUs<u8>,
+        delay: &mut impl DelayNs,
         reset: bool,
     ) -> Adc<TYPE, Disabled>;
 
@@ -1395,7 +1394,7 @@ pub trait AdcClaim<TYPE: TriggerType> {
         cs: ClockSource,
         rcc: &Rcc,
         config: config::AdcConfig<TYPE::ExternalTrigger>,
-        delay: &mut impl DelayUs<u8>,
+        delay: &mut impl DelayNs,
         reset: bool,
     ) -> Adc<TYPE, Configured>;
 }
@@ -1587,7 +1586,7 @@ macro_rules! adc {
 
                 /// Powers-up an powered-down Adc
                 #[inline(always)]
-                pub fn power_up(&mut self, delay: &mut impl DelayUs<u8>) {
+                pub fn power_up(&mut self, delay: &mut impl DelayNs) {
                     if self.is_deeppwd_enabled() {
                         self.disable_deeppwd_down();
                     }
@@ -1620,7 +1619,7 @@ macro_rules! adc {
 
                 /// Enables the Voltage Regulator
                 #[inline(always)]
-                pub fn enable_vreg(&mut self, delay: &mut impl DelayUs<u8>) {
+                pub fn enable_vreg(&mut self, delay: &mut impl DelayNs) {
                     self.adc_reg.cr.modify(|_, w| w.advregen().set_bit());
                     while !self.adc_reg.cr.read().advregen().bit_is_set() {}
 
@@ -2129,7 +2128,7 @@ macro_rules! adc {
                 ///
                 /// TODO: fix needing SYST
                 #[inline(always)]
-                fn claim(self, cs: ClockSource, rcc: &Rcc, delay: &mut impl DelayUs<u8>, reset: bool) -> Adc<stm32::$adc_type, Disabled> {
+                fn claim(self, cs: ClockSource, rcc: &Rcc, delay: &mut impl DelayNs, reset: bool) -> Adc<stm32::$adc_type, Disabled> {
                     unsafe {
                         let rcc_ptr = &(*stm32::RCC::ptr());
                         stm32::$adc_type::enable(rcc_ptr);
@@ -2153,7 +2152,7 @@ macro_rules! adc {
 
                 /// claims and configures the Adc
                 #[inline(always)]
-                fn claim_and_configure(self, cs: ClockSource, rcc: &Rcc, config: config::AdcConfig<$trigger_type>, delay: &mut impl DelayUs<u8>, reset :bool) -> Adc<stm32::$adc_type, Configured> {
+                fn claim_and_configure(self, cs: ClockSource, rcc: &Rcc, config: config::AdcConfig<$trigger_type>, delay: &mut impl DelayNs, reset :bool) -> Adc<stm32::$adc_type, Configured> {
                     let mut adc = self.claim(cs, rcc, delay, reset);
                     adc.adc.config = config;
 
@@ -2177,7 +2176,7 @@ macro_rules! adc {
             impl Adc<stm32::$adc_type, PoweredDown> {
                 /// Powers-up an powered-down Adc
                 #[inline(always)]
-                pub fn power_up(mut self, delay: &mut impl DelayUs<u8>) -> Adc<stm32::$adc_type, Disabled> {
+                pub fn power_up(mut self, delay: &mut impl DelayNs) -> Adc<stm32::$adc_type, Disabled> {
                     self.adc.power_up(delay);
 
                     Adc {
diff --git a/src/dac.rs b/src/dac.rs
index 109374c0..5289da29 100644
--- a/src/dac.rs
+++ b/src/dac.rs
@@ -12,7 +12,7 @@ use crate::gpio::gpioa::{PA4, PA5, PA6};
 use crate::gpio::DefaultMode;
 use crate::rcc::{self, *};
 use crate::stm32::{DAC1, DAC2, DAC3, DAC4, RCC};
-use hal::blocking::delay::DelayUs;
+use embedded_hal::delay::DelayNs;
 
 pub trait DacOut<V> {
     fn set_value(&mut self, val: V);
@@ -230,9 +230,9 @@ macro_rules! dac_helper {
                 ///
                 /// After the calibration operation, the DAC channel is
                 /// disabled.
-                pub fn calibrate_buffer<T>(self, delay: &mut T) -> $CX<MODE_BITS, Disabled>
+                pub fn calibrate_buffer<D>(self, delay: &mut D) -> $CX<MODE_BITS, Disabled>
                 where
-                    T: DelayUs<u32>,
+                    D: DelayNs
                 {
                     let dac = unsafe { &(*<$DAC>::ptr()) };
                     dac.dac_cr.modify(|_, w| w.$en().clear_bit());
diff --git a/src/delay.rs b/src/delay.rs
index f40ffeae..1b869adf 100644
--- a/src/delay.rs
+++ b/src/delay.rs
@@ -1,9 +1,9 @@
 //! Delay providers
 //!
 //! There are currently two delay providers. In general you should prefer to use
-//! [Delay](Delay), however if you do not have access to `SYST` you can use
-//! [DelayFromCountDownTimer](DelayFromCountDownTimer) with any timer that
-//! implements the [CountDown](embedded_hal::timer::CountDown) trait. This can be
+//! [Delay], however if you do not have access to `SYST` you can use
+//! [DelayFromCountDownTimer] with any timer that
+//! implements the [CountDown](embedded_hal_old::timer::CountDown) trait. This can be
 //! useful if you're using [RTIC](https://rtic.rs)'s schedule API, which occupies
 //! the `SYST` peripheral.
 //!
@@ -38,24 +38,83 @@
 
 use crate::rcc::Clocks;
 use crate::time::MicroSecond;
-pub use cortex_m::delay::*;
+pub use cortex_m::delay::Delay;
 use cortex_m::peripheral::SYST;
+use fugit::ExtU32Ceil;
 
 use crate::nb::block;
 use crate::time::ExtU32;
-use embedded_hal::blocking::delay::{DelayMs, DelayUs};
+use embedded_hal::delay::DelayNs;
+use embedded_hal_old::blocking::delay::{DelayMs, DelayUs};
 
-pub trait CountDown: embedded_hal::timer::CountDown {
+pub trait CountDown: embedded_hal_old::timer::CountDown {
     fn max_period(&self) -> MicroSecond;
 }
 
 pub trait SYSTDelayExt {
-    fn delay(self, clocks: &Clocks) -> Delay;
+    fn delay(self, clocks: &Clocks) -> SystDelay;
 }
 
 impl SYSTDelayExt for SYST {
-    fn delay(self, clocks: &Clocks) -> Delay {
-        Delay::new(self, clocks.ahb_clk.raw())
+    fn delay(self, clocks: &Clocks) -> SystDelay {
+        SystDelay(Delay::new(self, clocks.ahb_clk.raw()))
+    }
+}
+
+/// Delay provider
+pub struct SystDelay(Delay);
+
+impl DelayNs for SystDelay {
+    // TODO: the current fallback to 1us resolution is a stopgap until the module is reworked
+    fn delay_ns(&mut self, ns: u32) {
+        self.0.delay_us(ns.div_ceil(1000))
+    }
+    fn delay_us(&mut self, us: u32) {
+        self.0.delay_us(us);
+    }
+    fn delay_ms(&mut self, mut ms: u32) {
+        const MAX_MILLIS: u32 = u32::MAX / 1000;
+        while ms > MAX_MILLIS {
+            ms -= MAX_MILLIS;
+            DelayNs::delay_us(self, MAX_MILLIS * 1000);
+        }
+        DelayNs::delay_us(self, ms * 1000);
+    }
+}
+
+impl DelayUs<u32> for SystDelay {
+    fn delay_us(&mut self, us: u32) {
+        DelayNs::delay_us(self, us);
+    }
+}
+
+impl DelayUs<u16> for SystDelay {
+    fn delay_us(&mut self, us: u16) {
+        DelayNs::delay_us(self, us as u32);
+    }
+}
+
+impl DelayUs<u8> for SystDelay {
+    fn delay_us(&mut self, us: u8) {
+        DelayNs::delay_us(self, us as u32);
+    }
+}
+
+impl DelayMs<u32> for SystDelay {
+    fn delay_ms(&mut self, ms: u32) {
+        DelayNs::delay_ms(self, ms);
+    }
+}
+
+impl DelayMs<u16> for SystDelay {
+    fn delay_ms(&mut self, ms: u16) {
+        DelayNs::delay_ms(self, ms as u32);
+    }
+}
+
+impl DelayMs<u8> for SystDelay {
+    fn delay_ms(&mut self, ms: u8) {
+        DelayNs::delay_ms(self, ms as u32);
     }
 }
 
@@ -65,12 +124,12 @@ pub trait DelayExt {
         T: Into<MicroSecond>;
 }
 
-impl DelayExt for Delay {
+impl DelayExt for SystDelay {
     fn delay<T>(&mut self, delay: T)
     where
         T: Into<MicroSecond>,
     {
-        self.delay_us(delay.into().ticks())
+        self.0.delay_us(delay.into().ticks())
     }
 }
 
@@ -132,7 +191,7 @@ macro_rules! impl_delay_from_count_down_timer  {
                 T: CountDown<Time = MicroSecond>,
             {
                 fn $delay(&mut self, t: u16) {
-                    self.$delay(t as u32);
+                    $Delay::$delay(self, t as u32);
                 }
             }
 
@@ -141,7 +200,7 @@ macro_rules! impl_delay_from_count_down_timer  {
                 T: CountDown<Time = MicroSecond>,
             {
                 fn $delay(&mut self, t: u8) {
-                    self.$delay(t as u32);
+                    $Delay::$delay(self, t as u32);
                 }
             }
         )+
@@ -152,3 +211,34 @@ impl_delay_from_count_down_timer! {
     (DelayMs, delay_ms, 1_000),
     (DelayUs, delay_us, 1)
 }
+
+// TODO: decouple the timer API from embedded-hal 0.2, stm32f4xx-hal with constant timer
+// frequencies looks like a good example
+impl<T: CountDown<Time = MicroSecond>> DelayNs for DelayFromCountDownTimer<T> {
+    // From a quick look at the clock diagram timer resolution can go down to ~3ns on most timers
+    // 170MHz (PLL-R as SysClk) / 1 (AHB Prescaler) / 1 (APBx prescaler) * 2 = 340MHz timer clock
+    // TODO: the current fallback to 1us resolution is a stopgap until the module is reworked
+    fn delay_ns(&mut self, ns: u32) {
+        DelayNs::delay_us(self, ns.div_ceil(1000))
+    }
+    fn delay_us(&mut self, mut us: u32) {
+        let max_sleep = self.0.max_period();
+        let max_us = max_sleep.to_micros();
+
+        while us > max_us {
+            self.0.start(max_us.micros_at_least());
+            let _ = nb::block!(self.0.wait());
+            us -= max_us;
+        }
+        self.0.start(us.micros_at_least());
+        let _ = nb::block!(self.0.wait());
+    }
+    fn delay_ms(&mut self, mut ms: u32) {
+        const MAX_MILLIS: u32 = u32::MAX / 1000;
+        while ms > MAX_MILLIS {
+            ms -= MAX_MILLIS;
+            DelayNs::delay_us(self, MAX_MILLIS * 1000);
+        }
+        DelayNs::delay_us(self, ms * 1000);
+    }
+}
diff --git a/src/dma.rs b/src/dma.rs
index d05b6e00..d1033762 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -13,7 +13,7 @@
 //! instructions in DMA controller configuration.
 //!
 //! Adapted from
-//! https://github.com/stm32-rs/stm32h7xx-hal/blob/master/src/dma/mod.rs
+//! <https://github.com/stm32-rs/stm32h7xx-hal/blob/master/src/dma/mod.rs>
 
 use core::fmt::Debug;
 
diff --git a/src/dma/traits.rs b/src/dma/traits.rs
index d33a965e..214cc17a 100644
--- a/src/dma/traits.rs
+++ b/src/dma/traits.rs
@@ -1,7 +1,7 @@
 //! Traits for DMA types
 //!
 //! Adapted from
-//! https://github.com/stm32-rs/stm32f4xx-hal/blob/master/src/dma/traits.rs
+//! <https://github.com/stm32-rs/stm32f4xx-hal/blob/master/src/dma/traits.rs>
 
 use super::*;
 
diff --git a/src/gpio.rs b/src/gpio.rs
index bd43df0c..f0ae9845 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -240,7 +240,7 @@ macro_rules! gpio {
         /// GPIO
         pub mod $gpiox {
             use core::marker::PhantomData;
-            use hal::digital::v2::{toggleable, InputPin, OutputPin, StatefulOutputPin};
+            use embedded_hal_old::digital::v2::{toggleable, InputPin, OutputPin, StatefulOutputPin};
             use crate::stm32::{EXTI, $GPIOX};
             use crate::exti::{ExtiExt, Event};
             use crate::rcc::Rcc;
@@ -288,6 +288,24 @@ macro_rules! gpio {
                 }
             }
 
+            impl<MODE> embedded_hal::digital::ErrorType for $PXx<Output<MODE>> {
+                type Error = core::convert::Infallible;
+            }
+
+            impl<MODE> embedded_hal::digital::OutputPin for $PXx<Output<MODE>> {
+                fn set_high(&mut self) -> Result<(), Self::Error> {
+                    // NOTE(unsafe) atomic write to a stateless register
+                    unsafe { (*$GPIOX::ptr()).bsrr.write(|w| w.bits(1 << self.i)) };
+                    Ok(())
+                }
+
+                fn set_low(&mut self) -> Result<(), Self::Error> {
+                    // NOTE(unsafe) atomic write to a stateless register
+                    unsafe { (*$GPIOX::ptr()).bsrr.write(|w| w.bits(1 << (self.i + 16))) };
+                    Ok(())
+                }
+            }
+
             impl<MODE> StatefulOutputPin for $PXx<Output<MODE>> {
                 fn is_set_high(&self) -> Result<bool, ()> {
                     let is_set_high = !self.is_set_low()?;
@@ -301,9 +319,21 @@ macro_rules! gpio {
                 }
             }
 
-            impl<MODE> toggleable::Default for $PXx<Output<MODE>> {
+            impl<MODE> embedded_hal::digital::StatefulOutputPin for $PXx<Output<MODE>> {
+                fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+                    let is_set_high = !self.is_set_low()?;
+                    Ok(is_set_high)
+                }
+
+                fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+                    // NOTE(unsafe) atomic read with no side effects
+                    let is_set_low = unsafe { (*$GPIOX::ptr()).odr.read().bits() & (1 << self.i) == 0 };
+                    Ok(is_set_low)
+                }
             }
 
+            impl<MODE> toggleable::Default for $PXx<Output<MODE>> {}
+
             impl<MODE> InputPin for $PXx<Output<MODE>> {
                 type Error = ();
 
@@ -319,6 +349,20 @@ macro_rules! gpio {
                 }
             }
 
+            impl<MODE> embedded_hal::digital::InputPin for $PXx<Output<MODE>> {
+                fn is_high(&mut self) -> Result<bool, Self::Error> {
+                    let is_high = !self.is_low()?;
+                    Ok(is_high)
+                }
+
+                fn is_low(&mut self) -> Result<bool, Self::Error>  {
+                    // NOTE(unsafe) atomic read with no side effects
+                    let is_low = unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << self.i) == 0 };
+                    Ok(is_low)
+                }
+            }
+
+
             impl<MODE> InputPin for $PXx<Input<MODE>> {
                 type Error = ();
 
@@ -334,6 +378,23 @@ macro_rules! gpio {
                 }
             }
 
+            impl<MODE> embedded_hal::digital::ErrorType for $PXx<Input<MODE>> {
+                type Error = core::convert::Infallible;
+            }
+
+            impl<MODE> embedded_hal::digital::InputPin for $PXx<Input<MODE>> {
+                fn is_high(&mut self) -> Result<bool, Self::Error> {
+                    let is_high = !self.is_low()?;
+                    Ok(is_high)
+                }
+
+                fn is_low(&mut self) -> Result<bool, Self::Error> {
+                    // NOTE(unsafe) atomic read with no side effects
+                    let is_low = unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << self.i) == 0 };
+                    Ok(is_low)
+                }
+            }
+
             exti_erased!($PXx<Output<MODE>>, $Pxn);
             exti_erased!($PXx<Input<MODE>>, $Pxn);
 
@@ -572,6 +633,24 @@ macro_rules! gpio {
                     }
                 }
 
+                impl<MODE> embedded_hal::digital::ErrorType for $PXi<Output<MODE>> {
+                    type Error = core::convert::Infallible;
+                }
+
+                impl<MODE> embedded_hal::digital::OutputPin for $PXi<Output<MODE>> {
+                    fn set_high(&mut self) -> Result<(), Self::Error> {
+                        // NOTE(unsafe) atomic write to a stateless register
+                        unsafe { (*$GPIOX::ptr()).bsrr.write(|w| w.bits(1 << $i)) };
+                        Ok(())
+                    }
+
+                    fn set_low(&mut self) -> Result<(), Self::Error>{
+                        // NOTE(unsafe) atomic write to a stateless register
+                        unsafe { (*$GPIOX::ptr()).bsrr.write(|w| w.bits(1 << ($i + 16))) };
+                        Ok(())
+                    }
+                }
+
                 impl<MODE> StatefulOutputPin for $PXi<Output<MODE>> {
                     fn is_set_high(&self) -> Result<bool, ()> {
                         let is_set_high = !self.is_set_low()?;
@@ -585,9 +664,21 @@ macro_rules! gpio {
                     }
                 }
 
-                impl<MODE> toggleable::Default for $PXi<Output<MODE>> {
+                impl<MODE> embedded_hal::digital::StatefulOutputPin for $PXi<Output<MODE>> {
+                    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+                        let is_set_high = !self.is_set_low()?;
+                        Ok(is_set_high)
+                    }
+
+                    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+                        // NOTE(unsafe) atomic read with no side effects
+                        let is_set_low = unsafe { (*$GPIOX::ptr()).odr.read().bits() & (1 << $i) == 0 };
+                        Ok(is_set_low)
+                    }
                 }
 
+                impl<MODE> toggleable::Default for $PXi<Output<MODE>> {}
+
                 impl<MODE> InputPin for $PXi<Output<MODE>> {
                     type Error = ();
 
@@ -603,6 +694,19 @@ macro_rules! gpio {
                     }
                 }
 
+                impl<MODE> embedded_hal::digital::InputPin for $PXi<Output<MODE>> {
+                    fn is_high(&mut self) -> Result<bool, Self::Error> {
+                        let is_high = !self.is_low()?;
+                        Ok(is_high)
+                    }
+
+                    fn is_low(&mut self) -> Result<bool, Self::Error>  {
+                        // NOTE(unsafe) atomic read with no side effects
+                        let is_low = unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << $i) == 0 };
+                        Ok(is_low)
+                    }
+                }
+
                 impl<MODE> $PXi<Input<MODE>> {
                     /// Erases the pin number from the type
                     ///
@@ -613,6 +717,23 @@ macro_rules! gpio {
                     }
                 }
 
+                impl<MODE> embedded_hal::digital::ErrorType for $PXi<Input<MODE>> {
+                    type Error = core::convert::Infallible;
+                }
+
+                impl<MODE> embedded_hal::digital::InputPin for $PXi<Input<MODE>> {
+                    fn is_high(&mut self) -> Result<bool, Self::Error> {
+                        let is_high = !self.is_low()?;
+                        Ok(is_high)
+                    }
+
+                    fn is_low(&mut self) -> Result<bool, Self::Error> {
+                        // NOTE(unsafe) atomic read with no side effects
+                        let is_low = unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << $i) == 0 };
+                        Ok(is_low)
+                    }
+                }
+
                 impl<MODE> InputPin for $PXi<Input<MODE>> {
                     type Error = ();
 
diff --git a/src/i2c.rs b/src/i2c.rs
index 33fa7a65..c93f1c64 100644
--- a/src/i2c.rs
+++ b/src/i2c.rs
@@ -1,5 +1,6 @@
 //! I2C
-use hal::blocking::i2c::{Read, Write, WriteRead};
+use embedded_hal::i2c::{ErrorKind, Operation, SevenBitAddress, TenBitAddress};
+use embedded_hal_old::blocking::i2c::{Read, Write, WriteRead};
 
 use crate::gpio::{gpioa::*, gpiob::*, gpioc::*, gpiof::*};
 #[cfg(any(
@@ -116,15 +117,29 @@ pub trait SDAPin<I2C> {}
 pub trait SCLPin<I2C> {}
 
 /// I2C error
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[derive(Debug)]
 pub enum Error {
     Overrun,
+    // TODO: store NACK source (address/data)
     Nack,
     PECError,
     BusError,
     ArbitrationLost,
 }
 
+impl embedded_hal::i2c::Error for Error {
+    fn kind(&self) -> embedded_hal::i2c::ErrorKind {
+        match self {
+            Self::Overrun => ErrorKind::Overrun,
+            Self::Nack => ErrorKind::NoAcknowledge(embedded_hal::i2c::NoAcknowledgeSource::Unknown),
+            Self::PECError => ErrorKind::Other,
+            Self::BusError => ErrorKind::Bus,
+            Self::ArbitrationLost => ErrorKind::ArbitrationLoss,
+        }
+    }
+}
+
 pub trait I2cExt<I2C> {
     fn i2c<SDA, SCL>(self, sda: SDA, scl: SCL, config: Config, rcc: &mut Rcc) -> I2c<I2C, SDA, SCL>
     where
@@ -252,6 +267,143 @@ macro_rules! i2c {
             }
         }
 
+        impl<SDA, SCL> I2c<$I2CX, SDA, SCL> {
+            // copied from f3 hal
+            fn read_inner(&mut self, mut addr: u16, addr_10b: bool, buffer: &mut [u8]) -> Result<(), Error> {
+                if !addr_10b { addr <<= 1 };
+                let end = buffer.len() / 0xFF;
+
+                // Process 255 bytes at a time
+                for (i, buffer) in buffer.chunks_mut(0xFF).enumerate() {
+                    // Prepare to receive `bytes`
+                    self.i2c.cr2.modify(|_, w| {
+                        if i == 0 {
+                            w.add10().bit(addr_10b);
+                            w.sadd().bits(addr);
+                            w.rd_wrn().read();
+                            w.start().start();
+                        }
+                        w.nbytes().bits(buffer.len() as u8);
+                        if i == end {
+                            w.reload().completed().autoend().automatic()
+                        } else {
+                            w.reload().not_completed()
+                        }
+                    });
+
+                    for byte in buffer {
+                        // Wait until we have received something
+                        busy_wait!(self.i2c, rxne, is_not_empty);
+                        *byte = self.i2c.rxdr.read().rxdata().bits();
+                    }
+
+                    if i != end {
+                        // Wait until the last transmission is finished
+                        busy_wait!(self.i2c, tcr, is_complete);
+                    }
+                }
+
+                // Wait until the last transmission is finished
+                // auto stop is set
+                busy_wait!(self.i2c, stopf, is_stop);
+                Ok(self.i2c.icr.write(|w| w.stopcf().clear()))
+            }
+
+            fn write_inner(&mut self, mut addr: u16, addr_10b: bool, buffer: &[u8]) -> Result<(), Error> {
+                if !addr_10b { addr <<= 1 };
+                let end = buffer.len() / 0xFF;
+
+                if buffer.is_empty() {
+                    // 0 byte write
+                    self.i2c.cr2.modify(|_, w| {
+                        w.add10().bit(addr_10b);
+                        w.sadd().bits(addr);
+                        w.rd_wrn().write();
+                        w.nbytes().bits(0);
+                        w.reload().completed();
+                        w.autoend().automatic();
+                        w.start().start()
+                    });
+                    return Ok(())
+                }
+                // Process 255 bytes at a time
+                for (i, buffer) in buffer.chunks(0xFF).enumerate() {
+                    // Prepare to receive `bytes`
+                    self.i2c.cr2.modify(|_, w| {
+                        if i == 0 {
+                            w.add10().bit(addr_10b);
+                            w.sadd().bits(addr);
+                            w.rd_wrn().write();
+                            w.start().start();
+                        }
+                        w.nbytes().bits(buffer.len() as u8);
+                        if i == end {
+                            w.reload().completed().autoend().automatic()
+                        } else {
+                            w.reload().not_completed()
+                        }
+                    });
+
+                    for byte in buffer {
+                        // Wait until we are allowed to send data
+                        // (START has been ACKed or last byte went through)
+                        busy_wait!(self.i2c, txis, is_empty);
+                        self.i2c.txdr.write(|w| w.txdata().bits(*byte));
+                    }
+
+                    if i != end {
+                        // Wait until the last transmission is finished
+                        busy_wait!(self.i2c, tcr, is_complete);
+                    }
+                }
+
+                // Wait until the last transmission is finished
+                // auto stop is set
+                busy_wait!(self.i2c, stopf, is_stop);
+                Ok(self.i2c.icr.write(|w| w.stopcf().clear()))
+            }
+        }
+
+        impl<SDA, SCL> embedded_hal::i2c::ErrorType for I2c<$I2CX, SDA, SCL> {
+            type Error = Error;
+        }
+
+        // TODO: custom read/write/read_write impl with hardware stop logic
+        impl<SDA, SCL> embedded_hal::i2c::I2c for I2c<$I2CX, SDA, SCL> {
+            fn transaction(
+                &mut self,
+                address: SevenBitAddress,
+                operation: &mut [Operation<'_>]
+            ) -> Result<(), Self::Error> {
+                Ok(for op in operation {
+                    // Wait for any operation on the bus to finish
+                    // for example in the case of another bus master having claimed the bus
+                    while self.i2c.isr.read().busy().bit_is_set() {};
+                    match op {
+                        Operation::Read(data) => self.read_inner(address as u16, false, data)?,
+                        Operation::Write(data) => self.write_inner(address as u16, false, data)?,
+                    }
+                })
+            }
+        }
+        impl<SDA, SCL> embedded_hal::i2c::I2c<TenBitAddress> for I2c<$I2CX, SDA, SCL> {
+            fn transaction(
+                &mut self,
+                address: TenBitAddress,
+                operation: &mut [Operation<'_>]
+            ) -> Result<(), Self::Error> {
+                Ok(for op in operation {
+                    // Wait for any operation on the bus to finish
+                    // for example in the case of another bus master having claimed the bus
+                    while self.i2c.isr.read().busy().bit_is_set() {};
+                    match op {
+                        Operation::Read(data) => self.read_inner(address, true, data)?,
+                        Operation::Write(data) => self.write_inner(address, true, data)?,
+                    }
+                })
+            }
+        }
+
         impl<SDA, SCL> WriteRead for I2c<$I2CX, SDA, SCL> {
             type Error = Error;
 
@@ -261,71 +413,8 @@ macro_rules! i2c {
                 bytes: &[u8],
                 buffer: &mut [u8],
             ) -> Result<(), Self::Error> {
-                // TODO support transfers of more than 255 bytes
-                assert!(bytes.len() < 256 && bytes.len() > 0);
-                assert!(buffer.len() < 256 && buffer.len() > 0);
-
-                // Wait for any previous address sequence to end automatically.
-                // This could be up to 50% of a bus cycle (ie. up to 0.5/freq)
-                while self.i2c.cr2.read().start().bit_is_set() {};
-
-                // Set START and prepare to send `bytes`.
-                // The START bit can be set even if the bus is BUSY or
-                // I2C is in slave mode.
-                self.i2c.cr2.write(|w| {
-                    w
-                        // Start transfer
-                        .start().set_bit()
-                        // Set number of bytes to transfer
-                        .nbytes().bits(bytes.len() as u8)
-                        // Set address to transfer to/from
-                        .sadd().bits((addr << 1) as u16)
-                        // 7-bit addressing mode
-                        .add10().clear_bit()
-                        // Set transfer direction to write
-                        .rd_wrn().clear_bit()
-                        // Software end mode
-                        .autoend().clear_bit()
-                });
-
-                for byte in bytes {
-                    // Wait until we are allowed to send data
-                    // (START has been ACKed or last byte went through)
-                    busy_wait!(self.i2c, txis, bit_is_set);
-
-                    // Put byte on the wire
-                    self.i2c.txdr.write(|w| { w.txdata().bits(*byte) });
-                }
-
-                // Wait until the write finishes before beginning to read.
-                busy_wait!(self.i2c, tc, bit_is_set);
-
-                // reSTART and prepare to receive bytes into `buffer`
-                self.i2c.cr2.write(|w| {
-                    w
-                        // Start transfer
-                        .start().set_bit()
-                        // Set number of bytes to transfer
-                        .nbytes().bits(buffer.len() as u8)
-                        // Set address to transfer to/from
-                        .sadd().bits((addr << 1) as u16)
-                        // 7-bit addressing mode
-                        .add10().clear_bit()
-                        // Set transfer direction to read
-                        .rd_wrn().set_bit()
-                        // Automatic end mode
-                        .autoend().set_bit()
-                });
-
-                for byte in buffer {
-                    // Wait until we have received something
-                    busy_wait!(self.i2c, rxne, bit_is_set);
-
-                    *byte = self.i2c.rxdr.read().rxdata().bits();
-                }
-
-                // automatic STOP
-
+                self.write_inner(addr as u16, false, bytes)?;
+                self.read_inner(addr as u16, false, buffer)?;
                 Ok(())
             }
         }
@@ -334,33 +423,7 @@ macro_rules! i2c {
             type Error = Error;
 
             fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error> {
-                assert!(bytes.len() < 256 && bytes.len() > 0);
-
-                self.i2c.cr2.modify(|_, w| {
-                    w
-                        // Start transfer
-                        .start().set_bit()
-                        // Set number of bytes to transfer
-                        .nbytes().bits(bytes.len() as u8)
-                        // Set address to transfer to/from
-                        .sadd().bits((addr << 1) as u16)
-                        // Set transfer direction to write
-                        .rd_wrn().clear_bit()
-                        // Automatic end mode
-                        .autoend().set_bit()
-                });
-
-                for byte in bytes {
-                    // Wait until we are allowed to send data
-                    // (START has been ACKed or last byte when through)
-                    busy_wait!(self.i2c, txis, bit_is_set);
-
-                    // Put byte on the wire
-                    self.i2c.txdr.write(|w| w.txdata().bits(*byte) );
-                }
-
-                // automatic STOP
-
+                self.write_inner(addr as u16, false, bytes)?;
                 Ok(())
             }
         }
@@ -369,43 +432,11 @@ macro_rules! i2c {
             type Error = Error;
 
             fn read(&mut self, addr: u8, bytes: &mut [u8]) -> Result<(), Self::Error> {
-                // TODO support transfers of more than 255 bytes
-                assert!(bytes.len() < 256 && bytes.len() > 0);
-
-                // Wait for any previous address sequence to end automatically.
-                // This could be up to 50% of a bus cycle (ie. up to 0.5/freq)
-                while self.i2c.cr2.read().start().bit_is_set() {};
-
-                // Set START and prepare to receive bytes into `buffer`.
-                // The START bit can be set even if the bus
-                // is BUSY or I2C is in slave mode.
-                self.i2c.cr2.modify(|_, w| {
-                    w
-                        // Start transfer
-                        .start().set_bit()
-                        // Set number of bytes to transfer
-                        .nbytes().bits(bytes.len() as u8)
-                        // Set address to transfer to/from
-                        .sadd().bits((addr << 1) as u16)
-                        // Set transfer direction to read
-                        .rd_wrn().set_bit()
-                        // automatic end mode
-                        .autoend().set_bit()
-                });
-
-                for byte in bytes {
-                    // Wait until we have received something
-                    busy_wait!(self.i2c, rxne, bit_is_set);
-
-                    *byte = self.i2c.rxdr.read().rxdata().bits();
-                }
-
-                // automatic STOP
-
+                self.read_inner(addr as u16, false, bytes)?;
                 Ok(())
             }
         }
-    };
+    }
 }
 
 i2c!(
diff --git a/src/lib.rs b/src/lib.rs
index d274d5ae..0590f854 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -29,10 +29,11 @@ extern crate bare_metal;
 extern crate void;
 
 pub extern crate cortex_m;
-pub extern crate embedded_hal as hal;
 pub extern crate nb;
 pub extern crate stm32g4;
 
+pub use embedded_hal as hal;
+pub use embedded_hal_old as hal_02;
 pub use nb::block;
 
 mod sealed {
diff --git a/src/prelude.rs b/src/prelude.rs
index 42b8dd28..afb06da5 100644
--- a/src/prelude.rs
+++ b/src/prelude.rs
@@ -1,9 +1,15 @@
-pub use hal::digital::v2::*;
-pub use hal::prelude::*;
+pub use embedded_hal::{
+    delay::DelayNs,
+    digital::{InputPin, OutputPin, StatefulOutputPin},
+    i2c::I2c,
+    pwm::SetDutyCycle,
+    spi::SpiBus,
+};
 
-pub use hal::adc::OneShot as _;
-pub use hal::watchdog::Watchdog as _;
-pub use hal::watchdog::WatchdogEnable as _;
+pub use embedded_hal_old::{
+    adc::OneShot as _,
+    watchdog::{Watchdog as _, WatchdogEnable as _},
+};
 
 // pub use crate::analog::adc::AdcExt as _;
 
diff --git a/src/pwm.rs b/src/pwm.rs
index 5f27211d..e25d8a82 100644
--- a/src/pwm.rs
+++ b/src/pwm.rs
@@ -172,7 +172,6 @@
 use core::marker::PhantomData;
 use core::mem::MaybeUninit;
 
-use crate::hal;
 use crate::stm32::LPTIMER1;
 use crate::stm32::RCC;
 #[cfg(any(
@@ -216,6 +215,8 @@ use crate::gpio::AF14;
 use crate::gpio::{gpioa::*, gpiob::*, gpioc::*, gpiod::*, gpioe::*, gpiof::*};
 use crate::gpio::{Alternate, AF1, AF10, AF11, AF12, AF2, AF3, AF4, AF5, AF6, AF9};
 
+use core::mem::size_of;
+
 // This trait marks that a GPIO pin can be used with a specific timer channel
 // TIM is the timer being used
 // CHANNEL is a marker struct for the channel (or multi channels for tuples)
@@ -1404,7 +1405,7 @@ macro_rules! tim_hal {
             $(
                 impl<PINS, CHANNEL, COMP> PwmBuilder<$TIMX, PINS, CHANNEL, FaultDisabled, COMP, $typ> {
                     /// Configure a break pin that will disable PWM when activated (active level based on polarity argument)
-                    /// Note: not all timers have fault inputs; FaultPins<TIM> is only implemented for valid pins/timers.
+                    /// Note: not all timers have fault inputs; `FaultPins<TIM>` is only implemented for valid pins/timers.
                     pub fn with_break_pin<P: FaultPins<$TIMX>>(self, _pin: P, polarity: Polarity) -> PwmBuilder<$TIMX, PINS, CHANNEL, FaultEnabled, COMP, $typ> {
                         PwmBuilder {
                             _tim: PhantomData,
@@ -1495,18 +1496,14 @@ macro_rules! tim_pin_hal {
         $ccrx:ident, $typ:ident $(,$ccxne:ident, $ccxnp:ident)*),)+
     ) => {
         $(
-            impl<COMP, POL, NPOL> hal::PwmPin for Pwm<$TIMX, $CH, COMP, POL, NPOL>
+            impl<COMP, POL, NPOL> Pwm<$TIMX, $CH, COMP, POL, NPOL>
                 where Pwm<$TIMX, $CH, COMP, POL, NPOL>: PwmPinEnable {
-                type Duty = $typ;
-
-                // You may not access self in the following methods!
-                // See unsafe above
 
-                fn disable(&mut self) {
+                pub fn disable(&mut self) {
                     self.ccer_disable();
                 }
 
-                fn enable(&mut self) {
+                pub fn enable(&mut self) {
                     let tim = unsafe { &*$TIMX::ptr() };
 
                     tim.$ccmrx_output().modify(|_, w|
@@ -1518,6 +1515,23 @@ macro_rules! tim_pin_hal {
 
                     self.ccer_enable();
                 }
+            }
+            impl<COMP, POL, NPOL> embedded_hal_old::PwmPin for Pwm<$TIMX, $CH, COMP, POL, NPOL>
+                where Pwm<$TIMX, $CH, COMP, POL, NPOL>: PwmPinEnable {
+                type Duty = $typ;
+
+                // You may not access self in the following methods!
+                // See unsafe above
+
+                #[inline]
+                fn disable(&mut self) {
+                    Pwm::<$TIMX, $CH, COMP, POL, NPOL>::disable(self)
+                }
+
+                #[inline]
+                fn enable(&mut self) {
+                    Pwm::<$TIMX, $CH, COMP, POL, NPOL>::enable(self)
+                }
 
                 fn get_duty(&self) -> Self::Duty {
                     let tim = unsafe { &*$TIMX::ptr() };
@@ -1540,8 +1554,7 @@ macro_rules! tim_pin_hal {
                     // In that case, 100% duty cycle is not possible, only 65535/65536
                     if arr == Self::Duty::MAX {
                         arr
-                    }
-                    else {
+                    } else {
                         arr + 1
                     }
                 }
@@ -1553,6 +1566,31 @@ macro_rules! tim_pin_hal {
                 }
             }
 
+            impl<COMP, POL, NPOL> embedded_hal::pwm::ErrorType for Pwm<$TIMX, $CH, COMP, POL, NPOL>
+                where Pwm<$TIMX, $CH, COMP, POL, NPOL>: PwmPinEnable {
+                type Error = core::convert::Infallible;
+            }
+            impl<COMP, POL, NPOL> embedded_hal::pwm::SetDutyCycle for Pwm<$TIMX, $CH, COMP, POL, NPOL>
+                where Pwm<$TIMX, $CH, COMP, POL, NPOL>: PwmPinEnable {
+                fn max_duty_cycle(&self) -> u16 {
+                    let tim = unsafe { &*$TIMX::ptr() };
+                    let arr = tim.arr.read().arr().bits() as $typ;
+                    let arr = (arr >> (8*(size_of::<$typ>() - size_of::<u16>()))) as u16;
+                    // see note above
+                    if arr == u16::MAX {
+                        arr
+                    } else {
+                        arr + 1
+                    }
+                }
+                fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
+                    // hal trait always has 16 bit resolution
+                    let duty = (duty as $typ) << (8*(size_of::<$typ>() - size_of::<u16>()));
+                    let tim = unsafe { &*$TIMX::ptr() };
+                    Ok(tim.$ccrx().write(|w| unsafe { w.ccr().bits(duty.into()) }))
+                }
+            }
+
             // Enable implementation for ComplementaryImpossible
             impl<POL, NPOL> PwmPinEnable for Pwm<$TIMX, $CH, ComplementaryImpossible, POL, NPOL> {
                 fn ccer_enable(&mut self) {
@@ -1823,7 +1861,7 @@ macro_rules! lptim_hal {
                 unsafe { MaybeUninit::<PINS::Channel>::uninit().assume_init() }
             }
 
-            impl hal::PwmPin for Pwm<$TIMX, C1, ComplementaryImpossible, ActiveHigh, ActiveHigh> {
+            impl embedded_hal_old::PwmPin for Pwm<$TIMX, C1, ComplementaryImpossible, ActiveHigh, ActiveHigh> {
                 type Duty = u16;
 
                 // You may not access self in the following methods!
@@ -1863,6 +1901,23 @@ macro_rules! lptim_hal {
                     tim.icr.write(|w| w.cmpokcf().set_bit());
                 }
             }
+
+            impl embedded_hal::pwm::ErrorType for Pwm<$TIMX, C1, ComplementaryImpossible, ActiveHigh, ActiveHigh> {
+                type Error = core::convert::Infallible;
+            }
+            impl embedded_hal::pwm::SetDutyCycle for Pwm<$TIMX, C1, ComplementaryImpossible, ActiveHigh, ActiveHigh> {
+                fn max_duty_cycle(&self) -> u16 {
+                    let tim = unsafe { &*$TIMX::ptr() };
+                    tim.arr.read().arr().bits()
+                }
+                fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
+                    let tim = unsafe { &*$TIMX::ptr() };
+
+                    tim.cmp.write(|w| unsafe { w.cmp().bits(duty) });
+                    while !tim.isr.read().cmpok().bit_is_set() {}
+                    Ok(tim.icr.write(|w| w.cmpokcf().set_bit()))
+                }
+            }
         )+
     }
 }
diff --git a/src/serial/usart.rs b/src/serial/usart.rs
index d5779131..f4a5dc12 100644
--- a/src/serial/usart.rs
+++ b/src/serial/usart.rs
@@ -6,16 +6,19 @@ use crate::dma::{
 };
 use crate::gpio::{gpioa::*, gpiob::*, gpioc::*, gpiod::*, gpioe::*, gpiog::*};
 use crate::gpio::{Alternate, AlternateOD, AF12, AF5, AF7, AF8};
-use crate::prelude::*;
 use crate::rcc::{Enable, GetBusFreq, Rcc, RccBus, Reset};
 use crate::stm32::*;
 
 use cortex_m::interrupt;
 use nb::block;
 
+use embedded_hal_old::serial::Write;
+use embedded_io::{ReadReady, WriteReady};
+
 use crate::serial::config::*;
 /// Serial error
 #[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
     /// Framing error
     Framing,
@@ -27,6 +30,17 @@ pub enum Error {
     Parity,
 }
 
+impl embedded_io::Error for Error {
+    fn kind(&self) -> embedded_io::ErrorKind {
+        match self {
+            Error::Framing => embedded_io::ErrorKind::InvalidData,
+            Error::Noise => embedded_io::ErrorKind::InvalidData,
+            Error::Overrun => embedded_io::ErrorKind::Other,
+            Error::Parity => embedded_io::ErrorKind::InvalidData,
+        }
+    }
+}
+
 /// Interrupt event
 pub enum Event {
     /// TXFIFO reaches the threshold
@@ -125,7 +139,7 @@ pub trait SerialExt<USART, Config> {
 
 impl<USART, TX, RX> fmt::Write for Serial<USART, TX, RX>
 where
-    Serial<USART, TX, RX>: hal::serial::Write<u8>,
+    Serial<USART, TX, RX>: embedded_hal_old::serial::Write<u8>,
 {
     fn write_str(&mut self, s: &str) -> fmt::Result {
         let _ = s.as_bytes().iter().map(|c| block!(self.write(*c))).last();
@@ -135,7 +149,7 @@ where
 
 impl<USART, Pin, Dma> fmt::Write for Tx<USART, Pin, Dma>
 where
-    Tx<USART, Pin, Dma>: hal::serial::Write<u8>,
+    Tx<USART, Pin, Dma>: embedded_hal_old::serial::Write<u8>,
 {
     fn write_str(&mut self, s: &str) -> fmt::Result {
         let _ = s.as_bytes().iter().map(|c| block!(self.write(*c))).last();
@@ -202,6 +216,29 @@ macro_rules! uart_shared {
                     _dma: PhantomData,
                 }
             }
+            fn data_ready(&mut self) -> nb::Result<(), Error> {
+                let usart = unsafe { &(*$USARTX::ptr()) };
+                let isr = usart.isr.read();
+                Err(
+                    if isr.pe().bit_is_set() {
+                        usart.icr.write(|w| w.pecf().set_bit());
+                        nb::Error::Other(Error::Parity)
+                    } else if isr.fe().bit_is_set() {
+                        usart.icr.write(|w| w.fecf().set_bit());
+                        nb::Error::Other(Error::Framing)
+                    } else if isr.nf().bit_is_set() {
+                        usart.icr.write(|w| w.ncf().set_bit());
+                        nb::Error::Other(Error::Noise)
+                    } else if isr.ore().bit_is_set() {
+                        usart.icr.write(|w| w.orecf().set_bit());
+                        nb::Error::Other(Error::Overrun)
+                    } else if isr.rxne().bit_is_set() {
+                        return Ok(())
+                    } else {
+                        nb::Error::WouldBlock
+                    }
+                )
+            }
         }
 
         impl<Pin> Rx<$USARTX, Pin, DMA> {
@@ -220,35 +257,16 @@ macro_rules! uart_shared {
             }
         }
 
-        impl<Pin> hal::serial::Read<u8> for Rx<$USARTX, Pin, NoDMA> {
+        impl<Pin> embedded_hal_old::serial::Read<u8> for Rx<$USARTX, Pin, NoDMA> {
             type Error = Error;
 
             fn read(&mut self) -> nb::Result<u8, Error> {
                 let usart = unsafe { &(*$USARTX::ptr()) };
-                let isr = usart.isr.read();
-                Err(
-                    if isr.pe().bit_is_set() {
-                        usart.icr.write(|w| w.pecf().set_bit());
-                        nb::Error::Other(Error::Parity)
-                    } else if isr.fe().bit_is_set() {
-                        usart.icr.write(|w| w.fecf().set_bit());
-                        nb::Error::Other(Error::Framing)
-                    } else if isr.nf().bit_is_set() {
-                        usart.icr.write(|w| w.ncf().set_bit());
-                        nb::Error::Other(Error::Noise)
-                    } else if isr.ore().bit_is_set() {
-                        usart.icr.write(|w| w.orecf().set_bit());
-                        nb::Error::Other(Error::Overrun)
-                    } else if isr.rxne().bit_is_set() {
-                        return Ok(usart.rdr.read().bits() as u8)
-                    } else {
-                        nb::Error::WouldBlock
-                    }
-                )
+                self.data_ready().map(|_| usart.rdr.read().bits() as u8)
             }
         }
 
-        impl<TX, RX> hal::serial::Read<u8> for Serial<$USARTX, TX, RX> {
+        impl<TX, RX> embedded_hal_old::serial::Read<u8> for Serial<$USARTX, TX, RX> {
             type Error = Error;
 
             fn read(&mut self) -> nb::Result<u8, Error> {
@@ -314,7 +332,7 @@ macro_rules! uart_shared {
             }
         }
 
-        impl<Pin> hal::serial::Write<u8> for Tx<$USARTX, Pin, NoDMA> {
+        impl<Pin> embedded_hal_old::serial::Write<u8> for Tx<$USARTX, Pin, NoDMA> {
             type Error = Error;
 
             fn flush(&mut self) -> nb::Result<(), Self::Error> {
@@ -337,7 +355,7 @@ macro_rules! uart_shared {
             }
         }
 
-        impl<TX, RX> hal::serial::Write<u8> for Serial<$USARTX, TX, RX> {
+        impl<TX, RX> embedded_hal_old::serial::Write<u8> for Serial<$USARTX, TX, RX> {
             type Error = Error;
 
             fn flush(&mut self) -> nb::Result<(), Self::Error> {
@@ -349,6 +367,91 @@ macro_rules! uart_shared {
             }
         }
 
+        impl<Pin> embedded_io::ErrorType for Tx<$USARTX, Pin, NoDMA> {
+            type Error = Error;
+        }
+        impl<Pin> WriteReady for Tx<$USARTX, Pin, NoDMA> {
+            fn write_ready(&mut self) -> Result<bool, Self::Error> {
+                let usart = unsafe { &(*$USARTX::ptr()) };
+                Ok(usart.isr.read().txe().bit_is_set())
+            }
+        }
+        // writes until fifo (or tdr) is full
+        impl<Pin> embedded_io::Write for Tx<$USARTX, Pin, NoDMA> {
+            fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
+                if buf.len() == 0 { return Ok(0) }
+                let usart = unsafe { &(*$USARTX::ptr()) };
+                while !self.write_ready()? {
+                    core::hint::spin_loop()
+                }
+                // can't know fifo capacity in advance
+                let count = buf.into_iter()
+                    .take_while(|_| usart.isr.read().txe().bit_is_set())
+                    .map(|b| usart.tdr.write(|w| unsafe { w.tdr().bits(*b as u16) }))
+                    .count();
+
+                Ok(count)
+            }
+            fn flush(&mut self) -> Result<(), Error> {
+                nb::block!(embedded_hal_old::serial::Write::<u8>::flush(self))
+            }
+        }
+
+        impl<Pin> embedded_io::ErrorType for Rx<$USARTX, Pin, NoDMA> {
+            type Error = Error;
+        }
+        impl<Pin> ReadReady for Rx<$USARTX, Pin, NoDMA> {
+            fn read_ready(&mut self) -> Result<bool, Self::Error> {
+                match self.data_ready() {
+                    Ok(()) => Ok(true),
+                    Err(nb::Error::WouldBlock) => Ok(false),
+                    Err(nb::Error::Other(e)) => Err(e),
+                }
+            }
+        }
+        impl<Pin> embedded_io::Read for Rx<$USARTX, Pin, NoDMA> {
+            fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
+                if buf.len() == 0 { return Ok(0) }
+                let usart = unsafe { &(*$USARTX::ptr()) };
+                let mut count = 0;
+
+                while !self.read_ready()? {
+                    core::hint::spin_loop()
+                }
+                while self.read_ready()? && count < buf.len() {
+                    buf[count] = usart.rdr.read().bits() as u8;
+                    count += 1
+                }
+                Ok(count)
+            }
+        }
+
+        impl<TX, RX> embedded_io::ErrorType for Serial<$USARTX, TX, RX> {
+            type Error = Error;
+        }
+        impl<TX, RX> WriteReady for Serial<$USARTX, TX, RX> {
+            fn write_ready(&mut self) -> Result<bool, Self::Error> {
+                self.tx.write_ready()
+            }
+        }
+        impl<TX, RX> embedded_io::Write for Serial<$USARTX, TX, RX> {
+            fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
+                embedded_io::Write::write(&mut self.tx, buf)
+            }
+            fn flush(&mut self) -> Result<(), Error> {
+                embedded_io::Write::flush(&mut self.tx)
+            }
+        }
+        impl<TX, RX> ReadReady for Serial<$USARTX, TX, RX> {
+            fn read_ready(&mut self) -> Result<bool, Self::Error> {
+                self.rx.read_ready()
+            }
+        }
+        impl<TX, RX> embedded_io::Read for Serial<$USARTX, TX, RX> {
+            fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
+                embedded_io::Read::read(&mut self.rx, buf)
+            }
+        }
 
         impl<TX, RX> Serial<$USARTX, TX, RX> {
 
diff --git a/src/spi.rs b/src/spi.rs
index 78cda675..c08e66fa 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -24,7 +24,8 @@ use crate::time::Hertz;
 use core::cell::UnsafeCell;
 use core::ptr;
 
-pub use hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
+use embedded_hal::spi::ErrorKind;
+pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
 
 /// SPI error
 #[derive(Debug)]
@@ -37,6 +38,16 @@ pub enum Error {
     Crc,
 }
 
+impl embedded_hal::spi::Error for Error {
+    fn kind(&self) -> ErrorKind {
+        match self {
+            Self::Overrun => ErrorKind::Overrun,
+            Self::ModeFault => ErrorKind::ModeFault,
+            Self::Crc => ErrorKind::Other,
+        }
+    }
+}
+
 /// A filler type for when the SCK pin is unnecessary
 pub struct NoSck;
 /// A filler type for when the Miso pin is unnecessary
@@ -73,6 +84,17 @@ pub trait SpiExt<SPI>: Sized {
         T: Into<Hertz>;
 }
 
+pub trait FrameSize: Copy + Default {
+    const DFF: bool;
+}
+
+impl FrameSize for u8 {
+    const DFF: bool = false;
+}
+impl FrameSize for u16 {
+    const DFF: bool = true;
+}
+
 macro_rules! spi {
     ($SPIX:ident, $spiX:ident,
         sck: [ $($( #[ $pmetasck:meta ] )* $SCK:ty,)+ ],
@@ -181,22 +203,9 @@ macro_rules! spi {
             }
         }
 
-        impl SpiExt<$SPIX> for $SPIX {
-            fn spi<PINS, T>(self, pins: PINS, mode: Mode, freq: T, rcc: &mut Rcc) -> Spi<$SPIX, PINS>
-            where
-                PINS: Pins<$SPIX>,
-                T: Into<Hertz>
-                {
-                    Spi::$spiX(self, pins, mode, freq, rcc)
-                }
-        }
-
-        impl<PINS> hal::spi::FullDuplex<u8> for Spi<$SPIX, PINS> {
-            type Error = Error;
-
-            fn read(&mut self) -> nb::Result<u8, Error> {
+        impl<PINS> Spi<$SPIX, PINS> {
+            fn nb_read<W: FrameSize>(&mut self) -> nb::Result<W, Error> {
                 let sr = self.spi.sr.read();
-
                 Err(if sr.ovr().bit_is_set() {
                     nb::Error::Other(Error::Overrun)
                 } else if sr.modf().bit_is_set() {
@@ -207,16 +216,14 @@ macro_rules! spi {
                     // NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
                     // reading a half-word)
                     return Ok(unsafe {
-                        ptr::read_volatile(&self.spi.dr as *const _ as *const u8)
+                        ptr::read_volatile(&self.spi.dr as *const _ as *const W)
                     });
                 } else {
                     nb::Error::WouldBlock
                 })
             }
-
-            fn send(&mut self, byte: u8) -> nb::Result<(), Error> {
+            fn nb_write<W: FrameSize>(&mut self, word: W) -> nb::Result<(), Error> {
                 let sr = self.spi.sr.read();
-
                 Err(if sr.ovr().bit_is_set() {
                     nb::Error::Other(Error::Overrun)
                 } else if sr.modf().bit_is_set() {
@@ -224,14 +231,131 @@ macro_rules! spi {
                 } else if sr.crcerr().bit_is_set() {
                     nb::Error::Other(Error::Crc)
                 } else if sr.txe().bit_is_set() {
-                    let dr = &self.spi.dr as *const _ as *const UnsafeCell<u8>;
+                    let dr = &self.spi.dr as *const _ as *const UnsafeCell<W>;
                     // NOTE(write_volatile) see note above
-                    unsafe { ptr::write_volatile(UnsafeCell::raw_get(dr), byte) };
+                    unsafe { ptr::write_volatile(UnsafeCell::raw_get(dr), word) };
                     return Ok(());
                 } else {
                     nb::Error::WouldBlock
                 })
             }
+            fn set_tx_only(&mut self) {
+                self.spi
+                    .cr1
+                    .modify(|_, w| w.bidimode().set_bit().bidioe().set_bit());
+            }
+            fn set_bidi(&mut self) {
+                self.spi
+                    .cr1
+                    .modify(|_, w| w.bidimode().clear_bit().bidioe().clear_bit());
+            }
+        }
+
+        impl SpiExt<$SPIX> for $SPIX {
+            fn spi<PINS, T>(self, pins: PINS, mode: Mode, freq: T, rcc: &mut Rcc) -> Spi<$SPIX, PINS>
+            where
+                PINS: Pins<$SPIX>,
+                T: Into<Hertz>
+                {
+                    Spi::$spiX(self, pins, mode, freq, rcc)
+                }
+        }
+
+        impl<PINS> embedded_hal::spi::ErrorType for Spi<$SPIX, PINS> {
+            type Error = Error;
+        }
+
+        impl<PINS> embedded_hal::spi::SpiBus<u8> for Spi<$SPIX, PINS> {
+            fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+                if words.len() == 0 { return Ok(()) }
+                // clear tx-only status in the case the previous operation was a write
+                self.set_bidi();
+                // prefill write fifo so that the clock doen't stop while fetch the read byte
+                // one frame should be enough?
+                nb::block!(self.nb_write(0u8))?;
+                let len = words.len();
+                for w in words[..len-1].iter_mut() {
+                    // TODO: 16 bit frames, bidirectional pins
+                    nb::block!(self.nb_write(0u8))?;
+                    *w = nb::block!(self.nb_read())?;
+                }
+                // safety: length > 0 checked at start of function
+                *words.last_mut().unwrap() = nb::block!(self.nb_read())?;
+                Ok(())
+            }
+
+            fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+                self.set_tx_only();
+                Ok(for w in words {
+                    nb::block!(self.nb_write(*w))?
+                })
+            }
+
+            fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
+                if read.len() == 0 {
+                    return self.write(write)
+                } else if write.len() == 0 {
+                    return self.read(read)
+                }
+
+                self.set_bidi();
+                // same prefill as in read, this time with actual data
+                nb::block!(self.nb_write(write[0]))?;
+                let common_len = core::cmp::min(read.len(), write.len());
+                // take 1 less because write skips the first element
+                let zipped = read.iter_mut().zip(write.into_iter().skip(1)).take(common_len - 1);
+                for (r, w) in zipped {
+                    nb::block!(self.nb_write(*w))?;
+                    *r = nb::block!(self.nb_read())?;
+                }
+                read[common_len-1] = nb::block!(self.nb_read())?;
+
+                if read.len() > common_len {
+                    self.read(&mut read[common_len..])
+                } else {
+                    self.write(&write[common_len..])
+                }
+            }
+            fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+                if words.len() == 0 { return Ok(()) }
+                self.set_bidi();
+                nb::block!(self.nb_write(words[0]))?;
+                let cells = core::cell::Cell::from_mut(words).as_slice_of_cells();
+
+                for rw in cells.windows(2) {
+                    let r = &rw[0];
+                    let w = &rw[1];
+
+                    nb::block!(self.nb_write(w.get()))?;
+                    r.set(nb::block!(self.nb_read())?);
+                }
+                *words.last_mut().unwrap() = nb::block!(self.nb_read())?;
+                Ok(())
+            }
+            fn flush(&mut self) -> Result<(), Self::Error> {
+                // stop receiving data
+                self.set_tx_only();
+                // wait for tx fifo to be drained by the peripheral
+                while self.spi.sr.read().ftlvl() != 0 { core::hint::spin_loop() };
+                // drain rx fifo
+                Ok(while match self.nb_read::<u8>() {
+                    Ok(_) => true,
+                    Err(nb::Error::WouldBlock) => false,
+                    Err(nb::Error::Other(e)) => return Err(e)
+                } { core::hint::spin_loop() })
+            }
+        }
+
+        impl<PINS> embedded_hal_old::spi::FullDuplex<u8> for Spi<$SPIX, PINS> {
+            type Error = Error;
+
+            fn read(&mut self) -> nb::Result<u8, Error> {
+                self.nb_read()
+            }
+
+            fn send(&mut self, byte: u8) -> nb::Result<(), Error> {
+                self.nb_write(byte)
+            }
         }
         unsafe impl<Pin> TargetAddress<MemoryToPeripheral> for Spi<$SPIX, Pin> {
             #[inline(always)]
@@ -246,9 +370,9 @@ macro_rules! spi {
         }
 
 
-        impl<PINS> ::hal::blocking::spi::transfer::Default<u8> for Spi<$SPIX, PINS> {}
+        impl<PINS> embedded_hal_old::blocking::spi::transfer::Default<u8> for Spi<$SPIX, PINS> {}
 
-        impl<PINS> ::hal::blocking::spi::write::Default<u8> for Spi<$SPIX, PINS> {}
+        impl<PINS> embedded_hal_old::blocking::spi::write::Default<u8> for Spi<$SPIX, PINS> {}
     }
 }
 
diff --git a/src/time.rs b/src/time.rs
index 98a44a31..29dd234d 100644
--- a/src/time.rs
+++ b/src/time.rs
@@ -101,17 +101,22 @@ impl U32Ext for u32 {
     }
 }
 
-pub fn duration(hz: Hertz, cycles: u32) -> MicroSecond {
+/// Converts clock cycles at a given frequency into a Duration with arbitrary fraction
+pub fn duration<const NOM: u32, const DENOM: u32>(
+    hz: Hertz,
+    cycles: u32,
+) -> Duration<u32, NOM, DENOM> {
     let cycles = cycles as u64;
     let clk = hz.raw() as u64;
-    let us = cycles.saturating_mul(1_000_000_u64) / clk;
-    MicroSecond::from_ticks(us as u32)
+    let duration_ticks = cycles.saturating_mul(DENOM as u64) / clk / NOM as u64;
+    Duration::<u32, NOM, DENOM>::from_ticks(duration_ticks as u32)
 }
 
-pub fn cycles(ms: MicroSecond, clk: Hertz) -> u32 {
+/// Converts a Duration with arbitrary fraction into a number of cycles at the specified frequency
+pub fn cycles<const NOM: u32, const DENOM: u32>(ms: Duration<u32, NOM, DENOM>, clk: Hertz) -> u32 {
     assert!(ms.ticks() > 0);
     let clk = clk.raw() as u64;
     let period = ms.ticks() as u64;
-    let cycles = clk.saturating_mul(period) / 1_000_000_u64;
+    let cycles = clk.saturating_mul(period).saturating_mul(NOM as u64) / DENOM as u64;
     cycles as u32
 }
diff --git a/src/timer.rs b/src/timer.rs
index b3d72267..ff0ff892 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -3,11 +3,11 @@
 //! Pins can be used for PWM output in both push-pull mode (`Alternate`) and open-drain mode
 //! (`AlternateOD`).
 
-use crate::delay::CountDown;
+use crate::delay::{CountDown, DelayFromCountDownTimer};
 use cast::{u16, u32};
 use cortex_m::peripheral::syst::SystClkSource;
 use cortex_m::peripheral::{DCB, DWT, SYST};
-use embedded_hal::timer::{Cancel, CountDown as _, Periodic};
+use embedded_hal_old::timer::{Cancel, CountDown as _, Periodic};
 use void::Void;
 
 use crate::stm32::RCC;
@@ -108,7 +108,7 @@ impl CountDownTimer<SYST> {
     }
 }
 
-impl embedded_hal::timer::CountDown for CountDownTimer<SYST> {
+impl embedded_hal_old::timer::CountDown for CountDownTimer<SYST> {
     type Time = MicroSecond;
 
     fn start<T>(&mut self, timeout: T)
@@ -287,9 +287,13 @@ macro_rules! hal {
                     self.tim.cr1.modify(|_, w| w.cen().clear_bit());
                     self.tim
                 }
+
+                pub fn delay(self) -> DelayFromCountDownTimer<Self> {
+                    DelayFromCountDownTimer::new(self)
+                }
             }
 
-            impl embedded_hal::timer::CountDown for CountDownTimer<$TIM> {
+            impl embedded_hal_old::timer::CountDown for CountDownTimer<$TIM> {
                 type Time = MicroSecond;
 
                 fn start<T>(&mut self, timeout: T)