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[F1] Update STM32F1xx CMSIS Drivers to v4.3.2
Included in STM32CubeF1 FW v1.8.2 Signed-off-by: Frederic Pillon <[email protected]>
1 parent d3a4388 commit b720ec5

22 files changed

+2453
-1056
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h

+8-11
Original file line numberDiff line numberDiff line change
@@ -4880,7 +4880,6 @@ typedef struct
48804880
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
48814881

48824882

4883-
48844883
/******************************************************************************/
48854884
/* */
48864885
/* Inter-integrated Circuit Interface */
@@ -5718,8 +5717,6 @@ typedef struct
57185717
((INSTANCE) == TIM4) || \
57195718
((INSTANCE) == TIM15))
57205719

5721-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
5722-
57235720
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
57245721
(((INSTANCE) == TIM1) || \
57255722
((INSTANCE) == TIM2) || \
@@ -5921,31 +5918,31 @@ typedef struct
59215918
#define ADC1_2_IRQn ADC1_IRQn
59225919
#define USBWakeUp_IRQn CEC_IRQn
59235920
#define OTG_FS_WKUP_IRQn CEC_IRQn
5924-
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
5925-
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
59265921
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
5927-
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
5922+
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
5923+
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
59285924
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
59295925
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
5926+
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
5927+
#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
59305928
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
59315929
#define TIM10_IRQn TIM1_UP_TIM16_IRQn
5932-
#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
59335930
#define TIM6_IRQn TIM6_DAC_IRQn
59345931

59355932

59365933
/* Aliases for __IRQHandler */
59375934
#define ADC1_2_IRQHandler ADC1_IRQHandler
59385935
#define USBWakeUp_IRQHandler CEC_IRQHandler
59395936
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
5940-
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
5941-
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
59425937
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
5943-
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
5938+
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
5939+
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
59445940
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
59455941
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
5942+
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
5943+
#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
59465944
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
59475945
#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
5948-
#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
59495946
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
59505947

59515948

‎system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h

+8-11
Original file line numberDiff line numberDiff line change
@@ -5394,7 +5394,6 @@ typedef struct
53945394
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
53955395

53965396

5397-
53985397
/******************************************************************************/
53995398
/* */
54005399
/* Inter-integrated Circuit Interface */
@@ -6283,8 +6282,6 @@ typedef struct
62836282
((INSTANCE) == TIM12) || \
62846283
((INSTANCE) == TIM15))
62856284

6286-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
6287-
62886285
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
62896286
(((INSTANCE) == TIM1) || \
62906287
((INSTANCE) == TIM2) || \
@@ -6522,17 +6519,17 @@ typedef struct
65226519

65236520
/* Aliases for __IRQn */
65246521
#define ADC1_2_IRQn ADC1_IRQn
6525-
#define USBWakeUp_IRQn CEC_IRQn
65266522
#define OTG_FS_WKUP_IRQn CEC_IRQn
6523+
#define USBWakeUp_IRQn CEC_IRQn
65276524
#define TIM8_BRK_IRQn TIM12_IRQn
65286525
#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
6529-
#define TIM8_UP_TIM13_IRQn TIM13_IRQn
65306526
#define TIM8_UP_IRQn TIM13_IRQn
6531-
#define TIM8_TRG_COM_IRQn TIM14_IRQn
6527+
#define TIM8_UP_TIM13_IRQn TIM13_IRQn
65326528
#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
6529+
#define TIM8_TRG_COM_IRQn TIM14_IRQn
65336530
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
6534-
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
65356531
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
6532+
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
65366533
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
65376534
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
65386535
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
@@ -6544,17 +6541,17 @@ typedef struct
65446541

65456542
/* Aliases for __IRQHandler */
65466543
#define ADC1_2_IRQHandler ADC1_IRQHandler
6547-
#define USBWakeUp_IRQHandler CEC_IRQHandler
65486544
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
6545+
#define USBWakeUp_IRQHandler CEC_IRQHandler
65496546
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
65506547
#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
6551-
#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
65526548
#define TIM8_UP_IRQHandler TIM13_IRQHandler
6553-
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
6549+
#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
65546550
#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
6551+
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
65556552
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
6556-
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
65576553
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
6554+
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
65586555
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
65596556
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
65606557
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler

‎system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h

-4
Original file line numberDiff line numberDiff line change
@@ -4412,12 +4412,10 @@ typedef struct
44124412
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
44134413
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
44144414

4415-
/****************** Bit definition for SPI_I2SCFGR register *****************/
44164415
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
44174416
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
44184417
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
44194418

4420-
44214419
/******************************************************************************/
44224420
/* */
44234421
/* Inter-integrated Circuit Interface */
@@ -5170,8 +5168,6 @@ typedef struct
51705168
(((INSTANCE) == TIM2) || \
51715169
((INSTANCE) == TIM3))
51725170

5173-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
5174-
51755171
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
51765172
(((INSTANCE) == TIM2) || \
51775173
((INSTANCE) == TIM3))

‎system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h

-4
Original file line numberDiff line numberDiff line change
@@ -4474,12 +4474,10 @@ typedef struct
44744474
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
44754475
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
44764476

4477-
/****************** Bit definition for SPI_I2SCFGR register *****************/
44784477
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
44794478
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
44804479
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
44814480

4482-
44834481
/******************************************************************************/
44844482
/* */
44854483
/* Inter-integrated Circuit Interface */
@@ -5279,8 +5277,6 @@ typedef struct
52795277
((INSTANCE) == TIM3) || \
52805278
((INSTANCE) == TIM4))
52815279

5282-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
5283-
52845280
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
52855281
(((INSTANCE) == TIM2) || \
52865282
((INSTANCE) == TIM3) || \

‎system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h

+52-3
Original file line numberDiff line numberDiff line change
@@ -514,6 +514,7 @@ typedef struct
514514
__IO uint32_t RXCRCR;
515515
__IO uint32_t TXCRCR;
516516
__IO uint32_t I2SCFGR;
517+
__IO uint32_t I2SPR;
517518
} SPI_TypeDef;
518519

519520
/**
@@ -5283,6 +5284,10 @@ typedef struct
52835284
/* Serial Peripheral Interface */
52845285
/* */
52855286
/******************************************************************************/
5287+
/*
5288+
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
5289+
*/
5290+
#define SPI_I2S_SUPPORT /*!< I2S support */
52865291
#define SPI_CRC_ERROR_WORKAROUND_FEATURE
52875292

52885293
/******************* Bit definition for SPI_CR1 register ********************/
@@ -5401,10 +5406,52 @@ typedef struct
54015406
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
54025407

54035408
/****************** Bit definition for SPI_I2SCFGR register *****************/
5409+
#define SPI_I2SCFGR_CHLEN_Pos (0U)
5410+
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
5411+
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */
5412+
5413+
#define SPI_I2SCFGR_DATLEN_Pos (1U)
5414+
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
5415+
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */
5416+
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
5417+
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
5418+
5419+
#define SPI_I2SCFGR_CKPOL_Pos (3U)
5420+
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
5421+
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */
5422+
5423+
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
5424+
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
5425+
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */
5426+
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
5427+
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
5428+
5429+
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
5430+
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
5431+
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */
5432+
5433+
#define SPI_I2SCFGR_I2SCFG_Pos (8U)
5434+
#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
5435+
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */
5436+
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
5437+
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
5438+
5439+
#define SPI_I2SCFGR_I2SE_Pos (10U)
5440+
#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
5441+
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */
54045442
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
54055443
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
54065444
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
5407-
5445+
/****************** Bit definition for SPI_I2SPR register *******************/
5446+
#define SPI_I2SPR_I2SDIV_Pos (0U)
5447+
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
5448+
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */
5449+
#define SPI_I2SPR_ODD_Pos (8U)
5450+
#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
5451+
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */
5452+
#define SPI_I2SPR_MCKOE_Pos (9U)
5453+
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
5454+
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */
54085455

54095456
/******************************************************************************/
54105457
/* */
@@ -6153,6 +6200,10 @@ typedef struct
61536200
/******************************* SMBUS Instances ******************************/
61546201
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
61556202

6203+
/******************************** I2S Instances *******************************/
6204+
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
6205+
((INSTANCE) == SPI3))
6206+
61566207
/****************************** IWDG Instances ********************************/
61576208
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
61586209

@@ -6253,8 +6304,6 @@ typedef struct
62536304
((INSTANCE) == TIM4) || \
62546305
((INSTANCE) == TIM5))
62556306

6256-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
6257-
62586307
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
62596308
(((INSTANCE) == TIM2) || \
62606309
((INSTANCE) == TIM3) || \

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