diff --git a/.github/workflows/build-arduino-esp.yml b/.github/workflows/build-arduino-esp.yml new file mode 100644 index 00000000..c9b49ee6 --- /dev/null +++ b/.github/workflows/build-arduino-esp.yml @@ -0,0 +1,46 @@ +name: Build Arduino ESP Examples + +on: + push: + branches: ["main"] + pull_request: + branches: ["main"] + schedule: + # Build on Mondays at 9am PST every week + - cron: '0 17 * * 1' + +jobs: + build-arduino-esp: + runs-on: ubuntu-24.04 + container: espressif/idf:v5.4 + strategy: + fail-fast: false + matrix: + example: [arduino-esp32-led-blink-sdk, arduino-esp32-wifi-scan-sdk] + swift: [swift-DEVELOPMENT-SNAPSHOT-2025-03-17-a] + + steps: + - name: Checkout repo + uses: actions/checkout@v4 + + - name: Install apt dependencies + run: | + apt-get -qq update + apt-get -qq -y install pkg-config libstdc++6 + + - name: Install ${{ matrix.swift }} + run: | + wget -q https://download.swift.org/development/ubuntu2404/${{ matrix.swift }}/${{ matrix.swift }}-ubuntu24.04.tar.gz + tar xzf ${{ matrix.swift }}-ubuntu24.04.tar.gz + export PATH="`pwd`/${{ matrix.swift }}-ubuntu24.04/usr/bin/:$PATH" + echo "PATH=$PATH" >> $GITHUB_ENV + swiftc --version + + - name: Build ${{ matrix.example }} + run: | + cd $IDF_PATH + . ./export.sh + cd - + cd ${{ matrix.example }} + idf.py set-target esp32c6 + idf.py build diff --git a/.github/workflows/build-esp.yml b/.github/workflows/build-esp.yml deleted file mode 100644 index 34325add..00000000 --- a/.github/workflows/build-esp.yml +++ /dev/null @@ -1,38 +0,0 @@ -name: ESP - -on: - push: - branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] - workflow_dispatch: - -jobs: - build: - name: Build - runs-on: ubuntu-24.04 - container: espressif/idf:latest - - strategy: - fail-fast: false - matrix: - example: [esp32-led-blink-sdk, esp32-led-strip-sdk] - - steps: - - name: Checkout repo - uses: actions/checkout@v4 - - - name: Install apt dependencies - run: apt-get -qq update && apt-get -qq -y install pkg-config - - - name: Install Swift - uses: ./.github/actions/install-swift - - - name: Build ${{ matrix.example }} - run: | - cd $IDF_PATH - . ./export.sh - cd - - cd ${{ matrix.example }} - idf.py set-target esp32c6 - idf.py build diff --git a/.github/workflows/build-nuttx.yml b/.github/workflows/build-nuttx.yml deleted file mode 100644 index 554cd5f7..00000000 --- a/.github/workflows/build-nuttx.yml +++ /dev/null @@ -1,58 +0,0 @@ -name: NuttX - -on: - push: - branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] - workflow_dispatch: - -jobs: - build: - name: Build - runs-on: ubuntu-24.04 - - strategy: - fail-fast: false - matrix: - example: [nuttx-riscv-blink] - - steps: - - name: Checkout repo - uses: actions/checkout@v4 - - - name: Install apt dependencies - run: | - sudo apt-get -qq update && sudo apt-get -qq -y install \ - bison flex gettext texinfo libncurses5-dev libncursesw5-dev \ - gperf automake libtool pkg-config build-essential gperf genromfs \ - libgmp-dev libmpc-dev libmpfr-dev libisl-dev binutils-dev libelf-dev \ - libexpat-dev gcc-multilib g++-multilib u-boot-tools util-linux \ - kconfig-frontends ninja-build - - - name: Install CMake 3.30.2 - run: | - ARCH=`uname -m` - curl -sL https://github.com/Kitware/CMake/releases/download/v3.30.2/cmake-3.30.2-linux-$ARCH.tar.gz -O - tar xzf cmake-3.30.2-linux-$ARCH.tar.gz - export PATH="`pwd`/cmake-3.30.2-linux-$ARCH/bin:$PATH" - echo "PATH=$PATH" >> $GITHUB_ENV - cmake --version - - - name: Install RISC-V toolchain - run: | - mkdir -p riscv-none-elf-gcc && \ - curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz" \ - | tar -C riscv-none-elf-gcc --strip-components 1 -xz - export PATH="$PATH:`pwd`/riscv-none-elf-gcc/bin/" - echo "PATH=$PATH" >> $GITHUB_ENV - riscv-none-elf-gcc --version - - - name: Install Swift - uses: ./.github/actions/install-swift - - - name: Build ${{ matrix.example }} - working-directory: ${{ matrix.example }} - run: | - cmake -B build -GNinja -DBOARD_CONFIG=rv-virt:leds_swift -DENABLE_NUTTX_TRACE=ON - cmake --build build diff --git a/.github/workflows/build-rpi-baremetal.yml b/.github/workflows/build-rpi-baremetal.yml deleted file mode 100644 index eadc725d..00000000 --- a/.github/workflows/build-rpi-baremetal.yml +++ /dev/null @@ -1,32 +0,0 @@ -name: Raspberry Pi Baremetal - -on: - push: - branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] - workflow_dispatch: - -jobs: - build: - name: Build - runs-on: ubuntu-24.04 - - strategy: - fail-fast: false - matrix: - example: [rpi-4b-blink, rpi-5-blink] - - steps: - - name: Checkout repo - uses: actions/checkout@v4 - - - name: Install apt dependencies - run: sudo apt-get -qq update && sudo apt-get -qq -y install make llvm - - - name: Install Swift - uses: ./.github/actions/install-swift - - - name: Build ${{ matrix.example }} - working-directory: ${{ matrix.example }} - run: make diff --git a/.github/workflows/build-rpi-pico-sdk.yml b/.github/workflows/build-rpi-pico-sdk.yml deleted file mode 100644 index 258c65c3..00000000 --- a/.github/workflows/build-rpi-pico-sdk.yml +++ /dev/null @@ -1,77 +0,0 @@ -name: Raspberry Pi Pico SDK - -on: - push: - branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] - workflow_dispatch: - -jobs: - build: - name: Build - runs-on: ubuntu-24.04 - - strategy: - fail-fast: false - matrix: - example: - - name: rpi-pico-blink-sdk - board: pico - - name: rpi-picow-blink-sdk - board: pico_w - - name: harmony - board: pico_w - - steps: - - name: Checkout repo - uses: actions/checkout@v4 - - - name: Install apt dependencies - run: sudo apt-get -qq update && sudo apt-get -qq -y install curl ninja-build python3 - - - name: Install CMake 3.30.2 - run: | - ARCH=`uname -m` - curl -sL https://github.com/Kitware/CMake/releases/download/v3.30.2/cmake-3.30.2-linux-$ARCH.tar.gz -O - tar xzf cmake-3.30.2-linux-$ARCH.tar.gz - export PATH="`pwd`/cmake-3.30.2-linux-$ARCH/bin:$PATH" - echo "PATH=$PATH" >> $GITHUB_ENV - cmake --version - - - name: Install GNU ARM toolchain - run: | - ARCH=`uname -m` - curl -sL https://developer.arm.com/-/media/Files/downloads/gnu/14.2.rel1/binrel/arm-gnu-toolchain-14.2.rel1-$ARCH-arm-none-eabi.tar.xz -O - tar xf arm-gnu-toolchain-14.2.rel1-$ARCH-arm-none-eabi.tar.xz - - - name: Install Swift - uses: ./.github/actions/install-swift - - - name: Clone Pico SDK - run: | - git clone https://github.com/raspberrypi/pico-sdk.git - cd pico-sdk - git submodule update --init --recursive - cd .. - - - name: Clone Pico Extras - run: | - git clone https://github.com/raspberrypi/pico-extras.git - cd pico-extras - git submodule update --init --recursive - cd .. - - - name: Set Pico environment variables - run: | - ARCH=`uname -m` - echo "PICO_BOARD=${{ matrix.example.board }}" >> $GITHUB_ENV - echo "PICO_SDK_PATH=`pwd`/pico-sdk" >> $GITHUB_ENV - echo "PICO_EXTRAS_PATH=`pwd`/pico-extras" >> $GITHUB_ENV - echo "PICO_TOOLCHAIN_PATH=`pwd`/arm-gnu-toolchain-14.2.rel1-$ARCH-arm-none-eabi" >> $GITHUB_ENV - - - name: Build ${{ matrix.example.name }} - working-directory: ${{ matrix.example.name }} - run: | - cmake -B build -G Ninja . - cmake --build build diff --git a/.github/workflows/build-stm.yml b/.github/workflows/build-stm.yml deleted file mode 100644 index 57afd2c0..00000000 --- a/.github/workflows/build-stm.yml +++ /dev/null @@ -1,56 +0,0 @@ -name: STM32 - -on: - push: - branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] - workflow_dispatch: - -jobs: - build: - name: Build - runs-on: ubuntu-24.04 - - strategy: - fail-fast: false - matrix: - example: [stm32-blink, stm32-lvgl] - - steps: - - name: Checkout repo - uses: actions/checkout@v4 - - - name: Fixup for running locally in act - if: ${{ env.ACT }} - run: echo /opt/acttoolcache/node/18.20.8/x64/bin >> $GITHUB_PATH - - - name: Set up Python - uses: actions/setup-python@v5 - with: - python-version: 3.11 - - - name: Install uv - uses: astral-sh/setup-uv@v5 - - - name: Install Swift - uses: ./.github/actions/install-swift - - - name: Set environment variables - run: | - echo "STM_BOARD=STM32F746G_DISCOVERY" >> $GITHUB_ENV - - - name: Build ${{ matrix.example }} - working-directory: ${{ matrix.example }} - run: | - if [[ -f ./fetch-dependencies.sh ]]; then - ./fetch-dependencies.sh - fi - - if [[ -f ./build-elf.sh ]]; then - ./build-elf.sh - fi - - if [[ -f Makefile ]]; then - make - fi diff --git a/.github/workflows/build-zephyr.yml b/.github/workflows/build-zephyr.yml deleted file mode 100644 index 96c83b1c..00000000 --- a/.github/workflows/build-zephyr.yml +++ /dev/null @@ -1,41 +0,0 @@ -name: Zephyr - -on: - push: - branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] - workflow_dispatch: - -jobs: - build: - name: Build - runs-on: ubuntu-24.04 - - strategy: - fail-fast: false - matrix: - example: [nrfx-blink-sdk] - - steps: - - name: Checkout repo - uses: actions/checkout@v4 - - - name: Set up Python - uses: actions/setup-python@v5 - with: - python-version: 3.11 - - - name: Setup Zephyr project - uses: zephyrproject-rtos/action-zephyr-setup@v1 - with: - app-path: ${{ matrix.example }} - toolchains: arm-zephyr-eabi - sdk-version: 0.17.0 - - - name: Install Swift - uses: ./.github/actions/install-swift - - - name: Build ${{ matrix.example }} - working-directory: ${{ matrix.example }} - run: west build -b nrf52840dk/nrf52840 diff --git a/.swiftformatignore b/.swiftformatignore deleted file mode 100644 index cec22c76..00000000 --- a/.swiftformatignore +++ /dev/null @@ -1,6 +0,0 @@ -./harmony/* -./stm32-lvgl/* -./stm32-lcd-logo/Sources/STM32F7X6/* -./stm32-lvgl/Sources/Registers/* -./stm32-neopixel/Sources/STM32F7X6/* -./stm32-uart-echo/Sources/STM32F7X6/* diff --git a/CODEOWNERS b/CODEOWNERS deleted file mode 100644 index e0985355..00000000 --- a/CODEOWNERS +++ /dev/null @@ -1,19 +0,0 @@ -# This file is a list of the people responsible for ensuring that patches for a -# particular part of Swift are reviewed, either by themselves or by someone else. -# They are also the gatekeepers for their part of Swift, with the final word on -# what goes in or not. -# -# The list is sorted by surname and formatted to allow easy grepping and -# beautification by scripts. The fields are: name (N), email (E), web-address -# (W), PGP key ID and fingerprint (P), description (D), and snail-mail address -# (S). - -# N: Kuba Mracek -# E: mracek@apple.com -# D: Everything in swift-embedded-examples not covered by someone else - -### - -# The following lines are used by GitHub to automatically recommend reviewers. - -* @kubamracek @rauhul diff --git a/Documentation/README.md b/Documentation/README.md deleted file mode 100644 index 76b87d28..00000000 --- a/Documentation/README.md +++ /dev/null @@ -1,6 +0,0 @@ -Documentation for Embedded Swift -================================ - -Documentation for Embedded Swift can be found at these locations: -- [in rendered form at docs.swift.org](https://docs.swift.org/embedded/documentation/embedded/) -- [DocC source code](/Sources/EmbeddedSwift/Documentation.docc) diff --git a/Package.resolved b/Package.resolved deleted file mode 100644 index 034f2da3..00000000 --- a/Package.resolved +++ /dev/null @@ -1,24 +0,0 @@ -{ - "originHash" : "ffbd64644921de7b1a9cb8b17d9ecb480b14c4b6487677314b16730c1b12221b", - "pins" : [ - { - "identity" : "swift-docc-plugin", - "kind" : "remoteSourceControl", - "location" : "https://github.com/swiftlang/swift-docc-plugin", - "state" : { - "revision" : "85e4bb4e1cd62cec64a4b8e769dcefdf0c5b9d64", - "version" : "1.4.3" - } - }, - { - "identity" : "swift-docc-symbolkit", - "kind" : "remoteSourceControl", - "location" : "https://github.com/swiftlang/swift-docc-symbolkit", - "state" : { - "revision" : "b45d1f2ed151d057b54504d653e0da5552844e34", - "version" : "1.0.0" - } - } - ], - "version" : 3 -} diff --git a/Package.swift b/Package.swift deleted file mode 100644 index ab3b65ab..00000000 --- a/Package.swift +++ /dev/null @@ -1,16 +0,0 @@ -// swift-tools-version: 6.0 - -import PackageDescription - -let package = Package( - name: "swift-embedded-examples", - products: [ - .library(name: "EmbeddedSwift", targets: ["EmbeddedSwift"]) - ], - dependencies: [ - .package( - url: "https://github.com/swiftlang/swift-docc-plugin", from: "1.1.0") - ], - targets: [ - .target(name: "EmbeddedSwift") - ]) diff --git a/README.md b/README.md index 22199d9a..6915d325 100644 --- a/README.md +++ b/README.md @@ -1,76 +1,12 @@ -# Embedded Swift Example Projects +# Arduino Embedded Swift Example Projects -This repository is a set of demonstration projects of **Embedded Swift**. Embedded Swift is a compilation and language mode that enables development of baremetal, embedded and standalone software in Swift. To learn more, see: +This repository is a set of demonstration projects that use the [Arduino libraries](https://github.com/espressif/arduino-esp32/) and Embedded Swift. To learn more, see [swiftlang/swift-embedded-examples](https://github.com/swiftlang/swift-embedded-examples). -- [Blog post introducing this repository](https://www.swift.org/blog/embedded-swift-examples/) -- [Swift forums thread about this repository](https://forums.swift.org/t/embedded-swift-example-projects-for-arm-and-risc-v-microcontrollers/71066) -- [Discussions about Embedded Swift on the Swift forums](https://forums.swift.org/t/embedded-swift/67057) -- [Embedded Swift Vision Document](https://github.com/swiftlang/swift-evolution/blob/main/visions/embedded-swift.md) -- [Documentation for Embedded Swift](https://github.com/swiftlang/swift/tree/main/docs/EmbeddedSwift) +## Examples -## Building the examples +| Name | Platform | SDK | Description | +| ------------------------------------------------------------ | ------------------ | ----------- | -------------------------------------------------------------------------- | +| [arduino-esp32-led-blink-sdk](./arduino-esp32-led-blink-sdk) | ESP32-C6-DevKitC-1 | ESP-IDF SDK | Blink an LED repeatedly with Swift, the ESP-IDF and the Arduino libraries. | +| [arduino-esp32-wifi-scan-sdk](./arduino-esp32-wifi-scan-sdk) | ESP32-C6-DevKitC-1 | ESP-IDF SDK | Scan for WiFi networks using Swift, the ESP-IDF and the Arduino libraries. | -Each example in this repository contains build and deployment instructions, however there are a couple common steps needed for many of the examples included below: -1. Install [`swift`](https://swift.org) using the [instructions here](https://swiftpackageindex.com/swiftlang/swift-embedded-examples/main/documentation/embeddedswift/installembeddedswift). - -2. Install [`uv`](https://github.com/astral-sh/uv), "an extremely fast Python package and project manager", using the [instructions here](https://docs.astral.sh/uv/getting-started/installation/). - -## Catalog of Examples - -| Name | Platform | SDK | Description | Photo | -| ---- | -------- | --- | ----------- | ----- | -| [esp32-led-blink-sdk](./esp32-led-blink-sdk) | ESP32-C6-Bug | ESP-IDF SDK | Blink an LED repeatedly with Swift & the ESP-IDF. | | -| [esp32-led-strip-sdk](./esp32-led-strip-sdk) | ESP32-C6-DevKitC-1 | ESP-IDF SDK | Control NeoPixel LEDs with Swift & the ESP-IDF. | | -| [harmony](./harmony) | Raspberry Pi Pico W | Pico SDK | A bluetooth speaker and ferrofluidic music visualizer. Firmware, Electrical, and Mechanical designs fully available. | | -| [nrfx-blink-sdk](./nrfx-blink-sdk) | nRF52840-DK | Zephyr SDK | Blink an LED repeatedly with Swift & Zephyr. | | -| [nuttx-riscv-blink](./nuttx-riscv-blink) | QEMU | NuttX | Blink a virualized led in QEMU using the Apache NuttX RTOS | | -| [rpi-4b-blink](./rpi-4b-blink) | Raspberry Pi 4B | None | Blink the Pi's status green LED repeatedly using Swift MMIO. | | -| [rpi-5-blink](./rpi-5-blink) | Raspberry Pi 5 | None | Blink the Pi's status green LED repeatedly with Swift MMIO. | | -| [rpi-pico-blink-sdk](./rpi-pico-blink-sdk) | Raspberry Pi Pico, Pico 2 | Pico SDK | Blink an LED repeatedly with Swift & the Pico SDK. | | -| [rpi-pico-blink](./rpi-pico-blink) | Raspberry Pi Pico | None | Blink an LED repeatedly. | | -| [rpi-pico2-neopixel](./rpi-pico2-neopixel) | Raspberry Pi Pico 2 | None | Control Neopixel LEDs using the RP2350 PIO. | | -| [rpi-picow-blink-sdk](./rpi-picow-blink-sdk) | Raspberry Pi Pico W, Pico 2W | Pico SDK | Blink an LED to signal 'SOS' in Morse code repeatedly with Swift & the Pico SDK. | | -| [stm32-blink](./stm32-blink) | STM32F746G-DISCO | None | Blink an LED repeatedly. | | -| [stm32-lcd-logo](./stm32-lcd-logo) | STM32F746G-DISCO | None | Animate the Swift Logo on the built-in LCD. | | -| [stm32-lvgl](./stm32-lvgl) | STM32F746G-DISCO | – | Baremetal setup of LCD, touch panel, DRAM, using the LLVM Embedded toolchain for ARM. Renders graphics, animations, and reacts to user input via LVGL. Includes a macOS/Linux SDL based host simulation app. | | -| [stm32-neopixel](./stm32-neopixel) | STM32F746G-DISCO | None | Control NeoPixel LEDs using SPI. | | -| [stm32-uart-echo](./stm32-uart-echo) | STM32F746G-DISCO | None | Echo user input using UART. | | - -Note that the SDK integration examples (Pico SDK, Zephyr SDK, etc.) are not recommendations or endorsement, the same is true for build system choice (Make, CMake, SwiftPM, shell scripts). Embedded Swift aims to be versatile and allowing integration into existing SDKs and build systems, and the example projects show some of the possibilities. - -## Community Examples - -> [!WARNING] -> Community projects linked here are not officially supported by our team. They may not always be compatible with the latest nightly Swift toolchain builds. - - - -| Name | Platform | Description | -| ---- | -------- | ----------- | -| [swift-matter-examples](https://github.com/swiftlang/swift-matter-examples) | ESP32 | An Embedded Swift Matter application running on ESP32-C6. | -| [swift-flipperzero-hello](https://github.com/Sameesunkaria/swift-flipperzero-hello) | Flipper Zero | A demonstration of running Swift apps on the Flipper Zero. | -| [EmbeddedSwift nRF52 Examples](https://github.com/nelcea/EmbeddedSwift-nRF52-Examples) | nRF52840 (Development Kit) | A collection of examples using Embedded Swift on top of nRF Connect SDK (Zephyr). | -| [Swatak](https://github.com/nelcea/EmbeddedSwift-nRF52-Swatak) | nRF52840 (Seeed Studio XIAO) | A reaction time game inspired by BATAKΒ© boards, implemented in Embedded Swift using nRF Connect SDK. | -| [swift-picosystem-example](https://github.com/jerrodputman/swift-picosystem-example) | PicoSystem | An Embedded Swift demo running on the Pimoroni PicoSystem | -| [PlaydateKit](https://github.com/finnvoor/PlaydateKit) | Playdate | A full featured framework for building Playdate games using Embedded Swift. | -| [swift-playdate-examples](https://github.com/swiftlang/swift-playdate-examples) | Playdate | An Embedded Swift game running on Playdate by Panic. | -| [swift-stm32c011-examples](https://github.com/xtremekforever/swift-stm32c011-examples) | STM32 | Examples of running Embedded Swift on the STM32C011, which is a tiny MCU with only 6KB of SRAM and 32KB of flash. | -| [flappy-swift](https://github.com/sliemeobn/flappy-swift) | Web | A WebAssembly game written in Swift in ~100 KB. | -| [swift-for-wasm-examples](https://github.com/swiftlang/swift-for-wasm-examples) | Web | A "Swift Audio Workstation" example built with Swift for WebAssembly running in the browser using Embedded Swift. | - -Please note that the presence of community repositories and devices in this list does not constitute a recommendation or endorsement. If there's a project you'd like to see included here, please [submit an issue](https://github.com/swiftlang/swift-embedded-examples/issues/new) with the details. - -## Contributing to this repository - -This repository contains code that is not continuously developed, instead it's presented "as is" for educational and demonstrational purposes. Making major improvements to existing examples is discouraged, but additions of new examples is welcome. - -### Code of Conduct - -Like all Swift.org projects, we would like these Embedded Swift example projects to foster a diverse and friendly community. We expect contributors to adhere to the [Swift.org Code of Conduct](https://swift.org/code-of-conduct/). - -### Contact information - -The current code owners of this repository are Kuba Mracek ([@kubamracek](https://github.com/kubamracek)) and Rauhul Varma ([@rauhul](https://github.com/rauhul)). You can contact them on the Swift forums via the handles [@kubamracek](https://forums.swift.org/u/kubamracek/summary) and [@rauhul](https://forums.swift.org/u/rauhul/summary). - -In case of moderation issues, you can also directly contact a member of the [Swift Core Team](https://swift.org/community/#community-structure). diff --git a/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithBazel.md-wip b/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithBazel.md-wip deleted file mode 100644 index 44298f61..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithBazel.md-wip +++ /dev/null @@ -1,3 +0,0 @@ -# Integrate with Bazel - -🚧 Under construction... diff --git a/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithCMake.md-wip b/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithCMake.md-wip deleted file mode 100644 index a4b1ade8..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithCMake.md-wip +++ /dev/null @@ -1,3 +0,0 @@ -# Integrate with CMake - -🚧 Under construction... diff --git a/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithMake.md-wip b/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithMake.md-wip deleted file mode 100644 index 9cd03df9..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithMake.md-wip +++ /dev/null @@ -1,3 +0,0 @@ -# Integrate with Make - -🚧 Under construction... diff --git a/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithSwiftPM.md-wip b/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithSwiftPM.md-wip deleted file mode 100644 index 9c01a760..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithSwiftPM.md-wip +++ /dev/null @@ -1,3 +0,0 @@ -# Integrate with SwiftPM - -🚧 Under construction... diff --git a/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithXcode.md-wip b/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithXcode.md-wip deleted file mode 100644 index e1b79af7..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/BuildSystemSupport/IntegrateWithXcode.md-wip +++ /dev/null @@ -1,6 +0,0 @@ -# Integrate with Xcode - -🚧 Under construction... - -> Warning: Embedded Swift integration with Xcode is still under development and -> subject to change. diff --git a/Sources/EmbeddedSwift/Documentation.docc/CompilerDetails/ABI.md b/Sources/EmbeddedSwift/Documentation.docc/CompilerDetails/ABI.md deleted file mode 100644 index 54aee6ac..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/CompilerDetails/ABI.md +++ /dev/null @@ -1,54 +0,0 @@ -# ABI of Embedded Swift - -Understanding the different ABI (Application Binary Interface) for Embedded Swift - -## ABI stability - -The ABI of code generated by Embedded Swift is not currently stable. For a concrete compiler version, it will be consistent, but do not mix code built with different compiler versions. - -Similarly, do not mix Embedded Swift code with full Swift code, as the ABIs are different. Details are described in the following sections. - -## Symbol mangling under Embedded Swift - -Since Swift 5.0, the stable ABI mangling scheme uses the `$s` prefix on all Swift symbols. Because Embedded Swift's ABI differs from the stable ABI, and furthermore because it's not expected to be stable, Embedded Swift uses a `$e` mangling prefix. The logic and structure of the mangling stays the same, the only difference is the prefix. - -## Calling convention of Embedded Swift - -As of today, Embedded Swift has identical calling convention to full Swift. However, this does not need to continue in the future, and there should not be expectations that the ABI of Embedded Swift is compatible with full Swift. - -The compiler respects the ABIs and calling conventions of C and C++ when interoperating with code in those languages. Calling C/C++ functions from Embedded Swift code is supported, and similarly exporting Swift code via `@_extern`, `@_cdecl` or `@_expose` will match the right calling conventions that C/C++ expects. - -## Metadata ABI of Embedded Swift - -Embedded Swift eliminates almost all metadata compared to full Swift. However, class and existential metadata are still used, because those serve as vtables and witness tables for dynamic dispatch of methods to implement runtime polymorphism with classes and existentials. - -### Class Metadata ABI - -The layout of Embedded Swift's class metadata is *different* from full Swift: - -- The **super pointer** pointing to the class metadata record for the superclass is stored at **offset 0**. If the class is a root class, it is null. -- The **destructor pointer** is stored at **offset 1**. This function is invoked by Swift's deallocator when the class instance is destroyed. -- The **ivar destroyer** is stored at **offset 2**. This function is invoked to destroy instance members when creation of the object is cancelled (e.g. in a failable initializer). -- Lastly, the **vtable** is stored at **offset 3**: For each Swift class in the class's inheritance hierarchy, in order starting - from the root class and working down to the most derived class, the function pointers to the implementation of every method of the class in declaration order is stored. - -### Witness Tables ABI - -The layout of Embedded Swift's witness tables is *different* from full Swift: - -- The first word is always a null pointer (TODO: it can be eliminated) -- The following words are witness table entries which can be one of the following: - - A method witness: a pointer to the witness function. - - An associated conformance witness: a pointer to the witness table of the associated conformance - -Note that witness tables in Embedded Swift do not contain associated type entries. - -Witness functions are always specialized for concrete types. This also means that parameters and return values are passed directly (if possible). - -## Heap object layout in Embedded Swift - -Heap objects have the following layout in Embedded Swift: - -- The **isa pointer** (pointer to the class metadata) is stored at **offset 0**. -- The **refcount** is stored inline at **offset 1**. -- Normal stored properties follow. diff --git a/Sources/EmbeddedSwift/Documentation.docc/CompilerDetails/Status.md b/Sources/EmbeddedSwift/Documentation.docc/CompilerDetails/Status.md deleted file mode 100644 index a1d156f7..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/CompilerDetails/Status.md +++ /dev/null @@ -1,73 +0,0 @@ -# Implementation Status - -Implementation status of compiler and language features in Embedded Swift, comparison to standard Swift - -## Embedded Swift Language Features - -| **Language Feature** | **Currently Supported In Embedded Swift** | -|-------------------------------------------------------|------------------------------------------------------------------------------------| -| *Anything not listed below* | Yes | -| Library Evolution (resilience) | No, intentionally unsupported long-term | -| Objective-C interoperability | No, intentionally unsupported long-term | -| Non-WMO builds | No, intentionally unsupported long-term (WMO should be used) | -| Existentials (values of protocol types) | Only class-bound existentials (for protocols derived from AnyObject) are supported | -| Any | No, currently disallowed | -| AnyObject | Yes | -| Metatypes | No, currently only allowed as unused arguments (type hints) | -| Untyped throwing | No, intentionally unsupported long-term (typed throwing should be used instead) | -| Weak references, unowned references | No | -| Non-final generic class methods | No, intentionally unsupported long-term, see | -| Parameter packs (variadic generics) | No, not yet supported | - -## Embedded Standard Library Breakdown - -This status table describes which of the following standard library features can be used in Embedded Swift: - -| **Swift Standard Library Feature** | **Currently Supported In Embedded Swift?** | -|------------------------------------------------------------|-----------------------------------------------------| -| Array (dynamic heap-allocated container) | Yes | -| Array slices | Yes | -| assert, precondition, fatalError | Partial, only StaticStrings can be used as a failure message | -| Bool, Integer types, Float types | Yes | -| Codable, Encodable, Decodable | No | -| Collection + related protocols | Yes | -| Collection algorithms (sort, reverse) | Yes | -| CustomStringConvertible, CustomDebugStringConvertible | Yes, except those that require reflection (e.g. Array's .description) | -| Dictionary (dynamic heap-allocated container) | Yes | -| Floating-point conversion to string | No | -| Floating-point parsing | No | -| FixedWidthInteger + related protocols | Yes | -| Hashable, Equatable, Comparable protocols | Yes | -| InputStream, OutputStream | No | -| Integer conversion to string | Yes | -| Integer parsing | Yes | -| KeyPaths | Partial (only compile-time constant key paths to stored properties supported, only usable in MemoryLayout and UnsafePointer APIs) | -| Lazy collections | Yes | -| ManagedBuffer | Yes | -| Mirror (runtime reflection) | No, intentionally unsupported long-term | -| Objective-C bridging | No, intentionally unsupported long-term | -| Optional | Yes | -| print / debugPrint | Partial (only String, string interpolation, StaticStrings, integers, pointers and booleans, and custom types that are CustomStringConvertible) | -| Range, ClosedRange, Stride | Yes | -| Result | Yes | -| Set (dynamic heap-allocated container) | Yes | -| SIMD types | Yes | -| StaticString | Yes | -| String (dynamic) | Yes | -| String interpolations | Partial (only strings, integers, booleans, and custom types that are CustomStringConvertible can be interpolated) | -| Unicode | Yes | -| Unsafe\[Mutable\]\[Raw\]\[Buffer\]Pointer | Yes | -| VarArgs | No | - -## Non-stdlib Features - -This status table describes which of the following Swift features can be used in Embedded Swift: - -| **Swift Feature** | **Currently Supported In Embedded Swift?** | -|------------------------------------------------------------|-----------------------------------------------------| -| Synchronization module | Partial (only Atomic types, no Mutex) | -| Swift Concurrency | Partial, experimental (basics of actors and tasks work in single-threaded concurrency mode) | -| C interop | Yes | -| C++ interop | Yes | -| ObjC interop | No, intentionally unsupported long-term | -| Library Evolution | No, intentionally unsupported long-term | diff --git a/Sources/EmbeddedSwift/Documentation.docc/Documentation.md b/Sources/EmbeddedSwift/Documentation.docc/Documentation.md deleted file mode 100644 index 2439abb7..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/Documentation.md +++ /dev/null @@ -1,53 +0,0 @@ -# Embedded Swift - -Embedded Swift is a compilation and language mode that enables development of baremetal, embedded and standalone software in Swift - -@Metadata { - @TechnologyRoot -} - -## Topics - -### Getting Started - -- -- -- - -### Guided Examples - -- -- -- -- - -### Using Embedded Swift - -- -- -- -- -- -- -- - -### Build System Support - -- -- -- -- -- - -### SDK Support - -- -- -- -- -- - -### Compiler Development and Details - -- -- diff --git a/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/InstallEmbeddedSwift.md b/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/InstallEmbeddedSwift.md deleted file mode 100644 index efb26272..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/InstallEmbeddedSwift.md +++ /dev/null @@ -1,30 +0,0 @@ -# Install Embedded Swift - -Get the tools needed to use Embedded Swift - -## Overview - -The best way to install Swift for embedded development is using [`swiftly`](http://github.com/swiftlang/swiftly), the official Swift toolchain installer and manager. Since Embedded Swift is still experimental and not yet supported in public Swift releases, you'll need to use a development toolchain. - -For instructions on how to install `swiftly`, check out the [Getting Started](https://www.swift.org/swiftly/documentation/swiftly/getting-started) guide. - -> Note: Swiftly installs the latest release toolchain during `swiftly init`, if you only plan on using Embedded Swift, you can avoid downloading this toolchain by using the `swiftly init --skip-install` option. - -After installing Swiftly, install the latest main "Development Snapshot" toolchain available for your platform by running: - -```shell -$ swiftly install main-snapshot -... -main-snapshot-2025-04-12 installed successfully! -``` - -To test that you have Swift installed, run `swift --version` from your shell or terminal app. It should say "6.2-dev", meaning you have a "Development Snapshot" toolchain. - -```shell -$ swift --version -Apple Swift version 6.2-dev (LLVM 81ab6d9f7e4810f, Swift 9cc1947527bacea) -Target: arm64-apple-macosx15.0 -Build config: +assertions -``` - -> Warning: When using other shells, like one integrated into an IDE, be careful to verify that the version of Swift reported matches that of the shell you used to install Swift. diff --git a/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/Introduction.md b/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/Introduction.md deleted file mode 100644 index 4344ec63..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/Introduction.md +++ /dev/null @@ -1,62 +0,0 @@ -# Introduction to Embedded Swift - -Write Swift code for microcontrollers, embedded systems, and bare-metal applications - -## Overview - -Embedded Swift is an experimental and rapidly developing feature of the Swift language that enables development of baremetal, embedded and standalone software. It's a subset of the Swift language designed for producing small, efficient binaries with minimal dependencies, making it suitable for resource-constrained environments. - -> Note: Embedded Swift is experimental. Public releases of Swift do not support Embedded Swift, yet. See for details. - -## How does Embedded Swift differ from regular Swift? - -Regular Swift is not a good fit for small constrained environments like microcontrollers, mainly due to codesize and memory footprint. Regular Swift typically requires at least a few megabytes of code and data to support dynamic language features like reflection, and separately compiled generics with ABI stability. Embedded Swift, on the other hand, can be deployed to environments with as little as kilobytes of available memory. This is achieved by: - -- Eliminating runtime type metadata where possible -- Removing reflection capabilities -- Using compile-time specialization (monomorphization) for generic code -- Minimizing dependencies on external libraries - -It's also a good mental model to think of the Swift compiler in Embedded Swift mode as operating on a way a *traditional C compiler* does β€” specifically in the sense that the compiler produces an object file that does not call into or depend on symbols that are not explicitly used in the source code. This is achieved even for code that uses generics, protocols, tuples, arrays, and more β€” all the higher-level language features are "compiled out" (e.g. generics are specialized), and standard library code is pulled into the object file as needed (e.g. array implementation). - -This results in properties that are a great fit for embedded software development: - -- **Small binaries** that can be as tiny as a few hundred bytes for "Hello World"-like programs (fully self-contained). -- **No hidden runtime costs** – Embedded Swift's runtime library does not manage any data structures behind your back, is itself less than a kilobyte in size, and is eligible to be removed if unused. -- **No hidden allocations** which would cause unpredictable performance cliffs. -- **Full C/C++ interoperability** to directly interact with existing C libraries and hardware-specific code, making it easy to integrate with vendor SDKs. -- **Modern language features** like optionals, generics, and strong type safety are all available in Embedded Swift. -- **Full safety of Swift** is retained in Embedded Swift. - -For a detailed introduction and motivation into Embedded Swift, please see "[A Vision for Embedded Swift](https://github.com/swiftlang/swift-evolution/blob/main/visions/embedded-swift.md)", a Swift Evolution document highlighting the main goals and approaches. Note that this is a historical document and does not capture latest development and further evolution. For an up-to-date in-depth breakdown of the language features of Embedded Swift, please see . - -## What Embedded Swift is and isn't - -- Embedded Swift **is** a way to produce small and freestanding binaries (with no, or trivial dependencies). -- Embedded Swift **is not** a complete one-click solution to program all embedded boards and MCUs. -- Embedded Swift **is** a compilation model that's analogous to a traditional C compiler in the sense that the compiler produces an object file (.o) that can be simply linked with your existing code, and it's not going to require you to port any libraries or runtimes. -- Embedded Swift **is not** a HAL, it's not an SDK for development, it's not a set of libraries to program peripherals using high-level APIs. It's instead a compilation mode that's suitable for creating these components. - -## Platform support - -The Swift toolchain has the ability to produce code for almost any standard ARM and RISC-V platform, and that makes Embedded Swift versatile and not limited to specific platforms or hardware devices. This way, Embedded Swift can potentially target many different microcontroller families and embedded devices. - -Boards with active community support include the Raspberry Pi Pico, various STM32 development boards, various nRF52840 based boards and several ESP32 variants, with more platforms being regularly added as the community grows. - -## Interoperability with existing SDKs - -Software projects using Embedded Swift are typically developed in one of the following ways: - -1. Integrating with an existing SDK (typically in C, or C++) that provides either an embedded OS, or OS-like facilities, hardware drivers, and overall functionality that's needed for embedded software. - -2. Writing fully "bare-metal" code, without any pre-existing setup or SDK. This is typically done for extremely constrained environments and/or when full control of every piece of code is needed. - -Both the approaches are readily available in Embedded Swift, and the choice of which approach to use depends on your specific project requirements, hardware constraints, and development preferences. For integrating with existing SDKs, Swift's C/C++ interoperability makes it straightforward to call native SDK functions, while the bare-metal approach gives you complete control over every aspect of your code's execution environment. - -## Getting Started - -To start using Embedded Swift, please see the page for installation instructions. - -Once you've set up the toolchain, we recommend exploring the page which provides various paths for getting started, including the to try Embedded Swift on your development machine, and more advanced guides such as for programming an actual embedded device. - -For details about using Embedded Swift, consult the documentation, which explains how to build code with Embedded Swift and shows integration patterns with embedded SDKs and build systems. diff --git a/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/LanguageSubset.md b/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/LanguageSubset.md deleted file mode 100644 index 1120fbb1..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/LanguageSubset.md +++ /dev/null @@ -1,30 +0,0 @@ -# Language subset - -Details of the Embedded Swift language subset compared to full Swift - -Embedded Swift is a subset of the Swift language, and some features are not available in Embedded Swift. This is necessary in order to achieve small binaries with effective dead-code elimination and minimized system dependencies. - -That said, *the vast majority* of the Swift language works exactly the same in Embedded Swift. This includes generics, protocols, enums with associated values, tuples, optionals, classes (instances are allocated on the heap and refcounted just like in regular Swift), inheritance, runtime polymorphism, arrays (heap-allocated copy-on-write just like in regular Swift) and much more. - -Note that there are no behavior changes in Embedded Swift compared to full Swift, and Embedded Swift is strictly a *subset* and not a *dialect*. Any code compatible with Embedded Swift will also compile and have the same semantics in full Swift. - -## Code-level features that are not available - -- **Not available**: Runtime reflection (`Mirror` APIs). -- **Not available**: Values of protocol types ("existentials"), unless the protocol is restricted to be class-bound (derived from AnyObject). E.g. `let a: Hashable = ...` is not allowed. `Any` is also not allowed. See for details and alternatives of existentials. -- **Not available**: Throwing errors or `any Error` type (in contrast with "typed throws", which *is* supported in Embedded Swift). -- **Not available**: Metatypes, e.g. `let t = SomeClass.Type` or `type(of: value)` are not allowed. -- **Not available**: Standard library types that rely on the above, for example `Codable` and `KeyPath`, are not allowed. -- **Not available**: Printing and stringification of arbitrary types (which is achieved via reflection in desktop Swift). -- **Not available**: Using non-final generic class methods. See for details on this. -- **Not available**: Weak and unowned references are not allowed (unsafe unowned references *are* available). - -## Compilation facilities that are not available - -- **Not available**: Library Evolution (stable ABI), and facilities that requires Library Evolution (e.g. internal module imports) -- **Not available**: Objective-C interoperability -- **Not available**: Builds without WMO (whole module optimization) - -## Further resources - -The above lists are describing features that are removed from Embedded Swift *by design*. Since Embedded Swift is currently an experimental preview, there might also be features that are not yet implemented. See the in-development status at . diff --git a/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/WaysToGetStarted.md b/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/WaysToGetStarted.md deleted file mode 100644 index 22d189ba..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/GettingStarted/WaysToGetStarted.md +++ /dev/null @@ -1,40 +0,0 @@ -# Getting started with Embedded Swift - -Possible directions to explore to start using Embedded Swift - -## Introduction - -Embedded Swift is a way to write code for embedded systems using the Swift programming language. Depending on the use case, there are different ways of using it, different ways of integrating with existing ecosystems, and different setups for different hardware devices. This guide will help you explore various paths to get started with embedded development using Swift. - -Before diving into Embedded Swift development, you should have: - -- Basic knowledge of the Swift programming language -- A Swift toolchain installed on your development host -- A target embedded platform in mind (e.g. a Raspberry Pi Pico) - - this can also be a simulated hardware platform (e.g. in QEMU), or even a full desktop OS environment in case you're not interested in controlling low-level hardware or custom electronic peripherals - -> Note: Embedded Swift is experimental. Public releases of Swift do not support Embedded Swift, yet. See for details. - -## Guided Tutorials - -To help you get started with Embedded Swift, we've prepared several step-by-step guides that cover different platforms and use cases: - -- - Try out Embedded Swift on your development machine -- - Build and run Swift code on a Raspberry Pi Pico -- - Set up a baremetal Swift project for STM32 microcontrollers - -These guides provide a practical introduction to Embedded Swift development with specific hardware targets, showing you how to build, upload, and run your first Swift programs on embedded systems. - -## Other Resources - -For a deeper understanding of Embedded Swift concepts and philosophy, check out these resources: - -- - Learn about the core concepts and philosophy of Embedded Swift -- - Understand which Swift language features are available in Embedded Swift -- - Detailed instructions for installing the required toolchain - -For developers coming from embedded C/C++ backgrounds or those integrating Swift into existing projects: - -- - Essential knowledge for using Embedded Swift effectively -- - How to share code between Embedded Swift and standard Swift -- - Understanding how libraries work in Embedded Swift diff --git a/Sources/EmbeddedSwift/Documentation.docc/GuidedExamples/PicoGuide.md b/Sources/EmbeddedSwift/Documentation.docc/GuidedExamples/PicoGuide.md deleted file mode 100644 index d4480e2a..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/GuidedExamples/PicoGuide.md +++ /dev/null @@ -1,169 +0,0 @@ -# Raspberry Pi Pico Blink (Pico SDK) - -Tutorial for targetting a Raspberry Pi Pico as an embedded device that runs a simple Swift program - -In this guide we'll be targeting a Raspberry Pi Pico as the embedded device that our Swift application will run on. If you don't physically have one, don't worry! You can still run the application in an online emulator. - -## Installing Swift - -> Note: Embedded Swift is experimental. Public releases of Swift do not support Embedded Swift, yet. See for details. - -To install Swift for embedded development, follow the instructions in , which guides you through using `swiftly` to install the latest development snapshot with Embedded Swift support. - -To test that you have Swift installed, run `swift --version` from your shell or terminal app. It should say "6.2-dev" or similar, confirming you have a "Development Snapshot" toolchain. - -## Installing dependencies for embedded development - -Install the Raspberry Pi Pico SDK, and the Arm Embedded Toolchain by following the [Getting Started With Pico guide](https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf). -Export three environment variables to match your setup and hardware: - -```shell -$ export PICO_BOARD=pico -$ export PICO_SDK_PATH=... # location to your Pico SDK -$ export PICO_TOOLCHAIN_PATH=... # location to the Arm Embedded Toolchain -``` - -If you have the Wi-Fi enabled Pico W / Pico 2W board instead of the regular Pico, note that you will need a slightly different setup described in the [Pico W example project](https://github.com/swiftlang/swift-embedded-examples/tree/main/rpi-picow-blink-sdk), and just specifying `PICO_BOARD=pico_w` is not going to work. - -Install [CMake 3.29](https://cmake.org/) or newer. - -To test that you have all the necessary parts installed, you can run the following commands in a terminal: - -```shell -$ swift --version -Apple Swift version 6.2-dev (LLVM 81ab6d9f7e4810f, Swift 9cc1947527bacea) -$ cmake --version -cmake version 3.29.2 -$ echo $PICO_BOARD -pico -$ ls $PICO_SDK_PATH -CMakeLists.txt README.md external/ pico_sdk_version.cmake tools/ -CONTRIBUTING.md cmake/ lib/ src/ -LICENSE.TXT docs/ pico_sdk_init.cmake test/ -$ ls $PICO_TOOLCHAIN_PATH -13.2.Rel1-darwin-arm64-arm-none-eabi-manifest.txt include/ share/ -arm-none-eabi/ lib/ -bin/ libexec/ -``` - -## Building a "blinky" embedded app - -The standard "Hello, World" in embedded development is a program that repeatedly blinks an LED. Let's build one. The following setup can be also found in [swift-embedded-examples](https://github.com/swiftlang/swift-embedded-examples/blob/main/rpi-pico-blink-sdk/README.md), but we're going to show below that all you need is just three files. -Let's create a new empty directory and prepare a simple structure for a CMake-based project that can be used on top of the Pico SDK: - -``` -embedded-swift-tutorial -β”œβ”€β”€ BridgingHeader.h -β”œβ”€β”€ CMakeLists.txt -└── Main.swift -``` - -The Main.swift and BridgingHeader.h files can initially have the following basic content: - -```swift -// Main.swift -let led = UInt32(PICO_DEFAULT_LED_PIN) -gpio_init(led) -gpio_set_dir(led, /*out*/true) -while true { - gpio_put(led, true) - sleep_ms(250) - gpio_put(led, false) - sleep_ms(250) -} -``` - -```c -// BridgingHeader.h -#include "pico/stdlib.h" -``` - -To build on top of the Pico SDK's CMake support, we need a bit more CMake logic in the CMakeLists.txt file: - -```cmake -# CMakeLists.txt -cmake_minimum_required(VERSION 3.29) -include($ENV{PICO_SDK_PATH}/external/pico_sdk_import.cmake) - -set(CMAKE_Swift_COMPILATION_MODE wholemodule) -set(CMAKE_Swift_COMPILER_WORKS YES) - -project(blinky) -pico_sdk_init() -enable_language(Swift) - -add_executable(blinky Main.swift) -set_target_properties(blinky PROPERTIES LINKER_LANGUAGE CXX) - -# Clear the default COMPILE_OPTIONS which include C specific compiler flags that the Swift compiler will not accept -# Instead, set those options to only apply when compiling C code. -set_target_properties(pico_standard_link PROPERTIES INTERFACE_COMPILE_OPTIONS "") -target_compile_options(pico_standard_link INTERFACE "$<$:SHELL: -ffunction-sections -fdata-sections>") - -set(SWIFT_INCLUDES) -foreach(dir ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES}) - string(CONCAT SWIFT_INCLUDES ${SWIFT_INCLUDES} "-Xcc ") - string(CONCAT SWIFT_INCLUDES ${SWIFT_INCLUDES} "-I${dir} ") -endforeach() - -target_compile_options(blinky PUBLIC "$<$:SHELL: - -enable-experimental-feature Embedded - -target armv6m-none-none-eabi -Xcc -mfloat-abi=soft -Xcc -fshort-enums -Xfrontend -function-sections - -import-bridging-header ${CMAKE_CURRENT_LIST_DIR}/BridgingHeader.h - ${SWIFT_INCLUDES} - >") - -target_link_libraries(blinky pico_stdlib hardware_uart hardware_gpio) -pico_add_extra_outputs(blinky) -``` - -Now we're ready to configure and build this firmware for the Pico. Run the following commands: - -```shell -$ cmake -B build -G Ninja . # configure step -$ cmake --build build # build step -``` - -The build should succeed and produce the firmware in several formats (ELF, HEX, UF2), including some information dump files (DIS, ELF.MAP): - -```shell -$ ls -al build/blinky* --rwxr-xr-x 1 kuba staff 8.0K Jan 1 12:00 build/blinky.bin* --rw-r--r-- 1 kuba staff 145K Jan 1 12:00 build/blinky.dis --rwxr-xr-x 1 kuba staff 30K Jan 1 12:00 build/blinky.elf* --rw-r--r-- 1 kuba staff 222K Jan 1 12:00 build/blinky.elf.map --rw-r--r-- 1 kuba staff 23K Jan 1 12:00 build/blinky.hex --rw-r--r-- 1 kuba staff 16K Jan 1 12:00 build/blinky.uf2 -``` - -## Running the firmware on a device - -If you have a Raspberry Pi Pico, we're now going to upload the built firmware and run it. If you don't have one, skip to the next section and run the exact same firmware file **in an emulator instead**. - -Connect the Raspberry Pi Pico board via a USB cable to your Mac, and make sure it's in the USB Mass Storage firmware upload mode. This is normally the case if you have never uploaded any firmware yet – the Pico boots to the firmware upload mode if its memory doesn't contain any valid firmware. Once a valid firmware is uploaded, the device will run that firmware after plugging in. To go back to the firmware upload mode, *hold the BOOTSEL button while plugging in the board*. - -The Pico should then show up as a mounted volume in /Volumes (as RPI-RP2 in this case): - -```shell -$ ls -al /Volumes -lrwxr-xr-x 1 root wheel 1B Jan 1 12:00 Macintosh HD@ -> / -drwx------ 1 kuba staff 16K Dec 31 1969 RPI-RP2/ -``` - -Copy the UF2 file to this volume: - -```shell -$ cp build/blinky.uf2 /Volumes/RPI-RP2 -``` - -This will make the Pico automatically install the firmware, reboot itself, and run the firmware. - -The green LED should now be blinking repeatedly. Hooray! Our first Embedded Swift program is running on an embedded device! - -## Running the firmware in an emulator - -If you don't have a physical Pico, or if you want to iterate quickly, [Wokwi](https://wokwi.com/) is free online emulator of various embedded microcontrollers, including a Raspberry Pi Pico. It executes the same firmware binary that you would normally upload to a physical device, and emulates one instruction at a time. - -Open a [new Pico project in Wokwi](https://wokwi.com/projects/new/pi-pico). Instead of using the code editor to write C code, press F1 and choose "Upload Firmware and Start Simulation". Then select the UF2 file that our build process produced. - -Once you upload the UF2 file to Wokwi, the simulation will start, and the LED should begin blinking repeatedly. Hooray! Our first Embedded Swift program is running in an emulator! diff --git a/Sources/EmbeddedSwift/Documentation.docc/GuidedExamples/STM32BaremetalGuide.md b/Sources/EmbeddedSwift/Documentation.docc/GuidedExamples/STM32BaremetalGuide.md deleted file mode 100644 index fa3e4691..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/GuidedExamples/STM32BaremetalGuide.md +++ /dev/null @@ -1,495 +0,0 @@ -# Baremetal Setup for STM32 with Embedded Swift - -Program a STM32 microcontroller directly with low-level Swift code - -This tutorial will guide you through setting up a baremetal STM32 project with Embedded Swift to create a simple LED blinking application with text output to UART, the "Hello World" of embedded systems. Concretely, we'll be using the STM32F746G-DISCO (discovery) development board, but the setup will work (with only small tweaks) on most other STM32 devices. - -We will be writing a full firmware from scratch including low-level boot code, direct hardware register configuration, a custom linker script and more. Besides educational purposes, this level of control is typically only needed in specialized setups because it involves more work and more complexity. If you want a simpler path to get started, you can integrate with an existing embedded SDK (like STCube or BSPs) instead, which offers higher-level APIs and hardware abstraction. Check out for guidance on common integration patterns. - -## Overall plan - -The entire baremetal project will consist of: -- A Package.swift file describing the overall structure of the project -- Register definitions for GPIO registers generated by Swift MMIO -- A toolset.json file defining compilation and linking flags -- A Makefile that will serve as a simple shortcut for building and flashing -- A simple linker script -- An interrupt vector and a reset function implementing basic startup code -- Finally, the application logic in Embedded Swift that will set up UART and print "Hello World" - -Let's get started! - -## Prerequisites - -- Mac or Linux -- STM32F746G-DISCO board connected over a USB cable -- Swift toolchain installed using swiftly - -## Step 1: Create a New Swift Package - -Create a new directory for your project and initialize a Swift package: - -```bash -mkdir STM32BlinkLED -cd STM32BlinkLED -swift package init --type executable -``` - -The initial Swift code that this generates will be in `Sources/STM32BlinkLED/STM32BlinkLED.swift` and we can keep its current content for now: - -```swift -// The Swift Programming Language -// https://docs.swift.org/swift-book - -@main -struct STM32BlinkLED { - static func main() { - print("Hello, world!") - } -} -``` - -Let's work on getting this print to actually work and produce text into UART. - -## Step 2: Download Arm Toolchain for Embedded - -We're going to use the [Arm Toolchain for Embedded](https://github.com/arm/arm-toolchain/tree/arm-software/arm-software/embedded) (formerly called "LLVM Toolchain for ARM") to provide us with basic C-level helper code, concretely memset, memcpy, and an allocator (malloc, free). - -Go to [https://github.com/arm/arm-toolchain/releases](https://github.com/arm/arm-toolchain/releases) and download the latest released version of "ATfe" for your host OS: -- On macOS, download e.g. `ATfE-20.1.0-Darwin-universal.dmg`. -- On x86_64 Linux, download e.g. `ATfE-20.1.0-Linux-x86_64.tar.xz`. - -Expand and copy out the contents of the toolchain into a subdirectory `llvm-toolchain` of our project. We should end up with a structure of: -```shell -STM32BlinkLED -|- llvm-toolchain - |- bin/ - |- CHANGELOG.md - |- docs/ - |- include/ - |- lib/ - |- README.md - |- ... -|- Sources -|- Package.swift -``` - -## Step 3: Configure the Package - -Edit the `Package.swift` file to configure your project for embedded development, specifically let's use Swift MMIO as a dependency, and let's create two helper targets "Registers" and "Support": - -```swift -// swift-tools-version: 5.10 -import PackageDescription - -let package = Package( - name: "STM32BlinkLED", - platforms: [.macOS(.v11)], - products: [ - .executable(name: "STM32BlinkLED", targets: ["STM32BlinkLED"]) - ], - dependencies: [ - .package(url: "https://github.com/swiftlang/swift-mmio", branch: "main"), - ], - targets: [ - .executableTarget( - name: "STM32BlinkLED", - dependencies: ["Registers", "Support"]), - .target( - name: "Registers", - dependencies: [.product(name: "MMIO", package: "swift-mmio")]), - .target( - name: "Support"), - ]) -``` - -Then let's create the respective source directories for the new targets (empty for now): - -```shell -$ mkdir Sources/Registers -$ mkdir Sources/Support -$ mkdir Sources/Support/include -``` - -## Step 4: Generate MMIO register descriptions using SVD2Swift - -SVD2Swift is a tool provided by Swift MMIO that automatically generates Swift code from SVD (System View Description) files. SVD files contain detailed descriptions of all the memory-mapped registers in a microcontroller, making them invaluable for embedded development. Using this generated code gives us type-safe access to the hardware registers of the STM32F7 microcontroller. - -First, we'll build the SVD2Swift tool from the swift-mmio package we added as a dependency, then download an SVD file for our specific microcontroller, and finally generate the register definitions we need: - -```shell -$ swift build --product SVD2Swift -$ curl -L "https://github.com/swiftlang/swift-embedded-examples/raw/refs/heads/main/Tools/SVDs/stm32f7x6.patched.svd" -O -$ .build/debug/SVD2Swift --input stm32f7x6.patched.svd --output Sources/Registers --access-level public \ - --peripherals RCC USART1 GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG GPIOH GPIOI GPIOJ GPIOK -``` - -Tip: If a build fails for any reason, it's often useful to add the `--verbose` flag to `swift build` to see a full list of commands the build system runs. - -## Step 5: Create a toolset.json file - -Create a `toolset.json` file in the project directory to configure the build with essential settings for ARMv7-based STM32 microcontrollers. This file defines options for the Swift compiler, C compiler, and linker: - -```json -{ - "schemaVersion": "1.0", - "swiftCompiler": { - "extraCLIOptions": [ - "-enable-experimental-feature", "Embedded", - "-Xfrontend", "-mergeable-symbols" - ] - } -} -``` - -After this is done, let's attempt a build using `swift build`. We have to specify the path to the toolset file, and also the right target triple: - -```shell -$ swift build --configuration release --triple armv7em-none-none-eabi --toolset toolset.json -``` - -Currently, this should succeed during compilation, but fail to link (because we haven't yet defined a valid linker script for embedded usage): - -```shell -$ swift build --configuration release --triple armv7em-none-none-eabi --toolset toolset.json -... -error: link command failed with exit code 1 (use -v to see invocation) -ld.lld: error: unable to find library -lc -ld.lld: error: unable to find library -lm -ld.lld: error: libclang_rt.builtins.a: No such file or directory -clang: error: ld.lld command failed with exit code 1 (use -v to see invocation) -``` - -## Step 6: Create a Linker Script and Startup Code - -Let's now create a linker script, an interrupt vector and startup code. - -Create a linker script file named `stm32f4.ld` in the project root directory: - -``` -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* end: 0x08100000 */ - sram_stack (rw) : ORIGIN = 0x20000000, LENGTH = 32K /* end: 0x20008000 */ - sram_data (rw) : ORIGIN = 0x20008000, LENGTH = 160K /* end: 0x20030000 */ - sram_heap (rw) : ORIGIN = 0x20030000, LENGTH = 128K /* end: 0x20050000 */ -} - -SECTIONS -{ - .text : { *(.vectors*) ; *(.text*) } > flash - .rodata : { *(.rodata*) ; *(.got*) } > flash - - __flash_data_start = (. + 3) & ~ 3; /* 4-byte aligned end of text is where data is going to be placed (by elf2hex) */ - - .bss : { *(.bss*) } > sram_data - .tbss : { *(.tbss*) } > sram_data - .data : { *(.data*) } > sram_data - - __flash_data_len = . - ORIGIN(sram_data); - - /DISCARD/ : { *(.swift_modhash*) } - /* ARM metadata sections */ - /DISCARD/ : { *(.ARM.attributes*) *(.ARM.exidx) } - /* ELF metadata sections */ - .symtab : { *(.symtab) } - .strtab : { *(.strtab) } - .shstrtab : { *(.shstrtab) } - .debug : { *(.debug*) } - .comment : { *(.comment) } -} - -__stack_start = ORIGIN(sram_stack); -__stack_end = ORIGIN(sram_stack) + LENGTH(sram_stack); - -__data_start = ORIGIN(sram_data); -__data_end = ORIGIN(sram_data) + LENGTH(sram_data); - -__heap_start = ORIGIN(sram_heap); -__heap_end = ORIGIN(sram_heap) + LENGTH(sram_heap); -``` - -Create startup code in C that defines the interrupt table and reset handler, in `Sources/Support/Startup.c`: - -```c -#include -#include - -void enable_fpu(void) { - *(volatile uint32_t *)0xE000ED88 |= (0xF << 20); // set CP10 and CP11 Full Access -} - -// Reset entrypoint -__attribute__((naked)) __attribute__((noreturn)) void ResetISR(void) { - asm volatile("bl enable_fpu"); - asm volatile("ldr r0, =__data_start // dst"); - asm volatile("ldr r1, =__flash_data_start // src"); - asm volatile("ldr r2, =__flash_data_len // size"); - asm volatile("bl memcpy"); // Relocate data section to RAM - asm volatile("bl main"); - - // If main returns, spin. - asm volatile("b ."); -} - -void IntDefaultHandlerISR() { __builtin_trap(); } - -// These are provided by the linker script -extern void *__stack_start; -extern void *__stack_end; - -// Primary interrupt vector table -__attribute__((section(".vectors"))) const void *Vectors[120] = { - (void *)(((uintptr_t)&__stack_end) - 4), // initial SP - ResetISR, // 1 0x04 The reset handler - IntDefaultHandlerISR, // 2 0x08 The NMI handler - // All other interrupts are not handled -}; - -// ELF entrypoint, not actually called at runtime, but it's a GC root -void *_start_elf(void) { return (void *)&Vectors; } -``` - -Finally, let's update `toolset.json` to configure the linker settings for our embedded target. We'll need to add several important options: -1. The `-T` flag to specify our custom linker script -2. Library paths to the ARM toolchain we downloaded -3. Standard C library and runtime library linkage -4. Disable standard library and stack protector features that aren't appropriate for baremetal code. - -```json -{ - "schemaVersion": "1.0", - "swiftCompiler": { - "extraCLIOptions": [ - "-enable-experimental-feature", "Embedded", - "-Xfrontend", "-mergeable-symbols", - "-Xfrontend", "-disable-stack-protector", - "-Xclang-linker", "-nostdlib", - ] - }, - "linker": { - "extraCLIOptions": [ - "-T", "stm32f4.ld", - "-e", "_start_elf", - "-Lllvm-toolchain/lib/clang-runtimes/arm-none-eabi/armv7m_soft_fpv4_sp_d16_exn_rtti/lib", - "-lc", - "-lclang_rt.builtins", - ] - } -} -``` - -At this point, linking will *almost* succeed, the only unresolved reference should be stdout/putchar: - -```shell -$ swift build --configuration release --triple armv7em-none-none-eabi --toolset toolset.json -ld.lld: error: undefined symbol: stdout ->>> referenced by putchar.c ->>> libc_tinystdio_putchar.c.o:(putchar) in archive llvm-toolchain/lib/clang-runtimes/arm-none-eabi/armv7m_soft_fpv4_sp_d16_exn_rtti/lib/libc.a -``` - -We're not going to actually try to provide the `stdout` symbol, instead let's provide our own custom `putchar` that will be routed to the UART. - -## Step 7: Add UART code - -Create a new file at `Sources/STM32BlinkLED/UART.swift`: - -```swift -import Registers - -extension STM32BlinkLED { - static func initUartOutput() { - // A9 is UART1 TX, which is relayed by ST-LINK over USB - - // Clock configuration - rcc.ahb1enr.modify { $0.raw.gpioaen = 1 } // Enable AHB clock to port A - rcc.apb2enr.modify { $0.raw.usart1en = 1 } // Enable APB clock to usart 1 - - // Configure A9 as UART1 TX - gpioa.moder.modify { $0.raw.moder9 = 0b10 } // Put Pin A9 into alternate function mode - gpioa.otyper.modify { $0.raw.ot9 = 0b0 } // Put Pin A9 into push pull - gpioa.ospeedr.modify { $0.raw.ospeedr9 = 0b00 } // Put Pin A9 into low speed - gpioa.pupdr.modify { $0.raw.pupdr9 = 0b00 } // Disable pull up/down on Pin A9 - gpioa.afrh.modify { $0.raw.afrh9 = 0b0111 } // Set alternate function usart1 on Pin A9 - - // Configure UART1, set the baud rate to 115200 (we boot at 16 MHz) - usart1.brr.modify { $0.raw.storage = 16_000_000 / 115_200 } - - usart1.cr1.modify { - $0.raw.ue = 1 // Enable USART 1 - $0.raw.te = 1 // Enable TX - } - } -} - -func waitTxBufferEmpty() { - // Spin while tx buffer not empty - while usart1.isr.read().raw.txe == 0 {} -} - -func tx(value: UInt8) { - usart1.tdr.write { $0.raw.tdr_field = UInt32(value) } -} - -@_cdecl("putchar") -public func putchar(_ value: CInt) -> CInt { - waitTxBufferEmpty() - tx(value: UInt8(value)) - waitTxBufferEmpty() - return 0 -} -``` - -## Step 8: Package up and Boot the Firmware - -The firmware should now build successfully, and we are finally ready to boot the firmware! We're going to use the `elf2hex` script to convert the ELF file that `swift build` produced into a format that's suitable for flashing, and then we'll use the `st-flash` tool from the opensource stlink package to actually run the firmware. We'll also use the `minicom` program to receive the text over UART, which will be presented on the host system as a serial port (also known as "COM port"). - -First let's make sure we have st-link and minicom installed: -```shell -$ brew install stlink -$ st-info --probe -... TODO -$ brew install minicom -$ minicom --version -minicom version 2.10 (compiled Feb 22 2025) -Copyright (C) Miquel van Smoorenburg. - -This program is free software; you can redistribute it and/or -modify it under the terms of the GNU General Public License -as published by the Free Software Foundation; either version -2 of the License, or (at your option) any later version. -``` - -Then let's fetch the elf2hex tool: - -```shell -$ curl -L "https://raw.githubusercontent.com/swiftlang/swift-embedded-examples/refs/heads/main/Tools/elf2hex.py" -O -$ chmod +x elf2hex.py -``` - -Next, let's build, package, and flash the firmware: - -```shell -$ swift build --configuration release --triple armv7em-none-none-eabi --toolset toolset.json -$ ./elf2hex.py .build/release/STM32BlinkLED .build/release/STM32BlinkLED.hex -``` - -```shell -$ ls -al .build/release/STM32BlinkLED.hex --rw-r--r-- 1 kuba staff 13K May 18 10:12 .build/release/STM32BlinkLED.hex -$ st-flash --connect-under-reset --format ihex write .build/release/STM32BlinkLED.hex -... TODO -``` - -Flashing should succeed and the firmware will run, but at this point, you won't see any UART output yet, and that's expected. While we've created the functions to initialize UART and transmit data, we haven't actually called the initialization routine from our main application. The LED won't blink either since we haven't configured the GPIO pins for it. In the next step, we'll update our main application file to call our UART initialization function and configure the LED pin properly. - -## Step 9: Configuring pins for UART and LED - -Now let's update the main application file to actually use our UART setup and blink an LED. Open the `Sources/STM32BlinkLED/STM32BlinkLED.swift` file and replace its contents with: - -```swift -import Registers - -@main -struct STM32BlinkLED { - static func main() { - // Initialize UART for output - initUartOutput() - - // Initialize LED (Pin I1 on STM32F746G-DISCO) - let ledPin: UInt32 = 1 - - // Enable clock for GPIO port I - rcc.ahb1enr.modify { $0.raw.gpioien = 1 } - - // Configure I1 as output - gpioi.moder.modify { $0.raw.moder1 = 0b01 } // Output mode - gpioi.otyper.modify { $0.raw.ot1 = 0b0 } // Push-pull mode - gpioi.ospeedr.modify { $0.raw.ospeedr1 = 0b00 } // Low speed - - print("Hello from Embedded Swift on STM32F7!") - - // Main loop - toggle LED and print message - var count = 0 - while true { - // Toggle the LED - let ledState = count % 2 == 0 - gpioi.bsrr.write { - if ledState { - $0.raw.bs1 = 1 // Set pin (LED on) - } else { - $0.raw.br1 = 1 // Reset pin (LED off) - } - } - - // Print status message every iteration - print("LED is now \(ledState ? "ON" : "OFF") - count: \(count)") - - // Delay using a simple counter - for _ in 0..<500_000 { - // Empty loop to create delay - // This is not accurate timing, just a busy-wait - } - - count += 1 - } - } -} -``` - -Now we need to create a Makefile to simplify the build and flash process. Create a file named `Makefile` in the project root: - -```makefile -.PHONY: build flash clean - -# Serial port for UART output viewing (change to match your system) -SERIAL_PORT ?= /dev/tty.usbmodem14203 - -build: - swift build --configuration release --triple armv7em-none-none-eabi --toolset toolset.json - ./elf2hex.py .build/release/STM32BlinkLED .build/release/STM32BlinkLED.hex - -flash: build - st-flash --connect-under-reset --format ihex write .build/release/STM32BlinkLED.hex - -monitor: - minicom -D $(SERIAL_PORT) -b 115200 - -clean: - swift package clean - rm -f .build/release/STM32BlinkLED.hex -``` - -Now you can build and flash your firmware with a single command: - -```shell -$ make flash -``` - -To view the UART output, determine which serial port your STM32F7 board appears as on your system. The ST-Link on the discovery board presents itself as a USB-to-Serial device. Once you've identified the correct port (update the SERIAL_PORT variable in the Makefile if needed), run: - -```shell -$ make monitor -``` - -You should now see "Hello from Embedded Swift on STM32F7!" followed by LED status messages in the minicom terminal, and the LED on your board should be blinking. - -## Conclusion - -Congratulations! You've successfully set up and programmed an STM32 microcontroller in baremetal mode using Embedded Swift. This simple LED blinking project demonstrates the fundamental concepts of embedded programming: - -1. Setting up hardware registers -2. Configuring GPIO pins -3. Creating delay functions -4. Implementing a main loop - -From here, you can expand the project to include more complex functionality like interfacing with sensors, implementing communication protocols, or adding user input. - -## Next Steps - -- Add button input to control the LED patterns -- Implement proper timer-based delays instead of the busy-wait approach -- Add UART communication to send debug messages to your computer -- Explore other peripherals like ADC, I2C, or SPI - -Happy embedded programming with Swift! diff --git a/Sources/EmbeddedSwift/Documentation.docc/GuidedExamples/macOSGuide.md b/Sources/EmbeddedSwift/Documentation.docc/GuidedExamples/macOSGuide.md deleted file mode 100644 index cc604e8d..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/GuidedExamples/macOSGuide.md +++ /dev/null @@ -1,72 +0,0 @@ -# Try out Embedded Swift on macOS - -Tutorial for building a simple program for your host OS with Embedded Swift - -## Overview - -While desktop operating systems like macOS and Linux are not the typical targets for Embedded Swift, you **absolutely can** build code for them using the Embedded Swift mode. This is useful for experimentation, trying out Embedded Swift, or to be able to iterate fast on an idea for some code that doesn't really need the physical device to work. - -The simplest program in Embedded Swift can just be a regular "Hello, World": - -```swift -// HelloEmbedded.swift -print("Hello, Embedded Swift 😊") -``` - -And building it into an executable can be done by calling the `swiftc` compiler directly, but we'll want to add flags to enable Embedded Swift, and also Whole Module Optimization. - -```shell -$ swiftc HelloEmbedded.swift -o HelloEmbedded -enable-experimental-feature Embedded -wmo -``` - -This will produce a regular executable binary, and we can execute it right away: - -```shell -$ ./HelloEmbedded -Hello, Embedded Swift 😊 -``` -Hooray! Our first *host-side* Embedded Swift program is working! - -## Details - -Looking closer, this binary *does not actually depend on the Swift runtime in the OS* (all Embedded Swift binaries carry their runtime+stdlib dependencies within), but it is still a *dynamically-linked executable*, so it's not fully standalone in the embedded sense: - -```shell -$ otool -L HelloEmbedded -HelloEmbedded: - /usr/lib/libSystem.B.dylib (compatibility version 1.0.0, current version 1000.0.0) -``` - -However, the singular object file that was used to build this executable was produced by the compiler in the same fashion that a real embedded build would. If we ask the compiler and linker to minimize the size of the outputs and to remove any unused code, we can observe that the binary has no dependencies other than `putchar` from `libSystem` and that the machine code section is very small (176 bytes in the `__text` section): - -```shell -$ swiftc HelloEmbedded.swift -o HelloEmbedded -enable-experimental-feature Embedded -wmo -Osize -Xlinker -dead_strip - -$ nm -um HelloEmbedded - (undefined) external _putchar (from libSystem) - -$ size -m HelloEmbedded -Segment __TEXT: 16384 - Section __text: 176 -... -``` - -In contrast, if compiled without the Embedded Swift flags, we can see the dependencies on the Swift runtime in the OS: - -```shell -$ swiftc HelloEmbedded.swift -o HelloEmbedded - -$ otool -L HelloEmbedded -HelloEmbedded: - /usr/lib/libSystem.B.dylib (compatibility version 1.0.0, current version 1000.0.0) - /usr/lib/swift/libswiftCore.dylib (compatibility version 1.0.0, current version 0.0.0) - /usr/lib/swift/libswiftSwiftOnoneSupport.dylib (compatibility version 1.0.0, current version 0.0.0) -``` - -## Where to go next - -- The [Embedded Swift Vision Document](https://github.com/swiftlang/swift-evolution/blob/main/visions/embedded-swift.md) will give you an overview of the approaches and goals of Embedded Swift, and also what exactly is in the Embedded Swift language subset. -- The [collection of Embedded Swift example projects](https://github.com/swiftlang/swift-embedded-examples) on GitHub shows on which embedded devices can Swift work today, and the examples can also be used as templates for your own projects. -- The [Embedded Swift User Manual](https://github.com/swiftlang/swift/blob/main/docs/EmbeddedSwift/UserManual.md) describes how to use the Embedded Swift compilation mode and how to interact with the compiler. -- The [Tools page](https://www.swift.org/tools/#editors) has guides for setting up Swift integration in your editor to enable features like indexing, autocomplete, jump-to-definition, and others. -- The [Swift forums](https://forums.swift.org/) are the best place to ask questions, give feedback or share your cool projects. diff --git a/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/Baremetal.md b/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/Baremetal.md deleted file mode 100644 index 0956b359..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/Baremetal.md +++ /dev/null @@ -1,244 +0,0 @@ -# Baremetal use of Embedded Swift - -Programming without an SDK for maximum control and minimal size - -## Overview - -Developing in "baremetal mode" means programming directly for the hardware without any operating system or SDK abstractions. This provides maximum control and minimum codesize, but requires deeper understanding of the hardware. - -Embedded Swift supports true baremetal development, where you directly program hardware peripherals by manipulating memory-mapped registers. This approach is suitable for: - -- Extremely resource-constrained environments -- Safety-critical applications that need deterministic behavior -- Projects requiring full control over every aspect of the hardware -- Educational purposes to understand how hardware and software interact - -## Key components of a baremetal project - -A complete baremetal project typically includes: - -1. **Startup code** - Sets up the initial environment before `main()` runs -2. **Interrupt vector table** - Maps hardware events to handler functions -3. **Linker script** - Defines memory layout and sections -4. **Hardware register definition code** - To interface with peripherals -5. **Runtime support** - E.g. implementations of functions like `memcpy` and `malloc` -6. **Application logic** - Your actual embedded application code - -For a full working example of all these components, see . The rest of this document provides general platform-independent guidance when working in baremetal mode. However, much of the problem space of baremetal development is outside of the scope of this documentation, and requires deeper familiary with your specific setup. This information is typically provided by your board vendor, the spec of the MCU, the ISA spec of the execution core, the C toolchain documentation, ELF file format spec, and other similar sources. - -## Hardware access patterns - -### 1. Direct memory access using pointers - -Note that using UnsafePointers to directly access registers at known addresses is not recommended in almost any situation because doing that correctly is tricky, it's inherently unsafe (and shifts the safety responsibility to the user) and can easily cause very hard to debug runtime problems. However, sometimes it might be neccessary to use this method. - -One common issue when directly accessing hardware registers is that the compiler may optimize away repeated reads or writes, thinking they're redundant. This is a problem that's inherent to pointers in most programming languages (including C and C++). - -```swift -// Accessing a register at address 0x40010000 -let gpioBase = 0x40010000 - -// ❌ Do not do this - the memory write might be optimized out -let gpioDataRegister = UnsafeMutablePointer(bitPattern: gpioBase)! -gpioDataRegister.pointee |= (1 << 5) // Set bit 5 -``` - -Hardware registers are volatile - their values can change independently of your program's execution (due to hardware events, interrupts, or peripheral operation). To ensure correct behavior, you must inform the compiler that these memory locations are volatile, preventing unwanted optimizations: - -```swift -// Need to use these flags: -enable-experimental-feature Volatile -import _Volatile - -// βœ… Use VolatileMappedRegister for volatile semantics -let gpioBase: UInt = 0x40010000 -let gpioDataRegister = VolatileMappedRegister(unsafeBitPattern: gpioBase) -... = gpioDataRegister.load() -gpioDataRegister.store(1 << 5) -``` - -Whenever possible, consider using Swift MMIO (see below) which does also provide proper volatile semantics, but more importantly provides type safety on individual registers and their fields. - -### 2. Using Swift MMIO for type-safe register access - -Swift MMIO provides strongly-typed access to memory-mapped hardware and can automatically generate register definitions from SVD files. It can provide a higher-level type-safe access to hardware registers, for example: - -```swift -// Type-safe register access -gpioa.odr.write { $0.odr5 = true } // Set pin 5 high -``` - -See [Swift MMIO](https://github.com/swiftlang/swift-mmio/) for details and for a guided example of using it. - -## Creating a linker script and data segment relocation - -A baremetal project requires a custom linker script to properly place code and data in memory. This is a relatively complex task to get right, and requires understanding of the memory map, flash and RAM setup of your target device, as well as understanding the ELF file format and what code/data sections do you expect your entire program to use. - -Besides just defining the position of code at runtime, a linker script needs to also: -- Handle and coordinate the initialization of "zero-fill" global variables (aka the BSS section) -- Handle and coordinate the initialization of non-zero writable global variables (copying initial values from flash to RAM) - -Here's an incomplete sketch of an example linker script: - -``` -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K -} - -SECTIONS -{ - .text : { *(.vectors*) ; *(.text*) } > flash - .rodata : { *(.rodata*) ; *(.got*) } > flash - .bss : { *(.bss*) } > sram ; needs runtime handling - .data : { *(.data*) } > sram AT>flash ; needs runtime handling - - ... -} -``` - -A sketch of an example corresponding startup code (in C): - -```c -void ResetISR(void) { - // Initialize bss section - uint8_t *bss = &__bss_start; - while (bss < &__bss_end) *bss = 0; - - // Initialize read-write data section - extern uint8_t __data_start_flash, __data_start, __data_end; - uint8_t *src = &__data_start_flash; - uint8_t *dst = &__data_start; - while (dst < &__data_end) *dst++ = *src++; - - // Call main - extern int main(void); - main(); - - // If main returns, loop forever - while(1); -} -``` - -Both these code snippets are not fully functional, they are only demonstrating the complexity of what the linker script and startup code need to do to initialize global variables. - -Tip: If this handling is not done correctly, a typical symptom is that global variables "don't work", i.e. reading from them doesn't yield the right value, and writing to them doesn't persist. A good way to double check this is by using a debugger, dumping memory at runtime and checking if it matches the virtual memory layout of the ELF file. - -## Vector table and interrupts - -The vector table is a critical component that maps hardware interrupts and exceptions to specific handler functions in your code. It's typically placed at the beginning of flash memory and contains function pointers that the processor uses when responding to various events. - -The processor automatically jumps to the appropriate handler when an interrupt occurs by indexing into this table. If you don't provide a specific handler, it's common to point to a default handler that can help with debugging. - -Example vector table structure: - -```c -// Vector table for ARM Cortex-M -__attribute__((section(".vectors"))) const void *VectorTable[] = { - (void*)0x20008000, // Initial stack pointer - ResetISR, // Reset handler - DefaultHandler, // NMI handler - DefaultHandler, // Hard fault handler - // Additional vectors as needed -}; -``` - -If you want to actually handle an interrupt (e.g. a GPIO or UART interrupt) in your Swift code, you can forward declare the function in C, and define it using `@cdecl` in Swift: - -```c -// In startup.c or header file -void UART1_IRQHandler(void); -``` - -```swift -// In Swift code -@_cdecl("UART1_IRQHandler") -func uartInterruptHandler() { - // Handle UART interrupt in Swift - // Clear interrupt flags, process received data, etc. -} -``` - -However, note that Swift currently does not provide any form of synchronization or "interrupt safety" for the code that executes the interrupt. Namely, if your interrupt handler modifies global variables that are also accessed by your main program, you need to be careful about data races and ensure proper synchronization (such as using atomic operations or disabling interrupts during critical sections). Additionally, interrupt handlers should be kept short and fast to avoid blocking other important system events. - -## Building a minimal project - -To build an Embedded Swift baremetal project with SwiftPM, you will need a setup like this: - -- Your main application target defined in Package.swift. -- A helper C code helper target defined in Package.swift - this will contain your C startup code, vector table and possibly an assembly file. -- Invoke `swift build` with a `--triple` argument that specifies the target CPU architecture and output object file format. -- Use a `toolset.json` file that defines the common Swift and C compilation flags, and linking flags. This will e.g. enable the Embedded Swift mode when compiling Swift code, and point the linker at the right linker script. - -Example file structure: - -``` -MyBaremetalProject/ -β”œβ”€β”€ Package.swift -β”œβ”€β”€ toolset.json -β”œβ”€β”€ Sources/ -β”‚ β”œβ”€β”€ MyApp/ -β”‚ β”‚ └── main.swift -β”‚ └── CStartup/ -β”‚ β”œβ”€β”€ startup.c -β”‚ β”œβ”€β”€ linker.ld -β”‚ └── include/ -β”‚ └── startup.h -└── README.md -``` - -Example toolset.json file: - -```json -{ - "schemaVersion": "1.0", - "swiftCompiler": { - "extraCLIOptions": [ - "-enable-experimental-feature", "Embedded", - "-Xclang-linker", "-nostdlib", - ] - }, - "linker": { - "extraCLIOptions": [ - "-T", "Sources/CStartup/linker.ld", - "--gc-sections", - ] - } -} -``` - -Example Package.swift file: - -```swift -// swift-tools-version: 5.9 -import PackageDescription - -let package = Package( - name: "MyBaremetalProject", - products: [ - .executable( - name: "MyBaremetalApp", - targets: ["MyApp"] - ) - ], - targets: [ - .executableTarget( - name: "MyApp", - dependencies: ["CStartup"], - swiftSettings: [ - .enableExperimentalFeature("Embedded") - ] - ), - .target( - name: "CStartup", - publicHeadersPath: "include" - ) - ] -) -``` - -Example compilation invocation: - -```bash -swift build --triple armv7em-none-eabi --toolset toolset.json -``` diff --git a/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegrateWithESP.md-wip b/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegrateWithESP.md-wip deleted file mode 100644 index e45c7af6..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegrateWithESP.md-wip +++ /dev/null @@ -1,3 +0,0 @@ -# ESP IDF - -🚧 Under construction... diff --git a/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegrateWithPico.md b/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegrateWithPico.md deleted file mode 100644 index 2087de6a..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegrateWithPico.md +++ /dev/null @@ -1,104 +0,0 @@ -# Raspberry Pi Pico SDK - -Setting up a project that can seamlessly use C APIs from the Pico SDK. - -> Note: Embedded Swift is experimental. Public releases of Swift do not support Embedded Swift, yet. See for details. - -Development for [Raspberry Pi Pico and Pico W](https://www.raspberrypi.com/products/raspberry-pi-pico/) normally uses the [Pico SDK](https://github.com/raspberrypi/pico-sdk) and the vendor provides several [sample projects in the pico-examples repository](https://github.com/raspberrypi/pico-examples). The SDK and sample project setup is described in: - -- [https://www.raspberrypi.com/documentation/microcontrollers/c_sdk.html#sdk-setup](https://www.raspberrypi.com/documentation/microcontrollers/c_sdk.html#sdk-setup) -- [https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf](https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf) - -Before trying to use Swift with the Pico SDK, make sure your environment works and can build the provided C/C++ sample projects. - -## CMake setup with a bridging header - -The Pico SDK is using CMake as its build system, and so the simplest way to integrate with it is to also use CMake to build a Swift firmware application on top of the SDK and the libraries from it. The following describes an example set up of that on a "blinky" example (code that just blinks the built-in LED). - -Let's create a directory with a Swift source file, a bridging header, and a CMake definition file: - -``` -./SwiftPicoBlinky/Main.swift -./SwiftPicoBlinky/BridgingHeader.h -./SwiftPicoBlinky/CMakeLists.txt -``` - -In `Main.swift`, let's add basic logic to initialize the GPIO port for the Pico's built-in LED, and then turn it on and off in a loop: - -```swift -@main -struct Main { - static func main() { - let led = UInt32(PICO_DEFAULT_LED_PIN) - gpio_init(led) - gpio_set_dir(led, /*out*/true) - while true { - gpio_put(led, true) - sleep_ms(250) - gpio_put(led, false) - sleep_ms(250) - } - } -} -``` - -Notice that we're using functions and variables defined in C in the Pico SDK. For that to be possible, the Swift compiler needs to have access to the C header files that define these functions and variables. The cleanest option would be to define a modulemap, but for simplicity let's just use a bridging header to make declarations visible in Swift without a module. `BridgingHeader.h` should contain: - -```c -#pragma once - -#include "pico/stdlib.h" -``` - -Finally, we need to define the application's build rules in CMake that will be using CMake logic from the Pico SDK. The following content of `CMakeLists.txt` leverages CMake 3.29's native Swift language support: - -```cmake -cmake_minimum_required(VERSION 3.29) -include($ENV{PICO_SDK_PATH}/external/pico_sdk_import.cmake) - -project(swift-blinky) -pico_sdk_init() - -# Enable Swift language support -enable_language(Swift) - -# Set Swift compilation mode to whole module optimization -set(CMAKE_Swift_COMPILATION_MODE wholemodule) - -add_executable(swift-blinky Main.swift) -set_target_properties(swift-blinky PROPERTIES - LINKER_LANGUAGE CXX) - -target_compile_options(swift-blinky PUBLIC "$<$:SHELL: - -enable-experimental-feature Embedded - -target armv6m-none-none-eabi -Xcc -mfloat-abi=soft -Xcc -fshort-enums - -Xfrontend -function-sections - -import-bridging-header ${CMAKE_CURRENT_LIST_DIR}/BridgingHeader.h ->") - -target_link_libraries(swift-blinky - pico_stdlib hardware_uart hardware_gpio -) - -pico_add_extra_outputs(swift-blinky) -``` - -## Configure and build - -With these three files, we can now configure and build a Swift firmware for the Pico: - -```bash -$ export PICO_BOARD=pico -$ export PICO_SDK_PATH= -$ export PICO_TOOLCHAIN_PATH= -$ ls -al --rw-r--r-- 1 kuba staff 39B Feb 2 22:08 BridgingHeader.h --rw-r--r-- 1 kuba staff 650B Feb 2 22:08 CMakeLists.txt --rw-r--r-- 1 kuba staff 262B Feb 2 22:08 Main.swift -$ mkdir build -$ cd build -$ cmake -S ../ -B . -G Ninja -$ ninja -v -``` - -This should produce several build artifacts in the `build/` subdirectory, include `swift-blinky.uf2`, which can be directly uploaded to the Pico by copying it into the fake Mass Storage Volume that the device presents when plugged over USB in BOOTSEL mode. diff --git a/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegrateWithZephyr.md b/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegrateWithZephyr.md deleted file mode 100644 index 2e03b401..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegrateWithZephyr.md +++ /dev/null @@ -1,425 +0,0 @@ -# Zephyr RTOS SDK - -Integrating Swift with Zephyr RTOS for embedded systems development - -[Zephyr](https://www.zephyrproject.org/) is an open-source RTOS for embedded systems that is sponsored by the Linux Foundation. Since it depends on CMake primarily for its build system, it can easily be integrated to be used with Embedded Swift. - -The following document outlines how to setup a Swift to Zephyr project for an emulated ARM Cortex M0, explaining a few key concepts along the way. For a complete working example on real hardware, however, refer to the [nrfx-blink-sdk](https://github.com/swiftlang/swift-embedded-examples/tree/main/nrfx-blink-sdk) project that is compatible with nRF or other boards. - -> Note: Embedded Swift is experimental. Public releases of Swift do not support Embedded Swift, yet. See for details. - -## Target Architecture Compatibility - -Zephyr [supports quite a few target architectures](https://docs.zephyrproject.org/latest/introduction/index.html), but not all are supported by Embedded Swift. Please refer to the following table for an overview of Zephyr-supported architectures that are supported by Swift, along with the correct target triple to use: - -| Architecture | Details | Swift Triple | -|--------------|---------------------|-------------------------| -| ARMv6-M | Cortex M0, M0+, M1 | armv6m-none-none-eabi | -| ARMv7-M | Cortex M3 | armv7-none-none-eabi | -| ARMv7-EM | Cortex M4/M4F, M7 | armv7em-none-none-eabi | -| ARMv8-M | Cortex M23-85 | aarch64-none-none-elf | -| Intel | 32-bit (i686) | i686-unknown-none-elf | -| Intel | 64-bit (x86_64) | x86_64-unknown-none-elf | -| RISC-V | 32-bit | riscv32-none-none-eabi | -| RISC-V | 64-bit | riscv64-none-none-eabi | - -## Zephyr Setup - -Before setting up a Swift project that works with Zephyr, you need to setup dependencies and a Zephyr workspace as per the [Getting Started Guide](https://docs.zephyrproject.org/latest/develop/getting_started/index.html). Regardless of your platform (macOS or Linux), ensure that you can build the blinky example without errors before starting with Swift integration: - -```bash -cd ~/zephyrproject/zephyr -west build -p always -b reel_board samples/basic/blinky -``` - -By default, the `main` revision of the Zephyr sources are checked out when calling `west init`, which contains pre-release and development changes that may cause instability and changing APIs that are not desirable. To checkout a specific release version of Zephyr, use the following commands: - -```bash -cd ~/zephyrproject/zephyr -git checkout v4.1.0 -west update -west packages pip --install - -# For older versions of Zephyr (pre 4.1.0), use: -pip install -r ~/zephyrproject/zephyr/scripts/requirements.txt -``` - -Refer to the [Zephyr Releases](https://docs.zephyrproject.org/latest/releases/index.html) page for more information on current and LTS releases. - -## Project Setup - -Once Zephyr is setup, the next step is to setup a project with the following files included: - -```plain -SwiftZephyrProject/src/BridgingHeader.h -SwiftZephyrProject/src/Main.swift -SwiftZephyrProject/src/Stubs.c -SwiftZephyrProject/CMakeLists.txt -SwiftZephyrProject/prj.conf -``` - -These are the minimum required files in order to build a Zephyr project. By convention, source files should be placed in the src/ subdirectory, but this is not a hard requirement. Also, `prj.conf` is required even if it is empty, or the project will not build. - -Inside of `src/BridgingHeader.h`, add the following content: - -```c -#pragma once - -#include -#include -``` - -The `src/Main.swift` file must contain a `static func main()` as follows: - -```swift -@main -struct Main { - static func main() { - print("Hello Zephyr from Swift!") - - while true { - k_msleep(1000) - print("Loop") - } - } -} -``` - -Since Embedded Swift requires `posix_memalign` to be defined, add the following to `src/Stubs.c` to define it: - -```c -#include -#include - -void *aligned_alloc(size_t alignment, size_t size); - -// Embedded Swift currently requires posix_memalign, but the C libraries in the -// Zephyr SDK do not provide it. Let's implement it and forward the calls to -// aligned_alloc(3). -int -posix_memalign(void **memptr, size_t alignment, size_t size) -{ - void *p = aligned_alloc(alignment, size); - if (p) { - *memptr = p; - return 0; - } - - return errno; -} -``` - -Finally, add the following line to `prj.conf` so that the output of `print()` statements is sent to stdout: - -```conf -CONFIG_STDOUT_CONSOLE=y -``` - -### CMakeLists.txt Setup - -The `CMakeLists.txt` setup is more involved and complex since target, compilation flags, and library linking must be specified for Swift. First, some initial setup and flags: - -```cmake -cmake_minimum_required(VERSION 3.29) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) - -# Enable "wmo" as needed by Embedded Swift -set(CMAKE_Swift_COMPILATION_MODE wholemodule) - -# Create a new project called "SwiftZephyrProject" and enable "Swift" as a supported language -project(SwiftZephyrProject Swift) -``` - -Next, set the compiler target to the arch you are building for. For this example we use `armv6m-none-none-eabi` which is compatible with the [Cortex-M0](https://docs.zephyrproject.org/latest/boards/qemu/cortex_m0/doc/index.html) which we will compile for in a later step. If you are targeting a different architecture, see the [Zephyr Target Architecture Compatibility](#zephyr-target-architecture-compatibility) to see which target triple to use. - -```cmake -# Use the armv6m-none-none-eabi target triple for Swift -set(CMAKE_Swift_COMPILER_TARGET armv6m-none-none-eabi) -``` - -After setting the target triple, some additional additional Swift compiler flags need to be defined. - -```cmake -# Set global Swift compiler flags -add_compile_options( - # Enable Embedded Swift - "$<$:SHELL:-enable-experimental-feature Embedded>" - - # Enable function sections to enable dead code stripping on elf - "$<$:SHELL:-Xfrontend -function-sections>" - - # Use software floating point operations matching GCC - "$<$:SHELL:-Xcc -mfloat-abi=soft>" - - # Use compacted C enums matching GCC - "$<$:SHELL:-Xcc -fshort-enums>" - - # Disable PIC - "$<$:SHELL:-Xcc -fno-pic>" - - # Disable PIE - "$<$:SHELL:-Xcc -fno-pie>" - - # Add Libc include paths - "$<$:SHELL:-Xcc -I -Xcc ${ZEPHYR_SDK_INSTALL_DIR}/arm-zephyr-eabi/picolibc/include>" -) -``` - -- NOTE: The `-mfloat-abi=soft` flag may need to change to `-mfloat-abi=hard` for ARM CPUs that support hard-float, such as the Cortex-M4F and Cortex-M7. This and the `-fshort-enums` flags are not required for non-ARM architectures such as Intel and RISC-V. - -There are quite a few other Zephyr flags that can also be imported (optional) in order to get Zephyr include paths and flags such `-mcpu`, `mthumb`, `-mabi`, and so on: - -```cmake -# Import TOOLCHAIN_C_FLAGS from Zephyr as -Xcc flags -foreach(flag ${TOOLCHAIN_C_FLAGS}) - # Skip flags that are not known to swiftc - string(FIND "${flag}" "-imacro" is_imacro) - string(FIND "${flag}" "-mfp16-format" is_mfp16) - if(NOT is_imacro EQUAL -1 OR NOT is_mfp16 EQUAL -1) - continue() - endif() - - add_compile_options("$<$:SHELL:-Xcc ${flag}>") -endforeach() -``` - -Next, add the following block to automatically grab Zephyr compilation flags (such as `-D__ZEPHYR__=1` and `-DKERNEL`) and set them as Swift compiler definitions. This is required to successfully build Swift code that works with Zephyr: - -```cmake -# Add definitions from Zephyr to -Xcc flags -get_target_property(ZEPHYR_DEFINES zephyr_interface INTERFACE_COMPILE_DEFINITIONS) -if(ZEPHYR_DEFINES) - foreach(flag ${ZEPHYR_DEFINES}) - # Ignore expressions like "$" - string(FIND "${flag}" "$<" start_of_expression) - if(NOT start_of_expression EQUAL -1) - continue() - endif() - - add_compile_options("$<$:SHELL:-Xcc -D${flag}>") - endforeach() -endif() -``` - -Finally, setup targets, libraries, and additional compile options: - -```cmake -target_sources(app PRIVATE src/Stubs.c) - -# The Swift code providing "main" needs to be in an OBJECT library (instead of STATIC library) to make sure it actually gets linker. -# A STATIC library would get dropped from linking because Zephyr provides a default weak empty main definition. -add_library(app_swift OBJECT src/Main.swift) - -add_dependencies(app_swift syscall_list_h_target) -target_compile_options(app_swift PRIVATE - -parse-as-library - - -Osize - - -Xfrontend -disable-stack-protector - - # FIXME: add dependency on BridgingHeader.h - -import-bridging-header ${CMAKE_CURRENT_LIST_DIR}/src/BridgingHeader.h -) - -# Copy include paths from C target to Swift target -target_include_directories(app_swift PRIVATE - "$" -) - -# Link the Swift target into the primary target -target_link_libraries(app PRIVATE app_swift) -``` - -### Building and Running - -To build the project, ensure that the Zephyr workspace is sourced first: - -```bash -source ~/zephyrproject/.venv/bin/activate -``` - -Run the following command to configure the project with CMake: - -```console -(.venv)> cmake -B build -G Ninja -DBOARD=qemu_cortex_m0 -DUSE_CCACHE=0 . -Loading Zephyr default modules (Zephyr base (cached)). -... --- Configuring done (7.6s) --- Generating done (0.2s) --- Build files have been written to: ~/SwiftZephyrProject/build -``` - -Then, the project can be built using `cmake --build`: - -```console -(.venv)> cmake --build build -[1/135] Preparing syscall dependency handling - -[2/135] Generating include/generated/zephyr/version.h --- Zephyr version: 4.1.0 (~/zephyrproject/zephyr), build: v4.1.0 -[130/135] Linking C executable zephyr/zephyr_pre0.elf -~/zephyr-sdk-0.17.0/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: warning: orphan section `.swift_modhash' from `app/libapp.a(Main.swift.obj)' being placed in section `.swift_modhash' -[135/135] Linking C executable zephyr/zephyr.elf -~/zephyr-sdk-0.17.0/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: warning: orphan section `.swift_modhash' from `app/libapp.a(Main.swift.obj)' being placed in section `.swift_modhash' -Memory region Used Size Region Size %age Used - FLASH: 14674 B 256 KB 5.60% - RAM: 4032 B 16 KB 24.61% - IDT_LIST: 0 GB 32 KB 0.00% -Generating files from ~/SwiftZephyrProject/build/zephyr/zephyr.elf for board: qemu_cortex_m0 -``` - -Finally, to run the example in the qemu emulator, use `ninja run`: - -```console -(.venv)> ninja -C build run -ninja: Entering directory `build' -[0/1] To exit from QEMU enter: 'CTRL+a, x'[QEMU] CPU: cortex-m0 -*** Booting Zephyr OS build v4.1.0 *** -Hello Zephyr from Swift! -Loop -Loop -Loop -``` - -Congrats, you now have a Swift project running using Zephyr! - -## West Integration - -Up to now we have setup a project that works perfectly fine when used with just CMake and Ninja. However, projects can also be integrated with West, which is the official CLI tool used for Zephyr projects. To use `west`, start by adding a `west.yml` file to the root of the project: - -```yml -manifest: - remotes: - - name: zephyrproject-rtos - url-base: https://github.com/zephyrproject-rtos - - projects: - - name: zephyr - remote: zephyrproject-rtos - revision: v4.1.0 - import: - name-allowlist: - - cmsis # required by the ARM port -``` - -- It is recommended to set the `revision` to a tagged version of Zephyr instead of always getting the main revision, which could have changing APIs. -- Also, please note that depending on what architecture you are targeting, you may need to add more/different targets to the `name-allowlist`, which is useful to get needed dependencies when compiling a project from a CI. See the [Zephyr workflow from swift-embedded-examples](https://github.com/swiftlang/swift-embedded-examples/blob/main/.github/workflows/build-zephyr.yml) for an example of setting up a CI for Zephyr. - -Next, set the `ZEPHYR_BASE` environment variable to tell `west` where the Zephyr workspace is located: - -```bash -(.venv)> export ZEPHYR_BASE=~/zephyrproject/zephyr -``` - -This could even be set as a global env variable for the user in `~/.bashrc` or `~/.zshrc` if desired. - -With this, `west` commands now can be run instead of having to use `cmake` and `ninja` to build and run: - -```bash -(.venv)> west build -b qemu_cortex_m0 . -p always -... -(.venv)> west build -t run --- west build: running target run -[0/1] To exit from QEMU enter: 'CTRL+a, x'[QEMU] CPU: cortex-m0 -*** Booting Zephyr OS build v4.1.0 *** -Hello Zephyr from Swift! -Loop -Loop -Loop -Loop -``` - -This setup may also be desirable since `west flash` is also available and can be used instead of invoking the flashing tools manually. - -If compiling a firmware for a real/physical board such as the `nrf52840dk/nrf52840`, `west flash` will work if the SEGGER J-Link host tools are installed. As an example, with the [nrfx-blink-sdk](../../../../nrfx-blink-sdk/) project: - -```console -> cd nrfx-blink-sdk -> source ~/zephyrproject/.venv/bin/activate -(.venv)> export ZEPHYR_BASE=~/zephyrproject/zephyr -(.venv)> west build -b nrf52840dk/nrf52840 . -p always -... -(.venv)> west flash -r jlink --- west flash: rebuilding -ninja: no work to do. --- west flash: using runner jlink --- runners.jlink: reset after flashing requested --- runners.jlink: JLink version: 8.26 --- runners.jlink: Flashing file: ~/swift-embedded-examples/nrfx-blink-sdk/build/zephyr/zephyr.hex -``` - -The `-r jlink` param is needed for this example to use the J-Link tools instead of using `nrfjprog`, which is the default for this board and also [deprecated](https://www.nordicsemi.com/Products/Development-tools/nRF-Command-Line-Tools). - -## Customizing the Linker - -The default linker configuration for building a Zephyr project from CMake works well for simple projects, but it can be customized as needed. The following sections show off some useful ways to customize linking Zephyr projects for Swift. - -### Stripping Out Unused Sections - -When compiling Swift to Zephyr projects, you may see some warnings about orphaned sections from the linker, like `.swift_modhash`: - -```console -~/zephyr-sdk-0.17.0/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: warning: orphan section `.swift_modhash' from `app/libapp.a(Main.swift.obj)' being placed in section `.swift_modhash' -[135/135] Linking C executable zephyr/zephyr.elf -~/zephyr-sdk-0.17.0/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: warning: orphan section `.swift_modhash' from `app/libapp.a(Main.swift.obj)' being placed in section `.swift_modhash -``` - -These types of warnings can be suppressed by passing a custom linker script to Zephyr that discards the sections, especially if they are not needed. For example, a script called `sections.ld` can be created at the root of the project with the following contents: - -```ld -/DISCARD/ : { *(.swift_modhash*) } -/DISCARD/ : { *(.ARM.attributes*) *(.ARM.exidx) } -``` - -Then, in `CMakeLists.txt`, add the following line: - -```cmake -# Remove unused sections -zephyr_linker_sources(SECTIONS "sections.ld") -``` - -This can also help to reduce the size of the output elf/binary since unused sections are stripped out. Be careful what sections you strip out, however, as some sections may be required. - -### Linking Swift Libraries - -This example adds the `swiftUnicodeDataTables` library from Swift to be linked into the Zephyr project. This is useful for linking unicode symbols when using strings. See for more information on this. - -In order to add additional linker params, the CMake `target_link_libraries` invocation can be used against `zephyr_pre0` and `zephyr_final`, like this: - -```cmake -# The code is using a String as a Dictionary key and thus require linking with libswiftUnicodeDataTables.a -# We compute the path where this file reside, taking into accout how the toolchain is referenced (Swiftly or TOOLCHAINS env variable). -find_program(SWIFTLY "swiftly") -IF(SWIFTLY) - execute_process(COMMAND swiftly use --print-location OUTPUT_VARIABLE toolchain_path) - cmake_path(SET additional_lib_path NORMALIZE "${toolchain_path}/usr/lib/swift/embedded/${CMAKE_Swift_COMPILER_TARGET}") -ELSE() - get_filename_component(compiler_bin_dir ${CMAKE_Swift_COMPILER} DIRECTORY) - cmake_path(SET additional_lib_path NORMALIZE "${compiler_bin_dir}/../lib/swift/embedded/${CMAKE_Swift_COMPILER_TARGET}") -ENDIF() - -target_link_directories(zephyr_pre0 PRIVATE "${additional_lib_path}") -target_link_libraries(zephyr_pre0 - -Wl,--whole-archive - swiftUnicodeDataTables - -Wl,--no-whole-archive - ) - -target_link_directories(zephyr_final PRIVATE "${additional_lib_path}") -target_link_libraries(zephyr_final - -Wl,--whole-archive - swiftUnicodeDataTables - -Wl,--no-whole-archive - ) -``` - -Extra code is required to find the right paths where the `swiftUnicodeDataTables.a` file is located, depending on how Swift is installed. - -When this is built, depending on the target architecture, warnings may then be printed about 32-bit enums, like this: - -```console -~/zephyr-sdk-0.17.0/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: warning: ~/.local/share/swiftly/toolchains/6.1.0/usr/lib/swift/embedded/armv6m-none-none-eabi/libswiftUnicodeDataTables.a(UnicodeWord.cpp.o) uses 32-bit enums yet the output is to use variable-size enums; use of enum values across objects may fail -``` - -To suppress these, simply add `-Wl,--no-enum-size-warning` to the `target_link_libraries` invocations. diff --git a/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegratingWithPlatforms.md b/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegratingWithPlatforms.md deleted file mode 100644 index 25163351..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/SDKSupport/IntegratingWithPlatforms.md +++ /dev/null @@ -1,106 +0,0 @@ -# Integrating with embedded platforms - -Understand the common patterns and approaches for integrating Swift with existing embedded systems - -## Overview - -Most embedded platforms provide SDKs consisting of drivers, libraries, and HAL (Hardware Abstraction Layer) components, typically written in the C language. Embedded Swift's C interoperability makes it possible to seamlessly integrate with these existing SDKs. - -This will enable using the entire API surface of an SDK directly from Swift, and is usually the easiest way to get started β€” because all functionality from the SDK will simply be available in your Swift code. Additionally, you could build Swift wrappers around the C SDK to provide a more idiomatic Swift API. This approach requires a bit more work but can result in a more ergonomic and type-safe interface, leveraging Swift's strong type system and safety features to prevent common errors when interacting with low-level hardware. - -Alternatively, for the most constrained environments or when you need complete control over the hardware, you can develop baremetal Swift applications without relying on any SDK. This approach requires implementing your own hardware initialization code and peripheral drivers directly in Swift or in C with Swift wrappers. Baremetal development gives you the maximum flexibility but requires deeper understanding of the target hardware. - -## Common Integration Patterns - -### Using a Bridging Header - -The simplest method for integrating with an embedded platform SDK is using a bridging header that imports the necessary C headers: - -```c -// BridgingHeader.h -#include "platform_specific_header.h" -#include "hardware_drivers.h" -``` - -When compiling Swift code, include this header: - -```bash -swiftc -enable-experimental-feature Embedded -wmo \ - -import-bridging-header BridgingHeader.h \ - -target \ - YourSwiftCode.swift -c -o output.o -``` - -Using a bridging header is discouraged when building an entire set of Swift libraries, but it's a very simple approach when the goal is to simply add a single Swift module into an existing software ecosystem. - -### Integrating with Build Systems - -Most embedded platforms use one of these build systems: - -1. **CMake**. -2. **Make**. -3. **Platform-specific build tools** - These usually allow integration of custom build steps. - -For (1) and (2), articles will be added to this documentation in the future. -For (3), it is always possible to manually invoke the Swift compiler (`swiftc`) with the right flags to produce a .o file that can be further used in the build system. Follow the article for details. - -### Matching platform's ISA and ABI - -When integrating Swift code with embedded platforms, it's crucial to properly match the Instruction Set Architecture (ISA) and Application Binary Interface (ABI) of the target system. The Swift compiler needs specific arguments to generate code that's compatible with the target microcontroller's architecture and calling conventions. Mismatches in these settings can lead to hard-to-debug issues or even complete failure to execute. - -Different microcontrollers require specific target triples and compiler flags to generate appropriate machine code. Here are common configurations you'll need: - -- **ARM Cortex-M0/M0+**: `-target armv6m-none-none-eabi` - For low-power, minimal ARM cores -- **ARM Cortex-M3/M4**: `-target armv7m-none-none-eabi` - For more capable 32-bit ARM cores -- **ARM Cortex-M4F** (with FPU): `-target armv7em-none-none-eabi -Xcc -mfloat-abi=hard -Xcc -mfpu=fpv4-sp-d16` - For cores with hardware floating-point -- **RISC-V**: `-target riscv32-none-none-elf` - For RISC-V based microcontrollers - -Additional important compiler flags to consider include: -- `-Xcc -mfloat-abi=[soft|hard]` - Determines whether floating-point arguments are passed in integer registers (soft) or floating-point registers (hard) -- `-Xcc -fshort-enums` - Makes enums use the smallest possible integer type, important for ABI compatibility with C code -- `-Xcc -mcpu=specific-cpu` - Specifies the exact CPU model for more optimized code generation -- `-Xfrontend -function-sections` - Places each function in its own section, enabling better dead code elimination during linking (this is a recommended setting for ELF targets) - -## Platform Examples - -### Raspberry Pi Pico - -For detailed instructions on integrating with the Raspberry Pi Pico SDK, see . - -### ESP32 - -Note that only chips based on RISC-V architecture (e.g. ESP32-C3, ESP32-C6, ESP32-P4) are supported with Embedded Swift. The Xtensa ISA (used in e.g. ESP8266 or ESP32-S2 and ESP32-S3) is not supported. - -For ESP microcontrollers using the ESP-IDF framework, an article will be added to this documentation in the future. - -### STM32 - -STM32 microcontrollers can be programmed with Embedded Swift in two ways: - -1. Using the STM32Cube HAL/LL libraries - This requires proper integration with the STM32Cube build system -2. Bare-metal approach - See for details - -### Zephyr - -For detailed documentation on how to integrate Embedded Swift with Zephyr, see . - -### Bare-metal Development - -For completely bare-metal development without any SDK, see for guidance on implementing the necessary startup code and hardware initialization. - -## Tips & tricks - -- Using `print()` in your Swift code creates a dependency on `putchar`, which must be provided by your platform. Make sure your embedded environment has this C standard library function available if you plan to use Swift's printing functionality. - -- For debugging, consider implementing a custom print handler by implementing a C function called `putchar` that redirects output to your debug channel (UART, SWO, RTT, etc.). Many embedded platforms already do that by default. - -- Use the `-g` compiler flag during development to include debug information, making it easier to trace issues with a debugger like GDB or OpenOCD. - -- Use optimization flags to control code size and performance: - - Use `-Onone` during development for faster compilation and better debugging - - Use `-O` or `-Osize` for release builds to minimize code size and maximize performance - - Consider `-Osize` specifically for extremely constrained memory environments - -- When you cannot use `-Onone` (e.g. because the resulting binary size exceeds the platform limits), but you still want to maximize debuggability, use the `-assert-config=Debug` flag. This enables assertions, and also extra debug prints on failures. - -Remember that Embedded Swift is designed to have minimal impact on the overall system architecture, allowing you to start with small Swift components and gradually expand your Swift codebase as you become more comfortable with the language in embedded contexts. diff --git a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Basics.md b/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Basics.md deleted file mode 100644 index ad18f8c5..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Basics.md +++ /dev/null @@ -1,76 +0,0 @@ -# Basics of using Embedded Swift - -Basic information for using Embedded Swift in typical embedded projects - -## Using Embedded Swift - -A typical setup and build and run cycle for an embedded development board involves: - -1. Getting an SDK with the C compilers, headers and libraries for the target -2. Building the C source code, and Swift source code into object files. -3. Linking all the libraries, C object files, and Swift object files. -4. Post-processing the linked firmware into a flashable format (UF2, BIN, HEX, or bespoke formats) -5. Uploading the flashable binary to the board over a USB cable using some vendor-provided JTAG/SWD tool, by copying it to a fake USB Mass Storage volume presented by the board or a custom platform bootloader. -6. Restarting the board, observing physical effects of the firmware (LEDs light up) or UART output over USB, or presence on network, etc. - -Many of these steps are out of scope for this document, because they are unrelated to Swift, and need to be set up and achieved independently of using Embedded Swift. For that, refer to your hardware vendor provided documentation. - -This document only focuses on (2) from the list above, and it's important that you first get familiar with the details of firmware development for your board without Swift in the mix. Even if you want to build a completely pure Swift firmware, you are still going to need the vendor provided tooling for linking, post-processing, uploading, etc. - -## Building code using Embedded Swift - -A basic way to build a set of Swift source files in Embedded Swift mode, is to simply give the compiler the following: -1. a target triple -2. the `-enable-experimental-feature Embedded` flag -3. the set of source files that form the input module: - -```shell -$ swiftc -target -enable-experimental-feature Embedded -wmo \ - input1.swift input2.swift ... -c -o output.o -``` - -On macOS, it's common to have Xcode installed, which comes with a toolchain that does not support Embedded Swift yet. Unless you download, install, and activate a swift.org toolchain, you'll see this error: - -```shell -$ swiftc input1.swift -enable-experimental-feature Embedded -wmo -:0: error: unable to load standard library for target 'arm64-apple-macosx15.0' -``` - -To resolve that, install a nightly Swift toolchain using Swiftly. You can follow the guide at for full instructions on that. - -## Building Swift firmware for a concrete embedded target - -To build Swift firmware (for now ignoring integration with SDKs, libraries and other pre-existing C code), we can use the `-target` argument to specify the CPU architecture. The target triple also decides whether the output object file will be an ELF file, or a Mach-O. For example: - -```bash -# To build an ARMv7 Mach-O object file: -$ swiftc -target armv7-apple-none-macho -enable-experimental-feature Embedded -wmo \ - input1.swift input2.swift ... -c -o output.o - -# To build an ARMv7 ELF object file: -$ swiftc -target armv7-none-none-eabi -enable-experimental-feature Embedded -wmo \ - input1.swift input2.swift ... -c -o output.o -``` - -Additionally, you probably want to specify additional Clang and/or LLVM flags to get the compiler to produce code for the exact ISA and ABI you need for your target. - -For example, a Raspberry Pi Pico / Pico W should target the ARMv6-M architecture via the `armv6m-*` target triple, but the `-mfloat-abi=soft` Clang option should also be used, and if you want to match ABI with libraries built with the GNU toolchain, you might also need `-fshort-enums`. To pass those to Swift, use the `-Xcc` prefix: - -```bash -# To build an ELF object file for ARMv6-M with soft float ABI (floating-point arguments passed in integer registers) and "short enums": -$ swiftc -target armv6m-none-none-eabi -enable-experimental-feature Embedded -wmo \ - -Xcc -mfloat-abi=soft -Xcc -fshort-enums \ - input1.swift input2.swift ... -c -o output.o -``` - -This might not be obvious: `-Xcc` flags are typically only used to alter behavior of the Clang importer, but passing flags to Clang this way also works to specify LLVM target options like selecting a specific CPU architecture (`-march`, `-mcpu`, `-mmcu`), FPU unit availability (`-mfpu`), which registers are used to pass floating-point values (`-mfloat-abi`), and others. - -## Integrating with existing embedded SDKs and build systems - -It's very common to integrate with existing SDKs in embedded development. This typically involves: - -1. **Setting up the build environment** with the right compiler flags, include paths, and linker settings to match the SDK's requirements. -2. **Creating a bridging header** that exposes the C functions and types from the SDK to Swift. -3. **Configuring the build system** to compile Swift code with the right flags and link it with the SDK's libraries. - -Most embedded SDKs provide a build system integration, commonly with CMake, Make, or their own custom build scripts. For details and concrete examples of how to integrate with more common platforms, SDKs and build systems, see . diff --git a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/ConditionalCompilation.md b/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/ConditionalCompilation.md deleted file mode 100644 index d5407187..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/ConditionalCompilation.md +++ /dev/null @@ -1,27 +0,0 @@ -# Conditionalizing compilation for Embedded Swift - -How to share code between Embedded Swift and full Swift using conditional compilation - -It's often useful to have source code be compilable under both regular Swift and Embedded Swift. The following syntax is available for that (but note that as the rest of Embedded Swift, it's experimental, subject to change and not considered source stable): - -```swift -func sayHello() { - #if hasFeature(Embedded) - print("I'm Embedded Swift") - #else - print("I'm regular Swift") - #endif -} -``` - -Additionally, you can also use an attribute (also experimental, and not source stable) to make entire functions, types and other declarations unavailable in Embedded Swift. This can be particularly useful to explicitly mark your own code (and also entire types and conformances) that relies on features unavailable in Embedded Swift, e.g. the Any type or Codable -- it is explicitly allowed to use those in unavailable contexts: - -```swift -@_unavailableInEmbedded -func useAny(_: Any) { ... } - -@_unavailableInEmbedded -extension MyStruct: Codable { - ... -} -``` diff --git a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Existentials.md b/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Existentials.md deleted file mode 100644 index 716e009f..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Existentials.md +++ /dev/null @@ -1,104 +0,0 @@ -# Existentials - -Restrictions on existentials ("any" types) that apply in Embedded Swift - -## Background - -Existentials (also known as "any" types) in Swift are a way to express a type-erased value, where the actual type is not known statically, and at runtime it can be any type that conforms to the specified protocol. Because the possible types can vary in size, the representation of such a value is an "existential container" and the actual represented value is stored either inline (when it fits) or indirectly as a pointer to a heap allocation. There are also multiple concrete representations of the existential container that are optimized for different constraints (e.g. for class-bound existentials, the value does not make sense to ever store inline, so the size of the container is matched to hold exactly one pointer). - -Existentials are restricted in Embedded Swift in multiple ways, for multiple reasons: - -- Value existentials are not allowed. This prevents the optimization barriers and heap allocation indirections that come with those existentials in regular Swift. -- Class-bound protocols can be used as an existential. This still circumvents the often undesired behavior of existentials where they allocate (and deallocate) storage on the heap for the inner value if it cannot fit in the inline buffer, because class references are always refcounted and references are shared. -- Unbounded generic methods cannot be called through an existential. - -## Class-bound existentials - -Embedded Swift allows and supports class-bound existentials: - -```swift -protocol ClassBoundProtocol: AnyObject { // βœ…, this means any type that wants to conform to ClassBoundProtocol must be a class type - func foo() -} - -class Base: ClassBoundProtocol { ... } -class Derived: Base { ... } // also conforms to ClassBoundProtocol -class Other: ClassBoundProtocol { ... } - -let existential: any ClassBoundProtocol = ... // βœ… -existential.foo() // βœ… -``` - -Note that protocols that are not class-bound cannot form existentials (in Embedded Swift): - -```swift -let existential: any Equatable = ... // ❌ - -class MyClass: Equatable { ... } -let existential: any Equatable = MyClass // ❌, not enough that the actual type is a class, the protocol itself must be class-bound -``` - -Class-bound existentials in Embedded Swift allow the "is" and "as!" / "as?" operators: - -```swift -let existential: any ClassBoundProtocol = ... -if existential is Base { ... } // βœ… -guard let concrete = existential as? Derived else { ... } // βœ… -let concrete = existential as! Derived // βœ…, and will trap at runtime if a different type is inside the existential -``` - -## Restrictions on class-bound existentials - -Class-bound existentials in Embedded Swift do come with some restrictions compared to class-bound existentials in regular Swift: - -- You cannot use an existential to call a unbounded generic method from the protocol. This is described in depth in [Embedded Swift -- Non-final generic methods](NonFinalGenericMethods.md). For example: -```swift -protocol ClassBoundProtocol: AnyObject { - func foo(t: T) -} - -let ex: any ClassBoundProtocol = ... // βœ… -ex.foo(t: 42) // ❌ -``` - -- You cannot use an existential composition of a class-bound protocol with a non-class-bound protocol. For example: -```swift -let ex: any ClassBoundProtocol & OtherClassBound = ... // βœ… -let ex: any ClassBoundProtocol & Equatable = ... // ❌ -``` - -## Alternatives to existentials - -When existentials are not possible (e.g. because you need struct types in an existential), or not desirable (e.g. because the indirection on a class-bound existential causes an observation performance degradation), consider one of the following alternatives (which all have different tradeoffs and code structure implications): - -**(1) Avoid using an existential, use generics instead** - -```swift -protocol MyProtocol { - func write(t: T) -} - -func usingProtocolAsGeneric(p: some MyProtocol) { - p.write(t: 42) // βœ… -} -``` - -**(2) If you only need a different type based on compile-time configuration (e.g. mocking for unit testing), use #if and typealiases:** -```swift -#if UNIT_TESTING -typealias HWAccess = MMIOBasedHWAccess -#else -typealias HWAccess = MockHWAccess -#endif - -let v = HWAccess() -``` - -**(3) If you only have a handful of tightly-coupled types that need to participate in an existential, use an enum instead:** -```swift -enum E { - case type1(Type1) - case type2(Type2) - case type3(Type3) -} -``` diff --git a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/ExternalDependencies.md b/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/ExternalDependencies.md deleted file mode 100644 index cf075059..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/ExternalDependencies.md +++ /dev/null @@ -1,37 +0,0 @@ -# External dependencies - -What external system dependencies should you expect from Embedded Swift compilations - -Embedded Swift minimizes external dependencies (i.e. functions that need to be available at link-time), but they still exist. There are generally two categories of dependencies: (1) functions that the Swift standard library or Embedded Swift runtime need to call, and (2) functions/symbols that are implicitly added by LLVM and the compiler pipeline. - -For (1), external dependencies are only used based on actual usage of the program under compilation: - -- instantiating a class, or using UnsafeMutablePointer.allocate() - - dependency: `int posix_memalign(void **, size_t, size_t);` - - dependency: `void free(void *);` -- using print() - - dependency: `int putchar(int);` -- using Hashable, Set, Dictionary, or random-number generating APIs - - dependency: `void arc4random_buf(void *, size_t);` - -For (2), external dependencies are also triggered by specific code needing them, but they are somewhat lower-level patterns where it might not be obvious that such patterns should cause external dependencies: - -- **basic memory copying and zeroing functions** - - usage added for a variety of reasons (e.g. using structs on the stack) - - dependency: `void *memset(void *, int, size_t);` - - dependency: `void *memcpy(void *, const void *, size_t);` -- **stack protectors** (aka stack cookies or stack canaries) - - dependency: `void *__stack_chk_guard;` - - dependency: `void __stack_chk_fail(void);` - - stack protectors can be disabled with `-disable-stack-protector` swiftc flag -- **atomics intrinsics** - - on CPU architectures that don't have direct load-acquire/store-release support in the ISA, LLVM calls helper functions for atomic operations - - needed by refcounting in the Embedded Swift runtime (so any class usage will trigger this dependency) - - also needed when using atomics from the Synchronization module -- **multiplication/division/modulo intrinsics** - - on CPU architectures that don't have direct support for the math operations in the ISA - - dependency (on Mach-O): `__divti3` - - dependency (on Mach-O): `__modti3` - - dependency (with EABI): `__aeabi_ldivmod` - -The user and/or the platform (via basic libraries like libc or compiler builtins) is expected to provide these well-known APIs. diff --git a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Libraries.md b/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Libraries.md deleted file mode 100644 index 22f5d2c3..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Libraries.md +++ /dev/null @@ -1,19 +0,0 @@ -# Libraries and modules in Embedded Swift - -Understand the library setup and linkage model of Embedded Swift - -Traditional library build and use model of Swift is that library code is compiled into a .swiftmodule, containing the interfaces, and a compiled library with binary code, either a .a static library or a .dylib/.so dynamic library. A client's build then uses the .swiftmodule at compile-time, and the static/dynamic library at link-time. - -The library model in Embedded Swift works slightly differently: All Swift source code of a library is promoted into being inlinable and visible to client builds (this is necessary for generic code, and beneficial for optimizations for non-generic code), and ends up serialized into the .swiftmodule, the interface of the library. Therefore, the compiled code of a library is never needed, and doesn't even need to be produced. For example: - -```bash -# Build the library, only as a .swiftmodule. Notice that we never build the .o or .a for the library. -$ swiftc -target -enable-experimental-feature Embedded -wmo \ - a.swift b.swift -module-name MyLibrary -emit-module -emit-module-path ./MyLibrary.swiftmodule - -# Build the client, "-I ." add the current directory to the module search path list -$ swiftc -target -enable-experimental-feature Embedded -wmo \ - client.swift -I . -c -o client.o -``` - -The Embedded Swift standard library is distributed in the toolchain the same way: It's strictly a .swiftmodule without any compiled code present anywhere. All the compiling into machine code is performed as part of the client's build. This has the major benefit that the client's build can provide additional ABI and ISA defining flags, such as the above-mentioned `-mfloat-abi`, `-fshort-enums`, `-mcpu`, `-march` flags, and these flags in the client's build will apply to all the library code (including standard library code) as well. diff --git a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/NonFinalGenericMethods.md b/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/NonFinalGenericMethods.md deleted file mode 100644 index c1fe357e..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/NonFinalGenericMethods.md +++ /dev/null @@ -1,125 +0,0 @@ -# Non-final generic methods - -Restrictions on unbound generic methods that apply in Embedded Swift - -## Background - -Embedded Swift relies on monomorphization to achieve its properties like not requiring type metadata. Monomorphization is mandatory specialization of all compiled code -- all function bodies get their concrete types substituted and all generics are "compiled out". This is based on passing type information top-down, i.e. from callers to callees, and specializing callees based on the concrete type provided by the caller. - -This type information passing from the caller is crucial. If it cannot happen for some reason, then monomorphization cannot happen. This is why Embedded Swift imposes restrictions on non-final generic methods on classes. - -## Non-final generic methods on classes (for subclassing-based dispatch) - -A non-final generic method on a class where the generic type does not come from the class context itself, is disallowed in Embedded Swift. This is because conservatively, the compiler must assume there could be subclasses with the method overridden. Monomorphization of a function call then cannot know the concrete target type. For example: - -```swift -class MyClass { - func write(t: T) { /* implementation */ } -} - -let instance: MyClass = ... // could be MyClass, or a subclass -instance.write(t: 42) // ❌ -``` - -Alternatives (which all have different tradeoffs and code structure implications): - -**(1) Make the class final (disallow subclassing):** - -```swift -final class MyClass { - func write(t: T) { /* implementation */ } -} - -let instance: MyClass = ... // can only be MyClass -instance.write(t: 42) // βœ… -``` - -**(2) Make the individual method final (disallow overriding in subclasses):** - -```swift -class MyClass { - final func write(t: T) { /* implementation */ } -} - -let instance: MyClass = ... // could be MyClass, or a subclass -instance.write(t: 42) // βœ… -``` - -**(3) Make the class generic instead of the method:** - -```swift -class MyClass { - func write(t: T) { /* implementation */ } -} - -let instance: MyClass = ... // can only be MyClass -instance.write(t: 42) // βœ… -``` - -**(4) Use overloading to support a set of concrete types:** - -```swift -class MyClass { - func write(t: Int) { /* implementation */ } - func write(t: Double) { /* implementation */ } -} - -let instance: MyClass = ... // could be MyClass, or a subclass -instance.write(t: 42) // βœ… -``` - -## Non-final generic methods on classes (for existential-based dispatch) - -A similar restriction applies to using class-bound existentials for dispatch method calls. Because at compile-time the target type is not statically known, monomorphization is not possible. For example: - -```swift -protocol MyProtocol: AnyObject { - func write(t: T) -} - -// existential ("any") is a runtime type-erasing box, we cannot specialize the target -// function for T == Int.self because we don't know the concrete type of "p" -func usingProtocolAsExistential(p: any MyProtocol) { - p.write(t: 42) // ❌ -} -``` - -Alternatives: - -**(1) Avoid using an existential, use generics instead** - -```swift -protocol MyProtocol: AnyObject { - func write(t: T) -} - -func usingProtocolAsGeneric(p: some MyProtocol) { - p.write(t: 42) // βœ… -} -``` - -**(2) Use a primary associated type** - -```swift -protocol MyProtocol: AnyObject { - associatedtype T - func write(t: T) -} - -func usingProtocolAsExistential(p: any MyProtocol) { - p.write(t: 42) // βœ… -} -``` - -**(3) Use overloading to support a set of concrete types:** - -```swift -protocol MyProtocol: AnyObject { - func write(t: Int) - func write(t: Double) -} - -func usingProtocolAsExistential(p: any MyProtocol) { - p.write(t: 42) // βœ… -} -``` diff --git a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Strings.md b/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Strings.md deleted file mode 100644 index f1e23bda..00000000 --- a/Sources/EmbeddedSwift/Documentation.docc/UsingEmbeddedSwift/Strings.md +++ /dev/null @@ -1,53 +0,0 @@ -# Strings - -How to enable full Unicode-compliant string support in Embedded Swift - -Both StaticString and String types are available in Embedded Swift. As is the case in desktop Swift, certain operations on strings require Unicode data tables for strict Unicode compliance. In Embedded Swift these data tables are provided as a separate static library (libUnicodeDataTables.a) that users need to link in manually – if they need to use these string operations. If the library is required, linking will fail due to missing on one or more of the following symbols: - -``` -_swift_stdlib_getAge -_swift_stdlib_getBinaryProperties -_swift_stdlib_getCaseMapping -_swift_stdlib_getComposition -_swift_stdlib_getDecompositionEntry -_swift_stdlib_getGeneralCategory -_swift_stdlib_getGraphemeBreakProperty -_swift_stdlib_getMapping -_swift_stdlib_getMphIdx -_swift_stdlib_getNameAlias -_swift_stdlib_getNormData -_swift_stdlib_getNumericType -_swift_stdlib_getNumericValue -_swift_stdlib_getScalarBitArrayIdx -_swift_stdlib_getScalarName -_swift_stdlib_getScript -_swift_stdlib_getScriptExtensions -_swift_stdlib_getSpecialMapping -_swift_stdlib_getWordBreakProperty -_swift_stdlib_isLinkingConsonant -_swift_stdlib_nfd_decompositions -``` - -To resolve this, link in the `libswiftUnicodeDataTables.a` that's in Swift toolchain's resource directory (`lib/swift/`) under the target triple that you're using: - -```bash -$ swiftc -target armv6m-none-none-eabi -enable-experimental-feature Embedded -wmo -c -o output.o -$ ld ... -o binary output.o $(dirname `which swiftc`)/../lib/swift/embedded/armv6m-none-none-eabi/libswiftUnicodeDataTables.a -``` - -**Unicode data tables are required for (list not exhaustive):** - -- Comparing String objects for equality -- Sorting Strings -- Using String's hash values, and in particular using String as dictionary keys -- Using String's `.count` property -- Using Unicode-aware string processing APIs (`.split()`, iterating characters, indexing) -- Using Unicode-aware conversion String APIs (`.uppercased()`, `.lowercased()`, etc.) - -**For contrast, unicode data tables are *not required for* (list not exhaustive):** - -- Using StaticString -- Creating, concatenating, string interpolating, and printing String objects -- Using `.utf8`, `.utf16`, and `.unicodeScalars` views of strings, including their .count property, using them as dictionary keys - -Manually linking `libswiftUnicodeDataTables.a` is required for several reasons, including acknowledging that the data tables are desirable: Since they have a non-negligible size, it's useful to be aware that you are using them. diff --git a/Sources/EmbeddedSwift/Empty.swift b/Sources/EmbeddedSwift/Empty.swift deleted file mode 100644 index 24ae0cad..00000000 --- a/Sources/EmbeddedSwift/Empty.swift +++ /dev/null @@ -1,12 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// This file is included so SwiftPM considers the target to be a Swift target. diff --git a/Tools/SVDs/README.md b/Tools/SVDs/README.md deleted file mode 100644 index 9186aa9e..00000000 --- a/Tools/SVDs/README.md +++ /dev/null @@ -1,8 +0,0 @@ -# SVDs - -The SVDs used in this repo have been copied from the following sources. - -| file | source | -|----------------------|----------------------------------------------------------------------| -| `rp2040.patched.svd` | https://github.com/rp-rs/rp2040-pac/blob/main/svd/rp2040.svd.patched | -| `rp2350.patched.svd` | https://github.com/rp-rs/rp235x-pac/blob/main/svd/RP2350.svd.patched | diff --git a/Tools/SVDs/rp2040.patched.svd b/Tools/SVDs/rp2040.patched.svd deleted file mode 100644 index a57dfd30..00000000 --- a/Tools/SVDs/rp2040.patched.svd +++ /dev/null @@ -1,22267 +0,0 @@ - - - Raspberry Pi - RP2040 - 0.1 - Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz\n - 264KB on-chip SRAM\n - 2 x UART, 2 x SPI controllers, 2 x I2C controllers, 16 x PWM channels\n - 1 x USB 1.1 controller and PHY, with host and device support\n - 8 x Programmable I/O (PIO) state machines for custom peripheral support\n - Supported input power 1.8-5.5V DC\n - Operating temperature -20C to +85C\n - Drag-and-drop programming using mass storage over USB\n - Low-power sleep and dormant modes\n - Accurate on-chip clock\n - Temperature sensor\n - Accelerated integer and floating-point libraries on-chip - Copyright (c) 2020 Raspberry Pi (Trading) Ltd.\n - \n - SPDX-License-Identifier: BSD-3-Clause - - CM0PLUS - r0p1 - little - true - false - true - 2 - false - 26 - - 8 - 32 - - - XIP_CTRL - 1 - QSPI flash execute-in-place block - 0x14000000 - 0x20 - - 0x0 - 0x20 - registers - - - XIP_IRQ - 6 - - - - CTRL - Cache control - 0x0 - 0x00000003 - - - POWER_DOWN - When 1, the cache memories are powered down. They retain state,\n - but can not be accessed. This reduces static power dissipation.\n - Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n - be enabled when powered down.\n - Cache-as-SRAM accesses will produce a bus error response when\n - the cache is powered down. - [3:3] - read-write - - - ERR_BADWRITE - When 1, writes to any alias other than 0x0 (caching, allocating)\n - will produce a bus fault. When 0, these writes are silently ignored.\n - In either case, writes to the 0x0 alias will deallocate on tag match,\n - as usual. - [1:1] - read-write - - - EN - When 1, enable the cache. When the cache is disabled, all XIP accesses\n - will go straight to the flash, without querying the cache. When enabled,\n - cacheable XIP accesses will query the cache, and the flash will\n - not be accessed if the tag matches and the valid bit is set.\n\n - If the cache is enabled, cache-as-SRAM accesses have no effect on the\n - cache data RAM, and will produce a bus error response. - [0:0] - read-write - - - - - FLUSH - Cache Flush control - 0x4 - 0x00000000 - - - FLUSH - Write 1 to flush the cache. This clears the tag memory, but\n - the data memory retains its contents. (This means cache-as-SRAM\n - contents is not affected by flush or reset.)\n - Reading will hold the bus (stall the processor) until the flush\n - completes. Alternatively STAT can be polled until completion. - [0:0] - read-write - clear - - - - - STAT - Cache Status - 0x8 - 0x00000002 - - - FIFO_FULL - When 1, indicates the XIP streaming FIFO is completely full.\n - The streaming FIFO is 2 entries deep, so the full and empty\n - flag allow its level to be ascertained. - [2:2] - read-only - - - FIFO_EMPTY - When 1, indicates the XIP streaming FIFO is completely empty. - [1:1] - read-only - - - FLUSH_READY - Reads as 0 while a cache flush is in progress, and 1 otherwise.\n - The cache is flushed whenever the XIP block is reset, and also\n - when requested via the FLUSH register. - [0:0] - read-only - - - - - CTR_HIT - Cache Hit counter\n - A 32 bit saturating counter that increments upon each cache hit,\n - i.e. when an XIP access is serviced directly from cached data.\n - Write any value to clear. - 0xC - read-write - 0x00000000 - oneToClear - - - CTR_ACC - Cache Access counter\n - A 32 bit saturating counter that increments upon each XIP access,\n - whether the cache is hit or not. This includes noncacheable accesses.\n - Write any value to clear. - 0x10 - read-write - 0x00000000 - oneToClear - - - STREAM_ADDR - FIFO stream address - 0x14 - 0x00000000 - - - STREAM_ADDR - The address of the next word to be streamed from flash to the streaming FIFO.\n - Increments automatically after each flash access.\n - Write the initial access address here before starting a streaming read. - [31:2] - read-write - - - - - STREAM_CTR - FIFO stream control - 0x18 - 0x00000000 - - - STREAM_CTR - Write a nonzero value to start a streaming read. This will then\n - progress in the background, using flash idle cycles to transfer\n - a linear data block from flash to the streaming FIFO.\n - Decrements automatically (1 at a time) as the stream\n - progresses, and halts on reaching 0.\n - Write 0 to halt an in-progress stream, and discard any in-flight\n - read, so that a new stream can immediately be started (after\n - draining the FIFO and reinitialising STREAM_ADDR) - [21:0] - read-write - - - - - STREAM_FIFO - FIFO stream data\n - Streamed data is buffered here, for retrieval by the system DMA.\n - This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n - the DMA to bus stalls caused by other XIP traffic. - 0x1C - read-only - 0x00000000 - - - - - XIP_SSI - 1 - DW_apb_ssi has the following features:\n - * APB interface - Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n - * APB3 and APB4 protocol support.\n - * Scalable APB data bus width - Supports APB data bus widths of 8, 16, and 32 bits.\n - * Serial-master or serial-slave operation - Enables serial communication with serial-master or serial-slave peripheral devices.\n - * Programmable Dual/Quad/Octal SPI support in Master Mode.\n - * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n - * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n - * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n - * DMA Controller Interface - Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n - * Independent masking of interrupts - Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n - * Multi-master contention detection - Informs the processor of multiple serial-master accesses on the serial bus.\n - * Bypass of meta-stability flip-flops for synchronous clocks - When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n - * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n - * Programmable features:\n - - Serial interface operation - Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n - - Clock bit-rate - Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n - - Data Item size (4 to 32 bits) - Item size of each data transfer under the control of the programmer.\n - * Configured features:\n - - FIFO depth - 16 words deep. The FIFO width is fixed at 32 bits.\n - - 1 slave select output.\n - - Hardware slave-select - Dedicated hardware slave-select line.\n - - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n - - Interrupt polarity - active high interrupt lines.\n - - Serial clock polarity - low serial-clock polarity directly after reset.\n - - Serial clock phase - capture on first edge of serial-clock directly after reset. - 0x18000000 - 0x20 - - 0x0 - 0x100 - registers - - - - CTRLR0 - Control register 0 - 0x0 - 0x00000000 - - - SSTE - Slave select toggle enable - [24:24] - read-write - - - SPI_FRF - SPI frame format - [22:21] - read-write - - - STD - Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex - 0 - - - DUAL - Dual-SPI frame format; two bits per SCK, half-duplex - 1 - - - QUAD - Quad-SPI frame format; four bits per SCK, half-duplex - 2 - - - - - DFS_32 - Data frame size in 32b transfer mode\n - Value of n -> n+1 clocks per frame. - [20:16] - read-write - - - CFS - Control frame size\n - Value of n -> n+1 clocks per frame. - [15:12] - read-write - - - SRL - Shift register loop (test mode) - [11:11] - read-write - - - SLV_OE - Slave output enable - [10:10] - read-write - - - TMOD - Transfer mode - [9:8] - read-write - - - TX_AND_RX - Both transmit and receive - 0 - - - TX_ONLY - Transmit only (not for FRF == 0, standard SPI mode) - 1 - - - RX_ONLY - Receive only (not for FRF == 0, standard SPI mode) - 2 - - - EEPROM_READ - EEPROM read mode (TX then RX; RX starts after control data TX'd) - 3 - - - - - SCPOL - Serial clock polarity - [7:7] - read-write - - - SCPH - Serial clock phase - [6:6] - read-write - - - FRF - Frame format - [5:4] - read-write - - - DFS - Data frame size - [3:0] - read-write - - - - - CTRLR1 - Master Control register 1 - 0x4 - 0x00000000 - - - NDF - Number of data frames - [15:0] - read-write - - - - - SSIENR - SSI Enable - 0x8 - 0x00000000 - - - SSI_EN - SSI enable - [0:0] - read-write - - - - - MWCR - Microwire Control - 0xC - 0x00000000 - - - MHS - Microwire handshaking - [2:2] - read-write - - - MDD - Microwire control - [1:1] - read-write - - - MWMOD - Microwire transfer mode - [0:0] - read-write - - - - - SER - Slave enable - 0x10 - 0x00000000 - - - SER - For each bit:\n - 0 -> slave not selected\n - 1 -> slave selected - [0:0] - read-write - - - - - BAUDR - Baud rate - 0x14 - 0x00000000 - - - SCKDV - SSI clock divider - [15:0] - read-write - - - - - TXFTLR - TX FIFO threshold level - 0x18 - 0x00000000 - - - TFT - Transmit FIFO threshold - [7:0] - read-write - - - - - RXFTLR - RX FIFO threshold level - 0x1C - 0x00000000 - - - RFT - Receive FIFO threshold - [7:0] - read-write - - - - - TXFLR - TX FIFO level - 0x20 - 0x00000000 - - - TFTFL - Transmit FIFO level - [7:0] - read-only - - - - - RXFLR - RX FIFO level - 0x24 - 0x00000000 - - - RXTFL - Receive FIFO level - [7:0] - read-only - - - - - SR - Status register - 0x28 - 0x00000000 - - - DCOL - Data collision error - [6:6] - read-only - - - TXE - Transmission error - [5:5] - read-only - - - RFF - Receive FIFO full - [4:4] - read-only - - - RFNE - Receive FIFO not empty - [3:3] - read-only - - - TFE - Transmit FIFO empty - [2:2] - read-only - - - TFNF - Transmit FIFO not full - [1:1] - read-only - - - BUSY - SSI busy flag - [0:0] - read-only - - - - - IMR - Interrupt mask - 0x2C - 0x00000000 - - - MSTIM - Multi-master contention interrupt mask - [5:5] - read-write - - - RXFIM - Receive FIFO full interrupt mask - [4:4] - read-write - - - RXOIM - Receive FIFO overflow interrupt mask - [3:3] - read-write - - - RXUIM - Receive FIFO underflow interrupt mask - [2:2] - read-write - - - TXOIM - Transmit FIFO overflow interrupt mask - [1:1] - read-write - - - TXEIM - Transmit FIFO empty interrupt mask - [0:0] - read-write - - - - - ISR - Interrupt status - 0x30 - 0x00000000 - - - MSTIS - Multi-master contention interrupt status - [5:5] - read-only - - - RXFIS - Receive FIFO full interrupt status - [4:4] - read-only - - - RXOIS - Receive FIFO overflow interrupt status - [3:3] - read-only - - - RXUIS - Receive FIFO underflow interrupt status - [2:2] - read-only - - - TXOIS - Transmit FIFO overflow interrupt status - [1:1] - read-only - - - TXEIS - Transmit FIFO empty interrupt status - [0:0] - read-only - - - - - RISR - Raw interrupt status - 0x34 - 0x00000000 - - - MSTIR - Multi-master contention raw interrupt status - [5:5] - read-only - - - RXFIR - Receive FIFO full raw interrupt status - [4:4] - read-only - - - RXOIR - Receive FIFO overflow raw interrupt status - [3:3] - read-only - - - RXUIR - Receive FIFO underflow raw interrupt status - [2:2] - read-only - - - TXOIR - Transmit FIFO overflow raw interrupt status - [1:1] - read-only - - - TXEIR - Transmit FIFO empty raw interrupt status - [0:0] - read-only - - - - - TXOICR - TX FIFO overflow interrupt clear - 0x38 - 0x00000000 - - - TXOICR - Clear-on-read transmit FIFO overflow interrupt - [0:0] - read-only - - - - - RXOICR - RX FIFO overflow interrupt clear - 0x3C - 0x00000000 - - - RXOICR - Clear-on-read receive FIFO overflow interrupt - [0:0] - read-only - - - - - RXUICR - RX FIFO underflow interrupt clear - 0x40 - 0x00000000 - - - RXUICR - Clear-on-read receive FIFO underflow interrupt - [0:0] - read-only - - - - - MSTICR - Multi-master interrupt clear - 0x44 - 0x00000000 - - - MSTICR - Clear-on-read multi-master contention interrupt - [0:0] - read-only - - - - - ICR - Interrupt clear - 0x48 - 0x00000000 - - - ICR - Clear-on-read all active interrupts - [0:0] - read-only - - - - - DMACR - DMA control - 0x4C - 0x00000000 - - - TDMAE - Transmit DMA enable - [1:1] - read-write - - - RDMAE - Receive DMA enable - [0:0] - read-write - - - - - DMATDLR - DMA TX data level - 0x50 - 0x00000000 - - - DMATDL - Transmit data watermark level - [7:0] - read-write - - - - - DMARDLR - DMA RX data level - 0x54 - 0x00000000 - - - DMARDL - Receive data watermark level (DMARDLR+1) - [7:0] - read-write - - - - - IDR - Identification register - 0x58 - 0x51535049 - - - IDCODE - Peripheral dentification code - [31:0] - read-only - - - - - SSI_VERSION_ID - Version ID - 0x5C - 0x3430312A - - - SSI_COMP_VERSION - SNPS component version (format X.YY) - [31:0] - read-only - - - - - DR0 - Data Register 0 (of 36) - 0x60 - 0x00000000 - - - DR - First data register of 36 - [31:0] - read-write - - - - - RX_SAMPLE_DLY - RX sample delay - 0xF0 - 0x00000000 - - - RSD - RXD sample delay (in SCLK cycles) - [7:0] - read-write - - - - - SPI_CTRLR0 - SPI control - 0xF4 - 0x03000000 - - - XIP_CMD - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) - [31:24] - read-write - - - SPI_RXDS_EN - Read data strobe enable - [18:18] - read-write - - - INST_DDR_EN - Instruction DDR transfer enable - [17:17] - read-write - - - SPI_DDR_EN - SPI DDR transfer enable - [16:16] - read-write - - - WAIT_CYCLES - Wait cycles between control frame transmit and data reception (in SCLK cycles) - [15:11] - read-write - - - INST_L - Instruction length (0/4/8/16b) - [9:8] - read-write - - - NONE - No instruction - 0 - - - 4B - 4-bit instruction - 1 - - - 8B - 8-bit instruction - 2 - - - 16B - 16-bit instruction - 3 - - - - - ADDR_L - Address length (0b-60b in 4b increments) - [5:2] - read-write - - - TRANS_TYPE - Address and instruction transfer format - [1:0] - read-write - - - 1C1A - Command and address both in standard SPI frame format - 0 - - - 1C2A - Command in standard SPI format, address in format specified by FRF - 1 - - - 2C2A - Command and address both in format specified by FRF (e.g. Dual-SPI) - 2 - - - - - - - TXD_DRIVE_EDGE - TX drive edge - 0xF8 - 0x00000000 - - - TDE - TXD drive edge - [7:0] - read-write - - - - - - - SYSINFO - 1 - 0x40000000 - 0x20 - - 0x0 - 0x1000 - registers - - - - CHIP_ID - JEDEC JEP-106 compliant chip identifier. - 0x0 - 0x00000000 - - - REVISION - [31:28] - read-only - - - PART - [27:12] - read-only - - - MANUFACTURER - [11:0] - read-only - - - - - PLATFORM - Platform register. Allows software to know what environment it is running in. - 0x4 - 0x00000000 - - - ASIC - [1:1] - read-only - - - FPGA - [0:0] - read-only - - - - - GITREF_RP2040 - Git hash of the chip source. Used to identify chip version. - 0x40 - read-only - 0x00000000 - - - - - SYSCFG - 1 - Register block for various chip control signals - 0x40004000 - 0x20 - - 0x0 - 0x1000 - registers - - - - PROC0_NMI_MASK - Processor core 0 NMI source mask\n - Set a bit high to enable NMI from that IRQ - 0x0 - read-write - 0x00000000 - - - PROC1_NMI_MASK - Processor core 1 NMI source mask\n - Set a bit high to enable NMI from that IRQ - 0x4 - read-write - 0x00000000 - - - PROC_CONFIG - Configuration for processors - 0x8 - 0x10000000 - - - PROC1_DAP_INSTID - Configure proc1 DAP instance ID.\n - Recommend that this is NOT changed until you require debug access in multi-chip environment\n - WARNING: do not set to 15 as this is reserved for RescueDP - [31:28] - read-write - - - PROC0_DAP_INSTID - Configure proc0 DAP instance ID.\n - Recommend that this is NOT changed until you require debug access in multi-chip environment\n - WARNING: do not set to 15 as this is reserved for RescueDP - [27:24] - read-write - - - PROC1_HALTED - Indication that proc1 has halted - [1:1] - read-only - - - PROC0_HALTED - Indication that proc0 has halted - [0:0] - read-only - - - - - PROC_IN_SYNC_BYPASS - For each bit, if 1, bypass the input synchronizer between that GPIO\n - and the GPIO input register in the SIO. The input synchronizers should\n - generally be unbypassed, to avoid injecting metastabilities into processors.\n - If you're feeling brave, you can bypass to save two cycles of input\n - latency. This register applies to GPIO 0...29. - 0xC - 0x00000000 - - - PROC_IN_SYNC_BYPASS - [29:0] - read-write - - - - - PROC_IN_SYNC_BYPASS_HI - For each bit, if 1, bypass the input synchronizer between that GPIO\n - and the GPIO input register in the SIO. The input synchronizers should\n - generally be unbypassed, to avoid injecting metastabilities into processors.\n - If you're feeling brave, you can bypass to save two cycles of input\n - latency. This register applies to GPIO 30...35 (the QSPI IOs). - 0x10 - 0x00000000 - - - PROC_IN_SYNC_BYPASS_HI - [5:0] - read-write - - - - - DBGFORCE - Directly control the SWD debug port of either processor - 0x14 - 0x00000066 - - - PROC1_ATTACH - Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. - [7:7] - read-write - - - PROC1_SWCLK - Directly drive processor 1 SWCLK, if PROC1_ATTACH is set - [6:6] - read-write - - - PROC1_SWDI - Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set - [5:5] - read-write - - - PROC1_SWDO - Observe the value of processor 1 SWDIO output. - [4:4] - read-only - - - PROC0_ATTACH - Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. - [3:3] - read-write - - - PROC0_SWCLK - Directly drive processor 0 SWCLK, if PROC0_ATTACH is set - [2:2] - read-write - - - PROC0_SWDI - Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set - [1:1] - read-write - - - PROC0_SWDO - Observe the value of processor 0 SWDIO output. - [0:0] - read-only - - - - - MEMPOWERDOWN - Control power downs to memories. Set high to power down memories.\n - Use with extreme caution - 0x18 - 0x00000000 - - - ROM - [7:7] - read-write - - - USB - [6:6] - read-write - - - SRAM5 - [5:5] - read-write - - - SRAM4 - [4:4] - read-write - - - SRAM3 - [3:3] - read-write - - - SRAM2 - [2:2] - read-write - - - SRAM1 - [1:1] - read-write - - - SRAM0 - [0:0] - read-write - - - - - - - CLOCKS - 1 - 0x40008000 - 0x20 - - 0x0 - 0x1000 - registers - - - CLOCKS_IRQ - 17 - - - - CLK_GPOUT0_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x0 - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT0_DIV - Clock divisor, can be changed on-the-fly - 0x4 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT0_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x8 - read-only - 0x00000001 - - - CLK_GPOUT1_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0xC - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT1_DIV - Clock divisor, can be changed on-the-fly - 0x10 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT1_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x14 - read-only - 0x00000001 - - - CLK_GPOUT2_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x18 - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT2_DIV - Clock divisor, can be changed on-the-fly - 0x1C - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT2_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x20 - read-only - 0x00000001 - - - CLK_GPOUT3_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x24 - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT3_DIV - Clock divisor, can be changed on-the-fly - 0x28 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT3_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x2C - read-only - 0x00000001 - - - CLK_REF_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x30 - 0x00000000 - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [6:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - - - SRC - Selects the clock source glitchlessly, can be changed on-the-fly - [1:0] - read-write - - - rosc_clksrc_ph - 0 - - - clksrc_clk_ref_aux - 1 - - - xosc_clksrc - 2 - - - - - - - CLK_REF_DIV - Clock divisor, can be changed on-the-fly - 0x34 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [9:8] - read-write - - - - - CLK_REF_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. - 0x38 - read-only - 0x00000001 - - - CLK_SYS_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x3C - 0x00000000 - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_pll_usb - 1 - - - rosc_clksrc - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - SRC - Selects the clock source glitchlessly, can be changed on-the-fly - [0:0] - read-write - - - clk_ref - 0 - - - clksrc_clk_sys_aux - 1 - - - - - - - CLK_SYS_DIV - Clock divisor, can be changed on-the-fly - 0x40 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_SYS_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. - 0x44 - read-only - 0x00000001 - - - CLK_PERI_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x48 - 0x00000000 - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clk_sys - 0 - - - clksrc_pll_sys - 1 - - - clksrc_pll_usb - 2 - - - rosc_clksrc_ph - 3 - - - xosc_clksrc - 4 - - - clksrc_gpin0 - 5 - - - clksrc_gpin1 - 6 - - - - - - - CLK_PERI_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x50 - read-only - 0x00000001 - - - CLK_USB_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x54 - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_USB_DIV - Clock divisor, can be changed on-the-fly - 0x58 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [9:8] - read-write - - - - - CLK_USB_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x5C - read-only - 0x00000001 - - - CLK_ADC_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x60 - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_ADC_DIV - Clock divisor, can be changed on-the-fly - 0x64 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [9:8] - read-write - - - - - CLK_ADC_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x68 - read-only - 0x00000001 - - - CLK_RTC_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x6C - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_RTC_DIV - Clock divisor, can be changed on-the-fly - 0x70 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_RTC_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x74 - read-only - 0x00000001 - - - CLK_SYS_RESUS_CTRL - 0x78 - 0x000000FF - - - CLEAR - For clearing the resus after the fault that triggered it has been corrected - [16:16] - read-write - - - FRCE - Force a resus, for test purposes only - [12:12] - read-write - - - ENABLE - Enable resus - [8:8] - read-write - - - TIMEOUT - This is expressed as a number of clk_ref cycles\n - and must be >= 2x clk_ref_freq/min_clk_tst_freq - [7:0] - read-write - - - - - CLK_SYS_RESUS_STATUS - 0x7C - 0x00000000 - - - RESUSSED - Clock has been resuscitated, correct the error then send ctrl_clear=1 - [0:0] - read-only - - - - - FC0_REF_KHZ - Reference clock frequency in kHz - 0x80 - 0x00000000 - - - FC0_REF_KHZ - [19:0] - read-write - - - - - FC0_MIN_KHZ - Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags - 0x84 - 0x00000000 - - - FC0_MIN_KHZ - [24:0] - read-write - - - - - FC0_MAX_KHZ - Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags - 0x88 - 0x01FFFFFF - - - FC0_MAX_KHZ - [24:0] - read-write - - - - - FC0_DELAY - Delays the start of frequency counting to allow the mux to settle\n - Delay is measured in multiples of the reference clock period - 0x8C - 0x00000001 - - - FC0_DELAY - [2:0] - read-write - - - - - FC0_INTERVAL - The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n - The default gives a test interval of 250us - 0x90 - 0x00000008 - - - FC0_INTERVAL - [3:0] - read-write - - - - - FC0_SRC - Clock sent to frequency counter, set to 0 when not required\n - Writing to this register initiates the frequency count - 0x94 - 0x00000000 - - - FC0_SRC - [7:0] - read-write - - - NULL - 0 - - - pll_sys_clksrc_primary - 1 - - - pll_usb_clksrc_primary - 2 - - - rosc_clksrc - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clksrc_gpin0 - 6 - - - clksrc_gpin1 - 7 - - - clk_ref - 8 - - - clk_sys - 9 - - - clk_peri - 10 - - - clk_usb - 11 - - - clk_adc - 12 - - - clk_rtc - 13 - - - - - - - FC0_STATUS - Frequency counter status - 0x98 - 0x00000000 - - - DIED - Test clock stopped during test - [28:28] - read-only - - - FAST - Test clock faster than expected, only valid when status_done=1 - [24:24] - read-only - - - SLOW - Test clock slower than expected, only valid when status_done=1 - [20:20] - read-only - - - FAIL - Test failed - [16:16] - read-only - - - WAITING - Waiting for test clock to start - [12:12] - read-only - - - RUNNING - Test running - [8:8] - read-only - - - DONE - Test complete - [4:4] - read-only - - - PASS - Test passed - [0:0] - read-only - - - - - FC0_RESULT - Result of frequency measurement, only valid when status_done=1 - 0x9C - 0x00000000 - - - KHZ - [29:5] - read-only - - - FRAC - [4:0] - read-only - - - - - WAKE_EN0 - enable clock in wake mode - 0xA0 - 0xFFFFFFFF - - - clk_sys_sram3 - [31:31] - read-write - - - clk_sys_sram2 - [30:30] - read-write - - - clk_sys_sram1 - [29:29] - read-write - - - clk_sys_sram0 - [28:28] - read-write - - - clk_sys_spi1 - [27:27] - read-write - - - clk_peri_spi1 - [26:26] - read-write - - - clk_sys_spi0 - [25:25] - read-write - - - clk_peri_spi0 - [24:24] - read-write - - - clk_sys_sio - [23:23] - read-write - - - clk_sys_rtc - [22:22] - read-write - - - clk_rtc_rtc - [21:21] - read-write - - - clk_sys_rosc - [20:20] - read-write - - - clk_sys_rom - [19:19] - read-write - - - clk_sys_resets - [18:18] - read-write - - - clk_sys_pwm - [17:17] - read-write - - - clk_sys_psm - [16:16] - read-write - - - clk_sys_pll_usb - [15:15] - read-write - - - clk_sys_pll_sys - [14:14] - read-write - - - clk_sys_pio1 - [13:13] - read-write - - - clk_sys_pio0 - [12:12] - read-write - - - clk_sys_pads - [11:11] - read-write - - - clk_sys_vreg_and_chip_reset - [10:10] - read-write - - - clk_sys_jtag - [9:9] - read-write - - - clk_sys_io - [8:8] - read-write - - - clk_sys_i2c1 - [7:7] - read-write - - - clk_sys_i2c0 - [6:6] - read-write - - - clk_sys_dma - [5:5] - read-write - - - clk_sys_busfabric - [4:4] - read-write - - - clk_sys_busctrl - [3:3] - read-write - - - clk_sys_adc - [2:2] - read-write - - - clk_adc_adc - [1:1] - read-write - - - clk_sys_clocks - [0:0] - read-write - - - - - WAKE_EN1 - enable clock in wake mode - 0xA4 - 0x00007FFF - - - clk_sys_xosc - [14:14] - read-write - - - clk_sys_xip - [13:13] - read-write - - - clk_sys_watchdog - [12:12] - read-write - - - clk_usb_usbctrl - [11:11] - read-write - - - clk_sys_usbctrl - [10:10] - read-write - - - clk_sys_uart1 - [9:9] - read-write - - - clk_peri_uart1 - [8:8] - read-write - - - clk_sys_uart0 - [7:7] - read-write - - - clk_peri_uart0 - [6:6] - read-write - - - clk_sys_timer - [5:5] - read-write - - - clk_sys_tbman - [4:4] - read-write - - - clk_sys_sysinfo - [3:3] - read-write - - - clk_sys_syscfg - [2:2] - read-write - - - clk_sys_sram5 - [1:1] - read-write - - - clk_sys_sram4 - [0:0] - read-write - - - - - SLEEP_EN0 - enable clock in sleep mode - 0xA8 - 0xFFFFFFFF - - - clk_sys_sram3 - [31:31] - read-write - - - clk_sys_sram2 - [30:30] - read-write - - - clk_sys_sram1 - [29:29] - read-write - - - clk_sys_sram0 - [28:28] - read-write - - - clk_sys_spi1 - [27:27] - read-write - - - clk_peri_spi1 - [26:26] - read-write - - - clk_sys_spi0 - [25:25] - read-write - - - clk_peri_spi0 - [24:24] - read-write - - - clk_sys_sio - [23:23] - read-write - - - clk_sys_rtc - [22:22] - read-write - - - clk_rtc_rtc - [21:21] - read-write - - - clk_sys_rosc - [20:20] - read-write - - - clk_sys_rom - [19:19] - read-write - - - clk_sys_resets - [18:18] - read-write - - - clk_sys_pwm - [17:17] - read-write - - - clk_sys_psm - [16:16] - read-write - - - clk_sys_pll_usb - [15:15] - read-write - - - clk_sys_pll_sys - [14:14] - read-write - - - clk_sys_pio1 - [13:13] - read-write - - - clk_sys_pio0 - [12:12] - read-write - - - clk_sys_pads - [11:11] - read-write - - - clk_sys_vreg_and_chip_reset - [10:10] - read-write - - - clk_sys_jtag - [9:9] - read-write - - - clk_sys_io - [8:8] - read-write - - - clk_sys_i2c1 - [7:7] - read-write - - - clk_sys_i2c0 - [6:6] - read-write - - - clk_sys_dma - [5:5] - read-write - - - clk_sys_busfabric - [4:4] - read-write - - - clk_sys_busctrl - [3:3] - read-write - - - clk_sys_adc - [2:2] - read-write - - - clk_adc_adc - [1:1] - read-write - - - clk_sys_clocks - [0:0] - read-write - - - - - SLEEP_EN1 - enable clock in sleep mode - 0xAC - 0x00007FFF - - - clk_sys_xosc - [14:14] - read-write - - - clk_sys_xip - [13:13] - read-write - - - clk_sys_watchdog - [12:12] - read-write - - - clk_usb_usbctrl - [11:11] - read-write - - - clk_sys_usbctrl - [10:10] - read-write - - - clk_sys_uart1 - [9:9] - read-write - - - clk_peri_uart1 - [8:8] - read-write - - - clk_sys_uart0 - [7:7] - read-write - - - clk_peri_uart0 - [6:6] - read-write - - - clk_sys_timer - [5:5] - read-write - - - clk_sys_tbman - [4:4] - read-write - - - clk_sys_sysinfo - [3:3] - read-write - - - clk_sys_syscfg - [2:2] - read-write - - - clk_sys_sram5 - [1:1] - read-write - - - clk_sys_sram4 - [0:0] - read-write - - - - - ENABLED0 - indicates the state of the clock enable - 0xB0 - 0x00000000 - - - clk_sys_sram3 - [31:31] - read-only - - - clk_sys_sram2 - [30:30] - read-only - - - clk_sys_sram1 - [29:29] - read-only - - - clk_sys_sram0 - [28:28] - read-only - - - clk_sys_spi1 - [27:27] - read-only - - - clk_peri_spi1 - [26:26] - read-only - - - clk_sys_spi0 - [25:25] - read-only - - - clk_peri_spi0 - [24:24] - read-only - - - clk_sys_sio - [23:23] - read-only - - - clk_sys_rtc - [22:22] - read-only - - - clk_rtc_rtc - [21:21] - read-only - - - clk_sys_rosc - [20:20] - read-only - - - clk_sys_rom - [19:19] - read-only - - - clk_sys_resets - [18:18] - read-only - - - clk_sys_pwm - [17:17] - read-only - - - clk_sys_psm - [16:16] - read-only - - - clk_sys_pll_usb - [15:15] - read-only - - - clk_sys_pll_sys - [14:14] - read-only - - - clk_sys_pio1 - [13:13] - read-only - - - clk_sys_pio0 - [12:12] - read-only - - - clk_sys_pads - [11:11] - read-only - - - clk_sys_vreg_and_chip_reset - [10:10] - read-only - - - clk_sys_jtag - [9:9] - read-only - - - clk_sys_io - [8:8] - read-only - - - clk_sys_i2c1 - [7:7] - read-only - - - clk_sys_i2c0 - [6:6] - read-only - - - clk_sys_dma - [5:5] - read-only - - - clk_sys_busfabric - [4:4] - read-only - - - clk_sys_busctrl - [3:3] - read-only - - - clk_sys_adc - [2:2] - read-only - - - clk_adc_adc - [1:1] - read-only - - - clk_sys_clocks - [0:0] - read-only - - - - - ENABLED1 - indicates the state of the clock enable - 0xB4 - 0x00000000 - - - clk_sys_xosc - [14:14] - read-only - - - clk_sys_xip - [13:13] - read-only - - - clk_sys_watchdog - [12:12] - read-only - - - clk_usb_usbctrl - [11:11] - read-only - - - clk_sys_usbctrl - [10:10] - read-only - - - clk_sys_uart1 - [9:9] - read-only - - - clk_peri_uart1 - [8:8] - read-only - - - clk_sys_uart0 - [7:7] - read-only - - - clk_peri_uart0 - [6:6] - read-only - - - clk_sys_timer - [5:5] - read-only - - - clk_sys_tbman - [4:4] - read-only - - - clk_sys_sysinfo - [3:3] - read-only - - - clk_sys_syscfg - [2:2] - read-only - - - clk_sys_sram5 - [1:1] - read-only - - - clk_sys_sram4 - [0:0] - read-only - - - - - INTR - Raw Interrupts - 0xB8 - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0xBC - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-write - - - - - INTF - Interrupt Force - 0xC0 - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0xC4 - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-only - - - - - - - RESETS - 1 - 0x4000C000 - 0x20 - - 0x0 - 0x1000 - registers - - - - RESET - Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. - 0x0 - 0x01FFFFFF - - - usbctrl - [24:24] - read-write - - - uart1 - [23:23] - read-write - - - uart0 - [22:22] - read-write - - - timer - [21:21] - read-write - - - tbman - [20:20] - read-write - - - sysinfo - [19:19] - read-write - - - syscfg - [18:18] - read-write - - - spi1 - [17:17] - read-write - - - spi0 - [16:16] - read-write - - - rtc - [15:15] - read-write - - - pwm - [14:14] - read-write - - - pll_usb - [13:13] - read-write - - - pll_sys - [12:12] - read-write - - - pio1 - [11:11] - read-write - - - pio0 - [10:10] - read-write - - - pads_qspi - [9:9] - read-write - - - pads_bank0 - [8:8] - read-write - - - jtag - [7:7] - read-write - - - io_qspi - [6:6] - read-write - - - io_bank0 - [5:5] - read-write - - - i2c1 - [4:4] - read-write - - - i2c0 - [3:3] - read-write - - - dma - [2:2] - read-write - - - busctrl - [1:1] - read-write - - - adc - [0:0] - read-write - - - - - WDSEL - Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. - 0x4 - 0x00000000 - - - usbctrl - [24:24] - read-write - - - uart1 - [23:23] - read-write - - - uart0 - [22:22] - read-write - - - timer - [21:21] - read-write - - - tbman - [20:20] - read-write - - - sysinfo - [19:19] - read-write - - - syscfg - [18:18] - read-write - - - spi1 - [17:17] - read-write - - - spi0 - [16:16] - read-write - - - rtc - [15:15] - read-write - - - pwm - [14:14] - read-write - - - pll_usb - [13:13] - read-write - - - pll_sys - [12:12] - read-write - - - pio1 - [11:11] - read-write - - - pio0 - [10:10] - read-write - - - pads_qspi - [9:9] - read-write - - - pads_bank0 - [8:8] - read-write - - - jtag - [7:7] - read-write - - - io_qspi - [6:6] - read-write - - - io_bank0 - [5:5] - read-write - - - i2c1 - [4:4] - read-write - - - i2c0 - [3:3] - read-write - - - dma - [2:2] - read-write - - - busctrl - [1:1] - read-write - - - adc - [0:0] - read-write - - - - - RESET_DONE - Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. - 0x8 - 0x00000000 - - - usbctrl - [24:24] - read-only - - - uart1 - [23:23] - read-only - - - uart0 - [22:22] - read-only - - - timer - [21:21] - read-only - - - tbman - [20:20] - read-only - - - sysinfo - [19:19] - read-only - - - syscfg - [18:18] - read-only - - - spi1 - [17:17] - read-only - - - spi0 - [16:16] - read-only - - - rtc - [15:15] - read-only - - - pwm - [14:14] - read-only - - - pll_usb - [13:13] - read-only - - - pll_sys - [12:12] - read-only - - - pio1 - [11:11] - read-only - - - pio0 - [10:10] - read-only - - - pads_qspi - [9:9] - read-only - - - pads_bank0 - [8:8] - read-only - - - jtag - [7:7] - read-only - - - io_qspi - [6:6] - read-only - - - io_bank0 - [5:5] - read-only - - - i2c1 - [4:4] - read-only - - - i2c0 - [3:3] - read-only - - - dma - [2:2] - read-only - - - busctrl - [1:1] - read-only - - - adc - [0:0] - read-only - - - - - - - PSM - 1 - 0x40010000 - 0x20 - - 0x0 - 0x1000 - registers - - - - FRCE_ON - Force block out of reset (i.e. power it on) - 0x0 - 0x00000000 - - - proc1 - [16:16] - read-write - - - proc0 - [15:15] - read-write - - - sio - [14:14] - read-write - - - vreg_and_chip_reset - [13:13] - read-write - - - xip - [12:12] - read-write - - - sram5 - [11:11] - read-write - - - sram4 - [10:10] - read-write - - - sram3 - [9:9] - read-write - - - sram2 - [8:8] - read-write - - - sram1 - [7:7] - read-write - - - sram0 - [6:6] - read-write - - - rom - [5:5] - read-write - - - busfabric - [4:4] - read-write - - - resets - [3:3] - read-write - - - clocks - [2:2] - read-write - - - xosc - [1:1] - read-write - - - rosc - [0:0] - read-write - - - - - FRCE_OFF - Force into reset (i.e. power it off) - 0x4 - 0x00000000 - - - proc1 - [16:16] - read-write - - - proc0 - [15:15] - read-write - - - sio - [14:14] - read-write - - - vreg_and_chip_reset - [13:13] - read-write - - - xip - [12:12] - read-write - - - sram5 - [11:11] - read-write - - - sram4 - [10:10] - read-write - - - sram3 - [9:9] - read-write - - - sram2 - [8:8] - read-write - - - sram1 - [7:7] - read-write - - - sram0 - [6:6] - read-write - - - rom - [5:5] - read-write - - - busfabric - [4:4] - read-write - - - resets - [3:3] - read-write - - - clocks - [2:2] - read-write - - - xosc - [1:1] - read-write - - - rosc - [0:0] - read-write - - - - - WDSEL - Set to 1 if this peripheral should be reset when the watchdog fires. - 0x8 - 0x00000000 - - - proc1 - [16:16] - read-write - - - proc0 - [15:15] - read-write - - - sio - [14:14] - read-write - - - vreg_and_chip_reset - [13:13] - read-write - - - xip - [12:12] - read-write - - - sram5 - [11:11] - read-write - - - sram4 - [10:10] - read-write - - - sram3 - [9:9] - read-write - - - sram2 - [8:8] - read-write - - - sram1 - [7:7] - read-write - - - sram0 - [6:6] - read-write - - - rom - [5:5] - read-write - - - busfabric - [4:4] - read-write - - - resets - [3:3] - read-write - - - clocks - [2:2] - read-write - - - xosc - [1:1] - read-write - - - rosc - [0:0] - read-write - - - - - DONE - Indicates the peripheral's registers are ready to access. - 0xC - 0x00000000 - - - proc1 - [16:16] - read-only - - - proc0 - [15:15] - read-only - - - sio - [14:14] - read-only - - - vreg_and_chip_reset - [13:13] - read-only - - - xip - [12:12] - read-only - - - sram5 - [11:11] - read-only - - - sram4 - [10:10] - read-only - - - sram3 - [9:9] - read-only - - - sram2 - [8:8] - read-only - - - sram1 - [7:7] - read-only - - - sram0 - [6:6] - read-only - - - rom - [5:5] - read-only - - - busfabric - [4:4] - read-only - - - resets - [3:3] - read-only - - - clocks - [2:2] - read-only - - - xosc - [1:1] - read-only - - - rosc - [0:0] - read-only - - - - - - - IO_BANK0 - 1 - 0x40014000 - 0x20 - - 0x0 - 0x1000 - registers - - - IO_IRQ_BANK0 - 13 - - - - 30 - 0x8 - 0-29 - GPIO%s - Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL - 0x0 - - GPIO_STATUS - GPIO status - 0x0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_CTRL - GPIO control including function select and overrides. - 0x4 - 0x0000001F - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins. - [4:0] - read-write - - FUNCSEL - - jtag - Connect to JTAG peripheral - 0 - - - spi - Connect to matching SPI peripheral - 1 - - - uart - Connect to matching UART peripheral - 2 - - - i2c - Connect to matching I2C peripheral - 3 - - - pwm - Connect to matching PWM peripheral - 4 - - - sio - Use as a GPIO pin (connect to SIO peripheral) - 5 - - - pio0 - Connect to PIO0 peripheral - 6 - - - pio1 - Connect to PIO1 peripheral - 7 - - - clock - Connect to Clock peripheral - 8 - - - usb - Connect to USB peripheral - 9 - - - null - Connect to nothing - 31 - - - - - - - - 4 - 0x4 - 0-3 - INTR%s - Raw Interrupts - 0xF0 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO7_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO6_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO5_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO4_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO3_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO2_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO1_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO0_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - 4 - 0x4 - 0-3 - PROC0_INTE%s - Interrupt Enable for proc0 - 0x100 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 4 - 0x4 - 0-3 - PROC0_INTF%s - Interrupt Force for proc0 - 0x110 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 4 - 0x4 - 0-3 - PROC0_INTS%s - Interrupt status after masking & forcing for proc0 - 0x120 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - 4 - 0x4 - 0-3 - PROC1_INTE%s - Interrupt Enable for proc1 - 0x130 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 4 - 0x4 - 0-3 - PROC1_INTF%s - Interrupt Force for proc1 - 0x140 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 4 - 0x4 - 0-3 - PROC1_INTS%s - Interrupt status after masking & forcing for proc1 - 0x150 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - 4 - 0x4 - 0-3 - DORMANT_WAKE_INTE%s - Interrupt Enable for dormant_wake - 0x160 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 4 - 0x4 - 0-3 - DORMANT_WAKE_INTF%s - Interrupt Force for dormant_wake - 0x170 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 4 - 0x4 - 0-3 - DORMANT_WAKE_INTS%s - Interrupt status after masking & forcing for dormant_wake - 0x180 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - - - IO_QSPI - 1 - 0x40018000 - 0x20 - - 0x0 - 0x1000 - registers - - - IO_IRQ_QSPI - 14 - - - - 6 - 0x8 - SCLK,SS,SD0,SD1,SD2,SD3 - GPIO_QSPI%s - Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL - 0x0 - - GPIO_STATUS - GPIO status - 0x0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_CTRL - GPIO control including function select and overrides. - 0x4 - 0x0000001F - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - xip_sclk - 0 - - - sio_30 - 5 - - - null - 31 - - - - - - - - INTR - Raw Interrupts - 0x30 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTE - Interrupt Enable for proc0 - 0x34 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF - Interrupt Force for proc0 - 0x38 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTS - Interrupt status after masking & forcing for proc0 - 0x3C - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTE - Interrupt Enable for proc1 - 0x40 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF - Interrupt Force for proc1 - 0x44 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTS - Interrupt status after masking & forcing for proc1 - 0x48 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTE - Interrupt Enable for dormant_wake - 0x4C - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF - Interrupt Force for dormant_wake - 0x50 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTS - Interrupt status after masking & forcing for dormant_wake - 0x54 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - - - PADS_BANK0 - 1 - 0x4001C000 - 0x20 - - 0x0 - 0x1000 - registers - - - - VOLTAGE_SELECT - Voltage select. Per bank control - 0x0 - 0x00000000 - - - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - Set voltage to 3.3V (DVDD >= 2V5) - 0 - - - 1v8 - Set voltage to 1.8V (DVDD <= 1V8) - 1 - - - - - - - 30 - 0x4 - 0-29 - GPIO%s - Pad control register - 0x4 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - SWCLK - Pad control register - 0x7C - 0x000000DA - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - SWD - Pad control register - 0x80 - 0x0000005A - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - - - PADS_QSPI - 1 - 0x40020000 - 0x20 - - 0x0 - 0x1000 - registers - - - - VOLTAGE_SELECT - Voltage select. Per bank control - 0x0 - 0x00000000 - - - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - Set voltage to 3.3V (DVDD >= 2V5) - 0 - - - 1v8 - Set voltage to 1.8V (DVDD <= 1V8) - 1 - - - - - - - GPIO_QSPI_SCLK - Pad control register - 0x4 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD0 - Pad control register - 0x8 - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD1 - Pad control register - 0xC - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD2 - Pad control register - 0x10 - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD3 - Pad control register - 0x14 - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SS - Pad control register - 0x18 - 0x0000005A - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - - - XOSC - 1 - Controls the crystal oscillator - 0x40024000 - 0x20 - - 0x0 - 0x1000 - registers - - - - CTRL - Crystal Oscillator Control - 0x0 - 0x00000000 - - - ENABLE - On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - Frequency range. This resets to 0xAA0 and cannot be changed. - [11:0] - read-write - - - 1_15MHZ - 2720 - - - RESERVED_1 - 2721 - - - RESERVED_2 - 2722 - - - RESERVED_3 - 2723 - - - - - - - STATUS - Crystal Oscillator Status - 0x4 - 0x00000000 - - - STABLE - Oscillator is running and stable - [31:31] - read-only - - - BADWRITE - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT - [24:24] - read-write - oneToClear - - - ENABLED - Oscillator is enabled but not necessarily running and stable, resets to 0 - [12:12] - read-only - - - FREQ_RANGE - The current frequency range setting, always reads 0 - [1:0] - read-only - - - 1_15MHZ - 0 - - - RESERVED_1 - 1 - - - RESERVED_2 - 2 - - - RESERVED_3 - 3 - - - - - - - DORMANT - Crystal Oscillator pause control\n - This is used to save power by pausing the XOSC\n - On power-up this field is initialised to WAKE\n - An invalid write will also select WAKE\n - WARNING: stop the PLLs before selecting dormant mode\n - WARNING: setup the irq before selecting dormant mode - 0x8 - read-write - 0x00000000 - - - STARTUP - Controls the startup delay - 0xC - 0x000000C4 - - - X4 - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. - [20:20] - read-write - - - DELAY - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. - [13:0] - read-write - - - - - - - PLL_SYS - 1 - 0x40028000 - 0x20 - - 0x0 - 0x1000 - registers - - - - CS - Control and Status\n - GENERAL CONSTRAINTS:\n - Reference clock frequency min=5MHz, max=800MHz\n - Feedback divider min=16, max=320\n - VCO frequency min=750MHz, max=1600MHz - 0x0 - 0x00000001 - - - LOCK - PLL is locked - [31:31] - read-only - - - BYPASS - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. - [8:8] - read-write - - - REFDIV - Divides the PLL input reference clock.\n - Behaviour is undefined for div=0.\n - PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. - [5:0] - read-write - - - - - PWR - Controls the PLL power modes. - 0x4 - 0x0000002D - - - VCOPD - PLL VCO powerdown\n - To save power set high when PLL output not required or bypass=1. - [5:5] - read-write - - - POSTDIVPD - PLL post divider powerdown\n - To save power set high when PLL output not required or bypass=1. - [3:3] - read-write - - - DSMPD - PLL DSM powerdown\n - Nothing is achieved by setting this low. - [2:2] - read-write - - - PD - PLL powerdown\n - To save power set high when PLL output not required. - [0:0] - read-write - - - - - FBDIV_INT - Feedback divisor\n - (note: this PLL does not support fractional division) - 0x8 - 0x00000000 - - - FBDIV_INT - see ctrl reg description for constraints - [11:0] - read-write - - - - - PRIM - Controls the PLL post dividers for the primary output\n - (note: this PLL does not have a secondary output)\n - the primary output is driven from VCO divided by postdiv1*postdiv2 - 0xC - 0x00077000 - - - POSTDIV1 - divide by 1-7 - [18:16] - read-write - - - POSTDIV2 - divide by 1-7 - [14:12] - read-write - - - - - - - PLL_USB - 0x4002C000 - - - BUSCTRL - 1 - Register block for busfabric control signals and performance counters - 0x40030000 - 0x20 - - 0x0 - 0x1000 - registers - - - - BUS_PRIORITY - Set the priority of each master for bus arbitration. - 0x0 - 0x00000000 - - - DMA_W - 0 - low priority, 1 - high priority - [12:12] - read-write - - - DMA_R - 0 - low priority, 1 - high priority - [8:8] - read-write - - - PROC1 - 0 - low priority, 1 - high priority - [4:4] - read-write - - - PROC0 - 0 - low priority, 1 - high priority - [0:0] - read-write - - - - - BUS_PRIORITY_ACK - Bus priority acknowledge - 0x4 - 0x00000000 - - - BUS_PRIORITY_ACK - Goes to 1 once all arbiters have registered the new global priority levels.\n - Arbiters update their local priority when servicing a new nonsequential access.\n - In normal circumstances this will happen almost immediately. - [0:0] - read-only - - - - - PERFCTR0 - Bus fabric performance counter 0 - 0x8 - 0x00000000 - - - PERFCTR0 - Busfabric saturating performance counter 0\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL0 - [23:0] - read-write - oneToClear - - - - - PERFSEL0 - Bus fabric performance event select for PERFCTR0 - 0xC - 0x0000001F - - - PERFSEL0 - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - PERFCTR1 - Bus fabric performance counter 1 - 0x10 - 0x00000000 - - - PERFCTR1 - Busfabric saturating performance counter 1\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL1 - [23:0] - read-write - oneToClear - - - - - PERFSEL1 - Bus fabric performance event select for PERFCTR1 - 0x14 - 0x0000001F - - - PERFSEL1 - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - PERFCTR2 - Bus fabric performance counter 2 - 0x18 - 0x00000000 - - - PERFCTR2 - Busfabric saturating performance counter 2\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL2 - [23:0] - read-write - oneToClear - - - - - PERFSEL2 - Bus fabric performance event select for PERFCTR2 - 0x1C - 0x0000001F - - - PERFSEL2 - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - PERFCTR3 - Bus fabric performance counter 3 - 0x20 - 0x00000000 - - - PERFCTR3 - Busfabric saturating performance counter 3\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL3 - [23:0] - read-write - oneToClear - - - - - PERFSEL3 - Bus fabric performance event select for PERFCTR3 - 0x24 - 0x0000001F - - - PERFSEL3 - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - - - UART0 - 1 - 0x40034000 - 0x20 - - 0x0 - 0x1000 - registers - - - UART0_IRQ - 20 - - - - UARTDR - Data Register, UARTDR - 0x0 - 0x00000000 - - - OE - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. - [11:11] - read-only - - - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. - [10:10] - read-only - - - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. - [9:9] - read-only - - - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. - [8:8] - read-only - - - DATA - Receive (read) data character. Transmit (write) data character. - [7:0] - read-write - - - - - UARTRSR - Receive Status Register/Error Clear Register, UARTRSR/UARTECR - 0x4 - 0x00000000 - - - OE - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. - [3:3] - read-write - oneToClear - - - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. - [2:2] - read-write - oneToClear - - - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. - [1:1] - read-write - oneToClear - - - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. - [0:0] - read-write - oneToClear - - - - - UARTFR - Flag Register, UARTFR - 0x18 - 0x00000090 - - - RI - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. - [8:8] - read-only - - - TXFE - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. - [7:7] - read-only - - - RXFF - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. - [6:6] - read-only - - - TXFF - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. - [5:5] - read-only - - - RXFE - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. - [4:4] - read-only - - - BUSY - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. - [3:3] - read-only - - - DCD - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. - [2:2] - read-only - - - DSR - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. - [1:1] - read-only - - - CTS - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. - [0:0] - read-only - - - - - UARTILPR - IrDA Low-Power Counter Register, UARTILPR - 0x20 - 0x00000000 - - - ILPDVSR - 8-bit low-power divisor value. These bits are cleared to 0 at reset. - [7:0] - read-write - - - - - UARTIBRD - Integer Baud Rate Register, UARTIBRD - 0x24 - 0x00000000 - - - BAUD_DIVINT - The integer baud rate divisor. These bits are cleared to 0 on reset. - [15:0] - read-write - - - - - UARTFBRD - Fractional Baud Rate Register, UARTFBRD - 0x28 - 0x00000000 - - - BAUD_DIVFRAC - The fractional baud rate divisor. These bits are cleared to 0 on reset. - [5:0] - read-write - - - - - UARTLCR_H - Line Control Register, UARTLCR_H - 0x2C - 0x00000000 - - - SPS - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. - [7:7] - read-write - - - WLEN - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. - [6:5] - read-write - - - FEN - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). - [4:4] - read-write - - - STP2 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. - [3:3] - read-write - - - EPS - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. - [2:2] - read-write - - - PEN - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. - [1:1] - read-write - - - BRK - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. - [0:0] - read-write - - - - - UARTCR - Control Register, UARTCR - 0x30 - 0x00000300 - - - CTSEN - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. - [15:15] - read-write - - - RTSEN - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. - [14:14] - read-write - - - OUT2 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). - [13:13] - read-write - - - OUT1 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). - [12:12] - read-write - - - RTS - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. - [11:11] - read-write - - - DTR - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. - [10:10] - read-write - - - RXE - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. - [9:9] - read-write - - - TXE - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. - [8:8] - read-write - - - LBE - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. - [7:7] - read-write - - - SIRLP - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. - [2:2] - read-write - - - SIREN - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. - [1:1] - read-write - - - UARTEN - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. - [0:0] - read-write - - - - - UARTIFLS - Interrupt FIFO Level Select Register, UARTIFLS - 0x34 - 0x00000012 - - - RXIFLSEL - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. - [5:3] - read-write - - - TXIFLSEL - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. - [2:0] - read-write - - - - - UARTIMSC - Interrupt Mask Set/Clear Register, UARTIMSC - 0x38 - 0x00000000 - - - OEIM - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. - [10:10] - read-write - - - BEIM - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. - [9:9] - read-write - - - PEIM - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. - [8:8] - read-write - - - FEIM - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. - [7:7] - read-write - - - RTIM - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. - [6:6] - read-write - - - TXIM - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. - [5:5] - read-write - - - RXIM - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. - [4:4] - read-write - - - DSRMIM - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. - [3:3] - read-write - - - DCDMIM - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. - [2:2] - read-write - - - CTSMIM - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. - [1:1] - read-write - - - RIMIM - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. - [0:0] - read-write - - - - - UARTRIS - Raw Interrupt Status Register, UARTRIS - 0x3C - 0x00000000 - - - OERIS - Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BERIS - Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PERIS - Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FERIS - Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTRIS - Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a - [6:6] - read-only - - - TXRIS - Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXRIS - Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRRMIS - nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only - - - DCDRMIS - nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only - - - CTSRMIS - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. - [1:1] - read-only - - - RIRMIS - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. - [0:0] - read-only - - - - - UARTMIS - Masked Interrupt Status Register, UARTMIS - 0x40 - 0x00000000 - - - OEMIS - Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BEMIS - Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PEMIS - Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FEMIS - Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTMIS - Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. - [6:6] - read-only - - - TXMIS - Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXMIS - Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRMMIS - nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only - - - DCDMMIS - nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only - - - CTSMMIS - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. - [1:1] - read-only - - - RIMMIS - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. - [0:0] - read-only - - - - - UARTICR - Interrupt Clear Register, UARTICR - 0x44 - 0x00000000 - - - OEIC - Overrun error interrupt clear. Clears the UARTOEINTR interrupt. - [10:10] - read-write - oneToClear - - - BEIC - Break error interrupt clear. Clears the UARTBEINTR interrupt. - [9:9] - read-write - oneToClear - - - PEIC - Parity error interrupt clear. Clears the UARTPEINTR interrupt. - [8:8] - read-write - oneToClear - - - FEIC - Framing error interrupt clear. Clears the UARTFEINTR interrupt. - [7:7] - read-write - oneToClear - - - RTIC - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. - [6:6] - read-write - oneToClear - - - TXIC - Transmit interrupt clear. Clears the UARTTXINTR interrupt. - [5:5] - read-write - oneToClear - - - RXIC - Receive interrupt clear. Clears the UARTRXINTR interrupt. - [4:4] - read-write - oneToClear - - - DSRMIC - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. - [3:3] - read-write - oneToClear - - - DCDMIC - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. - [2:2] - read-write - oneToClear - - - CTSMIC - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. - [1:1] - read-write - oneToClear - - - RIMIC - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. - [0:0] - read-write - oneToClear - - - - - UARTDMACR - DMA Control Register, UARTDMACR - 0x48 - 0x00000000 - - - DMAONERR - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. - [2:2] - read-write - - - TXDMAE - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] - read-write - - - - - UARTPERIPHID0 - UARTPeriphID0 Register - 0xFE0 - 0x00000011 - - - PARTNUMBER0 - These bits read back as 0x11 - [7:0] - read-only - - - - - UARTPERIPHID1 - UARTPeriphID1 Register - 0xFE4 - 0x00000010 - - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only - - - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - UARTPERIPHID2 - UARTPeriphID2 Register - 0xFE8 - 0x00000034 - - - REVISION - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 - [7:4] - read-only - - - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only - - - - - UARTPERIPHID3 - UARTPeriphID3 Register - 0xFEC - 0x00000000 - - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only - - - - - UARTPCELLID0 - UARTPCellID0 Register - 0xFF0 - 0x0000000D - - - UARTPCELLID0 - These bits read back as 0x0D - [7:0] - read-only - - - - - UARTPCELLID1 - UARTPCellID1 Register - 0xFF4 - 0x000000F0 - - - UARTPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only - - - - - UARTPCELLID2 - UARTPCellID2 Register - 0xFF8 - 0x00000005 - - - UARTPCELLID2 - These bits read back as 0x05 - [7:0] - read-only - - - - - UARTPCELLID3 - UARTPCellID3 Register - 0xFFC - 0x000000B1 - - - UARTPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only - - - - - - - UART1 - 0x40038000 - - UART1_IRQ - 21 - - - - SPI0 - 1 - 0x4003C000 - 0x20 - - 0x0 - 0x1000 - registers - - - SPI0_IRQ - 18 - - - - SSPCR0 - Control register 0, SSPCR0 on page 3-4 - 0x0 - 0x00000000 - - - SCR - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. - [15:8] - read-write - - - SPH - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [7:7] - read-write - - - SPO - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [6:6] - read-write - - - FRF - Frame format. - [5:4] - read-write - - FRF - - Motorola - Motorola SPI frame format - 0 - - - Texas_Instruments - Texas Instruments synchronous serial frame format - 1 - - - National_Semiconductor_Microwire - National Semiconductor Microwire frame format - 2 - - - - - DSS - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. - [3:0] - read-write - - - - - SSPCR1 - Control register 1, SSPCR1 on page 3-5 - 0x4 - 0x00000000 - - - SOD - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. - [3:3] - read-write - - - MS - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. - [2:2] - read-write - - - SSE - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. - [1:1] - read-write - - - LBM - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. - [0:0] - read-write - - - - - SSPDR - Data register, SSPDR on page 3-6 - 0x8 - 0x00000000 - - - DATA - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. - [15:0] - read-write - - - - - SSPSR - Status register, SSPSR on page 3-7 - 0xC - 0x00000003 - - - BSY - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. - [4:4] - read-only - - - RFF - Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. - [3:3] - read-only - - - RNE - Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. - [2:2] - read-only - - - TNF - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. - [1:1] - read-only - - - TFE - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. - [0:0] - read-only - - - - - SSPCPSR - Clock prescale register, SSPCPSR on page 3-8 - 0x10 - 0x00000000 - - - CPSDVSR - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. - [7:0] - read-write - - - - - SSPIMSC - Interrupt mask set or clear register, SSPIMSC on page 3-9 - 0x14 - 0x00000000 - - - TXIM - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. - [3:3] - read-write - - - RXIM - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. - [2:2] - read-write - - - RTIM - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. - [1:1] - read-write - - - RORIM - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. - [0:0] - read-write - - - - - SSPRIS - Raw interrupt status register, SSPRIS on page 3-10 - 0x18 - 0x00000008 - - - TXRIS - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt - [3:3] - read-only - - - RXRIS - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt - [2:2] - read-only - - - RTRIS - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt - [1:1] - read-only - - - RORRIS - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt - [0:0] - read-only - - - - - SSPMIS - Masked interrupt status register, SSPMIS on page 3-11 - 0x1C - 0x00000000 - - - TXMIS - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - [3:3] - read-only - - - RXMIS - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - [2:2] - read-only - - - RTMIS - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - [1:1] - read-only - - - RORMIS - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - [0:0] - read-only - - - - - SSPICR - Interrupt clear register, SSPICR on page 3-11 - 0x20 - 0x00000000 - - - RTIC - Clears the SSPRTINTR interrupt - [1:1] - read-write - oneToClear - - - RORIC - Clears the SSPRORINTR interrupt - [0:0] - read-write - oneToClear - - - - - SSPDMACR - DMA control register, SSPDMACR on page 3-12 - 0x24 - 0x00000000 - - - TXDMAE - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] - read-write - - - - - SSPPERIPHID0 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFE0 - 0x00000022 - - - PARTNUMBER0 - These bits read back as 0x22 - [7:0] - read-only - - - - - SSPPERIPHID1 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFE4 - 0x00000010 - - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only - - - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - SSPPERIPHID2 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFE8 - 0x00000034 - - - REVISION - These bits return the peripheral revision - [7:4] - read-only - - - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only - - - - - SSPPERIPHID3 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFEC - 0x00000000 - - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only - - - - - SSPPCELLID0 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFF0 - 0x0000000D - - - SSPPCELLID0 - These bits read back as 0x0D - [7:0] - read-only - - - - - SSPPCELLID1 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFF4 - 0x000000F0 - - - SSPPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only - - - - - SSPPCELLID2 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFF8 - 0x00000005 - - - SSPPCELLID2 - These bits read back as 0x05 - [7:0] - read-only - - - - - SSPPCELLID3 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFFC - 0x000000B1 - - - SSPPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only - - - - - - - SPI1 - 0x40040000 - - SPI1_IRQ - 19 - - - - I2C0 - 1 - DW_apb_i2c address block\n\n - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n - IC_ULTRA_FAST_MODE ................ 0x0\n - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n - IC_UFM_SCL_LOW_COUNT .............. 0x0008\n - IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n - IC_TX_TL .......................... 0x0\n - IC_TX_CMD_BLOCK ................... 0x1\n - IC_HAS_DMA ........................ 0x1\n - IC_HAS_ASYNC_FIFO ................. 0x0\n - IC_SMBUS_ARP ...................... 0x0\n - IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n - IC_INTR_IO ........................ 0x1\n - IC_MASTER_MODE .................... 0x1\n - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n - IC_INTR_POL ....................... 0x1\n - IC_OPTIONAL_SAR ................... 0x0\n - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n - IC_DEFAULT_SLAVE_ADDR ............. 0x055\n - IC_DEFAULT_HS_SPKLEN .............. 0x1\n - IC_FS_SCL_HIGH_COUNT .............. 0x0006\n - IC_HS_SCL_LOW_COUNT ............... 0x0008\n - IC_DEVICE_ID_VALUE ................ 0x0\n - IC_10BITADDR_MASTER ............... 0x0\n - IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n - IC_DEFAULT_FS_SPKLEN .............. 0x7\n - IC_ADD_ENCODED_PARAMS ............. 0x0\n - IC_DEFAULT_SDA_HOLD ............... 0x000001\n - IC_DEFAULT_SDA_SETUP .............. 0x64\n - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n - IC_CLOCK_PERIOD ................... 100\n - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n - IC_RESTART_EN ..................... 0x1\n - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n - IC_BUS_CLEAR_FEATURE .............. 0x0\n - IC_CAP_LOADING .................... 100\n - IC_FS_SCL_LOW_COUNT ............... 0x000d\n - APB_DATA_WIDTH .................... 32\n - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n - IC_SLV_DATA_NACK_ONLY ............. 0x1\n - IC_10BITADDR_SLAVE ................ 0x0\n - IC_CLK_TYPE ....................... 0x0\n - IC_SMBUS_UDID_MSB ................. 0x0\n - IC_SMBUS_SUSPEND_ALERT ............ 0x0\n - IC_HS_SCL_HIGH_COUNT .............. 0x0006\n - IC_SLV_RESTART_DET_EN ............. 0x1\n - IC_SMBUS .......................... 0x0\n - IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n - IC_USE_COUNTS ..................... 0x0\n - IC_RX_BUFFER_DEPTH ................ 16\n - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n - IC_RX_FULL_HLD_BUS_EN ............. 0x1\n - IC_SLAVE_DISABLE .................. 0x1\n - IC_RX_TL .......................... 0x0\n - IC_DEVICE_ID ...................... 0x0\n - IC_HC_COUNT_VALUES ................ 0x0\n - I2C_DYNAMIC_TAR_UPDATE ............ 0\n - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n - IC_HS_MASTER_CODE ................. 0x1\n - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n - IC_SS_SCL_HIGH_COUNT .............. 0x0028\n - IC_SS_SCL_LOW_COUNT ............... 0x002f\n - IC_MAX_SPEED_MODE ................. 0x2\n - IC_STAT_FOR_CLK_STRETCH ........... 0x0\n - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n - IC_DEFAULT_UFM_SPKLEN ............. 0x1\n - IC_TX_BUFFER_DEPTH ................ 16 - 0x40044000 - 0x20 - - 0x0 - 0x100 - registers - - - I2C0_IRQ - 23 - - - - IC_CON - I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. - 0x0 - 0x00000065 - - - STOP_DET_IF_MASTER_ACTIVE - Master issues the STOP_DET interrupt irrespective of whether master is active or not - [10:10] - read-only - - - RX_FIFO_FULL_HLD_CTRL - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n - Reset value: 0x0. - [9:9] - read-write - - - DISABLED - Overflow when RX_FIFO is full - 0 - - - ENABLED - Hold bus when RX_FIFO is full - 1 - - - - - TX_EMPTY_CTRL - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0. - [8:8] - read-write - - - DISABLED - Default behaviour of TX_EMPTY interrupt - 0 - - - ENABLED - Controlled generation of TX_EMPTY interrupt - 1 - - - - - STOP_DET_IFADDRESSED - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - [7:7] - read-write - - - DISABLED - slave issues STOP_DET intr always - 0 - - - ENABLED - slave issues STOP_DET intr only if addressed - 1 - - - - - IC_SLAVE_DISABLE - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. - [6:6] - read-write - - - SLAVE_ENABLED - Slave mode is enabled - 0 - - - SLAVE_DISABLED - Slave mode is disabled - 1 - - - - - IC_RESTART_EN - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n - Reset value: ENABLED - [5:5] - read-write - - - DISABLED - Master restart disabled - 0 - - - ENABLED - Master restart enabled - 1 - - - - - IC_10BITADDR_MASTER - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing - [4:4] - read-write - - - ADDR_7BITS - Master 7Bit addressing mode - 0 - - - ADDR_10BITS - Master 10Bit addressing mode - 1 - - - - - IC_10BITADDR_SLAVE - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. - [3:3] - read-write - - - ADDR_7BITS - Slave 7Bit addressing - 0 - - - ADDR_10BITS - Slave 10Bit addressing - 1 - - - - - SPEED - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n - 1: standard mode (100 kbit/s)\n\n - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n - 3: high speed mode (3.4 Mbit/s)\n\n - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 - [2:1] - read-write - - - STANDARD - Standard Speed mode of operation - 1 - - - FAST - Fast or Fast Plus mode of operation - 2 - - - HIGH - High Speed mode of operation - 3 - - - - - MASTER_MODE - This bit controls whether the DW_apb_i2c master is enabled.\n\n - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. - [0:0] - read-write - - - DISABLED - Master mode is disabled - 0 - - - ENABLED - Master mode is enabled - 1 - - - - - - - IC_TAR - I2C Target Address Register\n\n - This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\n\n - Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. - 0x4 - 0x00000055 - - - SPECIAL - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 - [11:11] - read-write - - - DISABLED - Disables programming of GENERAL_CALL or START_BYTE transmission - 0 - - - ENABLED - Enables programming of GENERAL_CALL or START_BYTE transmission - 1 - - - - - GC_OR_START - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 - [10:10] - read-write - - - GENERAL_CALL - GENERAL_CALL byte transmission - 0 - - - START_BYTE - START byte transmission - 1 - - - - - IC_TAR - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n - If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. - [9:0] - read-write - - - - - IC_SAR - I2C Slave Address Register - 0x8 - 0x00000055 - - - IC_SAR - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. - [9:0] - read-write - - - - - IC_DATA_CMD - I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n - The size of the register changes as follows:\n\n - Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. - 0x10 - 0x00000000 - - - FIRST_DATA_BYTE - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n - Reset value : 0x0\n\n - NOTE: In case of APB_DATA_WIDTH=8,\n\n - 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n - 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n - 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. - [11:11] - read-only - - - INACTIVE - Sequential data byte received - 0 - - - ACTIVE - Non sequential data byte received - 1 - - - - - RESTART - This bit controls whether a RESTART is issued before the byte is sent or received.\n\n - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n - Reset value: 0x0 - [10:10] - read-write - clear - - - DISABLE - Don't Issue RESTART before this command - 0 - - - ENABLE - Issue RESTART before this command - 1 - - - - - STOP - This bit controls whether a STOP is issued after the byte is sent or received.\n\n - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 - [9:9] - read-write - clear - - - DISABLE - Don't Issue STOP after this command - 0 - - - ENABLE - Issue STOP after this command - 1 - - - - - CMD - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n - Reset value: 0x0 - [8:8] - read-write - clear - - - WRITE - Master Write Command - 0 - - - READ - Master Read Command - 1 - - - - - DAT - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n - Reset value: 0x0 - [7:0] - read-write - - - - - IC_SS_SCL_HCNT - Standard Speed I2C Clock SCL High Count Register - 0x14 - 0x00000028 - - - IC_SS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n - NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. - [15:0] - read-write - - - - - IC_SS_SCL_LCNT - Standard Speed I2C Clock SCL Low Count Register - 0x18 - 0x0000002F - - - IC_SS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. - [15:0] - read-write - - - - - IC_FS_SCL_HCNT - Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register - 0x1C - 0x00000006 - - - IC_FS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - [15:0] - read-write - - - - - IC_FS_SCL_LCNT - Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register - 0x20 - 0x0000000D - - - IC_FS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. - [15:0] - read-write - - - - - IC_INTR_STAT - I2C Interrupt Status Register\n\n - Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. - 0x2C - 0x00000000 - - - R_RESTART_DET - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - R_RESTART_DET interrupt is inactive - 0 - - - ACTIVE - R_RESTART_DET interrupt is active - 1 - - - - - R_GEN_CALL - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - R_GEN_CALL interrupt is inactive - 0 - - - ACTIVE - R_GEN_CALL interrupt is active - 1 - - - - - R_START_DET - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - R_START_DET interrupt is inactive - 0 - - - ACTIVE - R_START_DET interrupt is active - 1 - - - - - R_STOP_DET - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n - Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - R_STOP_DET interrupt is inactive - 0 - - - ACTIVE - R_STOP_DET interrupt is active - 1 - - - - - R_ACTIVITY - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - R_ACTIVITY interrupt is inactive - 0 - - - ACTIVE - R_ACTIVITY interrupt is active - 1 - - - - - R_RX_DONE - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - R_RX_DONE interrupt is inactive - 0 - - - ACTIVE - R_RX_DONE interrupt is active - 1 - - - - - R_TX_ABRT - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - R_TX_ABRT interrupt is inactive - 0 - - - ACTIVE - R_TX_ABRT interrupt is active - 1 - - - - - R_RD_REQ - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - R_RD_REQ interrupt is inactive - 0 - - - ACTIVE - R_RD_REQ interrupt is active - 1 - - - - - R_TX_EMPTY - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n - Reset value: 0x0 - [4:4] - read-only - - - INACTIVE - R_TX_EMPTY interrupt is inactive - 0 - - - ACTIVE - R_TX_EMPTY interrupt is active - 1 - - - - - R_TX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n - Reset value: 0x0 - [3:3] - read-only - - - INACTIVE - R_TX_OVER interrupt is inactive - 0 - - - ACTIVE - R_TX_OVER interrupt is active - 1 - - - - - R_RX_FULL - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - R_RX_FULL interrupt is inactive - 0 - - - ACTIVE - R_RX_FULL interrupt is active - 1 - - - - - R_RX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - R_RX_OVER interrupt is inactive - 0 - - - ACTIVE - R_RX_OVER interrupt is active - 1 - - - - - R_RX_UNDER - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n - Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - RX_UNDER interrupt is inactive - 0 - - - ACTIVE - RX_UNDER interrupt is active - 1 - - - - - - - IC_INTR_MASK - I2C Interrupt Mask Register.\n\n - These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. - 0x30 - 0x000008FF - - - M_RESTART_DET - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - [12:12] - read-write - - - ENABLED - RESTART_DET interrupt is masked - 0 - - - DISABLED - RESTART_DET interrupt is unmasked - 1 - - - - - M_GEN_CALL - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [11:11] - read-write - - - ENABLED - GEN_CALL interrupt is masked - 0 - - - DISABLED - GEN_CALL interrupt is unmasked - 1 - - - - - M_START_DET - This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - [10:10] - read-write - - - ENABLED - START_DET interrupt is masked - 0 - - - DISABLED - START_DET interrupt is unmasked - 1 - - - - - M_STOP_DET - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - [9:9] - read-write - - - ENABLED - STOP_DET interrupt is masked - 0 - - - DISABLED - STOP_DET interrupt is unmasked - 1 - - - - - M_ACTIVITY - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - [8:8] - read-write - - - ENABLED - ACTIVITY interrupt is masked - 0 - - - DISABLED - ACTIVITY interrupt is unmasked - 1 - - - - - M_RX_DONE - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [7:7] - read-write - - - ENABLED - RX_DONE interrupt is masked - 0 - - - DISABLED - RX_DONE interrupt is unmasked - 1 - - - - - M_TX_ABRT - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [6:6] - read-write - - - ENABLED - TX_ABORT interrupt is masked - 0 - - - DISABLED - TX_ABORT interrupt is unmasked - 1 - - - - - M_RD_REQ - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [5:5] - read-write - - - ENABLED - RD_REQ interrupt is masked - 0 - - - DISABLED - RD_REQ interrupt is unmasked - 1 - - - - - M_TX_EMPTY - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [4:4] - read-write - - - ENABLED - TX_EMPTY interrupt is masked - 0 - - - DISABLED - TX_EMPTY interrupt is unmasked - 1 - - - - - M_TX_OVER - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [3:3] - read-write - - - ENABLED - TX_OVER interrupt is masked - 0 - - - DISABLED - TX_OVER interrupt is unmasked - 1 - - - - - M_RX_FULL - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [2:2] - read-write - - - ENABLED - RX_FULL interrupt is masked - 0 - - - DISABLED - RX_FULL interrupt is unmasked - 1 - - - - - M_RX_OVER - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [1:1] - read-write - - - ENABLED - RX_OVER interrupt is masked - 0 - - - DISABLED - RX_OVER interrupt is unmasked - 1 - - - - - M_RX_UNDER - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [0:0] - read-write - - - ENABLED - RX_UNDER interrupt is masked - 0 - - - DISABLED - RX_UNDER interrupt is unmasked - 1 - - - - - - - IC_RAW_INTR_STAT - I2C Raw Interrupt Status Register\n\n - Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. - 0x34 - 0x00000000 - - - RESTART_DET - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n - Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - RESTART_DET interrupt is inactive - 0 - - - ACTIVE - RESTART_DET interrupt is active - 1 - - - - - GEN_CALL - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - GEN_CALL interrupt is inactive - 0 - - - ACTIVE - GEN_CALL interrupt is active - 1 - - - - - START_DET - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - START_DET interrupt is inactive - 0 - - - ACTIVE - START_DET interrupt is active - 1 - - - - - STOP_DET - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n - In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - STOP_DET interrupt is inactive - 0 - - - ACTIVE - STOP_DET interrupt is active - 1 - - - - - ACTIVITY - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - RAW_INTR_ACTIVITY interrupt is inactive - 0 - - - ACTIVE - RAW_INTR_ACTIVITY interrupt is active - 1 - - - - - RX_DONE - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - RX_DONE interrupt is inactive - 0 - - - ACTIVE - RX_DONE interrupt is active - 1 - - - - - TX_ABRT - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - TX_ABRT interrupt is inactive - 0 - - - ACTIVE - TX_ABRT interrupt is active - 1 - - - - - RD_REQ - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - RD_REQ interrupt is inactive - 0 - - - ACTIVE - RD_REQ interrupt is active - 1 - - - - - TX_EMPTY - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n - Reset value: 0x0. - [4:4] - read-only - - - INACTIVE - TX_EMPTY interrupt is inactive - 0 - - - ACTIVE - TX_EMPTY interrupt is active - 1 - - - - - TX_OVER - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n - Reset value: 0x0 - [3:3] - read-only - - - INACTIVE - TX_OVER interrupt is inactive - 0 - - - ACTIVE - TX_OVER interrupt is active - 1 - - - - - RX_FULL - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - RX_FULL interrupt is inactive - 0 - - - ACTIVE - RX_FULL interrupt is active - 1 - - - - - RX_OVER - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - RX_OVER interrupt is inactive - 0 - - - ACTIVE - RX_OVER interrupt is active - 1 - - - - - RX_UNDER - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n - Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - RX_UNDER interrupt is inactive - 0 - - - ACTIVE - RX_UNDER interrupt is active - 1 - - - - - - - IC_RX_TL - I2C Receive FIFO Threshold Register - 0x38 - 0x00000000 - - - RX_TL - Receive FIFO Threshold Level.\n\n - Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. - [7:0] - read-write - - - - - IC_TX_TL - I2C Transmit FIFO Threshold Register - 0x3C - 0x00000000 - - - TX_TL - Transmit FIFO Threshold Level.\n\n - Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. - [7:0] - read-write - - - - - IC_CLR_INTR - Clear Combined and Individual Interrupt Register - 0x40 - 0x00000000 - - - CLR_INTR - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_UNDER - Clear RX_UNDER Interrupt Register - 0x44 - 0x00000000 - - - CLR_RX_UNDER - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_OVER - Clear RX_OVER Interrupt Register - 0x48 - 0x00000000 - - - CLR_RX_OVER - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_TX_OVER - Clear TX_OVER Interrupt Register - 0x4C - 0x00000000 - - - CLR_TX_OVER - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RD_REQ - Clear RD_REQ Interrupt Register - 0x50 - 0x00000000 - - - CLR_RD_REQ - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_TX_ABRT - Clear TX_ABRT Interrupt Register - 0x54 - 0x00000000 - - - CLR_TX_ABRT - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_DONE - Clear RX_DONE Interrupt Register - 0x58 - 0x00000000 - - - CLR_RX_DONE - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_ACTIVITY - Clear ACTIVITY Interrupt Register - 0x5C - 0x00000000 - - - CLR_ACTIVITY - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_STOP_DET - Clear STOP_DET Interrupt Register - 0x60 - 0x00000000 - - - CLR_STOP_DET - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_START_DET - Clear START_DET Interrupt Register - 0x64 - 0x00000000 - - - CLR_START_DET - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_GEN_CALL - Clear GEN_CALL Interrupt Register - 0x68 - 0x00000000 - - - CLR_GEN_CALL - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_ENABLE - I2C Enable Register - 0x6C - 0x00000000 - - - TX_CMD_BLOCK - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT - [2:2] - read-write - - - NOT_BLOCKED - Tx Command execution not blocked - 0 - - - BLOCKED - Tx Command execution blocked - 1 - - - - - ABORT - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n - Reset value: 0x0 - [1:1] - read-write - - - DISABLE - ABORT operation not in progress - 0 - - - ENABLED - ABORT operation in progress - 1 - - - - - ENABLE - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n - Reset value: 0x0 - [0:0] - read-write - - - DISABLED - I2C is disabled - 0 - - - ENABLED - I2C is enabled - 1 - - - - - - - IC_STATUS - I2C Status Register\n\n - This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\n\n - When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 - 0x70 - 0x00000006 - - - SLV_ACTIVITY - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 - [6:6] - read-only - - - IDLE - Slave is idle - 0 - - - ACTIVE - Slave not idle - 1 - - - - - MST_ACTIVITY - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n - Reset value: 0x0 - [5:5] - read-only - - - IDLE - Master is idle - 0 - - - ACTIVE - Master not idle - 1 - - - - - RFF - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 - [4:4] - read-only - - - NOT_FULL - Rx FIFO not full - 0 - - - FULL - Rx FIFO is full - 1 - - - - - RFNE - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 - [3:3] - read-only - - - EMPTY - Rx FIFO is empty - 0 - - - NOT_EMPTY - Rx FIFO not empty - 1 - - - - - TFE - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 - [2:2] - read-only - - - NON_EMPTY - Tx FIFO not empty - 0 - - - EMPTY - Tx FIFO is empty - 1 - - - - - TFNF - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 - [1:1] - read-only - - - FULL - Tx FIFO is full - 0 - - - NOT_FULL - Tx FIFO not full - 1 - - - - - ACTIVITY - I2C Activity Status. Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - I2C is idle - 0 - - - ACTIVE - I2C is active - 1 - - - - - - - IC_TXFLR - I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. - 0x74 - 0x00000000 - - - TXFLR - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n - Reset value: 0x0 - [4:0] - read-only - - - - - IC_RXFLR - I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. - 0x78 - 0x00000000 - - - RXFLR - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n - Reset value: 0x0 - [4:0] - read-only - - - - - IC_SDA_HOLD - I2C SDA Hold Time Length Register\n\n - The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n - The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n - Writes to this register succeed only when IC_ENABLE[0]=0.\n\n - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. - 0x7C - 0x00000001 - - - IC_SDA_RX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n - Reset value: IC_DEFAULT_SDA_HOLD[23:16]. - [23:16] - read-write - - - IC_SDA_TX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n - Reset value: IC_DEFAULT_SDA_HOLD[15:0]. - [15:0] - read-write - - - - - IC_TX_ABRT_SOURCE - I2C Transmit Abort Source Register\n\n - This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\n\n - Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. - 0x80 - 0x00000000 - - - TX_FLUSH_CNT - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [31:23] - read-only - - - ABRT_USER_ABRT - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [16:16] - read-only - - - ABRT_USER_ABRT_VOID - Transfer abort detected by master- scenario not present - 0 - - - ABRT_USER_ABRT_GENERATED - Transfer abort detected by master - 1 - - - - - ABRT_SLVRD_INTX - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Slave-Transmitter - [15:15] - read-only - - - ABRT_SLVRD_INTX_VOID - Slave trying to transmit to remote master in read mode- scenario not present - 0 - - - ABRT_SLVRD_INTX_GENERATED - Slave trying to transmit to remote master in read mode - 1 - - - - - ABRT_SLV_ARBLOST - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Slave-Transmitter - [14:14] - read-only - - - ABRT_SLV_ARBLOST_VOID - Slave lost arbitration to remote master- scenario not present - 0 - - - ABRT_SLV_ARBLOST_GENERATED - Slave lost arbitration to remote master - 1 - - - - - ABRT_SLVFLUSH_TXFIFO - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Slave-Transmitter - [13:13] - read-only - - - ABRT_SLVFLUSH_TXFIFO_VOID - Slave flushes existing data in TX-FIFO upon getting read command- scenario not present - 0 - - - ABRT_SLVFLUSH_TXFIFO_GENERATED - Slave flushes existing data in TX-FIFO upon getting read command - 1 - - - - - ARB_LOST - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [12:12] - read-only - - - ABRT_LOST_VOID - Master or Slave-Transmitter lost arbitration- scenario not present - 0 - - - ABRT_LOST_GENERATED - Master or Slave-Transmitter lost arbitration - 1 - - - - - ABRT_MASTER_DIS - This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [11:11] - read-only - - - ABRT_MASTER_DIS_VOID - User initiating master operation when MASTER disabled- scenario not present - 0 - - - ABRT_MASTER_DIS_GENERATED - User initiating master operation when MASTER disabled - 1 - - - - - ABRT_10B_RD_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Receiver - [10:10] - read-only - - - ABRT_10B_RD_VOID - Master not trying to read in 10Bit addressing mode when RESTART disabled - 0 - - - ABRT_10B_RD_GENERATED - Master trying to read in 10Bit addressing mode when RESTART disabled - 1 - - - - - ABRT_SBYTE_NORSTRT - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master - [9:9] - read-only - - - ABRT_SBYTE_NORSTRT_VOID - User trying to send START byte when RESTART disabled- scenario not present - 0 - - - ABRT_SBYTE_NORSTRT_GENERATED - User trying to send START byte when RESTART disabled - 1 - - - - - ABRT_HS_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [8:8] - read-only - - - ABRT_HS_NORSTRT_VOID - User trying to switch Master to HS mode when RESTART disabled- scenario not present - 0 - - - ABRT_HS_NORSTRT_GENERATED - User trying to switch Master to HS mode when RESTART disabled - 1 - - - - - ABRT_SBYTE_ACKDET - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master - [7:7] - read-only - - - ABRT_SBYTE_ACKDET_VOID - ACK detected for START byte- scenario not present - 0 - - - ABRT_SBYTE_ACKDET_GENERATED - ACK detected for START byte - 1 - - - - - ABRT_HS_ACKDET - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master - [6:6] - read-only - - - ABRT_HS_ACK_VOID - HS Master code ACKed in HS Mode- scenario not present - 0 - - - ABRT_HS_ACK_GENERATED - HS Master code ACKed in HS Mode - 1 - - - - - ABRT_GCALL_READ - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [5:5] - read-only - - - ABRT_GCALL_READ_VOID - GCALL is followed by read from bus-scenario not present - 0 - - - ABRT_GCALL_READ_GENERATED - GCALL is followed by read from bus - 1 - - - - - ABRT_GCALL_NOACK - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [4:4] - read-only - - - ABRT_GCALL_NOACK_VOID - GCALL not ACKed by any slave-scenario not present - 0 - - - ABRT_GCALL_NOACK_GENERATED - GCALL not ACKed by any slave - 1 - - - - - ABRT_TXDATA_NOACK - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [3:3] - read-only - - - ABRT_TXDATA_NOACK_VOID - Transmitted data non-ACKed by addressed slave-scenario not present - 0 - - - ABRT_TXDATA_NOACK_GENERATED - Transmitted data not ACKed by addressed slave - 1 - - - - - ABRT_10ADDR2_NOACK - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [2:2] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - Byte 2 of 10Bit Address not ACKed by any slave - 1 - - - - - ABRT_10ADDR1_NOACK - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [1:1] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - Byte 1 of 10Bit Address not ACKed by any slave - 1 - - - - - ABRT_7B_ADDR_NOACK - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [0:0] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - This abort is generated because of NOACK for 7-bit address - 1 - - - - - - - IC_SLV_DATA_NACK_ONLY - Generate Slave Data NACK Register\n\n - The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\n\n - A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. - 0x84 - 0x00000000 - - - NACK - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 - [0:0] - read-write - - - DISABLED - Slave receiver generates NACK normally - 0 - - - ENABLED - Slave receiver generates NACK upon data reception only - 1 - - - - - - - IC_DMA_CR - DMA Control Register\n\n - The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. - 0x88 - 0x00000000 - - - TDMAE - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 - [1:1] - read-write - - - DISABLED - transmit FIFO DMA channel disabled - 0 - - - ENABLED - Transmit FIFO DMA channel enabled - 1 - - - - - RDMAE - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 - [0:0] - read-write - - - DISABLED - Receive FIFO DMA channel disabled - 0 - - - ENABLED - Receive FIFO DMA channel enabled - 1 - - - - - - - IC_DMA_TDLR - DMA Transmit Data Level Register - 0x8C - 0x00000000 - - - DMATDL - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n - Reset value: 0x0 - [3:0] - read-write - - - - - IC_DMA_RDLR - I2C Receive Data Level Register - 0x90 - 0x00000000 - - - DMARDL - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n - Reset value: 0x0 - [3:0] - read-write - - - - - IC_SDA_SETUP - I2C SDA Setup Register\n\n - This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\n\n - Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n - Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. - 0x94 - 0x00000064 - - - SDA_SETUP - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. - [7:0] - read-write - - - - - IC_ACK_GENERAL_CALL - I2C ACK General Call Register\n\n - The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n - This register is applicable only when the DW_apb_i2c is in slave mode. - 0x98 - 0x00000001 - - - ACK_GEN_CALL - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). - [0:0] - read-write - - - DISABLED - Generate NACK for a General Call - 0 - - - ENABLED - Generate ACK for a General Call - 1 - - - - - - - IC_ENABLE_STATUS - I2C Enable Status Register\n\n - The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\n\n - If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\n\n - If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\n\n - Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. - 0x9C - 0x00000000 - - - SLV_RX_DATA_LOST - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n - When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - Slave RX Data is not lost - 0 - - - ACTIVE - Slave RX Data is lost - 1 - - - - - SLV_DISABLED_WHILE_BUSY - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n - OR,\n\n - (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n - When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n - When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - Slave is disabled when it is idle - 0 - - - ACTIVE - Slave is disabled when it is active - 1 - - - - - IC_EN - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n - Reset value: 0x0 - [0:0] - read-only - - - DISABLED - I2C disabled - 0 - - - ENABLED - I2C enabled - 1 - - - - - - - IC_FS_SPKLEN - I2C SS, FS or FM+ spike suppression limit\n\n - This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. - 0xA0 - 0x00000007 - - - IC_FS_SPKLEN - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. - [7:0] - read-write - - - - - IC_CLR_RESTART_DET - Clear RESTART_DET Interrupt Register - 0xA8 - 0x00000000 - - - CLR_RESTART_DET - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_COMP_PARAM_1 - Component Parameter Register 1\n\n - Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters - 0xF4 - 0x00000000 - - - TX_BUFFER_DEPTH - TX Buffer Depth = 16 - [23:16] - read-only - - - RX_BUFFER_DEPTH - RX Buffer Depth = 16 - [15:8] - read-only - - - ADD_ENCODED_PARAMS - Encoded parameters not visible - [7:7] - read-only - - - HAS_DMA - DMA handshaking signals are enabled - [6:6] - read-only - - - INTR_IO - COMBINED Interrupt outputs - [5:5] - read-only - - - HC_COUNT_VALUES - Programmable count values for each mode. - [4:4] - read-only - - - MAX_SPEED_MODE - MAX SPEED MODE = FAST MODE - [3:2] - read-only - - - APB_DATA_WIDTH - APB data bus width is 32 bits - [1:0] - read-only - - - - - IC_COMP_VERSION - I2C Component Version Register - 0xF8 - 0x3230312A - - - IC_COMP_VERSION - [31:0] - read-only - - - - - IC_COMP_TYPE - I2C Component Type Register - 0xFC - 0x44570140 - - - IC_COMP_TYPE - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. - [31:0] - read-only - - - - - - - I2C1 - 0x40048000 - - I2C1_IRQ - 24 - - - - ADC - 2 - Control and data interface to SAR ADC - 0x4004C000 - 0x20 - - 0x0 - 0x1000 - registers - - - ADC_IRQ_FIFO - 22 - - - - CS - ADC Control and Status - 0x0 - 0x00000000 - - - RROBIN - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n - Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n - The first channel to be sampled will be the one currently indicated by AINSEL.\n - AINSEL will be updated after each conversion with the newly-selected channel. - [20:16] - read-write - - - AINSEL - Select analog mux input. Updated automatically in round-robin mode. - [14:12] - read-write - - - ERR_STICKY - Some past ADC conversion encountered an error. Write 1 to clear. - [10:10] - read-write - oneToClear - - - ERR - The most recent ADC conversion encountered an error; result is undefined or noisy. - [9:9] - read-only - - - READY - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n - 0 whilst conversion in progress. - [8:8] - read-only - - - START_MANY - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. - [3:3] - read-write - - - START_ONCE - Start a single conversion. Self-clearing. Ignored if start_many is asserted. - [2:2] - read-write - clear - - - TS_EN - Power on temperature sensor. 1 - enabled. 0 - disabled. - [1:1] - read-write - - - EN - Power on ADC and enable its clock.\n - 1 - enabled. 0 - disabled. - [0:0] - read-write - - - - - RESULT - Result of most recent ADC conversion - 0x4 - 0x00000000 - - - RESULT - [11:0] - read-only - - - - - FCS - FIFO control and status - 0x8 - 0x00000000 - - - THRESH - DREQ/IRQ asserted when level >= threshold - [27:24] - read-write - - - LEVEL - The number of conversion results currently waiting in the FIFO - [19:16] - read-only - - - OVER - 1 if the FIFO has been overflowed. Write 1 to clear. - [11:11] - read-write - oneToClear - - - UNDER - 1 if the FIFO has been underflowed. Write 1 to clear. - [10:10] - read-write - oneToClear - - - FULL - [9:9] - read-only - - - EMPTY - [8:8] - read-only - - - DREQ_EN - If 1: assert DMA requests when FIFO contains data - [3:3] - read-write - - - ERR - If 1: conversion error bit appears in the FIFO alongside the result - [2:2] - read-write - - - SHIFT - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. - [1:1] - read-write - - - EN - If 1: write result to the FIFO after each conversion. - [0:0] - read-write - - - - - FIFO - Conversion result FIFO - 0xC - 0x00000000 - - - ERR - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. - [15:15] - read-only - - - VAL - [11:0] - read-only - - - - - DIV - Clock divider. If non-zero, CS_START_MANY will start conversions\n - at regular intervals rather than back-to-back.\n - The divider is reset when either of these fields are written.\n - Total period is 1 + INT + FRAC / 256 - 0x10 - 0x00000000 - - - INT - Integer part of clock divisor. - [23:8] - read-write - - - FRAC - Fractional part of clock divisor. First-order delta-sigma. - [7:0] - read-write - - - - - INTR - Raw Interrupts - 0x14 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x18 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x1C - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x20 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - - - PWM - 1 - Simple PWM - 0x40050000 - 0x20 - - 0x0 - 0x1000 - registers - - - PWM_IRQ_WRAP - 4 - - - - 8 - 0x14 - 0-7 - CH%s - Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP - 0x0 - - CC - Counter compare values - 0xC - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CSR - Control and status register - 0x0 - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running\n - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - read-write - clear - - - PH_RET - Retard the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - read-write - clear - - - DIVMODE - [5:4] - read-write - - - div - Free-running counting at rate dictated by fractional divider - 0 - - - level - Fractional divider operation is gated by the PWM B pin. - 1 - - - rise - Counter advances with each rising edge of the PWM B pin. - 2 - - - fall - Counter advances with each falling edge of the PWM B pin. - 3 - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CTR - Direct access to the PWM counter - 0x8 - 0x00000000 - - - CTR - [15:0] - read-write - - - - - DIV - INT and FRAC form a fixed-point fractional number.\n - Counting rate is system clock frequency divided by this number.\n - Fractional division uses simple 1st-order sigma-delta. - 0x4 - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - TOP - Counter wrap value - 0x10 - 0x0000FFFF - - - TOP - [15:0] - read-write - - - - - - EN - This register aliases the CSR_EN bits for all channels.\n - Writing to this register allows multiple channels to be enabled\n - or disabled simultaneously, so they can run in perfect sync.\n - For each channel, there is only one physical EN register bit,\n - which can be accessed through here or CHx_CSR. - 0xA0 - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTR - Raw Interrupts - 0xA4 - 0x00000000 - - - CH7 - [7:7] - read-write - oneToClear - - - CH6 - [6:6] - read-write - oneToClear - - - CH5 - [5:5] - read-write - oneToClear - - - CH4 - [4:4] - read-write - oneToClear - - - CH3 - [3:3] - read-write - oneToClear - - - CH2 - [2:2] - read-write - oneToClear - - - CH1 - [1:1] - read-write - oneToClear - - - CH0 - [0:0] - read-write - oneToClear - - - - - INTE - Interrupt Enable - 0xA8 - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTF - Interrupt Force - 0xAC - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0xB0 - 0x00000000 - - - CH7 - [7:7] - read-only - - - CH6 - [6:6] - read-only - - - CH5 - [5:5] - read-only - - - CH4 - [4:4] - read-only - - - CH3 - [3:3] - read-only - - - CH2 - [2:2] - read-only - - - CH1 - [1:1] - read-only - - - CH0 - [0:0] - read-only - - - - - - - TIMER - 1 - Controls time and alarms\n - time is a 64 bit value indicating the time in usec since power-on\n - timeh is the top 32 bits of time & timel is the bottom 32 bits\n - to change time write to timelw before timehw\n - to read time read from timelr before timehr\n - An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n - When an alarm is pending, the corresponding alarm_running signal will be high\n - An alarm can be cancelled before it has finished by clearing the alarm_enable\n - When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n - To clear the interrupt write a 1 to the corresponding alarm_irq - 0x40054000 - 0x20 - - 0x0 - 0x1000 - registers - - - TIMER_IRQ_0 - 0 - - - TIMER_IRQ_1 - 1 - - - TIMER_IRQ_2 - 2 - - - TIMER_IRQ_3 - 3 - - - - TIMEHW - Write to bits 63:32 of time\n - always write timelw before timehw - 0x0 - write-only - 0x00000000 - - - TIMELW - Write to bits 31:0 of time\n - writes do not get copied to time until timehw is written - 0x4 - write-only - 0x00000000 - - - TIMEHR - Read from bits 63:32 of time\n - always read timelr before timehr - 0x8 - read-only - 0x00000000 - - - TIMELR - Read from bits 31:0 of time - 0xC - read-only - 0x00000000 - - - ALARM0 - Arm alarm 0, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x10 - read-write - 0x00000000 - - - ALARM1 - Arm alarm 1, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x14 - read-write - 0x00000000 - - - ALARM2 - Arm alarm 2, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x18 - read-write - 0x00000000 - - - ALARM3 - Arm alarm 3, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x1C - read-write - 0x00000000 - - - ARMED - Indicates the armed/disarmed status of each alarm.\n - A write to the corresponding ALARMx register arms the alarm.\n - Alarms automatically disarm upon firing, but writing ones here\n - will disarm immediately without waiting to fire. - 0x20 - 0x00000000 - - - ARMED - [3:0] - read-write - oneToClear - - - - - TIMERAWH - Raw read from bits 63:32 of time (no side effects) - 0x24 - read-only - 0x00000000 - - - TIMERAWL - Raw read from bits 31:0 of time (no side effects) - 0x28 - read-only - 0x00000000 - - - DBGPAUSE - Set bits high to enable pause when the corresponding debug ports are active - 0x2C - 0x00000007 - - - DBG1 - Pause when processor 1 is in debug mode - [2:2] - read-write - - - DBG0 - Pause when processor 0 is in debug mode - [1:1] - read-write - - - - - PAUSE - Set high to pause the timer - 0x30 - 0x00000000 - - - PAUSE - [0:0] - read-write - - - - - INTR - Raw Interrupts - 0x34 - 0x00000000 - - - ALARM_3 - [3:3] - read-write - oneToClear - - - ALARM_2 - [2:2] - read-write - oneToClear - - - ALARM_1 - [1:1] - read-write - oneToClear - - - ALARM_0 - [0:0] - read-write - oneToClear - - - - - INTE - Interrupt Enable - 0x38 - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x3C - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x40 - 0x00000000 - - - ALARM_3 - [3:3] - read-only - - - ALARM_2 - [2:2] - read-only - - - ALARM_1 - [1:1] - read-only - - - ALARM_0 - [0:0] - read-only - - - - - - - WATCHDOG - 1 - 0x40058000 - 0x20 - - 0x0 - 0x1000 - registers - - - - CTRL - Watchdog control\n - The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\n - The watchdog can be triggered in software. - 0x0 - 0x07000000 - - - TRIGGER - Trigger a watchdog reset - [31:31] - read-write - clear - - - ENABLE - When not enabled the watchdog timer is paused - [30:30] - read-write - - - PAUSE_DBG1 - Pause the watchdog timer when processor 1 is in debug mode - [26:26] - read-write - - - PAUSE_DBG0 - Pause the watchdog timer when processor 0 is in debug mode - [25:25] - read-write - - - PAUSE_JTAG - Pause the watchdog timer when JTAG is accessing the bus fabric - [24:24] - read-write - - - TIME - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered - [23:0] - read-only - - - - - LOAD - Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). - 0x4 - 0x00000000 - - - LOAD - [23:0] - write-only - - - - - REASON - Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. - 0x8 - 0x00000000 - - - FORCE - [1:1] - read-only - - - TIMER - [0:0] - read-only - - - - - SCRATCH0 - Scratch register. Information persists through soft reset of the chip. - 0xC - read-write - 0x00000000 - - - SCRATCH1 - Scratch register. Information persists through soft reset of the chip. - 0x10 - read-write - 0x00000000 - - - SCRATCH2 - Scratch register. Information persists through soft reset of the chip. - 0x14 - read-write - 0x00000000 - - - SCRATCH3 - Scratch register. Information persists through soft reset of the chip. - 0x18 - read-write - 0x00000000 - - - SCRATCH4 - Scratch register. Information persists through soft reset of the chip. - 0x1C - read-write - 0x00000000 - - - SCRATCH5 - Scratch register. Information persists through soft reset of the chip. - 0x20 - read-write - 0x00000000 - - - SCRATCH6 - Scratch register. Information persists through soft reset of the chip. - 0x24 - read-write - 0x00000000 - - - SCRATCH7 - Scratch register. Information persists through soft reset of the chip. - 0x28 - read-write - 0x00000000 - - - TICK - Controls the tick generator - 0x2C - 0x00000200 - - - COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [19:11] - read-only - - - RUNNING - Is the tick generator running? - [10:10] - read-only - - - ENABLE - start / stop tick generation - [9:9] - read-write - - - CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - - - RTC - 1 - Register block to control RTC - 0x4005C000 - 0x20 - - 0x0 - 0x1000 - registers - - - RTC_IRQ - 25 - - - - CLKDIV_M1 - Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. - 0x0 - 0x00000000 - - - CLKDIV_M1 - [15:0] - read-write - - - - - SETUP_0 - RTC setup register 0 - 0x4 - 0x00000000 - - - YEAR - Year - [23:12] - read-write - - - MONTH - Month (1..12) - [11:8] - read-write - - - DAY - Day of the month (1..31) - [4:0] - read-write - - - - - SETUP_1 - RTC setup register 1 - 0x8 - 0x00000000 - - - DOTW - Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 - [26:24] - read-write - - - HOUR - Hours - [20:16] - read-write - - - MIN - Minutes - [13:8] - read-write - - - SEC - Seconds - [5:0] - read-write - - - - - CTRL - RTC Control and status - 0xC - 0x00000000 - - - FORCE_NOTLEAPYEAR - If set, leapyear is forced off.\n - Useful for years divisible by 100 but not by 400 - [8:8] - read-write - - - LOAD - Load RTC - [4:4] - read-write - clear - - - RTC_ACTIVE - RTC enabled (running) - [1:1] - read-only - - - RTC_ENABLE - Enable RTC - [0:0] - read-write - - - - - IRQ_SETUP_0 - Interrupt setup register 0 - 0x10 - 0x00000000 - - - MATCH_ACTIVE - [29:29] - read-only - - - MATCH_ENA - Global match enable. Don't change any other value while this one is enabled - [28:28] - read-write - - - YEAR_ENA - Enable year matching - [26:26] - read-write - - - MONTH_ENA - Enable month matching - [25:25] - read-write - - - DAY_ENA - Enable day matching - [24:24] - read-write - - - YEAR - Year - [23:12] - read-write - - - MONTH - Month (1..12) - [11:8] - read-write - - - DAY - Day of the month (1..31) - [4:0] - read-write - - - - - IRQ_SETUP_1 - Interrupt setup register 1 - 0x14 - 0x00000000 - - - DOTW_ENA - Enable day of the week matching - [31:31] - read-write - - - HOUR_ENA - Enable hour matching - [30:30] - read-write - - - MIN_ENA - Enable minute matching - [29:29] - read-write - - - SEC_ENA - Enable second matching - [28:28] - read-write - - - DOTW - Day of the week - [26:24] - read-write - - - HOUR - Hours - [20:16] - read-write - - - MIN - Minutes - [13:8] - read-write - - - SEC - Seconds - [5:0] - read-write - - - - - RTC_1 - RTC register 1. - 0x18 - 0x00000000 - - - YEAR - Year - [23:12] - read-only - - - MONTH - Month (1..12) - [11:8] - read-only - - - DAY - Day of the month (1..31) - [4:0] - read-only - - - - - RTC_0 - RTC register 0\n - Read this before RTC 1! - 0x1C - 0x00000000 - - - DOTW - Day of the week - [26:24] - read-only - - - HOUR - Hours - [20:16] - read-only - - - MIN - Minutes - [13:8] - read-only - - - SEC - Seconds - [5:0] - read-only - - - - - INTR - Raw Interrupts - 0x20 - 0x00000000 - - - RTC - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x24 - 0x00000000 - - - RTC - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x28 - 0x00000000 - - - RTC - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x2C - 0x00000000 - - - RTC - [0:0] - read-only - - - - - - - ROSC - 1 - 0x40060000 - 0x20 - - 0x0 - 0x1000 - registers - - - - CTRL - Ring Oscillator control - 0x0 - 0x00000AA0 - - - ENABLE - On power-up this field is initialised to ENABLE\n - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - Controls the number of delay stages in the ROSC ring\n - LOW uses stages 0 to 7\n - MEDIUM uses stages 0 to 5\n - HIGH uses stages 0 to 3\n - TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n - The clock output will not glitch when changing the range up one step at a time\n - The clock output will glitch when changing the range down\n - Note: the values here are gray coded which is why HIGH comes before TOOHIGH - [11:0] - read-write - - - LOW - 4004 - - - MEDIUM - 4005 - - - HIGH - 4007 - - - TOOHIGH - 4006 - - - - - - - FREQA - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage\n - The drive strength has 4 levels determined by the number of bits set\n - Increasing the number of bits set increases the drive strength and increases the oscillation frequency\n - 0 bits set is the default drive strength\n - 1 bit set doubles the drive strength\n - 2 bits set triples drive strength\n - 3 bits set quadruples drive strength - 0x4 - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings\n - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS3 - Stage 3 drive strength - [14:12] - read-write - - - DS2 - Stage 2 drive strength - [10:8] - read-write - - - DS1 - Stage 1 drive strength - [6:4] - read-write - - - DS0 - Stage 0 drive strength - [2:0] - read-write - - - - - FREQB - For a detailed description see freqa register - 0x8 - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings\n - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS7 - Stage 7 drive strength - [14:12] - read-write - - - DS6 - Stage 6 drive strength - [10:8] - read-write - - - DS5 - Stage 5 drive strength - [6:4] - read-write - - - DS4 - Stage 4 drive strength - [2:0] - read-write - - - - - DORMANT - Ring Oscillator pause control\n - This is used to save power by pausing the ROSC\n - On power-up this field is initialised to WAKE\n - An invalid write will also select WAKE\n - Warning: setup the irq before selecting dormant mode - 0xC - read-write - 0x00000000 - - - DIV - Controls the output divider - 0x10 - 0x00000000 - - - DIV - set to 0xaa0 + div where\n - div = 0 divides by 32\n - div = 1-31 divides by div\n - any other value sets div=31\n - this register resets to div=16 - [11:0] - read-write - - - PASS - 2720 - - - - - - - PHASE - Controls the phase shifted output - 0x14 - 0x00000008 - - - PASSWD - set to 0xaa\n - any other value enables the output with shift=0 - [11:4] - read-write - - - ENABLE - enable the phase-shifted output\n - this can be changed on-the-fly - [3:3] - read-write - - - FLIP - invert the phase-shifted output\n - this is ignored when div=1 - [2:2] - read-write - - - SHIFT - phase shift the phase-shifted output by SHIFT input clocks\n - this can be changed on-the-fly\n - must be set to 0 before setting div=1 - [1:0] - read-write - - - - - RANDOMBIT - This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency - 0x1C - 0x00000001 - - - RANDOMBIT - [0:0] - read-only - - - - - STATUS - Ring Oscillator Status - 0x18 - 0x00000000 - - - STABLE - Oscillator is running and stable - 31 - 1 - read-only - - - DIV_RUNNING - post-divider is running - this resets to 0 but transitions to 1 during chip startup - 16 - 1 - read-only - - - ENABLED - Oscillator is enabled but not necessarily running and stable - this resets to 0 but transitions to 1 during chip startup - 12 - 1 - read-only - - - - - - - VREG_AND_CHIP_RESET - 1 - control and status for on-chip voltage regulator and chip level reset subsystem - 0x40064000 - 0x20 - - 0x0 - 0x1000 - registers - - - - VREG - Voltage regulator control and status - 0x0 - 0x000000B1 - - - ROK - regulation status\n - 0=not in regulation, 1=in regulation - [12:12] - read-only - - - VSEL - Output voltage select for on-chip voltage regulator. - [7:4] - read-write - - VSEL - - Voltage0_80 - 0.80V - 5 - - - Voltage0_85 - 0.85V - 6 - - - Voltage0_90 - 0.90V - 7 - - - Voltage0_95 - 0.95V - 8 - - - Voltage1_00 - 1.00V - 9 - - - Voltage1_05 - 1.05V - 10 - - - Voltage1_10 - 1.10V (default) - 11 - - - Voltage1_15 - 1.15V - 12 - - - Voltage1_20 - 1.20V - 13 - - - Voltage1_25 - 1.25V - 14 - - - Voltage1_30 - 1.30V - 15 - - - - - HIZ - high impedance mode select\n - 0=not in high impedance mode, 1=in high impedance mode - [1:1] - read-write - - - EN - enable\n - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - BOD - brown-out detection control - 0x4 - 0x00000091 - - - VSEL - threshold select\n - 0000 - 0.473V\n - 0001 - 0.516V\n - 0010 - 0.559V\n - 0011 - 0.602V\n - 0100 - 0.645V\n - 0101 - 0.688V\n - 0110 - 0.731V\n - 0111 - 0.774V\n - 1000 - 0.817V\n - 1001 - 0.860V (default)\n - 1010 - 0.903V\n - 1011 - 0.946V\n - 1100 - 0.989V\n - 1101 - 1.032V\n - 1110 - 1.075V\n - 1111 - 1.118V - [7:4] - read-write - - - EN - enable\n - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - CHIP_RESET - Chip reset control and status - 0x8 - 0x00000000 - - - PSM_RESTART_FLAG - This is set by psm_restart from the debugger.\n - Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n - In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. - [24:24] - read-write - oneToClear - - - HAD_PSM_RESTART - Last reset was from the debug port - [20:20] - read-only - - - HAD_RUN - Last reset was from the RUN pin - [16:16] - read-only - - - HAD_POR - Last reset was from the power-on reset or brown-out detection blocks - [8:8] - read-only - - - - - - - TBMAN - 1 - Testbench manager. Allows the programmer to know what platform their software is running on. - 0x4006C000 - 0x20 - - 0x0 - 0x1000 - registers - - - - PLATFORM - Indicates the type of platform in use - 0x0 - 0x00000005 - - - FPGA - Indicates the platform is an FPGA - [1:1] - read-only - - - ASIC - Indicates the platform is an ASIC - [0:0] - read-only - - - - - - - DMA - 1 - DMA with separate read and write masters - 0x50000000 - 0x20 - - 0x0 - 0x1000 - registers - - - DMA_IRQ_0 - 11 - - - DMA_IRQ_1 - 12 - - - - 12 - 0x40 - 0-11 - CH%s - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG - 0x0 - - CH_READ_ADDR - DMA Channel 0 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0 - read-write - 0x00000000 - - - CH_WRITE_ADDR - DMA Channel 0 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x4 - read-write - 0x00000000 - - - CH_TRANS_COUNT - DMA Channel 0 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x8 - read-write - 0x00000000 - - - CH_CTRL_TRIG - DMA Channel 0 Control and Status - 0xC - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - TREQ_SEL - - PIO0_TX0 - Select PIO0's TX FIFO 0 as TREQ - 0 - - - PIO0_TX1 - Select PIO0's TX FIFO 1 as TREQ - 1 - - - PIO0_TX2 - Select PIO0's TX FIFO 2 as TREQ - 2 - - - PIO0_TX3 - Select PIO0's TX FIFO 3 as TREQ - 3 - - - PIO0_RX0 - Select PIO0's RX FIFO 0 as TREQ - 4 - - - PIO0_RX1 - Select PIO0's RX FIFO 1 as TREQ - 5 - - - PIO0_RX2 - Select PIO0's RX FIFO 2 as TREQ - 6 - - - PIO0_RX3 - Select PIO0's RX FIFO 3 as TREQ - 7 - - - PIO1_TX0 - Select PIO1's TX FIFO 0 as TREQ - 8 - - - PIO1_TX1 - Select PIO1's TX FIFO 1 as TREQ - 9 - - - PIO1_TX2 - Select PIO1's TX FIFO 2 as TREQ - 10 - - - PIO1_TX3 - Select PIO1's TX FIFO 3 as TREQ - 11 - - - PIO1_RX0 - Select PIO1's RX FIFO 0 as TREQ - 12 - - - PIO1_RX1 - Select PIO1's RX FIFO 1 as TREQ - 13 - - - PIO1_RX2 - Select PIO1's RX FIFO 2 as TREQ - 14 - - - PIO1_RX3 - Select PIO1's RX FIFO 3 as TREQ - 15 - - - SPI0_TX - Select SPI0's TX FIFO as TREQ - 16 - - - SPI0_RX - Select SPI0's RX FIFO as TREQ - 17 - - - SPI1_TX - Select SPI1's TX FIFO as TREQ - 18 - - - SPI1_RX - Select SPI1's RX FIFO as TREQ - 19 - - - UART0_TX - Select UART0's TX FIFO as TREQ - 20 - - - UART0_RX - Select UART0's RX FIFO as TREQ - 21 - - - UART1_TX - Select UART1's TX FIFO as TREQ - 22 - - - UART1_RX - Select UART1's RX FIFO as TREQ - 23 - - - PWM_WRAP0 - Select PWM Counter 0's Wrap Value as TREQ - 24 - - - PWM_WRAP1 - Select PWM Counter 1's Wrap Value as TREQ - 25 - - - PWM_WRAP2 - Select PWM Counter 2's Wrap Value as TREQ - 26 - - - PWM_WRAP3 - Select PWM Counter 3's Wrap Value as TREQ - 27 - - - PWM_WRAP4 - Select PWM Counter 4's Wrap Value as TREQ - 28 - - - PWM_WRAP5 - Select PWM Counter 5's Wrap Value as TREQ - 29 - - - PWM_WRAP6 - Select PWM Counter 6's Wrap Value as TREQ - 30 - - - PWM_WRAP7 - Select PWM Counter 7's Wrap Value as TREQ - 31 - - - I2C0_TX - Select I2C0's TX FIFO as TREQ - 32 - - - I2C0_RX - Select I2C0's RX FIFO as TREQ - 33 - - - I2C1_TX - Select I2C1's TX FIFO as TREQ - 34 - - - I2C1_RX - Select I2C1's RX FIFO as TREQ - 35 - - - ADC - Select the ADC as TREQ - 36 - - - XIP_STREAM - Select the XIP Streaming FIFO as TREQ - 37 - - - XIP_SSITX - Select the XIP SSI TX FIFO as TREQ - 38 - - - XIP_SSIRX - Select the XIP SSI RX FIFO as TREQ - 39 - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH_AL1_CTRL - DMA Channel 0 Control and Status - 0x10 - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - TREQ_SEL - - PIO0_TX0 - Select PIO0's TX FIFO 0 as TREQ - 0 - - - PIO0_TX1 - Select PIO0's TX FIFO 1 as TREQ - 1 - - - PIO0_TX2 - Select PIO0's TX FIFO 2 as TREQ - 2 - - - PIO0_TX3 - Select PIO0's TX FIFO 3 as TREQ - 3 - - - PIO0_RX0 - Select PIO0's RX FIFO 0 as TREQ - 4 - - - PIO0_RX1 - Select PIO0's RX FIFO 1 as TREQ - 5 - - - PIO0_RX2 - Select PIO0's RX FIFO 2 as TREQ - 6 - - - PIO0_RX3 - Select PIO0's RX FIFO 3 as TREQ - 7 - - - PIO1_TX0 - Select PIO1's TX FIFO 0 as TREQ - 8 - - - PIO1_TX1 - Select PIO1's TX FIFO 1 as TREQ - 9 - - - PIO1_TX2 - Select PIO1's TX FIFO 2 as TREQ - 10 - - - PIO1_TX3 - Select PIO1's TX FIFO 3 as TREQ - 11 - - - PIO1_RX0 - Select PIO1's RX FIFO 0 as TREQ - 12 - - - PIO1_RX1 - Select PIO1's RX FIFO 1 as TREQ - 13 - - - PIO1_RX2 - Select PIO1's RX FIFO 2 as TREQ - 14 - - - PIO1_RX3 - Select PIO1's RX FIFO 3 as TREQ - 15 - - - SPI0_TX - Select SPI0's TX FIFO as TREQ - 16 - - - SPI0_RX - Select SPI0's RX FIFO as TREQ - 17 - - - SPI1_TX - Select SPI1's TX FIFO as TREQ - 18 - - - SPI1_RX - Select SPI1's RX FIFO as TREQ - 19 - - - UART0_TX - Select UART0's TX FIFO as TREQ - 20 - - - UART0_RX - Select UART0's RX FIFO as TREQ - 21 - - - UART1_TX - Select UART1's TX FIFO as TREQ - 22 - - - UART1_RX - Select UART1's RX FIFO as TREQ - 23 - - - PWM_WRAP0 - Select PWM Counter 0's Wrap Value as TREQ - 24 - - - PWM_WRAP1 - Select PWM Counter 1's Wrap Value as TREQ - 25 - - - PWM_WRAP2 - Select PWM Counter 2's Wrap Value as TREQ - 26 - - - PWM_WRAP3 - Select PWM Counter 3's Wrap Value as TREQ - 27 - - - PWM_WRAP4 - Select PWM Counter 4's Wrap Value as TREQ - 28 - - - PWM_WRAP5 - Select PWM Counter 5's Wrap Value as TREQ - 29 - - - PWM_WRAP6 - Select PWM Counter 6's Wrap Value as TREQ - 30 - - - PWM_WRAP7 - Select PWM Counter 7's Wrap Value as TREQ - 31 - - - I2C0_TX - Select I2C0's TX FIFO as TREQ - 32 - - - I2C0_RX - Select I2C0's RX FIFO as TREQ - 33 - - - I2C1_TX - Select I2C1's TX FIFO as TREQ - 34 - - - I2C1_RX - Select I2C1's RX FIFO as TREQ - 35 - - - ADC - Select the ADC as TREQ - 36 - - - XIP_STREAM - Select the XIP Streaming FIFO as TREQ - 37 - - - XIP_SSITX - Select the XIP SSI TX FIFO as TREQ - 38 - - - XIP_SSIRX - Select the XIP SSI RX FIFO as TREQ - 39 - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH_AL1_READ_ADDR - Alias for channel 0 READ_ADDR register - 0x14 - read-write - 0x00000000 - - - CH_AL1_WRITE_ADDR - Alias for channel 0 WRITE_ADDR register - 0x18 - read-write - 0x00000000 - - - CH_AL1_TRANS_COUNT_TRIG - Alias for channel 0 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x1C - read-write - 0x00000000 - - - CH_AL2_CTRL - DMA Channel 0 Control and Status - 0x20 - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - TREQ_SEL - - PIO0_TX0 - Select PIO0's TX FIFO 0 as TREQ - 0 - - - PIO0_TX1 - Select PIO0's TX FIFO 1 as TREQ - 1 - - - PIO0_TX2 - Select PIO0's TX FIFO 2 as TREQ - 2 - - - PIO0_TX3 - Select PIO0's TX FIFO 3 as TREQ - 3 - - - PIO0_RX0 - Select PIO0's RX FIFO 0 as TREQ - 4 - - - PIO0_RX1 - Select PIO0's RX FIFO 1 as TREQ - 5 - - - PIO0_RX2 - Select PIO0's RX FIFO 2 as TREQ - 6 - - - PIO0_RX3 - Select PIO0's RX FIFO 3 as TREQ - 7 - - - PIO1_TX0 - Select PIO1's TX FIFO 0 as TREQ - 8 - - - PIO1_TX1 - Select PIO1's TX FIFO 1 as TREQ - 9 - - - PIO1_TX2 - Select PIO1's TX FIFO 2 as TREQ - 10 - - - PIO1_TX3 - Select PIO1's TX FIFO 3 as TREQ - 11 - - - PIO1_RX0 - Select PIO1's RX FIFO 0 as TREQ - 12 - - - PIO1_RX1 - Select PIO1's RX FIFO 1 as TREQ - 13 - - - PIO1_RX2 - Select PIO1's RX FIFO 2 as TREQ - 14 - - - PIO1_RX3 - Select PIO1's RX FIFO 3 as TREQ - 15 - - - SPI0_TX - Select SPI0's TX FIFO as TREQ - 16 - - - SPI0_RX - Select SPI0's RX FIFO as TREQ - 17 - - - SPI1_TX - Select SPI1's TX FIFO as TREQ - 18 - - - SPI1_RX - Select SPI1's RX FIFO as TREQ - 19 - - - UART0_TX - Select UART0's TX FIFO as TREQ - 20 - - - UART0_RX - Select UART0's RX FIFO as TREQ - 21 - - - UART1_TX - Select UART1's TX FIFO as TREQ - 22 - - - UART1_RX - Select UART1's RX FIFO as TREQ - 23 - - - PWM_WRAP0 - Select PWM Counter 0's Wrap Value as TREQ - 24 - - - PWM_WRAP1 - Select PWM Counter 1's Wrap Value as TREQ - 25 - - - PWM_WRAP2 - Select PWM Counter 2's Wrap Value as TREQ - 26 - - - PWM_WRAP3 - Select PWM Counter 3's Wrap Value as TREQ - 27 - - - PWM_WRAP4 - Select PWM Counter 4's Wrap Value as TREQ - 28 - - - PWM_WRAP5 - Select PWM Counter 5's Wrap Value as TREQ - 29 - - - PWM_WRAP6 - Select PWM Counter 6's Wrap Value as TREQ - 30 - - - PWM_WRAP7 - Select PWM Counter 7's Wrap Value as TREQ - 31 - - - I2C0_TX - Select I2C0's TX FIFO as TREQ - 32 - - - I2C0_RX - Select I2C0's RX FIFO as TREQ - 33 - - - I2C1_TX - Select I2C1's TX FIFO as TREQ - 34 - - - I2C1_RX - Select I2C1's RX FIFO as TREQ - 35 - - - ADC - Select the ADC as TREQ - 36 - - - XIP_STREAM - Select the XIP Streaming FIFO as TREQ - 37 - - - XIP_SSITX - Select the XIP SSI TX FIFO as TREQ - 38 - - - XIP_SSIRX - Select the XIP SSI RX FIFO as TREQ - 39 - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH_AL2_TRANS_COUNT - Alias for channel 0 TRANS_COUNT register - 0x24 - read-write - 0x00000000 - - - CH_AL2_READ_ADDR - Alias for channel 0 READ_ADDR register - 0x28 - read-write - 0x00000000 - - - CH_AL2_WRITE_ADDR_TRIG - Alias for channel 0 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x2C - read-write - 0x00000000 - - - CH_AL3_CTRL - DMA Channel 0 Control and Status - 0x30 - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - TREQ_SEL - - PIO0_TX0 - Select PIO0's TX FIFO 0 as TREQ - 0 - - - PIO0_TX1 - Select PIO0's TX FIFO 1 as TREQ - 1 - - - PIO0_TX2 - Select PIO0's TX FIFO 2 as TREQ - 2 - - - PIO0_TX3 - Select PIO0's TX FIFO 3 as TREQ - 3 - - - PIO0_RX0 - Select PIO0's RX FIFO 0 as TREQ - 4 - - - PIO0_RX1 - Select PIO0's RX FIFO 1 as TREQ - 5 - - - PIO0_RX2 - Select PIO0's RX FIFO 2 as TREQ - 6 - - - PIO0_RX3 - Select PIO0's RX FIFO 3 as TREQ - 7 - - - PIO1_TX0 - Select PIO1's TX FIFO 0 as TREQ - 8 - - - PIO1_TX1 - Select PIO1's TX FIFO 1 as TREQ - 9 - - - PIO1_TX2 - Select PIO1's TX FIFO 2 as TREQ - 10 - - - PIO1_TX3 - Select PIO1's TX FIFO 3 as TREQ - 11 - - - PIO1_RX0 - Select PIO1's RX FIFO 0 as TREQ - 12 - - - PIO1_RX1 - Select PIO1's RX FIFO 1 as TREQ - 13 - - - PIO1_RX2 - Select PIO1's RX FIFO 2 as TREQ - 14 - - - PIO1_RX3 - Select PIO1's RX FIFO 3 as TREQ - 15 - - - SPI0_TX - Select SPI0's TX FIFO as TREQ - 16 - - - SPI0_RX - Select SPI0's RX FIFO as TREQ - 17 - - - SPI1_TX - Select SPI1's TX FIFO as TREQ - 18 - - - SPI1_RX - Select SPI1's RX FIFO as TREQ - 19 - - - UART0_TX - Select UART0's TX FIFO as TREQ - 20 - - - UART0_RX - Select UART0's RX FIFO as TREQ - 21 - - - UART1_TX - Select UART1's TX FIFO as TREQ - 22 - - - UART1_RX - Select UART1's RX FIFO as TREQ - 23 - - - PWM_WRAP0 - Select PWM Counter 0's Wrap Value as TREQ - 24 - - - PWM_WRAP1 - Select PWM Counter 1's Wrap Value as TREQ - 25 - - - PWM_WRAP2 - Select PWM Counter 2's Wrap Value as TREQ - 26 - - - PWM_WRAP3 - Select PWM Counter 3's Wrap Value as TREQ - 27 - - - PWM_WRAP4 - Select PWM Counter 4's Wrap Value as TREQ - 28 - - - PWM_WRAP5 - Select PWM Counter 5's Wrap Value as TREQ - 29 - - - PWM_WRAP6 - Select PWM Counter 6's Wrap Value as TREQ - 30 - - - PWM_WRAP7 - Select PWM Counter 7's Wrap Value as TREQ - 31 - - - I2C0_TX - Select I2C0's TX FIFO as TREQ - 32 - - - I2C0_RX - Select I2C0's RX FIFO as TREQ - 33 - - - I2C1_TX - Select I2C1's TX FIFO as TREQ - 34 - - - I2C1_RX - Select I2C1's RX FIFO as TREQ - 35 - - - ADC - Select the ADC as TREQ - 36 - - - XIP_STREAM - Select the XIP Streaming FIFO as TREQ - 37 - - - XIP_SSITX - Select the XIP SSI TX FIFO as TREQ - 38 - - - XIP_SSIRX - Select the XIP SSI RX FIFO as TREQ - 39 - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH_AL3_WRITE_ADDR - Alias for channel 0 WRITE_ADDR register - 0x34 - read-write - 0x00000000 - - - CH_AL3_TRANS_COUNT - Alias for channel 0 TRANS_COUNT register - 0x38 - read-write - 0x00000000 - - - CH_AL3_READ_ADDR_TRIG - Alias for channel 0 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x3C - read-write - 0x00000000 - - - - INTR - Interrupt Status (raw) - 0x400 - 0x00000000 - - - INTR - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n - Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n - This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n - It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. - [15:0] - read-write - oneToClear - - - - - INTE0 - Interrupt Enables for IRQ 0 - 0x404 - 0x00000000 - - - INTE0 - Set bit n to pass interrupts from channel n to DMA IRQ 0. - [15:0] - read-write - - - - - INTF0 - Force Interrupts - 0x408 - 0x00000000 - - - INTF0 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. - [15:0] - read-write - - - - - INTS0 - Interrupt Status for IRQ 0 - 0x40C - 0x00000000 - - - INTS0 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n - Channel interrupts can be cleared by writing a bit mask here. - [15:0] - read-write - oneToClear - - - - - INTE1 - Interrupt Enables for IRQ 1 - 0x414 - 0x00000000 - - - INTE1 - Set bit n to pass interrupts from channel n to DMA IRQ 1. - [15:0] - read-write - - - - - INTF1 - Force Interrupts for IRQ 1 - 0x418 - 0x00000000 - - - INTF1 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. - [15:0] - read-write - - - - - INTS1 - Interrupt Status (masked) for IRQ 1 - 0x41C - 0x00000000 - - - INTS1 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n - Channel interrupts can be cleared by writing a bit mask here. - [15:0] - read-write - oneToClear - - - - - TIMER0 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x420 - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER1 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x424 - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER2 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x428 - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER3 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x42C - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - MULTI_CHAN_TRIGGER - Trigger one or more channels simultaneously - 0x430 - 0x00000000 - - - MULTI_CHAN_TRIGGER - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. - [15:0] - read-write - clear - - - - - SNIFF_CTRL - Sniffer Control - 0x434 - 0x00000000 - - - OUT_INV - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. - [11:11] - read-write - - - OUT_REV - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. - [10:10] - read-write - - - BSWAP - Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n - Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. - [9:9] - read-write - - - CALC - [8:5] - read-write - - - CRC32 - Calculate a CRC-32 (IEEE802.3 polynomial) - 0 - - - CRC32R - Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data - 1 - - - CRC16 - Calculate a CRC-16-CCITT - 2 - - - CRC16R - Calculate a CRC-16-CCITT with bit reversed data - 3 - - - EVEN - XOR reduction over all data. == 1 if the total 1 population count is odd. - 14 - - - SUM - Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) - 15 - - - - - DMACH - DMA channel for Sniffer to observe - [4:1] - read-write - - - EN - Enable sniffer - [0:0] - read-write - - - - - SNIFF_DATA - Data accumulator for sniff hardware\n - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. - 0x438 - read-write - 0x00000000 - - - FIFO_LEVELS - Debug RAF, WAF, TDF levels - 0x440 - 0x00000000 - - - RAF_LVL - Current Read-Address-FIFO fill level - [23:16] - read-only - - - WAF_LVL - Current Write-Address-FIFO fill level - [15:8] - read-only - - - TDF_LVL - Current Transfer-Data-FIFO fill level - [7:0] - read-only - - - - - CHAN_ABORT - Abort an in-progress transfer sequence on one or more channels - 0x444 - 0x00000000 - - - CHAN_ABORT - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n - After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. - [15:0] - read-write - clear - - - - - N_CHANNELS - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. - 0x448 - 0x00000000 - - - N_CHANNELS - [4:0] - read-only - - - - - CH0_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x800 - 0x00000000 - - - CH0_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH0_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x804 - read-only - 0x00000000 - - - CH1_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x840 - 0x00000000 - - - CH1_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH1_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x844 - read-only - 0x00000000 - - - CH2_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x880 - 0x00000000 - - - CH2_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH2_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x884 - read-only - 0x00000000 - - - CH3_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x8C0 - 0x00000000 - - - CH3_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH3_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x8C4 - read-only - 0x00000000 - - - CH4_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x900 - 0x00000000 - - - CH4_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH4_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x904 - read-only - 0x00000000 - - - CH5_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x940 - 0x00000000 - - - CH5_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH5_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x944 - read-only - 0x00000000 - - - CH6_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x980 - 0x00000000 - - - CH6_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH6_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x984 - read-only - 0x00000000 - - - CH7_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x9C0 - 0x00000000 - - - CH7_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH7_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x9C4 - read-only - 0x00000000 - - - CH8_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xA00 - 0x00000000 - - - CH8_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH8_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xA04 - read-only - 0x00000000 - - - CH9_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xA40 - 0x00000000 - - - CH9_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH9_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xA44 - read-only - 0x00000000 - - - CH10_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xA80 - 0x00000000 - - - CH10_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH10_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xA84 - read-only - 0x00000000 - - - CH11_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xAC0 - 0x00000000 - - - CH11_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH11_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xAC4 - read-only - 0x00000000 - - - - - USBCTRL_DPRAM - 1 - DPRAM layout for USB device. - 0x50100000 - 0x20 - - 0x0 - 0x100 - registers - - - - SETUP_PACKET_LOW - Bytes 0-3 of the SETUP packet from the host. - 0x0 - 0x00000000 - - - WVALUE - [31:16] - read-write - - - BREQUEST - [15:8] - read-write - - - BMREQUESTTYPE - [7:0] - read-write - - - - - SETUP_PACKET_HIGH - Bytes 4-7 of the setup packet from the host. - 0x4 - 0x00000000 - - - WLENGTH - [31:16] - read-write - - - WINDEX - [15:0] - read-write - - - - - 30 - 0x4 - 0-29 - EP_CONTROL%s - - - 0x8 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - HOST_POLL_INTERVAL - The interval the host controller should poll this endpoint. Only applicable for interrupt endpoints. Specified in ms - 1. For example: a value of 9 would poll the endpoint every 10ms. - 16 - 10 - - - - - 32 - 0x4 - 0-31 - EP_BUFFER_CONTROL%s - - - 0x80 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EPX_CONTROL - EPx Control (Host-mode only!) - 0x100 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - - - USBCTRL_REGS - 1 - USB FS/LS controller device registers - 0x50110000 - 0x20 - - 0x0 - 0x1000 - registers - - - USBCTRL_IRQ - 5 - - - - ADDR_ENDP - Device address and endpoint control - 0x0 - 0x00000000 - - - ENDPOINT - Device endpoint to send data to. Only valid for HOST mode. - [19:16] - read-write - - - ADDRESS - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. - [6:0] - read-write - - - - - 15 - 0x4 - 1-15 - HOST_ADDR_ENDP%s - Interrupt endpoints. Only valid in HOST mode. - 0x4 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - MAIN_CTRL - Main control register - 0x40 - 0x00000000 - - - SIM_TIMING - Reduced timings for simulation - [31:31] - read-write - - - HOST_NDEVICE - Device mode = 0, Host mode = 1 - [1:1] - read-write - - - CONTROLLER_EN - Enable controller - [0:0] - read-write - - - - - SOF_WR - Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. - 0x44 - 0x00000000 - - - COUNT - [10:0] - write-only - - - - - SOF_RD - Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. - 0x48 - 0x00000000 - - - COUNT - [10:0] - read-only - - - - - SIE_CTRL - SIE control register - 0x4C - 0x00000000 - - - EP0_INT_STALL - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL - [31:31] - read-write - - - EP0_DOUBLE_BUF - Device: EP0 single buffered = 0, double buffered = 1 - [30:30] - read-write - - - EP0_INT_1BUF - Device: Set bit in BUFF_STATUS for every buffer completed on EP0 - [29:29] - read-write - - - EP0_INT_2BUF - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 - [28:28] - read-write - - - EP0_INT_NAK - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK - [27:27] - read-write - - - DIRECT_EN - Direct bus drive enable - [26:26] - read-write - - - DIRECT_DP - Direct control of DP - [25:25] - read-write - - - DIRECT_DM - Direct control of DM - [24:24] - read-write - - - TRANSCEIVER_PD - Power down bus transceiver - [18:18] - read-write - - - RPU_OPT - Device: Pull-up strength (0=1K2, 1=2k3) - [17:17] - read-write - - - PULLUP_EN - Device: Enable pull up resistor - [16:16] - read-write - - - PULLDOWN_EN - Host: Enable pull down resistors - [15:15] - read-write - - - RESET_BUS - Host: Reset bus - [13:13] - read-write - clear - - - RESUME - Device: Remote wakeup. Device can initiate its own resume after suspend. - [12:12] - read-write - clear - - - VBUS_EN - Host: Enable VBUS - [11:11] - read-write - - - KEEP_ALIVE_EN - Host: Enable keep alive packet (for low speed bus) - [10:10] - read-write - - - SOF_EN - Host: Enable SOF generation (for full speed bus) - [9:9] - read-write - - - SOF_SYNC - Host: Delay packet(s) until after SOF - [8:8] - read-write - - - PREAMBLE_EN - Host: Preable enable for LS device on FS hub - [6:6] - read-write - - - STOP_TRANS - Host: Stop transaction - [4:4] - read-write - clear - - - RECEIVE_DATA - Host: Receive transaction (IN to host) - [3:3] - read-write - - - SEND_DATA - Host: Send transaction (OUT from host) - [2:2] - read-write - - - SEND_SETUP - Host: Send Setup packet - [1:1] - read-write - - - START_TRANS - Host: Start transaction - [0:0] - read-write - clear - - - - - SIE_STATUS - SIE status register - 0x50 - 0x00000000 - - - DATA_SEQ_ERROR - Data Sequence Error.\n\n - The device can raise a sequence error in the following conditions:\n\n - * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n - The host can raise a data sequence error in the following conditions:\n\n - * An IN packet from the device has the wrong data PID - [31:31] - read-write - oneToClear - - - ACK_REC - ACK received. Raised by both host and device. - [30:30] - read-write - oneToClear - - - STALL_REC - Host: STALL received - [29:29] - read-write - oneToClear - - - NAK_REC - Host: NAK received - [28:28] - read-write - oneToClear - - - RX_TIMEOUT - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. - [27:27] - read-write - oneToClear - - - RX_OVERFLOW - RX overflow is raised by the Serial RX engine if the incoming data is too fast. - [26:26] - read-write - oneToClear - - - BIT_STUFF_ERROR - Bit Stuff Error. Raised by the Serial RX engine. - [25:25] - read-write - oneToClear - - - CRC_ERROR - CRC Error. Raised by the Serial RX engine. - [24:24] - read-write - oneToClear - - - BUS_RESET - Device: bus reset received - [19:19] - read-write - oneToClear - - - TRANS_COMPLETE - Transaction complete.\n\n - Raised by device if:\n\n - * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\n\n - Raised by host if:\n\n - * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set - [18:18] - read-write - oneToClear - - - SETUP_REC - Device: Setup packet received - [17:17] - read-write - oneToClear - - - CONNECTED - Device: connected - [16:16] - read-write - oneToClear - - - RESUME - Host: Device has initiated a remote resume. Device: host has initiated a resume. - [11:11] - read-write - oneToClear - - - VBUS_OVER_CURR - VBUS over current detected - [10:10] - read-only - - - SPEED - Host: device speed. Disconnected = 00, LS = 01, FS = 10 - [9:8] - read-write - oneToClear - - - SUSPENDED - Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. - [4:4] - read-write - oneToClear - - - LINE_STATE - USB bus line state - [3:2] - read-only - - LINE_STATE - - SE0 - SE0 - 0 - - - J - J - 1 - - - K - K - 2 - - - SE1 - SE1 - 3 - - - - - VBUS_DETECTED - Device: VBUS Detected - [0:0] - read-only - - - - - INT_EP_CTRL - interrupt endpoint control register - 0x54 - 0x00000000 - - - INT_EP_ACTIVE - Host: Enable interrupt endpoint 1 -> 15 - [15:1] - read-write - - - - - BUFF_STATUS - Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. - 0x58 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - BUFF_CPU_SHOULD_HANDLE - Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. - 0x5C - 0x00000000 - - - EP15_OUT - [31:31] - read-only - - - EP15_IN - [30:30] - read-only - - - EP14_OUT - [29:29] - read-only - - - EP14_IN - [28:28] - read-only - - - EP13_OUT - [27:27] - read-only - - - EP13_IN - [26:26] - read-only - - - EP12_OUT - [25:25] - read-only - - - EP12_IN - [24:24] - read-only - - - EP11_OUT - [23:23] - read-only - - - EP11_IN - [22:22] - read-only - - - EP10_OUT - [21:21] - read-only - - - EP10_IN - [20:20] - read-only - - - EP9_OUT - [19:19] - read-only - - - EP9_IN - [18:18] - read-only - - - EP8_OUT - [17:17] - read-only - - - EP8_IN - [16:16] - read-only - - - EP7_OUT - [15:15] - read-only - - - EP7_IN - [14:14] - read-only - - - EP6_OUT - [13:13] - read-only - - - EP6_IN - [12:12] - read-only - - - EP5_OUT - [11:11] - read-only - - - EP5_IN - [10:10] - read-only - - - EP4_OUT - [9:9] - read-only - - - EP4_IN - [8:8] - read-only - - - EP3_OUT - [7:7] - read-only - - - EP3_IN - [6:6] - read-only - - - EP2_OUT - [5:5] - read-only - - - EP2_IN - [4:4] - read-only - - - EP1_OUT - [3:3] - read-only - - - EP1_IN - [2:2] - read-only - - - EP0_OUT - [1:1] - read-only - - - EP0_IN - [0:0] - read-only - - - - - EP_ABORT - Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. - 0x60 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - - - EP15_IN - [30:30] - read-write - - - EP14_OUT - [29:29] - read-write - - - EP14_IN - [28:28] - read-write - - - EP13_OUT - [27:27] - read-write - - - EP13_IN - [26:26] - read-write - - - EP12_OUT - [25:25] - read-write - - - EP12_IN - [24:24] - read-write - - - EP11_OUT - [23:23] - read-write - - - EP11_IN - [22:22] - read-write - - - EP10_OUT - [21:21] - read-write - - - EP10_IN - [20:20] - read-write - - - EP9_OUT - [19:19] - read-write - - - EP9_IN - [18:18] - read-write - - - EP8_OUT - [17:17] - read-write - - - EP8_IN - [16:16] - read-write - - - EP7_OUT - [15:15] - read-write - - - EP7_IN - [14:14] - read-write - - - EP6_OUT - [13:13] - read-write - - - EP6_IN - [12:12] - read-write - - - EP5_OUT - [11:11] - read-write - - - EP5_IN - [10:10] - read-write - - - EP4_OUT - [9:9] - read-write - - - EP4_IN - [8:8] - read-write - - - EP3_OUT - [7:7] - read-write - - - EP3_IN - [6:6] - read-write - - - EP2_OUT - [5:5] - read-write - - - EP2_IN - [4:4] - read-write - - - EP1_OUT - [3:3] - read-write - - - EP1_IN - [2:2] - read-write - - - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] - read-write - - - - - EP_ABORT_DONE - Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. - 0x64 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - EP_STALL_ARM - Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. - 0x68 - 0x00000000 - - - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] - read-write - - - - - NAK_POLL - Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. - 0x6C - 0x00100010 - - - DELAY_FS - NAK polling interval for a full speed device - [25:16] - read-write - - - DELAY_LS - NAK polling interval for a low speed device - [9:0] - read-write - - - - - EP_STATUS_STALL_NAK - Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. - 0x70 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - USB_MUXING - Where to connect the USB controller. Should be to_phy by default. - 0x74 - 0x00000000 - - - SOFTCON - [3:3] - read-write - - - TO_DIGITAL_PAD - [2:2] - read-write - - - TO_EXTPHY - [1:1] - read-write - - - TO_PHY - [0:0] - read-write - - - - - USB_PWR - Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. - 0x78 - 0x00000000 - - - OVERCURR_DETECT_EN - [5:5] - read-write - - - OVERCURR_DETECT - [4:4] - read-write - - - VBUS_DETECT_OVERRIDE_EN - [3:3] - read-write - - - VBUS_DETECT - [2:2] - read-write - - - VBUS_EN_OVERRIDE_EN - [1:1] - read-write - - - VBUS_EN - [0:0] - read-write - - - - - USBPHY_DIRECT - This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. - 0x7C - 0x00000000 - - - DM_OVV - DM over voltage - [22:22] - read-only - - - DP_OVV - DP over voltage - [21:21] - read-only - - - DM_OVCN - DM overcurrent - [20:20] - read-only - - - DP_OVCN - DP overcurrent - [19:19] - read-only - - - RX_DM - DPM pin state - [18:18] - read-only - - - RX_DP - DPP pin state - [17:17] - read-only - - - RX_DD - Differential RX - [16:16] - read-only - - - TX_DIFFMODE - TX_DIFFMODE=0: Single ended mode\n - TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) - [15:15] - read-write - - - TX_FSSLEW - TX_FSSLEW=0: Low speed slew rate\n - TX_FSSLEW=1: Full speed slew rate - [14:14] - read-write - - - TX_PD - TX power down override (if override enable is set). 1 = powered down. - [13:13] - read-write - - - RX_PD - RX power down override (if override enable is set). 1 = powered down. - [12:12] - read-write - - - TX_DM - Output data. TX_DIFFMODE=1, Ignored\n - TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM - [11:11] - read-write - - - TX_DP - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n - If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP - [10:10] - read-write - - - TX_DM_OE - Output enable. If TX_DIFFMODE=1, Ignored.\n - If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving - [9:9] - read-write - - - TX_DP_OE - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n - If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving - [8:8] - read-write - - - DM_PULLDN_EN - DM pull down enable - [6:6] - read-write - - - DM_PULLUP_EN - DM pull up enable - [5:5] - read-write - - - DM_PULLUP_HISEL - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [4:4] - read-write - - - DP_PULLDN_EN - DP pull down enable - [2:2] - read-write - - - DP_PULLUP_EN - DP pull up enable - [1:1] - read-write - - - DP_PULLUP_HISEL - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [0:0] - read-write - - - - - USBPHY_DIRECT_OVERRIDE - Override enable for each control in usbphy_direct - 0x80 - 0x00000000 - - - TX_DIFFMODE_OVERRIDE_EN - [15:15] - read-write - - - DM_PULLUP_OVERRIDE_EN - [12:12] - read-write - - - TX_FSSLEW_OVERRIDE_EN - [11:11] - read-write - - - TX_PD_OVERRIDE_EN - [10:10] - read-write - - - RX_PD_OVERRIDE_EN - [9:9] - read-write - - - TX_DM_OVERRIDE_EN - [8:8] - read-write - - - TX_DP_OVERRIDE_EN - [7:7] - read-write - - - TX_DM_OE_OVERRIDE_EN - [6:6] - read-write - - - TX_DP_OE_OVERRIDE_EN - [5:5] - read-write - - - DM_PULLDN_EN_OVERRIDE_EN - [4:4] - read-write - - - DP_PULLDN_EN_OVERRIDE_EN - [3:3] - read-write - - - DP_PULLUP_EN_OVERRIDE_EN - [2:2] - read-write - - - DM_PULLUP_HISEL_OVERRIDE_EN - [1:1] - read-write - - - DP_PULLUP_HISEL_OVERRIDE_EN - [0:0] - read-write - - - - - USBPHY_TRIM - Used to adjust trim values of USB phy pull down resistors. - 0x84 - 0x00001F1F - - - DM_PULLDN_TRIM - Value to drive to USB PHY\n - DM pulldown resistor trim control\n - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [12:8] - read-write - - - DP_PULLDN_TRIM - Value to drive to USB PHY\n - DP pulldown resistor trim control\n - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [4:0] - read-write - - - - - INTR - Raw Interrupts - 0x8C - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-only - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x90 - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-write - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-write - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-write - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-write - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-write - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-write - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-write - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-write - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-write - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-write - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-write - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-write - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-write - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-write - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-write - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-write - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-write - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-write - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x94 - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-write - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-write - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-write - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-write - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-write - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-write - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-write - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-write - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-write - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-write - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-write - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-write - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-write - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-write - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-write - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-write - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-write - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-write - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x98 - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-only - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only - - - - - - - PIO0 - 1 - Programmable IO block - 0x50200000 - 0x20 - - 0x0 - 0x1000 - registers - - - PIO0_IRQ_0 - 7 - - - PIO0_IRQ_1 - 8 - - - - CTRL - PIO control register - 0x0 - 0x00000000 - - - CLKDIV_RESTART - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n - Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n - Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. - [11:8] - read-write - clear - - - SM_RESTART - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n - Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.\n\n - The program counter, the contents of the output shift register and the X/Y scratch registers are not affected. - [7:4] - read-write - clear - - - SM_ENABLE - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. - [3:0] - read-write - - - - - FSTAT - FIFO status register - 0x4 - 0x0F000F00 - - - TXEMPTY - State machine TX FIFO is empty - [27:24] - read-only - - - TXFULL - State machine TX FIFO is full - [19:16] - read-only - - - RXEMPTY - State machine RX FIFO is empty - [11:8] - read-only - - - RXFULL - State machine RX FIFO is full - [3:0] - read-only - - - - - FDEBUG - FIFO debug register - 0x8 - 0x00000000 - - - TXSTALL - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. - [27:24] - read-write - oneToClear - - - TXOVER - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. - [19:16] - read-write - oneToClear - - - RXUNDER - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. - [11:8] - read-write - oneToClear - - - RXSTALL - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. - [3:0] - read-write - oneToClear - - - - - FLEVEL - FIFO levels - 0xC - 0x00000000 - - - RX3 - [31:28] - read-only - - - TX3 - [27:24] - read-only - - - RX2 - [23:20] - read-only - - - TX2 - [19:16] - read-only - - - RX1 - [15:12] - read-only - - - TX1 - [11:8] - read-only - - - RX0 - [7:4] - read-only - - - TX0 - [3:0] - read-only - - - - - 4 - 0x4 - 0-3 - TXF%s - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x10 - write-only - 0x00000000 - - - 4 - 0x4 - 0-3 - RXF%s - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x20 - read-only - 0x00000000 - - - IRQ - State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n - Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. - 0x30 - 0x00000000 - - - IRQ - [7:0] - read-write - oneToClear - - - - - IRQ_FORCE - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. - 0x34 - 0x00000000 - - - IRQ_FORCE - [7:0] - write-only - - - - - INPUT_SYNC_BYPASS - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n - 0 -> input is synchronized (default)\n - 1 -> synchronizer is bypassed\n - If in doubt, leave this register as all zeroes. - 0x38 - read-write - 0x00000000 - - - DBG_PADOUT - Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x3C - read-only - 0x00000000 - - - DBG_PADOE - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x40 - read-only - 0x00000000 - - - DBG_CFGINFO - The PIO hardware has some free parameters that may vary between chip products.\n - These should be provided in the chip datasheet, but are also exposed here. - 0x44 - 0x00000000 - - - IMEM_SIZE - The size of the instruction memory, measured in units of one instruction - [21:16] - read-only - - - SM_COUNT - The number of state machines this PIO instance is equipped with. - [11:8] - read-only - - - FIFO_DEPTH - The depth of the state machine TX/RX FIFOs, measured in words.\n - Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n - this depth. - [5:0] - read-only - - - - - 32 - 0x4 - 0-31 - INSTR_MEM%s - Write-only access to instruction memory location %s - 0x48 - 0x00000000 - - - INSTR_MEM0 - [15:0] - write-only - - - - - 4 - 0x18 - 0-3 - SM%s - Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL - 0xC8 - - SM_CLKDIV - Clock divisor register for state machine 0\n - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x0 - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256).\n - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM_EXECCTRL - Execution/behavioural settings for state machine 0 - 0x4 - 0x0001F000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable\n - When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n - deassert the latest pin write. This can create useful masking/override behaviour\n - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom.\n - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [4:4] - read-write - - - TXLEVEL - All-ones if TX FIFO level < N, otherwise all-zeroes - 0 - - - RXLEVEL - All-ones if RX FIFO level < N, otherwise all-zeroes - 1 - - - - - STATUS_N - Comparison level for the MOV x, STATUS instruction - [3:0] - read-write - - - - - SM_SHIFTCTRL - Control behaviour of the input/output shift registers for state machine 0 - 0x8 - 0x000C0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n - TX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n - RX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - - - SM_ADDR - Current instruction address of state machine 0 - 0xC - 0x00000000 - - - SM0_ADDR - [4:0] - read-only - - - - - SM_INSTR - Read to see the instruction currently addressed by state machine 0's program counter\n - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x10 - 0x00000000 - - - SM0_INSTR - [15:0] - read-write - - - - - SM_PINCTRL - State machine pin control - 0x14 - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - - INTR - Raw Interrupts - 0x128 - 0x00000000 - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - 2 - 0xC - 0-1 - SM_IRQ%s - Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS - 0x12C - - IRQ_INTE - Interrupt Enable for irq0 - 0x0 - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ_INTF - Interrupt Force for irq0 - 0x4 - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ_INTS - Interrupt status after masking & forcing for irq0 - 0x8 - 0x00000000 - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - - - - PIO1 - 0x50300000 - - PIO1_IRQ_0 - 9 - - - PIO1_IRQ_1 - 10 - - - - SIO - 1 - Single-cycle IO block\n - Provides core-local and inter-core hardware for the two processors, with single-cycle access. - 0xD0000000 - 0x20 - - 0x0 - 0x200 - registers - - - SIO_IRQ_PROC0 - 15 - - - SIO_IRQ_PROC1 - 16 - - - - CPUID - Processor core identifier\n - Value is 0 when read from processor core 0, and 1 when read from processor core 1. - 0x0 - read-only - 0x00000000 - - - GPIO_IN - Input value for GPIO pins - 0x4 - 0x00000000 - - - GPIO_IN - Input value for GPIO0...29 - [29:0] - read-only - - - - - GPIO_HI_IN - Input value for QSPI pins - 0x8 - 0x00000000 - - - GPIO_HI_IN - Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 - [5:0] - read-only - - - - - GPIO_OUT - GPIO output value - 0x10 - 0x00000000 - - - GPIO_OUT - Set output level (1/0 -> high/low) for GPIO0...29.\n - Reading back gives the last value written, NOT the input value from the pins.\n - If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [29:0] - read-write - - - - - GPIO_OUT_SET - GPIO output value set - 0x14 - 0x00000000 - - - GPIO_OUT_SET - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` - [29:0] - write-only - - - - - GPIO_OUT_CLR - GPIO output value clear - 0x18 - 0x00000000 - - - GPIO_OUT_CLR - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` - [29:0] - write-only - - - - - GPIO_OUT_XOR - GPIO output value XOR - 0x1C - 0x00000000 - - - GPIO_OUT_XOR - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` - [29:0] - write-only - - - - - GPIO_OE - GPIO output enable - 0x20 - 0x00000000 - - - GPIO_OE - Set output enable (1/0 -> output/input) for GPIO0...29.\n - Reading back gives the last value written.\n - If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [29:0] - read-write - - - - - GPIO_OE_SET - GPIO output enable set - 0x24 - 0x00000000 - - - GPIO_OE_SET - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` - [29:0] - write-only - - - - - GPIO_OE_CLR - GPIO output enable clear - 0x28 - 0x00000000 - - - GPIO_OE_CLR - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` - [29:0] - write-only - - - - - GPIO_OE_XOR - GPIO output enable XOR - 0x2C - 0x00000000 - - - GPIO_OE_XOR - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` - [29:0] - write-only - - - - - GPIO_HI_OUT - QSPI output value - 0x30 - 0x00000000 - - - GPIO_HI_OUT - Set output level (1/0 -> high/low) for QSPI IO0...5.\n - Reading back gives the last value written, NOT the input value from the pins.\n - If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [5:0] - read-write - - - - - GPIO_HI_OUT_SET - QSPI output value set - 0x34 - 0x00000000 - - - GPIO_HI_OUT_SET - Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` - [5:0] - write-only - - - - - GPIO_HI_OUT_CLR - QSPI output value clear - 0x38 - 0x00000000 - - - GPIO_HI_OUT_CLR - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` - [5:0] - write-only - - - - - GPIO_HI_OUT_XOR - QSPI output value XOR - 0x3C - 0x00000000 - - - GPIO_HI_OUT_XOR - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` - [5:0] - write-only - - - - - GPIO_HI_OE - QSPI output enable - 0x40 - 0x00000000 - - - GPIO_HI_OE - Set output enable (1/0 -> output/input) for QSPI IO0...5.\n - Reading back gives the last value written.\n - If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [5:0] - read-write - - - - - GPIO_HI_OE_SET - QSPI output enable set - 0x44 - 0x00000000 - - - GPIO_HI_OE_SET - Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` - [5:0] - write-only - - - - - GPIO_HI_OE_CLR - QSPI output enable clear - 0x48 - 0x00000000 - - - GPIO_HI_OE_CLR - Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` - [5:0] - write-only - - - - - GPIO_HI_OE_XOR - QSPI output enable XOR - 0x4C - 0x00000000 - - - GPIO_HI_OE_XOR - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` - [5:0] - write-only - - - - - FIFO_ST - Status register for inter-core FIFOs (mailboxes).\n - There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\n - Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\n - Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\n - The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. - 0x50 - 0x00000002 - - - ROE - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. - [3:3] - read-write - oneToClear - - - WOF - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. - [2:2] - read-write - oneToClear - - - RDY - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) - [1:1] - read-only - - - VLD - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) - [0:0] - read-only - - - - - FIFO_WR - Write access to this core's TX FIFO - 0x54 - write-only - 0x00000000 - - - FIFO_RD - Read access to this core's RX FIFO - 0x58 - read-only - 0x00000000 - - - SPINLOCK_ST - Spinlock state\n - A bitmap containing the state of all 32 spinlocks (1=locked).\n - Mainly intended for debugging. - 0x5C - read-only - 0x00000000 - - - DIV_UDIVIDEND - Divider unsigned dividend\n - Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n - UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n - unsigned calculation, and the S alias starts a signed calculation. - 0x60 - read-write - 0x00000000 - - - DIV_UDIVISOR - Divider unsigned divisor\n - Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n - UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an\n - unsigned calculation, and the S alias starts a signed calculation. - 0x64 - read-write - 0x00000000 - - - DIV_SDIVIDEND - Divider signed dividend\n - The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. - 0x68 - read-write - 0x00000000 - - - DIV_SDIVISOR - Divider signed divisor\n - The same as UDIVISOR, but starts a signed calculation, rather than unsigned. - 0x6C - read-write - 0x00000000 - - - DIV_QUOTIENT - Divider result quotient\n - The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.\n - For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n - This register can be written to directly, for context save/restore purposes. This halts any\n - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n - Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n - REMAINDER, QUOTIENT if CSR_DIRTY is used. - 0x70 - read-write - 0x00000000 - - - DIV_REMAINDER - Divider result remainder\n - The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.\n - For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n - This register can be written to directly, for context save/restore purposes. This halts any\n - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. - 0x74 - read-write - 0x00000000 - - - DIV_CSR - Control and status register for divider. - 0x78 - 0x00000001 - - - DIRTY - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n - Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n - If the flag is used in this way, it's recommended to either read QUOTIENT only,\n - or REMAINDER and then QUOTIENT, to prevent data loss on context switch. - [1:1] - read-only - - - READY - Reads as 0 when a calculation is in progress, 1 otherwise.\n - Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\n - matter if one is already in progress.\n - Writing to a result register will immediately terminate any in-progress calculation\n - and set the READY and DIRTY flags. - [0:0] - read-only - - - - - INTERP0_ACCUM0 - Read/write access to accumulator 0 - 0x80 - read-write - 0x00000000 - - - INTERP0_ACCUM1 - Read/write access to accumulator 1 - 0x84 - read-write - 0x00000000 - - - INTERP0_BASE0 - Read/write access to BASE0 register. - 0x88 - read-write - 0x00000000 - - - INTERP0_BASE1 - Read/write access to BASE1 register. - 0x8C - read-write - 0x00000000 - - - INTERP0_BASE2 - Read/write access to BASE2 register. - 0x90 - read-write - 0x00000000 - - - INTERP0_POP_LANE0 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0x94 - read-only - 0x00000000 - - - INTERP0_POP_LANE1 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0x98 - read-only - 0x00000000 - - - INTERP0_POP_FULL - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0x9C - read-only - 0x00000000 - - - INTERP0_PEEK_LANE0 - Read LANE0 result, without altering any internal state (PEEK). - 0xA0 - read-only - 0x00000000 - - - INTERP0_PEEK_LANE1 - Read LANE1 result, without altering any internal state (PEEK). - 0xA4 - read-only - 0x00000000 - - - INTERP0_PEEK_FULL - Read FULL result, without altering any internal state (PEEK). - 0xA8 - read-only - 0x00000000 - - - INTERP0_CTRL_LANE0 - Control register for lane 0 - 0xAC - 0x00000000 - - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only - - - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only - - - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only - - - BLEND - Only present on INTERP0 on each core. If BLEND mode is enabled:\n - - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n - by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n - 0 and 255/256ths)\n - - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n - - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n - LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. - [21:21] - read-write - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP0_CTRL_LANE1 - Control register for lane 1 - 0xB0 - 0x00000000 - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP0_ACCUM0_ADD - Values written here are atomically added to ACCUM0\n - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0xB4 - 0x00000000 - - - INTERP0_ACCUM0_ADD - [23:0] - read-write - - - - - INTERP0_ACCUM1_ADD - Values written here are atomically added to ACCUM1\n - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0xB8 - 0x00000000 - - - INTERP0_ACCUM1_ADD - [23:0] - read-write - - - - - INTERP0_BASE_1AND0 - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0xBC - write-only - 0x00000000 - - - INTERP1_ACCUM0 - Read/write access to accumulator 0 - 0xC0 - read-write - 0x00000000 - - - INTERP1_ACCUM1 - Read/write access to accumulator 1 - 0xC4 - read-write - 0x00000000 - - - INTERP1_BASE0 - Read/write access to BASE0 register. - 0xC8 - read-write - 0x00000000 - - - INTERP1_BASE1 - Read/write access to BASE1 register. - 0xCC - read-write - 0x00000000 - - - INTERP1_BASE2 - Read/write access to BASE2 register. - 0xD0 - read-write - 0x00000000 - - - INTERP1_POP_LANE0 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0xD4 - read-only - 0x00000000 - - - INTERP1_POP_LANE1 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0xD8 - read-only - 0x00000000 - - - INTERP1_POP_FULL - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0xDC - read-only - 0x00000000 - - - INTERP1_PEEK_LANE0 - Read LANE0 result, without altering any internal state (PEEK). - 0xE0 - read-only - 0x00000000 - - - INTERP1_PEEK_LANE1 - Read LANE1 result, without altering any internal state (PEEK). - 0xE4 - read-only - 0x00000000 - - - INTERP1_PEEK_FULL - Read FULL result, without altering any internal state (PEEK). - 0xE8 - read-only - 0x00000000 - - - INTERP1_CTRL_LANE0 - Control register for lane 0 - 0xEC - 0x00000000 - - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only - - - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only - - - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only - - - CLAMP - Only present on INTERP1 on each core. If CLAMP mode is enabled:\n - - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n - BASE0 and an upper bound of BASE1.\n - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED - [22:22] - read-write - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP1_CTRL_LANE1 - Control register for lane 1 - 0xF0 - 0x00000000 - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP1_ACCUM0_ADD - Values written here are atomically added to ACCUM0\n - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0xF4 - 0x00000000 - - - INTERP1_ACCUM0_ADD - [23:0] - read-write - - - - - INTERP1_ACCUM1_ADD - Values written here are atomically added to ACCUM1\n - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0xF8 - 0x00000000 - - - INTERP1_ACCUM1_ADD - [23:0] - read-write - - - - - INTERP1_BASE_1AND0 - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0xFC - write-only - 0x00000000 - - - 32 - 0x4 - 0-31 - SPINLOCK%s - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x100 - read-write - 0x00000000 - - - - - PPB - 1 - 0xE0000000 - 0x20 - - 0x0 - 0x10000 - registers - - - - SYST_CSR - Use the SysTick Control and Status Register to enable the SysTick features. - 0xE010 - 0x00000000 - - - COUNTFLAG - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. - [16:16] - read-only - - - CLKSOURCE - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n - Selects the SysTick timer clock source:\n - 0 = External reference clock.\n - 1 = Processor clock. - [2:2] - read-write - - - TICKINT - Enables SysTick exception request:\n - 0 = Counting down to zero does not assert the SysTick exception request.\n - 1 = Counting down to zero to asserts the SysTick exception request. - [1:1] - read-write - - - ENABLE - Enable SysTick counter:\n - 0 = Counter disabled.\n - 1 = Counter enabled. - [0:0] - read-write - - - - - SYST_RVR - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n - To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. - 0xE014 - 0x00000000 - - - RELOAD - Value to load into the SysTick Current Value Register when the counter reaches 0. - [23:0] - read-write - - - - - SYST_CVR - Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. - 0xE018 - 0x00000000 - - - CURRENT - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. - [23:0] - read-write - - - - - SYST_CALIB - Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. - 0xE01C - 0x00000000 - - - NOREF - If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. - [31:31] - read-only - - - SKEW - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). - [30:30] - read-only - - - TENMS - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. - [23:0] - read-only - - - - - NVIC_ISER - Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n - If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. - 0xE100 - 0x00000000 - - - SETENA - Interrupt set-enable bits.\n - Write:\n - 0 = No effect.\n - 1 = Enable interrupt.\n - Read:\n - 0 = Interrupt disabled.\n - 1 = Interrupt enabled. - [31:0] - read-write - - - - - NVIC_ICER - Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. - 0xE180 - 0x00000000 - - - CLRENA - Interrupt clear-enable bits.\n - Write:\n - 0 = No effect.\n - 1 = Disable interrupt.\n - Read:\n - 0 = Interrupt disabled.\n - 1 = Interrupt enabled. - [31:0] - read-write - - - - - NVIC_ISPR - The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. - 0xE200 - 0x00000000 - - - SETPEND - Interrupt set-pending bits.\n - Write:\n - 0 = No effect.\n - 1 = Changes interrupt state to pending.\n - Read:\n - 0 = Interrupt is not pending.\n - 1 = Interrupt is pending.\n - Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n - An interrupt that is pending has no effect.\n - A disabled interrupt sets the state of that interrupt to pending. - [31:0] - read-write - - - - - NVIC_ICPR - Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. - 0xE280 - 0x00000000 - - - CLRPEND - Interrupt clear-pending bits.\n - Write:\n - 0 = No effect.\n - 1 = Removes pending state and interrupt.\n - Read:\n - 0 = Interrupt is not pending.\n - 1 = Interrupt is pending. - [31:0] - read-write - - - - - NVIC_IPR0 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n - Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n - These registers are only word-accessible - 0xE400 - 0x00000000 - - - IP_3 - Priority of interrupt 3 - [31:30] - read-write - - - IP_2 - Priority of interrupt 2 - [23:22] - read-write - - - IP_1 - Priority of interrupt 1 - [15:14] - read-write - - - IP_0 - Priority of interrupt 0 - [7:6] - read-write - - - - - NVIC_IPR1 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE404 - 0x00000000 - - - IP_7 - Priority of interrupt 7 - [31:30] - read-write - - - IP_6 - Priority of interrupt 6 - [23:22] - read-write - - - IP_5 - Priority of interrupt 5 - [15:14] - read-write - - - IP_4 - Priority of interrupt 4 - [7:6] - read-write - - - - - NVIC_IPR2 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE408 - 0x00000000 - - - IP_11 - Priority of interrupt 11 - [31:30] - read-write - - - IP_10 - Priority of interrupt 10 - [23:22] - read-write - - - IP_9 - Priority of interrupt 9 - [15:14] - read-write - - - IP_8 - Priority of interrupt 8 - [7:6] - read-write - - - - - NVIC_IPR3 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE40C - 0x00000000 - - - IP_15 - Priority of interrupt 15 - [31:30] - read-write - - - IP_14 - Priority of interrupt 14 - [23:22] - read-write - - - IP_13 - Priority of interrupt 13 - [15:14] - read-write - - - IP_12 - Priority of interrupt 12 - [7:6] - read-write - - - - - NVIC_IPR4 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE410 - 0x00000000 - - - IP_19 - Priority of interrupt 19 - [31:30] - read-write - - - IP_18 - Priority of interrupt 18 - [23:22] - read-write - - - IP_17 - Priority of interrupt 17 - [15:14] - read-write - - - IP_16 - Priority of interrupt 16 - [7:6] - read-write - - - - - NVIC_IPR5 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE414 - 0x00000000 - - - IP_23 - Priority of interrupt 23 - [31:30] - read-write - - - IP_22 - Priority of interrupt 22 - [23:22] - read-write - - - IP_21 - Priority of interrupt 21 - [15:14] - read-write - - - IP_20 - Priority of interrupt 20 - [7:6] - read-write - - - - - NVIC_IPR6 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE418 - 0x00000000 - - - IP_27 - Priority of interrupt 27 - [31:30] - read-write - - - IP_26 - Priority of interrupt 26 - [23:22] - read-write - - - IP_25 - Priority of interrupt 25 - [15:14] - read-write - - - IP_24 - Priority of interrupt 24 - [7:6] - read-write - - - - - NVIC_IPR7 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE41C - 0x00000000 - - - IP_31 - Priority of interrupt 31 - [31:30] - read-write - - - IP_30 - Priority of interrupt 30 - [23:22] - read-write - - - IP_29 - Priority of interrupt 29 - [15:14] - read-write - - - IP_28 - Priority of interrupt 28 - [7:6] - read-write - - - - - CPUID - Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. - 0xED00 - 0x410CC601 - - - IMPLEMENTER - Implementor code: 0x41 = ARM - [31:24] - read-only - - - VARIANT - Major revision number n in the rnpm revision status:\n - 0x0 = Revision 0. - [23:20] - read-only - - - ARCHITECTURE - Constant that defines the architecture of the processor:\n - 0xC = ARMv6-M architecture. - [19:16] - read-only - - - PARTNO - Number of processor within family: 0xC60 = Cortex-M0+ - [15:4] - read-only - - - REVISION - Minor revision number m in the rnpm revision status:\n - 0x1 = Patch 1. - [3:0] - read-only - - - - - ICSR - Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. - 0xED04 - 0x00000000 - - - NMIPENDSET - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n - NMI set-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Changes NMI exception state to pending.\n - Read:\n - 0 = NMI exception is not pending.\n - 1 = NMI exception is pending.\n - Because NMI is the highest-priority exception, normally the processor enters the NMI\n - exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n - this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n - NMI signal is reasserted while the processor is executing that handler. - [31:31] - read-write - - - PENDSVSET - PendSV set-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Changes PendSV exception state to pending.\n - Read:\n - 0 = PendSV exception is not pending.\n - 1 = PendSV exception is pending.\n - Writing 1 to this bit is the only way to set the PendSV exception state to pending. - [28:28] - read-write - - - PENDSVCLR - PendSV clear-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Removes the pending state from the PendSV exception. - [27:27] - read-write - - - PENDSTSET - SysTick exception set-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Changes SysTick exception state to pending.\n - Read:\n - 0 = SysTick exception is not pending.\n - 1 = SysTick exception is pending. - [26:26] - read-write - - - PENDSTCLR - SysTick exception clear-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Removes the pending state from the SysTick exception.\n - This bit is WO. On a register read its value is Unknown. - [25:25] - read-write - - - ISRPREEMPT - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. - [23:23] - read-only - - - ISRPENDING - External interrupt pending flag - [22:22] - read-only - - - VECTPENDING - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. - [20:12] - read-only - - - VECTACTIVE - Active exception number field. Reset clears the VECTACTIVE field. - [8:0] - read-only - - - - - VTOR - The VTOR holds the vector table offset address. - 0xED08 - 0x00000000 - - - TBLOFF - Bits [31:8] of the indicate the vector table offset address. - [31:8] - read-write - - - - - AIRCR - Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. - 0xED0C - 0x00000000 - - - VECTKEY - Register key:\n - Reads as Unknown\n - On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. - [31:16] - read-write - - - ENDIANESS - Data endianness implemented:\n - 0 = Little-endian. - [15:15] - read-only - - - SYSRESETREQ - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. - [2:2] - read-write - - - VECTCLRACTIVE - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. - [1:1] - read-write - - - - - SCR - System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. - 0xED10 - 0x00000000 - - - SEVONPEND - Send Event on Pending bit:\n - 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n - 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n - When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n - processor is not waiting for an event, the event is registered and affects the next WFE.\n - The processor also wakes up on execution of an SEV instruction or an external event. - [4:4] - read-write - - - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low power mode:\n - 0 = Sleep.\n - 1 = Deep sleep. - [2:2] - read-write - - - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n - 0 = Do not sleep when returning to Thread mode.\n - 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n - Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. - [1:1] - read-write - - - - - CCR - The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. - 0xED14 - 0x00000000 - - - STKALIGN - Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. - [9:9] - read-only - - - UNALIGN_TRP - Always reads as one, indicates that all unaligned accesses generate a HardFault. - [3:3] - read-only - - - - - SHPR2 - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. - 0xED1C - 0x00000000 - - - PRI_11 - Priority of system handler 11, SVCall - [31:30] - read-write - - - - - SHPR3 - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. - 0xED20 - 0x00000000 - - - PRI_15 - Priority of system handler 15, SysTick - [31:30] - read-write - - - PRI_14 - Priority of system handler 14, PendSV - [23:22] - read-write - - - - - SHCSR - Use the System Handler Control and State Register to determine or clear the pending status of SVCall. - 0xED24 - 0x00000000 - - - SVCALLPENDED - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. - [15:15] - read-write - - - - - MPU_TYPE - Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. - 0xED90 - 0x00000800 - - - IREGION - Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. - [23:16] - read-only - - - DREGION - Number of regions supported by the MPU. - [15:8] - read-only - - - SEPARATE - Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU. - [0:0] - read-only - - - - - MPU_CTRL - Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. - 0xED94 - 0x00000000 - - - PRIVDEFENA - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n - 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n - covered by any enabled region causes a fault.\n - 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n - When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. - [2:2] - read-write - - - HFNMIENA - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n - When the MPU is enabled:\n - 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n - 1 = the MPU is enabled during HardFault and NMI handlers. - [1:1] - read-write - - - ENABLE - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n - 0 = MPU disabled.\n - 1 = MPU enabled. - [0:0] - read-write - - - - - MPU_RNR - Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. - 0xED98 - 0x00000000 - - - REGION - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n - The MPU supports 8 memory regions, so the permitted values of this field are 0-7. - [3:0] - read-write - - - - - MPU_RBAR - Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. - 0xED9C - 0x00000000 - - - ADDR - Base address of the region. - [31:8] - read-write - - - VALID - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n - Write:\n - 0 = MPU_RNR not changed, and the processor:\n - Updates the base address for the region specified in the MPU_RNR.\n - Ignores the value of the REGION field.\n - 1 = The processor:\n - Updates the value of the MPU_RNR to the value of the REGION field.\n - Updates the base address for the region specified in the REGION field.\n - Always reads as zero. - [4:4] - read-write - - - REGION - On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. - [3:0] - read-write - - - - - MPU_RASR - Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. - 0xEDA0 - 0x00000000 - - - ATTRS - The MPU Region Attribute field. Use to define the region attribute control.\n - 28 = XN: Instruction access disable bit:\n - 0 = Instruction fetches enabled.\n - 1 = Instruction fetches disabled.\n - 26:24 = AP: Access permission field\n - 18 = S: Shareable bit\n - 17 = C: Cacheable bit\n - 16 = B: Bufferable bit - [31:16] - read-write - - - SRD - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. - [15:8] - read-write - - - SIZE - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes - [5:1] - read-write - - - ENABLE - Enables the region. - [0:0] - read-write - - - - - - - SW_IRQ - Virtual Peripheral to access unused NVIC software interrupts - 0x00000000 - - sw0_irq - Software IRQ 0 - 26 - - - sw1_irq - Software IRQ 1 - 27 - - - sw2_irq - Software IRQ 2 - 28 - - - sw3_irq - Software IRQ 3 - 29 - - - sw4_irq - Software IRQ 4 - 30 - - - sw5_irq - Software IRQ 5 - 31 - - - - \ No newline at end of file diff --git a/Tools/SVDs/rp235x.patched.svd b/Tools/SVDs/rp235x.patched.svd deleted file mode 100644 index 91ff49b5..00000000 --- a/Tools/SVDs/rp235x.patched.svd +++ /dev/null @@ -1,64929 +0,0 @@ - - - - Raspberry Pi - RP2350 - RP - 0.1 - Dual Cortex-M33 or Hazard3 processors at 150MHz - 520kB on-chip SRAM, in 10 independent banks - Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD - 8kB of one-time-programmable storage (OTP) - Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus - Additional 16MB flash/PSRAM accessible via optional second chip-select - On-chip switched-mode power supply to generate core voltage - Low-quiescent-current LDO mode can be enabled for sleep states - 2x on-chip PLLs for internal or external clock generation - GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) - Security features: - Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP - Protected OTP storage for optional boot decryption key - Global bus filtering based on Arm or RISC-V security/privilege levels - Peripherals, GPIOs and DMA channels individually assignable to security domains - Hardware mitigations for fault injection attacks - Hardware SHA-256 accelerator - Peripherals: - 2x UARTs - 2x SPI controllers - 2x I2C controllers - 24x PWM channels - USB 1.1 controller and PHY, with host and device support - 12x PIO state machines - 1x HSTX peripheral - Copyright (c) 2024 Raspberry Pi Ltd. - - SPDX-License-Identifier: BSD-3-Clause - - CM33 - r1p0 - little - true - true - true - true - 4 - false - 52 - 8 - - 8 - 32 - 0x20 - read-write - 0x00000000 - 0xFFFFFFFF - - - RESETS - 0x40020000 - - 0x0 - 0xC - registers - - - - RESET - 0x0 - 0x1FFFFFFF - - - USBCTRL - [28:28] - read-write - - - UART1 - [27:27] - read-write - - - UART0 - [26:26] - read-write - - - TRNG - [25:25] - read-write - - - TIMER1 - [24:24] - read-write - - - TIMER0 - [23:23] - read-write - - - TBMAN - [22:22] - read-write - - - SYSINFO - [21:21] - read-write - - - SYSCFG - [20:20] - read-write - - - SPI1 - [19:19] - read-write - - - SPI0 - [18:18] - read-write - - - SHA256 - [17:17] - read-write - - - PWM - [16:16] - read-write - - - PLL_USB - [15:15] - read-write - - - PLL_SYS - [14:14] - read-write - - - PIO2 - [13:13] - read-write - - - PIO1 - [12:12] - read-write - - - PIO0 - [11:11] - read-write - - - PADS_QSPI - [10:10] - read-write - - - PADS_BANK0 - [9:9] - read-write - - - JTAG - [8:8] - read-write - - - IO_QSPI - [7:7] - read-write - - - IO_BANK0 - [6:6] - read-write - - - I2C1 - [5:5] - read-write - - - I2C0 - [4:4] - read-write - - - HSTX - [3:3] - read-write - - - DMA - [2:2] - read-write - - - BUSCTRL - [1:1] - read-write - - - ADC - [0:0] - read-write - - - - - WDSEL - 0x4 - 0x00000000 - - - USBCTRL - [28:28] - read-write - - - UART1 - [27:27] - read-write - - - UART0 - [26:26] - read-write - - - TRNG - [25:25] - read-write - - - TIMER1 - [24:24] - read-write - - - TIMER0 - [23:23] - read-write - - - TBMAN - [22:22] - read-write - - - SYSINFO - [21:21] - read-write - - - SYSCFG - [20:20] - read-write - - - SPI1 - [19:19] - read-write - - - SPI0 - [18:18] - read-write - - - SHA256 - [17:17] - read-write - - - PWM - [16:16] - read-write - - - PLL_USB - [15:15] - read-write - - - PLL_SYS - [14:14] - read-write - - - PIO2 - [13:13] - read-write - - - PIO1 - [12:12] - read-write - - - PIO0 - [11:11] - read-write - - - PADS_QSPI - [10:10] - read-write - - - PADS_BANK0 - [9:9] - read-write - - - JTAG - [8:8] - read-write - - - IO_QSPI - [7:7] - read-write - - - IO_BANK0 - [6:6] - read-write - - - I2C1 - [5:5] - read-write - - - I2C0 - [4:4] - read-write - - - HSTX - [3:3] - read-write - - - DMA - [2:2] - read-write - - - BUSCTRL - [1:1] - read-write - - - ADC - [0:0] - read-write - - - - - RESET_DONE - 0x8 - 0x00000000 - - - USBCTRL - [28:28] - read-only - - - UART1 - [27:27] - read-only - - - UART0 - [26:26] - read-only - - - TRNG - [25:25] - read-only - - - TIMER1 - [24:24] - read-only - - - TIMER0 - [23:23] - read-only - - - TBMAN - [22:22] - read-only - - - SYSINFO - [21:21] - read-only - - - SYSCFG - [20:20] - read-only - - - SPI1 - [19:19] - read-only - - - SPI0 - [18:18] - read-only - - - SHA256 - [17:17] - read-only - - - PWM - [16:16] - read-only - - - PLL_USB - [15:15] - read-only - - - PLL_SYS - [14:14] - read-only - - - PIO2 - [13:13] - read-only - - - PIO1 - [12:12] - read-only - - - PIO0 - [11:11] - read-only - - - PADS_QSPI - [10:10] - read-only - - - PADS_BANK0 - [9:9] - read-only - - - JTAG - [8:8] - read-only - - - IO_QSPI - [7:7] - read-only - - - IO_BANK0 - [6:6] - read-only - - - I2C1 - [5:5] - read-only - - - I2C0 - [4:4] - read-only - - - HSTX - [3:3] - read-only - - - DMA - [2:2] - read-only - - - BUSCTRL - [1:1] - read-only - - - ADC - [0:0] - read-only - - - - - - - PSM - 0x40018000 - - 0x0 - 0x10 - registers - - - - FRCE_ON - Force block out of reset (i.e. power it on) - 0x0 - 0x00000000 - - - PROC1 - [24:24] - read-write - - - PROC0 - [23:23] - read-write - - - ACCESSCTRL - [22:22] - read-write - - - SIO - [21:21] - read-write - - - XIP - [20:20] - read-write - - - SRAM9 - [19:19] - read-write - - - SRAM8 - [18:18] - read-write - - - SRAM7 - [17:17] - read-write - - - SRAM6 - [16:16] - read-write - - - SRAM5 - [15:15] - read-write - - - SRAM4 - [14:14] - read-write - - - SRAM3 - [13:13] - read-write - - - SRAM2 - [12:12] - read-write - - - SRAM1 - [11:11] - read-write - - - SRAM0 - [10:10] - read-write - - - BOOTRAM - [9:9] - read-write - - - ROM - [8:8] - read-write - - - BUSFABRIC - [7:7] - read-write - - - PSM_READY - [6:6] - read-write - - - CLOCKS - [5:5] - read-write - - - RESETS - [4:4] - read-write - - - XOSC - [3:3] - read-write - - - ROSC - [2:2] - read-write - - - OTP - [1:1] - read-write - - - PROC_COLD - [0:0] - read-write - - - - - FRCE_OFF - Force into reset (i.e. power it off) - 0x4 - 0x00000000 - - - PROC1 - [24:24] - read-write - - - PROC0 - [23:23] - read-write - - - ACCESSCTRL - [22:22] - read-write - - - SIO - [21:21] - read-write - - - XIP - [20:20] - read-write - - - SRAM9 - [19:19] - read-write - - - SRAM8 - [18:18] - read-write - - - SRAM7 - [17:17] - read-write - - - SRAM6 - [16:16] - read-write - - - SRAM5 - [15:15] - read-write - - - SRAM4 - [14:14] - read-write - - - SRAM3 - [13:13] - read-write - - - SRAM2 - [12:12] - read-write - - - SRAM1 - [11:11] - read-write - - - SRAM0 - [10:10] - read-write - - - BOOTRAM - [9:9] - read-write - - - ROM - [8:8] - read-write - - - BUSFABRIC - [7:7] - read-write - - - PSM_READY - [6:6] - read-write - - - CLOCKS - [5:5] - read-write - - - RESETS - [4:4] - read-write - - - XOSC - [3:3] - read-write - - - ROSC - [2:2] - read-write - - - OTP - [1:1] - read-write - - - PROC_COLD - [0:0] - read-write - - - - - WDSEL - Set to 1 if the watchdog should reset this - 0x8 - 0x00000000 - - - PROC1 - [24:24] - read-write - - - PROC0 - [23:23] - read-write - - - ACCESSCTRL - [22:22] - read-write - - - SIO - [21:21] - read-write - - - XIP - [20:20] - read-write - - - SRAM9 - [19:19] - read-write - - - SRAM8 - [18:18] - read-write - - - SRAM7 - [17:17] - read-write - - - SRAM6 - [16:16] - read-write - - - SRAM5 - [15:15] - read-write - - - SRAM4 - [14:14] - read-write - - - SRAM3 - [13:13] - read-write - - - SRAM2 - [12:12] - read-write - - - SRAM1 - [11:11] - read-write - - - SRAM0 - [10:10] - read-write - - - BOOTRAM - [9:9] - read-write - - - ROM - [8:8] - read-write - - - BUSFABRIC - [7:7] - read-write - - - PSM_READY - [6:6] - read-write - - - CLOCKS - [5:5] - read-write - - - RESETS - [4:4] - read-write - - - XOSC - [3:3] - read-write - - - ROSC - [2:2] - read-write - - - OTP - [1:1] - read-write - - - PROC_COLD - [0:0] - read-write - - - - - DONE - Is the subsystem ready? - 0xC - 0x00000000 - - - PROC1 - [24:24] - read-only - - - PROC0 - [23:23] - read-only - - - ACCESSCTRL - [22:22] - read-only - - - SIO - [21:21] - read-only - - - XIP - [20:20] - read-only - - - SRAM9 - [19:19] - read-only - - - SRAM8 - [18:18] - read-only - - - SRAM7 - [17:17] - read-only - - - SRAM6 - [16:16] - read-only - - - SRAM5 - [15:15] - read-only - - - SRAM4 - [14:14] - read-only - - - SRAM3 - [13:13] - read-only - - - SRAM2 - [12:12] - read-only - - - SRAM1 - [11:11] - read-only - - - SRAM0 - [10:10] - read-only - - - BOOTRAM - [9:9] - read-only - - - ROM - [8:8] - read-only - - - BUSFABRIC - [7:7] - read-only - - - PSM_READY - [6:6] - read-only - - - CLOCKS - [5:5] - read-only - - - RESETS - [4:4] - read-only - - - XOSC - [3:3] - read-only - - - ROSC - [2:2] - read-only - - - OTP - [1:1] - read-only - - - PROC_COLD - [0:0] - read-only - - - - - - - CLOCKS - 0x40010000 - - 0x0 - 0xD4 - registers - - - CLOCKS_IRQ - 30 - - - - CLK_GPOUT0_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x0 - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors, can be changed on-the-fly - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - clksrc_pll_usb_primary_ref_opcg - 4 - - - rosc_clksrc - 5 - - - xosc_clksrc - 6 - - - lposc_clksrc - 7 - - - clk_sys - 8 - - - clk_usb - 9 - - - clk_adc - 10 - - - clk_ref - 11 - - - clk_peri - 12 - - - clk_hstx - 13 - - - otp_clk2fc - 14 - - - - - - - CLK_GPOUT0_DIV - 0x4 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [31:16] - read-write - - - FRAC - Fractional component of the divisor, can be changed on-the-fly - [15:0] - read-write - - - - - CLK_GPOUT0_SELECTED - Indicates which src is currently selected (one-hot) - 0x8 - 0x00000001 - - - CLK_GPOUT0_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_GPOUT1_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0xC - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors, can be changed on-the-fly - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - clksrc_pll_usb_primary_ref_opcg - 4 - - - rosc_clksrc - 5 - - - xosc_clksrc - 6 - - - lposc_clksrc - 7 - - - clk_sys - 8 - - - clk_usb - 9 - - - clk_adc - 10 - - - clk_ref - 11 - - - clk_peri - 12 - - - clk_hstx - 13 - - - otp_clk2fc - 14 - - - - - - - CLK_GPOUT1_DIV - 0x10 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [31:16] - read-write - - - FRAC - Fractional component of the divisor, can be changed on-the-fly - [15:0] - read-write - - - - - CLK_GPOUT1_SELECTED - Indicates which src is currently selected (one-hot) - 0x14 - 0x00000001 - - - CLK_GPOUT1_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_GPOUT2_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x18 - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors, can be changed on-the-fly - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - clksrc_pll_usb_primary_ref_opcg - 4 - - - rosc_clksrc_ph - 5 - - - xosc_clksrc - 6 - - - lposc_clksrc - 7 - - - clk_sys - 8 - - - clk_usb - 9 - - - clk_adc - 10 - - - clk_ref - 11 - - - clk_peri - 12 - - - clk_hstx - 13 - - - otp_clk2fc - 14 - - - - - - - CLK_GPOUT2_DIV - 0x1C - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [31:16] - read-write - - - FRAC - Fractional component of the divisor, can be changed on-the-fly - [15:0] - read-write - - - - - CLK_GPOUT2_SELECTED - Indicates which src is currently selected (one-hot) - 0x20 - 0x00000001 - - - CLK_GPOUT2_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_GPOUT3_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x24 - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors, can be changed on-the-fly - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - clksrc_pll_usb_primary_ref_opcg - 4 - - - rosc_clksrc_ph - 5 - - - xosc_clksrc - 6 - - - lposc_clksrc - 7 - - - clk_sys - 8 - - - clk_usb - 9 - - - clk_adc - 10 - - - clk_ref - 11 - - - clk_peri - 12 - - - clk_hstx - 13 - - - otp_clk2fc - 14 - - - - - - - CLK_GPOUT3_DIV - 0x28 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [31:16] - read-write - - - FRAC - Fractional component of the divisor, can be changed on-the-fly - [15:0] - read-write - - - - - CLK_GPOUT3_SELECTED - Indicates which src is currently selected (one-hot) - 0x2C - 0x00000001 - - - CLK_GPOUT3_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_REF_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x30 - 0x00000000 - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [6:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb_primary_ref_opcg - 3 - - - - - SRC - Selects the clock source glitchlessly, can be changed on-the-fly - [1:0] - read-write - - - rosc_clksrc_ph - 0 - - - clksrc_clk_ref_aux - 1 - - - xosc_clksrc - 2 - - - lposc_clksrc - 3 - - - - - - - CLK_REF_DIV - 0x34 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [23:16] - read-write - - - - - CLK_REF_SELECTED - Indicates which src is currently selected (one-hot) - 0x38 - 0x00000001 - - - CLK_REF_SELECTED - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. - [3:0] - read-only - - - - - CLK_SYS_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x3C - 0x00000000 - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_pll_usb - 1 - - - rosc_clksrc - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - SRC - Selects the clock source glitchlessly, can be changed on-the-fly - [0:0] - read-write - - - clk_ref - 0 - - - clksrc_clk_sys_aux - 1 - - - - - - - CLK_SYS_DIV - 0x40 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [31:16] - read-write - - - FRAC - Fractional component of the divisor, can be changed on-the-fly - [15:0] - read-write - - - - - CLK_SYS_SELECTED - Indicates which src is currently selected (one-hot) - 0x44 - 0x00000001 - - - CLK_SYS_SELECTED - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. - [1:0] - read-only - - - - - CLK_PERI_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x48 - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clk_sys - 0 - - - clksrc_pll_sys - 1 - - - clksrc_pll_usb - 2 - - - rosc_clksrc_ph - 3 - - - xosc_clksrc - 4 - - - clksrc_gpin0 - 5 - - - clksrc_gpin1 - 6 - - - - - - - CLK_PERI_DIV - 0x4C - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [17:16] - read-write - - - - - CLK_PERI_SELECTED - Indicates which src is currently selected (one-hot) - 0x50 - 0x00000001 - - - CLK_PERI_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_HSTX_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x54 - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clk_sys - 0 - - - clksrc_pll_sys - 1 - - - clksrc_pll_usb - 2 - - - clksrc_gpin0 - 3 - - - clksrc_gpin1 - 4 - - - - - - - CLK_HSTX_DIV - 0x58 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [17:16] - read-write - - - - - CLK_HSTX_SELECTED - Indicates which src is currently selected (one-hot) - 0x5C - 0x00000001 - - - CLK_HSTX_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_USB_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x60 - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_USB_DIV - 0x64 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [19:16] - read-write - - - - - CLK_USB_SELECTED - Indicates which src is currently selected (one-hot) - 0x68 - 0x00000001 - - - CLK_USB_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_ADC_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x6C - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_ADC_DIV - 0x70 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [19:16] - read-write - - - - - CLK_ADC_SELECTED - Indicates which src is currently selected (one-hot) - 0x74 - 0x00000001 - - - CLK_ADC_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - DFTCLK_XOSC_CTRL - 0x78 - 0x00000000 - - - SRC - [1:0] - read-write - - - NULL - 0 - - - clksrc_pll_usb_primary - 1 - - - clksrc_gpin0 - 2 - - - - - - - DFTCLK_ROSC_CTRL - 0x7C - 0x00000000 - - - SRC - [1:0] - read-write - - - NULL - 0 - - - clksrc_pll_sys_primary_rosc - 1 - - - clksrc_gpin1 - 2 - - - - - - - DFTCLK_LPOSC_CTRL - 0x80 - 0x00000000 - - - SRC - [1:0] - read-write - - - NULL - 0 - - - clksrc_pll_usb_primary_lposc - 1 - - - clksrc_gpin1 - 2 - - - - - - - CLK_SYS_RESUS_CTRL - 0x84 - 0x000000FF - - - CLEAR - For clearing the resus after the fault that triggered it has been corrected - [16:16] - read-write - - - FRCE - Force a resus, for test purposes only - [12:12] - read-write - - - ENABLE - Enable resus - [8:8] - read-write - - - TIMEOUT - This is expressed as a number of clk_ref cycles - and must be >= 2x clk_ref_freq/min_clk_tst_freq - [7:0] - read-write - - - - - CLK_SYS_RESUS_STATUS - 0x88 - 0x00000000 - - - RESUSSED - Clock has been resuscitated, correct the error then send ctrl_clear=1 - [0:0] - read-only - - - - - FC0_REF_KHZ - Reference clock frequency in kHz - 0x8C - 0x00000000 - - - FC0_REF_KHZ - [19:0] - read-write - - - - - FC0_MIN_KHZ - Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags - 0x90 - 0x00000000 - - - FC0_MIN_KHZ - [24:0] - read-write - - - - - FC0_MAX_KHZ - Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags - 0x94 - 0x01FFFFFF - - - FC0_MAX_KHZ - [24:0] - read-write - - - - - FC0_DELAY - Delays the start of frequency counting to allow the mux to settle - Delay is measured in multiples of the reference clock period - 0x98 - 0x00000001 - - - FC0_DELAY - [2:0] - read-write - - - - - FC0_INTERVAL - The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval - The default gives a test interval of 250us - 0x9C - 0x00000008 - - - FC0_INTERVAL - [3:0] - read-write - - - - - FC0_SRC - Clock sent to frequency counter, set to 0 when not required - Writing to this register initiates the frequency count - 0xA0 - 0x00000000 - - - FC0_SRC - [7:0] - read-write - - - NULL - 0 - - - pll_sys_clksrc_primary - 1 - - - pll_usb_clksrc_primary - 2 - - - rosc_clksrc - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clksrc_gpin0 - 6 - - - clksrc_gpin1 - 7 - - - clk_ref - 8 - - - clk_sys - 9 - - - clk_peri - 10 - - - clk_usb - 11 - - - clk_adc - 12 - - - clk_hstx - 13 - - - lposc_clksrc - 14 - - - otp_clk2fc - 15 - - - pll_usb_clksrc_primary_dft - 16 - - - - - - - FC0_STATUS - Frequency counter status - 0xA4 - 0x00000000 - - - DIED - Test clock stopped during test - [28:28] - read-only - - - FAST - Test clock faster than expected, only valid when status_done=1 - [24:24] - read-only - - - SLOW - Test clock slower than expected, only valid when status_done=1 - [20:20] - read-only - - - FAIL - Test failed - [16:16] - read-only - - - WAITING - Waiting for test clock to start - [12:12] - read-only - - - RUNNING - Test running - [8:8] - read-only - - - DONE - Test complete - [4:4] - read-only - - - PASS - Test passed - [0:0] - read-only - - - - - FC0_RESULT - Result of frequency measurement, only valid when status_done=1 - 0xA8 - 0x00000000 - - - KHZ - [29:5] - read-only - - - FRAC - [4:0] - read-only - - - - - WAKE_EN0 - enable clock in wake mode - 0xAC - 0xFFFFFFFF - - - CLK_SYS_SIO - [31:31] - read-write - - - CLK_SYS_SHA256 - [30:30] - read-write - - - CLK_SYS_PSM - [29:29] - read-write - - - CLK_SYS_ROSC - [28:28] - read-write - - - CLK_SYS_ROM - [27:27] - read-write - - - CLK_SYS_RESETS - [26:26] - read-write - - - CLK_SYS_PWM - [25:25] - read-write - - - CLK_SYS_POWMAN - [24:24] - read-write - - - CLK_REF_POWMAN - [23:23] - read-write - - - CLK_SYS_PLL_USB - [22:22] - read-write - - - CLK_SYS_PLL_SYS - [21:21] - read-write - - - CLK_SYS_PIO2 - [20:20] - read-write - - - CLK_SYS_PIO1 - [19:19] - read-write - - - CLK_SYS_PIO0 - [18:18] - read-write - - - CLK_SYS_PADS - [17:17] - read-write - - - CLK_SYS_OTP - [16:16] - read-write - - - CLK_REF_OTP - [15:15] - read-write - - - CLK_SYS_JTAG - [14:14] - read-write - - - CLK_SYS_IO - [13:13] - read-write - - - CLK_SYS_I2C1 - [12:12] - read-write - - - CLK_SYS_I2C0 - [11:11] - read-write - - - CLK_SYS_HSTX - [10:10] - read-write - - - CLK_HSTX - [9:9] - read-write - - - CLK_SYS_GLITCH_DETECTOR - [8:8] - read-write - - - CLK_SYS_DMA - [7:7] - read-write - - - CLK_SYS_BUSFABRIC - [6:6] - read-write - - - CLK_SYS_BUSCTRL - [5:5] - read-write - - - CLK_SYS_BOOTRAM - [4:4] - read-write - - - CLK_SYS_ADC - [3:3] - read-write - - - CLK_ADC - [2:2] - read-write - - - CLK_SYS_ACCESSCTRL - [1:1] - read-write - - - CLK_SYS_CLOCKS - [0:0] - read-write - - - - - WAKE_EN1 - enable clock in wake mode - 0xB0 - 0x7FFFFFFF - - - CLK_SYS_XOSC - [30:30] - read-write - - - CLK_SYS_XIP - [29:29] - read-write - - - CLK_SYS_WATCHDOG - [28:28] - read-write - - - CLK_USB - [27:27] - read-write - - - CLK_SYS_USBCTRL - [26:26] - read-write - - - CLK_SYS_UART1 - [25:25] - read-write - - - CLK_PERI_UART1 - [24:24] - read-write - - - CLK_SYS_UART0 - [23:23] - read-write - - - CLK_PERI_UART0 - [22:22] - read-write - - - CLK_SYS_TRNG - [21:21] - read-write - - - CLK_SYS_TIMER1 - [20:20] - read-write - - - CLK_SYS_TIMER0 - [19:19] - read-write - - - CLK_SYS_TICKS - [18:18] - read-write - - - CLK_REF_TICKS - [17:17] - read-write - - - CLK_SYS_TBMAN - [16:16] - read-write - - - CLK_SYS_SYSINFO - [15:15] - read-write - - - CLK_SYS_SYSCFG - [14:14] - read-write - - - CLK_SYS_SRAM9 - [13:13] - read-write - - - CLK_SYS_SRAM8 - [12:12] - read-write - - - CLK_SYS_SRAM7 - [11:11] - read-write - - - CLK_SYS_SRAM6 - [10:10] - read-write - - - CLK_SYS_SRAM5 - [9:9] - read-write - - - CLK_SYS_SRAM4 - [8:8] - read-write - - - CLK_SYS_SRAM3 - [7:7] - read-write - - - CLK_SYS_SRAM2 - [6:6] - read-write - - - CLK_SYS_SRAM1 - [5:5] - read-write - - - CLK_SYS_SRAM0 - [4:4] - read-write - - - CLK_SYS_SPI1 - [3:3] - read-write - - - CLK_PERI_SPI1 - [2:2] - read-write - - - CLK_SYS_SPI0 - [1:1] - read-write - - - CLK_PERI_SPI0 - [0:0] - read-write - - - - - SLEEP_EN0 - enable clock in sleep mode - 0xB4 - 0xFFFFFFFF - - - CLK_SYS_SIO - [31:31] - read-write - - - CLK_SYS_SHA256 - [30:30] - read-write - - - CLK_SYS_PSM - [29:29] - read-write - - - CLK_SYS_ROSC - [28:28] - read-write - - - CLK_SYS_ROM - [27:27] - read-write - - - CLK_SYS_RESETS - [26:26] - read-write - - - CLK_SYS_PWM - [25:25] - read-write - - - CLK_SYS_POWMAN - [24:24] - read-write - - - CLK_REF_POWMAN - [23:23] - read-write - - - CLK_SYS_PLL_USB - [22:22] - read-write - - - CLK_SYS_PLL_SYS - [21:21] - read-write - - - CLK_SYS_PIO2 - [20:20] - read-write - - - CLK_SYS_PIO1 - [19:19] - read-write - - - CLK_SYS_PIO0 - [18:18] - read-write - - - CLK_SYS_PADS - [17:17] - read-write - - - CLK_SYS_OTP - [16:16] - read-write - - - CLK_REF_OTP - [15:15] - read-write - - - CLK_SYS_JTAG - [14:14] - read-write - - - CLK_SYS_IO - [13:13] - read-write - - - CLK_SYS_I2C1 - [12:12] - read-write - - - CLK_SYS_I2C0 - [11:11] - read-write - - - CLK_SYS_HSTX - [10:10] - read-write - - - CLK_HSTX - [9:9] - read-write - - - CLK_SYS_GLITCH_DETECTOR - [8:8] - read-write - - - CLK_SYS_DMA - [7:7] - read-write - - - CLK_SYS_BUSFABRIC - [6:6] - read-write - - - CLK_SYS_BUSCTRL - [5:5] - read-write - - - CLK_SYS_BOOTRAM - [4:4] - read-write - - - CLK_SYS_ADC - [3:3] - read-write - - - CLK_ADC - [2:2] - read-write - - - CLK_SYS_ACCESSCTRL - [1:1] - read-write - - - CLK_SYS_CLOCKS - [0:0] - read-write - - - - - SLEEP_EN1 - enable clock in sleep mode - 0xB8 - 0x7FFFFFFF - - - CLK_SYS_XOSC - [30:30] - read-write - - - CLK_SYS_XIP - [29:29] - read-write - - - CLK_SYS_WATCHDOG - [28:28] - read-write - - - CLK_USB - [27:27] - read-write - - - CLK_SYS_USBCTRL - [26:26] - read-write - - - CLK_SYS_UART1 - [25:25] - read-write - - - CLK_PERI_UART1 - [24:24] - read-write - - - CLK_SYS_UART0 - [23:23] - read-write - - - CLK_PERI_UART0 - [22:22] - read-write - - - CLK_SYS_TRNG - [21:21] - read-write - - - CLK_SYS_TIMER1 - [20:20] - read-write - - - CLK_SYS_TIMER0 - [19:19] - read-write - - - CLK_SYS_TICKS - [18:18] - read-write - - - CLK_REF_TICKS - [17:17] - read-write - - - CLK_SYS_TBMAN - [16:16] - read-write - - - CLK_SYS_SYSINFO - [15:15] - read-write - - - CLK_SYS_SYSCFG - [14:14] - read-write - - - CLK_SYS_SRAM9 - [13:13] - read-write - - - CLK_SYS_SRAM8 - [12:12] - read-write - - - CLK_SYS_SRAM7 - [11:11] - read-write - - - CLK_SYS_SRAM6 - [10:10] - read-write - - - CLK_SYS_SRAM5 - [9:9] - read-write - - - CLK_SYS_SRAM4 - [8:8] - read-write - - - CLK_SYS_SRAM3 - [7:7] - read-write - - - CLK_SYS_SRAM2 - [6:6] - read-write - - - CLK_SYS_SRAM1 - [5:5] - read-write - - - CLK_SYS_SRAM0 - [4:4] - read-write - - - CLK_SYS_SPI1 - [3:3] - read-write - - - CLK_PERI_SPI1 - [2:2] - read-write - - - CLK_SYS_SPI0 - [1:1] - read-write - - - CLK_PERI_SPI0 - [0:0] - read-write - - - - - ENABLED0 - indicates the state of the clock enable - 0xBC - 0x00000000 - - - CLK_SYS_SIO - [31:31] - read-only - - - CLK_SYS_SHA256 - [30:30] - read-only - - - CLK_SYS_PSM - [29:29] - read-only - - - CLK_SYS_ROSC - [28:28] - read-only - - - CLK_SYS_ROM - [27:27] - read-only - - - CLK_SYS_RESETS - [26:26] - read-only - - - CLK_SYS_PWM - [25:25] - read-only - - - CLK_SYS_POWMAN - [24:24] - read-only - - - CLK_REF_POWMAN - [23:23] - read-only - - - CLK_SYS_PLL_USB - [22:22] - read-only - - - CLK_SYS_PLL_SYS - [21:21] - read-only - - - CLK_SYS_PIO2 - [20:20] - read-only - - - CLK_SYS_PIO1 - [19:19] - read-only - - - CLK_SYS_PIO0 - [18:18] - read-only - - - CLK_SYS_PADS - [17:17] - read-only - - - CLK_SYS_OTP - [16:16] - read-only - - - CLK_REF_OTP - [15:15] - read-only - - - CLK_SYS_JTAG - [14:14] - read-only - - - CLK_SYS_IO - [13:13] - read-only - - - CLK_SYS_I2C1 - [12:12] - read-only - - - CLK_SYS_I2C0 - [11:11] - read-only - - - CLK_SYS_HSTX - [10:10] - read-only - - - CLK_HSTX - [9:9] - read-only - - - CLK_SYS_GLITCH_DETECTOR - [8:8] - read-only - - - CLK_SYS_DMA - [7:7] - read-only - - - CLK_SYS_BUSFABRIC - [6:6] - read-only - - - CLK_SYS_BUSCTRL - [5:5] - read-only - - - CLK_SYS_BOOTRAM - [4:4] - read-only - - - CLK_SYS_ADC - [3:3] - read-only - - - CLK_ADC - [2:2] - read-only - - - CLK_SYS_ACCESSCTRL - [1:1] - read-only - - - CLK_SYS_CLOCKS - [0:0] - read-only - - - - - ENABLED1 - indicates the state of the clock enable - 0xC0 - 0x00000000 - - - CLK_SYS_XOSC - [30:30] - read-only - - - CLK_SYS_XIP - [29:29] - read-only - - - CLK_SYS_WATCHDOG - [28:28] - read-only - - - CLK_USB - [27:27] - read-only - - - CLK_SYS_USBCTRL - [26:26] - read-only - - - CLK_SYS_UART1 - [25:25] - read-only - - - CLK_PERI_UART1 - [24:24] - read-only - - - CLK_SYS_UART0 - [23:23] - read-only - - - CLK_PERI_UART0 - [22:22] - read-only - - - CLK_SYS_TRNG - [21:21] - read-only - - - CLK_SYS_TIMER1 - [20:20] - read-only - - - CLK_SYS_TIMER0 - [19:19] - read-only - - - CLK_SYS_TICKS - [18:18] - read-only - - - CLK_REF_TICKS - [17:17] - read-only - - - CLK_SYS_TBMAN - [16:16] - read-only - - - CLK_SYS_SYSINFO - [15:15] - read-only - - - CLK_SYS_SYSCFG - [14:14] - read-only - - - CLK_SYS_SRAM9 - [13:13] - read-only - - - CLK_SYS_SRAM8 - [12:12] - read-only - - - CLK_SYS_SRAM7 - [11:11] - read-only - - - CLK_SYS_SRAM6 - [10:10] - read-only - - - CLK_SYS_SRAM5 - [9:9] - read-only - - - CLK_SYS_SRAM4 - [8:8] - read-only - - - CLK_SYS_SRAM3 - [7:7] - read-only - - - CLK_SYS_SRAM2 - [6:6] - read-only - - - CLK_SYS_SRAM1 - [5:5] - read-only - - - CLK_SYS_SRAM0 - [4:4] - read-only - - - CLK_SYS_SPI1 - [3:3] - read-only - - - CLK_PERI_SPI1 - [2:2] - read-only - - - CLK_SYS_SPI0 - [1:1] - read-only - - - CLK_PERI_SPI0 - [0:0] - read-only - - - - - INTR - Raw Interrupts - 0xC4 - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0xC8 - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-write - - - - - INTF - Interrupt Force - 0xCC - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0xD0 - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-only - - - - - - - TICKS - 0x40108000 - - 0x0 - 0x48 - registers - - - - 6 - 0xC - PROC0,PROC1,TIMER0,TIMER1,WATCHDOG,RISCV - TICK%s - Cluster TICK%s, containing *_CTRL, *_CYCLES, *_COUNT - 0x0 - - CTRL - Controls the tick generator - 0x0 - 0x00000000 - - - RUNNING - Is the tick generator running? - [1:1] - read-only - - - ENABLE - start / stop tick generation - [0:0] - read-write - - - - - CYCLES - 0x4 - 0x00000000 - - - PROC0_CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - COUNT - 0x8 - 0x00000000 - - - PROC0_COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [8:0] - read-only - - - - - - - - PADS_BANK0 - 0x40038000 - - 0x0 - 0xCC - registers - - - - VOLTAGE_SELECT - Voltage select. Per bank control - 0x0 - 0x00000000 - - - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - Set voltage to 3.3V (DVDD >= 2V5) - 0 - - - 1v8 - Set voltage to 1.8V (DVDD <= 1V8) - 1 - - - - - - - 48 - 0x4 - 0-47 - GPIO%s - 0x4 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - SWCLK - 0xC4 - 0x0000005A - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - SWD - 0xC8 - 0x0000005A - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - - - PADS_QSPI - 0x40040000 - - 0x0 - 0x1C - registers - - - - VOLTAGE_SELECT - Voltage select. Per bank control - 0x0 - 0x00000000 - - - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - Set voltage to 3.3V (DVDD >= 2V5) - 0 - - - 1v8 - Set voltage to 1.8V (DVDD <= 1V8) - 1 - - - - - - - GPIO_QSPI_SCLK - 0x4 - 0x00000156 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD0 - 0x8 - 0x00000156 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD1 - 0xC - 0x00000156 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD2 - 0x10 - 0x0000015A - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD3 - 0x14 - 0x0000015A - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SS - 0x18 - 0x0000015A - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - - - IO_QSPI - 0x40030000 - - 0x0 - 0x240 - registers - - - IO_IRQ_QSPI - 23 - - - IO_IRQ_QSPI_NS - 24 - - - - USBPHY_DP_STATUS - 0x0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - USBPHY_DP_CTRL - 0x4 - 0x0000001F - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [15:14] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - siob_proc_56 - 5 - - - null - 31 - - - - - - - USBPHY_DM_STATUS - 0x8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - USBPHY_DM_CTRL - 0xC - 0x0000001F - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [15:14] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - siob_proc_57 - 5 - - - null - 31 - - - - - - - 6 - 0x8 - SCLK,SS,SD0,SD1,SD2,SD3 - GPIO_QSPI%s - Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL - 0x10 - - GPIO_STATUS - 0x0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO_CTRL - 0x4 - 0x0000001F - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [15:14] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sclk - 0 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - siob_proc_58 - 5 - - - uart1_tx - 11 - - - null - 31 - - - - - - - - IRQSUMMARY_PROC0_SECURE - 0x200 - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - IRQSUMMARY_PROC0_NONSECURE - 0x204 - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_SECURE - 0x208 - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_NONSECURE - 0x20C - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_SECURE - 0x210 - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_NONSECURE - 0x214 - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - INTR - Raw Interrupts - 0x218 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-only - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - oneToClear - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - oneToClear - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-only - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-only - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - oneToClear - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - oneToClear - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-only - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTE - Interrupt Enable for proc0 - 0x21C - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF - Interrupt Force for proc0 - 0x220 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTS - Interrupt status after masking & forcing for proc0 - 0x224 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-only - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-only - - - USBPHY_DM_EDGE_LOW - [6:6] - read-only - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-only - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-only - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-only - - - USBPHY_DP_EDGE_LOW - [2:2] - read-only - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-only - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTE - Interrupt Enable for proc1 - 0x228 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF - Interrupt Force for proc1 - 0x22C - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTS - Interrupt status after masking & forcing for proc1 - 0x230 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-only - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-only - - - USBPHY_DM_EDGE_LOW - [6:6] - read-only - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-only - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-only - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-only - - - USBPHY_DP_EDGE_LOW - [2:2] - read-only - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-only - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTE - Interrupt Enable for dormant_wake - 0x234 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF - Interrupt Force for dormant_wake - 0x238 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTS - Interrupt status after masking & forcing for dormant_wake - 0x23C - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-only - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-only - - - USBPHY_DM_EDGE_LOW - [6:6] - read-only - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-only - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-only - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-only - - - USBPHY_DP_EDGE_LOW - [2:2] - read-only - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-only - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-only - - - - - - - IO_BANK0 - 0x40028000 - - 0x0 - 0x320 - registers - - - IO_IRQ_BANK0 - 21 - - - IO_IRQ_BANK0_NS - 22 - - - - 48 - 0x8 - 0-47 - GPIO%s - Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL - 0x0 - - GPIO_STATUS - 0x0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO_CTRL - 0x4 - 0x0000001F - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [15:14] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins. - [4:0] - read-write - - FUNCSEL - - jtag - Connect to JTAG peripheral - 0 - - - spi - Connect to matching SPI peripheral - 1 - - - uart - Connect to matching UART peripheral - 2 - - - i2c - Connect to matching I2C peripheral - 3 - - - pwm - Connect to matching PWM peripheral - 4 - - - sio - Use as a GPIO pin (connect to SIO peripheral) - 5 - - - pio0 - Connect to PIO0 peripheral - 6 - - - pio1 - Connect to PIO1 peripheral - 7 - - - pio2 - Connect to PIO2 peripheral - 8 - - - gpck - Connect to GPCK peripheral - 9 - - - usb - Connect to USB peripheral - 10 - - - uart_aux - Connect to matching UART_AUX peripheral - 11 - - - null - Connect to nothing - 31 - - - - - - - - IRQSUMMARY_PROC0_SECURE0 - 0x200 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_PROC0_SECURE1 - 0x204 - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - IRQSUMMARY_PROC0_NONSECURE0 - 0x208 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_PROC0_NONSECURE1 - 0x20C - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_SECURE0 - 0x210 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_SECURE1 - 0x214 - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_NONSECURE0 - 0x218 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_NONSECURE1 - 0x21C - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_SECURE0 - 0x220 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_SECURE1 - 0x224 - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_NONSECURE0 - 0x228 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_NONSECURE1 - 0x22C - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - 6 - 0x4 - 0-5 - INTR%s - Raw Interrupts - 0x230 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO7_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO6_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO5_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO4_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO3_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO2_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO1_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO0_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - 6 - 0x4 - 0-5 - PROC0_INTE%s - Interrupt Enable for proc0 - 0x248 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 6 - 0x4 - 0-5 - PROC0_INTF%s - Interrupt Force for proc0 - 0x260 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 6 - 0x4 - 0-5 - PROC0_INTS%s - Interrupt status after masking & forcing for proc0 - 0x278 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - 6 - 0x4 - 0-5 - PROC1_INTE%s - Interrupt Enable for proc1 - 0x290 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 6 - 0x4 - 0-5 - PROC1_INTF%s - Interrupt Force for proc1 - 0x2A8 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 6 - 0x4 - 0-5 - PROC1_INTS%s - Interrupt status after masking & forcing for proc1 - 0x2C0 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - 6 - 0x4 - 0-5 - DORMANT_WAKE_INTE%s - Interrupt Enable for dormant_wake - 0x2D8 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 6 - 0x4 - 0-5 - DORMANT_WAKE_INTF%s - Interrupt Force for dormant_wake - 0x2F0 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - 6 - 0x4 - 0-5 - DORMANT_WAKE_INTS%s - Interrupt status after masking & forcing for dormant_wake - 0x308 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - - - SYSINFO - 0x40000000 - - 0x0 - 0x18 - registers - - - - CHIP_ID - JEDEC JEP-106 compliant chip identifier. - 0x0 - 0x00000001 - - - REVISION - [31:28] - read-only - - - PART - [27:12] - read-only - - - MANUFACTURER - [11:1] - read-only - - - STOP_BIT - [0:0] - read-only - - - - - PACKAGE_SEL - 0x4 - 0x00000000 - - - PACKAGE_SEL - [0:0] - read-only - - - - - PLATFORM - Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM. - 0x8 - 0x00000000 - - - GATESIM - [4:4] - read-only - - - BATCHSIM - [3:3] - read-only - - - HDLSIM - [2:2] - read-only - - - ASIC - [1:1] - read-only - - - FPGA - [0:0] - read-only - - - - - GITREF_RP2350 - Git hash of the chip source. Used to identify chip version. - 0x14 - 0x00000000 - - - GITREF_RP2350 - [31:0] - read-only - - - - - - - SHA256 - SHA-256 hash function implementation - 0x400F8000 - - 0x0 - 0x28 - registers - - - - CSR - Control and status register - 0x0 - 0x00001206 - - - BSWAP - Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. - - This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. - - However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. - - This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around. - [12:12] - read-write - - - DMA_SIZE - Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. - - The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block. - [9:8] - read-write - - - 8bit - 0 - - - 16bit - 1 - - - 32bit - 2 - - - - - ERR_WDATA_NOT_RDY - Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear. - [4:4] - read-write - oneToClear - - - SUM_VLD - If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. - - Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed. - [2:2] - read-only - - - WDATA_RDY - If 1, the SHA-256 core is ready to accept more data through the WDATA register. - - After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest. - [1:1] - read-only - - - START - Write 1 to prepare the SHA-256 core for a new checksum. - - The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. - - START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers. - [0:0] - write-only - - - - - WDATA - Write data register - 0x4 - 0x00000000 - - - WDATA - After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. - - Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. - - After this, WDATA_RDY will return high, and more data can be written (if any). - - This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block. - [31:0] - write-only - - - - - SUM0 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x8 - 0x00000000 - - - SUM0 - [31:0] - read-only - - - - - SUM1 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0xC - 0x00000000 - - - SUM1 - [31:0] - read-only - - - - - SUM2 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x10 - 0x00000000 - - - SUM2 - [31:0] - read-only - - - - - SUM3 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x14 - 0x00000000 - - - SUM3 - [31:0] - read-only - - - - - SUM4 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x18 - 0x00000000 - - - SUM4 - [31:0] - read-only - - - - - SUM5 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x1C - 0x00000000 - - - SUM5 - [31:0] - read-only - - - - - SUM6 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x20 - 0x00000000 - - - SUM6 - [31:0] - read-only - - - - - SUM7 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x24 - 0x00000000 - - - SUM7 - [31:0] - read-only - - - - - - - HSTX_FIFO - FIFO status and write access for HSTX - 0x50600000 - - 0x0 - 0x8 - registers - - - - STAT - FIFO status - 0x0 - 0x00000000 - - - WOF - FIFO was written when full. Write 1 to clear. - [10:10] - read-write - oneToClear - - - EMPTY - [9:9] - read-only - - - FULL - [8:8] - read-only - - - LEVEL - [7:0] - read-only - - - - - FIFO - Write access to FIFO - 0x4 - 0x00000000 - - - FIFO - [31:0] - write-only - - - - - - - HSTX_CTRL - Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. - 0x400C0000 - - 0x0 - 0x2C - registers - - - - CSR - 0x0 - 0x10050600 - - - CLKDIV - Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. - - For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). - - A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles. - [31:28] - read-write - - - CLKPHASE - Set the initial phase of the generated clock. - - A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: - - * The clock will be initially low - - * The first rising edge will be 0.5 clk_hstx cycles after asserting first data - - * The first falling edge will be 1.5 clk_hstx cycles after asserting first data - - This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. - - When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. - - Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined. - [27:24] - read-write - - - N_SHIFTS - Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) - - A register value of 0 means shift 32 times. - [20:16] - read-write - - - SHIFT - How many bits to right-rotate the shift register by each cycle. - - The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32. - [12:8] - read-write - - - COUPLED_SEL - Select which PIO to use for coupled mode operation. - [6:5] - read-write - - - COUPLED_MODE - Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. - - When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. - - The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. - - For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged. - [4:4] - read-write - - - EXPAND_EN - Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. - - Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN. - [1:1] - read-write - - - EN - When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. - - When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. - - Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched. - [0:0] - read-write - - - - - BIT0 - Data control register for output bit 0 - 0x4 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT1 - Data control register for output bit 1 - 0x8 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT2 - Data control register for output bit 2 - 0xC - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT3 - Data control register for output bit 3 - 0x10 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT4 - Data control register for output bit 4 - 0x14 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT5 - Data control register for output bit 5 - 0x18 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT6 - Data control register for output bit 6 - 0x1C - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT7 - Data control register for output bit 7 - 0x20 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - EXPAND_SHIFT - Configure the optional shifter inside the command expander - 0x24 - 0x01000100 - - - ENC_N_SHIFTS - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times. - [28:24] - read-write - - - ENC_SHIFT - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS). - [20:16] - read-write - - - RAW_N_SHIFTS - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times. - [12:8] - read-write - - - RAW_SHIFT - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command. - [4:0] - read-write - - - - - EXPAND_TMDS - Configure the optional TMDS encoder inside the command expander - 0x28 - 0x00000000 - - - L2_NBITS - Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. - [23:21] - read-write - - - L2_ROT - Right-rotate applied to the current shifter data before the lane 2 TMDS encoder. - [20:16] - read-write - - - L1_NBITS - Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. - [15:13] - read-write - - - L1_ROT - Right-rotate applied to the current shifter data before the lane 1 TMDS encoder. - [12:8] - read-write - - - L0_NBITS - Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. - [7:5] - read-write - - - L0_ROT - Right-rotate applied to the current shifter data before the lane 0 TMDS encoder. - [4:0] - read-write - - - - - - - EPPB - Cortex-M33 EPPB vendor register block for RP2350 - 0xE0080000 - - 0x0 - 0xC - registers - - - - NMI_MASK0 - NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset. - 0x0 - 0x00000000 - - - NMI_MASK0 - [31:0] - read-write - - - - - NMI_MASK1 - NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset. - 0x4 - 0x00000000 - - - NMI_MASK1 - [19:0] - read-write - - - - - SLEEPCTRL - Nonstandard sleep control register - 0x8 - 0x00000002 - - - WICENACK - Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK. - [2:2] - read-only - - - WICENREQ - Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change. - [1:1] - read-write - - - LIGHT_SLEEP - By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. - - Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request. - [0:0] - read-write - - - - - - - PPB - TEAL registers accessible through the debug interface - 0xE0000000 - - 0x0 - 0x43000 - registers - - - - ITM_STIM0 - Provides the interface for generating Instrumentation packets - 0x0 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM1 - Provides the interface for generating Instrumentation packets - 0x4 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM2 - Provides the interface for generating Instrumentation packets - 0x8 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM3 - Provides the interface for generating Instrumentation packets - 0xC - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM4 - Provides the interface for generating Instrumentation packets - 0x10 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM5 - Provides the interface for generating Instrumentation packets - 0x14 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM6 - Provides the interface for generating Instrumentation packets - 0x18 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM7 - Provides the interface for generating Instrumentation packets - 0x1C - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM8 - Provides the interface for generating Instrumentation packets - 0x20 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM9 - Provides the interface for generating Instrumentation packets - 0x24 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM10 - Provides the interface for generating Instrumentation packets - 0x28 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM11 - Provides the interface for generating Instrumentation packets - 0x2C - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM12 - Provides the interface for generating Instrumentation packets - 0x30 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM13 - Provides the interface for generating Instrumentation packets - 0x34 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM14 - Provides the interface for generating Instrumentation packets - 0x38 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM15 - Provides the interface for generating Instrumentation packets - 0x3C - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM16 - Provides the interface for generating Instrumentation packets - 0x40 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM17 - Provides the interface for generating Instrumentation packets - 0x44 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM18 - Provides the interface for generating Instrumentation packets - 0x48 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM19 - Provides the interface for generating Instrumentation packets - 0x4C - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM20 - Provides the interface for generating Instrumentation packets - 0x50 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM21 - Provides the interface for generating Instrumentation packets - 0x54 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM22 - Provides the interface for generating Instrumentation packets - 0x58 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM23 - Provides the interface for generating Instrumentation packets - 0x5C - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM24 - Provides the interface for generating Instrumentation packets - 0x60 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM25 - Provides the interface for generating Instrumentation packets - 0x64 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM26 - Provides the interface for generating Instrumentation packets - 0x68 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM27 - Provides the interface for generating Instrumentation packets - 0x6C - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM28 - Provides the interface for generating Instrumentation packets - 0x70 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM29 - Provides the interface for generating Instrumentation packets - 0x74 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM30 - Provides the interface for generating Instrumentation packets - 0x78 - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM31 - Provides the interface for generating Instrumentation packets - 0x7C - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_TER0 - Provide an individual enable bit for each ITM_STIM register - 0xE00 - 0x00000000 - - - STIMENA - For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled - [31:0] - read-write - - - - - ITM_TPR - Controls which stimulus ports can be accessed by unprivileged code - 0xE40 - 0x00000000 - - - PRIVMASK - Bit mask to enable tracing on ITM stimulus ports - [3:0] - read-write - - - - - ITM_TCR - Configures and controls transfers through the ITM interface - 0xE80 - 0x00000000 - - - BUSY - Indicates whether the ITM is currently processing events - [23:23] - read-only - - - TRACEBUSID - Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field - [22:16] - read-write - - - GTSFREQ - Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps - [11:10] - read-write - - - TSPRESCALE - Local timestamp prescaler, used with the trace packet reference clock - [9:8] - read-write - - - STALLENA - Stall the PE to guarantee delivery of Data Trace packets. - [5:5] - read-write - - - SWOENA - Enables asynchronous clocking of the timestamp counter - [4:4] - read-write - - - TXENA - Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU - [3:3] - read-write - - - SYNCENA - Enables Synchronization packet transmission for a synchronous TPIU - [2:2] - read-write - - - TSENA - Enables Local timestamp generation - [1:1] - read-write - - - ITMENA - Enables the ITM - [0:0] - read-write - - - - - INT_ATREADY - Integration Mode: Read ATB Ready - 0xEF0 - 0x00000000 - - - AFVALID - A read of this bit returns the value of AFVALID - [1:1] - read-only - - - ATREADY - A read of this bit returns the value of ATREADY - [0:0] - read-only - - - - - INT_ATVALID - Integration Mode: Write ATB Valid - 0xEF8 - 0x00000000 - - - AFREADY - A write to this bit gives the value of AFREADY - [1:1] - read-write - - - ATREADY - A write to this bit gives the value of ATVALID - [0:0] - read-write - - - - - ITM_ITCTRL - Integration Mode Control Register - 0xF00 - 0x00000000 - - - IME - Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing. - [0:0] - read-write - - - - - ITM_DEVARCH - Provides CoreSight discovery information for the ITM - 0xFBC - 0x47701A01 - - - ARCHITECT - Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. - [31:21] - read-only - - - PRESENT - Defines that the DEVARCH register is present - [20:20] - read-only - - - REVISION - Defines the architecture revision of the component - [19:16] - read-only - - - ARCHVER - Defines the architecture version of the component - [15:12] - read-only - - - ARCHPART - Defines the architecture of the component - [11:0] - read-only - - - - - ITM_DEVTYPE - Provides CoreSight discovery information for the ITM - 0xFCC - 0x00000043 - - - SUB - Component sub-type - [7:4] - read-only - - - MAJOR - Component major type - [3:0] - read-only - - - - - ITM_PIDR4 - Provides CoreSight discovery information for the ITM - 0xFD0 - 0x00000004 - - - SIZE - See CoreSight Architecture Specification - [7:4] - read-only - - - DES_2 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - ITM_PIDR5 - Provides CoreSight discovery information for the ITM - 0xFD4 - 0x00000000 - - - ITM_PIDR5 - [31:0] - read-write - - - - - ITM_PIDR6 - Provides CoreSight discovery information for the ITM - 0xFD8 - 0x00000000 - - - ITM_PIDR6 - [31:0] - read-write - - - - - ITM_PIDR7 - Provides CoreSight discovery information for the ITM - 0xFDC - 0x00000000 - - - ITM_PIDR7 - [31:0] - read-write - - - - - ITM_PIDR0 - Provides CoreSight discovery information for the ITM - 0xFE0 - 0x00000021 - - - PART_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - ITM_PIDR1 - Provides CoreSight discovery information for the ITM - 0xFE4 - 0x000000BD - - - DES_0 - See CoreSight Architecture Specification - [7:4] - read-only - - - PART_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - ITM_PIDR2 - Provides CoreSight discovery information for the ITM - 0xFE8 - 0x0000000B - - - REVISION - See CoreSight Architecture Specification - [7:4] - read-only - - - JEDEC - See CoreSight Architecture Specification - [3:3] - read-only - - - DES_1 - See CoreSight Architecture Specification - [2:0] - read-only - - - - - ITM_PIDR3 - Provides CoreSight discovery information for the ITM - 0xFEC - 0x00000000 - - - REVAND - See CoreSight Architecture Specification - [7:4] - read-only - - - CMOD - See CoreSight Architecture Specification - [3:0] - read-only - - - - - ITM_CIDR0 - Provides CoreSight discovery information for the ITM - 0xFF0 - 0x0000000D - - - PRMBL_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - ITM_CIDR1 - Provides CoreSight discovery information for the ITM - 0xFF4 - 0x00000090 - - - CLASS - See CoreSight Architecture Specification - [7:4] - read-only - - - PRMBL_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - ITM_CIDR2 - Provides CoreSight discovery information for the ITM - 0xFF8 - 0x00000005 - - - PRMBL_2 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - ITM_CIDR3 - Provides CoreSight discovery information for the ITM - 0xFFC - 0x000000B1 - - - PRMBL_3 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DWT_CTRL - Provides configuration and status information for the DWT unit, and used to control features of the unit - 0x1000 - 0x73741824 - - - NUMCOMP - Number of DWT comparators implemented - [31:28] - read-only - - - NOTRCPKT - Indicates whether the implementation does not support trace - [27:27] - read-only - - - NOEXTTRIG - Reserved, RAZ - [26:26] - read-only - - - NOCYCCNT - Indicates whether the implementation does not include a cycle counter - [25:25] - read-only - - - NOPRFCNT - Indicates whether the implementation does not include the profiling counters - [24:24] - read-only - - - CYCDISS - Controls whether the cycle counter is disabled in Secure state - [23:23] - read-write - - - CYCEVTENA - Enables Event Counter packet generation on POSTCNT underflow - [22:22] - read-write - - - FOLDEVTENA - Enables DWT_FOLDCNT counter - [21:21] - read-write - - - LSUEVTENA - Enables DWT_LSUCNT counter - [20:20] - read-write - - - SLEEPEVTENA - Enable DWT_SLEEPCNT counter - [19:19] - read-write - - - EXCEVTENA - Enables DWT_EXCCNT counter - [18:18] - read-write - - - CPIEVTENA - Enables DWT_CPICNT counter - [17:17] - read-write - - - EXTTRCENA - Enables generation of Exception Trace packets - [16:16] - read-write - - - PCSAMPLENA - Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation - [12:12] - read-write - - - SYNCTAP - Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate - [11:10] - read-write - - - CYCTAP - Selects the position of the POSTCNT tap on the CYCCNT counter - [9:9] - read-write - - - POSTINIT - Initial value for the POSTCNT counter - [8:5] - read-write - - - POSTPRESET - Reload value for the POSTCNT counter - [4:1] - read-write - - - CYCCNTENA - Enables CYCCNT - [0:0] - read-write - - - - - DWT_CYCCNT - Shows or sets the value of the processor cycle counter, CYCCNT - 0x1004 - 0x00000000 - - - CYCCNT - Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero - [31:0] - read-write - - - - - DWT_EXCCNT - Counts the total cycles spent in exception processing - 0x100C - 0x00000000 - - - EXCCNT - Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. - [7:0] - read-write - - - - - DWT_LSUCNT - Increments on the additional cycles required to execute all load or store instructions - 0x1014 - 0x00000000 - - - LSUCNT - Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. - [7:0] - read-write - - - - - DWT_FOLDCNT - Increments on the additional cycles required to execute all load or store instructions - 0x1018 - 0x00000000 - - - FOLDCNT - Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one - [7:0] - read-write - - - - - DWT_COMP0 - Provides a reference value for use by watchpoint comparator 0 - 0x1020 - 0x00000000 - - - DWT_COMP0 - [31:0] - read-write - - - - - DWT_FUNCTION0 - Controls the operation of watchpoint comparator 0 - 0x1028 - 0x58000000 - - - ID - Identifies the capabilities for MATCH for comparator *n - [31:27] - read-only - - - MATCHED - Set to 1 when the comparator matches - [24:24] - read-only - - - DATAVSIZE - Defines the size of the object being watched for by Data Value and Data Address comparators - [11:10] - read-write - - - ACTION - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH - [5:4] - read-write - - - MATCH - Controls the type of match generated by this comparator - [3:0] - read-write - - - - - DWT_COMP1 - Provides a reference value for use by watchpoint comparator 1 - 0x1030 - 0x00000000 - - - DWT_COMP1 - [31:0] - read-write - - - - - DWT_FUNCTION1 - Controls the operation of watchpoint comparator 1 - 0x1038 - 0x89000828 - - - ID - Identifies the capabilities for MATCH for comparator *n - [31:27] - read-only - - - MATCHED - Set to 1 when the comparator matches - [24:24] - read-only - - - DATAVSIZE - Defines the size of the object being watched for by Data Value and Data Address comparators - [11:10] - read-write - - - ACTION - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH - [5:4] - read-write - - - MATCH - Controls the type of match generated by this comparator - [3:0] - read-write - - - - - DWT_COMP2 - Provides a reference value for use by watchpoint comparator 2 - 0x1040 - 0x00000000 - - - DWT_COMP2 - [31:0] - read-write - - - - - DWT_FUNCTION2 - Controls the operation of watchpoint comparator 2 - 0x1048 - 0x50000000 - - - ID - Identifies the capabilities for MATCH for comparator *n - [31:27] - read-only - - - MATCHED - Set to 1 when the comparator matches - [24:24] - read-only - - - DATAVSIZE - Defines the size of the object being watched for by Data Value and Data Address comparators - [11:10] - read-write - - - ACTION - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH - [5:4] - read-write - - - MATCH - Controls the type of match generated by this comparator - [3:0] - read-write - - - - - DWT_COMP3 - Provides a reference value for use by watchpoint comparator 3 - 0x1050 - 0x00000000 - - - DWT_COMP3 - [31:0] - read-write - - - - - DWT_FUNCTION3 - Controls the operation of watchpoint comparator 3 - 0x1058 - 0x20000800 - - - ID - Identifies the capabilities for MATCH for comparator *n - [31:27] - read-only - - - MATCHED - Set to 1 when the comparator matches - [24:24] - read-only - - - DATAVSIZE - Defines the size of the object being watched for by Data Value and Data Address comparators - [11:10] - read-write - - - ACTION - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH - [5:4] - read-write - - - MATCH - Controls the type of match generated by this comparator - [3:0] - read-write - - - - - DWT_DEVARCH - Provides CoreSight discovery information for the DWT - 0x1FBC - 0x47701A02 - - - ARCHITECT - Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. - [31:21] - read-only - - - PRESENT - Defines that the DEVARCH register is present - [20:20] - read-only - - - REVISION - Defines the architecture revision of the component - [19:16] - read-only - - - ARCHVER - Defines the architecture version of the component - [15:12] - read-only - - - ARCHPART - Defines the architecture of the component - [11:0] - read-only - - - - - DWT_DEVTYPE - Provides CoreSight discovery information for the DWT - 0x1FCC - 0x00000000 - - - SUB - Component sub-type - [7:4] - read-only - - - MAJOR - Component major type - [3:0] - read-only - - - - - DWT_PIDR4 - Provides CoreSight discovery information for the DWT - 0x1FD0 - 0x00000004 - - - SIZE - See CoreSight Architecture Specification - [7:4] - read-only - - - DES_2 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DWT_PIDR5 - Provides CoreSight discovery information for the DWT - 0x1FD4 - 0x00000000 - - - DWT_PIDR5 - [31:0] - read-write - - - - - DWT_PIDR6 - Provides CoreSight discovery information for the DWT - 0x1FD8 - 0x00000000 - - - DWT_PIDR6 - [31:0] - read-write - - - - - DWT_PIDR7 - Provides CoreSight discovery information for the DWT - 0x1FDC - 0x00000000 - - - DWT_PIDR7 - [31:0] - read-write - - - - - DWT_PIDR0 - Provides CoreSight discovery information for the DWT - 0x1FE0 - 0x00000021 - - - PART_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DWT_PIDR1 - Provides CoreSight discovery information for the DWT - 0x1FE4 - 0x000000BD - - - DES_0 - See CoreSight Architecture Specification - [7:4] - read-only - - - PART_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DWT_PIDR2 - Provides CoreSight discovery information for the DWT - 0x1FE8 - 0x0000000B - - - REVISION - See CoreSight Architecture Specification - [7:4] - read-only - - - JEDEC - See CoreSight Architecture Specification - [3:3] - read-only - - - DES_1 - See CoreSight Architecture Specification - [2:0] - read-only - - - - - DWT_PIDR3 - Provides CoreSight discovery information for the DWT - 0x1FEC - 0x00000000 - - - REVAND - See CoreSight Architecture Specification - [7:4] - read-only - - - CMOD - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DWT_CIDR0 - Provides CoreSight discovery information for the DWT - 0x1FF0 - 0x0000000D - - - PRMBL_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DWT_CIDR1 - Provides CoreSight discovery information for the DWT - 0x1FF4 - 0x00000090 - - - CLASS - See CoreSight Architecture Specification - [7:4] - read-only - - - PRMBL_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DWT_CIDR2 - Provides CoreSight discovery information for the DWT - 0x1FF8 - 0x00000005 - - - PRMBL_2 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DWT_CIDR3 - Provides CoreSight discovery information for the DWT - 0x1FFC - 0x000000B1 - - - PRMBL_3 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - FP_CTRL - Provides FPB implementation information, and the global enable for the FPB unit - 0x2000 - 0x60005580 - - - REV - Flash Patch and Breakpoint Unit architecture revision - [31:28] - read-only - - - NUM_CODE_14_12_ - Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 - [14:12] - read-only - - - NUM_LIT - Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1 - [11:8] - read-only - - - NUM_CODE_7_4_ - Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 - [7:4] - read-only - - - KEY - Writes to the FP_CTRL are ignored unless KEY is concurrently written to one - [1:1] - read-write - - - ENABLE - Enables the FPB - [0:0] - read-write - - - - - FP_REMAP - Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap - 0x2004 - 0x00000000 - - - RMPSPT - Indicates whether the FPB unit supports the Flash Patch remap function - [29:29] - read-only - - - REMAP - Holds the bits[28:5] of the Flash Patch remap address - [28:5] - read-only - - - - - FP_COMP0 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x2008 - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP1 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x200C - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP2 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x2010 - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP3 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x2014 - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP4 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x2018 - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP5 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x201C - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP6 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x2020 - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP7 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x2024 - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_DEVARCH - Provides CoreSight discovery information for the FPB - 0x2FBC - 0x47701A03 - - - ARCHITECT - Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. - [31:21] - read-only - - - PRESENT - Defines that the DEVARCH register is present - [20:20] - read-only - - - REVISION - Defines the architecture revision of the component - [19:16] - read-only - - - ARCHVER - Defines the architecture version of the component - [15:12] - read-only - - - ARCHPART - Defines the architecture of the component - [11:0] - read-only - - - - - FP_DEVTYPE - Provides CoreSight discovery information for the FPB - 0x2FCC - 0x00000000 - - - SUB - Component sub-type - [7:4] - read-only - - - MAJOR - Component major type - [3:0] - read-only - - - - - FP_PIDR4 - Provides CoreSight discovery information for the FP - 0x2FD0 - 0x00000004 - - - SIZE - See CoreSight Architecture Specification - [7:4] - read-only - - - DES_2 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - FP_PIDR5 - Provides CoreSight discovery information for the FP - 0x2FD4 - 0x00000000 - - - FP_PIDR5 - [31:0] - read-write - - - - - FP_PIDR6 - Provides CoreSight discovery information for the FP - 0x2FD8 - 0x00000000 - - - FP_PIDR6 - [31:0] - read-write - - - - - FP_PIDR7 - Provides CoreSight discovery information for the FP - 0x2FDC - 0x00000000 - - - FP_PIDR7 - [31:0] - read-write - - - - - FP_PIDR0 - Provides CoreSight discovery information for the FP - 0x2FE0 - 0x00000021 - - - PART_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - FP_PIDR1 - Provides CoreSight discovery information for the FP - 0x2FE4 - 0x000000BD - - - DES_0 - See CoreSight Architecture Specification - [7:4] - read-only - - - PART_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - FP_PIDR2 - Provides CoreSight discovery information for the FP - 0x2FE8 - 0x0000000B - - - REVISION - See CoreSight Architecture Specification - [7:4] - read-only - - - JEDEC - See CoreSight Architecture Specification - [3:3] - read-only - - - DES_1 - See CoreSight Architecture Specification - [2:0] - read-only - - - - - FP_PIDR3 - Provides CoreSight discovery information for the FP - 0x2FEC - 0x00000000 - - - REVAND - See CoreSight Architecture Specification - [7:4] - read-only - - - CMOD - See CoreSight Architecture Specification - [3:0] - read-only - - - - - FP_CIDR0 - Provides CoreSight discovery information for the FP - 0x2FF0 - 0x0000000D - - - PRMBL_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - FP_CIDR1 - Provides CoreSight discovery information for the FP - 0x2FF4 - 0x00000090 - - - CLASS - See CoreSight Architecture Specification - [7:4] - read-only - - - PRMBL_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - FP_CIDR2 - Provides CoreSight discovery information for the FP - 0x2FF8 - 0x00000005 - - - PRMBL_2 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - FP_CIDR3 - Provides CoreSight discovery information for the FP - 0x2FFC - 0x000000B1 - - - PRMBL_3 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - ICTR - Provides information about the interrupt controller - 0xE004 - 0x00000001 - - - INTLINESNUM - Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4Γ—INTLINESNUM - [3:0] - read-only - - - - - ACTLR - Provides IMPLEMENTATION DEFINED configuration and control options - 0xE008 - 0x00000000 - - - EXTEXCLALL - External Exclusives Allowed with no MPU - [29:29] - read-write - - - DISITMATBFLUSH - Disable ATB Flush - [12:12] - read-write - - - FPEXCODIS - Disable FPU exception outputs - [10:10] - read-write - - - DISOOFP - Disable out-of-order FP instruction completion - [9:9] - read-write - - - DISFOLD - Disable dual-issue. - [2:2] - read-write - - - DISMCYCINT - Disable dual-issue. - [0:0] - read-write - - - - - SYST_CSR - Use the SysTick Control and Status Register to enable the SysTick features. - 0xE010 - 0x00000000 - - - COUNTFLAG - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. - [16:16] - read-only - - - CLKSOURCE - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. - Selects the SysTick timer clock source: - 0 = External reference clock. - 1 = Processor clock. - [2:2] - read-write - - - TICKINT - Enables SysTick exception request: - 0 = Counting down to zero does not assert the SysTick exception request. - 1 = Counting down to zero to asserts the SysTick exception request. - [1:1] - read-write - - - ENABLE - Enable SysTick counter: - 0 = Counter disabled. - 1 = Counter enabled. - [0:0] - read-write - - - - - SYST_RVR - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. - To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. - 0xE014 - 0x00000000 - - - RELOAD - Value to load into the SysTick Current Value Register when the counter reaches 0. - [23:0] - read-write - - - - - SYST_CVR - Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. - 0xE018 - 0x00000000 - - - CURRENT - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. - [23:0] - read-write - - - - - SYST_CALIB - Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. - 0xE01C - 0x00000000 - - - NOREF - If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. - [31:31] - read-only - - - SKEW - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). - [30:30] - read-only - - - TENMS - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. - [23:0] - read-only - - - - - NVIC_ISER0 - Enables or reads the enabled state of each group of 32 interrupts - 0xE100 - 0x00000000 - - - SETENA - For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled - [31:0] - read-write - - - - - NVIC_ISER1 - Enables or reads the enabled state of each group of 32 interrupts - 0xE104 - 0x00000000 - - - SETENA - For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled - [31:0] - read-write - - - - - NVIC_ICER0 - Clears or reads the enabled state of each group of 32 interrupts - 0xE180 - 0x00000000 - - - CLRENA - For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled - [31:0] - read-write - - - - - NVIC_ICER1 - Clears or reads the enabled state of each group of 32 interrupts - 0xE184 - 0x00000000 - - - CLRENA - For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled - [31:0] - read-write - - - - - NVIC_ISPR0 - Enables or reads the pending state of each group of 32 interrupts - 0xE200 - 0x00000000 - - - SETPEND - For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending - [31:0] - read-write - - - - - NVIC_ISPR1 - Enables or reads the pending state of each group of 32 interrupts - 0xE204 - 0x00000000 - - - SETPEND - For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending - [31:0] - read-write - - - - - NVIC_ICPR0 - Clears or reads the pending state of each group of 32 interrupts - 0xE280 - 0x00000000 - - - CLRPEND - For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending - [31:0] - read-write - - - - - NVIC_ICPR1 - Clears or reads the pending state of each group of 32 interrupts - 0xE284 - 0x00000000 - - - CLRPEND - For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending - [31:0] - read-write - - - - - NVIC_IABR0 - For each group of 32 interrupts, shows the active state of each interrupt - 0xE300 - 0x00000000 - - - ACTIVE - For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m - [31:0] - read-write - - - - - NVIC_IABR1 - For each group of 32 interrupts, shows the active state of each interrupt - 0xE304 - 0x00000000 - - - ACTIVE - For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m - [31:0] - read-write - - - - - NVIC_ITNS0 - For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state - 0xE380 - 0x00000000 - - - ITNS - For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m - [31:0] - read-write - - - - - NVIC_ITNS1 - For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state - 0xE384 - 0x00000000 - - - ITNS - For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m - [31:0] - read-write - - - - - NVIC_IPR0 - Sets or reads interrupt priorities - 0xE400 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR1 - Sets or reads interrupt priorities - 0xE404 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR2 - Sets or reads interrupt priorities - 0xE408 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR3 - Sets or reads interrupt priorities - 0xE40C - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR4 - Sets or reads interrupt priorities - 0xE410 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR5 - Sets or reads interrupt priorities - 0xE414 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR6 - Sets or reads interrupt priorities - 0xE418 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR7 - Sets or reads interrupt priorities - 0xE41C - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR8 - Sets or reads interrupt priorities - 0xE420 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR9 - Sets or reads interrupt priorities - 0xE424 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR10 - Sets or reads interrupt priorities - 0xE428 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR11 - Sets or reads interrupt priorities - 0xE42C - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR12 - Sets or reads interrupt priorities - 0xE430 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR13 - Sets or reads interrupt priorities - 0xE434 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR14 - Sets or reads interrupt priorities - 0xE438 - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR15 - Sets or reads interrupt priorities - 0xE43C - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - CPUID - Provides identification information for the PE, including an implementer code for the device and a device ID number - 0xED00 - 0x411FD210 - - - IMPLEMENTER - This field must hold an implementer code that has been assigned by ARM - [31:24] - read-only - - - VARIANT - IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product - [23:20] - read-only - - - ARCHITECTURE - Defines the Architecture implemented by the PE - [19:16] - read-only - - - PARTNO - IMPLEMENTATION DEFINED primary part number for the device - [15:4] - read-only - - - REVISION - IMPLEMENTATION DEFINED revision number for the device - [3:0] - read-only - - - - - ICSR - Controls and provides status information for NMI, PendSV, SysTick and interrupts - 0xED04 - 0x00000000 - - - PENDNMISET - Indicates whether the NMI exception is pending - [31:31] - read-only - - - PENDNMICLR - Allows the NMI exception pend state to be cleared - [30:30] - read-write - - - PENDSVSET - Indicates whether the PendSV `FTSSS exception is pending - [28:28] - read-only - - - PENDSVCLR - Allows the PendSV exception pend state to be cleared `FTSSS - [27:27] - read-write - - - PENDSTSET - Indicates whether the SysTick `FTSSS exception is pending - [26:26] - read-only - - - PENDSTCLR - Allows the SysTick exception pend state to be cleared `FTSSS - [25:25] - read-write - - - STTNS - Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure - [24:24] - read-write - - - ISRPREEMPT - Indicates whether a pending exception will be serviced on exit from debug halt state - [23:23] - read-only - - - ISRPENDING - Indicates whether an external interrupt, generated by the NVIC, is pending - [22:22] - read-only - - - VECTPENDING - The exception number of the highest priority pending and enabled interrupt - [20:12] - read-only - - - RETTOBASE - In Handler mode, indicates whether there is more than one active exception - [11:11] - read-only - - - VECTACTIVE - The exception number of the current executing exception - [8:0] - read-only - - - - - VTOR - The VTOR indicates the offset of the vector table base address from memory address 0x00000000. - 0xED08 - 0x00000000 - - - TBLOFF - Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memory map. - [31:7] - read-write - - - - - AIRCR - Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. - 0xED0C - 0x00000000 - - - VECTKEY - Register key: - Reads as Unknown - On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. - [31:16] - read-write - - - ENDIANESS - Data endianness implemented: - 0 = Little-endian. - [15:15] - read-only - - - PRIS - Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. - 0 Priority ranges of Secure and Non-secure exceptions are identical. - 1 Non-secure exceptions are de-prioritized. - [14:14] - read-write - - - BFHFNMINS - BusFault, HardFault, and NMI Non-secure enable. - 0 BusFault, HardFault, and NMI are Secure. - 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. - [13:13] - read-write - - - PRIGROUP - Interrupt priority grouping field. This field determines the split of group priority from subpriority. - See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en - [10:8] - read-write - - - SYSRESETREQS - System reset request, Secure state only. - 0 SYSRESETREQ functionality is available to both Security states. - 1 SYSRESETREQ functionality is only available to Secure state. - [3:3] - read-write - - - SYSRESETREQ - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. - [2:2] - read-write - - - VECTCLRACTIVE - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. - [1:1] - read-write - - - - - SCR - System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. - 0xED10 - 0x00000000 - - - SEVONPEND - Send Event on Pending bit: - 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. - 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. - When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the - processor is not waiting for an event, the event is registered and affects the next WFE. - The processor also wakes up on execution of an SEV instruction or an external event. - [4:4] - read-write - - - SLEEPDEEPS - 0 SLEEPDEEP is available to both security states - 1 SLEEPDEEP is only available to Secure state - [3:3] - read-write - - - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low power mode: - 0 = Sleep. - 1 = Deep sleep. - [2:2] - read-write - - - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode: - 0 = Do not sleep when returning to Thread mode. - 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. - Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. - [1:1] - read-write - - - - - CCR - Sets or returns configuration and control data - 0xED14 - 0x00000201 - - - BP - Enables program flow prediction `FTSSS - [18:18] - read-only - - - IC - This is a global enable bit for instruction caches in the selected Security state - [17:17] - read-only - - - DC - Enables data caching of all data accesses to Normal memory `FTSSS - [16:16] - read-only - - - STKOFHFNMIGN - Controls the effect of a stack limit violation while executing at a requested priority less than 0 - [10:10] - read-write - - - RES1 - Reserved, RES1 - [9:9] - read-only - - - BFHFNMIGN - Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 - [8:8] - read-write - - - DIV_0_TRP - Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero - [4:4] - read-write - - - UNALIGN_TRP - Controls the trapping of unaligned word or halfword accesses - [3:3] - read-write - - - USERSETMPEND - Determines whether unprivileged accesses are permitted to pend interrupts via the STIR - [1:1] - read-write - - - RES1_1 - Reserved, RES1 - [0:0] - read-only - - - - - SHPR1 - Sets or returns priority for system handlers 4 - 7 - 0xED18 - 0x00000000 - - - PRI_7_3 - Priority of system handler 7, SecureFault - [31:29] - read-write - - - PRI_6_3 - Priority of system handler 6, SecureFault - [23:21] - read-write - - - PRI_5_3 - Priority of system handler 5, SecureFault - [15:13] - read-write - - - PRI_4_3 - Priority of system handler 4, SecureFault - [7:5] - read-write - - - - - SHPR2 - Sets or returns priority for system handlers 8 - 11 - 0xED1C - 0x00000000 - - - PRI_11_3 - Priority of system handler 11, SecureFault - [31:29] - read-write - - - PRI_10 - Reserved, RES0 - [23:16] - read-only - - - PRI_9 - Reserved, RES0 - [15:8] - read-only - - - PRI_8 - Reserved, RES0 - [7:0] - read-only - - - - - SHPR3 - Sets or returns priority for system handlers 12 - 15 - 0xED20 - 0x00000000 - - - PRI_15_3 - Priority of system handler 15, SecureFault - [31:29] - read-write - - - PRI_14_3 - Priority of system handler 14, SecureFault - [23:21] - read-write - - - PRI_13 - Reserved, RES0 - [15:8] - read-only - - - PRI_12_3 - Priority of system handler 12, SecureFault - [7:5] - read-write - - - - - SHCSR - Provides access to the active and pending status of system exceptions - 0xED24 - 0x00000000 - - - HARDFAULTPENDED - `IAAMO the pending state of the HardFault exception `CTTSSS - [21:21] - read-write - - - SECUREFAULTPENDED - `IAAMO the pending state of the SecureFault exception - [20:20] - read-write - - - SECUREFAULTENA - `DW the SecureFault exception is enabled - [19:19] - read-write - - - USGFAULTENA - `DW the UsageFault exception is enabled `FTSSS - [18:18] - read-write - - - BUSFAULTENA - `DW the BusFault exception is enabled - [17:17] - read-write - - - MEMFAULTENA - `DW the MemManage exception is enabled `FTSSS - [16:16] - read-write - - - SVCALLPENDED - `IAAMO the pending state of the SVCall exception `FTSSS - [15:15] - read-write - - - BUSFAULTPENDED - `IAAMO the pending state of the BusFault exception - [14:14] - read-write - - - MEMFAULTPENDED - `IAAMO the pending state of the MemManage exception `FTSSS - [13:13] - read-write - - - USGFAULTPENDED - The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS - [12:12] - read-write - - - SYSTICKACT - `IAAMO the active state of the SysTick exception `FTSSS - [11:11] - read-write - - - PENDSVACT - `IAAMO the active state of the PendSV exception `FTSSS - [10:10] - read-write - - - MONITORACT - `IAAMO the active state of the DebugMonitor exception - [8:8] - read-write - - - SVCALLACT - `IAAMO the active state of the SVCall exception `FTSSS - [7:7] - read-write - - - NMIACT - `IAAMO the active state of the NMI exception - [5:5] - read-write - - - SECUREFAULTACT - `IAAMO the active state of the SecureFault exception - [4:4] - read-write - - - USGFAULTACT - `IAAMO the active state of the UsageFault exception `FTSSS - [3:3] - read-write - - - HARDFAULTACT - Indicates and allows limited modification of the active state of the HardFault exception `FTSSS - [2:2] - read-write - - - BUSFAULTACT - `IAAMO the active state of the BusFault exception - [1:1] - read-write - - - MEMFAULTACT - `IAAMO the active state of the MemManage exception `FTSSS - [0:0] - read-write - - - - - CFSR - Contains the three Configurable Fault Status Registers. - - 31:16 UFSR: Provides information on UsageFault exceptions - - 15:8 BFSR: Provides information on BusFault exceptions - - 7:0 MMFSR: Provides information on MemManage exceptions - 0xED28 - 0x00000000 - - - UFSR_DIVBYZERO - Sticky flag indicating whether an integer division by zero error has occurred - [25:25] - read-write - - - UFSR_UNALIGNED - Sticky flag indicating whether an unaligned access error has occurred - [24:24] - read-write - - - UFSR_STKOF - Sticky flag indicating whether a stack overflow error has occurred - [20:20] - read-write - - - UFSR_NOCP - Sticky flag indicating whether a coprocessor disabled or not present error has occurred - [19:19] - read-write - - - UFSR_INVPC - Sticky flag indicating whether an integrity check error has occurred - [18:18] - read-write - - - UFSR_INVSTATE - Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred - [17:17] - read-write - - - UFSR_UNDEFINSTR - Sticky flag indicating whether an undefined instruction error has occurred - [16:16] - read-write - - - BFSR_BFARVALID - Indicates validity of the contents of the BFAR register - [15:15] - read-write - - - BFSR_LSPERR - Records whether a BusFault occurred during FP lazy state preservation - [13:13] - read-write - - - BFSR_STKERR - Records whether a derived BusFault occurred during exception entry stacking - [12:12] - read-write - - - BFSR_UNSTKERR - Records whether a derived BusFault occurred during exception return unstacking - [11:11] - read-write - - - BFSR_IMPRECISERR - Records whether an imprecise data access error has occurred - [10:10] - read-write - - - BFSR_PRECISERR - Records whether a precise data access error has occurred - [9:9] - read-write - - - BFSR_IBUSERR - Records whether a BusFault on an instruction prefetch has occurred - [8:8] - read-write - - - MMFSR - Provides information on MemManage exceptions - [7:0] - read-write - - - - - HFSR - Shows the cause of any HardFaults - 0xED2C - 0x00000000 - - - DEBUGEVT - Indicates when a Debug event has occurred - [31:31] - read-write - - - FORCED - Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled - [30:30] - read-write - - - VECTTBL - Indicates when a fault has occurred because of a vector table read error on exception processing - [1:1] - read-write - - - - - DFSR - Shows which debug event occurred - 0xED30 - 0x00000000 - - - EXTERNAL - Sticky flag indicating whether an External debug request debug event has occurred - [4:4] - read-write - - - VCATCH - Sticky flag indicating whether a Vector catch debug event has occurred - [3:3] - read-write - - - DWTTRAP - Sticky flag indicating whether a Watchpoint debug event has occurred - [2:2] - read-write - - - BKPT - Sticky flag indicating whether a Breakpoint debug event has occurred - [1:1] - read-write - - - HALTED - Sticky flag indicating that a Halt request debug event or Step debug event has occurred - [0:0] - read-write - - - - - MMFAR - Shows the address of the memory location that caused an MPU fault - 0xED34 - 0x00000000 - - - ADDRESS - This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN - [31:0] - read-write - - - - - BFAR - Shows the address associated with a precise data access BusFault - 0xED38 - 0x00000000 - - - ADDRESS - This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN - [31:0] - read-write - - - - - ID_PFR0 - Gives top-level information about the instruction set supported by the PE - 0xED40 - 0x00000030 - - - STATE1 - T32 instruction set support - [7:4] - read-only - - - STATE0 - A32 instruction set support - [3:0] - read-only - - - - - ID_PFR1 - Gives information about the programmers' model and Extensions support - 0xED44 - 0x00000520 - - - MPROGMOD - Identifies support for the M-Profile programmers' model support - [11:8] - read-only - - - SECURITY - Identifies whether the Security Extension is implemented - [7:4] - read-only - - - - - ID_DFR0 - Provides top level information about the debug system - 0xED48 - 0x00200000 - - - MPROFDBG - Indicates the supported M-profile debug architecture - [23:20] - read-only - - - - - ID_AFR0 - Provides information about the IMPLEMENTATION DEFINED features of the PE - 0xED4C - 0x00000000 - - - IMPDEF3 - IMPLEMENTATION DEFINED meaning - [15:12] - read-only - - - IMPDEF2 - IMPLEMENTATION DEFINED meaning - [11:8] - read-only - - - IMPDEF1 - IMPLEMENTATION DEFINED meaning - [7:4] - read-only - - - IMPDEF0 - IMPLEMENTATION DEFINED meaning - [3:0] - read-only - - - - - ID_MMFR0 - Provides information about the implemented memory model and memory management support - 0xED50 - 0x00101F40 - - - AUXREG - Indicates support for Auxiliary Control Registers - [23:20] - read-only - - - TCM - Indicates support for tightly coupled memories (TCMs) - [19:16] - read-only - - - SHARELVL - Indicates the number of shareability levels implemented - [15:12] - read-only - - - OUTERSHR - Indicates the outermost shareability domain implemented - [11:8] - read-only - - - PMSA - Indicates support for the protected memory system architecture (PMSA) - [7:4] - read-only - - - - - ID_MMFR1 - Provides information about the implemented memory model and memory management support - 0xED54 - 0x00000000 - - - ID_MMFR1 - [31:0] - read-write - - - - - ID_MMFR2 - Provides information about the implemented memory model and memory management support - 0xED58 - 0x01000000 - - - WFISTALL - Indicates the support for Wait For Interrupt (WFI) stalling - [27:24] - read-only - - - - - ID_MMFR3 - Provides information about the implemented memory model and memory management support - 0xED5C - 0x00000000 - - - BPMAINT - Indicates the supported branch predictor maintenance - [11:8] - read-only - - - CMAINTSW - Indicates the supported cache maintenance operations by set/way - [7:4] - read-only - - - CMAINTVA - Indicates the supported cache maintenance operations by address - [3:0] - read-only - - - - - ID_ISAR0 - Provides information about the instruction set implemented by the PE - 0xED60 - 0x08092300 - - - DIVIDE - Indicates the supported Divide instructions - [27:24] - read-only - - - DEBUG - Indicates the implemented Debug instructions - [23:20] - read-only - - - COPROC - Indicates the supported Coprocessor instructions - [19:16] - read-only - - - CMPBRANCH - Indicates the supported combined Compare and Branch instructions - [15:12] - read-only - - - BITFIELD - Indicates the supported bit field instructions - [11:8] - read-only - - - BITCOUNT - Indicates the supported bit count instructions - [7:4] - read-only - - - - - ID_ISAR1 - Provides information about the instruction set implemented by the PE - 0xED64 - 0x05725000 - - - INTERWORK - Indicates the implemented Interworking instructions - [27:24] - read-only - - - IMMEDIATE - Indicates the implemented for data-processing instructions with long immediates - [23:20] - read-only - - - IFTHEN - Indicates the implemented If-Then instructions - [19:16] - read-only - - - EXTEND - Indicates the implemented Extend instructions - [15:12] - read-only - - - - - ID_ISAR2 - Provides information about the instruction set implemented by the PE - 0xED68 - 0x30173426 - - - REVERSAL - Indicates the implemented Reversal instructions - [31:28] - read-only - - - MULTU - Indicates the implemented advanced unsigned Multiply instructions - [23:20] - read-only - - - MULTS - Indicates the implemented advanced signed Multiply instructions - [19:16] - read-only - - - MULT - Indicates the implemented additional Multiply instructions - [15:12] - read-only - - - MULTIACCESSINT - Indicates the support for interruptible multi-access instructions - [11:8] - read-only - - - MEMHINT - Indicates the implemented Memory Hint instructions - [7:4] - read-only - - - LOADSTORE - Indicates the implemented additional load/store instructions - [3:0] - read-only - - - - - ID_ISAR3 - Provides information about the instruction set implemented by the PE - 0xED6C - 0x07895729 - - - TRUENOP - Indicates the implemented true NOP instructions - [27:24] - read-only - - - T32COPY - Indicates the support for T32 non flag-setting MOV instructions - [23:20] - read-only - - - TABBRANCH - Indicates the implemented Table Branch instructions - [19:16] - read-only - - - SYNCHPRIM - Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions - [15:12] - read-only - - - SVC - Indicates the implemented SVC instructions - [11:8] - read-only - - - SIMD - Indicates the implemented SIMD instructions - [7:4] - read-only - - - SATURATE - Indicates the implemented saturating instructions - [3:0] - read-only - - - - - ID_ISAR4 - Provides information about the instruction set implemented by the PE - 0xED70 - 0x01310132 - - - PSR_M - Indicates the implemented M profile instructions to modify the PSRs - [27:24] - read-only - - - SYNCPRIM_FRAC - Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions - [23:20] - read-only - - - BARRIER - Indicates the implemented Barrier instructions - [19:16] - read-only - - - WRITEBACK - Indicates the support for writeback addressing modes - [11:8] - read-only - - - WITHSHIFTS - Indicates the support for writeback addressing modes - [7:4] - read-only - - - UNPRIV - Indicates the implemented unprivileged instructions - [3:0] - read-only - - - - - ID_ISAR5 - Provides information about the instruction set implemented by the PE - 0xED74 - 0x00000000 - - - ID_ISAR5 - [31:0] - read-write - - - - - CTR - Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero. - 0xED7C - 0x8000C000 - - - RES1 - Reserved, RES1 - [31:31] - read-only - - - CWG - Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified - [27:24] - read-only - - - ERG - Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions - [23:20] - read-only - - - DMINLINE - Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE - [19:16] - read-only - - - RES1_1 - Reserved, RES1 - [15:14] - read-only - - - IMINLINE - Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE - [3:0] - read-only - - - - - CPACR - Specifies the access privileges for coprocessors and the FP Extension - 0xED88 - 0x00000000 - - - CP11 - The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN - [23:22] - read-write - - - CP10 - Defines the access rights for the floating-point functionality - [21:20] - read-write - - - CP7 - Controls access privileges for coprocessor 7 - [15:14] - read-write - - - CP6 - Controls access privileges for coprocessor 6 - [13:12] - read-write - - - CP5 - Controls access privileges for coprocessor 5 - [11:10] - read-write - - - CP4 - Controls access privileges for coprocessor 4 - [9:8] - read-write - - - CP3 - Controls access privileges for coprocessor 3 - [7:6] - read-write - - - CP2 - Controls access privileges for coprocessor 2 - [5:4] - read-write - - - CP1 - Controls access privileges for coprocessor 1 - [3:2] - read-write - - - CP0 - Controls access privileges for coprocessor 0 - [1:0] - read-write - - - - - NSACR - Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 - 0xED8C - 0x00000000 - - - CP11 - Enables Non-secure access to the Floating-point Extension - [11:11] - read-write - - - CP10 - Enables Non-secure access to the Floating-point Extension - [10:10] - read-write - - - CP7 - Enables Non-secure access to coprocessor CP7 - [7:7] - read-write - - - CP6 - Enables Non-secure access to coprocessor CP6 - [6:6] - read-write - - - CP5 - Enables Non-secure access to coprocessor CP5 - [5:5] - read-write - - - CP4 - Enables Non-secure access to coprocessor CP4 - [4:4] - read-write - - - CP3 - Enables Non-secure access to coprocessor CP3 - [3:3] - read-write - - - CP2 - Enables Non-secure access to coprocessor CP2 - [2:2] - read-write - - - CP1 - Enables Non-secure access to coprocessor CP1 - [1:1] - read-write - - - CP0 - Enables Non-secure access to coprocessor CP0 - [0:0] - read-write - - - - - MPU_TYPE - The MPU Type Register indicates how many regions the MPU `FTSSS supports - 0xED90 - 0x00000800 - - - DREGION - Number of regions supported by the MPU - [15:8] - read-only - - - SEPARATE - Indicates support for separate instructions and data address regions - [0:0] - read-only - - - - - MPU_CTRL - Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 - 0xED94 - 0x00000000 - - - PRIVDEFENA - Controls whether the default memory map is enabled for privileged software - [2:2] - read-write - - - HFNMIENA - Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 - [1:1] - read-write - - - ENABLE - Enables the MPU - [0:0] - read-write - - - - - MPU_RNR - Selects the region currently accessed by MPU_RBAR and MPU_RLAR - 0xED98 - 0x00000000 - - - REGION - Indicates the memory region accessed by MPU_RBAR and MPU_RLAR - [2:0] - read-write - - - - - MPU_RBAR - Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS - 0xED9C - 0x00000000 - - - BASE - Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against - [31:5] - read-write - - - SH - Defines the Shareability domain of this region for Normal memory - [4:3] - read-write - - - AP - Defines the access permissions for this region - [2:1] - read-write - - - XN - Defines whether code can be executed from this region - [0:0] - read-write - - - - - MPU_RLAR - Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS - 0xEDA0 - 0x00000000 - - - LIMIT - Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against - [31:5] - read-write - - - ATTRINDX - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields - [3:1] - read-write - - - EN - Region enable - [0:0] - read-write - - - - - MPU_RBAR_A1 - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS - 0xEDA4 - 0x00000000 - - - BASE - Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against - [31:5] - read-write - - - SH - Defines the Shareability domain of this region for Normal memory - [4:3] - read-write - - - AP - Defines the access permissions for this region - [2:1] - read-write - - - XN - Defines whether code can be executed from this region - [0:0] - read-write - - - - - MPU_RLAR_A1 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS - 0xEDA8 - 0x00000000 - - - LIMIT - Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against - [31:5] - read-write - - - ATTRINDX - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields - [3:1] - read-write - - - EN - Region enable - [0:0] - read-write - - - - - MPU_RBAR_A2 - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS - 0xEDAC - 0x00000000 - - - BASE - Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against - [31:5] - read-write - - - SH - Defines the Shareability domain of this region for Normal memory - [4:3] - read-write - - - AP - Defines the access permissions for this region - [2:1] - read-write - - - XN - Defines whether code can be executed from this region - [0:0] - read-write - - - - - MPU_RLAR_A2 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS - 0xEDB0 - 0x00000000 - - - LIMIT - Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against - [31:5] - read-write - - - ATTRINDX - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields - [3:1] - read-write - - - EN - Region enable - [0:0] - read-write - - - - - MPU_RBAR_A3 - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS - 0xEDB4 - 0x00000000 - - - BASE - Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against - [31:5] - read-write - - - SH - Defines the Shareability domain of this region for Normal memory - [4:3] - read-write - - - AP - Defines the access permissions for this region - [2:1] - read-write - - - XN - Defines whether code can be executed from this region - [0:0] - read-write - - - - - MPU_RLAR_A3 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS - 0xEDB8 - 0x00000000 - - - LIMIT - Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against - [31:5] - read-write - - - ATTRINDX - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields - [3:1] - read-write - - - EN - Region enable - [0:0] - read-write - - - - - MPU_MAIR0 - Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values - 0xEDC0 - 0x00000000 - - - ATTR3 - Memory attribute encoding for MPU regions with an AttrIndex of 3 - [31:24] - read-write - - - ATTR2 - Memory attribute encoding for MPU regions with an AttrIndex of 2 - [23:16] - read-write - - - ATTR1 - Memory attribute encoding for MPU regions with an AttrIndex of 1 - [15:8] - read-write - - - ATTR0 - Memory attribute encoding for MPU regions with an AttrIndex of 0 - [7:0] - read-write - - - - - MPU_MAIR1 - Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values - 0xEDC4 - 0x00000000 - - - ATTR7 - Memory attribute encoding for MPU regions with an AttrIndex of 7 - [31:24] - read-write - - - ATTR6 - Memory attribute encoding for MPU regions with an AttrIndex of 6 - [23:16] - read-write - - - ATTR5 - Memory attribute encoding for MPU regions with an AttrIndex of 5 - [15:8] - read-write - - - ATTR4 - Memory attribute encoding for MPU regions with an AttrIndex of 4 - [7:0] - read-write - - - - - SAU_CTRL - Allows enabling of the Security Attribution Unit - 0xEDD0 - 0x00000000 - - - ALLNS - When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure - [1:1] - read-write - - - ENABLE - Enables the SAU - [0:0] - read-write - - - - - SAU_TYPE - Indicates the number of regions implemented by the Security Attribution Unit - 0xEDD4 - 0x00000008 - - - SREGION - The number of implemented SAU regions - [7:0] - read-only - - - - - SAU_RNR - Selects the region currently accessed by SAU_RBAR and SAU_RLAR - 0xEDD8 - 0x00000000 - - - REGION - Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR - [7:0] - read-write - - - - - SAU_RBAR - Provides indirect read and write access to the base address of the currently selected SAU region - 0xEDDC - 0x00000000 - - - BADDR - Holds bits [31:5] of the base address for the selected SAU region - [31:5] - read-write - - - - - SAU_RLAR - Provides indirect read and write access to the limit address of the currently selected SAU region - 0xEDE0 - 0x00000000 - - - LADDR - Holds bits [31:5] of the limit address for the selected SAU region - [31:5] - read-write - - - NSC - Controls whether Non-secure state is permitted to execute an SG instruction from this region - [1:1] - read-write - - - ENABLE - SAU region enable - [0:0] - read-write - - - - - SFSR - Provides information about any security related faults - 0xEDE4 - 0x00000000 - - - LSERR - Sticky flag indicating that an error occurred during lazy state activation or deactivation - [7:7] - read-write - - - SFARVALID - This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault - [6:6] - read-write - - - LSPERR - Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state - [5:5] - read-write - - - INVTRAN - Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory - [4:4] - read-write - - - AUVIOL - Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR - [3:3] - read-write - - - INVER - This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state - [2:2] - read-write - - - INVIS - This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation - [1:1] - read-write - - - INVEP - This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set - [0:0] - read-write - - - - - SFAR - Shows the address of the memory location that caused a Security violation - 0xEDE8 - 0x00000000 - - - ADDRESS - The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state - [31:0] - read-write - - - - - DHCSR - Controls halting debug - 0xEDF0 - 0x00000000 - - - S_RESTART_ST - Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request - [26:26] - read-only - - - S_RESET_ST - Indicates whether the PE has been reset since the last read of the DHCSR - [25:25] - read-only - - - S_RETIRE_ST - Set to 1 every time the PE retires one of more instructions - [24:24] - read-only - - - S_SDE - Indicates whether Secure invasive debug is allowed - [20:20] - read-only - - - S_LOCKUP - Indicates whether the PE is in Lockup state - [19:19] - read-only - - - S_SLEEP - Indicates whether the PE is sleeping - [18:18] - read-only - - - S_HALT - Indicates whether the PE is in Debug state - [17:17] - read-only - - - S_REGRDY - Handshake flag to transfers through the DCRDR - [16:16] - read-only - - - C_SNAPSTALL - Allow imprecise entry to Debug state - [5:5] - read-write - - - C_MASKINTS - When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts - [3:3] - read-write - - - C_STEP - Enable single instruction step - [2:2] - read-write - - - C_HALT - PE enter Debug state halt request - [1:1] - read-write - - - C_DEBUGEN - Enable Halting debug - [0:0] - read-write - - - - - DCRSR - With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer - 0xEDF4 - 0x00000000 - - - REGWNR - Specifies the access type for the transfer - [16:16] - read-write - - - REGSEL - Specifies the general-purpose register, special-purpose register, or FP register to transfer - [6:0] - read-write - - - - - DCRDR - With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE - 0xEDF8 - 0x00000000 - - - DBGTMP - Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers - [31:0] - read-write - - - - - DEMCR - Manages vector catch behavior and DebugMonitor handling when debugging - 0xEDFC - 0x00000000 - - - TRCENA - Global enable for all DWT and ITM features - [24:24] - read-write - - - SDME - Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state - [20:20] - read-only - - - MON_REQ - DebugMonitor semaphore bit - [19:19] - read-write - - - MON_STEP - Enable DebugMonitor stepping - [18:18] - read-write - - - MON_PEND - Sets or clears the pending state of the DebugMonitor exception - [17:17] - read-write - - - MON_EN - Enable the DebugMonitor exception - [16:16] - read-write - - - VC_SFERR - SecureFault exception halting debug vector catch enable - [11:11] - read-write - - - VC_HARDERR - HardFault exception halting debug vector catch enable - [10:10] - read-write - - - VC_INTERR - Enable halting debug vector catch for faults during exception entry and return - [9:9] - read-write - - - VC_BUSERR - BusFault exception halting debug vector catch enable - [8:8] - read-write - - - VC_STATERR - Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception - [7:7] - read-write - - - VC_CHKERR - Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error - [6:6] - read-write - - - VC_NOCPERR - Enable halting debug trap on a UsageFault caused by an access to a coprocessor - [5:5] - read-write - - - VC_MMERR - Enable halting debug trap on a MemManage exception - [4:4] - read-write - - - VC_CORERESET - Enable Reset Vector Catch. This causes a warm reset to halt a running system - [0:0] - read-write - - - - - DSCSR - Provides control and status information for Secure debug - 0xEE08 - 0x00000000 - - - CDSKEY - Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero - [17:17] - read-write - - - CDS - This field indicates the current Security state of the processor - [16:16] - read-write - - - SBRSEL - If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger - [1:1] - read-write - - - SBRSELEN - Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger - [0:0] - read-write - - - - - STIR - Provides a mechanism for software to generate an interrupt - 0xEF00 - 0x00000000 - - - INTID - Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16) - [8:0] - read-write - - - - - FPCCR - Holds control data for the Floating-point extension - 0xEF34 - 0x20000472 - - - ASPEN - When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1 - [31:31] - read-write - - - LSPEN - Enables lazy context save of floating-point state - [30:30] - read-write - - - LSPENS - This bit controls whether the LSPEN bit is writeable from the Non-secure state - [29:29] - read-write - - - CLRONRET - Clear floating-point caller saved registers on exception return - [28:28] - read-write - - - CLRONRETS - This bit controls whether the CLRONRET bit is writeable from the Non-secure state - [27:27] - read-write - - - TS - Treat floating-point registers as Secure enable - [26:26] - read-write - - - UFRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending - [10:10] - read-write - - - SPLIMVIOL - This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior - [9:9] - read-write - - - MONRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending - [8:8] - read-write - - - SFRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state - [7:7] - read-write - - - BFRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending - [6:6] - read-write - - - MMRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending - [5:5] - read-write - - - HFRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending - [4:4] - read-write - - - THREAD - Indicates the PE mode when it allocated the floating-point stack frame - [3:3] - read-write - - - S - Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed - [2:2] - read-write - - - USER - Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame - [1:1] - read-write - - - LSPACT - Indicates whether lazy preservation of the floating-point state is active - [0:0] - read-write - - - - - FPCAR - Holds the location of the unpopulated floating-point register space allocated on an exception stack frame - 0xEF38 - 0x00000000 - - - ADDRESS - The location of the unpopulated floating-point register space allocated on an exception stack frame - [31:3] - read-write - - - - - FPDSCR - Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context - 0xEF3C - 0x00000000 - - - AHP - Default value for FPSCR.AHP - [26:26] - read-write - - - DN - Default value for FPSCR.DN - [25:25] - read-write - - - FZ - Default value for FPSCR.FZ - [24:24] - read-write - - - RMODE - Default value for FPSCR.RMode - [23:22] - read-write - - - - - MVFR0 - Describes the features provided by the Floating-point Extension - 0xEF40 - 0x60540601 - - - FPROUND - Indicates the rounding modes supported by the FP Extension - [31:28] - read-only - - - FPSQRT - Indicates the support for FP square root operations - [23:20] - read-only - - - FPDIVIDE - Indicates the support for FP divide operations - [19:16] - read-only - - - FPDP - Indicates support for FP double-precision operations - [11:8] - read-only - - - FPSP - Indicates support for FP single-precision operations - [7:4] - read-only - - - SIMDREG - Indicates size of FP register file - [3:0] - read-only - - - - - MVFR1 - Describes the features provided by the Floating-point Extension - 0xEF44 - 0x85000089 - - - FMAC - Indicates whether the FP Extension implements the fused multiply accumulate instructions - [31:28] - read-only - - - FPHP - Indicates whether the FP Extension implements half-precision FP conversion instructions - [27:24] - read-only - - - FPDNAN - Indicates whether the FP hardware implementation supports NaN propagation - [7:4] - read-only - - - FPFTZ - Indicates whether subnormals are always flushed-to-zero - [3:0] - read-only - - - - - MVFR2 - Describes the features provided by the Floating-point Extension - 0xEF48 - 0x00000060 - - - FPMISC - Indicates support for miscellaneous FP features - [7:4] - read-only - - - - - DDEVARCH - Provides CoreSight discovery information for the SCS - 0xEFBC - 0x47702A04 - - - ARCHITECT - Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. - [31:21] - read-only - - - PRESENT - Defines that the DEVARCH register is present - [20:20] - read-only - - - REVISION - Defines the architecture revision of the component - [19:16] - read-only - - - ARCHVER - Defines the architecture version of the component - [15:12] - read-only - - - ARCHPART - Defines the architecture of the component - [11:0] - read-only - - - - - DDEVTYPE - Provides CoreSight discovery information for the SCS - 0xEFCC - 0x00000000 - - - SUB - Component sub-type - [7:4] - read-only - - - MAJOR - CoreSight major type - [3:0] - read-only - - - - - DPIDR4 - Provides CoreSight discovery information for the SCS - 0xEFD0 - 0x00000004 - - - SIZE - See CoreSight Architecture Specification - [7:4] - read-only - - - DES_2 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DPIDR5 - Provides CoreSight discovery information for the SCS - 0xEFD4 - 0x00000000 - - - DPIDR5 - [31:0] - read-write - - - - - DPIDR6 - Provides CoreSight discovery information for the SCS - 0xEFD8 - 0x00000000 - - - DPIDR6 - [31:0] - read-write - - - - - DPIDR7 - Provides CoreSight discovery information for the SCS - 0xEFDC - 0x00000000 - - - DPIDR7 - [31:0] - read-write - - - - - DPIDR0 - Provides CoreSight discovery information for the SCS - 0xEFE0 - 0x00000021 - - - PART_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DPIDR1 - Provides CoreSight discovery information for the SCS - 0xEFE4 - 0x000000BD - - - DES_0 - See CoreSight Architecture Specification - [7:4] - read-only - - - PART_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DPIDR2 - Provides CoreSight discovery information for the SCS - 0xEFE8 - 0x0000000B - - - REVISION - See CoreSight Architecture Specification - [7:4] - read-only - - - JEDEC - See CoreSight Architecture Specification - [3:3] - read-only - - - DES_1 - See CoreSight Architecture Specification - [2:0] - read-only - - - - - DPIDR3 - Provides CoreSight discovery information for the SCS - 0xEFEC - 0x00000000 - - - REVAND - See CoreSight Architecture Specification - [7:4] - read-only - - - CMOD - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DCIDR0 - Provides CoreSight discovery information for the SCS - 0xEFF0 - 0x0000000D - - - PRMBL_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DCIDR1 - Provides CoreSight discovery information for the SCS - 0xEFF4 - 0x00000090 - - - CLASS - See CoreSight Architecture Specification - [7:4] - read-only - - - PRMBL_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DCIDR2 - Provides CoreSight discovery information for the SCS - 0xEFF8 - 0x00000005 - - - PRMBL_2 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DCIDR3 - Provides CoreSight discovery information for the SCS - 0xEFFC - 0x000000B1 - - - PRMBL_3 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - TRCPRGCTLR - Programming Control Register - 0x41004 - 0x00000000 - - - EN - Trace Unit Enable - [0:0] - read-write - - - - - TRCSTATR - The TRCSTATR indicates the ETM-Teal status - 0x4100C - 0x00000000 - - - PMSTABLE - Indicates whether the ETM-Teal registers are stable and can be read - [1:1] - read-only - - - IDLE - Indicates that the trace unit is inactive - [0:0] - read-only - - - - - TRCCONFIGR - The TRCCONFIGR sets the basic tracing options for the trace unit - 0x41010 - 0x00000000 - - - RS - Return stack enable - [12:12] - read-write - - - TS - Global timestamp tracing - [11:11] - read-write - - - COND - Conditional instruction tracing - [10:5] - read-write - - - CCI - Cycle counting in instruction trace - [4:4] - read-write - - - BB - Branch broadcast mode - [3:3] - read-write - - - - - TRCEVENTCTL0R - The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. - 0x41020 - 0x00000000 - - - TYPE1 - Selects the resource type for event 1 - [15:15] - read-write - - - SEL1 - Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0] - [10:8] - read-write - - - TYPE0 - Selects the resource type for event 0 - [7:7] - read-write - - - SEL0 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] - [2:0] - read-write - - - - - TRCEVENTCTL1R - The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave - 0x41024 - 0x00000000 - - - LPOVERRIDE - Low power state behavior override - [12:12] - read-write - - - ATB - ATB enabled - [11:11] - read-write - - - INSTEN1 - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs - [1:1] - read-write - - - INSTEN0 - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs - [0:0] - read-write - - - - - TRCSTALLCTLR - The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow - 0x4102C - 0x00000000 - - - INSTPRIORITY - Reserved, RES0 - [10:10] - read-only - - - ISTALL - Stall processor based on instruction trace buffer space - [8:8] - read-write - - - LEVEL - Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow - [3:2] - read-write - - - - - TRCTSCTLR - The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream - 0x41030 - 0x00000000 - - - TYPE0 - Selects the resource type for event 0 - [7:7] - read-write - - - SEL0 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] - [1:0] - read-write - - - - - TRCSYNCPR - The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two - 0x41034 - 0x0000000A - - - PERIOD - Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes - [4:0] - read-only - - - - - TRCCCCTLR - The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets - 0x41038 - 0x00000000 - - - THRESHOLD - Instruction trace cycle count threshold - [11:0] - read-write - - - - - TRCVICTLR - The TRCVICTLR controls instruction trace filtering - 0x41080 - 0x00000000 - - - EXLEVEL_S3 - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level - [19:19] - read-write - - - EXLEVEL_S0 - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level - [16:16] - read-write - - - TRCERR - Selects whether a system error exception must always be traced - [11:11] - read-write - - - TRCRESET - Selects whether a reset exception must always be traced - [10:10] - read-write - - - SSSTATUS - Indicates the current status of the start/stop logic - [9:9] - read-write - - - TYPE0 - Selects the resource type for event 0 - [7:7] - read-write - - - SEL0 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] - [1:0] - read-write - - - - - TRCCNTRLDVR0 - The TRCCNTRLDVR defines the reload value for the reduced function counter - 0x41140 - 0x00000000 - - - VALUE - Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs - [15:0] - read-write - - - - - TRCIDR8 - TRCIDR8 - 0x41180 - 0x00000000 - - - MAXSPEC - reads as `ImpDef - [31:0] - read-only - - - - - TRCIDR9 - TRCIDR9 - 0x41184 - 0x00000000 - - - NUMP0KEY - reads as `ImpDef - [31:0] - read-only - - - - - TRCIDR10 - TRCIDR10 - 0x41188 - 0x00000000 - - - NUMP1KEY - reads as `ImpDef - [31:0] - read-only - - - - - TRCIDR11 - TRCIDR11 - 0x4118C - 0x00000000 - - - NUMP1SPC - reads as `ImpDef - [31:0] - read-only - - - - - TRCIDR12 - TRCIDR12 - 0x41190 - 0x00000001 - - - NUMCONDKEY - reads as `ImpDef - [31:0] - read-only - - - - - TRCIDR13 - TRCIDR13 - 0x41194 - 0x00000000 - - - NUMCONDSPC - reads as `ImpDef - [31:0] - read-only - - - - - TRCIMSPEC - The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided - 0x411C0 - 0x00000000 - - - SUPPORT - Reserved, RES0 - [3:0] - read-only - - - - - TRCIDR0 - TRCIDR0 - 0x411E0 - 0x280006E1 - - - COMMOPT - reads as `ImpDef - [29:29] - read-only - - - TSSIZE - reads as `ImpDef - [28:24] - read-only - - - TRCEXDATA - reads as `ImpDef - [17:17] - read-only - - - QSUPP - reads as `ImpDef - [16:15] - read-only - - - QFILT - reads as `ImpDef - [14:14] - read-only - - - CONDTYPE - reads as `ImpDef - [13:12] - read-only - - - NUMEVENT - reads as `ImpDef - [11:10] - read-only - - - RETSTACK - reads as `ImpDef - [9:9] - read-only - - - TRCCCI - reads as `ImpDef - [7:7] - read-only - - - TRCCOND - reads as `ImpDef - [6:6] - read-only - - - TRCBB - reads as `ImpDef - [5:5] - read-only - - - TRCDATA - reads as `ImpDef - [4:3] - read-only - - - INSTP0 - reads as `ImpDef - [2:1] - read-only - - - RES1 - Reserved, RES1 - [0:0] - read-only - - - - - TRCIDR1 - TRCIDR1 - 0x411E4 - 0x4100F421 - - - DESIGNER - reads as `ImpDef - [31:24] - read-only - - - RES1 - Reserved, RES1 - [15:12] - read-only - - - TRCARCHMAJ - reads as 0b0100 - [11:8] - read-only - - - TRCARCHMIN - reads as 0b0000 - [7:4] - read-only - - - REVISION - reads as `ImpDef - [3:0] - read-only - - - - - TRCIDR2 - TRCIDR2 - 0x411E8 - 0x00000004 - - - CCSIZE - reads as `ImpDef - [28:25] - read-only - - - DVSIZE - reads as `ImpDef - [24:20] - read-only - - - DASIZE - reads as `ImpDef - [19:15] - read-only - - - VMIDSIZE - reads as `ImpDef - [14:10] - read-only - - - CIDSIZE - reads as `ImpDef - [9:5] - read-only - - - IASIZE - reads as `ImpDef - [4:0] - read-only - - - - - TRCIDR3 - TRCIDR3 - 0x411EC - 0x0F090004 - - - NOOVERFLOW - reads as `ImpDef - [31:31] - read-only - - - NUMPROC - reads as `ImpDef - [30:28] - read-only - - - SYSSTALL - reads as `ImpDef - [27:27] - read-only - - - STALLCTL - reads as `ImpDef - [26:26] - read-only - - - SYNCPR - reads as `ImpDef - [25:25] - read-only - - - TRCERR - reads as `ImpDef - [24:24] - read-only - - - EXLEVEL_NS - reads as `ImpDef - [23:20] - read-only - - - EXLEVEL_S - reads as `ImpDef - [19:16] - read-only - - - CCITMIN - reads as `ImpDef - [11:0] - read-only - - - - - TRCIDR4 - TRCIDR4 - 0x411F0 - 0x00114000 - - - NUMVMIDC - reads as `ImpDef - [31:28] - read-only - - - NUMCIDC - reads as `ImpDef - [27:24] - read-only - - - NUMSSCC - reads as `ImpDef - [23:20] - read-only - - - NUMRSPAIR - reads as `ImpDef - [19:16] - read-only - - - NUMPC - reads as `ImpDef - [15:12] - read-only - - - SUPPDAC - reads as `ImpDef - [8:8] - read-only - - - NUMDVC - reads as `ImpDef - [7:4] - read-only - - - NUMACPAIRS - reads as `ImpDef - [3:0] - read-only - - - - - TRCIDR5 - TRCIDR5 - 0x411F4 - 0x90C70004 - - - REDFUNCNTR - reads as `ImpDef - [31:31] - read-only - - - NUMCNTR - reads as `ImpDef - [30:28] - read-only - - - NUMSEQSTATE - reads as `ImpDef - [27:25] - read-only - - - LPOVERRIDE - reads as `ImpDef - [23:23] - read-only - - - ATBTRIG - reads as `ImpDef - [22:22] - read-only - - - TRACEIDSIZE - reads as 0x07 - [21:16] - read-only - - - NUMEXTINSEL - reads as `ImpDef - [11:9] - read-only - - - NUMEXTIN - reads as `ImpDef - [8:0] - read-only - - - - - TRCIDR6 - TRCIDR6 - 0x411F8 - 0x00000000 - - - TRCIDR6 - [31:0] - read-write - - - - - TRCIDR7 - TRCIDR7 - 0x411FC - 0x00000000 - - - TRCIDR7 - [31:0] - read-write - - - - - TRCRSCTLR2 - The TRCRSCTLR controls the trace resources - 0x41208 - 0x00000000 - - - PAIRINV - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors - [21:21] - read-write - - - INV - Inverts the selected resources - [20:20] - read-write - - - GROUP - Selects a group of resource - [18:16] - read-write - - - SELECT - Selects one or more resources from the wanted group. One bit is provided per resource from the group - [7:0] - read-write - - - - - TRCRSCTLR3 - The TRCRSCTLR controls the trace resources - 0x4120C - 0x00000000 - - - PAIRINV - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors - [21:21] - read-write - - - INV - Inverts the selected resources - [20:20] - read-write - - - GROUP - Selects a group of resource - [18:16] - read-write - - - SELECT - Selects one or more resources from the wanted group. One bit is provided per resource from the group - [7:0] - read-write - - - - - TRCSSCSR - Controls the corresponding single-shot comparator resource - 0x412A0 - 0x00000000 - - - STATUS - Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched - [31:31] - read-write - - - PC - Reserved, RES1 - [3:3] - read-only - - - DV - Reserved, RES0 - [2:2] - read-only - - - DA - Reserved, RES0 - [1:1] - read-only - - - INST - Reserved, RES0 - [0:0] - read-only - - - - - TRCSSPCICR - Selects the PE comparator inputs for Single-shot control - 0x412C0 - 0x00000000 - - - PC - Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control - [3:0] - read-write - - - - - TRCPDCR - Requests the system to provide power to the trace unit - 0x41310 - 0x00000000 - - - PU - Powerup request bit: - [3:3] - read-write - - - - - TRCPDSR - Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status - 0x41314 - 0x00000003 - - - OSLK - OS Lock status bit: - [5:5] - read-only - - - STICKYPD - Sticky powerdown status bit. Indicates whether the trace register state is valid: - [1:1] - read-only - - - POWER - Power status bit: - [0:0] - read-only - - - - - TRCITATBIDR - Trace Integration ATB Identification Register - 0x41EE4 - 0x00000000 - - - ID - Trace ID - [6:0] - read-write - - - - - TRCITIATBINR - Trace Integration Instruction ATB In Register - 0x41EF4 - 0x00000000 - - - AFVALIDM - Integration Mode instruction AFVALIDM in - [1:1] - read-write - - - ATREADYM - Integration Mode instruction ATREADYM in - [0:0] - read-write - - - - - TRCITIATBOUTR - Trace Integration Instruction ATB Out Register - 0x41EFC - 0x00000000 - - - AFREADY - Integration Mode instruction AFREADY out - [1:1] - read-write - - - ATVALID - Integration Mode instruction ATVALID out - [0:0] - read-write - - - - - TRCCLAIMSET - Claim Tag Set Register - 0x41FA0 - 0x0000000F - - - SET3 - When a write to one of these bits occurs, with the value: - [3:3] - read-write - - - SET2 - When a write to one of these bits occurs, with the value: - [2:2] - read-write - - - SET1 - When a write to one of these bits occurs, with the value: - [1:1] - read-write - - - SET0 - When a write to one of these bits occurs, with the value: - [0:0] - read-write - - - - - TRCCLAIMCLR - Claim Tag Clear Register - 0x41FA4 - 0x00000000 - - - CLR3 - When a write to one of these bits occurs, with the value: - [3:3] - read-write - - - CLR2 - When a write to one of these bits occurs, with the value: - [2:2] - read-write - - - CLR1 - When a write to one of these bits occurs, with the value: - [1:1] - read-write - - - CLR0 - When a write to one of these bits occurs, with the value: - [0:0] - read-write - - - - - TRCAUTHSTATUS - Returns the level of tracing that the trace unit can support - 0x41FB8 - 0x00000000 - - - SNID - Indicates whether the system enables the trace unit to support Secure non-invasive debug: - [7:6] - read-only - - - SID - Indicates whether the trace unit supports Secure invasive debug: - [5:4] - read-only - - - NSNID - Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: - [3:2] - read-only - - - NSID - Indicates whether the trace unit supports Non-secure invasive debug: - [1:0] - read-only - - - - - TRCDEVARCH - TRCDEVARCH - 0x41FBC - 0x47724A13 - - - ARCHITECT - reads as 0b01000111011 - [31:21] - read-only - - - PRESENT - reads as 0b1 - [20:20] - read-only - - - REVISION - reads as 0b0000 - [19:16] - read-only - - - ARCHID - reads as 0b0100101000010011 - [15:0] - read-only - - - - - TRCDEVID - TRCDEVID - 0x41FC8 - 0x00000000 - - - TRCDEVID - [31:0] - read-write - - - - - TRCDEVTYPE - TRCDEVTYPE - 0x41FCC - 0x00000013 - - - SUB - reads as 0b0001 - [7:4] - read-only - - - MAJOR - reads as 0b0011 - [3:0] - read-only - - - - - TRCPIDR4 - TRCPIDR4 - 0x41FD0 - 0x00000004 - - - SIZE - reads as `ImpDef - [7:4] - read-only - - - DES_2 - reads as `ImpDef - [3:0] - read-only - - - - - TRCPIDR5 - TRCPIDR5 - 0x41FD4 - 0x00000000 - - - TRCPIDR5 - [31:0] - read-write - - - - - TRCPIDR6 - TRCPIDR6 - 0x41FD8 - 0x00000000 - - - TRCPIDR6 - [31:0] - read-write - - - - - TRCPIDR7 - TRCPIDR7 - 0x41FDC - 0x00000000 - - - TRCPIDR7 - [31:0] - read-write - - - - - TRCPIDR0 - TRCPIDR0 - 0x41FE0 - 0x00000021 - - - PART_0 - reads as `ImpDef - [7:0] - read-only - - - - - TRCPIDR1 - TRCPIDR1 - 0x41FE4 - 0x000000BD - - - DES_0 - reads as `ImpDef - [7:4] - read-only - - - PART_0 - reads as `ImpDef - [3:0] - read-only - - - - - TRCPIDR2 - TRCPIDR2 - 0x41FE8 - 0x0000002B - - - REVISION - reads as `ImpDef - [7:4] - read-only - - - JEDEC - reads as 0b1 - [3:3] - read-only - - - DES_0 - reads as `ImpDef - [2:0] - read-only - - - - - TRCPIDR3 - TRCPIDR3 - 0x41FEC - 0x00000000 - - - REVAND - reads as `ImpDef - [7:4] - read-only - - - CMOD - reads as `ImpDef - [3:0] - read-only - - - - - TRCCIDR0 - TRCCIDR0 - 0x41FF0 - 0x0000000D - - - PRMBL_0 - reads as 0b00001101 - [7:0] - read-only - - - - - TRCCIDR1 - TRCCIDR1 - 0x41FF4 - 0x00000090 - - - CLASS - reads as 0b1001 - [7:4] - read-only - - - PRMBL_1 - reads as 0b0000 - [3:0] - read-only - - - - - TRCCIDR2 - TRCCIDR2 - 0x41FF8 - 0x00000005 - - - PRMBL_2 - reads as 0b00000101 - [7:0] - read-only - - - - - TRCCIDR3 - TRCCIDR3 - 0x41FFC - 0x000000B1 - - - PRMBL_3 - reads as 0b10110001 - [7:0] - read-only - - - - - CTICONTROL - CTI Control Register - 0x42000 - 0x00000000 - - - GLBEN - Enables or disables the CTI - [0:0] - read-write - - - - - CTIINTACK - CTI Interrupt Acknowledge Register - 0x42010 - 0x00000000 - - - INTACK - Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared. - [7:0] - read-write - - - - - CTIAPPSET - CTI Application Trigger Set Register - 0x42014 - 0x00000000 - - - APPSET - Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel - [3:0] - read-write - - - - - CTIAPPCLEAR - CTI Application Trigger Clear Register - 0x42018 - 0x00000000 - - - APPCLEAR - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. - [3:0] - read-write - - - - - CTIAPPPULSE - CTI Application Pulse Register - 0x4201C - 0x00000000 - - - APPULSE - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. - [3:0] - read-write - - - - - CTIINEN0 - CTI Trigger to Channel Enable Registers - 0x42020 - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN1 - CTI Trigger to Channel Enable Registers - 0x42024 - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN2 - CTI Trigger to Channel Enable Registers - 0x42028 - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN3 - CTI Trigger to Channel Enable Registers - 0x4202C - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN4 - CTI Trigger to Channel Enable Registers - 0x42030 - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN5 - CTI Trigger to Channel Enable Registers - 0x42034 - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN6 - CTI Trigger to Channel Enable Registers - 0x42038 - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN7 - CTI Trigger to Channel Enable Registers - 0x4203C - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIOUTEN0 - CTI Trigger to Channel Enable Registers - 0x420A0 - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN1 - CTI Trigger to Channel Enable Registers - 0x420A4 - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN2 - CTI Trigger to Channel Enable Registers - 0x420A8 - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN3 - CTI Trigger to Channel Enable Registers - 0x420AC - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN4 - CTI Trigger to Channel Enable Registers - 0x420B0 - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN5 - CTI Trigger to Channel Enable Registers - 0x420B4 - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN6 - CTI Trigger to Channel Enable Registers - 0x420B8 - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN7 - CTI Trigger to Channel Enable Registers - 0x420BC - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTITRIGINSTATUS - CTI Trigger to Channel Enable Registers - 0x42130 - 0x00000000 - - - TRIGINSTATUS - Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. - [7:0] - read-only - - - - - CTITRIGOUTSTATUS - CTI Trigger In Status Register - 0x42134 - 0x00000000 - - - TRIGOUTSTATUS - Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. - [7:0] - read-only - - - - - CTICHINSTATUS - CTI Channel In Status Register - 0x42138 - 0x00000000 - - - CTICHOUTSTATUS - Shows the status of the ctichout outputs. There is one bit of the field for each channel output - [3:0] - read-only - - - - - CTIGATE - Enable CTI Channel Gate register - 0x42140 - 0x0000000F - - - CTIGATEEN3 - Enable ctichout3. Set to 0 to disable channel propagation. - [3:3] - read-write - - - CTIGATEEN2 - Enable ctichout2. Set to 0 to disable channel propagation. - [2:2] - read-write - - - CTIGATEEN1 - Enable ctichout1. Set to 0 to disable channel propagation. - [1:1] - read-write - - - CTIGATEEN0 - Enable ctichout0. Set to 0 to disable channel propagation. - [0:0] - read-write - - - - - ASICCTL - External Multiplexer Control register - 0x42144 - 0x00000000 - - - ASICCTL - [31:0] - read-write - - - - - ITCHOUT - Integration Test Channel Output register - 0x42EE4 - 0x00000000 - - - CTCHOUT - Sets the value of the ctichout outputs - [3:0] - read-write - - - - - ITTRIGOUT - Integration Test Trigger Output register - 0x42EE8 - 0x00000000 - - - CTTRIGOUT - Sets the value of the ctitrigout outputs - [7:0] - read-write - - - - - ITCHIN - Integration Test Channel Input register - 0x42EF4 - 0x00000000 - - - CTCHIN - Reads the value of the ctichin inputs. - [3:0] - read-only - - - - - ITCTRL - Integration Mode Control register - 0x42F00 - 0x00000000 - - - IME - Integration Mode Enable - [0:0] - read-write - - - - - DEVARCH - Device Architecture register - 0x42FBC - 0x47701A14 - - - ARCHITECT - Indicates the component architect - [31:21] - read-only - - - PRESENT - Indicates whether the DEVARCH register is present - [20:20] - read-only - - - REVISION - Indicates the architecture revision - [19:16] - read-only - - - ARCHID - Indicates the component - [15:0] - read-only - - - - - DEVID - Device Configuration register - 0x42FC8 - 0x00040800 - - - NUMCH - Number of ECT channels available - [19:16] - read-only - - - NUMTRIG - Number of ECT triggers available. - [15:8] - read-only - - - EXTMUXNUM - Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. - [4:0] - read-only - - - - - DEVTYPE - Device Type Identifier register - 0x42FCC - 0x00000014 - - - SUB - Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field. - [7:4] - read-only - - - MAJOR - Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component. - [3:0] - read-only - - - - - PIDR4 - CoreSight Peripheral ID4 - 0x42FD0 - 0x00000004 - - - SIZE - Always 0b0000. Indicates that the device only occupies 4KB of memory - [7:4] - read-only - - - DES_2 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - [3:0] - read-only - - - - - PIDR5 - CoreSight Peripheral ID5 - 0x42FD4 - 0x00000000 - - - PIDR5 - [31:0] - read-write - - - - - PIDR6 - CoreSight Peripheral ID6 - 0x42FD8 - 0x00000000 - - - PIDR6 - [31:0] - read-write - - - - - PIDR7 - CoreSight Peripheral ID7 - 0x42FDC - 0x00000000 - - - PIDR7 - [31:0] - read-write - - - - - PIDR0 - CoreSight Peripheral ID0 - 0x42FE0 - 0x00000021 - - - PART_0 - Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. - [7:0] - read-only - - - - - PIDR1 - CoreSight Peripheral ID1 - 0x42FE4 - 0x000000BD - - - DES_0 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - [7:4] - read-only - - - PART_1 - Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. - [3:0] - read-only - - - - - PIDR2 - CoreSight Peripheral ID2 - 0x42FE8 - 0x0000000B - - - REVISION - This device is at r1p0 - [7:4] - read-only - - - JEDEC - Always 1. Indicates that the JEDEC-assigned designer ID is used. - [3:3] - read-only - - - DES_1 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - [2:0] - read-only - - - - - PIDR3 - CoreSight Peripheral ID3 - 0x42FEC - 0x00000000 - - - REVAND - Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. - [7:4] - read-only - - - CMOD - Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. - [3:0] - read-only - - - - - CIDR0 - CoreSight Component ID0 - 0x42FF0 - 0x0000000D - - - PRMBL_0 - Preamble[0]. Contains bits[7:0] of the component identification code - [7:0] - read-only - - - - - CIDR1 - CoreSight Component ID1 - 0x42FF4 - 0x00000090 - - - CLASS - Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code. - [7:4] - read-only - - - PRMBL_1 - Preamble[1]. Contains bits[11:8] of the component identification code. - [3:0] - read-only - - - - - CIDR2 - CoreSight Component ID2 - 0x42FF8 - 0x00000005 - - - PRMBL_2 - Preamble[2]. Contains bits[23:16] of the component identification code. - [7:0] - read-only - - - - - CIDR3 - CoreSight Component ID3 - 0x42FFC - 0x000000B1 - - - PRMBL_3 - Preamble[3]. Contains bits[31:24] of the component identification code. - [7:0] - read-only - - - - - - - PPB_NS - 0xE0020000 - - - QMI - QSPI Memory Interface. - - Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. - 0x400D0000 - - 0x0 - 0x54 - registers - - - - DIRECT_CSR - Control and status for direct serial mode - - Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. - 0x0 - 0x01800000 - - - RXDELAY - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) - [31:30] - read-write - - - CLKDIV - Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. - - The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte. - [29:22] - read-write - - - RXLEVEL - Current level of DIRECT_RX FIFO - [20:18] - read-only - - - RXFULL - When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full. - [17:17] - read-only - - - RXEMPTY - When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined. - [16:16] - read-only - - - TXLEVEL - Current level of DIRECT_TX FIFO - [14:12] - read-only - - - TXEMPTY - When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes. - [11:11] - read-only - - - TXFULL - When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored. - [10:10] - read-only - - - AUTO_CS1N - When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set. - [7:7] - read-write - - - AUTO_CS0N - When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set. - [6:6] - read-write - - - ASSERT_CS1N - When 1, assert (i.e. drive low) the CS1n chip select line. - - Note that this applies even when DIRECT_CSR_EN is 0. - [3:3] - read-write - - - ASSERT_CS0N - When 1, assert (i.e. drive low) the CS0n chip select line. - - Note that this applies even when DIRECT_CSR_EN is 0. - [2:2] - read-write - - - BUSY - Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. - - The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. - - (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.) - [1:1] - read-only - - - EN - Enable direct mode. - - In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. - - Memory-mapped accesses will generate bus errors when direct serial mode is enabled. - [0:0] - read-write - - - - - DIRECT_TX - Transmit FIFO for direct mode - 0x4 - 0x00000000 - - - NOPUSH - Inhibit the RX FIFO push that would correspond to this TX FIFO entry. - - Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. - [20:20] - write-only - - - OE - Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. - - For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. - [19:19] - write-only - - - DWIDTH - Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. - [18:18] - write-only - - - IWIDTH - Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. - [17:16] - write-only - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - DATA - Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. - - For 16-bit data, the least-significant byte is transmitted first. - [15:0] - write-only - - - - - DIRECT_RX - Receive FIFO for direct mode - 0x8 - 0x00000000 - - - DIRECT_RX - With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. - - When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. - [15:0] - read-only - modify - - - - - M0_TIMING - Timing configuration register for memory address window 0. - 0xC - 0x40000004 - - - COOLDOWN - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. - - If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. - - Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. - - If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. - [31:30] - read-write - - - PAGEBREAK - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. - - Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. - - This field has no effect when COOLDOWN is disabled. - [29:28] - read-write - - - NONE - No page boundary is enforced - 0 - - - 256 - Break bursts crossing a 256-byte page boundary - 1 - - - 1024 - Break bursts crossing a 1024-byte quad-page boundary - 2 - - - 4096 - Break bursts crossing a 4096-byte sector boundary - 3 - - - - - SELECT_SETUP - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. - - The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. - [25:25] - read-write - - - SELECT_HOLD - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. - - The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. - - Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. - - Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. - [24:23] - read-write - - - MAX_SELECT - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). - - This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. - - If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. - [22:17] - read-write - - - MIN_DESELECT - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. - - Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. - [16:12] - read-write - - - RXDELAY - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. - - At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. - [10:8] - read-write - - - CLKDIV - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. - - The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. - - If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. - [7:0] - read-write - - - - - M0_RFMT - Read transfer format configuration for memory address window 0. - - Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. - - The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. - 0x10 - 0x00001000 - - - DTR - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. - - DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. - - If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. - [28:28] - read-write - - - DUMMY_LEN - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - [18:16] - read-write - - - NONE - No dummy phase - 0 - - - 4 - 4 dummy bits - 1 - - - 8 - 8 dummy bits - 2 - - - 12 - 12 dummy bits - 3 - - - 16 - 16 dummy bits - 4 - - - 20 - 20 dummy bits - 5 - - - 24 - 24 dummy bits - 6 - - - 28 - 28 dummy bits - 7 - - - - - SUFFIX_LEN - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - - Only values of 0 and 8 bits are supported. - [15:14] - read-write - - - NONE - No suffix - 0 - - - 8 - 8-bit suffix - 2 - - - - - PREFIX_LEN - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) - [12:12] - read-write - - - NONE - No prefix - 0 - - - 8 - 8-bit prefix - 1 - - - - - DATA_WIDTH - The width used for the data transfer - [9:8] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - DUMMY_WIDTH - The width used for the dummy phase, if any. - - If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. - [7:6] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - SUFFIX_WIDTH - The width used for the post-address command suffix, if any - [5:4] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - ADDR_WIDTH - The transfer width used for the address. The address phase always transfers 24 bits in total. - [3:2] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - PREFIX_WIDTH - The transfer width used for the command prefix, if any - [1:0] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - - - M0_RCMD - Command constants used for reads from memory address window 0. - - The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. - 0x14 - 0x0000A003 - - - SUFFIX - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. - [15:8] - read-write - - - PREFIX - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. - [7:0] - read-write - - - - - M0_WFMT - Write transfer format configuration for memory address window 0. - - Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. - - The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default. - 0x18 - 0x00001000 - - - DTR - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. - - DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. - - If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. - [28:28] - read-write - - - DUMMY_LEN - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - [18:16] - read-write - - - NONE - No dummy phase - 0 - - - 4 - 4 dummy bits - 1 - - - 8 - 8 dummy bits - 2 - - - 12 - 12 dummy bits - 3 - - - 16 - 16 dummy bits - 4 - - - 20 - 20 dummy bits - 5 - - - 24 - 24 dummy bits - 6 - - - 28 - 28 dummy bits - 7 - - - - - SUFFIX_LEN - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - - Only values of 0 and 8 bits are supported. - [15:14] - read-write - - - NONE - No suffix - 0 - - - 8 - 8-bit suffix - 2 - - - - - PREFIX_LEN - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) - [12:12] - read-write - - - NONE - No prefix - 0 - - - 8 - 8-bit prefix - 1 - - - - - DATA_WIDTH - The width used for the data transfer - [9:8] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - DUMMY_WIDTH - The width used for the dummy phase, if any. - - If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. - [7:6] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - SUFFIX_WIDTH - The width used for the post-address command suffix, if any - [5:4] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - ADDR_WIDTH - The transfer width used for the address. The address phase always transfers 24 bits in total. - [3:2] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - PREFIX_WIDTH - The transfer width used for the command prefix, if any - [1:0] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - - - M0_WCMD - Command constants used for writes to memory address window 0. - - The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. - 0x1C - 0x0000A002 - - - SUFFIX - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. - [15:8] - read-write - - - PREFIX - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. - [7:0] - read-write - - - - - M1_TIMING - Timing configuration register for memory address window 1. - 0x20 - 0x40000004 - - - COOLDOWN - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. - - If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. - - Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. - - If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. - [31:30] - read-write - - - PAGEBREAK - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. - - Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. - - This field has no effect when COOLDOWN is disabled. - [29:28] - read-write - - - NONE - No page boundary is enforced - 0 - - - 256 - Break bursts crossing a 256-byte page boundary - 1 - - - 1024 - Break bursts crossing a 1024-byte quad-page boundary - 2 - - - 4096 - Break bursts crossing a 4096-byte sector boundary - 3 - - - - - SELECT_SETUP - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. - - The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. - [25:25] - read-write - - - SELECT_HOLD - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. - - The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. - - Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. - - Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. - [24:23] - read-write - - - MAX_SELECT - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). - - This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. - - If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. - [22:17] - read-write - - - MIN_DESELECT - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. - - Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. - [16:12] - read-write - - - RXDELAY - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. - - At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. - [10:8] - read-write - - - CLKDIV - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. - - The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. - - If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. - [7:0] - read-write - - - - - M1_RFMT - Read transfer format configuration for memory address window 1. - - Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. - - The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. - 0x24 - 0x00001000 - - - DTR - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. - - DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. - - If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. - [28:28] - read-write - - - DUMMY_LEN - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - [18:16] - read-write - - - NONE - No dummy phase - 0 - - - 4 - 4 dummy bits - 1 - - - 8 - 8 dummy bits - 2 - - - 12 - 12 dummy bits - 3 - - - 16 - 16 dummy bits - 4 - - - 20 - 20 dummy bits - 5 - - - 24 - 24 dummy bits - 6 - - - 28 - 28 dummy bits - 7 - - - - - SUFFIX_LEN - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - - Only values of 0 and 8 bits are supported. - [15:14] - read-write - - - NONE - No suffix - 0 - - - 8 - 8-bit suffix - 2 - - - - - PREFIX_LEN - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) - [12:12] - read-write - - - NONE - No prefix - 0 - - - 8 - 8-bit prefix - 1 - - - - - DATA_WIDTH - The width used for the data transfer - [9:8] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - DUMMY_WIDTH - The width used for the dummy phase, if any. - - If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. - [7:6] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - SUFFIX_WIDTH - The width used for the post-address command suffix, if any - [5:4] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - ADDR_WIDTH - The transfer width used for the address. The address phase always transfers 24 bits in total. - [3:2] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - PREFIX_WIDTH - The transfer width used for the command prefix, if any - [1:0] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - - - M1_RCMD - Command constants used for reads from memory address window 1. - - The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. - 0x28 - 0x0000A003 - - - SUFFIX - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. - [15:8] - read-write - - - PREFIX - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. - [7:0] - read-write - - - - - M1_WFMT - Write transfer format configuration for memory address window 1. - - Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. - - The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default. - 0x2C - 0x00001000 - - - DTR - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. - - DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. - - If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. - [28:28] - read-write - - - DUMMY_LEN - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - [18:16] - read-write - - - NONE - No dummy phase - 0 - - - 4 - 4 dummy bits - 1 - - - 8 - 8 dummy bits - 2 - - - 12 - 12 dummy bits - 3 - - - 16 - 16 dummy bits - 4 - - - 20 - 20 dummy bits - 5 - - - 24 - 24 dummy bits - 6 - - - 28 - 28 dummy bits - 7 - - - - - SUFFIX_LEN - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - - Only values of 0 and 8 bits are supported. - [15:14] - read-write - - - NONE - No suffix - 0 - - - 8 - 8-bit suffix - 2 - - - - - PREFIX_LEN - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) - [12:12] - read-write - - - NONE - No prefix - 0 - - - 8 - 8-bit prefix - 1 - - - - - DATA_WIDTH - The width used for the data transfer - [9:8] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - DUMMY_WIDTH - The width used for the dummy phase, if any. - - If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. - [7:6] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - SUFFIX_WIDTH - The width used for the post-address command suffix, if any - [5:4] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - ADDR_WIDTH - The transfer width used for the address. The address phase always transfers 24 bits in total. - [3:2] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - PREFIX_WIDTH - The transfer width used for the command prefix, if any - [1:0] - read-write - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - - - M1_WCMD - Command constants used for writes to memory address window 1. - - The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. - 0x30 - 0x0000A002 - - - SUFFIX - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. - [15:8] - read-write - - - PREFIX - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. - [7:0] - read-write - - - - - ATRANS0 - Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x34 - 0x04000000 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS1 - Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x38 - 0x04000400 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS2 - Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x3C - 0x04000800 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS3 - Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x40 - 0x04000C00 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS4 - Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x44 - 0x04000000 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS5 - Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x48 - 0x04000400 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS6 - Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x4C - 0x04000800 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS7 - Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x50 - 0x04000C00 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - - - XIP_CTRL - QSPI flash execute-in-place block - 0x400C8000 - - 0x0 - 0x20 - registers - - - - CTRL - Cache control register. Read-only from a Non-secure context. - 0x0 - 0x00000083 - - - WRITABLE_M1 - If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. - - XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. - - The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. - - Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. - - Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. - [11:11] - read-write - - - WRITABLE_M0 - If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. - - XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. - - The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. - - Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. - - Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. - [10:10] - read-write - - - SPLIT_WAYS - When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. - - This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. - - A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation. - [9:9] - read-write - - - MAINT_NONSEC - When 0, Non-secure accesses to the cache maintenance address window (addr[27] == 1, addr[26] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. - - Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. - - Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code. - [8:8] - read-write - - - NO_UNTRANSLATED_NONSEC - When 1, Non-secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. - [7:7] - read-write - - - NO_UNTRANSLATED_SEC - When 1, Secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. - [6:6] - read-write - - - NO_UNCACHED_NONSEC - When 1, Non-secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. - - Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. - [5:5] - read-write - - - NO_UNCACHED_SEC - When 1, Secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. - - Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. - [4:4] - read-write - - - POWER_DOWN - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down. - [3:3] - read-write - - - EN_NONSECURE - When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. - - Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. - [1:1] - read-write - - - EN_SECURE - When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. - - Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. - - There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled. - [0:0] - read-write - - - - - STAT - 0x8 - 0x00000002 - - - FIFO_FULL - When 1, indicates the XIP streaming FIFO is completely full. - The streaming FIFO is 2 entries deep, so the full and empty - flag allow its level to be ascertained. - [2:2] - read-only - - - FIFO_EMPTY - When 1, indicates the XIP streaming FIFO is completely empty. - [1:1] - read-only - - - - - CTR_HIT - Cache Hit counter - 0xC - 0x00000000 - - - CTR_HIT - A 32 bit saturating counter that increments upon each cache hit, - i.e. when an XIP access is serviced directly from cached data. - Write any value to clear. - [31:0] - read-write - oneToClear - - - - - CTR_ACC - Cache Access counter - 0x10 - 0x00000000 - - - CTR_ACC - A 32 bit saturating counter that increments upon each XIP access, - whether the cache is hit or not. This includes noncacheable accesses. - Write any value to clear. - [31:0] - read-write - oneToClear - - - - - STREAM_ADDR - FIFO stream address - 0x14 - 0x00000000 - - - STREAM_ADDR - The address of the next word to be streamed from flash to the streaming FIFO. - Increments automatically after each flash access. - Write the initial access address here before starting a streaming read. - [31:2] - read-write - - - - - STREAM_CTR - FIFO stream control - 0x18 - 0x00000000 - - - STREAM_CTR - Write a nonzero value to start a streaming read. This will then - progress in the background, using flash idle cycles to transfer - a linear data block from flash to the streaming FIFO. - Decrements automatically (1 at a time) as the stream - progresses, and halts on reaching 0. - Write 0 to halt an in-progress stream, and discard any in-flight - read, so that a new stream can immediately be started (after - draining the FIFO and reinitialising STREAM_ADDR) - [21:0] - read-write - - - - - STREAM_FIFO - FIFO stream data - 0x1C - 0x00000000 - - - STREAM_FIFO - Streamed data is buffered here, for retrieval by the system DMA. - This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing - the DMA to bus stalls caused by other XIP traffic. - [31:0] - read-only - modify - - - - - - - XIP_AUX - Auxiliary DMA access to XIP FIFOs, via fast AHB bus access - 0x50500000 - - 0x0 - 0xC - registers - - - - STREAM - Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) - 0x0 - 0x00000000 - - - STREAM - [31:0] - read-only - modify - - - - - QMI_DIRECT_TX - Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) - 0x4 - 0x00000000 - - - NOPUSH - Inhibit the RX FIFO push that would correspond to this TX FIFO entry. - - Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. - [20:20] - write-only - - - OE - Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. - - For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. - [19:19] - write-only - - - DWIDTH - Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. - [18:18] - write-only - - - IWIDTH - Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. - [17:16] - write-only - - - S - Single width - 0 - - - D - Dual width - 1 - - - Q - Quad width - 2 - - - - - DATA - Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. - - For 16-bit data, the least-significant byte is transmitted first. - [15:0] - write-only - - - - - QMI_DIRECT_RX - Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) - 0x8 - 0x00000000 - - - QMI_DIRECT_RX - With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. - - When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. - [15:0] - read-only - modify - - - - - - - SYSCFG - Register block for various chip control signals - 0x40008000 - - 0x0 - 0x18 - registers - - - - PROC_CONFIG - Configuration for processors - 0x0 - 0x00000000 - - - PROC1_HALTED - Indication that proc1 has halted - [1:1] - read-only - - - PROC0_HALTED - Indication that proc0 has halted - [0:0] - read-only - - - - - PROC_IN_SYNC_BYPASS - For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 0...31. - 0x4 - 0x00000000 - - - GPIO - [31:0] - read-write - - - - - PROC_IN_SYNC_BYPASS_HI - For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63 - 0x8 - 0x00000000 - - - QSPI_SD - [31:28] - read-write - - - QSPI_CSN - [27:27] - read-write - - - QSPI_SCK - [26:26] - read-write - - - USB_DM - [25:25] - read-write - - - USB_DP - [24:24] - read-write - - - GPIO - [15:0] - read-write - - - - - DBGFORCE - Directly control the chip SWD debug port - 0xC - 0x00000006 - - - ATTACH - Attach chip debug port to syscfg controls, and disconnect it from external SWD pads. - [3:3] - read-write - - - SWCLK - Directly drive SWCLK, if ATTACH is set - [2:2] - read-write - - - SWDI - Directly drive SWDIO input, if ATTACH is set - [1:1] - read-write - - - SWDO - Observe the value of SWDIO output. - [0:0] - read-only - - - - - MEMPOWERDOWN - Control PD pins to memories. - Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible - Use with caution - 0x10 - 0x00000000 - - - BOOTRAM - [12:12] - read-write - - - ROM - [11:11] - read-write - - - USB - [10:10] - read-write - - - SRAM9 - [9:9] - read-write - - - SRAM8 - [8:8] - read-write - - - SRAM7 - [7:7] - read-write - - - SRAM6 - [6:6] - read-write - - - SRAM5 - [5:5] - read-write - - - SRAM4 - [4:4] - read-write - - - SRAM3 - [3:3] - read-write - - - SRAM2 - [2:2] - read-write - - - SRAM1 - [1:1] - read-write - - - SRAM0 - [0:0] - read-write - - - - - AUXCTRL - Auxiliary system control register - 0x14 - 0x00000000 - - - AUXCTRL - * Bits 7:2: Reserved - - * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. - - * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state. - [7:0] - read-write - - - - - - - XOSC - Controls the crystal oscillator - 0x40048000 - - 0x0 - 0x14 - registers - - - - CTRL - Crystal Oscillator Control - 0x0 - 0x00000000 - - - ENABLE - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE - [11:0] - read-write - - - 1_15MHZ - 2720 - - - 10_30MHZ - 2721 - - - 25_60MHZ - 2722 - - - 40_100MHZ - 2723 - - - - - - - STATUS - Crystal Oscillator Status - 0x4 - 0x00000000 - - - STABLE - Oscillator is running and stable - [31:31] - read-only - - - BADWRITE - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT - [24:24] - read-write - oneToClear - - - ENABLED - Oscillator is enabled but not necessarily running and stable, resets to 0 - [12:12] - read-only - - - FREQ_RANGE - The current frequency range setting - [1:0] - read-only - - - 1_15MHZ - 0 - - - 10_30MHZ - 1 - - - 25_60MHZ - 2 - - - 40_100MHZ - 3 - - - - - - - DORMANT - Crystal Oscillator pause control - 0x8 - 0x00000000 - - - DORMANT - This is used to save power by pausing the XOSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - Warning: stop the PLLs before selecting dormant mode - Warning: setup the irq before selecting dormant mode - [31:0] - read-write - - - dormant - 1668246881 - - - WAKE - 2002873189 - - - - - - - STARTUP - Controls the startup delay - 0xC - 0x00000000 - - - X4 - Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0. - [20:20] - read-write - - - DELAY - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. - [13:0] - read-write - - - - - COUNT - A down counter running at the xosc frequency which counts to zero and stops. - Can be used for short software pauses when setting up time sensitive hardware. - To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. - Minimum count value is 4. Count values <4 will be treated as count value =4. - Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that. - 0x10 - 0x00000000 - - - COUNT - [15:0] - read-write - - - - - - - PLL_SYS - 0x40050000 - - 0x0 - 0x20 - registers - - - PLL_SYS_IRQ - 42 - - - - CS - Control and Status - GENERAL CONSTRAINTS: - Reference clock frequency min=5MHz, max=800MHz - Feedback divider min=16, max=320 - VCO frequency min=750MHz, max=1600MHz - 0x0 - 0x00000001 - - - LOCK - PLL is locked - [31:31] - read-only - - - LOCK_N - PLL is not locked - Ideally this is cleared when PLL lock is seen and this should never normally be set - [30:30] - read-write - oneToClear - - - BYPASS - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. - [8:8] - read-write - - - REFDIV - Divides the PLL input reference clock. - Behaviour is undefined for div=0. - PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. - [5:0] - read-write - - - - - PWR - Controls the PLL power modes. - 0x4 - 0x0000002D - - - VCOPD - PLL VCO powerdown - To save power set high when PLL output not required or bypass=1. - [5:5] - read-write - - - POSTDIVPD - PLL post divider powerdown - To save power set high when PLL output not required or bypass=1. - [3:3] - read-write - - - DSMPD - PLL DSM powerdown - Nothing is achieved by setting this low. - [2:2] - read-write - - - PD - PLL powerdown - To save power set high when PLL output not required. - [0:0] - read-write - - - - - FBDIV_INT - Feedback divisor - (note: this PLL does not support fractional division) - 0x8 - 0x00000000 - - - FBDIV_INT - see ctrl reg description for constraints - [11:0] - read-write - - - - - PRIM - Controls the PLL post dividers for the primary output - (note: this PLL does not have a secondary output) - the primary output is driven from VCO divided by postdiv1*postdiv2 - 0xC - 0x00077000 - - - POSTDIV1 - divide by 1-7 - [18:16] - read-write - - - POSTDIV2 - divide by 1-7 - [14:12] - read-write - - - - - INTR - Raw Interrupts - 0x10 - 0x00000000 - - - LOCK_N_STICKY - [0:0] - read-write - oneToClear - - - - - INTE - Interrupt Enable - 0x14 - 0x00000000 - - - LOCK_N_STICKY - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x18 - 0x00000000 - - - LOCK_N_STICKY - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x1C - 0x00000000 - - - LOCK_N_STICKY - [0:0] - read-only - - - - - - - PLL_USB - 0x40058000 - - PLL_USB_IRQ - 43 - - - - ACCESSCTRL - Hardware access control registers - 0x40060000 - - 0x0 - 0xEC - registers - - - - LOCK - Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. - - LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL - - Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to. - 0x0 - 0x00000004 - - - DEBUG - [3:3] - read-write - - - DMA - [2:2] - read-only - - - CORE1 - [1:1] - read-write - - - CORE0 - [0:0] - read-write - - - - - FORCE_CORE_NS - Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. - - Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID. - 0x4 - 0x00000000 - - - CORE1 - [1:1] - read-write - - - - - CFGRESET - Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. - - This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. - - Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents. - 0x8 - 0x00000000 - - - CFGRESET - [0:0] - write-only - - - - - GPIO_NSMASK0 - Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. - - 0 -> Secure access only - - 1 -> Secure + Non-secure access - 0xC - 0x00000000 - - - GPIO_NSMASK0 - [31:0] - read-write - - - - - GPIO_NSMASK1 - Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger. - 0x10 - 0x00000000 - - - QSPI_SD - [31:28] - read-write - - - QSPI_CSN - [27:27] - read-write - - - QSPI_SCK - [26:26] - read-write - - - USB_DM - [25:25] - read-write - - - USB_DP - [24:24] - read-write - - - GPIO - [15:0] - read-write - - - - - ROM - Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x14 - 0x000000FF - - - DBG - If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, ROM can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, ROM can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - XIP_MAIN - Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x18 - 0x000000FF - - - DBG - If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, XIP_MAIN can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM0 - Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x1C - 0x000000FF - - - DBG - If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM1 - Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x20 - 0x000000FF - - - DBG - If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM2 - Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x24 - 0x000000FF - - - DBG - If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM2 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM2 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM3 - Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x28 - 0x000000FF - - - DBG - If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM3 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM3 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM4 - Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x2C - 0x000000FF - - - DBG - If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM4 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM4 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM5 - Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x30 - 0x000000FF - - - DBG - If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM5 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM5 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM6 - Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x34 - 0x000000FF - - - DBG - If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM6 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM6 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM7 - Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x38 - 0x000000FF - - - DBG - If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM7 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM7 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM8 - Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x3C - 0x000000FF - - - DBG - If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM8 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM8 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM9 - Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x40 - 0x000000FF - - - DBG - If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM9 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM9 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - DMA - Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x44 - 0x000000FC - - - DBG - If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, DMA can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, DMA can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - USBCTRL - Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x48 - 0x000000FC - - - DBG - If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, USBCTRL can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, USBCTRL can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PIO0 - Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x4C - 0x000000FC - - - DBG - If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PIO0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PIO0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PIO1 - Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x50 - 0x000000FC - - - DBG - If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PIO1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PIO1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PIO2 - Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x54 - 0x000000FC - - - DBG - If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PIO2 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PIO2 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - CORESIGHT_TRACE - Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x58 - 0x000000B8 - - - DBG - If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - CORESIGHT_PERIPH - Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x5C - 0x000000B8 - - - DBG - If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SYSINFO - Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x60 - 0x000000FF - - - DBG - If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SYSINFO can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SYSINFO can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - RESETS - Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x64 - 0x000000FC - - - DBG - If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, RESETS can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, RESETS can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - IO_BANK0 - Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x68 - 0x000000FC - - - DBG - If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, IO_BANK0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - IO_BANK1 - Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x6C - 0x000000FC - - - DBG - If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, IO_BANK1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PADS_BANK0 - Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x70 - 0x000000FC - - - DBG - If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PADS_BANK0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PADS_QSPI - Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x74 - 0x000000FC - - - DBG - If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PADS_QSPI can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - BUSCTRL - Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x78 - 0x000000FC - - - DBG - If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, BUSCTRL can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, BUSCTRL can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - ADC0 - Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x7C - 0x000000FC - - - DBG - If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, ADC0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, ADC0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - HSTX - Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x80 - 0x000000FC - - - DBG - If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, HSTX can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, HSTX can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - I2C0 - Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x84 - 0x000000FC - - - DBG - If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, I2C0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, I2C0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - I2C1 - Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x88 - 0x000000FC - - - DBG - If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, I2C1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, I2C1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PWM - Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x8C - 0x000000FC - - - DBG - If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PWM can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PWM can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SPI0 - Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x90 - 0x000000FC - - - DBG - If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SPI0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SPI0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SPI1 - Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x94 - 0x000000FC - - - DBG - If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SPI1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SPI1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - TIMER0 - Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x98 - 0x000000FC - - - DBG - If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, TIMER0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, TIMER0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - TIMER1 - Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x9C - 0x000000FC - - - DBG - If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, TIMER1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, TIMER1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - UART0 - Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xA0 - 0x000000FC - - - DBG - If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, UART0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, UART0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - UART1 - Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xA4 - 0x000000FC - - - DBG - If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, UART1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, UART1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - OTP - Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xA8 - 0x000000FC - - - DBG - If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, OTP can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, OTP can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - TBMAN - Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xAC - 0x000000FC - - - DBG - If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, TBMAN can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, TBMAN can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - POWMAN - Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xB0 - 0x000000B8 - - - DBG - If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, POWMAN can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, POWMAN can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - TRNG - Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xB4 - 0x000000B8 - - - DBG - If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, TRNG can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, TRNG can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SHA256 - Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xB8 - 0x000000F8 - - - DBG - If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SHA256 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SHA256 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SYSCFG - Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xBC - 0x000000B8 - - - DBG - If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SYSCFG can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SYSCFG can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - CLOCKS - Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xC0 - 0x000000B8 - - - DBG - If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, CLOCKS can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, CLOCKS can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - XOSC - Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xC4 - 0x000000B8 - - - DBG - If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, XOSC can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, XOSC can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - ROSC - Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xC8 - 0x000000B8 - - - DBG - If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, ROSC can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, ROSC can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PLL_SYS - Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xCC - 0x000000B8 - - - DBG - If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PLL_SYS can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PLL_SYS can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PLL_USB - Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xD0 - 0x000000B8 - - - DBG - If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PLL_USB can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PLL_USB can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - TICKS - Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xD4 - 0x000000B8 - - - DBG - If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, TICKS can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, TICKS can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - WATCHDOG - Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xD8 - 0x000000B8 - - - DBG - If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, WATCHDOG can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, WATCHDOG can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - RSM - Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xDC - 0x000000B8 - - - DBG - If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, RSM can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, RSM can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - XIP_CTRL - Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xE0 - 0x000000B8 - - - DBG - If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, XIP_CTRL can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - XIP_QMI - Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xE4 - 0x000000B8 - - - DBG - If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, XIP_QMI can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, XIP_QMI can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - XIP_AUX - Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0xE8 - 0x000000F8 - - - DBG - If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, XIP_AUX can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, XIP_AUX can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - - - UART0 - 0x40070000 - - 0x0 - 0x1000 - registers - - - UART0_IRQ - 33 - - - - UARTDR - Data Register, UARTDR - 0x0 - 0x00000000 - - - OE - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. - [11:11] - read-only - - - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. - [10:10] - read-only - - - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. - [9:9] - read-only - - - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. - [8:8] - read-only - - - DATA - Receive (read) data character. Transmit (write) data character. - [7:0] - read-write - modify - - - - - UARTRSR - Receive Status Register/Error Clear Register, UARTRSR/UARTECR - 0x4 - 0x00000000 - - - OE - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. - [3:3] - read-write - oneToClear - - - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. - [2:2] - read-write - oneToClear - - - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. - [1:1] - read-write - oneToClear - - - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. - [0:0] - read-write - oneToClear - - - - - UARTFR - Flag Register, UARTFR - 0x18 - 0x00000090 - - - RI - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. - [8:8] - read-only - - - TXFE - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. - [7:7] - read-only - - - RXFF - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. - [6:6] - read-only - - - TXFF - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. - [5:5] - read-only - - - RXFE - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. - [4:4] - read-only - - - BUSY - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. - [3:3] - read-only - - - DCD - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. - [2:2] - read-only - - - DSR - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. - [1:1] - read-only - - - CTS - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. - [0:0] - read-only - - - - - UARTILPR - IrDA Low-Power Counter Register, UARTILPR - 0x20 - 0x00000000 - - - ILPDVSR - 8-bit low-power divisor value. These bits are cleared to 0 at reset. - [7:0] - read-write - - - - - UARTIBRD - Integer Baud Rate Register, UARTIBRD - 0x24 - 0x00000000 - - - BAUD_DIVINT - The integer baud rate divisor. These bits are cleared to 0 on reset. - [15:0] - read-write - - - - - UARTFBRD - Fractional Baud Rate Register, UARTFBRD - 0x28 - 0x00000000 - - - BAUD_DIVFRAC - The fractional baud rate divisor. These bits are cleared to 0 on reset. - [5:0] - read-write - - - - - UARTLCR_H - Line Control Register, UARTLCR_H - 0x2C - 0x00000000 - - - SPS - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. - [7:7] - read-write - - - WLEN - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. - [6:5] - read-write - - - FEN - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). - [4:4] - read-write - - - STP2 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. - [3:3] - read-write - - - EPS - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. - [2:2] - read-write - - - PEN - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. - [1:1] - read-write - - - BRK - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. - [0:0] - read-write - - - - - UARTCR - Control Register, UARTCR - 0x30 - 0x00000300 - - - CTSEN - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. - [15:15] - read-write - - - RTSEN - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. - [14:14] - read-write - - - OUT2 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). - [13:13] - read-write - - - OUT1 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). - [12:12] - read-write - - - RTS - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. - [11:11] - read-write - - - DTR - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. - [10:10] - read-write - - - RXE - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. - [9:9] - read-write - - - TXE - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. - [8:8] - read-write - - - LBE - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. - [7:7] - read-write - - - SIRLP - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. - [2:2] - read-write - - - SIREN - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. - [1:1] - read-write - - - UARTEN - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. - [0:0] - read-write - - - - - UARTIFLS - Interrupt FIFO Level Select Register, UARTIFLS - 0x34 - 0x00000012 - - - RXIFLSEL - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. - [5:3] - read-write - - - TXIFLSEL - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. - [2:0] - read-write - - - - - UARTIMSC - Interrupt Mask Set/Clear Register, UARTIMSC - 0x38 - 0x00000000 - - - OEIM - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. - [10:10] - read-write - - - BEIM - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. - [9:9] - read-write - - - PEIM - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. - [8:8] - read-write - - - FEIM - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. - [7:7] - read-write - - - RTIM - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. - [6:6] - read-write - - - TXIM - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. - [5:5] - read-write - - - RXIM - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. - [4:4] - read-write - - - DSRMIM - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. - [3:3] - read-write - - - DCDMIM - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. - [2:2] - read-write - - - CTSMIM - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. - [1:1] - read-write - - - RIMIM - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. - [0:0] - read-write - - - - - UARTRIS - Raw Interrupt Status Register, UARTRIS - 0x3C - 0x00000000 - - - OERIS - Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BERIS - Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PERIS - Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FERIS - Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTRIS - Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a - [6:6] - read-only - - - TXRIS - Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXRIS - Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRRMIS - nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only - - - DCDRMIS - nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only - - - CTSRMIS - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. - [1:1] - read-only - - - RIRMIS - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. - [0:0] - read-only - - - - - UARTMIS - Masked Interrupt Status Register, UARTMIS - 0x40 - 0x00000000 - - - OEMIS - Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BEMIS - Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PEMIS - Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FEMIS - Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTMIS - Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. - [6:6] - read-only - - - TXMIS - Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXMIS - Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRMMIS - nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only - - - DCDMMIS - nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only - - - CTSMMIS - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. - [1:1] - read-only - - - RIMMIS - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. - [0:0] - read-only - - - - - UARTICR - Interrupt Clear Register, UARTICR - 0x44 - 0x00000000 - - - OEIC - Overrun error interrupt clear. Clears the UARTOEINTR interrupt. - [10:10] - read-write - oneToClear - - - BEIC - Break error interrupt clear. Clears the UARTBEINTR interrupt. - [9:9] - read-write - oneToClear - - - PEIC - Parity error interrupt clear. Clears the UARTPEINTR interrupt. - [8:8] - read-write - oneToClear - - - FEIC - Framing error interrupt clear. Clears the UARTFEINTR interrupt. - [7:7] - read-write - oneToClear - - - RTIC - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. - [6:6] - read-write - oneToClear - - - TXIC - Transmit interrupt clear. Clears the UARTTXINTR interrupt. - [5:5] - read-write - oneToClear - - - RXIC - Receive interrupt clear. Clears the UARTRXINTR interrupt. - [4:4] - read-write - oneToClear - - - DSRMIC - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. - [3:3] - read-write - oneToClear - - - DCDMIC - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. - [2:2] - read-write - oneToClear - - - CTSMIC - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. - [1:1] - read-write - oneToClear - - - RIMIC - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. - [0:0] - read-write - oneToClear - - - - - UARTDMACR - DMA Control Register, UARTDMACR - 0x48 - 0x00000000 - - - DMAONERR - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. - [2:2] - read-write - - - TXDMAE - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] - read-write - - - - - UARTPERIPHID0 - UARTPeriphID0 Register - 0xFE0 - 0x00000011 - - - PARTNUMBER0 - These bits read back as 0x11 - [7:0] - read-only - - - - - UARTPERIPHID1 - UARTPeriphID1 Register - 0xFE4 - 0x00000010 - - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only - - - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - UARTPERIPHID2 - UARTPeriphID2 Register - 0xFE8 - 0x00000034 - - - REVISION - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 - [7:4] - read-only - - - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only - - - - - UARTPERIPHID3 - UARTPeriphID3 Register - 0xFEC - 0x00000000 - - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only - - - - - UARTPCELLID0 - UARTPCellID0 Register - 0xFF0 - 0x0000000D - - - UARTPCELLID0 - These bits read back as 0x0D - [7:0] - read-only - - - - - UARTPCELLID1 - UARTPCellID1 Register - 0xFF4 - 0x000000F0 - - - UARTPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only - - - - - UARTPCELLID2 - UARTPCellID2 Register - 0xFF8 - 0x00000005 - - - UARTPCELLID2 - These bits read back as 0x05 - [7:0] - read-only - - - - - UARTPCELLID3 - UARTPCellID3 Register - 0xFFC - 0x000000B1 - - - UARTPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only - - - - - - - UART1 - 0x40078000 - - UART1_IRQ - 34 - - - - ROSC - 0x400E8000 - - 0x0 - 0x28 - registers - - - - CTRL - Ring Oscillator control - 0x0 - 0x00000AA0 - - - ENABLE - On power-up this field is initialised to ENABLE - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - Controls the number of delay stages in the ROSC ring - LOW uses stages 0 to 7 - MEDIUM uses stages 2 to 7 - HIGH uses stages 4 to 7 - TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications - The clock output will not glitch when changing the range up one step at a time - The clock output will glitch when changing the range down - Note: the values here are gray coded which is why HIGH comes before TOOHIGH - [11:0] - read-write - - - LOW - 4004 - - - MEDIUM - 4005 - - - HIGH - 4007 - - - TOOHIGH - 4006 - - - - - - - FREQA - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage - The drive strength has 4 levels determined by the number of bits set - Increasing the number of bits set increases the drive strength and increases the oscillation frequency - 0 bits set is the default drive strength - 1 bit set doubles the drive strength - 2 bits set triples drive strength - 3 bits set quadruples drive strength - For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 - 0x4 - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS3 - Stage 3 drive strength - [14:12] - read-write - - - DS2 - Stage 2 drive strength - [10:8] - read-write - - - DS1_RANDOM - Randomises the stage 1 drive strength - [7:7] - read-write - - - DS1 - Stage 1 drive strength - [6:4] - read-write - - - DS0_RANDOM - Randomises the stage 0 drive strength - [3:3] - read-write - - - DS0 - Stage 0 drive strength - [2:0] - read-write - - - - - FREQB - For a detailed description see freqa register - 0x8 - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS7 - Stage 7 drive strength - [14:12] - read-write - - - DS6 - Stage 6 drive strength - [10:8] - read-write - - - DS5 - Stage 5 drive strength - [6:4] - read-write - - - DS4 - Stage 4 drive strength - [2:0] - read-write - - - - - RANDOM - Loads a value to the LFSR randomiser - 0xC - 0x3F04B16D - - - SEED - [31:0] - read-write - - - - - DORMANT - Ring Oscillator pause control - 0x10 - 0x00000000 - - - DORMANT - This is used to save power by pausing the ROSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - Warning: setup the irq before selecting dormant mode - [31:0] - read-write - - - dormant - 1668246881 - - - WAKE - 2002873189 - - - - - - - DIV - Controls the output divider - 0x14 - 0x00000000 - - - DIV - set to 0xaa00 + div where - div = 0 divides by 128 - div = 1-127 divides by div - any other value sets div=128 - this register resets to div=32 - [15:0] - read-write - - - PASS - 43520 - - - - - - - PHASE - Controls the phase shifted output - 0x18 - 0x00000008 - - - PASSWD - set to 0xaa - any other value enables the output with shift=0 - [11:4] - read-write - - - ENABLE - enable the phase-shifted output - this can be changed on-the-fly - [3:3] - read-write - - - FLIP - invert the phase-shifted output - this is ignored when div=1 - [2:2] - read-write - - - SHIFT - phase shift the phase-shifted output by SHIFT input clocks - this can be changed on-the-fly - must be set to 0 before setting div=1 - [1:0] - read-write - - - - - STATUS - Ring Oscillator Status - 0x1C - 0x00000000 - - - STABLE - Oscillator is running and stable - [31:31] - read-only - - - BADWRITE - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT - [24:24] - read-write - oneToClear - - - DIV_RUNNING - post-divider is running - this resets to 0 but transitions to 1 during chip startup - [16:16] - read-only - - - ENABLED - Oscillator is enabled but not necessarily running and stable - this resets to 0 but transitions to 1 during chip startup - [12:12] - read-only - - - - - RANDOMBIT - This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency - 0x20 - 0x00000001 - - - RANDOMBIT - [0:0] - read-only - - - - - COUNT - A down counter running at the ROSC frequency which counts to zero and stops. - To start the counter write a non-zero value. - Can be used for short software pauses when setting up time sensitive hardware. - 0x24 - 0x00000000 - - - COUNT - [15:0] - read-write - - - - - - - POWMAN - Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use - 0x40100000 - - 0x0 - 0xF0 - registers - - - POWMAN_IRQ_POW - 44 - - - POWMAN_IRQ_TIMER - 45 - - - - BADPASSWD - Indicates a bad password has been used - 0x0 - 0x00000000 - - - BADPASSWD - [0:0] - read-write - oneToClear - - - - - VREG_CTRL - Voltage Regulator Control - 0x4 - 0x00008050 - - - RST_N - returns the regulator to its startup settings - 0 - reset - 1 - not reset (default) - [15:15] - read-write - - - UNLOCK - unlocks the VREG control interface after power up - 0 - Locked (default) - 1 - Unlocked - It cannot be relocked when it is unlocked. - [13:13] - read-write - - - ISOLATE - isolates the VREG control interface - 0 - not isolated (default) - 1 - isolated - [12:12] - read-write - - - DISABLE_VOLTAGE_LIMIT - 0=not disabled, 1=enabled - [8:8] - read-write - - - HT_TH - high temperature protection threshold - regulator power transistors are disabled when junction temperature exceeds threshold - 000 - 100C - 001 - 105C - 010 - 110C - 011 - 115C - 100 - 120C - 101 - 125C - 110 - 135C - 111 - 150C - [6:4] - read-write - - - - - VREG_STS - Voltage Regulator Status - 0x8 - 0x00000000 - - - VOUT_OK - output regulation status - 0=not in regulation, 1=in regulation - [4:4] - read-only - - - STARTUP - startup status - 0=startup complete, 1=starting up - [0:0] - read-only - - - - - VREG - Voltage Regulator Settings - 0xC - 0x000000B0 - - - UPDATE_IN_PROGRESS - regulator state is being updated - writes to the vreg register will be ignored when this field is set - [15:15] - read-only - - - VSEL - output voltage select - the regulator output voltage is limited to 1.3V unless the voltage limit - is disabled using the disable_voltage_limit field in the vreg_ctrl register - 00000 - 0.55V - 00001 - 0.60V - 00010 - 0.65V - 00011 - 0.70V - 00100 - 0.75V - 00101 - 0.80V - 00110 - 0.85V - 00111 - 0.90V - 01000 - 0.95V - 01001 - 1.00V - 01010 - 1.05V - 01011 - 1.10V (default) - 01100 - 1.15V - 01101 - 1.20V - 01110 - 1.25V - 01111 - 1.30V - 10000 - 1.35V - 10001 - 1.40V - 10010 - 1.50V - 10011 - 1.60V - 10100 - 1.65V - 10101 - 1.70V - 10110 - 1.80V - 10111 - 1.90V - 11000 - 2.00V - 11001 - 2.35V - 11010 - 2.50V - 11011 - 2.65V - 11100 - 2.80V - 11101 - 3.00V - 11110 - 3.15V - 11111 - 3.30V - [8:4] - read-write - - - HIZ - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode - [1:1] - read-write - - - - - VREG_LP_ENTRY - Voltage Regulator Low Power Entry Settings - 0x10 - 0x000000B4 - - - VSEL - output voltage select - the regulator output voltage is limited to 1.3V unless the voltage limit - is disabled using the disable_voltage_limit field in the vreg_ctrl register - 00000 - 0.55V - 00001 - 0.60V - 00010 - 0.65V - 00011 - 0.70V - 00100 - 0.75V - 00101 - 0.80V - 00110 - 0.85V - 00111 - 0.90V - 01000 - 0.95V - 01001 - 1.00V - 01010 - 1.05V - 01011 - 1.10V (default) - 01100 - 1.15V - 01101 - 1.20V - 01110 - 1.25V - 01111 - 1.30V - 10000 - 1.35V - 10001 - 1.40V - 10010 - 1.50V - 10011 - 1.60V - 10100 - 1.65V - 10101 - 1.70V - 10110 - 1.80V - 10111 - 1.90V - 11000 - 2.00V - 11001 - 2.35V - 11010 - 2.50V - 11011 - 2.65V - 11100 - 2.80V - 11101 - 3.00V - 11110 - 3.15V - 11111 - 3.30V - [8:4] - read-write - - - MODE - selects either normal (switching) mode or low power (linear) mode - low power mode can only be selected for output voltages up to 1.3V - 0 = normal mode (switching) - 1 = low power mode (linear) - [2:2] - read-write - - - HIZ - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode - [1:1] - read-write - - - - - VREG_LP_EXIT - Voltage Regulator Low Power Exit Settings - 0x14 - 0x000000B0 - - - VSEL - output voltage select - the regulator output voltage is limited to 1.3V unless the voltage limit - is disabled using the disable_voltage_limit field in the vreg_ctrl register - 00000 - 0.55V - 00001 - 0.60V - 00010 - 0.65V - 00011 - 0.70V - 00100 - 0.75V - 00101 - 0.80V - 00110 - 0.85V - 00111 - 0.90V - 01000 - 0.95V - 01001 - 1.00V - 01010 - 1.05V - 01011 - 1.10V (default) - 01100 - 1.15V - 01101 - 1.20V - 01110 - 1.25V - 01111 - 1.30V - 10000 - 1.35V - 10001 - 1.40V - 10010 - 1.50V - 10011 - 1.60V - 10100 - 1.65V - 10101 - 1.70V - 10110 - 1.80V - 10111 - 1.90V - 11000 - 2.00V - 11001 - 2.35V - 11010 - 2.50V - 11011 - 2.65V - 11100 - 2.80V - 11101 - 3.00V - 11110 - 3.15V - 11111 - 3.30V - [8:4] - read-write - - - MODE - selects either normal (switching) mode or low power (linear) mode - low power mode can only be selected for output voltages up to 1.3V - 0 = normal mode (switching) - 1 = low power mode (linear) - [2:2] - read-write - - - HIZ - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode - [1:1] - read-write - - - - - BOD_CTRL - Brown-out Detection Control - 0x18 - 0x00000000 - - - ISOLATE - isolates the brown-out detection control interface - 0 - not isolated (default) - 1 - isolated - [12:12] - read-write - - - - - BOD - Brown-out Detection Settings - 0x1C - 0x000000B1 - - - VSEL - threshold select - 00000 - 0.473V - 00001 - 0.516V - 00010 - 0.559V - 00011 - 0.602V - 00100 - 0.645VS - 00101 - 0.688V - 00110 - 0.731V - 00111 - 0.774V - 01000 - 0.817V - 01001 - 0.860V (default) - 01010 - 0.903V - 01011 - 0.946V - 01100 - 0.989V - 01101 - 1.032V - 01110 - 1.075V - 01111 - 1.118V - 10000 - 1.161 - 10001 - 1.204V - [8:4] - read-write - - - EN - enable brown-out detection - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - BOD_LP_ENTRY - Brown-out Detection Low Power Entry Settings - 0x20 - 0x000000B0 - - - VSEL - threshold select - 00000 - 0.473V - 00001 - 0.516V - 00010 - 0.559V - 00011 - 0.602V - 00100 - 0.645VS - 00101 - 0.688V - 00110 - 0.731V - 00111 - 0.774V - 01000 - 0.817V - 01001 - 0.860V (default) - 01010 - 0.903V - 01011 - 0.946V - 01100 - 0.989V - 01101 - 1.032V - 01110 - 1.075V - 01111 - 1.118V - 10000 - 1.161 - 10001 - 1.204V - [8:4] - read-write - - - EN - enable brown-out detection - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - BOD_LP_EXIT - Brown-out Detection Low Power Exit Settings - 0x24 - 0x000000B1 - - - VSEL - threshold select - 00000 - 0.473V - 00001 - 0.516V - 00010 - 0.559V - 00011 - 0.602V - 00100 - 0.645VS - 00101 - 0.688V - 00110 - 0.731V - 00111 - 0.774V - 01000 - 0.817V - 01001 - 0.860V (default) - 01010 - 0.903V - 01011 - 0.946V - 01100 - 0.989V - 01101 - 1.032V - 01110 - 1.075V - 01111 - 1.118V - 10000 - 1.161 - 10001 - 1.204V - [8:4] - read-write - - - EN - enable brown-out detection - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - LPOSC - Low power oscillator control register. - 0x28 - 0x00000203 - - - TRIM - Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3% - [9:4] - read-write - - - MODE - This feature has been removed - [1:0] - read-write - - - - - CHIP_RESET - Chip reset control and status - 0x2C - 0x00000000 - - - HAD_WATCHDOG_RESET_RSM - Last reset was a watchdog timeout which was configured to reset the power-on state machine - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer no - powman no - swcore no - psm yes - and does not change the power state - [28:28] - read-only - - - HAD_HZD_SYS_RESET_REQ - Last reset was a system reset from the hazard debugger - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer no - powman no - swcore no - psm yes - and does not change the power state - [27:27] - read-only - - - HAD_GLITCH_DETECT - Last reset was due to a power supply glitch - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer no - powman no - swcore no - psm yes - and does not change the power state - [26:26] - read-only - - - HAD_SWCORE_PD - Last reset was a switched core powerdown - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer no - powman no - swcore yes - psm yes - then starts the power sequencer - [25:25] - read-only - - - HAD_WATCHDOG_RESET_SWCORE - Last reset was a watchdog timeout which was configured to reset the switched-core - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer no - powman no - swcore yes - psm yes - then starts the power sequencer - [24:24] - read-only - - - HAD_WATCHDOG_RESET_POWMAN - Last reset was a watchdog timeout which was configured to reset the power manager - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [23:23] - read-only - - - HAD_WATCHDOG_RESET_POWMAN_ASYNC - Last reset was a watchdog timeout which was configured to reset the power manager asynchronously - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [22:22] - read-only - - - HAD_RESCUE - Last reset was a rescue reset from the debugger - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no, it sets this flag - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [21:21] - read-only - - - HAD_DP_RESET_REQ - Last reset was an reset request from the arm debugger - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag yes - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [19:19] - read-only - - - HAD_RUN_LOW - Last reset was from the RUN pin - This resets: - double_tap flag no - DP yes - RPAP yes - rescue_flag yes - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [18:18] - read-only - - - HAD_BOR - Last reset was from the brown-out detection block - This resets: - double_tap flag yes - DP yes - RPAP yes - rescue_flag yes - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [17:17] - read-only - - - HAD_POR - Last reset was from the power-on reset - This resets: - double_tap flag yes - DP yes - RPAP yes - rescue_flag yes - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [16:16] - read-only - - - RESCUE_FLAG - This is set by a rescue reset from the RP-AP. - Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. - The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up. - [4:4] - read-write - oneToClear - - - DOUBLE_TAP - This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader. - [0:0] - read-write - - - - - WDSEL - Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). - Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect. - 0x30 - 0x00000000 - - - RESET_RSM - If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence - From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD - From a hardware debug perspective it has the same effect as a reset from a glitch detector - [12:12] - read-write - - - RESET_SWCORE - If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence - From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD - From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain - [8:8] - read-write - - - RESET_POWMAN - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain - and run the full power-on state machine (PSM) sequence - This relies on clk_ref running. Use reset_powman_async if that may not be true - [4:4] - read-write - - - RESET_POWMAN_ASYNC - If set to 1, a watchdog reset will restore powman defaults, reset the timer, - reset the switched core domain and run the full power-on state machine (PSM) sequence - This does not rely on clk_ref running - [0:0] - read-write - - - - - SEQ_CFG - For configuration of the power sequencer - Writes are ignored while POWMAN_STATE_CHANGING=1 - 0x34 - 0x001011F0 - - - USING_FAST_POWCK - 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) - 1 indicates the POWMAN clock is running from the reference clock (2-50MHz) - [20:20] - read-only - - - USING_BOD_LP - Indicates the brown-out detector (BOD) mode - 0 = BOD high power mode which is the default - 1 = BOD low power mode - [17:17] - read-only - - - USING_VREG_LP - Indicates the voltage regulator (VREG) mode - 0 = VREG high power mode which is the default - 1 = VREG low power mode - [16:16] - read-only - - - USE_FAST_POWCK - selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. - 0 always run the POWMAN clock from the slow clock (lposc) - 1 run the POWMAN clock from the fast clock when available - This setting takes effect when a power up sequence is next run - [12:12] - read-write - - - RUN_LPOSC_IN_LP - Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer - This setting takes effect when the swcore is next powered down - [8:8] - read-write - - - USE_BOD_HP - Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up - This setting takes effect when the swcore is next powered up - [7:7] - read-write - - - USE_BOD_LP - Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down - This setting takes effect when the swcore is next powered down - [6:6] - read-write - - - USE_VREG_HP - Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up - This setting takes effect when the swcore is next powered up - [5:5] - read-write - - - USE_VREG_LP - Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down - This setting takes effect when the swcore is next powered down - [4:4] - read-write - - - HW_PWRUP_SRAM0 - Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). - 0=power-up - 1=no change - [1:1] - read-write - - - HW_PWRUP_SRAM1 - Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). - 0=power-up - 1=no change - [0:0] - read-write - - - - - STATE - This register controls the power state of the 4 power domains. - The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. - To change the state, write to POWMAN_STATE_REQ. - The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states - defined in the datasheet: - bit 3 = SWCORE - bit 2 = XIP cache - bit 1 = SRAM0 - bit 0 = SRAM1 - 0 = powered up - 1 = powered down - When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes. - 0x38 - 0x0000000F - - - CHANGING - [13:13] - read-only - - - WAITING - [12:12] - read-only - - - BAD_HW_REQ - Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up) - [11:11] - read-only - - - BAD_SW_REQ - Bad software initiated state request. No action taken. - [10:10] - read-only - - - PWRUP_WHILE_WAITING - Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down. - [9:9] - read-write - oneToClear - - - REQ_IGNORED - [8:8] - read-write - oneToClear - - - REQ - [7:4] - read-write - - - CURRENT - [3:0] - read-only - - - - - POW_FASTDIV - 0x3C - 0x00000040 - - - POW_FASTDIV - divides the POWMAN clock to provide a tick for the delay module and state machines - when clk_pow is running from the slow clock it is not divided - when clk_pow is running from the fast clock it is divided by tick_div - [10:0] - read-write - - - - - POW_DELAY - power state machine delays - 0x40 - 0x00002011 - - - SRAM_STEP - timing between the sram0 and sram1 power state machine steps - measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit - [15:8] - read-write - - - XIP_STEP - timing between the xip power state machine steps - measured in units of the lposc period, 0 gives a delay of 1 unit - [7:4] - read-write - - - SWCORE_STEP - timing between the swcore power state machine steps - measured in units of the lposc period, 0 gives a delay of 1 unit - [3:0] - read-write - - - - - EXT_CTRL0 - Configures a gpio as a power mode aware control output - 0x44 - 0x0000003F - - - LP_EXIT_STATE - output level when exiting the low power state - [14:14] - read-write - - - LP_ENTRY_STATE - output level when entering the low power state - [13:13] - read-write - - - INIT_STATE - [12:12] - read-write - - - INIT - [8:8] - read-write - - - GPIO_SELECT - selects from gpio 0->30 - set to 31 to disable this feature - [5:0] - read-write - - - - - EXT_CTRL1 - Configures a gpio as a power mode aware control output - 0x48 - 0x0000003F - - - LP_EXIT_STATE - output level when exiting the low power state - [14:14] - read-write - - - LP_ENTRY_STATE - output level when entering the low power state - [13:13] - read-write - - - INIT_STATE - [12:12] - read-write - - - INIT - [8:8] - read-write - - - GPIO_SELECT - selects from gpio 0->30 - set to 31 to disable this feature - [5:0] - read-write - - - - - EXT_TIME_REF - Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register. - 0x4C - 0x00000000 - - - DRIVE_LPCK - Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0 - [4:4] - read-write - - - SOURCE_SEL - 0 -> gpio12 - 1 -> gpio20 - 2 -> gpio14 - 3 -> gpio22 - [1:0] - read-write - - - - - LPOSC_FREQ_KHZ_INT - Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC. - 0x50 - 0x00000020 - - - LPOSC_FREQ_KHZ_INT - Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 - [5:0] - read-write - - - - - LPOSC_FREQ_KHZ_FRAC - Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC. - 0x54 - 0x0000C49C - - - LPOSC_FREQ_KHZ_FRAC - Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 - [15:0] - read-write - - - - - XOSC_FREQ_KHZ_INT - Informs the AON Timer of the integer component of the clock frequency when running off the XOSC. - 0x58 - 0x00002EE0 - - - XOSC_FREQ_KHZ_INT - Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 - [15:0] - read-write - - - - - XOSC_FREQ_KHZ_FRAC - Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC. - 0x5C - 0x00000000 - - - XOSC_FREQ_KHZ_FRAC - Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 - [15:0] - read-write - - - - - SET_TIME_63TO48 - 0x60 - 0x00000000 - - - SET_TIME_63TO48 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 - [15:0] - read-write - - - - - SET_TIME_47TO32 - 0x64 - 0x00000000 - - - SET_TIME_47TO32 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 - [15:0] - read-write - - - - - SET_TIME_31TO16 - 0x68 - 0x00000000 - - - SET_TIME_31TO16 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 - [15:0] - read-write - - - - - SET_TIME_15TO0 - 0x6C - 0x00000000 - - - SET_TIME_15TO0 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 - [15:0] - read-write - - - - - READ_TIME_UPPER - 0x70 - 0x00000000 - - - READ_TIME_UPPER - For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER. - [31:0] - read-only - - - - - READ_TIME_LOWER - 0x74 - 0x00000000 - - - READ_TIME_LOWER - For reading bits 31:0 of the timer. - [31:0] - read-only - - - - - ALARM_TIME_63TO48 - 0x78 - 0x00000000 - - - ALARM_TIME_63TO48 - This field must only be written when POWMAN_ALARM_ENAB=0 - [15:0] - read-write - - - - - ALARM_TIME_47TO32 - 0x7C - 0x00000000 - - - ALARM_TIME_47TO32 - This field must only be written when POWMAN_ALARM_ENAB=0 - [15:0] - read-write - - - - - ALARM_TIME_31TO16 - 0x80 - 0x00000000 - - - ALARM_TIME_31TO16 - This field must only be written when POWMAN_ALARM_ENAB=0 - [15:0] - read-write - - - - - ALARM_TIME_15TO0 - 0x84 - 0x00000000 - - - ALARM_TIME_15TO0 - This field must only be written when POWMAN_ALARM_ENAB=0 - [15:0] - read-write - - - - - TIMER - 0x88 - 0x00000000 - - - USING_GPIO_1HZ - Timer is synchronised to a 1hz gpio source - [19:19] - read-only - - - USING_GPIO_1KHZ - Timer is running from a 1khz gpio source - [18:18] - read-only - - - USING_LPOSC - Timer is running from lposc - [17:17] - read-only - - - USING_XOSC - Timer is running from xosc - [16:16] - read-only - - - USE_GPIO_1HZ - Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference. - [13:13] - read-write - - - USE_GPIO_1KHZ - switch to gpio as the source of the 1kHz timer tick - [10:10] - write-only - - - USE_XOSC - switch to xosc as the source of the 1kHz timer tick - [9:9] - write-only - - - USE_LPOSC - Switch to lposc as the source of the 1kHz timer tick - [8:8] - write-only - - - ALARM - Alarm has fired. Write to 1 to clear the alarm. - [6:6] - read-write - oneToClear - - - PWRUP_ON_ALARM - Alarm wakes the chip from low power mode - [5:5] - read-write - - - ALARM_ENAB - Enables the alarm. The alarm must be disabled while writing the alarm time. - [4:4] - read-write - - - CLEAR - Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time. - [2:2] - write-only - - - RUN - Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. - - Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. - - Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 - [1:1] - read-write - - - NONSEC_WRITE - Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure. - [0:0] - read-write - - - - - PWRUP0 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. - The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event - The number of gpios available depends on the package option. An invalid selection will be ignored - source = 0 selects gpio0 - . - . - source = 47 selects gpio47 - source = 48 selects qspi_ss - source = 49 selects qspi_sd0 - source = 50 selects qspi_sd1 - source = 51 selects qspi_sd2 - source = 52 selects qspi_sd3 - source = 53 selects qspi_sclk - level = 0 triggers the pwrup when the source is low - level = 1 triggers the pwrup when the source is high - 0x8C - 0x0000003F - - - RAW_STATUS - Value of selected gpio pin (only if enable == 1) - [10:10] - read-only - - - STATUS - Status of gpio wakeup. Write to 1 to clear a latched edge detect. - [9:9] - read-write - oneToClear - - - MODE - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. - [8:8] - read-write - - - level - 0 - - - edge - 1 - - - - - DIRECTION - [7:7] - read-write - - - low_falling - 0 - - - high_rising - 1 - - - - - ENABLE - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. - If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. - [6:6] - read-write - - - SOURCE - [5:0] - read-write - - - - - PWRUP1 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. - The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event - The number of gpios available depends on the package option. An invalid selection will be ignored - source = 0 selects gpio0 - . - . - source = 47 selects gpio47 - source = 48 selects qspi_ss - source = 49 selects qspi_sd0 - source = 50 selects qspi_sd1 - source = 51 selects qspi_sd2 - source = 52 selects qspi_sd3 - source = 53 selects qspi_sclk - level = 0 triggers the pwrup when the source is low - level = 1 triggers the pwrup when the source is high - 0x90 - 0x0000003F - - - RAW_STATUS - Value of selected gpio pin (only if enable == 1) - [10:10] - read-only - - - STATUS - Status of gpio wakeup. Write to 1 to clear a latched edge detect. - [9:9] - read-write - oneToClear - - - MODE - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. - [8:8] - read-write - - - level - 0 - - - edge - 1 - - - - - DIRECTION - [7:7] - read-write - - - low_falling - 0 - - - high_rising - 1 - - - - - ENABLE - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. - If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. - [6:6] - read-write - - - SOURCE - [5:0] - read-write - - - - - PWRUP2 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. - The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event - The number of gpios available depends on the package option. An invalid selection will be ignored - source = 0 selects gpio0 - . - . - source = 47 selects gpio47 - source = 48 selects qspi_ss - source = 49 selects qspi_sd0 - source = 50 selects qspi_sd1 - source = 51 selects qspi_sd2 - source = 52 selects qspi_sd3 - source = 53 selects qspi_sclk - level = 0 triggers the pwrup when the source is low - level = 1 triggers the pwrup when the source is high - 0x94 - 0x0000003F - - - RAW_STATUS - Value of selected gpio pin (only if enable == 1) - [10:10] - read-only - - - STATUS - Status of gpio wakeup. Write to 1 to clear a latched edge detect. - [9:9] - read-write - oneToClear - - - MODE - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. - [8:8] - read-write - - - level - 0 - - - edge - 1 - - - - - DIRECTION - [7:7] - read-write - - - low_falling - 0 - - - high_rising - 1 - - - - - ENABLE - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. - If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. - [6:6] - read-write - - - SOURCE - [5:0] - read-write - - - - - PWRUP3 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. - The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event - The number of gpios available depends on the package option. An invalid selection will be ignored - source = 0 selects gpio0 - . - . - source = 47 selects gpio47 - source = 48 selects qspi_ss - source = 49 selects qspi_sd0 - source = 50 selects qspi_sd1 - source = 51 selects qspi_sd2 - source = 52 selects qspi_sd3 - source = 53 selects qspi_sclk - level = 0 triggers the pwrup when the source is low - level = 1 triggers the pwrup when the source is high - 0x98 - 0x0000003F - - - RAW_STATUS - Value of selected gpio pin (only if enable == 1) - [10:10] - read-only - - - STATUS - Status of gpio wakeup. Write to 1 to clear a latched edge detect. - [9:9] - read-write - oneToClear - - - MODE - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. - [8:8] - read-write - - - level - 0 - - - edge - 1 - - - - - DIRECTION - [7:7] - read-write - - - low_falling - 0 - - - high_rising - 1 - - - - - ENABLE - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. - If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. - [6:6] - read-write - - - SOURCE - [5:0] - read-write - - - - - CURRENT_PWRUP_REQ - Indicates current powerup request state - pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab - 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET - 1 = pwrup0 - 2 = pwrup1 - 3 = pwrup2 - 4 = pwrup3 - 5 = coresight_pwrup - 6 = alarm_pwrup - 0x9C - 0x00000000 - - - CURRENT_PWRUP_REQ - [6:0] - read-only - - - - - LAST_SWCORE_PWRUP - Indicates which pwrup source triggered the last switched-core power up - 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET - 1 = pwrup0 - 2 = pwrup1 - 3 = pwrup2 - 4 = pwrup3 - 5 = coresight_pwrup - 6 = alarm_pwrup - 0xA0 - 0x00000000 - - - LAST_SWCORE_PWRUP - [6:0] - read-only - - - - - DBG_PWRCFG - 0xA4 - 0x00000000 - - - IGNORE - Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req - [0:0] - read-write - - - - - BOOTDIS - Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). - - If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. - - This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. - - Should be used in conjunction with the OTP BOOTDIS register. - 0xA8 - 0x00000000 - - - NEXT - This flag always ORs writes into its current contents. It can be set but not cleared by software. - - The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. - - This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling. - [1:1] - read-write - - - NOW - When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. - - The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. - [0:0] - read-write - oneToClear - - - - - DBGCONFIG - 0xAC - 0x00000000 - - - DP_INSTID - Configure DP instance ID for SWD multidrop selection. - Recommend that this is NOT changed until you require debug access in multi-chip environment - [3:0] - read-write - - - - - SCRATCH0 - Scratch register. Information persists in low power mode - 0xB0 - 0x00000000 - - - SCRATCH0 - [31:0] - read-write - - - - - SCRATCH1 - Scratch register. Information persists in low power mode - 0xB4 - 0x00000000 - - - SCRATCH1 - [31:0] - read-write - - - - - SCRATCH2 - Scratch register. Information persists in low power mode - 0xB8 - 0x00000000 - - - SCRATCH2 - [31:0] - read-write - - - - - SCRATCH3 - Scratch register. Information persists in low power mode - 0xBC - 0x00000000 - - - SCRATCH3 - [31:0] - read-write - - - - - SCRATCH4 - Scratch register. Information persists in low power mode - 0xC0 - 0x00000000 - - - SCRATCH4 - [31:0] - read-write - - - - - SCRATCH5 - Scratch register. Information persists in low power mode - 0xC4 - 0x00000000 - - - SCRATCH5 - [31:0] - read-write - - - - - SCRATCH6 - Scratch register. Information persists in low power mode - 0xC8 - 0x00000000 - - - SCRATCH6 - [31:0] - read-write - - - - - SCRATCH7 - Scratch register. Information persists in low power mode - 0xCC - 0x00000000 - - - SCRATCH7 - [31:0] - read-write - - - - - BOOT0 - Scratch register. Information persists in low power mode - 0xD0 - 0x00000000 - - - BOOT0 - [31:0] - read-write - - - - - BOOT1 - Scratch register. Information persists in low power mode - 0xD4 - 0x00000000 - - - BOOT1 - [31:0] - read-write - - - - - BOOT2 - Scratch register. Information persists in low power mode - 0xD8 - 0x00000000 - - - BOOT2 - [31:0] - read-write - - - - - BOOT3 - Scratch register. Information persists in low power mode - 0xDC - 0x00000000 - - - BOOT3 - [31:0] - read-write - - - - - INTR - Raw Interrupts - 0xE0 - 0x00000000 - - - PWRUP_WHILE_WAITING - Source is state.pwrup_while_waiting - [3:3] - read-only - - - STATE_REQ_IGNORED - Source is state.req_ignored - [2:2] - read-only - - - TIMER - [1:1] - read-only - - - VREG_OUTPUT_LOW - [0:0] - read-write - oneToClear - - - - - INTE - Interrupt Enable - 0xE4 - 0x00000000 - - - PWRUP_WHILE_WAITING - Source is state.pwrup_while_waiting - [3:3] - read-write - - - STATE_REQ_IGNORED - Source is state.req_ignored - [2:2] - read-write - - - TIMER - [1:1] - read-write - - - VREG_OUTPUT_LOW - [0:0] - read-write - - - - - INTF - Interrupt Force - 0xE8 - 0x00000000 - - - PWRUP_WHILE_WAITING - Source is state.pwrup_while_waiting - [3:3] - read-write - - - STATE_REQ_IGNORED - Source is state.req_ignored - [2:2] - read-write - - - TIMER - [1:1] - read-write - - - VREG_OUTPUT_LOW - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0xEC - 0x00000000 - - - PWRUP_WHILE_WAITING - Source is state.pwrup_while_waiting - [3:3] - read-only - - - STATE_REQ_IGNORED - Source is state.req_ignored - [2:2] - read-only - - - TIMER - [1:1] - read-only - - - VREG_OUTPUT_LOW - [0:0] - read-only - - - - - - - WATCHDOG - 0x400D8000 - - 0x0 - 0x2C - registers - - - - CTRL - Watchdog control - The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. - The watchdog can be triggered in software. - 0x0 - 0x07000000 - - - TRIGGER - Trigger a watchdog reset - [31:31] - write-only - - - ENABLE - When not enabled the watchdog timer is paused - [30:30] - read-write - - - PAUSE_DBG1 - Pause the watchdog timer when processor 1 is in debug mode - [26:26] - read-write - - - PAUSE_DBG0 - Pause the watchdog timer when processor 0 is in debug mode - [25:25] - read-write - - - PAUSE_JTAG - Pause the watchdog timer when JTAG is accessing the bus fabric - [24:24] - read-write - - - TIME - Indicates the time in usec before a watchdog reset will be triggered - [23:0] - read-only - - - - - LOAD - Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds. - 0x4 - 0x00000000 - - - LOAD - [23:0] - write-only - - - - - REASON - Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. - - Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition. - 0x8 - 0x00000000 - - - FORCE - [1:1] - read-only - - - TIMER - [0:0] - read-only - - - - - SCRATCH0 - Scratch register. Information persists through soft reset of the chip. - 0xC - 0x00000000 - - - SCRATCH0 - [31:0] - read-write - - - - - SCRATCH1 - Scratch register. Information persists through soft reset of the chip. - 0x10 - 0x00000000 - - - SCRATCH1 - [31:0] - read-write - - - - - SCRATCH2 - Scratch register. Information persists through soft reset of the chip. - 0x14 - 0x00000000 - - - SCRATCH2 - [31:0] - read-write - - - - - SCRATCH3 - Scratch register. Information persists through soft reset of the chip. - 0x18 - 0x00000000 - - - SCRATCH3 - [31:0] - read-write - - - - - SCRATCH4 - Scratch register. Information persists through soft reset of the chip. - 0x1C - 0x00000000 - - - SCRATCH4 - [31:0] - read-write - - - - - SCRATCH5 - Scratch register. Information persists through soft reset of the chip. - 0x20 - 0x00000000 - - - SCRATCH5 - [31:0] - read-write - - - - - SCRATCH6 - Scratch register. Information persists through soft reset of the chip. - 0x24 - 0x00000000 - - - SCRATCH6 - [31:0] - read-write - - - - - SCRATCH7 - Scratch register. Information persists through soft reset of the chip. - 0x28 - 0x00000000 - - - SCRATCH7 - [31:0] - read-write - - - - - - - DMA - DMA with separate read and write masters - 0x50000000 - - 0x0 - 0xBC8 - registers - - - DMA_IRQ_0 - 10 - - - DMA_IRQ_1 - 11 - - - DMA_IRQ_2 - 12 - - - DMA_IRQ_3 - 13 - - - - 16 - 0x40 - 0-15 - CH%s - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG - 0x0 - - CH_READ_ADDR - DMA Channel 0 Read Address pointer - 0x0 - 0x00000000 - - - CH0_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH_WRITE_ADDR - DMA Channel 0 Write Address pointer - 0x4 - 0x00000000 - - - CH0_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH_TRANS_COUNT - DMA Channel 0 Transfer Count - 0x8 - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH_CTRL_TRIG - DMA Channel 0 Control and Status - 0xC - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - TREQ_SEL - - PIO0_TX0 - Select PIO0's TX FIFO 0 as TREQ - 0 - - - PIO0_TX1 - Select PIO0's TX FIFO 1 as TREQ - 1 - - - PIO0_TX2 - Select PIO0's TX FIFO 2 as TREQ - 2 - - - PIO0_TX3 - Select PIO0's TX FIFO 3 as TREQ - 3 - - - PIO0_RX0 - Select PIO0's RX FIFO 0 as TREQ - 4 - - - PIO0_RX1 - Select PIO0's RX FIFO 1 as TREQ - 5 - - - PIO0_RX2 - Select PIO0's RX FIFO 2 as TREQ - 6 - - - PIO0_RX3 - Select PIO0's RX FIFO 3 as TREQ - 7 - - - PIO1_TX0 - Select PIO1's TX FIFO 0 as TREQ - 8 - - - PIO1_TX1 - Select PIO1's TX FIFO 1 as TREQ - 9 - - - PIO1_TX2 - Select PIO1's TX FIFO 2 as TREQ - 10 - - - PIO1_TX3 - Select PIO1's TX FIFO 3 as TREQ - 11 - - - PIO1_RX0 - Select PIO1's RX FIFO 0 as TREQ - 12 - - - PIO1_RX1 - Select PIO1's RX FIFO 1 as TREQ - 13 - - - PIO1_RX2 - Select PIO1's RX FIFO 2 as TREQ - 14 - - - PIO1_RX3 - Select PIO1's RX FIFO 3 as TREQ - 15 - - - PIO2_TX0 - Select PIO2's TX FIFO 0 as TREQ - 16 - - - PIO2_TX1 - Select PIO2's TX FIFO 1 as TREQ - 17 - - - PIO2_TX2 - Select PIO2's TX FIFO 2 as TREQ - 18 - - - PIO2_TX3 - Select PIO2's TX FIFO 3 as TREQ - 19 - - - PIO2_RX0 - Select PIO2's RX FIFO 0 as TREQ - 20 - - - PIO2_RX1 - Select PIO2's RX FIFO 1 as TREQ - 21 - - - PIO2_RX2 - Select PIO2's RX FIFO 2 as TREQ - 22 - - - PIO2_RX3 - Select PIO2's RX FIFO 3 as TREQ - 23 - - - SPI0_TX - Select SPI0's TX FIFO as TREQ - 24 - - - SPI0_RX - Select SPI0's RX FIFO as TREQ - 25 - - - SPI1_TX - Select SPI1's TX FIFO as TREQ - 26 - - - SPI1_RX - Select SPI1's RX FIFO as TREQ - 27 - - - UART0_TX - Select UART0's TX FIFO as TREQ - 28 - - - UART0_RX - Select UART0's RX FIFO as TREQ - 29 - - - UART1_TX - Select UART1's TX FIFO as TREQ - 30 - - - UART1_RX - Select UART1's RX FIFO as TREQ - 31 - - - PWM_WRAP0 - Select PWM Counter 0's Wrap Value as TREQ - 32 - - - PWM_WRAP1 - Select PWM Counter 1's Wrap Value as TREQ - 33 - - - PWM_WRAP2 - Select PWM Counter 2's Wrap Value as TREQ - 34 - - - PWM_WRAP3 - Select PWM Counter 3's Wrap Value as TREQ - 35 - - - PWM_WRAP4 - Select PWM Counter 4's Wrap Value as TREQ - 36 - - - PWM_WRAP5 - Select PWM Counter 5's Wrap Value as TREQ - 37 - - - PWM_WRAP6 - Select PWM Counter 6's Wrap Value as TREQ - 38 - - - PWM_WRAP7 - Select PWM Counter 7's Wrap Value as TREQ - 39 - - - PWM_WRAP8 - Select PWM Counter 8's Wrap Value as TREQ - 40 - - - PWM_WRAP9 - Select PWM Counter 9's Wrap Value as TREQ - 41 - - - PWM_WRAP10 - Select PWM Counter 10's Wrap Value as TREQ - 42 - - - PWM_WRAP11 - Select PWM Counter 11's Wrap Value as TREQ - 43 - - - I2C0_TX - Select I2C0's TX FIFO as TREQ - 44 - - - I2C0_RX - Select I2C0's RX FIFO as TREQ - 45 - - - I2C1_TX - Select I2C1's TX FIFO as TREQ - 46 - - - I2C1_RX - Select I2C1's RX FIFO as TREQ - 47 - - - ADC - Select ADC as TREQ - 48 - - - XIP_STREAM - Select XIP_STREAM as TREQ - 49 - - - XIP_QMITX - Select XIP_QMI's TX FIFO as TREQ - 50 - - - XIP_QMIRX - Select XIP_QMI's RX FIFO as TREQ - 51 - - - HSTX - Select HSTX as TREQ - 52 - - - CORESIGHT - Select CORESIGHT as TREQ - 53 - - - SHA256 - Select SHA256 as TREQ - 54 - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH_AL1_CTRL - DMA Channel 0 Control and Status - 0x10 - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - TREQ_SEL - - PIO0_TX0 - Select PIO0's TX FIFO 0 as TREQ - 0 - - - PIO0_TX1 - Select PIO0's TX FIFO 1 as TREQ - 1 - - - PIO0_TX2 - Select PIO0's TX FIFO 2 as TREQ - 2 - - - PIO0_TX3 - Select PIO0's TX FIFO 3 as TREQ - 3 - - - PIO0_RX0 - Select PIO0's RX FIFO 0 as TREQ - 4 - - - PIO0_RX1 - Select PIO0's RX FIFO 1 as TREQ - 5 - - - PIO0_RX2 - Select PIO0's RX FIFO 2 as TREQ - 6 - - - PIO0_RX3 - Select PIO0's RX FIFO 3 as TREQ - 7 - - - PIO1_TX0 - Select PIO1's TX FIFO 0 as TREQ - 8 - - - PIO1_TX1 - Select PIO1's TX FIFO 1 as TREQ - 9 - - - PIO1_TX2 - Select PIO1's TX FIFO 2 as TREQ - 10 - - - PIO1_TX3 - Select PIO1's TX FIFO 3 as TREQ - 11 - - - PIO1_RX0 - Select PIO1's RX FIFO 0 as TREQ - 12 - - - PIO1_RX1 - Select PIO1's RX FIFO 1 as TREQ - 13 - - - PIO1_RX2 - Select PIO1's RX FIFO 2 as TREQ - 14 - - - PIO1_RX3 - Select PIO1's RX FIFO 3 as TREQ - 15 - - - PIO2_TX0 - Select PIO2's TX FIFO 0 as TREQ - 16 - - - PIO2_TX1 - Select PIO2's TX FIFO 1 as TREQ - 17 - - - PIO2_TX2 - Select PIO2's TX FIFO 2 as TREQ - 18 - - - PIO2_TX3 - Select PIO2's TX FIFO 3 as TREQ - 19 - - - PIO2_RX0 - Select PIO2's RX FIFO 0 as TREQ - 20 - - - PIO2_RX1 - Select PIO2's RX FIFO 1 as TREQ - 21 - - - PIO2_RX2 - Select PIO2's RX FIFO 2 as TREQ - 22 - - - PIO2_RX3 - Select PIO2's RX FIFO 3 as TREQ - 23 - - - SPI0_TX - Select SPI0's TX FIFO as TREQ - 24 - - - SPI0_RX - Select SPI0's RX FIFO as TREQ - 25 - - - SPI1_TX - Select SPI1's TX FIFO as TREQ - 26 - - - SPI1_RX - Select SPI1's RX FIFO as TREQ - 27 - - - UART0_TX - Select UART0's TX FIFO as TREQ - 28 - - - UART0_RX - Select UART0's RX FIFO as TREQ - 29 - - - UART1_TX - Select UART1's TX FIFO as TREQ - 30 - - - UART1_RX - Select UART1's RX FIFO as TREQ - 31 - - - PWM_WRAP0 - Select PWM Counter 0's Wrap Value as TREQ - 32 - - - PWM_WRAP1 - Select PWM Counter 1's Wrap Value as TREQ - 33 - - - PWM_WRAP2 - Select PWM Counter 2's Wrap Value as TREQ - 34 - - - PWM_WRAP3 - Select PWM Counter 3's Wrap Value as TREQ - 35 - - - PWM_WRAP4 - Select PWM Counter 4's Wrap Value as TREQ - 36 - - - PWM_WRAP5 - Select PWM Counter 5's Wrap Value as TREQ - 37 - - - PWM_WRAP6 - Select PWM Counter 6's Wrap Value as TREQ - 38 - - - PWM_WRAP7 - Select PWM Counter 7's Wrap Value as TREQ - 39 - - - PWM_WRAP8 - Select PWM Counter 8's Wrap Value as TREQ - 40 - - - PWM_WRAP9 - Select PWM Counter 9's Wrap Value as TREQ - 41 - - - PWM_WRAP10 - Select PWM Counter 10's Wrap Value as TREQ - 42 - - - PWM_WRAP11 - Select PWM Counter 11's Wrap Value as TREQ - 43 - - - I2C0_TX - Select I2C0's TX FIFO as TREQ - 44 - - - I2C0_RX - Select I2C0's RX FIFO as TREQ - 45 - - - I2C1_TX - Select I2C1's TX FIFO as TREQ - 46 - - - I2C1_RX - Select I2C1's RX FIFO as TREQ - 47 - - - ADC - Select ADC as TREQ - 48 - - - XIP_STREAM - Select XIP_STREAM as TREQ - 49 - - - XIP_QMITX - Select XIP_QMI's TX FIFO as TREQ - 50 - - - XIP_QMIRX - Select XIP_QMI's RX FIFO as TREQ - 51 - - - HSTX - Select HSTX as TREQ - 52 - - - CORESIGHT - Select CORESIGHT as TREQ - 53 - - - SHA256 - Select SHA256 as TREQ - 54 - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH_AL1_READ_ADDR - Alias for channel 0 READ_ADDR register - 0x14 - 0x00000000 - - - CH0_AL1_READ_ADDR - [31:0] - read-write - - - - - CH_AL1_WRITE_ADDR - Alias for channel 0 WRITE_ADDR register - 0x18 - 0x00000000 - - - CH0_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH_AL1_TRANS_COUNT_TRIG - Alias for channel 0 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x1C - 0x00000000 - - - CH0_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH_AL2_CTRL - DMA Channel 0 Control and Status - 0x20 - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - TREQ_SEL - - PIO0_TX0 - Select PIO0's TX FIFO 0 as TREQ - 0 - - - PIO0_TX1 - Select PIO0's TX FIFO 1 as TREQ - 1 - - - PIO0_TX2 - Select PIO0's TX FIFO 2 as TREQ - 2 - - - PIO0_TX3 - Select PIO0's TX FIFO 3 as TREQ - 3 - - - PIO0_RX0 - Select PIO0's RX FIFO 0 as TREQ - 4 - - - PIO0_RX1 - Select PIO0's RX FIFO 1 as TREQ - 5 - - - PIO0_RX2 - Select PIO0's RX FIFO 2 as TREQ - 6 - - - PIO0_RX3 - Select PIO0's RX FIFO 3 as TREQ - 7 - - - PIO1_TX0 - Select PIO1's TX FIFO 0 as TREQ - 8 - - - PIO1_TX1 - Select PIO1's TX FIFO 1 as TREQ - 9 - - - PIO1_TX2 - Select PIO1's TX FIFO 2 as TREQ - 10 - - - PIO1_TX3 - Select PIO1's TX FIFO 3 as TREQ - 11 - - - PIO1_RX0 - Select PIO1's RX FIFO 0 as TREQ - 12 - - - PIO1_RX1 - Select PIO1's RX FIFO 1 as TREQ - 13 - - - PIO1_RX2 - Select PIO1's RX FIFO 2 as TREQ - 14 - - - PIO1_RX3 - Select PIO1's RX FIFO 3 as TREQ - 15 - - - PIO2_TX0 - Select PIO2's TX FIFO 0 as TREQ - 16 - - - PIO2_TX1 - Select PIO2's TX FIFO 1 as TREQ - 17 - - - PIO2_TX2 - Select PIO2's TX FIFO 2 as TREQ - 18 - - - PIO2_TX3 - Select PIO2's TX FIFO 3 as TREQ - 19 - - - PIO2_RX0 - Select PIO2's RX FIFO 0 as TREQ - 20 - - - PIO2_RX1 - Select PIO2's RX FIFO 1 as TREQ - 21 - - - PIO2_RX2 - Select PIO2's RX FIFO 2 as TREQ - 22 - - - PIO2_RX3 - Select PIO2's RX FIFO 3 as TREQ - 23 - - - SPI0_TX - Select SPI0's TX FIFO as TREQ - 24 - - - SPI0_RX - Select SPI0's RX FIFO as TREQ - 25 - - - SPI1_TX - Select SPI1's TX FIFO as TREQ - 26 - - - SPI1_RX - Select SPI1's RX FIFO as TREQ - 27 - - - UART0_TX - Select UART0's TX FIFO as TREQ - 28 - - - UART0_RX - Select UART0's RX FIFO as TREQ - 29 - - - UART1_TX - Select UART1's TX FIFO as TREQ - 30 - - - UART1_RX - Select UART1's RX FIFO as TREQ - 31 - - - PWM_WRAP0 - Select PWM Counter 0's Wrap Value as TREQ - 32 - - - PWM_WRAP1 - Select PWM Counter 1's Wrap Value as TREQ - 33 - - - PWM_WRAP2 - Select PWM Counter 2's Wrap Value as TREQ - 34 - - - PWM_WRAP3 - Select PWM Counter 3's Wrap Value as TREQ - 35 - - - PWM_WRAP4 - Select PWM Counter 4's Wrap Value as TREQ - 36 - - - PWM_WRAP5 - Select PWM Counter 5's Wrap Value as TREQ - 37 - - - PWM_WRAP6 - Select PWM Counter 6's Wrap Value as TREQ - 38 - - - PWM_WRAP7 - Select PWM Counter 7's Wrap Value as TREQ - 39 - - - PWM_WRAP8 - Select PWM Counter 8's Wrap Value as TREQ - 40 - - - PWM_WRAP9 - Select PWM Counter 9's Wrap Value as TREQ - 41 - - - PWM_WRAP10 - Select PWM Counter 10's Wrap Value as TREQ - 42 - - - PWM_WRAP11 - Select PWM Counter 11's Wrap Value as TREQ - 43 - - - I2C0_TX - Select I2C0's TX FIFO as TREQ - 44 - - - I2C0_RX - Select I2C0's RX FIFO as TREQ - 45 - - - I2C1_TX - Select I2C1's TX FIFO as TREQ - 46 - - - I2C1_RX - Select I2C1's RX FIFO as TREQ - 47 - - - ADC - Select ADC as TREQ - 48 - - - XIP_STREAM - Select XIP_STREAM as TREQ - 49 - - - XIP_QMITX - Select XIP_QMI's TX FIFO as TREQ - 50 - - - XIP_QMIRX - Select XIP_QMI's RX FIFO as TREQ - 51 - - - HSTX - Select HSTX as TREQ - 52 - - - CORESIGHT - Select CORESIGHT as TREQ - 53 - - - SHA256 - Select SHA256 as TREQ - 54 - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH_AL2_TRANS_COUNT - Alias for channel 0 TRANS_COUNT register - 0x24 - 0x00000000 - - - CH0_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH_AL2_READ_ADDR - Alias for channel 0 READ_ADDR register - 0x28 - 0x00000000 - - - CH0_AL2_READ_ADDR - [31:0] - read-write - - - - - CH_AL2_WRITE_ADDR_TRIG - Alias for channel 0 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x2C - 0x00000000 - - - CH0_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH_AL3_CTRL - DMA Channel 0 Control and Status - 0x30 - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - TREQ_SEL - - PIO0_TX0 - Select PIO0's TX FIFO 0 as TREQ - 0 - - - PIO0_TX1 - Select PIO0's TX FIFO 1 as TREQ - 1 - - - PIO0_TX2 - Select PIO0's TX FIFO 2 as TREQ - 2 - - - PIO0_TX3 - Select PIO0's TX FIFO 3 as TREQ - 3 - - - PIO0_RX0 - Select PIO0's RX FIFO 0 as TREQ - 4 - - - PIO0_RX1 - Select PIO0's RX FIFO 1 as TREQ - 5 - - - PIO0_RX2 - Select PIO0's RX FIFO 2 as TREQ - 6 - - - PIO0_RX3 - Select PIO0's RX FIFO 3 as TREQ - 7 - - - PIO1_TX0 - Select PIO1's TX FIFO 0 as TREQ - 8 - - - PIO1_TX1 - Select PIO1's TX FIFO 1 as TREQ - 9 - - - PIO1_TX2 - Select PIO1's TX FIFO 2 as TREQ - 10 - - - PIO1_TX3 - Select PIO1's TX FIFO 3 as TREQ - 11 - - - PIO1_RX0 - Select PIO1's RX FIFO 0 as TREQ - 12 - - - PIO1_RX1 - Select PIO1's RX FIFO 1 as TREQ - 13 - - - PIO1_RX2 - Select PIO1's RX FIFO 2 as TREQ - 14 - - - PIO1_RX3 - Select PIO1's RX FIFO 3 as TREQ - 15 - - - PIO2_TX0 - Select PIO2's TX FIFO 0 as TREQ - 16 - - - PIO2_TX1 - Select PIO2's TX FIFO 1 as TREQ - 17 - - - PIO2_TX2 - Select PIO2's TX FIFO 2 as TREQ - 18 - - - PIO2_TX3 - Select PIO2's TX FIFO 3 as TREQ - 19 - - - PIO2_RX0 - Select PIO2's RX FIFO 0 as TREQ - 20 - - - PIO2_RX1 - Select PIO2's RX FIFO 1 as TREQ - 21 - - - PIO2_RX2 - Select PIO2's RX FIFO 2 as TREQ - 22 - - - PIO2_RX3 - Select PIO2's RX FIFO 3 as TREQ - 23 - - - SPI0_TX - Select SPI0's TX FIFO as TREQ - 24 - - - SPI0_RX - Select SPI0's RX FIFO as TREQ - 25 - - - SPI1_TX - Select SPI1's TX FIFO as TREQ - 26 - - - SPI1_RX - Select SPI1's RX FIFO as TREQ - 27 - - - UART0_TX - Select UART0's TX FIFO as TREQ - 28 - - - UART0_RX - Select UART0's RX FIFO as TREQ - 29 - - - UART1_TX - Select UART1's TX FIFO as TREQ - 30 - - - UART1_RX - Select UART1's RX FIFO as TREQ - 31 - - - PWM_WRAP0 - Select PWM Counter 0's Wrap Value as TREQ - 32 - - - PWM_WRAP1 - Select PWM Counter 1's Wrap Value as TREQ - 33 - - - PWM_WRAP2 - Select PWM Counter 2's Wrap Value as TREQ - 34 - - - PWM_WRAP3 - Select PWM Counter 3's Wrap Value as TREQ - 35 - - - PWM_WRAP4 - Select PWM Counter 4's Wrap Value as TREQ - 36 - - - PWM_WRAP5 - Select PWM Counter 5's Wrap Value as TREQ - 37 - - - PWM_WRAP6 - Select PWM Counter 6's Wrap Value as TREQ - 38 - - - PWM_WRAP7 - Select PWM Counter 7's Wrap Value as TREQ - 39 - - - PWM_WRAP8 - Select PWM Counter 8's Wrap Value as TREQ - 40 - - - PWM_WRAP9 - Select PWM Counter 9's Wrap Value as TREQ - 41 - - - PWM_WRAP10 - Select PWM Counter 10's Wrap Value as TREQ - 42 - - - PWM_WRAP11 - Select PWM Counter 11's Wrap Value as TREQ - 43 - - - I2C0_TX - Select I2C0's TX FIFO as TREQ - 44 - - - I2C0_RX - Select I2C0's RX FIFO as TREQ - 45 - - - I2C1_TX - Select I2C1's TX FIFO as TREQ - 46 - - - I2C1_RX - Select I2C1's RX FIFO as TREQ - 47 - - - ADC - Select ADC as TREQ - 48 - - - XIP_STREAM - Select XIP_STREAM as TREQ - 49 - - - XIP_QMITX - Select XIP_QMI's TX FIFO as TREQ - 50 - - - XIP_QMIRX - Select XIP_QMI's RX FIFO as TREQ - 51 - - - HSTX - Select HSTX as TREQ - 52 - - - CORESIGHT - Select CORESIGHT as TREQ - 53 - - - SHA256 - Select SHA256 as TREQ - 54 - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH_AL3_WRITE_ADDR - Alias for channel 0 WRITE_ADDR register - 0x34 - 0x00000000 - - - CH0_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH_AL3_TRANS_COUNT - Alias for channel 0 TRANS_COUNT register - 0x38 - 0x00000000 - - - CH0_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH_AL3_READ_ADDR_TRIG - Alias for channel 0 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x3C - 0x00000000 - - - CH0_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - - INTR - Interrupt Status (raw) - 0x400 - 0x00000000 - - - INTR - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. - [15:0] - read-write - oneToClear - - - - - INTE0 - Interrupt Enables for IRQ 0 - 0x404 - 0x00000000 - - - INTE0 - Set bit n to pass interrupts from channel n to DMA IRQ 0. - - Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0. - [15:0] - read-write - - - - - INTF0 - Force Interrupts - 0x408 - 0x00000000 - - - INTF0 - Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared. - [15:0] - read-write - - - - - INTS0 - Interrupt Status for IRQ 0 - 0x40C - 0x00000000 - - - INTS0 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. - Channel interrupts can be cleared by writing a bit mask here. - - Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes. - [15:0] - read-write - oneToClear - - - - - INTR1 - Interrupt Status (raw) - 0x410 - 0x00000000 - - - INTR1 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. - [15:0] - read-write - oneToClear - - - - - INTE1 - Interrupt Enables for IRQ 1 - 0x414 - 0x00000000 - - - INTE1 - Set bit n to pass interrupts from channel n to DMA IRQ 1. - - Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1. - [15:0] - read-write - - - - - INTF1 - Force Interrupts - 0x418 - 0x00000000 - - - INTF1 - Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared. - [15:0] - read-write - - - - - INTS1 - Interrupt Status for IRQ 1 - 0x41C - 0x00000000 - - - INTS1 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. - Channel interrupts can be cleared by writing a bit mask here. - - Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes. - [15:0] - read-write - oneToClear - - - - - INTR2 - Interrupt Status (raw) - 0x420 - 0x00000000 - - - INTR2 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. - [15:0] - read-write - oneToClear - - - - - INTE2 - Interrupt Enables for IRQ 2 - 0x424 - 0x00000000 - - - INTE2 - Set bit n to pass interrupts from channel n to DMA IRQ 2. - - Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2. - [15:0] - read-write - - - - - INTF2 - Force Interrupts - 0x428 - 0x00000000 - - - INTF2 - Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared. - [15:0] - read-write - - - - - INTS2 - Interrupt Status for IRQ 2 - 0x42C - 0x00000000 - - - INTS2 - Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. - Channel interrupts can be cleared by writing a bit mask here. - - Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes. - [15:0] - read-write - oneToClear - - - - - INTR3 - Interrupt Status (raw) - 0x430 - 0x00000000 - - - INTR3 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. - [15:0] - read-write - oneToClear - - - - - INTE3 - Interrupt Enables for IRQ 3 - 0x434 - 0x00000000 - - - INTE3 - Set bit n to pass interrupts from channel n to DMA IRQ 3. - - Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3. - [15:0] - read-write - - - - - INTF3 - Force Interrupts - 0x438 - 0x00000000 - - - INTF3 - Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared. - [15:0] - read-write - - - - - INTS3 - Interrupt Status for IRQ 3 - 0x43C - 0x00000000 - - - INTS3 - Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. - Channel interrupts can be cleared by writing a bit mask here. - - Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes. - [15:0] - read-write - oneToClear - - - - - TIMER0 - Pacing (X/Y) fractional timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x440 - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER1 - Pacing (X/Y) fractional timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x444 - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER2 - Pacing (X/Y) fractional timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x448 - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER3 - Pacing (X/Y) fractional timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x44C - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - MULTI_CHAN_TRIGGER - Trigger one or more channels simultaneously - 0x450 - 0x00000000 - - - MULTI_CHAN_TRIGGER - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. - [15:0] - write-only - - - - - SNIFF_CTRL - Sniffer Control - 0x454 - 0x00000000 - - - OUT_INV - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. - [11:11] - read-write - - - OUT_REV - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. - [10:10] - read-write - - - BSWAP - Locally perform a byte reverse on the sniffed data, before feeding into checksum. - - Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. - [9:9] - read-write - - - CALC - [8:5] - read-write - - - CRC32 - Calculate a CRC-32 (IEEE802.3 polynomial) - 0 - - - CRC32R - Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data - 1 - - - CRC16 - Calculate a CRC-16-CCITT - 2 - - - CRC16R - Calculate a CRC-16-CCITT with bit reversed data - 3 - - - EVEN - XOR reduction over all data. == 1 if the total 1 population count is odd. - 14 - - - SUM - Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) - 15 - - - - - DMACH - DMA channel for Sniffer to observe - [4:1] - read-write - - - EN - Enable sniffer - [0:0] - read-write - - - - - SNIFF_DATA - Data accumulator for sniff hardware - 0x458 - 0x00000000 - - - SNIFF_DATA - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. - [31:0] - read-write - - - - - FIFO_LEVELS - Debug RAF, WAF, TDF levels - 0x460 - 0x00000000 - - - RAF_LVL - Current Read-Address-FIFO fill level - [23:16] - read-only - - - WAF_LVL - Current Write-Address-FIFO fill level - [15:8] - read-only - - - TDF_LVL - Current Transfer-Data-FIFO fill level - [7:0] - read-only - - - - - CHAN_ABORT - Abort an in-progress transfer sequence on one or more channels - 0x464 - 0x00000000 - - - CHAN_ABORT - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. - - After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. - [15:0] - write-only - - - - - N_CHANNELS - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. - 0x468 - 0x00000000 - - - N_CHANNELS - [4:0] - read-only - - - - - SECCFG_CH0 - Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x480 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH1 - Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x484 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH2 - Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x488 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH3 - Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x48C - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH4 - Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x490 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH5 - Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x494 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH6 - Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x498 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH7 - Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x49C - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH8 - Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x4A0 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH9 - Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x4A4 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH10 - Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x4A8 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH11 - Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x4AC - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH12 - Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x4B0 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH13 - Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x4B4 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH14 - Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x4B8 - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH15 - Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x4BC - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_IRQ0 - Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. - 0x4C0 - 0x00000003 - - - S - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. - - If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. - [1:1] - read-write - - - P - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. - - If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. - [0:0] - read-write - - - - - SECCFG_IRQ1 - Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. - 0x4C4 - 0x00000003 - - - S - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. - - If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. - [1:1] - read-write - - - P - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. - - If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. - [0:0] - read-write - - - - - SECCFG_IRQ2 - Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. - 0x4C8 - 0x00000003 - - - S - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. - - If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. - [1:1] - read-write - - - P - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. - - If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. - [0:0] - read-write - - - - - SECCFG_IRQ3 - Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. - 0x4CC - 0x00000003 - - - S - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. - - If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. - [1:1] - read-write - - - P - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. - - If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. - [0:0] - read-write - - - - - SECCFG_MISC - Miscellaneous security configuration - 0x4D0 - 0x000003FF - - - TIMER3_S - If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. - [9:9] - read-write - - - TIMER3_P - If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels. - [8:8] - read-write - - - TIMER2_S - If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels. - [7:7] - read-write - - - TIMER2_P - If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels. - [6:6] - read-write - - - TIMER1_S - If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels. - [5:5] - read-write - - - TIMER1_P - If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels. - [4:4] - read-write - - - TIMER0_S - If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels. - [3:3] - read-write - - - TIMER0_P - If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels. - [2:2] - read-write - - - SNIFF_S - If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. - - If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels. - [1:1] - read-write - - - SNIFF_P - If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. - - If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels. - [0:0] - read-write - - - - - MPU_CTRL - Control register for DMA MPU. Accessible only from a Privileged context. - 0x500 - 0x00000000 - - - NS_HIDE_ADDR - By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map. - [3:3] - read-write - - - S - Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0) - [2:2] - read-write - - - P - Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0) - [1:1] - read-write - - - - - MPU_BAR0 - Base address register for MPU region 0. Writable only from a Secure, Privileged context. - 0x504 - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR0 - Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x508 - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR1 - Base address register for MPU region 1. Writable only from a Secure, Privileged context. - 0x50C - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR1 - Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x510 - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR2 - Base address register for MPU region 2. Writable only from a Secure, Privileged context. - 0x514 - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR2 - Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x518 - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR3 - Base address register for MPU region 3. Writable only from a Secure, Privileged context. - 0x51C - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR3 - Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x520 - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR4 - Base address register for MPU region 4. Writable only from a Secure, Privileged context. - 0x524 - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR4 - Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x528 - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR5 - Base address register for MPU region 5. Writable only from a Secure, Privileged context. - 0x52C - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR5 - Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x530 - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR6 - Base address register for MPU region 6. Writable only from a Secure, Privileged context. - 0x534 - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR6 - Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x538 - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR7 - Base address register for MPU region 7. Writable only from a Secure, Privileged context. - 0x53C - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR7 - Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x540 - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - CH0_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x800 - 0x00000000 - - - CH0_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH0_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x804 - 0x00000000 - - - CH0_DBG_TCR - [31:0] - read-only - - - - - CH1_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x840 - 0x00000000 - - - CH1_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH1_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x844 - 0x00000000 - - - CH1_DBG_TCR - [31:0] - read-only - - - - - CH2_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x880 - 0x00000000 - - - CH2_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH2_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x884 - 0x00000000 - - - CH2_DBG_TCR - [31:0] - read-only - - - - - CH3_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x8C0 - 0x00000000 - - - CH3_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH3_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x8C4 - 0x00000000 - - - CH3_DBG_TCR - [31:0] - read-only - - - - - CH4_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x900 - 0x00000000 - - - CH4_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH4_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x904 - 0x00000000 - - - CH4_DBG_TCR - [31:0] - read-only - - - - - CH5_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x940 - 0x00000000 - - - CH5_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH5_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x944 - 0x00000000 - - - CH5_DBG_TCR - [31:0] - read-only - - - - - CH6_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x980 - 0x00000000 - - - CH6_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH6_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x984 - 0x00000000 - - - CH6_DBG_TCR - [31:0] - read-only - - - - - CH7_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x9C0 - 0x00000000 - - - CH7_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH7_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x9C4 - 0x00000000 - - - CH7_DBG_TCR - [31:0] - read-only - - - - - CH8_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xA00 - 0x00000000 - - - CH8_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH8_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xA04 - 0x00000000 - - - CH8_DBG_TCR - [31:0] - read-only - - - - - CH9_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xA40 - 0x00000000 - - - CH9_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH9_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xA44 - 0x00000000 - - - CH9_DBG_TCR - [31:0] - read-only - - - - - CH10_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xA80 - 0x00000000 - - - CH10_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH10_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xA84 - 0x00000000 - - - CH10_DBG_TCR - [31:0] - read-only - - - - - CH11_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xAC0 - 0x00000000 - - - CH11_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH11_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xAC4 - 0x00000000 - - - CH11_DBG_TCR - [31:0] - read-only - - - - - CH12_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xB00 - 0x00000000 - - - CH12_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH12_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xB04 - 0x00000000 - - - CH12_DBG_TCR - [31:0] - read-only - - - - - CH13_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xB40 - 0x00000000 - - - CH13_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH13_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xB44 - 0x00000000 - - - CH13_DBG_TCR - [31:0] - read-only - - - - - CH14_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xB80 - 0x00000000 - - - CH14_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH14_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xB84 - 0x00000000 - - - CH14_DBG_TCR - [31:0] - read-only - - - - - CH15_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xBC0 - 0x00000000 - - - CH15_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH15_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xBC4 - 0x00000000 - - - CH15_DBG_TCR - [31:0] - read-only - - - - - - - TIMER0 - Controls time and alarms - - time is a 64 bit value indicating the time since power-on - - timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr - - An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing - 0x400B0000 - - 0x0 - 0x4C - registers - - - TIMER0_IRQ_0 - 0 - - - TIMER0_IRQ_1 - 1 - - - TIMER0_IRQ_2 - 2 - - - TIMER0_IRQ_3 - 3 - - - - TIMEHW - Write to bits 63:32 of time always write timelw before timehw - 0x0 - 0x00000000 - - - TIMEHW - [31:0] - write-only - - - - - TIMELW - Write to bits 31:0 of time writes do not get copied to time until timehw is written - 0x4 - 0x00000000 - - - TIMELW - [31:0] - write-only - - - - - TIMEHR - Read from bits 63:32 of time always read timelr before timehr - 0x8 - 0x00000000 - - - TIMEHR - [31:0] - read-only - - - - - TIMELR - Read from bits 31:0 of time - 0xC - 0x00000000 - - - TIMELR - [31:0] - read-only - modify - - - - - ALARM0 - Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. - 0x10 - 0x00000000 - - - ALARM0 - [31:0] - read-write - - - - - ALARM1 - Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. - 0x14 - 0x00000000 - - - ALARM1 - [31:0] - read-write - - - - - ALARM2 - Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. - 0x18 - 0x00000000 - - - ALARM2 - [31:0] - read-write - - - - - ALARM3 - Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. - 0x1C - 0x00000000 - - - ALARM3 - [31:0] - read-write - - - - - ARMED - Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. - 0x20 - 0x00000000 - - - ARMED - [3:0] - read-write - oneToClear - - - - - TIMERAWH - Raw read from bits 63:32 of time (no side effects) - 0x24 - 0x00000000 - - - TIMERAWH - [31:0] - read-only - - - - - TIMERAWL - Raw read from bits 31:0 of time (no side effects) - 0x28 - 0x00000000 - - - TIMERAWL - [31:0] - read-only - - - - - DBGPAUSE - Set bits high to enable pause when the corresponding debug ports are active - 0x2C - 0x00000007 - - - DBG1 - Pause when processor 1 is in debug mode - [2:2] - read-write - - - DBG0 - Pause when processor 0 is in debug mode - [1:1] - read-write - - - - - PAUSE - Set high to pause the timer - 0x30 - 0x00000000 - - - PAUSE - [0:0] - read-write - - - - - LOCKED - Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) - 0x34 - 0x00000000 - - - LOCKED - [0:0] - read-write - - - - - SOURCE - Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead. - 0x38 - 0x00000000 - - - CLK_SYS - [0:0] - read-write - - - TICK - 0 - - - CLK_SYS - 1 - - - - - - - INTR - Raw Interrupts - 0x3C - 0x00000000 - - - ALARM_3 - [3:3] - read-write - oneToClear - - - ALARM_2 - [2:2] - read-write - oneToClear - - - ALARM_1 - [1:1] - read-write - oneToClear - - - ALARM_0 - [0:0] - read-write - oneToClear - - - - - INTE - Interrupt Enable - 0x40 - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x44 - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x48 - 0x00000000 - - - ALARM_3 - [3:3] - read-only - - - ALARM_2 - [2:2] - read-only - - - ALARM_1 - [1:1] - read-only - - - ALARM_0 - [0:0] - read-only - - - - - - - TIMER1 - 0x400B8000 - - TIMER1_IRQ_0 - 4 - - - TIMER1_IRQ_1 - 5 - - - TIMER1_IRQ_2 - 6 - - - TIMER1_IRQ_3 - 7 - - - - PWM - Simple PWM - 0x400A8000 - - 0x0 - 0x110 - registers - - - PWM_IRQ_WRAP_0 - 8 - - - PWM_IRQ_WRAP_1 - 9 - - - - 12 - 0x14 - 0-11 - CH%s - Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP - 0x0 - - CC - Counter compare values - 0xC - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CSR - Control and status register - 0x0 - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - Free-running counting at rate dictated by fractional divider - 0 - - - level - Fractional divider operation is gated by the PWM B pin. - 1 - - - rise - Counter advances with each rising edge of the PWM B pin. - 2 - - - fall - Counter advances with each falling edge of the PWM B pin. - 3 - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CTR - Direct access to the PWM counter - 0x8 - 0x00000000 - - - CTR - [15:0] - read-write - - - - - DIV - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x4 - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - TOP - Counter wrap value - 0x10 - 0x0000FFFF - - - TOP - [15:0] - read-write - - - - - - EN - This register aliases the CSR_EN bits for all channels. - Writing to this register allows multiple channels to be enabled - or disabled simultaneously, so they can run in perfect sync. - For each channel, there is only one physical EN register bit, - which can be accessed through here or CHx_CSR. - 0xF0 - 0x00000000 - - - CH11 - [11:11] - read-write - - - CH10 - [10:10] - read-write - - - CH9 - [9:9] - read-write - - - CH8 - [8:8] - read-write - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTR - Raw Interrupts - 0xF4 - 0x00000000 - - - CH11 - [11:11] - read-write - oneToClear - - - CH10 - [10:10] - read-write - oneToClear - - - CH9 - [9:9] - read-write - oneToClear - - - CH8 - [8:8] - read-write - oneToClear - - - CH7 - [7:7] - read-write - oneToClear - - - CH6 - [6:6] - read-write - oneToClear - - - CH5 - [5:5] - read-write - oneToClear - - - CH4 - [4:4] - read-write - oneToClear - - - CH3 - [3:3] - read-write - oneToClear - - - CH2 - [2:2] - read-write - oneToClear - - - CH1 - [1:1] - read-write - oneToClear - - - CH0 - [0:0] - read-write - oneToClear - - - - - IRQ0_INTE - Interrupt Enable for irq0 - 0xF8 - 0x00000000 - - - CH11 - [11:11] - read-write - - - CH10 - [10:10] - read-write - - - CH9 - [9:9] - read-write - - - CH8 - [8:8] - read-write - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - IRQ0_INTF - Interrupt Force for irq0 - 0xFC - 0x00000000 - - - CH11 - [11:11] - read-write - - - CH10 - [10:10] - read-write - - - CH9 - [9:9] - read-write - - - CH8 - [8:8] - read-write - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - IRQ0_INTS - Interrupt status after masking & forcing for irq0 - 0x100 - 0x00000000 - - - CH11 - [11:11] - read-only - - - CH10 - [10:10] - read-only - - - CH9 - [9:9] - read-only - - - CH8 - [8:8] - read-only - - - CH7 - [7:7] - read-only - - - CH6 - [6:6] - read-only - - - CH5 - [5:5] - read-only - - - CH4 - [4:4] - read-only - - - CH3 - [3:3] - read-only - - - CH2 - [2:2] - read-only - - - CH1 - [1:1] - read-only - - - CH0 - [0:0] - read-only - - - - - IRQ1_INTE - Interrupt Enable for irq1 - 0x104 - 0x00000000 - - - CH11 - [11:11] - read-write - - - CH10 - [10:10] - read-write - - - CH9 - [9:9] - read-write - - - CH8 - [8:8] - read-write - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - IRQ1_INTF - Interrupt Force for irq1 - 0x108 - 0x00000000 - - - CH11 - [11:11] - read-write - - - CH10 - [10:10] - read-write - - - CH9 - [9:9] - read-write - - - CH8 - [8:8] - read-write - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - IRQ1_INTS - Interrupt status after masking & forcing for irq1 - 0x10C - 0x00000000 - - - CH11 - [11:11] - read-only - - - CH10 - [10:10] - read-only - - - CH9 - [9:9] - read-only - - - CH8 - [8:8] - read-only - - - CH7 - [7:7] - read-only - - - CH6 - [6:6] - read-only - - - CH5 - [5:5] - read-only - - - CH4 - [4:4] - read-only - - - CH3 - [3:3] - read-only - - - CH2 - [2:2] - read-only - - - CH1 - [1:1] - read-only - - - CH0 - [0:0] - read-only - - - - - - - ADC - Control and data interface to SAR ADC - 0x400A0000 - - 0x0 - 0x24 - registers - - - ADC_IRQ_FIFO - 35 - - - - CS - ADC Control and Status - 0x0 - 0x00000000 - - - RROBIN - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. - Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. - The first channel to be sampled will be the one currently indicated by AINSEL. - AINSEL will be updated after each conversion with the newly-selected channel. - [24:16] - read-write - - - AINSEL - Select analog mux input. Updated automatically in round-robin mode. - This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order - [15:12] - read-write - - - ERR_STICKY - Some past ADC conversion encountered an error. Write 1 to clear. - [10:10] - read-write - oneToClear - - - ERR - The most recent ADC conversion encountered an error; result is undefined or noisy. - [9:9] - read-only - - - READY - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. - 0 whilst conversion in progress. - [8:8] - read-only - - - START_MANY - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. - [3:3] - read-write - - - START_ONCE - Start a single conversion. Self-clearing. Ignored if start_many is asserted. - [2:2] - write-only - - - TS_EN - Power on temperature sensor. 1 - enabled. 0 - disabled. - [1:1] - read-write - - - EN - Power on ADC and enable its clock. - 1 - enabled. 0 - disabled. - [0:0] - read-write - - - - - RESULT - Result of most recent ADC conversion - 0x4 - 0x00000000 - - - RESULT - [11:0] - read-only - - - - - FCS - FIFO control and status - 0x8 - 0x00000000 - - - THRESH - DREQ/IRQ asserted when level >= threshold - [27:24] - read-write - - - LEVEL - The number of conversion results currently waiting in the FIFO - [19:16] - read-only - - - OVER - 1 if the FIFO has been overflowed. Write 1 to clear. - [11:11] - read-write - oneToClear - - - UNDER - 1 if the FIFO has been underflowed. Write 1 to clear. - [10:10] - read-write - oneToClear - - - FULL - [9:9] - read-only - - - EMPTY - [8:8] - read-only - - - DREQ_EN - If 1: assert DMA requests when FIFO contains data - [3:3] - read-write - - - ERR - If 1: conversion error bit appears in the FIFO alongside the result - [2:2] - read-write - - - SHIFT - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. - [1:1] - read-write - - - EN - If 1: write result to the FIFO after each conversion. - [0:0] - read-write - - - - - FIFO - Conversion result FIFO - 0xC - 0x00000000 - - - ERR - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. - [15:15] - read-only - modify - - - VAL - [11:0] - read-only - modify - - - - - DIV - Clock divider. If non-zero, CS_START_MANY will start conversions - at regular intervals rather than back-to-back. - The divider is reset when either of these fields are written. - Total period is 1 + INT + FRAC / 256 - 0x10 - 0x00000000 - - - INT - Integer part of clock divisor. - [23:8] - read-write - - - FRAC - Fractional part of clock divisor. First-order delta-sigma. - [7:0] - read-write - - - - - INTR - Raw Interrupts - 0x14 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x18 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x1C - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x20 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - - - I2C0 - DW_apb_i2c address block - - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): - - IC_ULTRA_FAST_MODE ................ 0x0 - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 - IC_UFM_SCL_LOW_COUNT .............. 0x0008 - IC_UFM_SCL_HIGH_COUNT ............. 0x0006 - IC_TX_TL .......................... 0x0 - IC_TX_CMD_BLOCK ................... 0x1 - IC_HAS_DMA ........................ 0x1 - IC_HAS_ASYNC_FIFO ................. 0x0 - IC_SMBUS_ARP ...................... 0x0 - IC_FIRST_DATA_BYTE_STATUS ......... 0x1 - IC_INTR_IO ........................ 0x1 - IC_MASTER_MODE .................... 0x1 - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 - IC_INTR_POL ....................... 0x1 - IC_OPTIONAL_SAR ................... 0x0 - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 - IC_DEFAULT_SLAVE_ADDR ............. 0x055 - IC_DEFAULT_HS_SPKLEN .............. 0x1 - IC_FS_SCL_HIGH_COUNT .............. 0x0006 - IC_HS_SCL_LOW_COUNT ............... 0x0008 - IC_DEVICE_ID_VALUE ................ 0x0 - IC_10BITADDR_MASTER ............... 0x0 - IC_CLK_FREQ_OPTIMIZATION .......... 0x0 - IC_DEFAULT_FS_SPKLEN .............. 0x7 - IC_ADD_ENCODED_PARAMS ............. 0x0 - IC_DEFAULT_SDA_HOLD ............... 0x000001 - IC_DEFAULT_SDA_SETUP .............. 0x64 - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 - IC_CLOCK_PERIOD ................... 100 - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 - IC_RESTART_EN ..................... 0x1 - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 - IC_BUS_CLEAR_FEATURE .............. 0x0 - IC_CAP_LOADING .................... 100 - IC_FS_SCL_LOW_COUNT ............... 0x000d - APB_DATA_WIDTH .................... 32 - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_SLV_DATA_NACK_ONLY ............. 0x1 - IC_10BITADDR_SLAVE ................ 0x0 - IC_CLK_TYPE ....................... 0x0 - IC_SMBUS_UDID_MSB ................. 0x0 - IC_SMBUS_SUSPEND_ALERT ............ 0x0 - IC_HS_SCL_HIGH_COUNT .............. 0x0006 - IC_SLV_RESTART_DET_EN ............. 0x1 - IC_SMBUS .......................... 0x0 - IC_OPTIONAL_SAR_DEFAULT ........... 0x0 - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 - IC_USE_COUNTS ..................... 0x0 - IC_RX_BUFFER_DEPTH ................ 16 - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_RX_FULL_HLD_BUS_EN ............. 0x1 - IC_SLAVE_DISABLE .................. 0x1 - IC_RX_TL .......................... 0x0 - IC_DEVICE_ID ...................... 0x0 - IC_HC_COUNT_VALUES ................ 0x0 - I2C_DYNAMIC_TAR_UPDATE ............ 0 - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff - IC_HS_MASTER_CODE ................. 0x1 - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff - IC_SS_SCL_HIGH_COUNT .............. 0x0028 - IC_SS_SCL_LOW_COUNT ............... 0x002f - IC_MAX_SPEED_MODE ................. 0x2 - IC_STAT_FOR_CLK_STRETCH ........... 0x0 - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 - IC_DEFAULT_UFM_SPKLEN ............. 0x1 - IC_TX_BUFFER_DEPTH ................ 16 - 0x40090000 - - 0x0 - 0x100 - registers - - - I2C0_IRQ - 36 - - - - IC_CON - I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. - 0x0 - 0x00000065 - - - STOP_DET_IF_MASTER_ACTIVE - Master issues the STOP_DET interrupt irrespective of whether master is active or not - [10:10] - read-only - - - RX_FIFO_FULL_HLD_CTRL - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. - - Reset value: 0x0. - [9:9] - read-write - - - DISABLED - Overflow when RX_FIFO is full - 0 - - - ENABLED - Hold bus when RX_FIFO is full - 1 - - - - - TX_EMPTY_CTRL - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. - - Reset value: 0x0. - [8:8] - read-write - - - DISABLED - Default behaviour of TX_EMPTY interrupt - 0 - - - ENABLED - Controlled generation of TX_EMPTY interrupt - 1 - - - - - STOP_DET_IFADDRESSED - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 - - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - [7:7] - read-write - - - DISABLED - slave issues STOP_DET intr always - 0 - - - ENABLED - slave issues STOP_DET intr only if addressed - 1 - - - - - IC_SLAVE_DISABLE - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. - - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. - - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. - [6:6] - read-write - - - SLAVE_ENABLED - Slave mode is enabled - 0 - - - SLAVE_DISABLED - Slave mode is disabled - 1 - - - - - IC_RESTART_EN - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. - - Reset value: ENABLED - [5:5] - read-write - - - DISABLED - Master restart disabled - 0 - - - ENABLED - Master restart enabled - 1 - - - - - IC_10BITADDR_MASTER - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing - [4:4] - read-write - - - ADDR_7BITS - Master 7Bit addressing mode - 0 - - - ADDR_10BITS - Master 10Bit addressing mode - 1 - - - - - IC_10BITADDR_SLAVE - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. - [3:3] - read-write - - - ADDR_7BITS - Slave 7Bit addressing - 0 - - - ADDR_10BITS - Slave 10Bit addressing - 1 - - - - - SPEED - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. - - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. - - 1: standard mode (100 kbit/s) - - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) - - 3: high speed mode (3.4 Mbit/s) - - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 - [2:1] - read-write - - - STANDARD - Standard Speed mode of operation - 1 - - - FAST - Fast or Fast Plus mode of operation - 2 - - - HIGH - High Speed mode of operation - 3 - - - - - MASTER_MODE - This bit controls whether the DW_apb_i2c master is enabled. - - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. - [0:0] - read-write - - - DISABLED - Master mode is disabled - 0 - - - ENABLED - Master mode is enabled - 1 - - - - - - - IC_TAR - I2C Target Address Register - - This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. - - Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. - 0x4 - 0x00000055 - - - SPECIAL - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 - [11:11] - read-write - - - DISABLED - Disables programming of GENERAL_CALL or START_BYTE transmission - 0 - - - ENABLED - Enables programming of GENERAL_CALL or START_BYTE transmission - 1 - - - - - GC_OR_START - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 - [10:10] - read-write - - - GENERAL_CALL - GENERAL_CALL byte transmission - 0 - - - START_BYTE - START byte transmission - 1 - - - - - IC_TAR - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. - - If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. - [9:0] - read-write - - - - - IC_SAR - I2C Slave Address Register - 0x8 - 0x00000055 - - - IC_SAR - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. - [9:0] - read-write - - - - - IC_DATA_CMD - I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. - - The size of the register changes as follows: - - Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. - 0x10 - 0x00000000 - - - FIRST_DATA_BYTE - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. - - Reset value : 0x0 - - NOTE: In case of APB_DATA_WIDTH=8, - - 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. - - 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). - - 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. - [11:11] - read-only - - - INACTIVE - Sequential data byte received - 0 - - - ACTIVE - Non sequential data byte received - 1 - - - - - RESTART - This bit controls whether a RESTART is issued before the byte is sent or received. - - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - Reset value: 0x0 - [10:10] - write-only - - - DISABLE - Don't Issue RESTART before this command - 0 - - - ENABLE - Issue RESTART before this command - 1 - - - - - STOP - This bit controls whether a STOP is issued after the byte is sent or received. - - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 - [9:9] - write-only - - - DISABLE - Don't Issue STOP after this command - 0 - - - ENABLE - Issue STOP after this command - 1 - - - - - CMD - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. - - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. - - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. - - Reset value: 0x0 - [8:8] - write-only - - - WRITE - Master Write Command - 0 - - - READ - Master Read Command - 1 - - - - - DAT - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. - - Reset value: 0x0 - [7:0] - read-write - - - - - IC_SS_SCL_HCNT - Standard Speed I2C Clock SCL High Count Register - 0x14 - 0x00000028 - - - IC_SS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - - NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. - [15:0] - read-write - - - - - IC_SS_SCL_LCNT - Standard Speed I2C Clock SCL Low Count Register - 0x18 - 0x0000002F - - - IC_SS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. - [15:0] - read-write - - - - - IC_FS_SCL_HCNT - Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register - 0x1C - 0x00000006 - - - IC_FS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - [15:0] - read-write - - - - - IC_FS_SCL_LCNT - Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register - 0x20 - 0x0000000D - - - IC_FS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. - [15:0] - read-write - - - - - IC_INTR_STAT - I2C Interrupt Status Register - - Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. - 0x2C - 0x00000000 - - - R_RESTART_DET - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. - - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - R_RESTART_DET interrupt is inactive - 0 - - - ACTIVE - R_RESTART_DET interrupt is active - 1 - - - - - R_GEN_CALL - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. - - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - R_GEN_CALL interrupt is inactive - 0 - - - ACTIVE - R_GEN_CALL interrupt is active - 1 - - - - - R_START_DET - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. - - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - R_START_DET interrupt is inactive - 0 - - - ACTIVE - R_START_DET interrupt is active - 1 - - - - - R_STOP_DET - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. - - Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - R_STOP_DET interrupt is inactive - 0 - - - ACTIVE - R_STOP_DET interrupt is active - 1 - - - - - R_ACTIVITY - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. - - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - R_ACTIVITY interrupt is inactive - 0 - - - ACTIVE - R_ACTIVITY interrupt is active - 1 - - - - - R_RX_DONE - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. - - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - R_RX_DONE interrupt is inactive - 0 - - - ACTIVE - R_RX_DONE interrupt is active - 1 - - - - - R_TX_ABRT - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. - - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - R_TX_ABRT interrupt is inactive - 0 - - - ACTIVE - R_TX_ABRT interrupt is active - 1 - - - - - R_RD_REQ - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. - - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - R_RD_REQ interrupt is inactive - 0 - - - ACTIVE - R_RD_REQ interrupt is active - 1 - - - - - R_TX_EMPTY - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. - - Reset value: 0x0 - [4:4] - read-only - - - INACTIVE - R_TX_EMPTY interrupt is inactive - 0 - - - ACTIVE - R_TX_EMPTY interrupt is active - 1 - - - - - R_TX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. - - Reset value: 0x0 - [3:3] - read-only - - - INACTIVE - R_TX_OVER interrupt is inactive - 0 - - - ACTIVE - R_TX_OVER interrupt is active - 1 - - - - - R_RX_FULL - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. - - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - R_RX_FULL interrupt is inactive - 0 - - - ACTIVE - R_RX_FULL interrupt is active - 1 - - - - - R_RX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. - - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - R_RX_OVER interrupt is inactive - 0 - - - ACTIVE - R_RX_OVER interrupt is active - 1 - - - - - R_RX_UNDER - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. - - Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - RX_UNDER interrupt is inactive - 0 - - - ACTIVE - RX_UNDER interrupt is active - 1 - - - - - - - IC_INTR_MASK - I2C Interrupt Mask Register. - - These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. - 0x30 - 0x000008FF - - - M_RESTART_DET - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [12:12] - read-write - - - ENABLED - RESTART_DET interrupt is masked - 0 - - - DISABLED - RESTART_DET interrupt is unmasked - 1 - - - - - M_GEN_CALL - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [11:11] - read-write - - - ENABLED - GEN_CALL interrupt is masked - 0 - - - DISABLED - GEN_CALL interrupt is unmasked - 1 - - - - - M_START_DET - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [10:10] - read-write - - - ENABLED - START_DET interrupt is masked - 0 - - - DISABLED - START_DET interrupt is unmasked - 1 - - - - - M_STOP_DET - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [9:9] - read-write - - - ENABLED - STOP_DET interrupt is masked - 0 - - - DISABLED - STOP_DET interrupt is unmasked - 1 - - - - - M_ACTIVITY - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [8:8] - read-write - - - ENABLED - ACTIVITY interrupt is masked - 0 - - - DISABLED - ACTIVITY interrupt is unmasked - 1 - - - - - M_RX_DONE - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [7:7] - read-write - - - ENABLED - RX_DONE interrupt is masked - 0 - - - DISABLED - RX_DONE interrupt is unmasked - 1 - - - - - M_TX_ABRT - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [6:6] - read-write - - - ENABLED - TX_ABORT interrupt is masked - 0 - - - DISABLED - TX_ABORT interrupt is unmasked - 1 - - - - - M_RD_REQ - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [5:5] - read-write - - - ENABLED - RD_REQ interrupt is masked - 0 - - - DISABLED - RD_REQ interrupt is unmasked - 1 - - - - - M_TX_EMPTY - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [4:4] - read-write - - - ENABLED - TX_EMPTY interrupt is masked - 0 - - - DISABLED - TX_EMPTY interrupt is unmasked - 1 - - - - - M_TX_OVER - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [3:3] - read-write - - - ENABLED - TX_OVER interrupt is masked - 0 - - - DISABLED - TX_OVER interrupt is unmasked - 1 - - - - - M_RX_FULL - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [2:2] - read-write - - - ENABLED - RX_FULL interrupt is masked - 0 - - - DISABLED - RX_FULL interrupt is unmasked - 1 - - - - - M_RX_OVER - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [1:1] - read-write - - - ENABLED - RX_OVER interrupt is masked - 0 - - - DISABLED - RX_OVER interrupt is unmasked - 1 - - - - - M_RX_UNDER - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [0:0] - read-write - - - ENABLED - RX_UNDER interrupt is masked - 0 - - - DISABLED - RX_UNDER interrupt is unmasked - 1 - - - - - - - IC_RAW_INTR_STAT - I2C Raw Interrupt Status Register - - Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. - 0x34 - 0x00000000 - - - RESTART_DET - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. - - Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. - - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - RESTART_DET interrupt is inactive - 0 - - - ACTIVE - RESTART_DET interrupt is active - 1 - - - - - GEN_CALL - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. - - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - GEN_CALL interrupt is inactive - 0 - - - ACTIVE - GEN_CALL interrupt is active - 1 - - - - - START_DET - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - START_DET interrupt is inactive - 0 - - - ACTIVE - START_DET interrupt is active - 1 - - - - - STOP_DET - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - STOP_DET interrupt is inactive - 0 - - - ACTIVE - STOP_DET interrupt is active - 1 - - - - - ACTIVITY - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. - - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - RAW_INTR_ACTIVITY interrupt is inactive - 0 - - - ACTIVE - RAW_INTR_ACTIVITY interrupt is active - 1 - - - - - RX_DONE - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. - - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - RX_DONE interrupt is inactive - 0 - - - ACTIVE - RX_DONE interrupt is active - 1 - - - - - TX_ABRT - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. - - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. - - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - TX_ABRT interrupt is inactive - 0 - - - ACTIVE - TX_ABRT interrupt is active - 1 - - - - - RD_REQ - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. - - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - RD_REQ interrupt is inactive - 0 - - - ACTIVE - RD_REQ interrupt is active - 1 - - - - - TX_EMPTY - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. - - Reset value: 0x0. - [4:4] - read-only - - - INACTIVE - TX_EMPTY interrupt is inactive - 0 - - - ACTIVE - TX_EMPTY interrupt is active - 1 - - - - - TX_OVER - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0 - [3:3] - read-only - - - INACTIVE - TX_OVER interrupt is inactive - 0 - - - ACTIVE - TX_OVER interrupt is active - 1 - - - - - RX_FULL - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. - - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - RX_FULL interrupt is inactive - 0 - - - ACTIVE - RX_FULL interrupt is active - 1 - - - - - RX_OVER - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. - - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - RX_OVER interrupt is inactive - 0 - - - ACTIVE - RX_OVER interrupt is active - 1 - - - - - RX_UNDER - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - RX_UNDER interrupt is inactive - 0 - - - ACTIVE - RX_UNDER interrupt is active - 1 - - - - - - - IC_RX_TL - I2C Receive FIFO Threshold Register - 0x38 - 0x00000000 - - - RX_TL - Receive FIFO Threshold Level. - - Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. - [7:0] - read-write - - - - - IC_TX_TL - I2C Transmit FIFO Threshold Register - 0x3C - 0x00000000 - - - TX_TL - Transmit FIFO Threshold Level. - - Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. - [7:0] - read-write - - - - - IC_CLR_INTR - Clear Combined and Individual Interrupt Register - 0x40 - 0x00000000 - - - CLR_INTR - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_UNDER - Clear RX_UNDER Interrupt Register - 0x44 - 0x00000000 - - - CLR_RX_UNDER - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_OVER - Clear RX_OVER Interrupt Register - 0x48 - 0x00000000 - - - CLR_RX_OVER - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_TX_OVER - Clear TX_OVER Interrupt Register - 0x4C - 0x00000000 - - - CLR_TX_OVER - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RD_REQ - Clear RD_REQ Interrupt Register - 0x50 - 0x00000000 - - - CLR_RD_REQ - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_TX_ABRT - Clear TX_ABRT Interrupt Register - 0x54 - 0x00000000 - - - CLR_TX_ABRT - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_DONE - Clear RX_DONE Interrupt Register - 0x58 - 0x00000000 - - - CLR_RX_DONE - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_ACTIVITY - Clear ACTIVITY Interrupt Register - 0x5C - 0x00000000 - - - CLR_ACTIVITY - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_STOP_DET - Clear STOP_DET Interrupt Register - 0x60 - 0x00000000 - - - CLR_STOP_DET - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_START_DET - Clear START_DET Interrupt Register - 0x64 - 0x00000000 - - - CLR_START_DET - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_GEN_CALL - Clear GEN_CALL Interrupt Register - 0x68 - 0x00000000 - - - CLR_GEN_CALL - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_ENABLE - I2C Enable Register - 0x6C - 0x00000000 - - - TX_CMD_BLOCK - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT - [2:2] - read-write - - - NOT_BLOCKED - Tx Command execution not blocked - 0 - - - BLOCKED - Tx Command execution blocked - 1 - - - - - ABORT - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. - - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. - - Reset value: 0x0 - [1:1] - read-write - - - DISABLE - ABORT operation not in progress - 0 - - - ENABLED - ABORT operation in progress - 1 - - - - - ENABLE - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. - - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. - - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' - - Reset value: 0x0 - [0:0] - read-write - - - DISABLED - I2C is disabled - 0 - - - ENABLED - I2C is enabled - 1 - - - - - - - IC_STATUS - I2C Status Register - - This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. - - When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 - 0x70 - 0x00000006 - - - SLV_ACTIVITY - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 - [6:6] - read-only - - - IDLE - Slave is idle - 0 - - - ACTIVE - Slave not idle - 1 - - - - - MST_ACTIVITY - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. - - Reset value: 0x0 - [5:5] - read-only - - - IDLE - Master is idle - 0 - - - ACTIVE - Master not idle - 1 - - - - - RFF - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 - [4:4] - read-only - - - NOT_FULL - Rx FIFO not full - 0 - - - FULL - Rx FIFO is full - 1 - - - - - RFNE - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 - [3:3] - read-only - - - EMPTY - Rx FIFO is empty - 0 - - - NOT_EMPTY - Rx FIFO not empty - 1 - - - - - TFE - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 - [2:2] - read-only - - - NON_EMPTY - Tx FIFO not empty - 0 - - - EMPTY - Tx FIFO is empty - 1 - - - - - TFNF - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 - [1:1] - read-only - - - FULL - Tx FIFO is full - 0 - - - NOT_FULL - Tx FIFO not full - 1 - - - - - ACTIVITY - I2C Activity Status. Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - I2C is idle - 0 - - - ACTIVE - I2C is active - 1 - - - - - - - IC_TXFLR - I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. - 0x74 - 0x00000000 - - - TXFLR - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. - - Reset value: 0x0 - [4:0] - read-only - - - - - IC_RXFLR - I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. - 0x78 - 0x00000000 - - - RXFLR - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. - - Reset value: 0x0 - [4:0] - read-only - - - - - IC_SDA_HOLD - I2C SDA Hold Time Length Register - - The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). - - The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. - - Writes to this register succeed only when IC_ENABLE[0]=0. - - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. - - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. - 0x7C - 0x00000001 - - - IC_SDA_RX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. - - Reset value: IC_DEFAULT_SDA_HOLD[23:16]. - [23:16] - read-write - - - IC_SDA_TX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. - - Reset value: IC_DEFAULT_SDA_HOLD[15:0]. - [15:0] - read-write - - - - - IC_TX_ABRT_SOURCE - I2C Transmit Abort Source Register - - This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). - - Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. - 0x80 - 0x00000000 - - - TX_FLUSH_CNT - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [31:23] - read-only - - - ABRT_USER_ABRT - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [16:16] - read-only - - - ABRT_USER_ABRT_VOID - Transfer abort detected by master- scenario not present - 0 - - - ABRT_USER_ABRT_GENERATED - Transfer abort detected by master - 1 - - - - - ABRT_SLVRD_INTX - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter - [15:15] - read-only - - - ABRT_SLVRD_INTX_VOID - Slave trying to transmit to remote master in read mode- scenario not present - 0 - - - ABRT_SLVRD_INTX_GENERATED - Slave trying to transmit to remote master in read mode - 1 - - - - - ABRT_SLV_ARBLOST - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter - [14:14] - read-only - - - ABRT_SLV_ARBLOST_VOID - Slave lost arbitration to remote master- scenario not present - 0 - - - ABRT_SLV_ARBLOST_GENERATED - Slave lost arbitration to remote master - 1 - - - - - ABRT_SLVFLUSH_TXFIFO - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter - [13:13] - read-only - - - ABRT_SLVFLUSH_TXFIFO_VOID - Slave flushes existing data in TX-FIFO upon getting read command- scenario not present - 0 - - - ABRT_SLVFLUSH_TXFIFO_GENERATED - Slave flushes existing data in TX-FIFO upon getting read command - 1 - - - - - ARB_LOST - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [12:12] - read-only - - - ABRT_LOST_VOID - Master or Slave-Transmitter lost arbitration- scenario not present - 0 - - - ABRT_LOST_GENERATED - Master or Slave-Transmitter lost arbitration - 1 - - - - - ABRT_MASTER_DIS - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [11:11] - read-only - - - ABRT_MASTER_DIS_VOID - User initiating master operation when MASTER disabled- scenario not present - 0 - - - ABRT_MASTER_DIS_GENERATED - User initiating master operation when MASTER disabled - 1 - - - - - ABRT_10B_RD_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Receiver - [10:10] - read-only - - - ABRT_10B_RD_VOID - Master not trying to read in 10Bit addressing mode when RESTART disabled - 0 - - - ABRT_10B_RD_GENERATED - Master trying to read in 10Bit addressing mode when RESTART disabled - 1 - - - - - ABRT_SBYTE_NORSTRT - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master - [9:9] - read-only - - - ABRT_SBYTE_NORSTRT_VOID - User trying to send START byte when RESTART disabled- scenario not present - 0 - - - ABRT_SBYTE_NORSTRT_GENERATED - User trying to send START byte when RESTART disabled - 1 - - - - - ABRT_HS_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [8:8] - read-only - - - ABRT_HS_NORSTRT_VOID - User trying to switch Master to HS mode when RESTART disabled- scenario not present - 0 - - - ABRT_HS_NORSTRT_GENERATED - User trying to switch Master to HS mode when RESTART disabled - 1 - - - - - ABRT_SBYTE_ACKDET - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master - [7:7] - read-only - - - ABRT_SBYTE_ACKDET_VOID - ACK detected for START byte- scenario not present - 0 - - - ABRT_SBYTE_ACKDET_GENERATED - ACK detected for START byte - 1 - - - - - ABRT_HS_ACKDET - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master - [6:6] - read-only - - - ABRT_HS_ACK_VOID - HS Master code ACKed in HS Mode- scenario not present - 0 - - - ABRT_HS_ACK_GENERATED - HS Master code ACKed in HS Mode - 1 - - - - - ABRT_GCALL_READ - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [5:5] - read-only - - - ABRT_GCALL_READ_VOID - GCALL is followed by read from bus-scenario not present - 0 - - - ABRT_GCALL_READ_GENERATED - GCALL is followed by read from bus - 1 - - - - - ABRT_GCALL_NOACK - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [4:4] - read-only - - - ABRT_GCALL_NOACK_VOID - GCALL not ACKed by any slave-scenario not present - 0 - - - ABRT_GCALL_NOACK_GENERATED - GCALL not ACKed by any slave - 1 - - - - - ABRT_TXDATA_NOACK - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [3:3] - read-only - - - ABRT_TXDATA_NOACK_VOID - Transmitted data non-ACKed by addressed slave-scenario not present - 0 - - - ABRT_TXDATA_NOACK_GENERATED - Transmitted data not ACKed by addressed slave - 1 - - - - - ABRT_10ADDR2_NOACK - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [2:2] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - Byte 2 of 10Bit Address not ACKed by any slave - 1 - - - - - ABRT_10ADDR1_NOACK - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [1:1] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - Byte 1 of 10Bit Address not ACKed by any slave - 1 - - - - - ABRT_7B_ADDR_NOACK - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [0:0] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - This abort is generated because of NOACK for 7-bit address - 1 - - - - - - - IC_SLV_DATA_NACK_ONLY - Generate Slave Data NACK Register - - The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. - - A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. - 0x84 - 0x00000000 - - - NACK - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. - - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 - [0:0] - read-write - - - DISABLED - Slave receiver generates NACK normally - 0 - - - ENABLED - Slave receiver generates NACK upon data reception only - 1 - - - - - - - IC_DMA_CR - DMA Control Register - - The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. - 0x88 - 0x00000000 - - - TDMAE - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 - [1:1] - read-write - - - DISABLED - transmit FIFO DMA channel disabled - 0 - - - ENABLED - Transmit FIFO DMA channel enabled - 1 - - - - - RDMAE - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 - [0:0] - read-write - - - DISABLED - Receive FIFO DMA channel disabled - 0 - - - ENABLED - Receive FIFO DMA channel enabled - 1 - - - - - - - IC_DMA_TDLR - DMA Transmit Data Level Register - 0x8C - 0x00000000 - - - DMATDL - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. - - Reset value: 0x0 - [3:0] - read-write - - - - - IC_DMA_RDLR - I2C Receive Data Level Register - 0x90 - 0x00000000 - - - DMARDL - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. - - Reset value: 0x0 - [3:0] - read-write - - - - - IC_SDA_SETUP - I2C SDA Setup Register - - This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. - - Writes to this register succeed only when IC_ENABLE[0] = 0. - - Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. - 0x94 - 0x00000064 - - - SDA_SETUP - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. - [7:0] - read-write - - - - - IC_ACK_GENERAL_CALL - I2C ACK General Call Register - - The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. - - This register is applicable only when the DW_apb_i2c is in slave mode. - 0x98 - 0x00000001 - - - ACK_GEN_CALL - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). - [0:0] - read-write - - - DISABLED - Generate NACK for a General Call - 0 - - - ENABLED - Generate ACK for a General Call - 1 - - - - - - - IC_ENABLE_STATUS - I2C Enable Status Register - - The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. - - If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. - - If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. - - Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. - 0x9C - 0x00000000 - - - SLV_RX_DATA_LOST - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - Slave RX Data is not lost - 0 - - - ACTIVE - Slave RX Data is lost - 1 - - - - - SLV_DISABLED_WHILE_BUSY - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: - - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; - - OR, - - (b) address and data bytes of the Slave-Receiver operation from a remote master. - - When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - Slave is disabled when it is idle - 0 - - - ACTIVE - Slave is disabled when it is active - 1 - - - - - IC_EN - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). - - Reset value: 0x0 - [0:0] - read-only - - - DISABLED - I2C disabled - 0 - - - ENABLED - I2C enabled - 1 - - - - - - - IC_FS_SPKLEN - I2C SS, FS or FM+ spike suppression limit - - This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. - 0xA0 - 0x00000007 - - - IC_FS_SPKLEN - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. - [7:0] - read-write - - - - - IC_CLR_RESTART_DET - Clear RESTART_DET Interrupt Register - 0xA8 - 0x00000000 - - - CLR_RESTART_DET - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_COMP_PARAM_1 - Component Parameter Register 1 - - Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters - 0xF4 - 0x00000000 - - - TX_BUFFER_DEPTH - TX Buffer Depth = 16 - [23:16] - read-only - - - RX_BUFFER_DEPTH - RX Buffer Depth = 16 - [15:8] - read-only - - - ADD_ENCODED_PARAMS - Encoded parameters not visible - [7:7] - read-only - - - HAS_DMA - DMA handshaking signals are enabled - [6:6] - read-only - - - INTR_IO - COMBINED Interrupt outputs - [5:5] - read-only - - - HC_COUNT_VALUES - Programmable count values for each mode. - [4:4] - read-only - - - MAX_SPEED_MODE - MAX SPEED MODE = FAST MODE - [3:2] - read-only - - - APB_DATA_WIDTH - APB data bus width is 32 bits - [1:0] - read-only - - - - - IC_COMP_VERSION - I2C Component Version Register - 0xF8 - 0x3230312A - - - IC_COMP_VERSION - [31:0] - read-only - - - - - IC_COMP_TYPE - I2C Component Type Register - 0xFC - 0x44570140 - - - IC_COMP_TYPE - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. - [31:0] - read-only - - - - - - - I2C1 - 0x40098000 - - I2C1_IRQ - 37 - - - - SPI0 - 0x40080000 - - 0x0 - 0x1000 - registers - - - SPI0_IRQ - 31 - - - - SSPCR0 - Control register 0, SSPCR0 on page 3-4 - 0x0 - 0x00000000 - - - SCR - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. - [15:8] - read-write - - - SPH - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [7:7] - read-write - - - SPO - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [6:6] - read-write - - - FRF - Frame format. - [5:4] - read-write - - FRF - - Motorola - Motorola SPI frame format - 0 - - - Texas_Instruments - Texas Instruments synchronous serial frame format - 1 - - - National_Semiconductor_Microwire - National Semiconductor Microwire frame format - 2 - - - - - DSS - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. - [3:0] - read-write - - - - - SSPCR1 - Control register 1, SSPCR1 on page 3-5 - 0x4 - 0x00000000 - - - SOD - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. - [3:3] - read-write - - - MS - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. - [2:2] - read-write - - - SSE - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. - [1:1] - read-write - - - LBM - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. - [0:0] - read-write - - - - - SSPDR - Data register, SSPDR on page 3-6 - 0x8 - 0x00000000 - - - DATA - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. - [15:0] - read-write - modify - - - - - SSPSR - Status register, SSPSR on page 3-7 - 0xC - 0x00000003 - - - BSY - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. - [4:4] - read-only - - - RFF - Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. - [3:3] - read-only - - - RNE - Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. - [2:2] - read-only - - - TNF - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. - [1:1] - read-only - - - TFE - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. - [0:0] - read-only - - - - - SSPCPSR - Clock prescale register, SSPCPSR on page 3-8 - 0x10 - 0x00000000 - - - CPSDVSR - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. - [7:0] - read-write - - - - - SSPIMSC - Interrupt mask set or clear register, SSPIMSC on page 3-9 - 0x14 - 0x00000000 - - - TXIM - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. - [3:3] - read-write - - - RXIM - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. - [2:2] - read-write - - - RTIM - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. - [1:1] - read-write - - - RORIM - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. - [0:0] - read-write - - - - - SSPRIS - Raw interrupt status register, SSPRIS on page 3-10 - 0x18 - 0x00000008 - - - TXRIS - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt - [3:3] - read-only - - - RXRIS - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt - [2:2] - read-only - - - RTRIS - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt - [1:1] - read-only - - - RORRIS - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt - [0:0] - read-only - - - - - SSPMIS - Masked interrupt status register, SSPMIS on page 3-11 - 0x1C - 0x00000000 - - - TXMIS - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - [3:3] - read-only - - - RXMIS - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - [2:2] - read-only - - - RTMIS - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - [1:1] - read-only - - - RORMIS - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - [0:0] - read-only - - - - - SSPICR - Interrupt clear register, SSPICR on page 3-11 - 0x20 - 0x00000000 - - - RTIC - Clears the SSPRTINTR interrupt - [1:1] - read-write - oneToClear - - - RORIC - Clears the SSPRORINTR interrupt - [0:0] - read-write - oneToClear - - - - - SSPDMACR - DMA control register, SSPDMACR on page 3-12 - 0x24 - 0x00000000 - - - TXDMAE - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] - read-write - - - - - SSPPERIPHID0 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFE0 - 0x00000022 - - - PARTNUMBER0 - These bits read back as 0x22 - [7:0] - read-only - - - - - SSPPERIPHID1 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFE4 - 0x00000010 - - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only - - - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - SSPPERIPHID2 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFE8 - 0x00000034 - - - REVISION - These bits return the peripheral revision - [7:4] - read-only - - - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only - - - - - SSPPERIPHID3 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFEC - 0x00000000 - - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only - - - - - SSPPCELLID0 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFF0 - 0x0000000D - - - SSPPCELLID0 - These bits read back as 0x0D - [7:0] - read-only - - - - - SSPPCELLID1 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFF4 - 0x000000F0 - - - SSPPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only - - - - - SSPPCELLID2 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFF8 - 0x00000005 - - - SSPPCELLID2 - These bits read back as 0x05 - [7:0] - read-only - - - - - SSPPCELLID3 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFFC - 0x000000B1 - - - SSPPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only - - - - - - - SPI1 - 0x40088000 - - SPI1_IRQ - 32 - - - - PIO0 - Programmable IO block - 0x50200000 - - 0x0 - 0x188 - registers - - - PIO0_IRQ_0 - 15 - - - PIO0_IRQ_1 - 16 - - - - CTRL - PIO control register - 0x0 - 0x00000000 - - - NEXTPREV_CLKDIV_RESTART - Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. - - This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. - [26:26] - write-only - - - NEXTPREV_SM_DISABLE - Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. - - This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. - [25:25] - write-only - - - NEXTPREV_SM_ENABLE - Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. - - This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. - - If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence. - [24:24] - write-only - - - NEXT_PIO_MASK - A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. - - This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. - - Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). - - Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. - [23:20] - write-only - - - PREV_PIO_MASK - A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. - - This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. - - Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. - [19:16] - write-only - - - CLKDIV_RESTART - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. - - Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. - - Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. - [11:8] - write-only - - - SM_RESTART - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. - - Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. - - The contents of the output shift register and the X/Y scratch registers are not affected. - [7:4] - write-only - - - SM_ENABLE - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. - [3:0] - read-write - - - - - FSTAT - FIFO status register - 0x4 - 0x0F000F00 - - - TXEMPTY - State machine TX FIFO is empty - [27:24] - read-only - - - TXFULL - State machine TX FIFO is full - [19:16] - read-only - - - RXEMPTY - State machine RX FIFO is empty - [11:8] - read-only - - - RXFULL - State machine RX FIFO is full - [3:0] - read-only - - - - - FDEBUG - FIFO debug register - 0x8 - 0x00000000 - - - TXSTALL - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. - [27:24] - read-write - oneToClear - - - TXOVER - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. - [19:16] - read-write - oneToClear - - - RXUNDER - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. - [11:8] - read-write - oneToClear - - - RXSTALL - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. - [3:0] - read-write - oneToClear - - - - - FLEVEL - FIFO levels - 0xC - 0x00000000 - - - RX3 - [31:28] - read-only - - - TX3 - [27:24] - read-only - - - RX2 - [23:20] - read-only - - - TX2 - [19:16] - read-only - - - RX1 - [15:12] - read-only - - - TX1 - [11:8] - read-only - - - RX0 - [7:4] - read-only - - - TX0 - [3:0] - read-only - - - - - 4 - 0x4 - 0-3 - TXF%s - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x10 - 0x00000000 - - - TXF0 - [31:0] - write-only - - - - - 4 - 0x4 - 0-3 - RXF%s - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x20 - 0x00000000 - - - RXF0 - [31:0] - read-only - modify - - - - - IRQ - State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. - - Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. - 0x30 - 0x00000000 - - - IRQ - [7:0] - read-write - oneToClear - - - - - IRQ_FORCE - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. - 0x34 - 0x00000000 - - - IRQ_FORCE - [7:0] - write-only - - - - - INPUT_SYNC_BYPASS - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. - 0 -> input is synchronized (default) - 1 -> synchronizer is bypassed - If in doubt, leave this register as all zeroes. - 0x38 - 0x00000000 - - - INPUT_SYNC_BYPASS - [31:0] - read-write - - - - - DBG_PADOUT - Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x3C - 0x00000000 - - - DBG_PADOUT - [31:0] - read-only - - - - - DBG_PADOE - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x40 - 0x00000000 - - - DBG_PADOE - [31:0] - read-only - - - - - DBG_CFGINFO - The PIO hardware has some free parameters that may vary between chip products. - These should be provided in the chip datasheet, but are also exposed here. - 0x44 - 0x10000000 - - - VERSION - Version of the core PIO hardware. - [31:28] - read-only - - - v0 - Version 0 (RP2040) - 0 - - - v1 - Version 1 (RP2350) - 1 - - - - - IMEM_SIZE - The size of the instruction memory, measured in units of one instruction - [21:16] - read-only - - - SM_COUNT - The number of state machines this PIO instance is equipped with. - [11:8] - read-only - - - FIFO_DEPTH - The depth of the state machine TX/RX FIFOs, measured in words. - Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double - this depth. - [5:0] - read-only - - - - - 32 - 0x4 - 0-31 - INSTR_MEM%s - Write-only access to instruction memory location %s - 0x48 - 0x00000000 - - - INSTR_MEM0 - [15:0] - write-only - - - - - 4 - 0x18 - 0-3 - SM%s - Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL - 0xC8 - - SM_CLKDIV - Clock divisor register for state machine 0 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x0 - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM_EXECCTRL - Execution/behavioural settings for state machine 0 - 0x4 - 0x0001F000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [6:5] - read-write - - - TXLEVEL - All-ones if TX FIFO level < N, otherwise all-zeroes - 0 - - - RXLEVEL - All-ones if RX FIFO level < N, otherwise all-zeroes - 1 - - - IRQ - All-ones if the indexed IRQ flag is raised, otherwise all-zeroes - 2 - - - - - STATUS_N - Comparison level or IRQ index for the MOV x, STATUS instruction. - - If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. - [4:0] - read-write - - - IRQ - Index 0-7 of an IRQ flag in this PIO block - 0 - - - IRQ_PREVPIO - Index 0-7 of an IRQ flag in the next lower-numbered PIO block - 8 - - - IRQ_NEXTPIO - Index 0-7 of an IRQ flag in the next higher-numbered PIO block - 16 - - - - - - - SM_SHIFTCTRL - Control behaviour of the input/output shift registers for state machine 0 - 0x8 - 0x000C0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - FJOIN_RX_PUT - If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). - - If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. - - Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. - [15:15] - read-write - - - FJOIN_RX_GET - If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). - - If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. - - Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. - [14:14] - read-write - - - IN_COUNT - Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. - - For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. - - Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. - [4:0] - read-write - - - - - SM_ADDR - Current instruction address of state machine 0 - 0xC - 0x00000000 - - - SM0_ADDR - [4:0] - read-only - - - - - SM_INSTR - Read to see the instruction currently addressed by state machine 0's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x10 - 0x00000000 - - - SM0_INSTR - [15:0] - read-write - - - - - SM_PINCTRL - State machine pin control - 0x14 - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - - 4 - 0x4 - 0-3 - RXF0_PUTGET%s - Direct read/write access to entry %s of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x128 - 0x00000000 - - - RXF0_PUTGET0 - [31:0] - read-write - - - - - 4 - 0x4 - 0-3 - RXF1_PUTGET%s - Direct read/write access to entry %s of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x138 - 0x00000000 - - - RXF1_PUTGET0 - [31:0] - read-write - - - - - 4 - 0x4 - 0-3 - RXF2_PUTGET%s - Direct read/write access to entry %s of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x148 - 0x00000000 - - - RXF2_PUTGET0 - [31:0] - read-write - - - - - 4 - 0x4 - 0-3 - RXF3_PUTGET%s - Direct read/write access to entry %s of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x158 - 0x00000000 - - - RXF3_PUTGET0 - [31:0] - read-write - - - - - GPIOBASE - Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. - - Only the values 0 and 16 are supported (only bit 4 is writable). - 0x168 - 0x00000000 - - - GPIOBASE - [4:4] - read-write - - - - - INTR - Raw Interrupts - 0x16C - 0x00000000 - - - SM7 - [15:15] - read-only - - - SM6 - [14:14] - read-only - - - SM5 - [13:13] - read-only - - - SM4 - [12:12] - read-only - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - 2 - 0xC - 0-1 - SM_IRQ%s - Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS - 0x170 - - IRQ_INTE - Interrupt Enable for irq0 - 0x0 - 0x00000000 - - - SM7 - [15:15] - read-write - - - SM6 - [14:14] - read-write - - - SM5 - [13:13] - read-write - - - SM4 - [12:12] - read-write - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ_INTF - Interrupt Force for irq0 - 0x4 - 0x00000000 - - - SM7 - [15:15] - read-write - - - SM6 - [14:14] - read-write - - - SM5 - [13:13] - read-write - - - SM4 - [12:12] - read-write - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ_INTS - Interrupt status after masking & forcing for irq0 - 0x8 - 0x00000000 - - - SM7 - [15:15] - read-only - - - SM6 - [14:14] - read-only - - - SM5 - [13:13] - read-only - - - SM4 - [12:12] - read-only - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - - - - PIO1 - 0x50300000 - - PIO1_IRQ_0 - 17 - - - PIO1_IRQ_1 - 18 - - - - PIO2 - 0x50400000 - - PIO2_IRQ_0 - 19 - - - PIO2_IRQ_1 - 20 - - - - BUSCTRL - Register block for busfabric control signals and performance counters - 0x40068000 - - 0x0 - 0x2C - registers - - - - BUS_PRIORITY - Set the priority of each master for bus arbitration. - 0x0 - 0x00000000 - - - DMA_W - 0 - low priority, 1 - high priority - [12:12] - read-write - - - DMA_R - 0 - low priority, 1 - high priority - [8:8] - read-write - - - PROC1 - 0 - low priority, 1 - high priority - [4:4] - read-write - - - PROC0 - 0 - low priority, 1 - high priority - [0:0] - read-write - - - - - BUS_PRIORITY_ACK - Bus priority acknowledge - 0x4 - 0x00000000 - - - BUS_PRIORITY_ACK - Goes to 1 once all arbiters have registered the new global priority levels. - Arbiters update their local priority when servicing a new nonsequential access. - In normal circumstances this will happen almost immediately. - [0:0] - read-only - - - - - PERFCTR_EN - Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. - - The performance counters are initially disabled, to save energy. - 0x8 - 0x00000000 - - - PERFCTR_EN - [0:0] - read-write - - - - - PERFCTR0 - Bus fabric performance counter 0 - 0xC - 0x00000000 - - - PERFCTR0 - Busfabric saturating performance counter 0 - Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. - Write any value to clear. Select an event to count using PERFSEL0 - [23:0] - read-write - oneToClear - - - - - PERFSEL0 - Bus fabric performance event select for PERFCTR0 - 0x10 - 0x0000001F - - - PERFSEL0 - Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. - [6:0] - read-write - - - siob_proc1_stall_upstream - 0 - - - siob_proc1_stall_downstream - 1 - - - siob_proc1_access_contested - 2 - - - siob_proc1_access - 3 - - - siob_proc0_stall_upstream - 4 - - - siob_proc0_stall_downstream - 5 - - - siob_proc0_access_contested - 6 - - - siob_proc0_access - 7 - - - apb_stall_upstream - 8 - - - apb_stall_downstream - 9 - - - apb_access_contested - 10 - - - apb_access - 11 - - - fastperi_stall_upstream - 12 - - - fastperi_stall_downstream - 13 - - - fastperi_access_contested - 14 - - - fastperi_access - 15 - - - sram9_stall_upstream - 16 - - - sram9_stall_downstream - 17 - - - sram9_access_contested - 18 - - - sram9_access - 19 - - - sram8_stall_upstream - 20 - - - sram8_stall_downstream - 21 - - - sram8_access_contested - 22 - - - sram8_access - 23 - - - sram7_stall_upstream - 24 - - - sram7_stall_downstream - 25 - - - sram7_access_contested - 26 - - - sram7_access - 27 - - - sram6_stall_upstream - 28 - - - sram6_stall_downstream - 29 - - - sram6_access_contested - 30 - - - sram6_access - 31 - - - sram5_stall_upstream - 32 - - - sram5_stall_downstream - 33 - - - sram5_access_contested - 34 - - - sram5_access - 35 - - - sram4_stall_upstream - 36 - - - sram4_stall_downstream - 37 - - - sram4_access_contested - 38 - - - sram4_access - 39 - - - sram3_stall_upstream - 40 - - - sram3_stall_downstream - 41 - - - sram3_access_contested - 42 - - - sram3_access - 43 - - - sram2_stall_upstream - 44 - - - sram2_stall_downstream - 45 - - - sram2_access_contested - 46 - - - sram2_access - 47 - - - sram1_stall_upstream - 48 - - - sram1_stall_downstream - 49 - - - sram1_access_contested - 50 - - - sram1_access - 51 - - - sram0_stall_upstream - 52 - - - sram0_stall_downstream - 53 - - - sram0_access_contested - 54 - - - sram0_access - 55 - - - xip_main1_stall_upstream - 56 - - - xip_main1_stall_downstream - 57 - - - xip_main1_access_contested - 58 - - - xip_main1_access - 59 - - - xip_main0_stall_upstream - 60 - - - xip_main0_stall_downstream - 61 - - - xip_main0_access_contested - 62 - - - xip_main0_access - 63 - - - rom_stall_upstream - 64 - - - rom_stall_downstream - 65 - - - rom_access_contested - 66 - - - rom_access - 67 - - - - - - - PERFCTR1 - Bus fabric performance counter 1 - 0x14 - 0x00000000 - - - PERFCTR1 - Busfabric saturating performance counter 1 - Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. - Write any value to clear. Select an event to count using PERFSEL1 - [23:0] - read-write - oneToClear - - - - - PERFSEL1 - Bus fabric performance event select for PERFCTR1 - 0x18 - 0x0000001F - - - PERFSEL1 - Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. - [6:0] - read-write - - - siob_proc1_stall_upstream - 0 - - - siob_proc1_stall_downstream - 1 - - - siob_proc1_access_contested - 2 - - - siob_proc1_access - 3 - - - siob_proc0_stall_upstream - 4 - - - siob_proc0_stall_downstream - 5 - - - siob_proc0_access_contested - 6 - - - siob_proc0_access - 7 - - - apb_stall_upstream - 8 - - - apb_stall_downstream - 9 - - - apb_access_contested - 10 - - - apb_access - 11 - - - fastperi_stall_upstream - 12 - - - fastperi_stall_downstream - 13 - - - fastperi_access_contested - 14 - - - fastperi_access - 15 - - - sram9_stall_upstream - 16 - - - sram9_stall_downstream - 17 - - - sram9_access_contested - 18 - - - sram9_access - 19 - - - sram8_stall_upstream - 20 - - - sram8_stall_downstream - 21 - - - sram8_access_contested - 22 - - - sram8_access - 23 - - - sram7_stall_upstream - 24 - - - sram7_stall_downstream - 25 - - - sram7_access_contested - 26 - - - sram7_access - 27 - - - sram6_stall_upstream - 28 - - - sram6_stall_downstream - 29 - - - sram6_access_contested - 30 - - - sram6_access - 31 - - - sram5_stall_upstream - 32 - - - sram5_stall_downstream - 33 - - - sram5_access_contested - 34 - - - sram5_access - 35 - - - sram4_stall_upstream - 36 - - - sram4_stall_downstream - 37 - - - sram4_access_contested - 38 - - - sram4_access - 39 - - - sram3_stall_upstream - 40 - - - sram3_stall_downstream - 41 - - - sram3_access_contested - 42 - - - sram3_access - 43 - - - sram2_stall_upstream - 44 - - - sram2_stall_downstream - 45 - - - sram2_access_contested - 46 - - - sram2_access - 47 - - - sram1_stall_upstream - 48 - - - sram1_stall_downstream - 49 - - - sram1_access_contested - 50 - - - sram1_access - 51 - - - sram0_stall_upstream - 52 - - - sram0_stall_downstream - 53 - - - sram0_access_contested - 54 - - - sram0_access - 55 - - - xip_main1_stall_upstream - 56 - - - xip_main1_stall_downstream - 57 - - - xip_main1_access_contested - 58 - - - xip_main1_access - 59 - - - xip_main0_stall_upstream - 60 - - - xip_main0_stall_downstream - 61 - - - xip_main0_access_contested - 62 - - - xip_main0_access - 63 - - - rom_stall_upstream - 64 - - - rom_stall_downstream - 65 - - - rom_access_contested - 66 - - - rom_access - 67 - - - - - - - PERFCTR2 - Bus fabric performance counter 2 - 0x1C - 0x00000000 - - - PERFCTR2 - Busfabric saturating performance counter 2 - Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. - Write any value to clear. Select an event to count using PERFSEL2 - [23:0] - read-write - oneToClear - - - - - PERFSEL2 - Bus fabric performance event select for PERFCTR2 - 0x20 - 0x0000001F - - - PERFSEL2 - Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. - [6:0] - read-write - - - siob_proc1_stall_upstream - 0 - - - siob_proc1_stall_downstream - 1 - - - siob_proc1_access_contested - 2 - - - siob_proc1_access - 3 - - - siob_proc0_stall_upstream - 4 - - - siob_proc0_stall_downstream - 5 - - - siob_proc0_access_contested - 6 - - - siob_proc0_access - 7 - - - apb_stall_upstream - 8 - - - apb_stall_downstream - 9 - - - apb_access_contested - 10 - - - apb_access - 11 - - - fastperi_stall_upstream - 12 - - - fastperi_stall_downstream - 13 - - - fastperi_access_contested - 14 - - - fastperi_access - 15 - - - sram9_stall_upstream - 16 - - - sram9_stall_downstream - 17 - - - sram9_access_contested - 18 - - - sram9_access - 19 - - - sram8_stall_upstream - 20 - - - sram8_stall_downstream - 21 - - - sram8_access_contested - 22 - - - sram8_access - 23 - - - sram7_stall_upstream - 24 - - - sram7_stall_downstream - 25 - - - sram7_access_contested - 26 - - - sram7_access - 27 - - - sram6_stall_upstream - 28 - - - sram6_stall_downstream - 29 - - - sram6_access_contested - 30 - - - sram6_access - 31 - - - sram5_stall_upstream - 32 - - - sram5_stall_downstream - 33 - - - sram5_access_contested - 34 - - - sram5_access - 35 - - - sram4_stall_upstream - 36 - - - sram4_stall_downstream - 37 - - - sram4_access_contested - 38 - - - sram4_access - 39 - - - sram3_stall_upstream - 40 - - - sram3_stall_downstream - 41 - - - sram3_access_contested - 42 - - - sram3_access - 43 - - - sram2_stall_upstream - 44 - - - sram2_stall_downstream - 45 - - - sram2_access_contested - 46 - - - sram2_access - 47 - - - sram1_stall_upstream - 48 - - - sram1_stall_downstream - 49 - - - sram1_access_contested - 50 - - - sram1_access - 51 - - - sram0_stall_upstream - 52 - - - sram0_stall_downstream - 53 - - - sram0_access_contested - 54 - - - sram0_access - 55 - - - xip_main1_stall_upstream - 56 - - - xip_main1_stall_downstream - 57 - - - xip_main1_access_contested - 58 - - - xip_main1_access - 59 - - - xip_main0_stall_upstream - 60 - - - xip_main0_stall_downstream - 61 - - - xip_main0_access_contested - 62 - - - xip_main0_access - 63 - - - rom_stall_upstream - 64 - - - rom_stall_downstream - 65 - - - rom_access_contested - 66 - - - rom_access - 67 - - - - - - - PERFCTR3 - Bus fabric performance counter 3 - 0x24 - 0x00000000 - - - PERFCTR3 - Busfabric saturating performance counter 3 - Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. - Write any value to clear. Select an event to count using PERFSEL3 - [23:0] - read-write - oneToClear - - - - - PERFSEL3 - Bus fabric performance event select for PERFCTR3 - 0x28 - 0x0000001F - - - PERFSEL3 - Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. - [6:0] - read-write - - - siob_proc1_stall_upstream - 0 - - - siob_proc1_stall_downstream - 1 - - - siob_proc1_access_contested - 2 - - - siob_proc1_access - 3 - - - siob_proc0_stall_upstream - 4 - - - siob_proc0_stall_downstream - 5 - - - siob_proc0_access_contested - 6 - - - siob_proc0_access - 7 - - - apb_stall_upstream - 8 - - - apb_stall_downstream - 9 - - - apb_access_contested - 10 - - - apb_access - 11 - - - fastperi_stall_upstream - 12 - - - fastperi_stall_downstream - 13 - - - fastperi_access_contested - 14 - - - fastperi_access - 15 - - - sram9_stall_upstream - 16 - - - sram9_stall_downstream - 17 - - - sram9_access_contested - 18 - - - sram9_access - 19 - - - sram8_stall_upstream - 20 - - - sram8_stall_downstream - 21 - - - sram8_access_contested - 22 - - - sram8_access - 23 - - - sram7_stall_upstream - 24 - - - sram7_stall_downstream - 25 - - - sram7_access_contested - 26 - - - sram7_access - 27 - - - sram6_stall_upstream - 28 - - - sram6_stall_downstream - 29 - - - sram6_access_contested - 30 - - - sram6_access - 31 - - - sram5_stall_upstream - 32 - - - sram5_stall_downstream - 33 - - - sram5_access_contested - 34 - - - sram5_access - 35 - - - sram4_stall_upstream - 36 - - - sram4_stall_downstream - 37 - - - sram4_access_contested - 38 - - - sram4_access - 39 - - - sram3_stall_upstream - 40 - - - sram3_stall_downstream - 41 - - - sram3_access_contested - 42 - - - sram3_access - 43 - - - sram2_stall_upstream - 44 - - - sram2_stall_downstream - 45 - - - sram2_access_contested - 46 - - - sram2_access - 47 - - - sram1_stall_upstream - 48 - - - sram1_stall_downstream - 49 - - - sram1_access_contested - 50 - - - sram1_access - 51 - - - sram0_stall_upstream - 52 - - - sram0_stall_downstream - 53 - - - sram0_access_contested - 54 - - - sram0_access - 55 - - - xip_main1_stall_upstream - 56 - - - xip_main1_stall_downstream - 57 - - - xip_main1_access_contested - 58 - - - xip_main1_access - 59 - - - xip_main0_stall_upstream - 60 - - - xip_main0_stall_downstream - 61 - - - xip_main0_access_contested - 62 - - - xip_main0_access - 63 - - - rom_stall_upstream - 64 - - - rom_stall_downstream - 65 - - - rom_access_contested - 66 - - - rom_access - 67 - - - - - - - - - SIO - Single-cycle IO block - Provides core-local and inter-core hardware for the two processors, with single-cycle access. - 0xD0000000 - - 0x0 - 0x1E8 - registers - - - SIO_IRQ_FIFO - 25 - - - SIO_IRQ_BELL - 26 - - - SIO_IRQ_FIFO_NS - 27 - - - SIO_IRQ_BELL_NS - 28 - - - SIO_IRQ_MTIMECMP - 29 - - - - CPUID - Processor core identifier - 0x0 - 0x00000000 - - - CPUID - Value is 0 when read from processor core 0, and 1 when read from processor core 1. - [31:0] - read-only - - - - - GPIO_IN - Input value for GPIO0...31. - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. - 0x4 - 0x00000000 - - - GPIO_IN - [31:0] - read-only - - - - - GPIO_HI_IN - Input value on GPIO32...47, QSPI IOs and USB pins - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. - 0x8 - 0x00000000 - - - QSPI_SD - Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins - [31:28] - read-only - - - QSPI_CSN - Input value on QSPI CSn pin - [27:27] - read-only - - - QSPI_SCK - Input value on QSPI SCK pin - [26:26] - read-only - - - USB_DM - Input value on USB D- pin - [25:25] - read-only - - - USB_DP - Input value on USB D+ pin - [24:24] - read-only - - - GPIO - Input value on GPIO32...47 - [15:0] - read-only - - - - - GPIO_OUT - GPIO0...31 output value - 0x10 - 0x00000000 - - - GPIO_OUT - Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. - - If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. - [31:0] - read-write - - - - - GPIO_HI_OUT - Output value for GPIO32...47, QSPI IOs and USB pins. - - Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. - 0x14 - 0x00000000 - - - QSPI_SD - Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins - [31:28] - read-write - - - QSPI_CSN - Output value for QSPI CSn pin - [27:27] - read-write - - - QSPI_SCK - Output value for QSPI SCK pin - [26:26] - read-write - - - USB_DM - Output value for USB D- pin - [25:25] - read-write - - - USB_DP - Output value for USB D+ pin - [24:24] - read-write - - - GPIO - Output value for GPIO32...47 - [15:0] - read-write - - - - - GPIO_OUT_SET - GPIO0...31 output value set - 0x18 - 0x00000000 - - - GPIO_OUT_SET - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` - [31:0] - write-only - - - - - GPIO_HI_OUT_SET - Output value set for GPIO32..47, QSPI IOs and USB pins. - Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` - 0x1C - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - GPIO_OUT_CLR - GPIO0...31 output value clear - 0x20 - 0x00000000 - - - GPIO_OUT_CLR - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` - [31:0] - write-only - - - - - GPIO_HI_OUT_CLR - Output value clear for GPIO32..47, QSPI IOs and USB pins. - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` - 0x24 - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - GPIO_OUT_XOR - GPIO0...31 output value XOR - 0x28 - 0x00000000 - - - GPIO_OUT_XOR - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` - [31:0] - write-only - - - - - GPIO_HI_OUT_XOR - Output value XOR for GPIO32..47, QSPI IOs and USB pins. - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` - 0x2C - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - GPIO_OE - GPIO0...31 output enable - 0x30 - 0x00000000 - - - GPIO_OE - Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. - - If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. - [31:0] - read-write - - - - - GPIO_HI_OE - Output enable value for GPIO32...47, QSPI IOs and USB pins. - - Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. - 0x34 - 0x00000000 - - - QSPI_SD - Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins - [31:28] - read-write - - - QSPI_CSN - Output enable value for QSPI CSn pin - [27:27] - read-write - - - QSPI_SCK - Output enable value for QSPI SCK pin - [26:26] - read-write - - - USB_DM - Output enable value for USB D- pin - [25:25] - read-write - - - USB_DP - Output enable value for USB D+ pin - [24:24] - read-write - - - GPIO - Output enable value for GPIO32...47 - [15:0] - read-write - - - - - GPIO_OE_SET - GPIO0...31 output enable set - 0x38 - 0x00000000 - - - GPIO_OE_SET - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` - [31:0] - write-only - - - - - GPIO_HI_OE_SET - Output enable set for GPIO32...47, QSPI IOs and USB pins. - Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` - 0x3C - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - GPIO_OE_CLR - GPIO0...31 output enable clear - 0x40 - 0x00000000 - - - GPIO_OE_CLR - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` - [31:0] - write-only - - - - - GPIO_HI_OE_CLR - Output enable clear for GPIO32...47, QSPI IOs and USB pins. - Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` - 0x44 - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - GPIO_OE_XOR - GPIO0...31 output enable XOR - 0x48 - 0x00000000 - - - GPIO_OE_XOR - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` - [31:0] - write-only - - - - - GPIO_HI_OE_XOR - Output enable XOR for GPIO32...47, QSPI IOs and USB pins. - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` - 0x4C - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - FIFO_ST - Status register for inter-core FIFOs (mailboxes). - There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. - Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). - Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). - The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. - 0x50 - 0x00000002 - - - ROE - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. - [3:3] - read-write - oneToClear - - - WOF - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. - [2:2] - read-write - oneToClear - - - RDY - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) - [1:1] - read-only - - - VLD - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) - [0:0] - read-only - - - - - FIFO_WR - Write access to this core's TX FIFO - 0x54 - 0x00000000 - - - FIFO_WR - [31:0] - write-only - - - - - FIFO_RD - Read access to this core's RX FIFO - 0x58 - 0x00000000 - - - FIFO_RD - [31:0] - read-only - modify - - - - - SPINLOCK_ST - Spinlock state - A bitmap containing the state of all 32 spinlocks (1=locked). - Mainly intended for debugging. - 0x5C - 0x00000000 - - - SPINLOCK_ST - [31:0] - read-only - - - - - INTERP0_ACCUM0 - Read/write access to accumulator 0 - 0x80 - 0x00000000 - - - INTERP0_ACCUM0 - [31:0] - read-write - - - - - INTERP0_ACCUM1 - Read/write access to accumulator 1 - 0x84 - 0x00000000 - - - INTERP0_ACCUM1 - [31:0] - read-write - - - - - INTERP0_BASE0 - Read/write access to BASE0 register. - 0x88 - 0x00000000 - - - INTERP0_BASE0 - [31:0] - read-write - - - - - INTERP0_BASE1 - Read/write access to BASE1 register. - 0x8C - 0x00000000 - - - INTERP0_BASE1 - [31:0] - read-write - - - - - INTERP0_BASE2 - Read/write access to BASE2 register. - 0x90 - 0x00000000 - - - INTERP0_BASE2 - [31:0] - read-write - - - - - INTERP0_POP_LANE0 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0x94 - 0x00000000 - - - INTERP0_POP_LANE0 - [31:0] - read-only - - - - - INTERP0_POP_LANE1 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0x98 - 0x00000000 - - - INTERP0_POP_LANE1 - [31:0] - read-only - - - - - INTERP0_POP_FULL - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0x9C - 0x00000000 - - - INTERP0_POP_FULL - [31:0] - read-only - - - - - INTERP0_PEEK_LANE0 - Read LANE0 result, without altering any internal state (PEEK). - 0xA0 - 0x00000000 - - - INTERP0_PEEK_LANE0 - [31:0] - read-only - - - - - INTERP0_PEEK_LANE1 - Read LANE1 result, without altering any internal state (PEEK). - 0xA4 - 0x00000000 - - - INTERP0_PEEK_LANE1 - [31:0] - read-only - - - - - INTERP0_PEEK_FULL - Read FULL result, without altering any internal state (PEEK). - 0xA8 - 0x00000000 - - - INTERP0_PEEK_FULL - [31:0] - read-only - - - - - INTERP0_CTRL_LANE0 - Control register for lane 0 - 0xAC - 0x00000000 - - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only - - - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only - - - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only - - - BLEND - Only present on INTERP0 on each core. If BLEND mode is enabled: - - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled - by the 8 LSBs of lane 1 shift and mask value (a fractional number between - 0 and 255/256ths) - - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) - LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. - [21:21] - read-write - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. - [4:0] - read-write - - - - - INTERP0_CTRL_LANE1 - Control register for lane 1 - 0xB0 - 0x00000000 - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. - [4:0] - read-write - - - - - INTERP0_ACCUM0_ADD - Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0xB4 - 0x00000000 - - - INTERP0_ACCUM0_ADD - [23:0] - read-write - - - - - INTERP0_ACCUM1_ADD - Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0xB8 - 0x00000000 - - - INTERP0_ACCUM1_ADD - [23:0] - read-write - - - - - INTERP0_BASE_1AND0 - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0xBC - 0x00000000 - - - INTERP0_BASE_1AND0 - [31:0] - write-only - - - - - INTERP1_ACCUM0 - Read/write access to accumulator 0 - 0xC0 - 0x00000000 - - - INTERP1_ACCUM0 - [31:0] - read-write - - - - - INTERP1_ACCUM1 - Read/write access to accumulator 1 - 0xC4 - 0x00000000 - - - INTERP1_ACCUM1 - [31:0] - read-write - - - - - INTERP1_BASE0 - Read/write access to BASE0 register. - 0xC8 - 0x00000000 - - - INTERP1_BASE0 - [31:0] - read-write - - - - - INTERP1_BASE1 - Read/write access to BASE1 register. - 0xCC - 0x00000000 - - - INTERP1_BASE1 - [31:0] - read-write - - - - - INTERP1_BASE2 - Read/write access to BASE2 register. - 0xD0 - 0x00000000 - - - INTERP1_BASE2 - [31:0] - read-write - - - - - INTERP1_POP_LANE0 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0xD4 - 0x00000000 - - - INTERP1_POP_LANE0 - [31:0] - read-only - - - - - INTERP1_POP_LANE1 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0xD8 - 0x00000000 - - - INTERP1_POP_LANE1 - [31:0] - read-only - - - - - INTERP1_POP_FULL - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0xDC - 0x00000000 - - - INTERP1_POP_FULL - [31:0] - read-only - - - - - INTERP1_PEEK_LANE0 - Read LANE0 result, without altering any internal state (PEEK). - 0xE0 - 0x00000000 - - - INTERP1_PEEK_LANE0 - [31:0] - read-only - - - - - INTERP1_PEEK_LANE1 - Read LANE1 result, without altering any internal state (PEEK). - 0xE4 - 0x00000000 - - - INTERP1_PEEK_LANE1 - [31:0] - read-only - - - - - INTERP1_PEEK_FULL - Read FULL result, without altering any internal state (PEEK). - 0xE8 - 0x00000000 - - - INTERP1_PEEK_FULL - [31:0] - read-only - - - - - INTERP1_CTRL_LANE0 - Control register for lane 0 - 0xEC - 0x00000000 - - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only - - - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only - - - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only - - - CLAMP - Only present on INTERP1 on each core. If CLAMP mode is enabled: - - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of - BASE0 and an upper bound of BASE1. - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED - [22:22] - read-write - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. - [4:0] - read-write - - - - - INTERP1_CTRL_LANE1 - Control register for lane 1 - 0xF0 - 0x00000000 - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. - [4:0] - read-write - - - - - INTERP1_ACCUM0_ADD - Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0xF4 - 0x00000000 - - - INTERP1_ACCUM0_ADD - [23:0] - read-write - - - - - INTERP1_ACCUM1_ADD - Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0xF8 - 0x00000000 - - - INTERP1_ACCUM1_ADD - [23:0] - read-write - - - - - INTERP1_BASE_1AND0 - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0xFC - 0x00000000 - - - INTERP1_BASE_1AND0 - [31:0] - write-only - - - - - 32 - 0x4 - 0-31 - SPINLOCK%s - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x100 - read-write - 0x00000000 - - - SPINLOCK0 - [31:0] - read-write - modify - - - - - DOORBELL_OUT_SET - Trigger a doorbell interrupt on the opposite core. - - Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. - - Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status. - 0x180 - 0x00000000 - - - DOORBELL_OUT_SET - [7:0] - read-write - - - - - DOORBELL_OUT_CLR - Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. - - Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. - - Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status. - 0x184 - 0x00000000 - - - DOORBELL_OUT_CLR - [7:0] - read-write - oneToClear - - - - - DOORBELL_IN_SET - Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core. - 0x188 - 0x00000000 - - - DOORBELL_IN_SET - [7:0] - read-write - - - - - DOORBELL_IN_CLR - Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. - - Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core. - 0x18C - 0x00000000 - - - DOORBELL_IN_CLR - [7:0] - read-write - oneToClear - - - - - PERI_NONSEC - Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. - - This register is per-core, and is only present on the Secure SIO. - - Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register. - 0x190 - 0x00000000 - - - TMDS - IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO. - [5:5] - read-write - - - INTERP1 - If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO. - [1:1] - read-write - - - INTERP0 - If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO. - [0:0] - read-write - - - - - RISCV_SOFTIRQ - Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. - - Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. - - It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect. - 0x1A0 - 0x00000000 - - - CORE1_CLR - Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag. - [9:9] - read-write - - - CORE0_CLR - Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag. - [8:8] - read-write - - - CORE1_SET - Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag. - [1:1] - read-write - - - CORE0_SET - Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag. - [0:0] - read-write - - - - - MTIME_CTRL - Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. - - Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores. - 0x1A4 - 0x0000000D - - - DBGPAUSE_CORE1 - If 1, the timer pauses when core 1 is in the debug halt state. - [3:3] - read-write - - - DBGPAUSE_CORE0 - If 1, the timer pauses when core 0 is in the debug halt state. - [2:2] - read-write - - - FULLSPEED - If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input. - [1:1] - read-write - - - EN - Timer enable bit. When 0, the timer will not increment automatically. - [0:0] - read-write - - - - - MTIME - Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. - 0x1B0 - 0x00000000 - - - MTIME - [31:0] - read-write - - - - - MTIMEH - Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. - 0x1B4 - 0x00000000 - - - MTIMEH - [31:0] - read-write - - - - - MTIMECMP - Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. - - The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. - 0x1B8 - 0xFFFFFFFF - - - MTIMECMP - [31:0] - read-write - - - - - MTIMECMPH - High half of RISC-V Machine-mode timer comparator. This register is core-local. - - The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. - 0x1BC - 0xFFFFFFFF - - - MTIMECMPH - [31:0] - read-write - - - - - TMDS_CTRL - Control register for TMDS encoder. - 0x1C0 - 0x00000000 - - - CLEAR_BALANCE - Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline. - [28:28] - write-only - - - PIX2_NOSHIFT - When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. - - This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling. - [27:27] - read-write - - - PIX_SHIFT - Shift applied to the colour data register with each read of a POP alias register. - - Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. - - Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.) - [26:24] - read-write - - - 0 - Do not shift the colour data register. - 0 - - - 1 - Shift the colour data register by 1 bit - 1 - - - 2 - Shift the colour data register by 2 bits - 2 - - - 4 - Shift the colour data register by 4 bits - 3 - - - 8 - Shift the colour data register by 8 bits - 4 - - - 16 - Shift the colour data register by 16 bits - 5 - - - - - INTERLEAVE - Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. - - When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. - - When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant. - [23:23] - read-write - - - L2_NBITS - Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. - [20:18] - read-write - - - L1_NBITS - Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. - [17:15] - read-write - - - L0_NBITS - Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. - [14:12] - read-write - - - L2_ROT - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. - - For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input. - [11:8] - read-write - - - L1_ROT - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. - - For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input. - [7:4] - read-write - - - L0_ROT - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. - - For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input. - [3:0] - read-write - - - - - TMDS_WDATA - Write-only access to the TMDS colour data register. - 0x1C4 - 0x00000000 - - - TMDS_WDATA - [31:0] - write-only - - - - - TMDS_PEEK_SINGLE - Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). - - The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling. - 0x1C8 - 0x00000000 - - - TMDS_PEEK_SINGLE - [31:0] - read-only - modify - - - - - TMDS_POP_SINGLE - Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. - - The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder. - 0x1CC - 0x00000000 - - - TMDS_POP_SINGLE - [31:0] - read-only - modify - - - - - TMDS_PEEK_DOUBLE_L0 - Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. - 0x1D0 - 0x00000000 - - - TMDS_PEEK_DOUBLE_L0 - [31:0] - read-only - modify - - - - - TMDS_POP_DOUBLE_L0 - Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. - 0x1D4 - 0x00000000 - - - TMDS_POP_DOUBLE_L0 - [31:0] - read-only - modify - - - - - TMDS_PEEK_DOUBLE_L1 - Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. - 0x1D8 - 0x00000000 - - - TMDS_PEEK_DOUBLE_L1 - [31:0] - read-only - modify - - - - - TMDS_POP_DOUBLE_L1 - Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. - 0x1DC - 0x00000000 - - - TMDS_POP_DOUBLE_L1 - [31:0] - read-only - modify - - - - - TMDS_PEEK_DOUBLE_L2 - Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. - 0x1E0 - 0x00000000 - - - TMDS_PEEK_DOUBLE_L2 - [31:0] - read-only - modify - - - - - TMDS_POP_DOUBLE_L2 - Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. - 0x1E4 - 0x00000000 - - - TMDS_POP_DOUBLE_L2 - [31:0] - read-only - modify - - - - - - - SIO_NS - 0xD0020000 - - - BOOTRAM - Additional registers mapped adjacent to the bootram, for use by the bootrom. - 0x400E0000 - - 0x0 - 0x82C - registers - - - - WRITE_ONCE0 - This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. - 0x800 - 0x00000000 - - - WRITE_ONCE0 - [31:0] - read-write - - - - - WRITE_ONCE1 - This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. - 0x804 - 0x00000000 - - - WRITE_ONCE1 - [31:0] - read-write - - - - - BOOTLOCK_STAT - Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use. - 0x808 - 0x000000FF - - - BOOTLOCK_STAT - [7:0] - read-write - - - - - BOOTLOCK0 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x80C - 0x00000000 - - - BOOTLOCK0 - [31:0] - read-write - - - - - BOOTLOCK1 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x810 - 0x00000000 - - - BOOTLOCK1 - [31:0] - read-write - - - - - BOOTLOCK2 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x814 - 0x00000000 - - - BOOTLOCK2 - [31:0] - read-write - - - - - BOOTLOCK3 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x818 - 0x00000000 - - - BOOTLOCK3 - [31:0] - read-write - - - - - BOOTLOCK4 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x81C - 0x00000000 - - - BOOTLOCK4 - [31:0] - read-write - - - - - BOOTLOCK5 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x820 - 0x00000000 - - - BOOTLOCK5 - [31:0] - read-write - - - - - BOOTLOCK6 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x824 - 0x00000000 - - - BOOTLOCK6 - [31:0] - read-write - - - - - BOOTLOCK7 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x828 - 0x00000000 - - - BOOTLOCK7 - [31:0] - read-write - - - - - - - CORESIGHT_TRACE - Coresight block - RP specific registers - 0x50700000 - - 0x0 - 0x8 - registers - - - - CTRL_STATUS - Control and status register - 0x0 - 0x00000001 - - - TRACE_CAPTURE_FIFO_OVERFLOW - This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit. - [1:1] - read-write - - - TRACE_CAPTURE_FIFO_FLUSH - Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. - - Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. - - Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU. - [0:0] - read-write - - - - - TRACE_CAPTURE_FIFO - FIFO for trace data captured from the TPIU - 0x4 - 0x00000000 - - - RDATA - Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU. - - Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true: - - * TPIU TRACECTL output is low (normal trace data) - - * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet) - - These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices - - The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock. - [31:0] - read-only - modify - - - - - - - USB - USB FS/LS controller device registers - 0x50110000 - - 0x0 - 0x118 - registers - - - USBCTRL_IRQ - 14 - - - - ADDR_ENDP - Device address and endpoint control - 0x0 - 0x00000000 - - - ENDPOINT - Device endpoint to send data to. Only valid for HOST mode. - [19:16] - read-write - - - ADDRESS - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. - [6:0] - read-write - - - - - 15 - 0x4 - 1-15 - HOST_ADDR_ENDP%s - Interrupt endpoints. Only valid in HOST mode. - 0x4 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - MAIN_CTRL - Main control register - 0x40 - 0x00000004 - - - SIM_TIMING - Reduced timings for simulation - [31:31] - read-write - - - PHY_ISO - Isolates USB phy after controller power-up - Remove isolation once software has configured the controller - Not isolated = 0, Isolated = 1 - [2:2] - read-write - - - HOST_NDEVICE - Device mode = 0, Host mode = 1 - [1:1] - read-write - - - CONTROLLER_EN - Enable controller - [0:0] - read-write - - - - - SOF_WR - Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. - 0x44 - 0x00000000 - - - COUNT - [10:0] - write-only - - - - - SOF_RD - Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. - 0x48 - 0x00000000 - - - COUNT - [10:0] - read-only - - - - - SIE_CTRL - SIE control register - 0x4C - 0x00008000 - - - EP0_INT_STALL - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL - [31:31] - read-write - - - EP0_DOUBLE_BUF - Device: EP0 single buffered = 0, double buffered = 1 - [30:30] - read-write - - - EP0_INT_1BUF - Device: Set bit in BUFF_STATUS for every buffer completed on EP0 - [29:29] - read-write - - - EP0_INT_2BUF - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 - [28:28] - read-write - - - EP0_INT_NAK - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK - [27:27] - read-write - - - DIRECT_EN - Direct bus drive enable - [26:26] - read-write - - - DIRECT_DP - Direct control of DP - [25:25] - read-write - - - DIRECT_DM - Direct control of DM - [24:24] - read-write - - - EP0_STOP_ON_SHORT_PACKET - Device: Stop EP0 on a short packet. - [19:19] - read-write - - - TRANSCEIVER_PD - Power down bus transceiver - [18:18] - read-write - - - RPU_OPT - Device: Pull-up strength (0=1K2, 1=2k3) - [17:17] - read-write - - - PULLUP_EN - Device: Enable pull up resistor - [16:16] - read-write - - - PULLDOWN_EN - Host: Enable pull down resistors - [15:15] - read-write - - - RESET_BUS - Host: Reset bus - [13:13] - write-only - - - RESUME - Device: Remote wakeup. Device can initiate its own resume after suspend. - [12:12] - write-only - - - VBUS_EN - Host: Enable VBUS - [11:11] - read-write - - - KEEP_ALIVE_EN - Host: Enable keep alive packet (for low speed bus) - [10:10] - read-write - - - SOF_EN - Host: Enable SOF generation (for full speed bus) - [9:9] - read-write - - - SOF_SYNC - Host: Delay packet(s) until after SOF - [8:8] - read-write - - - PREAMBLE_EN - Host: Preable enable for LS device on FS hub - [6:6] - read-write - - - STOP_TRANS - Host: Stop transaction - [4:4] - write-only - - - RECEIVE_DATA - Host: Receive transaction (IN to host) - [3:3] - read-write - - - SEND_DATA - Host: Send transaction (OUT from host) - [2:2] - read-write - - - SEND_SETUP - Host: Send Setup packet - [1:1] - read-write - - - START_TRANS - Host: Start transaction - [0:0] - write-only - - - - - SIE_STATUS - SIE status register - 0x50 - 0x00000000 - - - DATA_SEQ_ERROR - Data Sequence Error. - - The device can raise a sequence error in the following conditions: - - * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM - - The host can raise a data sequence error in the following conditions: - - * An IN packet from the device has the wrong data PID - [31:31] - read-write - oneToClear - - - ACK_REC - ACK received. Raised by both host and device. - [30:30] - read-write - oneToClear - - - STALL_REC - Host: STALL received - [29:29] - read-write - oneToClear - - - NAK_REC - Host: NAK received - [28:28] - read-write - oneToClear - - - RX_TIMEOUT - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. - [27:27] - read-write - oneToClear - - - RX_OVERFLOW - RX overflow is raised by the Serial RX engine if the incoming data is too fast. - [26:26] - read-write - oneToClear - - - BIT_STUFF_ERROR - Bit Stuff Error. Raised by the Serial RX engine. - [25:25] - read-write - oneToClear - - - CRC_ERROR - CRC Error. Raised by the Serial RX engine. - [24:24] - read-write - oneToClear - - - ENDPOINT_ERROR - An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error. - [23:23] - read-write - oneToClear - - - BUS_RESET - Device: bus reset received - [19:19] - read-write - oneToClear - - - TRANS_COMPLETE - Transaction complete. - - Raised by device if: - - * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register - - Raised by host if: - - * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set - [18:18] - read-write - oneToClear - - - SETUP_REC - Device: Setup packet received - [17:17] - read-write - oneToClear - - - CONNECTED - Device: connected - [16:16] - read-only - - - RX_SHORT_PACKET - Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early. - [12:12] - read-write - oneToClear - - - RESUME - Host: Device has initiated a remote resume. Device: host has initiated a resume. - [11:11] - read-write - oneToClear - - - VBUS_OVER_CURR - VBUS over current detected - [10:10] - read-only - - - SPEED - Host: device speed. Disconnected = 00, LS = 01, FS = 10 - [9:8] - read-only - - - SUSPENDED - Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled. - [4:4] - read-write - oneToClear - - - LINE_STATE - USB bus line state - [3:2] - read-only - - LINE_STATE - - SE0 - SE0 - 0 - - - J - J - 1 - - - K - K - 2 - - - SE1 - SE1 - 3 - - - - - VBUS_DETECTED - Device: VBUS Detected - [0:0] - read-only - - - - - INT_EP_CTRL - interrupt endpoint control register - 0x54 - 0x00000000 - - - INT_EP_ACTIVE - Host: Enable interrupt endpoint 1 -> 15 - [15:1] - read-write - - - - - BUFF_STATUS - Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. - 0x58 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - BUFF_CPU_SHOULD_HANDLE - Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. - 0x5C - 0x00000000 - - - EP15_OUT - [31:31] - read-only - - - EP15_IN - [30:30] - read-only - - - EP14_OUT - [29:29] - read-only - - - EP14_IN - [28:28] - read-only - - - EP13_OUT - [27:27] - read-only - - - EP13_IN - [26:26] - read-only - - - EP12_OUT - [25:25] - read-only - - - EP12_IN - [24:24] - read-only - - - EP11_OUT - [23:23] - read-only - - - EP11_IN - [22:22] - read-only - - - EP10_OUT - [21:21] - read-only - - - EP10_IN - [20:20] - read-only - - - EP9_OUT - [19:19] - read-only - - - EP9_IN - [18:18] - read-only - - - EP8_OUT - [17:17] - read-only - - - EP8_IN - [16:16] - read-only - - - EP7_OUT - [15:15] - read-only - - - EP7_IN - [14:14] - read-only - - - EP6_OUT - [13:13] - read-only - - - EP6_IN - [12:12] - read-only - - - EP5_OUT - [11:11] - read-only - - - EP5_IN - [10:10] - read-only - - - EP4_OUT - [9:9] - read-only - - - EP4_IN - [8:8] - read-only - - - EP3_OUT - [7:7] - read-only - - - EP3_IN - [6:6] - read-only - - - EP2_OUT - [5:5] - read-only - - - EP2_IN - [4:4] - read-only - - - EP1_OUT - [3:3] - read-only - - - EP1_IN - [2:2] - read-only - - - EP0_OUT - [1:1] - read-only - - - EP0_IN - [0:0] - read-only - - - - - EP_ABORT - Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. - 0x60 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - - - EP15_IN - [30:30] - read-write - - - EP14_OUT - [29:29] - read-write - - - EP14_IN - [28:28] - read-write - - - EP13_OUT - [27:27] - read-write - - - EP13_IN - [26:26] - read-write - - - EP12_OUT - [25:25] - read-write - - - EP12_IN - [24:24] - read-write - - - EP11_OUT - [23:23] - read-write - - - EP11_IN - [22:22] - read-write - - - EP10_OUT - [21:21] - read-write - - - EP10_IN - [20:20] - read-write - - - EP9_OUT - [19:19] - read-write - - - EP9_IN - [18:18] - read-write - - - EP8_OUT - [17:17] - read-write - - - EP8_IN - [16:16] - read-write - - - EP7_OUT - [15:15] - read-write - - - EP7_IN - [14:14] - read-write - - - EP6_OUT - [13:13] - read-write - - - EP6_IN - [12:12] - read-write - - - EP5_OUT - [11:11] - read-write - - - EP5_IN - [10:10] - read-write - - - EP4_OUT - [9:9] - read-write - - - EP4_IN - [8:8] - read-write - - - EP3_OUT - [7:7] - read-write - - - EP3_IN - [6:6] - read-write - - - EP2_OUT - [5:5] - read-write - - - EP2_IN - [4:4] - read-write - - - EP1_OUT - [3:3] - read-write - - - EP1_IN - [2:2] - read-write - - - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] - read-write - - - - - EP_ABORT_DONE - Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. - 0x64 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - EP_STALL_ARM - Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. - 0x68 - 0x00000000 - - - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] - read-write - - - - - NAK_POLL - Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. - 0x6C - 0x00100010 - - - RETRY_COUNT_HI - Bits 9:6 of nak_retry count - [31:28] - read-only - - - EPX_STOPPED_ON_NAK - EPX polling has stopped because a nak was received - [27:27] - read-write - oneToClear - - - STOP_EPX_ON_NAK - Stop polling epx when a nak is received - [26:26] - read-write - - - DELAY_FS - NAK polling interval for a full speed device - [25:16] - read-write - - - RETRY_COUNT_LO - Bits 5:0 of nak_retry_count - [15:10] - read-only - - - DELAY_LS - NAK polling interval for a low speed device - [9:0] - read-write - - - - - EP_STATUS_STALL_NAK - Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. - 0x70 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - USB_MUXING - Where to connect the USB controller. Should be to_phy by default. - 0x74 - 0x00000001 - - - SWAP_DPDM - Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. - This is done at a low level so overrides all other controls. - [31:31] - read-write - - - USBPHY_AS_GPIO - Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller. - [4:4] - read-write - - - SOFTCON - [3:3] - read-write - - - TO_DIGITAL_PAD - [2:2] - read-write - - - TO_EXTPHY - [1:1] - read-write - - - TO_PHY - [0:0] - read-write - - - - - USB_PWR - Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. - 0x78 - 0x00000000 - - - OVERCURR_DETECT_EN - [5:5] - read-write - - - OVERCURR_DETECT - [4:4] - read-write - - - VBUS_DETECT_OVERRIDE_EN - [3:3] - read-write - - - VBUS_DETECT - [2:2] - read-write - - - VBUS_EN_OVERRIDE_EN - [1:1] - read-write - - - VBUS_EN - [0:0] - read-write - - - - - USBPHY_DIRECT - This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. - 0x7C - 0x00000000 - - - RX_DM_OVERRIDE - Override rx_dm value into controller - [25:25] - read-write - - - RX_DP_OVERRIDE - Override rx_dp value into controller - [24:24] - read-write - - - RX_DD_OVERRIDE - Override rx_dd value into controller - [23:23] - read-write - - - DM_OVV - DM over voltage - [22:22] - read-only - - - DP_OVV - DP over voltage - [21:21] - read-only - - - DM_OVCN - DM overcurrent - [20:20] - read-only - - - DP_OVCN - DP overcurrent - [19:19] - read-only - - - RX_DM - DPM pin state - [18:18] - read-only - - - RX_DP - DPP pin state - [17:17] - read-only - - - RX_DD - Differential RX - [16:16] - read-only - - - TX_DIFFMODE - TX_DIFFMODE=0: Single ended mode - TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) - [15:15] - read-write - - - TX_FSSLEW - TX_FSSLEW=0: Low speed slew rate - TX_FSSLEW=1: Full speed slew rate - [14:14] - read-write - - - TX_PD - TX power down override (if override enable is set). 1 = powered down. - [13:13] - read-write - - - RX_PD - RX power down override (if override enable is set). 1 = powered down. - [12:12] - read-write - - - TX_DM - Output data. TX_DIFFMODE=1, Ignored - TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM - [11:11] - read-write - - - TX_DP - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP - If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP - [10:10] - read-write - - - TX_DM_OE - Output enable. If TX_DIFFMODE=1, Ignored. - If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving - [9:9] - read-write - - - TX_DP_OE - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving - If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving - [8:8] - read-write - - - DM_PULLDN_EN - DM pull down enable - [6:6] - read-write - - - DM_PULLUP_EN - DM pull up enable - [5:5] - read-write - - - DM_PULLUP_HISEL - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [4:4] - read-write - - - DP_PULLDN_EN - DP pull down enable - [2:2] - read-write - - - DP_PULLUP_EN - DP pull up enable - [1:1] - read-write - - - DP_PULLUP_HISEL - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [0:0] - read-write - - - - - USBPHY_DIRECT_OVERRIDE - Override enable for each control in usbphy_direct - 0x80 - 0x00000000 - - - RX_DM_OVERRIDE_EN - [18:18] - read-write - - - RX_DP_OVERRIDE_EN - [17:17] - read-write - - - RX_DD_OVERRIDE_EN - [16:16] - read-write - - - TX_DIFFMODE_OVERRIDE_EN - [15:15] - read-write - - - DM_PULLUP_OVERRIDE_EN - [12:12] - read-write - - - TX_FSSLEW_OVERRIDE_EN - [11:11] - read-write - - - TX_PD_OVERRIDE_EN - [10:10] - read-write - - - RX_PD_OVERRIDE_EN - [9:9] - read-write - - - TX_DM_OVERRIDE_EN - [8:8] - read-write - - - TX_DP_OVERRIDE_EN - [7:7] - read-write - - - TX_DM_OE_OVERRIDE_EN - [6:6] - read-write - - - TX_DP_OE_OVERRIDE_EN - [5:5] - read-write - - - DM_PULLDN_EN_OVERRIDE_EN - [4:4] - read-write - - - DP_PULLDN_EN_OVERRIDE_EN - [3:3] - read-write - - - DP_PULLUP_EN_OVERRIDE_EN - [2:2] - read-write - - - DM_PULLUP_HISEL_OVERRIDE_EN - [1:1] - read-write - - - DP_PULLUP_HISEL_OVERRIDE_EN - [0:0] - read-write - - - - - USBPHY_TRIM - Used to adjust trim values of USB phy pull down resistors. - 0x84 - 0x00001F1F - - - DM_PULLDN_TRIM - Value to drive to USB PHY - DM pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [12:8] - read-write - - - DP_PULLDN_TRIM - Value to drive to USB PHY - DP pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [4:0] - read-write - - - - - LINESTATE_TUNING - Used for debug only. - 0x88 - 0x000000F8 - - - SPARE_FIX - [11:8] - read-write - - - DEV_LS_WAKE_FIX - Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer - [7:7] - read-write - - - DEV_RX_ERR_QUIESCE - Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet. - [6:6] - read-write - - - SIE_RX_CHATTER_SE0_FIX - RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as - 8 consecutive idle bits. - [5:5] - read-write - - - SIE_RX_BITSTUFF_FIX - RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to - avoid a hang during certain packet phases. - [4:4] - read-write - - - DEV_BUFF_CONTROL_DOUBLE_READ_FIX - Device - the controller FSM performs two reads of the buffer status memory address to - avoid sampling metastable data. An enabled buffer is only used if both reads match. - [3:3] - read-write - - - MULTI_HUB_FIX - Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays. - [2:2] - read-write - - - LINESTATE_DELAY - Device/Host - add an extra 1-bit debounce of linestate sampling. - [1:1] - read-write - - - RCV_DELAY - Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs. - [0:0] - read-write - - - - - INTR - Raw Interrupts - 0x8C - 0x00000000 - - - EPX_STOPPED_ON_NAK - Source: NAK_POLL.EPX_STOPPED_ON_NAK - [23:23] - read-only - - - DEV_SM_WATCHDOG_FIRED - Source: DEV_SM_WATCHDOG.FIRED - [22:22] - read-only - - - ENDPOINT_ERROR - Source: SIE_STATUS.ENDPOINT_ERROR - [21:21] - read-only - - - RX_SHORT_PACKET - Source: SIE_STATUS.RX_SHORT_PACKET - [20:20] - read-only - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-only - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x90 - 0x00000000 - - - EPX_STOPPED_ON_NAK - Source: NAK_POLL.EPX_STOPPED_ON_NAK - [23:23] - read-write - - - DEV_SM_WATCHDOG_FIRED - Source: DEV_SM_WATCHDOG.FIRED - [22:22] - read-write - - - ENDPOINT_ERROR - Source: SIE_STATUS.ENDPOINT_ERROR - [21:21] - read-write - - - RX_SHORT_PACKET - Source: SIE_STATUS.RX_SHORT_PACKET - [20:20] - read-write - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-write - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-write - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-write - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-write - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-write - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-write - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-write - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-write - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-write - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-write - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-write - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-write - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-write - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-write - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-write - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-write - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-write - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-write - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x94 - 0x00000000 - - - EPX_STOPPED_ON_NAK - Source: NAK_POLL.EPX_STOPPED_ON_NAK - [23:23] - read-write - - - DEV_SM_WATCHDOG_FIRED - Source: DEV_SM_WATCHDOG.FIRED - [22:22] - read-write - - - ENDPOINT_ERROR - Source: SIE_STATUS.ENDPOINT_ERROR - [21:21] - read-write - - - RX_SHORT_PACKET - Source: SIE_STATUS.RX_SHORT_PACKET - [20:20] - read-write - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-write - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-write - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-write - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-write - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-write - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-write - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-write - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-write - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-write - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-write - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-write - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-write - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-write - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-write - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-write - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-write - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-write - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-write - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x98 - 0x00000000 - - - EPX_STOPPED_ON_NAK - Source: NAK_POLL.EPX_STOPPED_ON_NAK - [23:23] - read-only - - - DEV_SM_WATCHDOG_FIRED - Source: DEV_SM_WATCHDOG.FIRED - [22:22] - read-only - - - ENDPOINT_ERROR - Source: SIE_STATUS.ENDPOINT_ERROR - [21:21] - read-only - - - RX_SHORT_PACKET - Source: SIE_STATUS.RX_SHORT_PACKET - [20:20] - read-only - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-only - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only - - - - - SOF_TIMESTAMP_RAW - Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events. - 0x100 - 0x00000000 - - - SOF_TIMESTAMP_RAW - [20:0] - read-only - - - - - SOF_TIMESTAMP_LAST - Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred. - 0x104 - 0x00000000 - - - SOF_TIMESTAMP_LAST - [20:0] - read-only - - - - - SM_STATE - 0x108 - 0x00000000 - - - RX_DASM - [11:8] - read-only - - - BC_STATE - [7:5] - read-only - - - STATE - [4:0] - read-only - - - - - EP_TX_ERROR - TX error count for each endpoint. Write to each field to reset the counter to 0. - 0x10C - 0x00000000 - - - EP15 - [31:30] - read-write - oneToClear - - - EP14 - [29:28] - read-write - oneToClear - - - EP13 - [27:26] - read-write - oneToClear - - - EP12 - [25:24] - read-write - oneToClear - - - EP11 - [23:22] - read-write - oneToClear - - - EP10 - [21:20] - read-write - oneToClear - - - EP9 - [19:18] - read-write - oneToClear - - - EP8 - [17:16] - read-write - oneToClear - - - EP7 - [15:14] - read-write - oneToClear - - - EP6 - [13:12] - read-write - oneToClear - - - EP5 - [11:10] - read-write - oneToClear - - - EP4 - [9:8] - read-write - oneToClear - - - EP3 - [7:6] - read-write - oneToClear - - - EP2 - [5:4] - read-write - oneToClear - - - EP1 - [3:2] - read-write - oneToClear - - - EP0 - [1:0] - read-write - oneToClear - - - - - EP_RX_ERROR - RX error count for each endpoint. Write to each field to reset the counter to 0. - 0x110 - 0x00000000 - - - EP15_SEQ - [31:31] - read-write - oneToClear - - - EP15_TRANSACTION - [30:30] - read-write - oneToClear - - - EP14_SEQ - [29:29] - read-write - oneToClear - - - EP14_TRANSACTION - [28:28] - read-write - oneToClear - - - EP13_SEQ - [27:27] - read-write - oneToClear - - - EP13_TRANSACTION - [26:26] - read-write - oneToClear - - - EP12_SEQ - [25:25] - read-write - oneToClear - - - EP12_TRANSACTION - [24:24] - read-write - oneToClear - - - EP11_SEQ - [23:23] - read-write - oneToClear - - - EP11_TRANSACTION - [22:22] - read-write - oneToClear - - - EP10_SEQ - [21:21] - read-write - oneToClear - - - EP10_TRANSACTION - [20:20] - read-write - oneToClear - - - EP9_SEQ - [19:19] - read-write - oneToClear - - - EP9_TRANSACTION - [18:18] - read-write - oneToClear - - - EP8_SEQ - [17:17] - read-write - oneToClear - - - EP8_TRANSACTION - [16:16] - read-write - oneToClear - - - EP7_SEQ - [15:15] - read-write - oneToClear - - - EP7_TRANSACTION - [14:14] - read-write - oneToClear - - - EP6_SEQ - [13:13] - read-write - oneToClear - - - EP6_TRANSACTION - [12:12] - read-write - oneToClear - - - EP5_SEQ - [11:11] - read-write - oneToClear - - - EP5_TRANSACTION - [10:10] - read-write - oneToClear - - - EP4_SEQ - [9:9] - read-write - oneToClear - - - EP4_TRANSACTION - [8:8] - read-write - oneToClear - - - EP3_SEQ - [7:7] - read-write - oneToClear - - - EP3_TRANSACTION - [6:6] - read-write - oneToClear - - - EP2_SEQ - [5:5] - read-write - oneToClear - - - EP2_TRANSACTION - [4:4] - read-write - oneToClear - - - EP1_SEQ - [3:3] - read-write - oneToClear - - - EP1_TRANSACTION - [2:2] - read-write - oneToClear - - - EP0_SEQ - [1:1] - read-write - oneToClear - - - EP0_TRANSACTION - [0:0] - read-write - oneToClear - - - - - DEV_SM_WATCHDOG - Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. - Set limit while enable is low and then set the enable. - 0x114 - 0x00000000 - - - FIRED - [20:20] - read-write - oneToClear - - - RESET - Set to 1 to forcibly reset the device state machine on watchdog expiry - [19:19] - read-write - - - ENABLE - [18:18] - read-write - - - LIMIT - [17:0] - read-write - - - - - - - TRNG - ARM TrustZone RNG register block - 0x400F0000 - - 0x0 - 0x1EC - registers - - - TRNG_IRQ - 39 - - - - RNG_IMR - Interrupt masking. - 0x100 - 0x0000000F - - - RESERVED - RESERVED - [31:4] - read-only - - - VN_ERR_INT_MASK - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. - [3:3] - read-write - - - CRNGT_ERR_INT_MASK - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. - [2:2] - read-write - - - AUTOCORR_ERR_INT_MASK - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. - [1:1] - read-write - - - EHR_VALID_INT_MASK - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. - [0:0] - read-write - - - - - RNG_ISR - RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated. - 0x104 - 0x00000000 - - - RESERVED - RESERVED - [31:4] - read-only - - - VN_ERR - 1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE. - [3:3] - read-only - - - CRNGT_ERR - 1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal. - [2:2] - read-only - - - AUTOCORR_ERR - 1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset. - [1:1] - read-only - - - EHR_VALID - 1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read. - [0:0] - read-only - - - - - RNG_ICR - Interrupt/status bit clear Register. - 0x108 - 0x00000000 - - - RESERVED - RESERVED - [31:4] - read-only - - - VN_ERR - Write 1'b1 - clear corresponding bit in RNG_ISR. - [3:3] - read-write - - - CRNGT_ERR - Write 1'b1 - clear corresponding bit in RNG_ISR. - [2:2] - read-write - - - AUTOCORR_ERR - Cannot be cleared by SW! Only RNG reset clears this bit. - [1:1] - read-write - - - EHR_VALID - Write 1'b1 - clear corresponding bit in RNG_ISR. - [0:0] - read-write - - - - - TRNG_CONFIG - Selecting the inverter-chain length. - 0x10C - 0x00000000 - - - RESERVED - RESERVED - [31:2] - read-only - - - RND_SRC_SEL - Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source). - [1:0] - read-write - - - - - TRNG_VALID - 192 bit collection indication. - 0x110 - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - EHR_VALID - 1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register. - [0:0] - read-only - - - - - EHR_DATA0 - RNG collected bits. - 0x114 - 0x00000000 - - - EHR_DATA0 - Bits [31:0] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - EHR_DATA1 - RNG collected bits. - 0x118 - 0x00000000 - - - EHR_DATA1 - Bits [63:32] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - EHR_DATA2 - RNG collected bits. - 0x11C - 0x00000000 - - - EHR_DATA2 - Bits [95:64] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - EHR_DATA3 - RNG collected bits. - 0x120 - 0x00000000 - - - EHR_DATA3 - Bits [127:96] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - EHR_DATA4 - RNG collected bits. - 0x124 - 0x00000000 - - - EHR_DATA4 - Bits [159:128] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - EHR_DATA5 - RNG collected bits. - 0x128 - 0x00000000 - - - EHR_DATA5 - Bits [191:160] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - RND_SOURCE_ENABLE - Enable signal for the random source. - 0x12C - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - RND_SRC_EN - * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled - [0:0] - read-write - - - - - SAMPLE_CNT1 - Counts clocks between sampling of random bit. - 0x130 - 0x0000FFFF - - - SAMPLE_CNTR1 - Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen - [31:0] - read-write - - - - - AUTOCORR_STATISTIC - Statistic about Autocorrelation test activations. - 0x134 - 0x00000000 - - - RESERVED - RESERVED - [31:22] - read-only - - - AUTOCORR_FAILS - Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. - [21:14] - read-write - - - AUTOCORR_TRYS - Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. - [13:0] - read-write - - - - - TRNG_DEBUG_CONTROL - Debug register. - 0x138 - 0x00000000 - - - AUTO_CORRELATE_BYPASS - When set, the autocorrelation test in the TRNG module is bypassed. - [3:3] - read-write - - - TRNG_CRNGT_BYPASS - When set, the CRNGT test in the RNG is bypassed. - [2:2] - read-write - - - VNC_BYPASS - When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test). - [1:1] - read-write - - - RESERVED - N/A - [0:0] - read-only - - - - - TRNG_SW_RESET - Generate internal SW reset within the RNG block. - 0x140 - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - TRNG_SW_RESET - Writing 1'b1 to this register causes an internal RNG reset. - [0:0] - read-write - - - - - RNG_DEBUG_EN_INPUT - Enable the RNG debug mode - 0x1B4 - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - RNG_DEBUG_EN - * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled - [0:0] - read-write - - - - - TRNG_BUSY - RNG Busy indication. - 0x1B8 - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - TRNG_BUSY - Reflects rng_busy status. - [0:0] - read-only - - - - - RST_BITS_COUNTER - Reset the counter of collected bits in the RNG. - 0x1BC - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - RST_BITS_COUNTER - Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place. - [0:0] - read-write - - - - - RNG_VERSION - Displays the version settings of the TRNG. - 0x1C0 - 0x00000000 - - - RESERVED - RESERVED - [31:8] - read-only - - - RNG_USE_5_SBOXES - * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES - [7:7] - read-only - - - RESEEDING_EXISTS - * 1'b1 - Exists. *1'b0 - Does not exist - [6:6] - read-only - - - KAT_EXISTS - * 1'b1 - Exists. *1'b0 - Does not exist - [5:5] - read-only - - - PRNG_EXISTS - * 1'b1 - Exists. *1'b0 - Does not exist - [4:4] - read-only - - - TRNG_TESTS_BYPASS_EN - * 1'b1 - Exists. *1'b0 - Does not exist - [3:3] - read-only - - - AUTOCORR_EXISTS - * 1'b1 - Exists. *1'b0 - Does not exist - [2:2] - read-only - - - CRNGT_EXISTS - * 1'b1 - Exists. *1'b0 - Does not exist - [1:1] - read-only - - - EHR_WIDTH_192 - * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR - [0:0] - read-only - - - - - RNG_BIST_CNTR_0 - Collected BIST results. - 0x1E0 - 0x00000000 - - - RESERVED - RESERVED - [31:22] - read-only - - - ROSC_CNTR_VAL - Reflects the results of RNG BIST counter. - [21:0] - read-only - - - - - RNG_BIST_CNTR_1 - Collected BIST results. - 0x1E4 - 0x00000000 - - - RESERVED - RESERVED - [31:22] - read-only - - - ROSC_CNTR_VAL - Reflects the results of RNG BIST counter. - [21:0] - read-only - - - - - RNG_BIST_CNTR_2 - Collected BIST results. - 0x1E8 - 0x00000000 - - - RESERVED - RESERVED - [31:22] - read-only - - - ROSC_CNTR_VAL - Reflects the results of RNG BIST counter. - [21:0] - read-only - - - - - - - GLITCH_DETECTOR - Glitch detector controls - 0x40158000 - - 0x0 - 0x18 - registers - - - - ARM - Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. - - Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. - - This register is Secure read/write only. - 0x0 - 0x00005BAD - - - ARM - [15:0] - read-write - - - no - Do not force the glitch detectors to be armed - 23469 - - - yes - Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) - 0 - - - - - - - DISARM - 0x4 - 0x00000000 - - - DISARM - Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. - - This register is Secure read/write only. - [15:0] - read-write - - - no - Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) - 0 - - - yes - Disarm the glitch detectors - 56495 - - - - - - - SENSITIVITY - Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. - - This register is Secure read/write only. - 0x8 - 0x00000000 - - - DEFAULT - [31:24] - read-write - - - yes - Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) - 0 - - - no - Do not use the default sensitivity configured in OTP. Instead use the value from this register. - 222 - - - - - DET3_INV - Must be the inverse of DET3, else the default value is used. - [15:14] - read-write - - - DET2_INV - Must be the inverse of DET2, else the default value is used. - [13:12] - read-write - - - DET1_INV - Must be the inverse of DET1, else the default value is used. - [11:10] - read-write - - - DET0_INV - Must be the inverse of DET0, else the default value is used. - [9:8] - read-write - - - DET3 - Set sensitivity for detector 3. Higher values are more sensitive. - [7:6] - read-write - - - DET2 - Set sensitivity for detector 2. Higher values are more sensitive. - [5:4] - read-write - - - DET1 - Set sensitivity for detector 1. Higher values are more sensitive. - [3:2] - read-write - - - DET0 - Set sensitivity for detector 0. Higher values are more sensitive. - [1:0] - read-write - - - - - LOCK - 0xC - 0x00000000 - - - LOCK - Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only. - [7:0] - read-write - - - - - TRIG_STATUS - Set when a detector output triggers. Write-1-clear. - - (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) - - This register is Secure read/write only. - 0x10 - 0x00000000 - - - DET3 - [3:3] - read-write - oneToClear - - - DET2 - [2:2] - read-write - oneToClear - - - DET1 - [1:1] - read-write - oneToClear - - - DET0 - [0:0] - read-write - oneToClear - - - - - TRIG_FORCE - Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. - - If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. - - This register is Secure read/write only. - 0x14 - 0x00000000 - - - TRIG_FORCE - [3:0] - write-only - - - - - - - OTP - SNPS OTP control IF (SBPI and RPi wrapper control) - 0x40120000 - - 0x0 - 0x174 - registers - - - OTP_IRQ - 38 - - - - SW_LOCK0 - Software lock register for page 0. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x0 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK1 - Software lock register for page 1. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x4 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK2 - Software lock register for page 2. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x8 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK3 - Software lock register for page 3. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xC - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK4 - Software lock register for page 4. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x10 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK5 - Software lock register for page 5. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x14 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK6 - Software lock register for page 6. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x18 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK7 - Software lock register for page 7. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x1C - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK8 - Software lock register for page 8. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x20 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK9 - Software lock register for page 9. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x24 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK10 - Software lock register for page 10. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x28 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK11 - Software lock register for page 11. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x2C - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK12 - Software lock register for page 12. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x30 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK13 - Software lock register for page 13. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x34 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK14 - Software lock register for page 14. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x38 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK15 - Software lock register for page 15. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x3C - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK16 - Software lock register for page 16. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x40 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK17 - Software lock register for page 17. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x44 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK18 - Software lock register for page 18. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x48 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK19 - Software lock register for page 19. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x4C - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK20 - Software lock register for page 20. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x50 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK21 - Software lock register for page 21. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x54 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK22 - Software lock register for page 22. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x58 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK23 - Software lock register for page 23. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x5C - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK24 - Software lock register for page 24. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x60 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK25 - Software lock register for page 25. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x64 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK26 - Software lock register for page 26. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x68 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK27 - Software lock register for page 27. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x6C - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK28 - Software lock register for page 28. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x70 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK29 - Software lock register for page 29. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x74 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK30 - Software lock register for page 30. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x78 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK31 - Software lock register for page 31. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x7C - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK32 - Software lock register for page 32. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x80 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK33 - Software lock register for page 33. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x84 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK34 - Software lock register for page 34. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x88 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK35 - Software lock register for page 35. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x8C - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK36 - Software lock register for page 36. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x90 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK37 - Software lock register for page 37. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x94 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK38 - Software lock register for page 38. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x98 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK39 - Software lock register for page 39. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x9C - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK40 - Software lock register for page 40. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xA0 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK41 - Software lock register for page 41. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xA4 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK42 - Software lock register for page 42. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xA8 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK43 - Software lock register for page 43. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xAC - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK44 - Software lock register for page 44. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xB0 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK45 - Software lock register for page 45. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xB4 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK46 - Software lock register for page 46. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xB8 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK47 - Software lock register for page 47. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xBC - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK48 - Software lock register for page 48. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xC0 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK49 - Software lock register for page 49. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xC4 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK50 - Software lock register for page 50. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xC8 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK51 - Software lock register for page 51. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xCC - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK52 - Software lock register for page 52. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xD0 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK53 - Software lock register for page 53. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xD4 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK54 - Software lock register for page 54. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xD8 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK55 - Software lock register for page 55. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xDC - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK56 - Software lock register for page 56. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xE0 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK57 - Software lock register for page 57. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xE4 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK58 - Software lock register for page 58. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xE8 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK59 - Software lock register for page 59. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xEC - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK60 - Software lock register for page 60. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xF0 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK61 - Software lock register for page 61. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xF4 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK62 - Software lock register for page 62. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xF8 - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK63 - Software lock register for page 63. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0xFC - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SBPI_INSTR - Dispatch instructions to the SBPI interface, used for programming the OTP fuses. - 0x100 - 0x00000000 - - - EXEC - Execute instruction - [30:30] - write-only - - - IS_WR - Payload type is write - [29:29] - read-write - - - HAS_PAYLOAD - Instruction has payload (data to be written or to be read) - [28:28] - read-write - - - PAYLOAD_SIZE_M1 - Instruction payload size in bytes minus 1 - [27:24] - read-write - - - TARGET - Instruction target, it can be PMC (0x3a) or DAP (0x02) - [23:16] - read-write - - - CMD - [15:8] - read-write - - - SHORT_WDATA - wdata to be used only when payload_size_m1=0 - [7:0] - read-write - - - - - SBPI_WDATA_0 - SBPI write payload bytes 3..0 - 0x104 - 0x00000000 - - - SBPI_WDATA_0 - [31:0] - read-write - - - - - SBPI_WDATA_1 - SBPI write payload bytes 7..4 - 0x108 - 0x00000000 - - - SBPI_WDATA_1 - [31:0] - read-write - - - - - SBPI_WDATA_2 - SBPI write payload bytes 11..8 - 0x10C - 0x00000000 - - - SBPI_WDATA_2 - [31:0] - read-write - - - - - SBPI_WDATA_3 - SBPI write payload bytes 15..12 - 0x110 - 0x00000000 - - - SBPI_WDATA_3 - [31:0] - read-write - - - - - SBPI_RDATA_0 - Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0. - 0x114 - 0x00000000 - - - SBPI_RDATA_0 - [31:0] - read-only - modify - - - - - SBPI_RDATA_1 - Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0. - 0x118 - 0x00000000 - - - SBPI_RDATA_1 - [31:0] - read-only - modify - - - - - SBPI_RDATA_2 - Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0. - 0x11C - 0x00000000 - - - SBPI_RDATA_2 - [31:0] - read-only - modify - - - - - SBPI_RDATA_3 - Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0. - 0x120 - 0x00000000 - - - SBPI_RDATA_3 - [31:0] - read-only - modify - - - - - SBPI_STATUS - 0x124 - 0x00000000 - - - MISO - SBPI MISO (master in - slave out): response from SBPI - [23:16] - read-only - - - FLAG - SBPI flag - [12:12] - read-only - - - INSTR_MISS - Last instruction missed (dropped), as the previous has not finished running - [8:8] - read-write - oneToClear - - - INSTR_DONE - Last instruction done - [4:4] - read-write - oneToClear - - - RDATA_VLD - Read command has returned data - [0:0] - read-write - oneToClear - - - - - USR - Controls for APB data read interface (USER interface) - 0x128 - 0x00000001 - - - PD - Power-down; 1 disables current reference. Must be 0 to read data from the OTP. - [4:4] - read-write - - - DCTRL - 1 enables USER interface; 0 disables USER interface (enables SBPI). - - This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted. - [0:0] - read-write - - - - - DBG - Debug for OTP power-on state machine - 0x12C - 0x00000000 - - - CUSTOMER_RMA_FLAG - The chip is in RMA mode - [12:12] - read-only - - - PSM_STATE - Monitor the PSM FSM's state - [7:4] - read-only - - - ROSC_UP - Ring oscillator is up and running - [3:3] - read-only - - - ROSC_UP_SEEN - Ring oscillator was seen up and running - [2:2] - read-write - oneToClear - - - BOOT_DONE - PSM boot done status flag - [1:1] - read-only - - - PSM_DONE - PSM done status flag - [0:0] - read-only - - - - - BIST - During BIST, count address locations that have at least one leaky bit - 0x134 - 0x0FFF0000 - - - CNT_FAIL - Flag if the count of address locations with at least one leaky bit exceeds cnt_max - [30:30] - read-only - - - CNT_CLR - Clear counter before use - [29:29] - write-only - - - CNT_ENA - Enable the counter before the BIST function is initiated - [28:28] - read-write - - - CNT_MAX - The cnt_fail flag will be set if the number of leaky locations exceeds this number - [27:16] - read-write - - - CNT - Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option. - [12:0] - read-only - - - - - CRT_KEY_W0 - Word 0 (bits 31..0) of the key. Write only, read returns 0x0 - 0x138 - 0x00000000 - - - CRT_KEY_W0 - [31:0] - write-only - - - - - CRT_KEY_W1 - Word 1 (bits 63..32) of the key. Write only, read returns 0x0 - 0x13C - 0x00000000 - - - CRT_KEY_W1 - [31:0] - write-only - - - - - CRT_KEY_W2 - Word 2 (bits 95..64) of the key. Write only, read returns 0x0 - 0x140 - 0x00000000 - - - CRT_KEY_W2 - [31:0] - write-only - - - - - CRT_KEY_W3 - Word 3 (bits 127..96) of the key. Write only, read returns 0x0 - 0x144 - 0x00000000 - - - CRT_KEY_W3 - [31:0] - write-only - - - - - CRITICAL - Quickly check values of critical flags read during boot up - 0x148 - 0x00000000 - - - RISCV_DISABLE - [17:17] - read-only - - - ARM_DISABLE - [16:16] - read-only - - - GLITCH_DETECTOR_SENS - [6:5] - read-only - - - GLITCH_DETECTOR_ENABLE - [4:4] - read-only - - - DEFAULT_ARCHSEL - [3:3] - read-only - - - DEBUG_DISABLE - [2:2] - read-only - - - SECURE_DEBUG_DISABLE - [1:1] - read-only - - - SECURE_BOOT_ENABLE - [0:0] - read-only - - - - - KEY_VALID - Which keys were valid (enrolled) at boot time - 0x14C - 0x00000000 - - - KEY_VALID - [7:0] - read-only - - - - - DEBUGEN - Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. - - Specifically: - - - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - - - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - - - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - - - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - - - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags. - 0x150 - 0x00000000 - - - MISC - Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. - - These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. - [8:8] - read-write - - - PROC1_SECURE - Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). - - Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. - [3:3] - read-write - - - PROC1 - Enable core 1's Mem-AP if it is currently disabled. - - The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. - [2:2] - read-write - - - PROC0_SECURE - Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). - - Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. - - Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). - [1:1] - read-write - - - PROC0 - Enable core 0's Mem-AP if it is currently disabled. - - The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. - - Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). - [0:0] - read-write - - - - - DEBUGEN_LOCK - Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset. - 0x154 - 0x00000000 - - - MISC - Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set. - [8:8] - read-write - - - PROC1_SECURE - Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set. - [3:3] - read-write - - - PROC1 - Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set. - [2:2] - read-write - - - PROC0_SECURE - Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set. - [1:1] - read-write - - - PROC0 - Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set. - [0:0] - read-write - - - - - ARCHSEL - Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. - - This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). - - Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. - - Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module. - 0x158 - 0x00000000 - - - CORE1 - Select architecture for core 1. - [1:1] - read-write - - - arm - Switch core 1 to Arm (Cortex-M33) - 0 - - - riscv - Switch core 1 to RISC-V (Hazard3) - 1 - - - - - CORE0 - Select architecture for core 0. - [0:0] - read-write - - - arm - Switch core 0 to Arm (Cortex-M33) - 0 - - - riscv - Switch core 0 to RISC-V (Hazard3) - 1 - - - - - - - ARCHSEL_STATUS - Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update. - 0x15C - 0x00000000 - - - CORE1 - Current architecture for core 0. Updated on processor warm reset. - [1:1] - read-only - - - arm - Core 1 is currently Arm (Cortex-M33) - 0 - - - riscv - Core 1 is currently RISC-V (Hazard3) - 1 - - - - - CORE0 - Current architecture for core 0. Updated on processor warm reset. - [0:0] - read-only - - - arm - Core 0 is currently Arm (Cortex-M33) - 0 - - - riscv - Core 0 is currently RISC-V (Hazard3) - 1 - - - - - - - BOOTDIS - Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. - - If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. - - This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. - - Should be used in conjunction with the power manager BOOTDIS register. - 0x160 - 0x00000000 - - - NEXT - This flag always ORs writes into its current contents. It can be set but not cleared by software. - - The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. - - This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset. - [1:1] - read-write - - - NOW - When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. - - The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. - [0:0] - read-write - oneToClear - - - - - INTR - Raw Interrupts - 0x164 - 0x00000000 - - - APB_RD_NSEC_FAIL - [4:4] - read-write - oneToClear - - - APB_RD_SEC_FAIL - [3:3] - read-write - oneToClear - - - APB_DCTRL_FAIL - [2:2] - read-write - oneToClear - - - SBPI_WR_FAIL - [1:1] - read-write - oneToClear - - - SBPI_FLAG_N - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x168 - 0x00000000 - - - APB_RD_NSEC_FAIL - [4:4] - read-write - - - APB_RD_SEC_FAIL - [3:3] - read-write - - - APB_DCTRL_FAIL - [2:2] - read-write - - - SBPI_WR_FAIL - [1:1] - read-write - - - SBPI_FLAG_N - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x16C - 0x00000000 - - - APB_RD_NSEC_FAIL - [4:4] - read-write - - - APB_RD_SEC_FAIL - [3:3] - read-write - - - APB_DCTRL_FAIL - [2:2] - read-write - - - SBPI_WR_FAIL - [1:1] - read-write - - - SBPI_FLAG_N - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x170 - 0x00000000 - - - APB_RD_NSEC_FAIL - [4:4] - read-only - - - APB_RD_SEC_FAIL - [3:3] - read-only - - - APB_DCTRL_FAIL - [2:2] - read-only - - - SBPI_WR_FAIL - [1:1] - read-only - - - SBPI_FLAG_N - [0:0] - read-only - - - - - - - OTP_DATA - Predefined OTP data layout for RP2350 - 0x40130000 - - 0x0 - 0x1EF0 - registers - - - - CHIPID0 - Bits 15:0 of public device ID. (ECC) - - The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. - - The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. - 0x0 - 0x10 - 0x00000000 - - - CHIPID0 - [15:0] - read-only - - - - - CHIPID1 - Bits 31:16 of public device ID (ECC) - 0x2 - 0x10 - 0x00000000 - - - CHIPID1 - [15:0] - read-only - - - - - CHIPID2 - Bits 47:32 of public device ID (ECC) - 0x4 - 0x10 - 0x00000000 - - - CHIPID2 - [15:0] - read-only - - - - - CHIPID3 - Bits 63:48 of public device ID (ECC) - 0x6 - 0x10 - 0x00000000 - - - CHIPID3 - [15:0] - read-only - - - - - RANDID0 - Bits 15:0 of private per-device random number (ECC) - - The RANDID0..7 rows form a 128-bit random number generated during device test. - - This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. - 0x8 - 0x10 - 0x00000000 - - - RANDID0 - [15:0] - read-only - - - - - RANDID1 - Bits 31:16 of private per-device random number (ECC) - 0xA - 0x10 - 0x00000000 - - - RANDID1 - [15:0] - read-only - - - - - RANDID2 - Bits 47:32 of private per-device random number (ECC) - 0xC - 0x10 - 0x00000000 - - - RANDID2 - [15:0] - read-only - - - - - RANDID3 - Bits 63:48 of private per-device random number (ECC) - 0xE - 0x10 - 0x00000000 - - - RANDID3 - [15:0] - read-only - - - - - RANDID4 - Bits 79:64 of private per-device random number (ECC) - 0x10 - 0x10 - 0x00000000 - - - RANDID4 - [15:0] - read-only - - - - - RANDID5 - Bits 95:80 of private per-device random number (ECC) - 0x12 - 0x10 - 0x00000000 - - - RANDID5 - [15:0] - read-only - - - - - RANDID6 - Bits 111:96 of private per-device random number (ECC) - 0x14 - 0x10 - 0x00000000 - - - RANDID6 - [15:0] - read-only - - - - - RANDID7 - Bits 127:112 of private per-device random number (ECC) - 0x16 - 0x10 - 0x00000000 - - - RANDID7 - [15:0] - read-only - - - - - ROSC_CALIB - Ring oscillator frequency in kHz, measured during manufacturing (ECC) - - This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. - 0x20 - 0x10 - 0x00000000 - - - ROSC_CALIB - [15:0] - read-only - - - - - LPOSC_CALIB - Low-power oscillator frequency in Hz, measured during manufacturing (ECC) - - This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. - 0x22 - 0x10 - 0x00000000 - - - LPOSC_CALIB - [15:0] - read-only - - - - - NUM_GPIOS - The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) - 0x30 - 0x10 - 0x00000000 - - - NUM_GPIOS - [7:0] - read-only - - - - - INFO_CRC0 - Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) - 0x6C - 0x10 - 0x00000000 - - - INFO_CRC0 - [15:0] - read-only - - - - - INFO_CRC1 - Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) - 0x6E - 0x10 - 0x00000000 - - - INFO_CRC1 - [15:0] - read-only - - - - - FLASH_DEVINFO - Stores information about external flash device(s). (ECC) - - Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. - 0xA8 - 0x10 - 0x00000000 - - - CS1_SIZE - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). - - A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. - [15:12] - read-only - - - NONE - 0 - - - 8K - 1 - - - 16K - 2 - - - 32K - 3 - - - 64k - 4 - - - 128K - 5 - - - 256K - 6 - - - 512K - 7 - - - 1M - 8 - - - 2M - 9 - - - 4M - 10 - - - 8M - 11 - - - 16M - 12 - - - - - CS0_SIZE - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). - - A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. - [11:8] - read-only - - - NONE - 0 - - - 8K - 1 - - - 16K - 2 - - - 32K - 3 - - - 64k - 4 - - - 128K - 5 - - - 256K - 6 - - - 512K - 7 - - - 1M - 8 - - - 2M - 9 - - - 4M - 10 - - - 8M - 11 - - - 16M - 12 - - - - - D8H_ERASE_SUPPORTED - If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. - - If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. - [7:7] - read-only - - - CS1_GPIO - Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. - - On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. - - Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). - [5:0] - read-only - - - - - FLASH_PARTITION_SLOT_SIZE - Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) - 0xAA - 0x10 - 0x00000000 - - - FLASH_PARTITION_SLOT_SIZE - [15:0] - read-only - - - - - BOOTSEL_LED_CFG - Pin configuration for LED status, used by USB bootloader. (ECC) - Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. - 0xAC - 0x10 - 0x00000000 - - - ACTIVELOW - LED is active-low. (Default: active-high.) - [8:8] - read-only - - - PIN - GPIO index to use for bootloader activity LED. - [5:0] - read-only - - - - - BOOTSEL_PLL_CFG - Optional PLL configuration for BOOTSEL mode. (ECC) - - This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. - - If no configuration is given, the crystal is assumed to be 12 MHz. - - The PLL frequency can be calculated as: - - PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) - - Conversely the crystal frequency can be calculated as: - - XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV - - (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) - - Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. - 0xAE - 0x10 - 0x00000000 - - - REFDIV - PLL reference divisor, minus one. - - Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) - [15:15] - read-only - - - POSTDIV2 - PLL post-divide 2 divisor, in the range 1..7 inclusive. - [14:12] - read-only - - - POSTDIV1 - PLL post-divide 1 divisor, in the range 1..7 inclusive. - [11:9] - read-only - - - FBDIV - PLL feedback divisor, in the range 16..320 inclusive. - [8:0] - read-only - - - - - BOOTSEL_XOSC_CFG - Non-default crystal oscillator configuration for the USB bootloader. (ECC) - - These values may also be used by user code configuring the crystal oscillator. - - Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. - 0xB0 - 0x10 - 0x00000000 - - - RANGE - Value of the XOSC_CTRL_FREQ_RANGE register. - [15:14] - read-only - - - 1_15MHZ - 0 - - - 10_30MHZ - 1 - - - 25_60MHZ - 2 - - - 40_100MHZ - 3 - - - - - STARTUP - Value of the XOSC_STARTUP register - [13:0] - read-only - - - - - USB_WHITE_LABEL_ADDR - Row index of the USB_WHITE_LABEL structure within OTP (ECC) - - The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). - - The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. - - The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. - - In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. - - Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. - - Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. - - The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): - 0xB8 - 0x10 - 0x00000000 - - - USB_WHITE_LABEL_ADDR - [15:0] - read-only - - - INDEX_USB_DEVICE_VID_VALUE - 0 - - - INDEX_USB_DEVICE_PID_VALUE - 1 - - - INDEX_USB_DEVICE_BCD_DEVICE_VALUE - 2 - - - INDEX_USB_DEVICE_LANG_ID_VALUE - 3 - - - INDEX_USB_DEVICE_MANUFACTURER_STRDEF - 4 - - - INDEX_USB_DEVICE_PRODUCT_STRDEF - 5 - - - INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF - 6 - - - INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES - 7 - - - INDEX_VOLUME_LABEL_STRDEF - 8 - - - INDEX_SCSI_INQUIRY_VENDOR_STRDEF - 9 - - - INDEX_SCSI_INQUIRY_PRODUCT_STRDEF - 10 - - - INDEX_SCSI_INQUIRY_VERSION_STRDEF - 11 - - - INDEX_INDEX_HTM_REDIRECT_URL_STRDEF - 12 - - - INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF - 13 - - - INDEX_INFO_UF2_TXT_MODEL_STRDEF - 14 - - - INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF - 15 - - - - - - - OTPBOOT_SRC - OTP start row for the OTP boot image. (ECC) - - If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. - - This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. - 0xBC - 0x10 - 0x00000000 - - - OTPBOOT_SRC - [15:0] - read-only - - - - - OTPBOOT_LEN - Length in rows of the OTP boot image. (ECC) - - OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). - 0xBE - 0x10 - 0x00000000 - - - OTPBOOT_LEN - [15:0] - read-only - - - - - OTPBOOT_DST0 - Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) - - This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. - 0xC0 - 0x10 - 0x00000000 - - - OTPBOOT_DST0 - [15:0] - read-only - - - - - OTPBOOT_DST1 - Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) - - This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. - 0xC2 - 0x10 - 0x00000000 - - - OTPBOOT_DST1 - [15:0] - read-only - - - - - BOOTKEY0_0 - Bits 15:0 of SHA-256 hash of boot key 0 (ECC) - 0x100 - 0x10 - 0x00000000 - - - BOOTKEY0_0 - [15:0] - read-only - - - - - BOOTKEY0_1 - Bits 31:16 of SHA-256 hash of boot key 0 (ECC) - 0x102 - 0x10 - 0x00000000 - - - BOOTKEY0_1 - [15:0] - read-only - - - - - BOOTKEY0_2 - Bits 47:32 of SHA-256 hash of boot key 0 (ECC) - 0x104 - 0x10 - 0x00000000 - - - BOOTKEY0_2 - [15:0] - read-only - - - - - BOOTKEY0_3 - Bits 63:48 of SHA-256 hash of boot key 0 (ECC) - 0x106 - 0x10 - 0x00000000 - - - BOOTKEY0_3 - [15:0] - read-only - - - - - BOOTKEY0_4 - Bits 79:64 of SHA-256 hash of boot key 0 (ECC) - 0x108 - 0x10 - 0x00000000 - - - BOOTKEY0_4 - [15:0] - read-only - - - - - BOOTKEY0_5 - Bits 95:80 of SHA-256 hash of boot key 0 (ECC) - 0x10A - 0x10 - 0x00000000 - - - BOOTKEY0_5 - [15:0] - read-only - - - - - BOOTKEY0_6 - Bits 111:96 of SHA-256 hash of boot key 0 (ECC) - 0x10C - 0x10 - 0x00000000 - - - BOOTKEY0_6 - [15:0] - read-only - - - - - BOOTKEY0_7 - Bits 127:112 of SHA-256 hash of boot key 0 (ECC) - 0x10E - 0x10 - 0x00000000 - - - BOOTKEY0_7 - [15:0] - read-only - - - - - BOOTKEY0_8 - Bits 143:128 of SHA-256 hash of boot key 0 (ECC) - 0x110 - 0x10 - 0x00000000 - - - BOOTKEY0_8 - [15:0] - read-only - - - - - BOOTKEY0_9 - Bits 159:144 of SHA-256 hash of boot key 0 (ECC) - 0x112 - 0x10 - 0x00000000 - - - BOOTKEY0_9 - [15:0] - read-only - - - - - BOOTKEY0_10 - Bits 175:160 of SHA-256 hash of boot key 0 (ECC) - 0x114 - 0x10 - 0x00000000 - - - BOOTKEY0_10 - [15:0] - read-only - - - - - BOOTKEY0_11 - Bits 191:176 of SHA-256 hash of boot key 0 (ECC) - 0x116 - 0x10 - 0x00000000 - - - BOOTKEY0_11 - [15:0] - read-only - - - - - BOOTKEY0_12 - Bits 207:192 of SHA-256 hash of boot key 0 (ECC) - 0x118 - 0x10 - 0x00000000 - - - BOOTKEY0_12 - [15:0] - read-only - - - - - BOOTKEY0_13 - Bits 223:208 of SHA-256 hash of boot key 0 (ECC) - 0x11A - 0x10 - 0x00000000 - - - BOOTKEY0_13 - [15:0] - read-only - - - - - BOOTKEY0_14 - Bits 239:224 of SHA-256 hash of boot key 0 (ECC) - 0x11C - 0x10 - 0x00000000 - - - BOOTKEY0_14 - [15:0] - read-only - - - - - BOOTKEY0_15 - Bits 255:240 of SHA-256 hash of boot key 0 (ECC) - 0x11E - 0x10 - 0x00000000 - - - BOOTKEY0_15 - [15:0] - read-only - - - - - BOOTKEY1_0 - Bits 15:0 of SHA-256 hash of boot key 1 (ECC) - 0x120 - 0x10 - 0x00000000 - - - BOOTKEY1_0 - [15:0] - read-only - - - - - BOOTKEY1_1 - Bits 31:16 of SHA-256 hash of boot key 1 (ECC) - 0x122 - 0x10 - 0x00000000 - - - BOOTKEY1_1 - [15:0] - read-only - - - - - BOOTKEY1_2 - Bits 47:32 of SHA-256 hash of boot key 1 (ECC) - 0x124 - 0x10 - 0x00000000 - - - BOOTKEY1_2 - [15:0] - read-only - - - - - BOOTKEY1_3 - Bits 63:48 of SHA-256 hash of boot key 1 (ECC) - 0x126 - 0x10 - 0x00000000 - - - BOOTKEY1_3 - [15:0] - read-only - - - - - BOOTKEY1_4 - Bits 79:64 of SHA-256 hash of boot key 1 (ECC) - 0x128 - 0x10 - 0x00000000 - - - BOOTKEY1_4 - [15:0] - read-only - - - - - BOOTKEY1_5 - Bits 95:80 of SHA-256 hash of boot key 1 (ECC) - 0x12A - 0x10 - 0x00000000 - - - BOOTKEY1_5 - [15:0] - read-only - - - - - BOOTKEY1_6 - Bits 111:96 of SHA-256 hash of boot key 1 (ECC) - 0x12C - 0x10 - 0x00000000 - - - BOOTKEY1_6 - [15:0] - read-only - - - - - BOOTKEY1_7 - Bits 127:112 of SHA-256 hash of boot key 1 (ECC) - 0x12E - 0x10 - 0x00000000 - - - BOOTKEY1_7 - [15:0] - read-only - - - - - BOOTKEY1_8 - Bits 143:128 of SHA-256 hash of boot key 1 (ECC) - 0x130 - 0x10 - 0x00000000 - - - BOOTKEY1_8 - [15:0] - read-only - - - - - BOOTKEY1_9 - Bits 159:144 of SHA-256 hash of boot key 1 (ECC) - 0x132 - 0x10 - 0x00000000 - - - BOOTKEY1_9 - [15:0] - read-only - - - - - BOOTKEY1_10 - Bits 175:160 of SHA-256 hash of boot key 1 (ECC) - 0x134 - 0x10 - 0x00000000 - - - BOOTKEY1_10 - [15:0] - read-only - - - - - BOOTKEY1_11 - Bits 191:176 of SHA-256 hash of boot key 1 (ECC) - 0x136 - 0x10 - 0x00000000 - - - BOOTKEY1_11 - [15:0] - read-only - - - - - BOOTKEY1_12 - Bits 207:192 of SHA-256 hash of boot key 1 (ECC) - 0x138 - 0x10 - 0x00000000 - - - BOOTKEY1_12 - [15:0] - read-only - - - - - BOOTKEY1_13 - Bits 223:208 of SHA-256 hash of boot key 1 (ECC) - 0x13A - 0x10 - 0x00000000 - - - BOOTKEY1_13 - [15:0] - read-only - - - - - BOOTKEY1_14 - Bits 239:224 of SHA-256 hash of boot key 1 (ECC) - 0x13C - 0x10 - 0x00000000 - - - BOOTKEY1_14 - [15:0] - read-only - - - - - BOOTKEY1_15 - Bits 255:240 of SHA-256 hash of boot key 1 (ECC) - 0x13E - 0x10 - 0x00000000 - - - BOOTKEY1_15 - [15:0] - read-only - - - - - BOOTKEY2_0 - Bits 15:0 of SHA-256 hash of boot key 2 (ECC) - 0x140 - 0x10 - 0x00000000 - - - BOOTKEY2_0 - [15:0] - read-only - - - - - BOOTKEY2_1 - Bits 31:16 of SHA-256 hash of boot key 2 (ECC) - 0x142 - 0x10 - 0x00000000 - - - BOOTKEY2_1 - [15:0] - read-only - - - - - BOOTKEY2_2 - Bits 47:32 of SHA-256 hash of boot key 2 (ECC) - 0x144 - 0x10 - 0x00000000 - - - BOOTKEY2_2 - [15:0] - read-only - - - - - BOOTKEY2_3 - Bits 63:48 of SHA-256 hash of boot key 2 (ECC) - 0x146 - 0x10 - 0x00000000 - - - BOOTKEY2_3 - [15:0] - read-only - - - - - BOOTKEY2_4 - Bits 79:64 of SHA-256 hash of boot key 2 (ECC) - 0x148 - 0x10 - 0x00000000 - - - BOOTKEY2_4 - [15:0] - read-only - - - - - BOOTKEY2_5 - Bits 95:80 of SHA-256 hash of boot key 2 (ECC) - 0x14A - 0x10 - 0x00000000 - - - BOOTKEY2_5 - [15:0] - read-only - - - - - BOOTKEY2_6 - Bits 111:96 of SHA-256 hash of boot key 2 (ECC) - 0x14C - 0x10 - 0x00000000 - - - BOOTKEY2_6 - [15:0] - read-only - - - - - BOOTKEY2_7 - Bits 127:112 of SHA-256 hash of boot key 2 (ECC) - 0x14E - 0x10 - 0x00000000 - - - BOOTKEY2_7 - [15:0] - read-only - - - - - BOOTKEY2_8 - Bits 143:128 of SHA-256 hash of boot key 2 (ECC) - 0x150 - 0x10 - 0x00000000 - - - BOOTKEY2_8 - [15:0] - read-only - - - - - BOOTKEY2_9 - Bits 159:144 of SHA-256 hash of boot key 2 (ECC) - 0x152 - 0x10 - 0x00000000 - - - BOOTKEY2_9 - [15:0] - read-only - - - - - BOOTKEY2_10 - Bits 175:160 of SHA-256 hash of boot key 2 (ECC) - 0x154 - 0x10 - 0x00000000 - - - BOOTKEY2_10 - [15:0] - read-only - - - - - BOOTKEY2_11 - Bits 191:176 of SHA-256 hash of boot key 2 (ECC) - 0x156 - 0x10 - 0x00000000 - - - BOOTKEY2_11 - [15:0] - read-only - - - - - BOOTKEY2_12 - Bits 207:192 of SHA-256 hash of boot key 2 (ECC) - 0x158 - 0x10 - 0x00000000 - - - BOOTKEY2_12 - [15:0] - read-only - - - - - BOOTKEY2_13 - Bits 223:208 of SHA-256 hash of boot key 2 (ECC) - 0x15A - 0x10 - 0x00000000 - - - BOOTKEY2_13 - [15:0] - read-only - - - - - BOOTKEY2_14 - Bits 239:224 of SHA-256 hash of boot key 2 (ECC) - 0x15C - 0x10 - 0x00000000 - - - BOOTKEY2_14 - [15:0] - read-only - - - - - BOOTKEY2_15 - Bits 255:240 of SHA-256 hash of boot key 2 (ECC) - 0x15E - 0x10 - 0x00000000 - - - BOOTKEY2_15 - [15:0] - read-only - - - - - BOOTKEY3_0 - Bits 15:0 of SHA-256 hash of boot key 3 (ECC) - 0x160 - 0x10 - 0x00000000 - - - BOOTKEY3_0 - [15:0] - read-only - - - - - BOOTKEY3_1 - Bits 31:16 of SHA-256 hash of boot key 3 (ECC) - 0x162 - 0x10 - 0x00000000 - - - BOOTKEY3_1 - [15:0] - read-only - - - - - BOOTKEY3_2 - Bits 47:32 of SHA-256 hash of boot key 3 (ECC) - 0x164 - 0x10 - 0x00000000 - - - BOOTKEY3_2 - [15:0] - read-only - - - - - BOOTKEY3_3 - Bits 63:48 of SHA-256 hash of boot key 3 (ECC) - 0x166 - 0x10 - 0x00000000 - - - BOOTKEY3_3 - [15:0] - read-only - - - - - BOOTKEY3_4 - Bits 79:64 of SHA-256 hash of boot key 3 (ECC) - 0x168 - 0x10 - 0x00000000 - - - BOOTKEY3_4 - [15:0] - read-only - - - - - BOOTKEY3_5 - Bits 95:80 of SHA-256 hash of boot key 3 (ECC) - 0x16A - 0x10 - 0x00000000 - - - BOOTKEY3_5 - [15:0] - read-only - - - - - BOOTKEY3_6 - Bits 111:96 of SHA-256 hash of boot key 3 (ECC) - 0x16C - 0x10 - 0x00000000 - - - BOOTKEY3_6 - [15:0] - read-only - - - - - BOOTKEY3_7 - Bits 127:112 of SHA-256 hash of boot key 3 (ECC) - 0x16E - 0x10 - 0x00000000 - - - BOOTKEY3_7 - [15:0] - read-only - - - - - BOOTKEY3_8 - Bits 143:128 of SHA-256 hash of boot key 3 (ECC) - 0x170 - 0x10 - 0x00000000 - - - BOOTKEY3_8 - [15:0] - read-only - - - - - BOOTKEY3_9 - Bits 159:144 of SHA-256 hash of boot key 3 (ECC) - 0x172 - 0x10 - 0x00000000 - - - BOOTKEY3_9 - [15:0] - read-only - - - - - BOOTKEY3_10 - Bits 175:160 of SHA-256 hash of boot key 3 (ECC) - 0x174 - 0x10 - 0x00000000 - - - BOOTKEY3_10 - [15:0] - read-only - - - - - BOOTKEY3_11 - Bits 191:176 of SHA-256 hash of boot key 3 (ECC) - 0x176 - 0x10 - 0x00000000 - - - BOOTKEY3_11 - [15:0] - read-only - - - - - BOOTKEY3_12 - Bits 207:192 of SHA-256 hash of boot key 3 (ECC) - 0x178 - 0x10 - 0x00000000 - - - BOOTKEY3_12 - [15:0] - read-only - - - - - BOOTKEY3_13 - Bits 223:208 of SHA-256 hash of boot key 3 (ECC) - 0x17A - 0x10 - 0x00000000 - - - BOOTKEY3_13 - [15:0] - read-only - - - - - BOOTKEY3_14 - Bits 239:224 of SHA-256 hash of boot key 3 (ECC) - 0x17C - 0x10 - 0x00000000 - - - BOOTKEY3_14 - [15:0] - read-only - - - - - BOOTKEY3_15 - Bits 255:240 of SHA-256 hash of boot key 3 (ECC) - 0x17E - 0x10 - 0x00000000 - - - BOOTKEY3_15 - [15:0] - read-only - - - - - KEY1_0 - Bits 15:0 of OTP access key 1 (ECC) - 0x1E90 - 0x10 - 0x00000000 - - - KEY1_0 - [15:0] - read-only - - - - - KEY1_1 - Bits 31:16 of OTP access key 1 (ECC) - 0x1E92 - 0x10 - 0x00000000 - - - KEY1_1 - [15:0] - read-only - - - - - KEY1_2 - Bits 47:32 of OTP access key 1 (ECC) - 0x1E94 - 0x10 - 0x00000000 - - - KEY1_2 - [15:0] - read-only - - - - - KEY1_3 - Bits 63:48 of OTP access key 1 (ECC) - 0x1E96 - 0x10 - 0x00000000 - - - KEY1_3 - [15:0] - read-only - - - - - KEY1_4 - Bits 79:64 of OTP access key 1 (ECC) - 0x1E98 - 0x10 - 0x00000000 - - - KEY1_4 - [15:0] - read-only - - - - - KEY1_5 - Bits 95:80 of OTP access key 1 (ECC) - 0x1E9A - 0x10 - 0x00000000 - - - KEY1_5 - [15:0] - read-only - - - - - KEY1_6 - Bits 111:96 of OTP access key 1 (ECC) - 0x1E9C - 0x10 - 0x00000000 - - - KEY1_6 - [15:0] - read-only - - - - - KEY1_7 - Bits 127:112 of OTP access key 1 (ECC) - 0x1E9E - 0x10 - 0x00000000 - - - KEY1_7 - [15:0] - read-only - - - - - KEY2_0 - Bits 15:0 of OTP access key 2 (ECC) - 0x1EA0 - 0x10 - 0x00000000 - - - KEY2_0 - [15:0] - read-only - - - - - KEY2_1 - Bits 31:16 of OTP access key 2 (ECC) - 0x1EA2 - 0x10 - 0x00000000 - - - KEY2_1 - [15:0] - read-only - - - - - KEY2_2 - Bits 47:32 of OTP access key 2 (ECC) - 0x1EA4 - 0x10 - 0x00000000 - - - KEY2_2 - [15:0] - read-only - - - - - KEY2_3 - Bits 63:48 of OTP access key 2 (ECC) - 0x1EA6 - 0x10 - 0x00000000 - - - KEY2_3 - [15:0] - read-only - - - - - KEY2_4 - Bits 79:64 of OTP access key 2 (ECC) - 0x1EA8 - 0x10 - 0x00000000 - - - KEY2_4 - [15:0] - read-only - - - - - KEY2_5 - Bits 95:80 of OTP access key 2 (ECC) - 0x1EAA - 0x10 - 0x00000000 - - - KEY2_5 - [15:0] - read-only - - - - - KEY2_6 - Bits 111:96 of OTP access key 2 (ECC) - 0x1EAC - 0x10 - 0x00000000 - - - KEY2_6 - [15:0] - read-only - - - - - KEY2_7 - Bits 127:112 of OTP access key 2 (ECC) - 0x1EAE - 0x10 - 0x00000000 - - - KEY2_7 - [15:0] - read-only - - - - - KEY3_0 - Bits 15:0 of OTP access key 3 (ECC) - 0x1EB0 - 0x10 - 0x00000000 - - - KEY3_0 - [15:0] - read-only - - - - - KEY3_1 - Bits 31:16 of OTP access key 3 (ECC) - 0x1EB2 - 0x10 - 0x00000000 - - - KEY3_1 - [15:0] - read-only - - - - - KEY3_2 - Bits 47:32 of OTP access key 3 (ECC) - 0x1EB4 - 0x10 - 0x00000000 - - - KEY3_2 - [15:0] - read-only - - - - - KEY3_3 - Bits 63:48 of OTP access key 3 (ECC) - 0x1EB6 - 0x10 - 0x00000000 - - - KEY3_3 - [15:0] - read-only - - - - - KEY3_4 - Bits 79:64 of OTP access key 3 (ECC) - 0x1EB8 - 0x10 - 0x00000000 - - - KEY3_4 - [15:0] - read-only - - - - - KEY3_5 - Bits 95:80 of OTP access key 3 (ECC) - 0x1EBA - 0x10 - 0x00000000 - - - KEY3_5 - [15:0] - read-only - - - - - KEY3_6 - Bits 111:96 of OTP access key 3 (ECC) - 0x1EBC - 0x10 - 0x00000000 - - - KEY3_6 - [15:0] - read-only - - - - - KEY3_7 - Bits 127:112 of OTP access key 3 (ECC) - 0x1EBE - 0x10 - 0x00000000 - - - KEY3_7 - [15:0] - read-only - - - - - KEY4_0 - Bits 15:0 of OTP access key 4 (ECC) - 0x1EC0 - 0x10 - 0x00000000 - - - KEY4_0 - [15:0] - read-only - - - - - KEY4_1 - Bits 31:16 of OTP access key 4 (ECC) - 0x1EC2 - 0x10 - 0x00000000 - - - KEY4_1 - [15:0] - read-only - - - - - KEY4_2 - Bits 47:32 of OTP access key 4 (ECC) - 0x1EC4 - 0x10 - 0x00000000 - - - KEY4_2 - [15:0] - read-only - - - - - KEY4_3 - Bits 63:48 of OTP access key 4 (ECC) - 0x1EC6 - 0x10 - 0x00000000 - - - KEY4_3 - [15:0] - read-only - - - - - KEY4_4 - Bits 79:64 of OTP access key 4 (ECC) - 0x1EC8 - 0x10 - 0x00000000 - - - KEY4_4 - [15:0] - read-only - - - - - KEY4_5 - Bits 95:80 of OTP access key 4 (ECC) - 0x1ECA - 0x10 - 0x00000000 - - - KEY4_5 - [15:0] - read-only - - - - - KEY4_6 - Bits 111:96 of OTP access key 4 (ECC) - 0x1ECC - 0x10 - 0x00000000 - - - KEY4_6 - [15:0] - read-only - - - - - KEY4_7 - Bits 127:112 of OTP access key 4 (ECC) - 0x1ECE - 0x10 - 0x00000000 - - - KEY4_7 - [15:0] - read-only - - - - - KEY5_0 - Bits 15:0 of OTP access key 5 (ECC) - 0x1ED0 - 0x10 - 0x00000000 - - - KEY5_0 - [15:0] - read-only - - - - - KEY5_1 - Bits 31:16 of OTP access key 5 (ECC) - 0x1ED2 - 0x10 - 0x00000000 - - - KEY5_1 - [15:0] - read-only - - - - - KEY5_2 - Bits 47:32 of OTP access key 5 (ECC) - 0x1ED4 - 0x10 - 0x00000000 - - - KEY5_2 - [15:0] - read-only - - - - - KEY5_3 - Bits 63:48 of OTP access key 5 (ECC) - 0x1ED6 - 0x10 - 0x00000000 - - - KEY5_3 - [15:0] - read-only - - - - - KEY5_4 - Bits 79:64 of OTP access key 5 (ECC) - 0x1ED8 - 0x10 - 0x00000000 - - - KEY5_4 - [15:0] - read-only - - - - - KEY5_5 - Bits 95:80 of OTP access key 5 (ECC) - 0x1EDA - 0x10 - 0x00000000 - - - KEY5_5 - [15:0] - read-only - - - - - KEY5_6 - Bits 111:96 of OTP access key 5 (ECC) - 0x1EDC - 0x10 - 0x00000000 - - - KEY5_6 - [15:0] - read-only - - - - - KEY5_7 - Bits 127:112 of OTP access key 5 (ECC) - 0x1EDE - 0x10 - 0x00000000 - - - KEY5_7 - [15:0] - read-only - - - - - KEY6_0 - Bits 15:0 of OTP access key 6 (ECC) - 0x1EE0 - 0x10 - 0x00000000 - - - KEY6_0 - [15:0] - read-only - - - - - KEY6_1 - Bits 31:16 of OTP access key 6 (ECC) - 0x1EE2 - 0x10 - 0x00000000 - - - KEY6_1 - [15:0] - read-only - - - - - KEY6_2 - Bits 47:32 of OTP access key 6 (ECC) - 0x1EE4 - 0x10 - 0x00000000 - - - KEY6_2 - [15:0] - read-only - - - - - KEY6_3 - Bits 63:48 of OTP access key 6 (ECC) - 0x1EE6 - 0x10 - 0x00000000 - - - KEY6_3 - [15:0] - read-only - - - - - KEY6_4 - Bits 79:64 of OTP access key 6 (ECC) - 0x1EE8 - 0x10 - 0x00000000 - - - KEY6_4 - [15:0] - read-only - - - - - KEY6_5 - Bits 95:80 of OTP access key 6 (ECC) - 0x1EEA - 0x10 - 0x00000000 - - - KEY6_5 - [15:0] - read-only - - - - - KEY6_6 - Bits 111:96 of OTP access key 6 (ECC) - 0x1EEC - 0x10 - 0x00000000 - - - KEY6_6 - [15:0] - read-only - - - - - KEY6_7 - Bits 127:112 of OTP access key 6 (ECC) - 0x1EEE - 0x10 - 0x00000000 - - - KEY6_7 - [15:0] - read-only - - - - - - - OTP_DATA_RAW - Predefined OTP data layout for RP2350 - 0x40134000 - - 0x0 - 0x3FFF - registers - - - - CHIPID0 - Bits 15:0 of public device ID. (ECC) - - The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. - - The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. - 0x0 - 0x20 - 0x00000000 - - - CHIPID0 - [23:0] - read-only - - - - - CHIPID1 - Bits 31:16 of public device ID (ECC) - 0x4 - 0x20 - 0x00000000 - - - CHIPID1 - [23:0] - read-only - - - - - CHIPID2 - Bits 47:32 of public device ID (ECC) - 0x8 - 0x20 - 0x00000000 - - - CHIPID2 - [23:0] - read-only - - - - - CHIPID3 - Bits 63:48 of public device ID (ECC) - 0xC - 0x20 - 0x00000000 - - - CHIPID3 - [23:0] - read-only - - - - - RANDID0 - Bits 15:0 of private per-device random number (ECC) - - The RANDID0..7 rows form a 128-bit random number generated during device test. - - This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. - 0x10 - 0x20 - 0x00000000 - - - RANDID0 - [23:0] - read-only - - - - - RANDID1 - Bits 31:16 of private per-device random number (ECC) - 0x14 - 0x20 - 0x00000000 - - - RANDID1 - [23:0] - read-only - - - - - RANDID2 - Bits 47:32 of private per-device random number (ECC) - 0x18 - 0x20 - 0x00000000 - - - RANDID2 - [23:0] - read-only - - - - - RANDID3 - Bits 63:48 of private per-device random number (ECC) - 0x1C - 0x20 - 0x00000000 - - - RANDID3 - [23:0] - read-only - - - - - RANDID4 - Bits 79:64 of private per-device random number (ECC) - 0x20 - 0x20 - 0x00000000 - - - RANDID4 - [23:0] - read-only - - - - - RANDID5 - Bits 95:80 of private per-device random number (ECC) - 0x24 - 0x20 - 0x00000000 - - - RANDID5 - [23:0] - read-only - - - - - RANDID6 - Bits 111:96 of private per-device random number (ECC) - 0x28 - 0x20 - 0x00000000 - - - RANDID6 - [23:0] - read-only - - - - - RANDID7 - Bits 127:112 of private per-device random number (ECC) - 0x2C - 0x20 - 0x00000000 - - - RANDID7 - [23:0] - read-only - - - - - ROSC_CALIB - Ring oscillator frequency in kHz, measured during manufacturing (ECC) - - This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. - 0x40 - 0x20 - 0x00000000 - - - ROSC_CALIB - [23:0] - read-only - - - - - LPOSC_CALIB - Low-power oscillator frequency in Hz, measured during manufacturing (ECC) - - This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. - 0x44 - 0x20 - 0x00000000 - - - LPOSC_CALIB - [23:0] - read-only - - - - - NUM_GPIOS - The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) - 0x60 - 0x20 - 0x00000000 - - - NUM_GPIOS - [23:0] - read-only - - - - - INFO_CRC0 - Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) - 0xD8 - 0x20 - 0x00000000 - - - INFO_CRC0 - [23:0] - read-only - - - - - INFO_CRC1 - Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) - 0xDC - 0x20 - 0x00000000 - - - INFO_CRC1 - [23:0] - read-only - - - - - CRIT0 - Page 0 critical boot flags (RBIT-8) - 0xE0 - 0x20 - 0x00000000 - - - RISCV_DISABLE - Permanently disable RISC-V processors (Hazard3) - [1:1] - read-only - - - ARM_DISABLE - Permanently disable ARM processors (Cortex-M33) - [0:0] - read-only - - - - - CRIT0_R1 - Redundant copy of CRIT0 - 0xE4 - 0x20 - 0x00000000 - - - CRIT0_R1 - [23:0] - read-only - - - - - CRIT0_R2 - Redundant copy of CRIT0 - 0xE8 - 0x20 - 0x00000000 - - - CRIT0_R2 - [23:0] - read-only - - - - - CRIT0_R3 - Redundant copy of CRIT0 - 0xEC - 0x20 - 0x00000000 - - - CRIT0_R3 - [23:0] - read-only - - - - - CRIT0_R4 - Redundant copy of CRIT0 - 0xF0 - 0x20 - 0x00000000 - - - CRIT0_R4 - [23:0] - read-only - - - - - CRIT0_R5 - Redundant copy of CRIT0 - 0xF4 - 0x20 - 0x00000000 - - - CRIT0_R5 - [23:0] - read-only - - - - - CRIT0_R6 - Redundant copy of CRIT0 - 0xF8 - 0x20 - 0x00000000 - - - CRIT0_R6 - [23:0] - read-only - - - - - CRIT0_R7 - Redundant copy of CRIT0 - 0xFC - 0x20 - 0x00000000 - - - CRIT0_R7 - [23:0] - read-only - - - - - CRIT1 - Page 1 critical boot flags (RBIT-8) - 0x100 - 0x20 - 0x00000000 - - - GLITCH_DETECTOR_SENS - Increase the sensitivity of the glitch detectors from their default. - [6:5] - read-only - - - GLITCH_DETECTOR_ENABLE - Arm the glitch detectors to reset the system if an abnormal clock/power event is observed. - [4:4] - read-only - - - BOOT_ARCH - Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. - [3:3] - read-only - - - DEBUG_DISABLE - Disable all debug access - [2:2] - read-only - - - SECURE_DEBUG_DISABLE - Disable Secure debug access - [1:1] - read-only - - - SECURE_BOOT_ENABLE - Enable boot signature enforcement, and permanently disable the RISC-V cores. - [0:0] - read-only - - - - - CRIT1_R1 - Redundant copy of CRIT1 - 0x104 - 0x20 - 0x00000000 - - - CRIT1_R1 - [23:0] - read-only - - - - - CRIT1_R2 - Redundant copy of CRIT1 - 0x108 - 0x20 - 0x00000000 - - - CRIT1_R2 - [23:0] - read-only - - - - - CRIT1_R3 - Redundant copy of CRIT1 - 0x10C - 0x20 - 0x00000000 - - - CRIT1_R3 - [23:0] - read-only - - - - - CRIT1_R4 - Redundant copy of CRIT1 - 0x110 - 0x20 - 0x00000000 - - - CRIT1_R4 - [23:0] - read-only - - - - - CRIT1_R5 - Redundant copy of CRIT1 - 0x114 - 0x20 - 0x00000000 - - - CRIT1_R5 - [23:0] - read-only - - - - - CRIT1_R6 - Redundant copy of CRIT1 - 0x118 - 0x20 - 0x00000000 - - - CRIT1_R6 - [23:0] - read-only - - - - - CRIT1_R7 - Redundant copy of CRIT1 - 0x11C - 0x20 - 0x00000000 - - - CRIT1_R7 - [23:0] - read-only - - - - - BOOT_FLAGS0 - Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) - 0x120 - 0x20 - 0x00000000 - - - DISABLE_SRAM_WINDOW_BOOT - [21:21] - read-only - - - DISABLE_XIP_ACCESS_ON_SRAM_ENTRY - Disable all access to XIP after entering an SRAM binary. - - Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table. - [20:20] - read-only - - - DISABLE_BOOTSEL_UART_BOOT - [19:19] - read-only - - - DISABLE_BOOTSEL_USB_PICOBOOT_IFC - [18:18] - read-only - - - DISABLE_BOOTSEL_USB_MSD_IFC - [17:17] - read-only - - - DISABLE_WATCHDOG_SCRATCH - [16:16] - read-only - - - DISABLE_POWER_SCRATCH - [15:15] - read-only - - - ENABLE_OTP_BOOT - Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. - - The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. - - Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window. - [14:14] - read-only - - - DISABLE_OTP_BOOT - Takes precedence over ENABLE_OTP_BOOT. - [13:13] - read-only - - - DISABLE_FLASH_BOOT - [12:12] - read-only - - - ROLLBACK_REQUIRED - Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted. - [11:11] - read-only - - - HASHED_PARTITION_TABLE - Require a partition table to be hashed (if not signed) - [10:10] - read-only - - - SECURE_PARTITION_TABLE - Require a partition table to be signed - [9:9] - read-only - - - DISABLE_AUTO_SWITCH_ARCH - Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled - [8:8] - read-only - - - SINGLE_FLASH_BINARY - Restrict flash boot path to use of a single binary at the start of flash - [7:7] - read-only - - - OVERRIDE_FLASH_PARTITION_SLOT_SIZE - Override the limit for default flash metadata scanning. - - The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit - [6:6] - read-only - - - FLASH_DEVINFO_ENABLE - Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices. - [5:5] - read-only - - - FAST_SIGCHECK_ROSC_DIV - Enable quartering of ROSC divisor during signature check, to reduce secure boot time - [4:4] - read-only - - - FLASH_IO_VOLTAGE_1V8 - If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. - - If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V) - [3:3] - read-only - - - ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG - Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. - - Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. - - If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz. - [2:2] - read-only - - - ENABLE_BOOTSEL_LED - Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid - [1:1] - read-only - - - DISABLE_BOOTSEL_EXEC2 - [0:0] - read-only - - - - - BOOT_FLAGS0_R1 - Redundant copy of BOOT_FLAGS0 - 0x124 - 0x20 - 0x00000000 - - - BOOT_FLAGS0_R1 - [23:0] - read-only - - - - - BOOT_FLAGS0_R2 - Redundant copy of BOOT_FLAGS0 - 0x128 - 0x20 - 0x00000000 - - - BOOT_FLAGS0_R2 - [23:0] - read-only - - - - - BOOT_FLAGS1 - Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) - 0x12C - 0x20 - 0x00000000 - - - DOUBLE_TAP - Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. - - This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART. - [19:19] - read-only - - - DOUBLE_TAP_DELAY - Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. - - For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. - - 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value. - [18:16] - read-only - - - KEY_INVALID - Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. - - Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. - - When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time. - [11:8] - read-only - - - KEY_VALID - Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. - - Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. - - A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. - - Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. - - Do not enable secure boot without first installing a valid key. This will render your device unbootable. - [3:0] - read-only - - - - - BOOT_FLAGS1_R1 - Redundant copy of BOOT_FLAGS1 - 0x130 - 0x20 - 0x00000000 - - - BOOT_FLAGS1_R1 - [23:0] - read-only - - - - - BOOT_FLAGS1_R2 - Redundant copy of BOOT_FLAGS1 - 0x134 - 0x20 - 0x00000000 - - - BOOT_FLAGS1_R2 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION0 - Default boot version thermometer counter, bits 23:0 (RBIT-3) - 0x138 - 0x20 - 0x00000000 - - - DEFAULT_BOOT_VERSION0 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION0_R1 - Redundant copy of DEFAULT_BOOT_VERSION0 - 0x13C - 0x20 - 0x00000000 - - - DEFAULT_BOOT_VERSION0_R1 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION0_R2 - Redundant copy of DEFAULT_BOOT_VERSION0 - 0x140 - 0x20 - 0x00000000 - - - DEFAULT_BOOT_VERSION0_R2 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION1 - Default boot version thermometer counter, bits 47:24 (RBIT-3) - 0x144 - 0x20 - 0x00000000 - - - DEFAULT_BOOT_VERSION1 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION1_R1 - Redundant copy of DEFAULT_BOOT_VERSION1 - 0x148 - 0x20 - 0x00000000 - - - DEFAULT_BOOT_VERSION1_R1 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION1_R2 - Redundant copy of DEFAULT_BOOT_VERSION1 - 0x14C - 0x20 - 0x00000000 - - - DEFAULT_BOOT_VERSION1_R2 - [23:0] - read-only - - - - - FLASH_DEVINFO - Stores information about external flash device(s). (ECC) - - Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. - 0x150 - 0x20 - 0x00000000 - - - CS1_SIZE - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). - - A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. - [23:12] - read-only - - - NONE - 0 - - - 8K - 1 - - - 16K - 2 - - - 32K - 3 - - - 64k - 4 - - - 128K - 5 - - - 256K - 6 - - - 512K - 7 - - - 1M - 8 - - - 2M - 9 - - - 4M - 10 - - - 8M - 11 - - - 16M - 12 - - - - - CS0_SIZE - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). - - A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. - [11:8] - read-only - - - NONE - 0 - - - 8K - 1 - - - 16K - 2 - - - 32K - 3 - - - 64k - 4 - - - 128K - 5 - - - 256K - 6 - - - 512K - 7 - - - 1M - 8 - - - 2M - 9 - - - 4M - 10 - - - 8M - 11 - - - 16M - 12 - - - - - D8H_ERASE_SUPPORTED - If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. - - If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. - [7:7] - read-only - - - CS1_GPIO - Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. - - On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. - - Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). - [5:0] - read-only - - - - - FLASH_PARTITION_SLOT_SIZE - Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) - 0x154 - 0x20 - 0x00000000 - - - FLASH_PARTITION_SLOT_SIZE - [23:0] - read-only - - - - - BOOTSEL_LED_CFG - Pin configuration for LED status, used by USB bootloader. (ECC) - Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. - 0x158 - 0x20 - 0x00000000 - - - ACTIVELOW - LED is active-low. (Default: active-high.) - [23:8] - read-only - - - PIN - GPIO index to use for bootloader activity LED. - [5:0] - read-only - - - - - BOOTSEL_PLL_CFG - Optional PLL configuration for BOOTSEL mode. (ECC) - - This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. - - If no configuration is given, the crystal is assumed to be 12 MHz. - - The PLL frequency can be calculated as: - - PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) - - Conversely the crystal frequency can be calculated as: - - XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV - - (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) - - Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. - 0x15C - 0x20 - 0x00000000 - - - REFDIV - PLL reference divisor, minus one. - - Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) - [23:15] - read-only - - - POSTDIV2 - PLL post-divide 2 divisor, in the range 1..7 inclusive. - [14:12] - read-only - - - POSTDIV1 - PLL post-divide 1 divisor, in the range 1..7 inclusive. - [11:9] - read-only - - - FBDIV - PLL feedback divisor, in the range 16..320 inclusive. - [8:0] - read-only - - - - - BOOTSEL_XOSC_CFG - Non-default crystal oscillator configuration for the USB bootloader. (ECC) - - These values may also be used by user code configuring the crystal oscillator. - - Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. - 0x160 - 0x20 - 0x00000000 - - - RANGE - Value of the XOSC_CTRL_FREQ_RANGE register. - [23:14] - read-only - - - 1_15MHZ - 0 - - - 10_30MHZ - 1 - - - 25_60MHZ - 2 - - - 40_100MHZ - 3 - - - - - STARTUP - Value of the XOSC_STARTUP register - [13:0] - read-only - - - - - USB_BOOT_FLAGS - USB boot specific feature flags (RBIT-3) - 0x164 - 0x20 - 0x00000000 - - - DP_DM_SWAP - Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental). - [23:23] - read-only - - - WHITE_LABEL_ADDR_VALID - valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15) - [22:22] - read-only - - - WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID - valid flag for the USB_WHITE_LABEL_ADDR field - [15:15] - read-only - - - WL_INFO_UF2_TXT_MODEL_STRDEF_VALID - valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14) - [14:14] - read-only - - - WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID - valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13) - [13:13] - read-only - - - WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID - valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12) - [12:12] - read-only - - - WL_SCSI_INQUIRY_VERSION_STRDEF_VALID - valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11) - [11:11] - read-only - - - WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID - valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10) - [10:10] - read-only - - - WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID - valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9) - [9:9] - read-only - - - WL_VOLUME_LABEL_STRDEF_VALID - valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8) - [8:8] - read-only - - - WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID - valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7) - [7:7] - read-only - - - WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID - valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6) - [6:6] - read-only - - - WL_USB_DEVICE_PRODUCT_STRDEF_VALID - valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5) - [5:5] - read-only - - - WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID - valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4) - [4:4] - read-only - - - WL_USB_DEVICE_LANG_ID_VALUE_VALID - valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3) - [3:3] - read-only - - - WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID - valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2) - [2:2] - read-only - - - WL_USB_DEVICE_PID_VALUE_VALID - valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1) - [1:1] - read-only - - - WL_USB_DEVICE_VID_VALUE_VALID - valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0) - [0:0] - read-only - - - - - USB_BOOT_FLAGS_R1 - Redundant copy of USB_BOOT_FLAGS - 0x168 - 0x20 - 0x00000000 - - - USB_BOOT_FLAGS_R1 - [23:0] - read-only - - - - - USB_BOOT_FLAGS_R2 - Redundant copy of USB_BOOT_FLAGS - 0x16C - 0x20 - 0x00000000 - - - USB_BOOT_FLAGS_R2 - [23:0] - read-only - - - - - USB_WHITE_LABEL_ADDR - Row index of the USB_WHITE_LABEL structure within OTP (ECC) - - The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). - - The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. - - The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. - - In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. - - Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. - - Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. - - The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): - 0x170 - 0x20 - 0x00000000 - - - USB_WHITE_LABEL_ADDR - [23:0] - read-only - - - INDEX_USB_DEVICE_VID_VALUE - 0 - - - INDEX_USB_DEVICE_PID_VALUE - 1 - - - INDEX_USB_DEVICE_BCD_DEVICE_VALUE - 2 - - - INDEX_USB_DEVICE_LANG_ID_VALUE - 3 - - - INDEX_USB_DEVICE_MANUFACTURER_STRDEF - 4 - - - INDEX_USB_DEVICE_PRODUCT_STRDEF - 5 - - - INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF - 6 - - - INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES - 7 - - - INDEX_VOLUME_LABEL_STRDEF - 8 - - - INDEX_SCSI_INQUIRY_VENDOR_STRDEF - 9 - - - INDEX_SCSI_INQUIRY_PRODUCT_STRDEF - 10 - - - INDEX_SCSI_INQUIRY_VERSION_STRDEF - 11 - - - INDEX_INDEX_HTM_REDIRECT_URL_STRDEF - 12 - - - INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF - 13 - - - INDEX_INFO_UF2_TXT_MODEL_STRDEF - 14 - - - INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF - 15 - - - - - - - OTPBOOT_SRC - OTP start row for the OTP boot image. (ECC) - - If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. - - This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. - 0x178 - 0x20 - 0x00000000 - - - OTPBOOT_SRC - [23:0] - read-only - - - - - OTPBOOT_LEN - Length in rows of the OTP boot image. (ECC) - - OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). - 0x17C - 0x20 - 0x00000000 - - - OTPBOOT_LEN - [23:0] - read-only - - - - - OTPBOOT_DST0 - Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) - - This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. - 0x180 - 0x20 - 0x00000000 - - - OTPBOOT_DST0 - [23:0] - read-only - - - - - OTPBOOT_DST1 - Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) - - This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. - 0x184 - 0x20 - 0x00000000 - - - OTPBOOT_DST1 - [23:0] - read-only - - - - - BOOTKEY0_0 - Bits 15:0 of SHA-256 hash of boot key 0 (ECC) - 0x200 - 0x20 - 0x00000000 - - - BOOTKEY0_0 - [23:0] - read-only - - - - - BOOTKEY0_1 - Bits 31:16 of SHA-256 hash of boot key 0 (ECC) - 0x204 - 0x20 - 0x00000000 - - - BOOTKEY0_1 - [23:0] - read-only - - - - - BOOTKEY0_2 - Bits 47:32 of SHA-256 hash of boot key 0 (ECC) - 0x208 - 0x20 - 0x00000000 - - - BOOTKEY0_2 - [23:0] - read-only - - - - - BOOTKEY0_3 - Bits 63:48 of SHA-256 hash of boot key 0 (ECC) - 0x20C - 0x20 - 0x00000000 - - - BOOTKEY0_3 - [23:0] - read-only - - - - - BOOTKEY0_4 - Bits 79:64 of SHA-256 hash of boot key 0 (ECC) - 0x210 - 0x20 - 0x00000000 - - - BOOTKEY0_4 - [23:0] - read-only - - - - - BOOTKEY0_5 - Bits 95:80 of SHA-256 hash of boot key 0 (ECC) - 0x214 - 0x20 - 0x00000000 - - - BOOTKEY0_5 - [23:0] - read-only - - - - - BOOTKEY0_6 - Bits 111:96 of SHA-256 hash of boot key 0 (ECC) - 0x218 - 0x20 - 0x00000000 - - - BOOTKEY0_6 - [23:0] - read-only - - - - - BOOTKEY0_7 - Bits 127:112 of SHA-256 hash of boot key 0 (ECC) - 0x21C - 0x20 - 0x00000000 - - - BOOTKEY0_7 - [23:0] - read-only - - - - - BOOTKEY0_8 - Bits 143:128 of SHA-256 hash of boot key 0 (ECC) - 0x220 - 0x20 - 0x00000000 - - - BOOTKEY0_8 - [23:0] - read-only - - - - - BOOTKEY0_9 - Bits 159:144 of SHA-256 hash of boot key 0 (ECC) - 0x224 - 0x20 - 0x00000000 - - - BOOTKEY0_9 - [23:0] - read-only - - - - - BOOTKEY0_10 - Bits 175:160 of SHA-256 hash of boot key 0 (ECC) - 0x228 - 0x20 - 0x00000000 - - - BOOTKEY0_10 - [23:0] - read-only - - - - - BOOTKEY0_11 - Bits 191:176 of SHA-256 hash of boot key 0 (ECC) - 0x22C - 0x20 - 0x00000000 - - - BOOTKEY0_11 - [23:0] - read-only - - - - - BOOTKEY0_12 - Bits 207:192 of SHA-256 hash of boot key 0 (ECC) - 0x230 - 0x20 - 0x00000000 - - - BOOTKEY0_12 - [23:0] - read-only - - - - - BOOTKEY0_13 - Bits 223:208 of SHA-256 hash of boot key 0 (ECC) - 0x234 - 0x20 - 0x00000000 - - - BOOTKEY0_13 - [23:0] - read-only - - - - - BOOTKEY0_14 - Bits 239:224 of SHA-256 hash of boot key 0 (ECC) - 0x238 - 0x20 - 0x00000000 - - - BOOTKEY0_14 - [23:0] - read-only - - - - - BOOTKEY0_15 - Bits 255:240 of SHA-256 hash of boot key 0 (ECC) - 0x23C - 0x20 - 0x00000000 - - - BOOTKEY0_15 - [23:0] - read-only - - - - - BOOTKEY1_0 - Bits 15:0 of SHA-256 hash of boot key 1 (ECC) - 0x240 - 0x20 - 0x00000000 - - - BOOTKEY1_0 - [23:0] - read-only - - - - - BOOTKEY1_1 - Bits 31:16 of SHA-256 hash of boot key 1 (ECC) - 0x244 - 0x20 - 0x00000000 - - - BOOTKEY1_1 - [23:0] - read-only - - - - - BOOTKEY1_2 - Bits 47:32 of SHA-256 hash of boot key 1 (ECC) - 0x248 - 0x20 - 0x00000000 - - - BOOTKEY1_2 - [23:0] - read-only - - - - - BOOTKEY1_3 - Bits 63:48 of SHA-256 hash of boot key 1 (ECC) - 0x24C - 0x20 - 0x00000000 - - - BOOTKEY1_3 - [23:0] - read-only - - - - - BOOTKEY1_4 - Bits 79:64 of SHA-256 hash of boot key 1 (ECC) - 0x250 - 0x20 - 0x00000000 - - - BOOTKEY1_4 - [23:0] - read-only - - - - - BOOTKEY1_5 - Bits 95:80 of SHA-256 hash of boot key 1 (ECC) - 0x254 - 0x20 - 0x00000000 - - - BOOTKEY1_5 - [23:0] - read-only - - - - - BOOTKEY1_6 - Bits 111:96 of SHA-256 hash of boot key 1 (ECC) - 0x258 - 0x20 - 0x00000000 - - - BOOTKEY1_6 - [23:0] - read-only - - - - - BOOTKEY1_7 - Bits 127:112 of SHA-256 hash of boot key 1 (ECC) - 0x25C - 0x20 - 0x00000000 - - - BOOTKEY1_7 - [23:0] - read-only - - - - - BOOTKEY1_8 - Bits 143:128 of SHA-256 hash of boot key 1 (ECC) - 0x260 - 0x20 - 0x00000000 - - - BOOTKEY1_8 - [23:0] - read-only - - - - - BOOTKEY1_9 - Bits 159:144 of SHA-256 hash of boot key 1 (ECC) - 0x264 - 0x20 - 0x00000000 - - - BOOTKEY1_9 - [23:0] - read-only - - - - - BOOTKEY1_10 - Bits 175:160 of SHA-256 hash of boot key 1 (ECC) - 0x268 - 0x20 - 0x00000000 - - - BOOTKEY1_10 - [23:0] - read-only - - - - - BOOTKEY1_11 - Bits 191:176 of SHA-256 hash of boot key 1 (ECC) - 0x26C - 0x20 - 0x00000000 - - - BOOTKEY1_11 - [23:0] - read-only - - - - - BOOTKEY1_12 - Bits 207:192 of SHA-256 hash of boot key 1 (ECC) - 0x270 - 0x20 - 0x00000000 - - - BOOTKEY1_12 - [23:0] - read-only - - - - - BOOTKEY1_13 - Bits 223:208 of SHA-256 hash of boot key 1 (ECC) - 0x274 - 0x20 - 0x00000000 - - - BOOTKEY1_13 - [23:0] - read-only - - - - - BOOTKEY1_14 - Bits 239:224 of SHA-256 hash of boot key 1 (ECC) - 0x278 - 0x20 - 0x00000000 - - - BOOTKEY1_14 - [23:0] - read-only - - - - - BOOTKEY1_15 - Bits 255:240 of SHA-256 hash of boot key 1 (ECC) - 0x27C - 0x20 - 0x00000000 - - - BOOTKEY1_15 - [23:0] - read-only - - - - - BOOTKEY2_0 - Bits 15:0 of SHA-256 hash of boot key 2 (ECC) - 0x280 - 0x20 - 0x00000000 - - - BOOTKEY2_0 - [23:0] - read-only - - - - - BOOTKEY2_1 - Bits 31:16 of SHA-256 hash of boot key 2 (ECC) - 0x284 - 0x20 - 0x00000000 - - - BOOTKEY2_1 - [23:0] - read-only - - - - - BOOTKEY2_2 - Bits 47:32 of SHA-256 hash of boot key 2 (ECC) - 0x288 - 0x20 - 0x00000000 - - - BOOTKEY2_2 - [23:0] - read-only - - - - - BOOTKEY2_3 - Bits 63:48 of SHA-256 hash of boot key 2 (ECC) - 0x28C - 0x20 - 0x00000000 - - - BOOTKEY2_3 - [23:0] - read-only - - - - - BOOTKEY2_4 - Bits 79:64 of SHA-256 hash of boot key 2 (ECC) - 0x290 - 0x20 - 0x00000000 - - - BOOTKEY2_4 - [23:0] - read-only - - - - - BOOTKEY2_5 - Bits 95:80 of SHA-256 hash of boot key 2 (ECC) - 0x294 - 0x20 - 0x00000000 - - - BOOTKEY2_5 - [23:0] - read-only - - - - - BOOTKEY2_6 - Bits 111:96 of SHA-256 hash of boot key 2 (ECC) - 0x298 - 0x20 - 0x00000000 - - - BOOTKEY2_6 - [23:0] - read-only - - - - - BOOTKEY2_7 - Bits 127:112 of SHA-256 hash of boot key 2 (ECC) - 0x29C - 0x20 - 0x00000000 - - - BOOTKEY2_7 - [23:0] - read-only - - - - - BOOTKEY2_8 - Bits 143:128 of SHA-256 hash of boot key 2 (ECC) - 0x2A0 - 0x20 - 0x00000000 - - - BOOTKEY2_8 - [23:0] - read-only - - - - - BOOTKEY2_9 - Bits 159:144 of SHA-256 hash of boot key 2 (ECC) - 0x2A4 - 0x20 - 0x00000000 - - - BOOTKEY2_9 - [23:0] - read-only - - - - - BOOTKEY2_10 - Bits 175:160 of SHA-256 hash of boot key 2 (ECC) - 0x2A8 - 0x20 - 0x00000000 - - - BOOTKEY2_10 - [23:0] - read-only - - - - - BOOTKEY2_11 - Bits 191:176 of SHA-256 hash of boot key 2 (ECC) - 0x2AC - 0x20 - 0x00000000 - - - BOOTKEY2_11 - [23:0] - read-only - - - - - BOOTKEY2_12 - Bits 207:192 of SHA-256 hash of boot key 2 (ECC) - 0x2B0 - 0x20 - 0x00000000 - - - BOOTKEY2_12 - [23:0] - read-only - - - - - BOOTKEY2_13 - Bits 223:208 of SHA-256 hash of boot key 2 (ECC) - 0x2B4 - 0x20 - 0x00000000 - - - BOOTKEY2_13 - [23:0] - read-only - - - - - BOOTKEY2_14 - Bits 239:224 of SHA-256 hash of boot key 2 (ECC) - 0x2B8 - 0x20 - 0x00000000 - - - BOOTKEY2_14 - [23:0] - read-only - - - - - BOOTKEY2_15 - Bits 255:240 of SHA-256 hash of boot key 2 (ECC) - 0x2BC - 0x20 - 0x00000000 - - - BOOTKEY2_15 - [23:0] - read-only - - - - - BOOTKEY3_0 - Bits 15:0 of SHA-256 hash of boot key 3 (ECC) - 0x2C0 - 0x20 - 0x00000000 - - - BOOTKEY3_0 - [23:0] - read-only - - - - - BOOTKEY3_1 - Bits 31:16 of SHA-256 hash of boot key 3 (ECC) - 0x2C4 - 0x20 - 0x00000000 - - - BOOTKEY3_1 - [23:0] - read-only - - - - - BOOTKEY3_2 - Bits 47:32 of SHA-256 hash of boot key 3 (ECC) - 0x2C8 - 0x20 - 0x00000000 - - - BOOTKEY3_2 - [23:0] - read-only - - - - - BOOTKEY3_3 - Bits 63:48 of SHA-256 hash of boot key 3 (ECC) - 0x2CC - 0x20 - 0x00000000 - - - BOOTKEY3_3 - [23:0] - read-only - - - - - BOOTKEY3_4 - Bits 79:64 of SHA-256 hash of boot key 3 (ECC) - 0x2D0 - 0x20 - 0x00000000 - - - BOOTKEY3_4 - [23:0] - read-only - - - - - BOOTKEY3_5 - Bits 95:80 of SHA-256 hash of boot key 3 (ECC) - 0x2D4 - 0x20 - 0x00000000 - - - BOOTKEY3_5 - [23:0] - read-only - - - - - BOOTKEY3_6 - Bits 111:96 of SHA-256 hash of boot key 3 (ECC) - 0x2D8 - 0x20 - 0x00000000 - - - BOOTKEY3_6 - [23:0] - read-only - - - - - BOOTKEY3_7 - Bits 127:112 of SHA-256 hash of boot key 3 (ECC) - 0x2DC - 0x20 - 0x00000000 - - - BOOTKEY3_7 - [23:0] - read-only - - - - - BOOTKEY3_8 - Bits 143:128 of SHA-256 hash of boot key 3 (ECC) - 0x2E0 - 0x20 - 0x00000000 - - - BOOTKEY3_8 - [23:0] - read-only - - - - - BOOTKEY3_9 - Bits 159:144 of SHA-256 hash of boot key 3 (ECC) - 0x2E4 - 0x20 - 0x00000000 - - - BOOTKEY3_9 - [23:0] - read-only - - - - - BOOTKEY3_10 - Bits 175:160 of SHA-256 hash of boot key 3 (ECC) - 0x2E8 - 0x20 - 0x00000000 - - - BOOTKEY3_10 - [23:0] - read-only - - - - - BOOTKEY3_11 - Bits 191:176 of SHA-256 hash of boot key 3 (ECC) - 0x2EC - 0x20 - 0x00000000 - - - BOOTKEY3_11 - [23:0] - read-only - - - - - BOOTKEY3_12 - Bits 207:192 of SHA-256 hash of boot key 3 (ECC) - 0x2F0 - 0x20 - 0x00000000 - - - BOOTKEY3_12 - [23:0] - read-only - - - - - BOOTKEY3_13 - Bits 223:208 of SHA-256 hash of boot key 3 (ECC) - 0x2F4 - 0x20 - 0x00000000 - - - BOOTKEY3_13 - [23:0] - read-only - - - - - BOOTKEY3_14 - Bits 239:224 of SHA-256 hash of boot key 3 (ECC) - 0x2F8 - 0x20 - 0x00000000 - - - BOOTKEY3_14 - [23:0] - read-only - - - - - BOOTKEY3_15 - Bits 255:240 of SHA-256 hash of boot key 3 (ECC) - 0x2FC - 0x20 - 0x00000000 - - - BOOTKEY3_15 - [23:0] - read-only - - - - - KEY1_0 - Bits 15:0 of OTP access key 1 (ECC) - 0x3D20 - 0x20 - 0x00000000 - - - KEY1_0 - [23:0] - read-only - - - - - KEY1_1 - Bits 31:16 of OTP access key 1 (ECC) - 0x3D24 - 0x20 - 0x00000000 - - - KEY1_1 - [23:0] - read-only - - - - - KEY1_2 - Bits 47:32 of OTP access key 1 (ECC) - 0x3D28 - 0x20 - 0x00000000 - - - KEY1_2 - [23:0] - read-only - - - - - KEY1_3 - Bits 63:48 of OTP access key 1 (ECC) - 0x3D2C - 0x20 - 0x00000000 - - - KEY1_3 - [23:0] - read-only - - - - - KEY1_4 - Bits 79:64 of OTP access key 1 (ECC) - 0x3D30 - 0x20 - 0x00000000 - - - KEY1_4 - [23:0] - read-only - - - - - KEY1_5 - Bits 95:80 of OTP access key 1 (ECC) - 0x3D34 - 0x20 - 0x00000000 - - - KEY1_5 - [23:0] - read-only - - - - - KEY1_6 - Bits 111:96 of OTP access key 1 (ECC) - 0x3D38 - 0x20 - 0x00000000 - - - KEY1_6 - [23:0] - read-only - - - - - KEY1_7 - Bits 127:112 of OTP access key 1 (ECC) - 0x3D3C - 0x20 - 0x00000000 - - - KEY1_7 - [23:0] - read-only - - - - - KEY2_0 - Bits 15:0 of OTP access key 2 (ECC) - 0x3D40 - 0x20 - 0x00000000 - - - KEY2_0 - [23:0] - read-only - - - - - KEY2_1 - Bits 31:16 of OTP access key 2 (ECC) - 0x3D44 - 0x20 - 0x00000000 - - - KEY2_1 - [23:0] - read-only - - - - - KEY2_2 - Bits 47:32 of OTP access key 2 (ECC) - 0x3D48 - 0x20 - 0x00000000 - - - KEY2_2 - [23:0] - read-only - - - - - KEY2_3 - Bits 63:48 of OTP access key 2 (ECC) - 0x3D4C - 0x20 - 0x00000000 - - - KEY2_3 - [23:0] - read-only - - - - - KEY2_4 - Bits 79:64 of OTP access key 2 (ECC) - 0x3D50 - 0x20 - 0x00000000 - - - KEY2_4 - [23:0] - read-only - - - - - KEY2_5 - Bits 95:80 of OTP access key 2 (ECC) - 0x3D54 - 0x20 - 0x00000000 - - - KEY2_5 - [23:0] - read-only - - - - - KEY2_6 - Bits 111:96 of OTP access key 2 (ECC) - 0x3D58 - 0x20 - 0x00000000 - - - KEY2_6 - [23:0] - read-only - - - - - KEY2_7 - Bits 127:112 of OTP access key 2 (ECC) - 0x3D5C - 0x20 - 0x00000000 - - - KEY2_7 - [23:0] - read-only - - - - - KEY3_0 - Bits 15:0 of OTP access key 3 (ECC) - 0x3D60 - 0x20 - 0x00000000 - - - KEY3_0 - [23:0] - read-only - - - - - KEY3_1 - Bits 31:16 of OTP access key 3 (ECC) - 0x3D64 - 0x20 - 0x00000000 - - - KEY3_1 - [23:0] - read-only - - - - - KEY3_2 - Bits 47:32 of OTP access key 3 (ECC) - 0x3D68 - 0x20 - 0x00000000 - - - KEY3_2 - [23:0] - read-only - - - - - KEY3_3 - Bits 63:48 of OTP access key 3 (ECC) - 0x3D6C - 0x20 - 0x00000000 - - - KEY3_3 - [23:0] - read-only - - - - - KEY3_4 - Bits 79:64 of OTP access key 3 (ECC) - 0x3D70 - 0x20 - 0x00000000 - - - KEY3_4 - [23:0] - read-only - - - - - KEY3_5 - Bits 95:80 of OTP access key 3 (ECC) - 0x3D74 - 0x20 - 0x00000000 - - - KEY3_5 - [23:0] - read-only - - - - - KEY3_6 - Bits 111:96 of OTP access key 3 (ECC) - 0x3D78 - 0x20 - 0x00000000 - - - KEY3_6 - [23:0] - read-only - - - - - KEY3_7 - Bits 127:112 of OTP access key 3 (ECC) - 0x3D7C - 0x20 - 0x00000000 - - - KEY3_7 - [23:0] - read-only - - - - - KEY4_0 - Bits 15:0 of OTP access key 4 (ECC) - 0x3D80 - 0x20 - 0x00000000 - - - KEY4_0 - [23:0] - read-only - - - - - KEY4_1 - Bits 31:16 of OTP access key 4 (ECC) - 0x3D84 - 0x20 - 0x00000000 - - - KEY4_1 - [23:0] - read-only - - - - - KEY4_2 - Bits 47:32 of OTP access key 4 (ECC) - 0x3D88 - 0x20 - 0x00000000 - - - KEY4_2 - [23:0] - read-only - - - - - KEY4_3 - Bits 63:48 of OTP access key 4 (ECC) - 0x3D8C - 0x20 - 0x00000000 - - - KEY4_3 - [23:0] - read-only - - - - - KEY4_4 - Bits 79:64 of OTP access key 4 (ECC) - 0x3D90 - 0x20 - 0x00000000 - - - KEY4_4 - [23:0] - read-only - - - - - KEY4_5 - Bits 95:80 of OTP access key 4 (ECC) - 0x3D94 - 0x20 - 0x00000000 - - - KEY4_5 - [23:0] - read-only - - - - - KEY4_6 - Bits 111:96 of OTP access key 4 (ECC) - 0x3D98 - 0x20 - 0x00000000 - - - KEY4_6 - [23:0] - read-only - - - - - KEY4_7 - Bits 127:112 of OTP access key 4 (ECC) - 0x3D9C - 0x20 - 0x00000000 - - - KEY4_7 - [23:0] - read-only - - - - - KEY5_0 - Bits 15:0 of OTP access key 5 (ECC) - 0x3DA0 - 0x20 - 0x00000000 - - - KEY5_0 - [23:0] - read-only - - - - - KEY5_1 - Bits 31:16 of OTP access key 5 (ECC) - 0x3DA4 - 0x20 - 0x00000000 - - - KEY5_1 - [23:0] - read-only - - - - - KEY5_2 - Bits 47:32 of OTP access key 5 (ECC) - 0x3DA8 - 0x20 - 0x00000000 - - - KEY5_2 - [23:0] - read-only - - - - - KEY5_3 - Bits 63:48 of OTP access key 5 (ECC) - 0x3DAC - 0x20 - 0x00000000 - - - KEY5_3 - [23:0] - read-only - - - - - KEY5_4 - Bits 79:64 of OTP access key 5 (ECC) - 0x3DB0 - 0x20 - 0x00000000 - - - KEY5_4 - [23:0] - read-only - - - - - KEY5_5 - Bits 95:80 of OTP access key 5 (ECC) - 0x3DB4 - 0x20 - 0x00000000 - - - KEY5_5 - [23:0] - read-only - - - - - KEY5_6 - Bits 111:96 of OTP access key 5 (ECC) - 0x3DB8 - 0x20 - 0x00000000 - - - KEY5_6 - [23:0] - read-only - - - - - KEY5_7 - Bits 127:112 of OTP access key 5 (ECC) - 0x3DBC - 0x20 - 0x00000000 - - - KEY5_7 - [23:0] - read-only - - - - - KEY6_0 - Bits 15:0 of OTP access key 6 (ECC) - 0x3DC0 - 0x20 - 0x00000000 - - - KEY6_0 - [23:0] - read-only - - - - - KEY6_1 - Bits 31:16 of OTP access key 6 (ECC) - 0x3DC4 - 0x20 - 0x00000000 - - - KEY6_1 - [23:0] - read-only - - - - - KEY6_2 - Bits 47:32 of OTP access key 6 (ECC) - 0x3DC8 - 0x20 - 0x00000000 - - - KEY6_2 - [23:0] - read-only - - - - - KEY6_3 - Bits 63:48 of OTP access key 6 (ECC) - 0x3DCC - 0x20 - 0x00000000 - - - KEY6_3 - [23:0] - read-only - - - - - KEY6_4 - Bits 79:64 of OTP access key 6 (ECC) - 0x3DD0 - 0x20 - 0x00000000 - - - KEY6_4 - [23:0] - read-only - - - - - KEY6_5 - Bits 95:80 of OTP access key 6 (ECC) - 0x3DD4 - 0x20 - 0x00000000 - - - KEY6_5 - [23:0] - read-only - - - - - KEY6_6 - Bits 111:96 of OTP access key 6 (ECC) - 0x3DD8 - 0x20 - 0x00000000 - - - KEY6_6 - [23:0] - read-only - - - - - KEY6_7 - Bits 127:112 of OTP access key 6 (ECC) - 0x3DDC - 0x20 - 0x00000000 - - - KEY6_7 - [23:0] - read-only - - - - - KEY1_VALID - Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x3DE4 - 0x20 - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - KEY2_VALID - Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x3DE8 - 0x20 - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - KEY3_VALID - Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x3DEC - 0x20 - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - KEY4_VALID - Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x3DF0 - 0x20 - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - KEY5_VALID - Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x3DF4 - 0x20 - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - KEY6_VALID - Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x3DF8 - 0x20 - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - PAGE0_LOCK0 - Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E00 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE0_LOCK1 - Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E04 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE1_LOCK0 - Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E08 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE1_LOCK1 - Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E0C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE2_LOCK0 - Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E10 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE2_LOCK1 - Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E14 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE3_LOCK0 - Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E18 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE3_LOCK1 - Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E1C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE4_LOCK0 - Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E20 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE4_LOCK1 - Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E24 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE5_LOCK0 - Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E28 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE5_LOCK1 - Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E2C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE6_LOCK0 - Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E30 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE6_LOCK1 - Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E34 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE7_LOCK0 - Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E38 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE7_LOCK1 - Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E3C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE8_LOCK0 - Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E40 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE8_LOCK1 - Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E44 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE9_LOCK0 - Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E48 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE9_LOCK1 - Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E4C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE10_LOCK0 - Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E50 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE10_LOCK1 - Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E54 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE11_LOCK0 - Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E58 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE11_LOCK1 - Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E5C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE12_LOCK0 - Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E60 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE12_LOCK1 - Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E64 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE13_LOCK0 - Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E68 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE13_LOCK1 - Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E6C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE14_LOCK0 - Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E70 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE14_LOCK1 - Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E74 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE15_LOCK0 - Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E78 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE15_LOCK1 - Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E7C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE16_LOCK0 - Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E80 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE16_LOCK1 - Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E84 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE17_LOCK0 - Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E88 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE17_LOCK1 - Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E8C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE18_LOCK0 - Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E90 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE18_LOCK1 - Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E94 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE19_LOCK0 - Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E98 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE19_LOCK1 - Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3E9C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE20_LOCK0 - Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EA0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE20_LOCK1 - Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EA4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE21_LOCK0 - Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EA8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE21_LOCK1 - Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EAC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE22_LOCK0 - Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EB0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE22_LOCK1 - Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EB4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE23_LOCK0 - Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EB8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE23_LOCK1 - Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EBC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE24_LOCK0 - Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EC0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE24_LOCK1 - Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EC4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE25_LOCK0 - Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EC8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE25_LOCK1 - Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3ECC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE26_LOCK0 - Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3ED0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE26_LOCK1 - Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3ED4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE27_LOCK0 - Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3ED8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE27_LOCK1 - Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EDC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE28_LOCK0 - Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EE0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE28_LOCK1 - Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EE4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE29_LOCK0 - Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EE8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE29_LOCK1 - Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EEC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE30_LOCK0 - Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EF0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE30_LOCK1 - Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EF4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE31_LOCK0 - Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EF8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE31_LOCK1 - Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3EFC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE32_LOCK0 - Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F00 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE32_LOCK1 - Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F04 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE33_LOCK0 - Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F08 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE33_LOCK1 - Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F0C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE34_LOCK0 - Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F10 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE34_LOCK1 - Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F14 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE35_LOCK0 - Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F18 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE35_LOCK1 - Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F1C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE36_LOCK0 - Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F20 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE36_LOCK1 - Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F24 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE37_LOCK0 - Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F28 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE37_LOCK1 - Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F2C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE38_LOCK0 - Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F30 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE38_LOCK1 - Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F34 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE39_LOCK0 - Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F38 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE39_LOCK1 - Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F3C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE40_LOCK0 - Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F40 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE40_LOCK1 - Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F44 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE41_LOCK0 - Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F48 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE41_LOCK1 - Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F4C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE42_LOCK0 - Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F50 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE42_LOCK1 - Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F54 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE43_LOCK0 - Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F58 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE43_LOCK1 - Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F5C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE44_LOCK0 - Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F60 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE44_LOCK1 - Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F64 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE45_LOCK0 - Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F68 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE45_LOCK1 - Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F6C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE46_LOCK0 - Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F70 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE46_LOCK1 - Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F74 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE47_LOCK0 - Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F78 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE47_LOCK1 - Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F7C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE48_LOCK0 - Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F80 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE48_LOCK1 - Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F84 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE49_LOCK0 - Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F88 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE49_LOCK1 - Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F8C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE50_LOCK0 - Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F90 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE50_LOCK1 - Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F94 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE51_LOCK0 - Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F98 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE51_LOCK1 - Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3F9C - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE52_LOCK0 - Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FA0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE52_LOCK1 - Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FA4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE53_LOCK0 - Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FA8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE53_LOCK1 - Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FAC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE54_LOCK0 - Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FB0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE54_LOCK1 - Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FB4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE55_LOCK0 - Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FB8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE55_LOCK1 - Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FBC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE56_LOCK0 - Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FC0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE56_LOCK1 - Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FC4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE57_LOCK0 - Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FC8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE57_LOCK1 - Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FCC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE58_LOCK0 - Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FD0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE58_LOCK1 - Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FD4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE59_LOCK0 - Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FD8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE59_LOCK1 - Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FDC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE60_LOCK0 - Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FE0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE60_LOCK1 - Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FE4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE61_LOCK0 - Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FE8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE61_LOCK1 - Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FEC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE62_LOCK0 - Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FF0 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE62_LOCK1 - Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FF4 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - PAGE63_LOCK0 - Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FF8 - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - RMA - Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible. - [7:7] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE63_LOCK1 - Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x3FFC - 0x20 - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - Bootloader permits user reads and writes to this page - 0 - - - read_only - Bootloader permits user reads of this page - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE - 2 - - - inaccessible - Bootloader does not permit user access to this page - 3 - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - 0 - - - read_only - Page can be read by Non-secure software - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Non-secure software. - 3 - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - Page is fully accessible by Secure software. - 0 - - - read_only - Page can be read by Secure software, but can not be written. - 1 - - - reserved - Do not use. Behaves the same as INACCESSIBLE. - 2 - - - inaccessible - Page can not be accessed by Secure software. - 3 - - - - - - - - - TBMAN - For managing simulation testbenches - 0x40160000 - - 0x0 - 0x4 - registers - - - - PLATFORM - Indicates the type of platform in use - 0x0 - 0x00000001 - - - HDLSIM - Indicates the platform is a simulation - [2:2] - read-only - - - FPGA - Indicates the platform is an FPGA - [1:1] - read-only - - - ASIC - Indicates the platform is an ASIC - [0:0] - read-only - - - - - - - USB_DPRAM - DPRAM layout for USB device. - 0x50100000 - - 0x0 - 0x100 - registers - - - - SETUP_PACKET_LOW - Bytes 0-3 of the SETUP packet from the host. - 0x0 - 0x00000000 - - - WVALUE - [31:16] - read-write - - - BREQUEST - [15:8] - read-write - - - BMREQUESTTYPE - [7:0] - read-write - - - - - SETUP_PACKET_HIGH - Bytes 4-7 of the setup packet from the host. - 0x4 - 0x00000000 - - - WLENGTH - [31:16] - read-write - - - WINDEX - [15:0] - read-write - - - - - 30 - 0x4 - 0-29 - EP_CONTROL%s - TODO - 0x8 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - 32 - 0x4 - 0-31 - EP_BUFFER_CONTROL%s - TODO - 0x80 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - - - diff --git a/Tools/SVDs/stm32f7x6.patched.svd b/Tools/SVDs/stm32f7x6.patched.svd deleted file mode 100644 index db7cd9aa..00000000 --- a/Tools/SVDs/stm32f7x6.patched.svd +++ /dev/null @@ -1,54193 +0,0 @@ - - - STM32F7x6 - 1.6 - STM32F7x6 - - CM7 - r0p1 - little - true - true - 4 - false - - 8 - 32 - 0x20 - 0x00000000 - 0xFFFFFFFF - - - RNG - Random number generator - RNG - 0x50060800 - - 0x0 - 0x400 - registers - - - HASH_RNG - Hash and Rng global interrupt - 80 - - - - CR - CR - control register - 0x0 - 0x20 - read-write - 0x00000000 - - - IE - Interrupt enable - 3 - 1 - - - RNGEN - Random number generator enable - 2 - 1 - - - - - SR - SR - status register - 0x4 - 0x20 - 0x00000000 - - - SEIS - Seed error interrupt status - 6 - 1 - read-write - - - CEIS - Clock error interrupt status - 5 - 1 - read-write - - - SECS - Seed error current status - 2 - 1 - read-only - - - CECS - Clock error current status - 1 - 1 - read-only - - - DRDY - Data ready - 0 - 1 - read-only - - - - - DR - DR - data register - 0x8 - 0x20 - read-only - 0x00000000 - - - RNDATA - Random data - 0 - 32 - - - - - - - HASH - Hash processor - HASH - 0x50060400 - - 0x0 - 0x400 - registers - - - - CR - CR - control register - 0x0 - 0x20 - 0x00000000 - - - INIT - Initialize message digest calculation - 2 - 1 - write-only - - - DMAE - DMA enable - 3 - 1 - read-write - - - DATATYPE - Data type selection - 4 - 2 - read-write - - - MODE - Mode selection - 6 - 1 - read-write - - - ALGO0 - Algorithm selection - 7 - 1 - read-write - - - NBW - Number of words already pushed - 8 - 4 - read-only - - - DINNE - DIN not empty - 12 - 1 - read-only - - - MDMAT - Multiple DMA Transfers - 13 - 1 - read-write - - - LKEY - Long key selection - 16 - 1 - read-write - - - ALGO1 - ALGO - 18 - 1 - read-write - - - - - DIN - DIN - data input register - 0x4 - 0x20 - read-write - 0x00000000 - - - DATAIN - Data input - 0 - 32 - - - - - STR - STR - start register - 0x8 - 0x20 - 0x00000000 - - - DCAL - Digest calculation - 8 - 1 - write-only - - - NBLW - Number of valid bits in the last word of the message - 0 - 5 - read-write - - - - - 5 - 0x4 - 0-4 - HR%s - HR0 - digest registers - 0xC - 0x20 - read-only - 0x00000000 - - - H - H0 - 0 - 32 - - - - - IMR - IMR - interrupt enable register - 0x20 - 0x20 - read-write - 0x00000000 - - - DCIE - Digest calculation completion interrupt enable - 1 - 1 - - - DINIE - Data input interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x24 - 0x20 - 0x00000001 - - - BUSY - Busy bit - 3 - 1 - read-only - - - DMAS - DMA Status - 2 - 1 - read-only - - - DCIS - Digest calculation completion interrupt status - 1 - 1 - read-write - - - DINIS - Data input interrupt status - 0 - 1 - read-write - - - - - 54 - 0x4 - 0-53 - CSR%s - CSR0 - context swap registers - 0xF8 - 0x20 - read-write - 0x00000000 - - - CSR - CSR0 - 0 - 32 - - - - - 8 - 0x4 - 0-7 - HASH_HR%s - HASH_HR0 - HASH digest register - 0x310 - 0x20 - read-only - 0x00000000 - - - H - H0 - 0 - 32 - - - - - - - CRYP - Cryptographic processor - CRYP - 0x50060000 - - 0x0 - 0x400 - registers - - - CRYP - CRYP crypto global interrupt - 79 - - - - CR - CR - control register - 0x0 - 0x20 - 0x00000000 - - - ALGODIR - Algorithm direction - 2 - 1 - read-write - - - ALGOMODE0 - Algorithm mode - 3 - 3 - read-write - - - DATATYPE - Data type selection - 6 - 2 - read-write - - - KEYSIZE - Key size selection (AES mode only) - 8 - 2 - read-write - - - FFLUSH - FIFO flush - 14 - 1 - write-only - - - CRYPEN - Cryptographic processor enable - 15 - 1 - read-write - - - GCM_CCMPH - GCM_CCMPH - 16 - 2 - read-write - - - ALGOMODE3 - ALGOMODE - 19 - 1 - read-write - - - - - SR - SR - status register - 0x4 - 0x20 - read-only - 0x00000003 - - - BUSY - Busy bit - 4 - 1 - - - OFFU - Output FIFO full - 3 - 1 - - - OFNE - Output FIFO not empty - 2 - 1 - - - IFNF - Input FIFO not full - 1 - 1 - - - IFEM - Input FIFO empty - 0 - 1 - - - - - DIN - DIN - data input register - 0x8 - 0x20 - read-write - 0x00000000 - - - DATAIN - Data input - 0 - 32 - - - - - DOUT - DOUT - data output register - 0xC - 0x20 - read-only - 0x00000000 - - - DATAOUT - Data output - 0 - 32 - - - - - DMACR - DMACR - DMA control register - 0x10 - 0x20 - read-write - 0x00000000 - - - DOEN - DMA output enable - 1 - 1 - - - DIEN - DMA input enable - 0 - 1 - - - - - IMSCR - IMSCR - interrupt mask set/clear register - 0x14 - 0x20 - read-write - 0x00000000 - - - OUTIM - Output FIFO service interrupt mask - 1 - 1 - - - INIM - Input FIFO service interrupt mask - 0 - 1 - - - - - RISR - RISR - raw interrupt status register - 0x18 - 0x20 - read-only - 0x00000001 - - - OUTRIS - Output FIFO service raw interrupt status - 1 - 1 - - - INRIS - Input FIFO service raw interrupt status - 0 - 1 - - - - - MISR - MISR - masked interrupt status register - 0x1C - 0x20 - read-only - 0x00000000 - - - OUTMIS - Output FIFO service masked interrupt status - 1 - 1 - - - INMIS - Input FIFO service masked interrupt status - 0 - 1 - - - - - 4 - 0x8 - 0-3 - KEY%s - Cluster KEY%s, containing K?LR, K?RR - 0x20 - - KLR - K0LR - key registers - 0x0 - 0x20 - write-only - 0x00000000 - - - b2 - b224 - 0 - 32 - - - - - KRR - K0RR - key registers - 0x4 - 0x20 - write-only - 0x00000000 - - - b - b192 - 0 - 32 - - - - - - 2 - 0x8 - 0-1 - INIT%s - Cluster INIT%s, containing IV?LR, IV?RR - 0x40 - - IVLR - IV0LR - initialization vector registers - 0x0 - 0x20 - read-write - 0x00000000 - - - IV - IV31 - 0 - 32 - - - - - IVRR - IV0RR - initialization vector registers - 0x4 - 0x20 - read-write - 0x00000000 - - - IV - IV63 - 0 - 32 - - - - - - 8 - 0x4 - 0-7 - CSGCMCCM%sR - CSGCMCCM0R - context swap register - 0x50 - 0x20 - read-write - 0x00000000 - - - CSGCMCCM0R - CSGCMCCM0R - 0 - 32 - - - - - 8 - 0x4 - 0-7 - CSGCM%sR - CSGCM0R - context swap register - 0x70 - 0x20 - read-write - 0x00000000 - - - CSGCMR - CSGCM0R - 0 - 32 - - - - - - - DCMI - Digital camera interface - DCMI - 0x50050000 - - 0x0 - 0x400 - registers - - - DCMI - DCMI global interrupt - 78 - - - - CR - CR - control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - ENABLE - DCMI enable - 14 - 1 - - - EDM - Extended data mode - 10 - 2 - - - FCRC - Frame capture rate control - 8 - 2 - - - VSPOL - Vertical synchronization polarity - 7 - 1 - - - HSPOL - Horizontal synchronization polarity - 6 - 1 - - - PCKPOL - Pixel clock polarity - 5 - 1 - - - ESS - Embedded synchronization select - 4 - 1 - - - JPEG - JPEG format - 3 - 1 - - - CROP - Crop feature - 2 - 1 - - - CM - Capture mode - 1 - 1 - - - CAPTURE - Capture enable - 0 - 1 - - - - - SR - SR - status register - 0x4 - 0x20 - read-only - 0x00000000 - - - FNE - FIFO not empty - 2 - 1 - - - VSYNC - VSYNC - 1 - 1 - - - HSYNC - HSYNC - 0 - 1 - - - - - RIS - RIS - raw interrupt status register - 0x8 - 0x20 - read-only - 0x00000000 - - - LINE_RIS - Line raw interrupt status - 4 - 1 - - - VSYNC_RIS - VSYNC raw interrupt status - 3 - 1 - - - ERR_RIS - Synchronization error raw interrupt status - 2 - 1 - - - OVR_RIS - Overrun raw interrupt status - 1 - 1 - - - FRAME_RIS - Capture complete raw interrupt status - 0 - 1 - - - - - IER - IER - interrupt enable register - 0xC - 0x20 - read-write - 0x00000000 - - - LINE_IE - Line interrupt enable - 4 - 1 - - - VSYNC_IE - VSYNC interrupt enable - 3 - 1 - - - ERR_IE - Synchronization error interrupt enable - 2 - 1 - - - OVR_IE - Overrun interrupt enable - 1 - 1 - - - FRAME_IE - Capture complete interrupt enable - 0 - 1 - - - - - MIS - MIS - masked interrupt status register - 0x10 - 0x20 - read-only - 0x00000000 - - - LINE_MIS - Line masked interrupt status - 4 - 1 - - - VSYNC_MIS - VSYNC masked interrupt status - 3 - 1 - - - ERR_MIS - Synchronization error masked interrupt status - 2 - 1 - - - OVR_MIS - Overrun masked interrupt status - 1 - 1 - - - FRAME_MIS - Capture complete masked interrupt status - 0 - 1 - - - - - ICR - ICR - interrupt clear register - 0x14 - 0x20 - write-only - 0x00000000 - - - LINE_ISC - line interrupt status clear - 4 - 1 - - - VSYNC_ISC - Vertical synch interrupt status clear - 3 - 1 - - - ERR_ISC - Synchronization error interrupt status clear - 2 - 1 - - - OVR_ISC - Overrun interrupt status clear - 1 - 1 - - - FRAME_ISC - Capture complete interrupt status clear - 0 - 1 - - - - - ESCR - ESCR - embedded synchronization code register - 0x18 - 0x20 - read-write - 0x00000000 - - - FEC - Frame end delimiter code - 24 - 8 - - - LEC - Line end delimiter code - 16 - 8 - - - LSC - Line start delimiter code - 8 - 8 - - - FSC - Frame start delimiter code - 0 - 8 - - - - - ESUR - ESUR - embedded synchronization unmask register - 0x1C - 0x20 - read-write - 0x00000000 - - - FEU - Frame end delimiter unmask - 24 - 8 - - - LEU - Line end delimiter unmask - 16 - 8 - - - LSU - Line start delimiter unmask - 8 - 8 - - - FSU - Frame start delimiter unmask - 0 - 8 - - - - - CWSTRT - CWSTRT - crop window start - 0x20 - 0x20 - read-write - 0x00000000 - - - VST - Vertical start line count - 16 - 13 - - - HOFFCNT - Horizontal offset count - 0 - 14 - - - - - CWSIZE - CWSIZE - crop window size - 0x24 - 0x20 - read-write - 0x00000000 - - - VLINE - Vertical line count - 16 - 14 - - - CAPCNT - Capture count - 0 - 14 - - - - - DR - DR - data register - 0x28 - 0x20 - read-only - 0x00000000 - - - Byte3 - Data byte 3 - 24 - 8 - - - Byte2 - Data byte 2 - 16 - 8 - - - Byte1 - Data byte 1 - 8 - 8 - - - Byte0 - Data byte 0 - 0 - 8 - - - - - - - FMC - Flexible memory controller - FSMC - 0xA0000000 - - 0x0 - 0x1000 - registers - - - FMC - FMC global interrupt - 48 - - - - BCR1 - BCR1 - SRAM/NOR-Flash chip-select control register 1 - 0x0 - 0x20 - read-write - 0x000030D0 - - - CCLKEN - CCLKEN - 20 - 1 - - CCLKEN - read-write - - Disabled - The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set - 0 - - - Enabled - The FMC_CLK is only generated during the synchronous memory access (read/write transaction) - 1 - - - - - CBURSTRW - CBURSTRW - 19 - 1 - - CBURSTRW - read-write - - Disabled - Write operations are always performed in asynchronous mode - 0 - - - Enabled - Write operations are performed in synchronous mode - 1 - - - - - ASYNCWAIT - ASYNCWAIT - 15 - 1 - - ASYNCWAIT - read-write - - Disabled - Wait signal not used in asynchronous mode - 0 - - - Enabled - Wait signal used even in asynchronous mode - 1 - - - - - EXTMOD - EXTMOD - 14 - 1 - - EXTMOD - read-write - - Disabled - Values inside the FMC_BWTR are not taken into account - 0 - - - Enabled - Values inside the FMC_BWTR are taken into account - 1 - - - - - WAITEN - WAITEN - 13 - 1 - - WAITEN - read-write - - Disabled - Values inside the FMC_BWTR are taken into account - 0 - - - Enabled - NWAIT signal enabled - 1 - - - - - WREN - WREN - 12 - 1 - - WREN - read-write - - Disabled - Write operations disabled for the bank by the FMC - 0 - - - Enabled - Write operations enabled for the bank by the FMC - 1 - - - - - WAITCFG - WAITCFG - 11 - 1 - - WAITCFG - read-write - - BeforeWaitState - NWAIT signal is active one data cycle before wait state - 0 - - - DuringWaitState - NWAIT signal is active during wait state - 1 - - - - - WAITPOL - WAITPOL - 9 - 1 - - WAITPOL - read-write - - ActiveLow - NWAIT active low - 0 - - - ActiveHigh - NWAIT active high - 1 - - - - - BURSTEN - BURSTEN - 8 - 1 - - BURSTEN - read-write - - Disabled - Burst mode disabled - 0 - - - Enabled - Burst mode enabled - 1 - - - - - FACCEN - FACCEN - 6 - 1 - - FACCEN - read-write - - Disabled - Corresponding NOR Flash memory access is disabled - 0 - - - Enabled - Corresponding NOR Flash memory access is enabled - 1 - - - - - MWID - MWID - 4 - 2 - - MWID - read-write - - Bits8 - Memory data bus width 8 bits - 0 - - - Bits16 - Memory data bus width 16 bits - 1 - - - Bits32 - Memory data bus width 32 bits - 2 - - - - - MTYP - MTYP - 2 - 2 - - MTYP - read-write - - SRAM - SRAM memory type - 0 - - - PSRAM - PSRAM (CRAM) memory type - 1 - - - Flash - NOR Flash/OneNAND Flash - 2 - - - - - MUXEN - MUXEN - 1 - 1 - - MUXEN - read-write - - Disabled - Address/Data non-multiplexed - 0 - - - Enabled - Address/Data multiplexed on databus - 1 - - - - - MBKEN - MBKEN - 0 - 1 - - MBKEN - read-write - - Disabled - Corresponding memory bank is disabled - 0 - - - Enabled - Corresponding memory bank is enabled - 1 - - - - - WRAPMOD - WRAPMOD - 10 - 1 - - - WFDIS - Write FIFO disable - 21 - 1 - read-write - - WFDIS - read-write - - Enabled - Write FIFO enabled - 0 - - - Disabled - Write FIFO disabled - 1 - - - - - CPSIZE - CRAM page size - 16 - 3 - read-write - - CPSIZE - read-write - - NoBurstSplit - No burst split when crossing page boundary - 0 - - - Bytes128 - 128 bytes CRAM page size - 1 - - - Bytes256 - 256 bytes CRAM page size - 2 - - - Bytes512 - 512 bytes CRAM page size - 3 - - - Bytes1024 - 1024 bytes CRAM page size - 4 - - - - - - - 4 - 0x8 - 1-4 - BTR%s - BTR1 - SRAM/NOR-Flash chip-select timing register 1 - 0x4 - 0x20 - read-write - 0xFFFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - ACCMOD - read-write - - A - Access mode A - 0 - - - B - Access mode B - 1 - - - C - Access mode C - 2 - - - D - Access mode D - 3 - - - - - DATLAT - DATLAT - 24 - 4 - - - 0 - 15 - - - - - CLKDIV - CLKDIV - 20 - 4 - - - 1 - 15 - - - - - BUSTURN - BUSTURN - 16 - 4 - - - 0 - 15 - - - - - DATAST - DATAST - 8 - 8 - - - 1 - 255 - - - - - ADDHLD - ADDHLD - 4 - 4 - - - 1 - 15 - - - - - ADDSET - ADDSET - 0 - 4 - - - 0 - 15 - - - - - - - 3 - 0x8 - 2-4 - BCR%s - BCR2 - SRAM/NOR-Flash chip-select control register 2 - 0x8 - 0x20 - read-write - 0x000030D0 - - - CBURSTRW - CBURSTRW - 19 - 1 - - CBURSTRW - read-write - - Disabled - Write operations are always performed in asynchronous mode - 0 - - - Enabled - Write operations are performed in synchronous mode - 1 - - - - - ASYNCWAIT - ASYNCWAIT - 15 - 1 - - ASYNCWAIT - read-write - - Disabled - Wait signal not used in asynchronous mode - 0 - - - Enabled - Wait signal used even in asynchronous mode - 1 - - - - - EXTMOD - EXTMOD - 14 - 1 - - EXTMOD - read-write - - Disabled - Values inside the FMC_BWTR are not taken into account - 0 - - - Enabled - Values inside the FMC_BWTR are taken into account - 1 - - - - - WAITEN - WAITEN - 13 - 1 - - WAITEN - read-write - - Disabled - Values inside the FMC_BWTR are taken into account - 0 - - - Enabled - NWAIT signal enabled - 1 - - - - - WREN - WREN - 12 - 1 - - WREN - read-write - - Disabled - Write operations disabled for the bank by the FMC - 0 - - - Enabled - Write operations enabled for the bank by the FMC - 1 - - - - - WAITCFG - WAITCFG - 11 - 1 - - WAITCFG - read-write - - BeforeWaitState - NWAIT signal is active one data cycle before wait state - 0 - - - DuringWaitState - NWAIT signal is active during wait state - 1 - - - - - WRAPMOD - WRAPMOD - 10 - 1 - - - WAITPOL - WAITPOL - 9 - 1 - - WAITPOL - read-write - - ActiveLow - NWAIT active low - 0 - - - ActiveHigh - NWAIT active high - 1 - - - - - BURSTEN - BURSTEN - 8 - 1 - - BURSTEN - read-write - - Disabled - Burst mode disabled - 0 - - - Enabled - Burst mode enabled - 1 - - - - - FACCEN - FACCEN - 6 - 1 - - FACCEN - read-write - - Disabled - Corresponding NOR Flash memory access is disabled - 0 - - - Enabled - Corresponding NOR Flash memory access is enabled - 1 - - - - - MWID - MWID - 4 - 2 - - MWID - read-write - - Bits8 - Memory data bus width 8 bits - 0 - - - Bits16 - Memory data bus width 16 bits - 1 - - - Bits32 - Memory data bus width 32 bits - 2 - - - - - MTYP - MTYP - 2 - 2 - - MTYP - read-write - - SRAM - SRAM memory type - 0 - - - PSRAM - PSRAM (CRAM) memory type - 1 - - - Flash - NOR Flash/OneNAND Flash - 2 - - - - - MUXEN - MUXEN - 1 - 1 - - MUXEN - read-write - - Disabled - Address/Data non-multiplexed - 0 - - - Enabled - Address/Data multiplexed on databus - 1 - - - - - MBKEN - MBKEN - 0 - 1 - - MBKEN - read-write - - Disabled - Corresponding memory bank is disabled - 0 - - - Enabled - Corresponding memory bank is enabled - 1 - - - - - CPSIZE - CRAM page size - 16 - 3 - read-write - - CPSIZE - read-write - - NoBurstSplit - No burst split when crossing page boundary - 0 - - - Bytes128 - 128 bytes CRAM page size - 1 - - - Bytes256 - 256 bytes CRAM page size - 2 - - - Bytes512 - 512 bytes CRAM page size - 3 - - - Bytes1024 - 1024 bytes CRAM page size - 4 - - - - - - - PCR - PCR - PC Card/NAND Flash control register - 0x80 - 0x20 - read-write - 0x00000018 - - - ECCPS - ECCPS - 17 - 3 - - ECCPS - read-write - - Bytes256 - ECC page size 256 bytes - 0 - - - Bytes512 - ECC page size 512 bytes - 1 - - - Bytes1024 - ECC page size 1024 bytes - 2 - - - Bytes2048 - ECC page size 2048 bytes - 3 - - - Bytes4096 - ECC page size 4096 bytes - 4 - - - Bytes8192 - ECC page size 8192 bytes - 5 - - - - - TAR - TAR - 13 - 4 - - - 0 - 15 - - - - - TCLR - TCLR - 9 - 4 - - - 0 - 15 - - - - - ECCEN - ECCEN - 6 - 1 - - ECCEN - read-write - - Disabled - ECC logic is disabled and reset - 0 - - - Enabled - ECC logic is enabled - 1 - - - - - PWID - PWID - 4 - 2 - - PWID - read-write - - Bits8 - External memory device width 8 bits - 0 - - - Bits16 - External memory device width 16 bits - 1 - - - - - PTYP - PTYP - 3 - 1 - - PTYP - read-write - - NANDFlash - NAND Flash - 1 - - - - - PBKEN - PBKEN - 2 - 1 - - PBKEN - read-write - - Disabled - Corresponding memory bank is disabled - 0 - - - Enabled - Corresponding memory bank is enabled - 1 - - - - - PWAITEN - PWAITEN - 1 - 1 - - PWAITEN - read-write - - Disabled - Wait feature disabled - 0 - - - Enabled - Wait feature enabled - 1 - - - - - - - SR - SR - FIFO status and interrupt register - 0x84 - 0x20 - 0x00000040 - - - FEMPT - FEMPT - 6 - 1 - read-only - - FEMPT - read - - NotEmpty - FIFO not empty - 0 - - - Empty - FIFO empty - 1 - - - - - IFEN - IFEN - 5 - 1 - read-write - - IFEN - read-write - - Disabled - Interrupt falling edge detection request disabled - 0 - - - Enabled - Interrupt falling edge detection request enabled - 1 - - - - - ILEN - ILEN - 4 - 1 - read-write - - ILEN - read-write - - Disabled - Interrupt high-level detection request disabled - 0 - - - Enabled - Interrupt high-level detection request enabled - 1 - - - - - IREN - IREN - 3 - 1 - read-write - - IREN - read-write - - Disabled - Interrupt rising edge detection request disabled - 0 - - - Enabled - Interrupt rising edge detection request enabled - 1 - - - - - IFS - IFS - 2 - 1 - read-write - - IFS - read-write - - DidNotOccur - Interrupt falling edge did not occur - 0 - - - Occurred - Interrupt falling edge occurred - 1 - - - - - ILS - ILS - 1 - 1 - read-write - - ILS - read-write - - DidNotOccur - Interrupt high-level did not occur - 0 - - - Occurred - Interrupt high-level occurred - 1 - - - - - IRS - IRS - 0 - 1 - read-write - - IRS - read-write - - DidNotOccur - Interrupt rising edge did not occur - 0 - - - Occurred - Interrupt rising edge occurred - 1 - - - - - - - PMEM - PMEM - Common memory space timing register - 0x88 - 0x20 - read-write - 0xFCFCFCFC - - - MEMHIZ - MEMHIZx - 24 - 8 - - - 0 - 254 - - - - - MEMHOLD - MEMHOLDx - 16 - 8 - - - 1 - 254 - - - - - MEMWAIT - MEMWAITx - 8 - 8 - - - 1 - 254 - - - - - MEMSET - MEMSETx - 0 - 8 - - - 0 - 254 - - - - - - - PATT - PATT - Attribute memory space timing register - 0x8C - 0x20 - read-write - 0xFCFCFCFC - - - ATTHIZ - ATTHIZx - 24 - 8 - - - 0 - 254 - - - - - ATTHOLD - ATTHOLDx - 16 - 8 - - - 1 - 254 - - - - - ATTWAIT - ATTWAITx - 8 - 8 - - - 1 - 254 - - - - - ATTSET - ATTSETx - 0 - 8 - - - 0 - 254 - - - - - - - ECCR - ECCR - ECC result register - 0x94 - 0x20 - read-only - 0x00000000 - - - ECC - ECCx - 0 - 32 - - - 0 - 4294967295 - - - - - - - 4 - 0x8 - 1-4 - BWTR%s - BWTR1 - SRAM/NOR-Flash write timing registers 1 - 0x104 - 0x20 - read-write - 0x0FFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - ACCMOD - read-write - - A - Access mode A - 0 - - - B - Access mode B - 1 - - - C - Access mode C - 2 - - - D - Access mode D - 3 - - - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - DATAST - DATAST - 8 - 8 - - - 1 - 255 - - - - - ADDHLD - ADDHLD - 4 - 4 - - - 1 - 15 - - - - - ADDSET - ADDSET - 0 - 4 - - - 0 - 15 - - - - - BUSTURN - Bus turnaround phase duration - 16 - 4 - read-write - - - 0 - 15 - - - - - - - 2 - 0x4 - 1-2 - SDCR%s - SDCR1 - SDRAM Control Register 1 - 0x140 - 0x20 - read-write - 0x000002D0 - - - NC - Number of column address bits - 0 - 2 - - NC - read-write - - Bits8 - 8 bits - 0 - - - Bits9 - 9 bits - 1 - - - Bits10 - 10 bits - 2 - - - Bits11 - 11 bits - 3 - - - - - NR - Number of row address bits - 2 - 2 - - NR - read-write - - Bits11 - 11 bits - 0 - - - Bits12 - 12 bits - 1 - - - Bits13 - 13 bits - 2 - - - - - MWID - Memory data bus width - 4 - 2 - - MWID - read-write - - Bits8 - Memory data bus width 8 bits - 0 - - - Bits16 - Memory data bus width 16 bits - 1 - - - Bits32 - Memory data bus width 32 bits - 2 - - - - - NB - Number of internal banks - 6 - 1 - - NB - read-write - - NB2 - Two internal Banks - 0 - - - NB4 - Four internal Banks - 1 - - - - - CAS - CAS latency - 7 - 2 - - CAS - read-write - - Clocks1 - 1 cycle - 1 - - - Clocks2 - 2 cycles - 2 - - - Clocks3 - 3 cycles - 3 - - - - - WP - Write protection - 9 - 1 - - WP - read-write - - Disabled - Write accesses allowed - 0 - - - Enabled - Write accesses ignored - 1 - - - - - SDCLK - SDRAM clock configuration - 10 - 2 - - SDCLK - read-write - - Disabled - SDCLK clock disabled - 0 - - - Div2 - SDCLK period = 2 x HCLK period - 2 - - - Div3 - SDCLK period = 3 x HCLK period - 3 - - - - - RBURST - Burst read - 12 - 1 - - RBURST - read-write - - Disabled - Single read requests are not managed as bursts - 0 - - - Enabled - Single read requests are always managed as bursts - 1 - - - - - RPIPE - Read pipe - 13 - 2 - - RPIPE - read-write - - NoDelay - No clock cycle delay - 0 - - - Clocks1 - One clock cycle delay - 1 - - - Clocks2 - Two clock cycles delay - 2 - - - - - - - 2 - 0x4 - 1-2 - SDTR%s - SDTR1 - SDRAM Timing register 1 - 0x148 - 0x20 - read-write - 0x0FFFFFFF - - - TMRD - Load Mode Register to Active - 0 - 4 - - - 0 - 15 - - - - - TXSR - Exit self-refresh delay - 4 - 4 - - - 0 - 15 - - - - - TRAS - Self refresh time - 8 - 4 - - - 0 - 15 - - - - - TRC - Row cycle delay - 12 - 4 - - - 0 - 15 - - - - - TWR - Recovery delay - 16 - 4 - - - 0 - 15 - - - - - TRP - Row precharge delay - 20 - 4 - - - 0 - 15 - - - - - TRCD - Row to column delay - 24 - 4 - - - 0 - 15 - - - - - - - SDCMR - SDCMR - SDRAM Command Mode register - 0x150 - 0x20 - 0x00000000 - - - MODE - Command mode - 0 - 3 - write-only - - MODE - write - - Normal - Normal Mode - 0 - - - ClockConfigurationEnable - Clock Configuration Enable - 1 - - - PALL - PALL (All Bank Precharge) command - 2 - - - AutoRefreshCommand - Auto-refresh command - 3 - - - LoadModeRegister - Load Mode Resgier - 4 - - - SelfRefreshCommand - Self-refresh command - 5 - - - PowerDownCommand - Power-down command - 6 - - - - - CTB2 - Command target bank 2 - 3 - 1 - write-only - - CTB2 - write - - NotIssued - Command not issued to SDRAM Bank 1 - 0 - - - Issued - Command issued to SDRAM Bank 1 - 1 - - - - - CTB1 - Command target bank 1 - 4 - 1 - write-only - - - - NRFS - Number of Auto-refresh - 5 - 4 - read-write - - - 0 - 15 - - - - - MRD - Mode Register definition - 9 - 13 - read-write - - - 0 - 8191 - - - - - - - SDRTR - SDRTR - SDRAM Refresh Timer register - 0x154 - 0x20 - 0x00000000 - - - CRE - Clear Refresh error flag - 0 - 1 - write-only - - CRE - write - - Clear - Refresh Error Flag is cleared - 1 - - - - - COUNT - Refresh Timer Count - 1 - 13 - read-write - - - 0 - 8191 - - - - - REIE - RES Interrupt Enable - 14 - 1 - read-write - - REIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is generated if RE = 1 - 1 - - - - - - - SDSR - SDSR - SDRAM Status register - 0x158 - 0x20 - read-only - 0x00000000 - - - RE - Refresh error flag - 0 - 1 - - RE - read - - NoError - No refresh error has been detected - 0 - - - Error - A refresh error has been detected - 1 - - - - - MODES1 - Status Mode for Bank 1 - 1 - 2 - - MODES1 - read - - Normal - Normal Mode - 0 - - - SelfRefresh - Self-refresh mode - 1 - - - PowerDown - Power-down mode - 2 - - - - - MODES2 - Status Mode for Bank 2 - 3 - 2 - - - - BUSY - Busy status - 5 - 1 - - BUSY - read - - NotBusy - SDRAM Controller is ready to accept a new request - 0 - - - Busy - SDRAM Controller is not ready to accept a new request - 1 - - - - - - - - - DBGMCU - Debug support - DBG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - IDCODE - 0x0 - 0x20 - read-only - 0x10006411 - - - DEV_ID - DEV_ID - 0 - 12 - - - REV_ID - REV_ID - 16 - 16 - - - - - CR - CR - Control Register - 0x4 - 0x20 - read-write - 0x00000000 - - - DBG_SLEEP - DBG_SLEEP - 0 - 1 - - - DBG_STOP - DBG_STOP - 1 - 1 - - - DBG_STANDBY - DBG_STANDBY - 2 - 1 - - - TRACE_IOEN - TRACE_IOEN - 5 - 1 - - - TRACE_MODE - TRACE_MODE - 6 - 2 - - - - - APB1_FZ - APB1_FZ - Debug MCU APB1 Freeze registe - 0x8 - 0x20 - read-write - 0x00000000 - - - DBG_TIM2_STOP - DBG_TIM2_STOP - 0 - 1 - - - DBG_TIM3_STOP - DBG_TIM3 _STOP - 1 - 1 - - - DBG_TIM4_STOP - DBG_TIM4_STOP - 2 - 1 - - - DBG_TIM5_STOP - DBG_TIM5_STOP - 3 - 1 - - - DBG_TIM6_STOP - DBG_TIM6_STOP - 4 - 1 - - - DBG_TIM7_STOP - DBG_TIM7_STOP - 5 - 1 - - - DBG_TIM12_STOP - DBG_TIM12_STOP - 6 - 1 - - - DBG_TIM13_STOP - DBG_TIM13_STOP - 7 - 1 - - - DBG_TIM14_STOP - DBG_TIM14_STOP - 8 - 1 - - - DBG_WWDG_STOP - DBG_WWDG_STOP - 11 - 1 - - - DBG_IWDG_STOP - DBG_IWDEG_STOP - 12 - 1 - - - DBG_J2C1_SMBUS_TIMEOUT - DBG_J2C1_SMBUS_TIMEOUT - 21 - 1 - - - DBG_J2C2_SMBUS_TIMEOUT - DBG_J2C2_SMBUS_TIMEOUT - 22 - 1 - - - DBG_J2C3SMBUS_TIMEOUT - DBG_J2C3SMBUS_TIMEOUT - 23 - 1 - - - DBG_CAN1_STOP - DBG_CAN1_STOP - 25 - 1 - - - DBG_CAN2_STOP - DBG_CAN2_STOP - 26 - 1 - - - - - APB2_FZ - APB2_FZ - Debug MCU APB2 Freeze registe - 0xC - 0x20 - read-write - 0x00000000 - - - DBG_TIM1_STOP - TIM1 counter stopped when core is halted - 0 - 1 - - - DBG_TIM8_STOP - TIM8 counter stopped when core is halted - 1 - 1 - - - DBG_TIM9_STOP - TIM9 counter stopped when core is halted - 16 - 1 - - - DBG_TIM10_STOP - TIM10 counter stopped when core is halted - 17 - 1 - - - DBG_TIM11_STOP - TIM11 counter stopped when core is halted - 18 - 1 - - - - - - - DMA2 - DMA controller - DMA - 0x40026400 - - 0x0 - 0x400 - registers - - - DMA2_Stream0 - DMA2 Stream0 global interrupt - 56 - - - DMA2_Stream1 - DMA2 Stream1 global interrupt - 57 - - - DMA2_Stream2 - DMA2 Stream2 global interrupt - 58 - - - DMA2_Stream3 - DMA2 Stream3 global interrupt - 59 - - - DMA2_Stream4 - DMA2 Stream4 global interrupt - 60 - - - DMA2_Stream5 - DMA2 Stream5 global interrupt - 68 - - - DMA2_Stream6 - DMA2 Stream6 global interrupt - 69 - - - DMA2_Stream7 - DMA2 Stream7 global interrupt - 70 - - - - LISR - LISR - low interrupt status register - 0x0 - 0x20 - read-only - 0x00000000 - - - TCIF3 - Stream x transfer complete interrupt flag (x = 3..0) - 27 - 1 - - - - HTIF3 - Stream x half transfer interrupt flag (x=3..0) - 26 - 1 - - - - TEIF3 - Stream x transfer error interrupt flag (x=3..0) - 25 - 1 - - - - DMEIF3 - Stream x direct mode error interrupt flag (x=3..0) - 24 - 1 - - - - FEIF3 - Stream x FIFO error interrupt flag (x=3..0) - 22 - 1 - - - - TCIF2 - Stream x transfer complete interrupt flag (x = 3..0) - 21 - 1 - - - - HTIF2 - Stream x half transfer interrupt flag (x=3..0) - 20 - 1 - - - - TEIF2 - Stream x transfer error interrupt flag (x=3..0) - 19 - 1 - - - - DMEIF2 - Stream x direct mode error interrupt flag (x=3..0) - 18 - 1 - - - - FEIF2 - Stream x FIFO error interrupt flag (x=3..0) - 16 - 1 - - - - TCIF1 - Stream x transfer complete interrupt flag (x = 3..0) - 11 - 1 - - - - HTIF1 - Stream x half transfer interrupt flag (x=3..0) - 10 - 1 - - - - TEIF1 - Stream x transfer error interrupt flag (x=3..0) - 9 - 1 - - - - DMEIF1 - Stream x direct mode error interrupt flag (x=3..0) - 8 - 1 - - - - FEIF1 - Stream x FIFO error interrupt flag (x=3..0) - 6 - 1 - - - - TCIF0 - Stream x transfer complete interrupt flag (x = 3..0) - 5 - 1 - - TCIF0 - read - - NotComplete - No transfer complete event on stream x - 0 - - - Complete - A transfer complete event occurred on stream x - 1 - - - - - HTIF0 - Stream x half transfer interrupt flag (x=3..0) - 4 - 1 - - HTIF0 - read - - NotHalf - No half transfer event on stream x - 0 - - - Half - A half transfer event occurred on stream x - 1 - - - - - TEIF0 - Stream x transfer error interrupt flag (x=3..0) - 3 - 1 - - TEIF0 - read - - NoError - No transfer error on stream x - 0 - - - Error - A transfer error occurred on stream x - 1 - - - - - DMEIF0 - Stream x direct mode error interrupt flag (x=3..0) - 2 - 1 - - DMEIF0 - read - - NoError - No Direct Mode error on stream x - 0 - - - Error - A Direct Mode error occurred on stream x - 1 - - - - - FEIF0 - Stream x FIFO error interrupt flag (x=3..0) - 0 - 1 - - FEIF0 - read - - NoError - No FIFO error event on stream x - 0 - - - Error - A FIFO error event occurred on stream x - 1 - - - - - - - HISR - HISR - high interrupt status register - 0x4 - 0x20 - read-only - 0x00000000 - - - TCIF7 - Stream x transfer complete interrupt flag (x=7..4) - 27 - 1 - - - - HTIF7 - Stream x half transfer interrupt flag (x=7..4) - 26 - 1 - - - - TEIF7 - Stream x transfer error interrupt flag (x=7..4) - 25 - 1 - - - - DMEIF7 - Stream x direct mode error interrupt flag (x=7..4) - 24 - 1 - - - - FEIF7 - Stream x FIFO error interrupt flag (x=7..4) - 22 - 1 - - - - TCIF6 - Stream x transfer complete interrupt flag (x=7..4) - 21 - 1 - - - - HTIF6 - Stream x half transfer interrupt flag (x=7..4) - 20 - 1 - - - - TEIF6 - Stream x transfer error interrupt flag (x=7..4) - 19 - 1 - - - - DMEIF6 - Stream x direct mode error interrupt flag (x=7..4) - 18 - 1 - - - - FEIF6 - Stream x FIFO error interrupt flag (x=7..4) - 16 - 1 - - - - TCIF5 - Stream x transfer complete interrupt flag (x=7..4) - 11 - 1 - - - - HTIF5 - Stream x half transfer interrupt flag (x=7..4) - 10 - 1 - - - - TEIF5 - Stream x transfer error interrupt flag (x=7..4) - 9 - 1 - - - - DMEIF5 - Stream x direct mode error interrupt flag (x=7..4) - 8 - 1 - - - - FEIF5 - Stream x FIFO error interrupt flag (x=7..4) - 6 - 1 - - - - TCIF4 - Stream x transfer complete interrupt flag (x=7..4) - 5 - 1 - - TCIF4 - read - - NotComplete - No transfer complete event on stream x - 0 - - - Complete - A transfer complete event occurred on stream x - 1 - - - - - HTIF4 - Stream x half transfer interrupt flag (x=7..4) - 4 - 1 - - HTIF4 - read - - NotHalf - No half transfer event on stream x - 0 - - - Half - A half transfer event occurred on stream x - 1 - - - - - TEIF4 - Stream x transfer error interrupt flag (x=7..4) - 3 - 1 - - TEIF4 - read - - NoError - No transfer error on stream x - 0 - - - Error - A transfer error occurred on stream x - 1 - - - - - DMEIF4 - Stream x direct mode error interrupt flag (x=7..4) - 2 - 1 - - DMEIF4 - read - - NoError - No Direct Mode error on stream x - 0 - - - Error - A Direct Mode error occurred on stream x - 1 - - - - - FEIF4 - Stream x FIFO error interrupt flag (x=7..4) - 0 - 1 - - FEIF4 - read - - NoError - No FIFO error event on stream x - 0 - - - Error - A FIFO error event occurred on stream x - 1 - - - - - - - LIFCR - LIFCR - low interrupt flag clear register - 0x8 - 0x20 - write-only - 0x00000000 - - - CTCIF3 - Stream x clear transfer complete interrupt flag (x = 3..0) - 27 - 1 - - - - CHTIF3 - Stream x clear half transfer interrupt flag (x = 3..0) - 26 - 1 - - - - CTEIF3 - Stream x clear transfer error interrupt flag (x = 3..0) - 25 - 1 - - - - CDMEIF3 - Stream x clear direct mode error interrupt flag (x = 3..0) - 24 - 1 - - - - CFEIF3 - Stream x clear FIFO error interrupt flag (x = 3..0) - 22 - 1 - - - - CTCIF2 - Stream x clear transfer complete interrupt flag (x = 3..0) - 21 - 1 - - - - CHTIF2 - Stream x clear half transfer interrupt flag (x = 3..0) - 20 - 1 - - - - CTEIF2 - Stream x clear transfer error interrupt flag (x = 3..0) - 19 - 1 - - - - CDMEIF2 - Stream x clear direct mode error interrupt flag (x = 3..0) - 18 - 1 - - - - CFEIF2 - Stream x clear FIFO error interrupt flag (x = 3..0) - 16 - 1 - - - - CTCIF1 - Stream x clear transfer complete interrupt flag (x = 3..0) - 11 - 1 - - - - CHTIF1 - Stream x clear half transfer interrupt flag (x = 3..0) - 10 - 1 - - - - CTEIF1 - Stream x clear transfer error interrupt flag (x = 3..0) - 9 - 1 - - - - CDMEIF1 - Stream x clear direct mode error interrupt flag (x = 3..0) - 8 - 1 - - - - CFEIF1 - Stream x clear FIFO error interrupt flag (x = 3..0) - 6 - 1 - - - - CTCIF0 - Stream x clear transfer complete interrupt flag (x = 3..0) - 5 - 1 - - CTCIF0 - write - - Clear - Clear the corresponding TCIFx flag - 1 - - - - - CHTIF0 - Stream x clear half transfer interrupt flag (x = 3..0) - 4 - 1 - - CHTIF0 - write - - Clear - Clear the corresponding HTIFx flag - 1 - - - - - CTEIF0 - Stream x clear transfer error interrupt flag (x = 3..0) - 3 - 1 - - CTEIF0 - write - - Clear - Clear the corresponding TEIFx flag - 1 - - - - - CDMEIF0 - Stream x clear direct mode error interrupt flag (x = 3..0) - 2 - 1 - - CDMEIF0 - write - - Clear - Clear the corresponding DMEIFx flag - 1 - - - - - CFEIF0 - Stream x clear FIFO error interrupt flag (x = 3..0) - 0 - 1 - - CFEIF0 - write - - Clear - Clear the corresponding CFEIFx flag - 1 - - - - - - - HIFCR - HIFCR - high interrupt flag clear register - 0xC - 0x20 - write-only - 0x00000000 - - - CTCIF7 - Stream x clear transfer complete interrupt flag (x = 7..4) - 27 - 1 - - - - CHTIF7 - Stream x clear half transfer interrupt flag (x = 7..4) - 26 - 1 - - - - CTEIF7 - Stream x clear transfer error interrupt flag (x = 7..4) - 25 - 1 - - - - CDMEIF7 - Stream x clear direct mode error interrupt flag (x = 7..4) - 24 - 1 - - - - CFEIF7 - Stream x clear FIFO error interrupt flag (x = 7..4) - 22 - 1 - - - - CTCIF6 - Stream x clear transfer complete interrupt flag (x = 7..4) - 21 - 1 - - - - CHTIF6 - Stream x clear half transfer interrupt flag (x = 7..4) - 20 - 1 - - - - CTEIF6 - Stream x clear transfer error interrupt flag (x = 7..4) - 19 - 1 - - - - CDMEIF6 - Stream x clear direct mode error interrupt flag (x = 7..4) - 18 - 1 - - - - CFEIF6 - Stream x clear FIFO error interrupt flag (x = 7..4) - 16 - 1 - - - - CTCIF5 - Stream x clear transfer complete interrupt flag (x = 7..4) - 11 - 1 - - - - CHTIF5 - Stream x clear half transfer interrupt flag (x = 7..4) - 10 - 1 - - - - CTEIF5 - Stream x clear transfer error interrupt flag (x = 7..4) - 9 - 1 - - - - CDMEIF5 - Stream x clear direct mode error interrupt flag (x = 7..4) - 8 - 1 - - - - CFEIF5 - Stream x clear FIFO error interrupt flag (x = 7..4) - 6 - 1 - - - - CTCIF4 - Stream x clear transfer complete interrupt flag (x = 7..4) - 5 - 1 - - CTCIF4 - write - - Clear - Clear the corresponding TCIFx flag - 1 - - - - - CHTIF4 - Stream x clear half transfer interrupt flag (x = 7..4) - 4 - 1 - - CHTIF4 - write - - Clear - Clear the corresponding HTIFx flag - 1 - - - - - CTEIF4 - Stream x clear transfer error interrupt flag (x = 7..4) - 3 - 1 - - CTEIF4 - write - - Clear - Clear the corresponding TEIFx flag - 1 - - - - - CDMEIF4 - Stream x clear direct mode error interrupt flag (x = 7..4) - 2 - 1 - - CDMEIF4 - write - - Clear - Clear the corresponding DMEIFx flag - 1 - - - - - CFEIF4 - Stream x clear FIFO error interrupt flag (x = 7..4) - 0 - 1 - - CFEIF4 - write - - Clear - Clear the corresponding CFEIFx flag - 1 - - - - - - - 8 - 0x18 - 0-7 - ST%s - Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers - 0x10 - - CR - S0CR - stream x configuration register - 0x0 - 0x20 - read-write - 0x00000000 - - - CHSEL - Channel selection - 25 - 3 - - - 0 - 7 - - - - - MBURST - Memory burst transfer configuration - 23 - 2 - - - - PBURST - Peripheral burst transfer configuration - 21 - 2 - - PBURST - read-write - - Single - Single transfer - 0 - - - INCR4 - Incremental burst of 4 beats - 1 - - - INCR8 - Incremental burst of 8 beats - 2 - - - INCR16 - Incremental burst of 16 beats - 3 - - - - - CT - Current target (only in double buffer mode) - 19 - 1 - - CT - read-write - - Memory0 - The current target memory is Memory 0 - 0 - - - Memory1 - The current target memory is Memory 1 - 1 - - - - - DBM - Double buffer mode - 18 - 1 - - DBM - read-write - - Disabled - No buffer switching at the end of transfer - 0 - - - Enabled - Memory target switched at the end of the DMA transfer - 1 - - - - - PL - Priority level - 16 - 2 - - PL - read-write - - Low - Low - 0 - - - Medium - Medium - 1 - - - High - High - 2 - - - VeryHigh - Very high - 3 - - - - - PINCOS - Peripheral increment offset size - 15 - 1 - - PINCOS - read-write - - PSIZE - The offset size for the peripheral address calculation is linked to the PSIZE - 0 - - - Fixed4 - The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) - 1 - - - - - MSIZE - Memory data size - 13 - 2 - - - - PSIZE - Peripheral data size - 11 - 2 - - PSIZE - read-write - - Bits8 - Byte (8-bit) - 0 - - - Bits16 - Half-word (16-bit) - 1 - - - Bits32 - Word (32-bit) - 2 - - - - - MINC - Memory increment mode - 10 - 1 - - - - PINC - Peripheral increment mode - 9 - 1 - - PINC - read-write - - Fixed - Address pointer is fixed - 0 - - - Incremented - Address pointer is incremented after each data transfer - 1 - - - - - CIRC - Circular mode - 8 - 1 - - CIRC - read-write - - Disabled - Circular mode disabled - 0 - - - Enabled - Circular mode enabled - 1 - - - - - DIR - Data transfer direction - 6 - 2 - - DIR - read-write - - PeripheralToMemory - Peripheral-to-memory - 0 - - - MemoryToPeripheral - Memory-to-peripheral - 1 - - - MemoryToMemory - Memory-to-memory - 2 - - - - - PFCTRL - Peripheral flow controller - 5 - 1 - - PFCTRL - read-write - - DMA - The DMA is the flow controller - 0 - - - Peripheral - The peripheral is the flow controller - 1 - - - - - TCIE - Transfer complete interrupt enable - 4 - 1 - - TCIE - read-write - - Disabled - TC interrupt disabled - 0 - - - Enabled - TC interrupt enabled - 1 - - - - - HTIE - Half transfer interrupt enable - 3 - 1 - - HTIE - read-write - - Disabled - HT interrupt disabled - 0 - - - Enabled - HT interrupt enabled - 1 - - - - - TEIE - Transfer error interrupt enable - 2 - 1 - - TEIE - read-write - - Disabled - TE interrupt disabled - 0 - - - Enabled - TE interrupt enabled - 1 - - - - - DMEIE - Direct mode error interrupt enable - 1 - 1 - - DMEIE - read-write - - Disabled - DME interrupt disabled - 0 - - - Enabled - DME interrupt enabled - 1 - - - - - EN - Stream enable / flag stream ready when read low - 0 - 1 - - EN - read-write - - Disabled - Stream disabled - 0 - - - Enabled - Stream enabled - 1 - - - - - - - NDTR - S0NDTR - stream x number of data register - 0x4 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data items to transfer - 0 - 16 - - - 0 - 65535 - - - - - - - PAR - S0PAR - stream x peripheral address register - 0x8 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - M0AR - S0M0AR - stream x memory 0 address register - 0xC - 0x20 - read-write - 0x00000000 - - - M0A - Memory 0 address - 0 - 32 - - - - - M1AR - S0M1AR - stream x memory 1 address register - 0x10 - 0x20 - read-write - 0x00000000 - - - M1A - Memory 1 address (used in case of Double buffer mode) - 0 - 32 - - - - - FCR - S0FCR - stream x FIFO control register - 0x14 - 0x20 - 0x00000021 - - - FEIE - FIFO error interrupt enable - 7 - 1 - read-write - - FEIE - read-write - - Disabled - FE interrupt disabled - 0 - - - Enabled - FE interrupt enabled - 1 - - - - - FS - FIFO status - 3 - 3 - read-only - - FS - read - - Quarter1 - 0 < fifo_level < 1/4 - 0 - - - Quarter2 - 1/4 <= fifo_level < 1/2 - 1 - - - Quarter3 - 1/2 <= fifo_level < 3/4 - 2 - - - Quarter4 - 3/4 <= fifo_level < full - 3 - - - Empty - FIFO is empty - 4 - - - Full - FIFO is full - 5 - - - - - DMDIS - Direct mode disable - 2 - 1 - read-write - - DMDIS - read-write - - Enabled - Direct mode is enabled - 0 - - - Disabled - Direct mode is disabled - 1 - - - - - FTH - FIFO threshold selection - 0 - 2 - read-write - - FTH - read-write - - Quarter - 1/4 full FIFO - 0 - - - Half - 1/2 full FIFO - 1 - - - ThreeQuarters - 3/4 full FIFO - 2 - - - Full - Full FIFO - 3 - - - - - - - - - - DMA1 - 0x40026000 - - DMA1_Stream0 - DMA1 Stream0 global interrupt - 11 - - - DMA1_Stream1 - DMA1 Stream1 global interrupt - 12 - - - DMA1_Stream2 - DMA1 Stream2 global interrupt - 13 - - - DMA1_Stream3 - DMA1 Stream3 global interrupt - 14 - - - DMA1_Stream4 - DMA1 Stream4 global interrupt - 15 - - - DMA1_Stream5 - DMA1 Stream5 global interrupt - 16 - - - DMA1_Stream6 - DMA1 Stream6 global interrupt - 17 - - - DMA1_Stream7 - DMA1 Stream7 global interrupt - 47 - - - - RCC - Reset and clock control - RCC - 0x40023800 - - 0x0 - 0x400 - registers - - - RCC - RCC global interrupt - 5 - - - - CR - CR - clock control register - 0x0 - 0x20 - 0x00000083 - - - PLLI2SRDY - PLLI2S clock ready flag - 27 - 1 - read-only - - - - PLLI2SON - PLLI2S enable - 26 - 1 - read-write - - - - PLLRDY - Main PLL (PLL) clock ready flag - 25 - 1 - read-only - - - - PLLON - Main PLL (PLL) enable - 24 - 1 - read-write - - - - CSSON - Clock security system enable - 19 - 1 - read-write - - CSSON - read-write - - Off - Clock security system disabled (clock detector OFF) - 0 - - - On - Clock security system enable (clock detector ON if the HSE is ready, OFF if not) - 1 - - - - - HSEBYP - HSE clock bypass - 18 - 1 - read-write - - HSEBYP - read-write - - NotBypassed - HSE crystal oscillator not bypassed - 0 - - - Bypassed - HSE crystal oscillator bypassed with external clock - 1 - - - - - HSERDY - HSE clock ready flag - 17 - 1 - read-only - - - - HSEON - HSE clock enable - 16 - 1 - read-write - - - - HSICAL - Internal high-speed clock calibration - 8 - 8 - read-only - - - 0 - 255 - - - - - HSITRIM - Internal high-speed clock trimming - 3 - 5 - read-write - - - 0 - 31 - - - - - HSIRDY - Internal high-speed clock ready flag - 1 - 1 - read-only - - HSIRDYR - read - - NotReady - Clock not ready - 0 - - - Ready - Clock ready - 1 - - - - - HSION - Internal high-speed clock enable - 0 - 1 - read-write - - HSION - read-write - - Off - Clock Off - 0 - - - On - Clock On - 1 - - - - - PLLSAIRDY - PLLSAI clock ready flag - 29 - 1 - read-only - - - - PLLSAION - PLLSAI enable - 28 - 1 - read-write - - - - - - PLLCFGR - PLLCFGR - PLL configuration register - 0x4 - 0x20 - read-write - 0x24003010 - - - PLLSRC - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - 22 - 1 - - PLLSRC - read-write - - HSI - HSI clock selected as PLL and PLLI2S clock entry - 0 - - - HSE - HSE oscillator clock selected as PLL and PLLI2S clock entry - 1 - - - - - PLLM - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - 0 - 6 - - - 2 - 63 - - - - - PLLN - Main PLL (PLL) multiplication factor for VCO - 6 - 9 - - - 50 - 432 - - - - - PLLP - Main PLL (PLL) division factor for main system clock - 16 - 2 - - PLLP - read-write - - Div2 - PLLP=2 - 0 - - - Div4 - PLLP=4 - 1 - - - Div6 - PLLP=6 - 2 - - - Div8 - PLLP=8 - 3 - - - - - PLLQ - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - 24 - 4 - - - 2 - 15 - - - - - - - CFGR - CFGR - clock configuration register - 0x8 - 0x20 - 0x00000000 - - - MCO2 - Microcontroller clock output 2 - 30 - 2 - read-write - - MCO2 - read-write - - SYSCLK - System clock (SYSCLK) selected - 0 - - - PLLI2S - PLLI2S clock selected - 1 - - - HSE - HSE oscillator clock selected - 2 - - - PLL - PLL clock selected - 3 - - - - - MCO2PRE - MCO2 prescaler - 27 - 3 - read-write - - - - MCO1PRE - MCO1 prescaler - 24 - 3 - read-write - - MCO1PRE - read-write - - Div1 - No division - 0 - - - Div2 - Division by 2 - 4 - - - Div3 - Division by 3 - 5 - - - Div4 - Division by 4 - 6 - - - Div5 - Division by 5 - 7 - - - - - I2SSRC - I2S clock selection - 23 - 1 - read-write - - I2SSRC - read-write - - PLLI2S - PLLI2S clock used as I2S clock source - 0 - - - CKIN - External clock mapped on the I2S_CKIN pin used as I2S clock source - 1 - - - - - MCO1 - Microcontroller clock output 1 - 21 - 2 - read-write - - MCO1 - read-write - - HSI - HSI clock selected - 0 - - - LSE - LSE oscillator selected - 1 - - - HSE - HSE oscillator clock selected - 2 - - - PLL - PLL clock selected - 3 - - - - - RTCPRE - HSE division factor for RTC clock - 16 - 5 - read-write - - - 0 - 31 - - - - - PPRE2 - APB high-speed prescaler (APB2) - 13 - 3 - read-write - - - - PPRE1 - APB Low speed prescaler (APB1) - 10 - 3 - read-write - - PPRE1 - read-write - - Div1 - HCLK not divided - 0 - - - Div2 - HCLK divided by 2 - 4 - - - Div4 - HCLK divided by 4 - 5 - - - Div8 - HCLK divided by 8 - 6 - - - Div16 - HCLK divided by 16 - 7 - - - - - HPRE - AHB prescaler - 4 - 4 - read-write - - HPRE - read-write - - Div1 - SYSCLK not divided - 0 - - - Div2 - SYSCLK divided by 2 - 8 - - - Div4 - SYSCLK divided by 4 - 9 - - - Div8 - SYSCLK divided by 8 - 10 - - - Div16 - SYSCLK divided by 16 - 11 - - - Div64 - SYSCLK divided by 64 - 12 - - - Div128 - SYSCLK divided by 128 - 13 - - - Div256 - SYSCLK divided by 256 - 14 - - - Div512 - SYSCLK divided by 512 - 15 - - - - - SW - System clock switch - 0 - 2 - - SW - read-write - - HSI - HSI selected as system clock - 0 - - - HSE - HSE selected as system clock - 1 - - - PLL - PLL selected as system clock - 2 - - - - - SWS - System clock switch status - 2 - 2 - - SWSR - read - - HSI - HSI oscillator used as system clock - 0 - - - HSE - HSE oscillator used as system clock - 1 - - - PLL - PLL used as system clock - 2 - - - - - - - CIR - CIR - clock interrupt register - 0xC - 0x20 - 0x00000000 - - - CSSC - Clock security system interrupt clear - 23 - 1 - write-only - - CSSCW - write - - Clear - Clear CSSF flag - 1 - - - - - PLLSAIRDYC - PLLSAI Ready Interrupt Clear - 22 - 1 - write-only - - - - PLLI2SRDYC - PLLI2S ready interrupt clear - 21 - 1 - write-only - - - - PLLRDYC - Main PLL(PLL) ready interrupt clear - 20 - 1 - write-only - - - - HSERDYC - HSE ready interrupt clear - 19 - 1 - write-only - - - - HSIRDYC - HSI ready interrupt clear - 18 - 1 - write-only - - - - LSERDYC - LSE ready interrupt clear - 17 - 1 - write-only - - - - LSIRDYC - LSI ready interrupt clear - 16 - 1 - write-only - - LSIRDYCW - write - - Clear - Clear interrupt flag - 1 - - - - - PLLSAIRDYIE - PLLSAI Ready Interrupt Enable - 14 - 1 - read-write - - - - PLLI2SRDYIE - PLLI2S ready interrupt enable - 13 - 1 - read-write - - - - PLLRDYIE - Main PLL (PLL) ready interrupt enable - 12 - 1 - read-write - - - - HSERDYIE - HSE ready interrupt enable - 11 - 1 - read-write - - - - HSIRDYIE - HSI ready interrupt enable - 10 - 1 - read-write - - - - LSERDYIE - LSE ready interrupt enable - 9 - 1 - read-write - - - - LSIRDYIE - LSI ready interrupt enable - 8 - 1 - read-write - - LSIRDYIE - read-write - - Disabled - Interrupt disabled - 0 - - - Enabled - Interrupt enabled - 1 - - - - - CSSF - Clock security system interrupt flag - 7 - 1 - read-only - - CSSFR - read - - NotInterrupted - No clock security interrupt caused by HSE clock failure - 0 - - - Interrupted - Clock security interrupt caused by HSE clock failure - 1 - - - - - PLLSAIRDYF - PLLSAI ready interrupt flag - 6 - 1 - read-only - - - - PLLI2SRDYF - PLLI2S ready interrupt flag - 5 - 1 - read-only - - - - PLLRDYF - Main PLL (PLL) ready interrupt flag - 4 - 1 - read-only - - - - HSERDYF - HSE ready interrupt flag - 3 - 1 - read-only - - - - HSIRDYF - HSI ready interrupt flag - 2 - 1 - read-only - - - - LSERDYF - LSE ready interrupt flag - 1 - 1 - read-only - - - - LSIRDYF - LSI ready interrupt flag - 0 - 1 - read-only - - LSIRDYFR - read - - NotInterrupted - No clock ready interrupt - 0 - - - Interrupted - Clock ready interrupt - 1 - - - - - - - AHB1RSTR - AHB1RSTR - AHB1 peripheral reset register - 0x10 - 0x20 - read-write - 0x00000000 - - - OTGHSRST - USB OTG HS module reset - 29 - 1 - - - - ETHMACRST - Ethernet MAC reset - 25 - 1 - - - - DMA2DRST - DMA2D reset - 23 - 1 - - - - DMA2RST - DMA2 reset - 22 - 1 - - - - DMA1RST - DMA2 reset - 21 - 1 - - - - CRCRST - CRC reset - 12 - 1 - - - - GPIOKRST - IO port K reset - 10 - 1 - - - - GPIOJRST - IO port J reset - 9 - 1 - - - - GPIOIRST - IO port I reset - 8 - 1 - - - - GPIOHRST - IO port H reset - 7 - 1 - - - - GPIOGRST - IO port G reset - 6 - 1 - - - - GPIOFRST - IO port F reset - 5 - 1 - - - - GPIOERST - IO port E reset - 4 - 1 - - - - GPIODRST - IO port D reset - 3 - 1 - - - - GPIOCRST - IO port C reset - 2 - 1 - - - - GPIOBRST - IO port B reset - 1 - 1 - - - - GPIOARST - IO port A reset - 0 - 1 - - GPIOARST - read-write - - Reset - Reset the selected module - 1 - - - - - - - AHB2RSTR - AHB2RSTR - AHB2 peripheral reset register - 0x14 - 0x20 - read-write - 0x00000000 - - - OTGFSRST - USB OTG FS module reset - 7 - 1 - - - - RNGRST - Random number generator module reset - 6 - 1 - - - - HSAHRST - Hash module reset - 5 - 1 - - - - CRYPRST - Cryptographic module reset - 4 - 1 - - - - DCMIRST - Camera interface reset - 0 - 1 - - DCMIRST - read-write - - Reset - Reset the selected module - 1 - - - - - - - AHB3RSTR - AHB3RSTR - AHB3 peripheral reset register - 0x18 - 0x20 - read-write - 0x00000000 - - - FMCRST - Flexible memory controller module reset - 0 - 1 - - FMCRST - read-write - - Reset - Reset the selected module - 1 - - - - - QSPIRST - Quad SPI memory controller reset - 1 - 1 - - - - - - APB1RSTR - APB1RSTR - APB1 peripheral reset register - 0x20 - 0x20 - read-write - 0x00000000 - - - TIM2RST - TIM2 reset - 0 - 1 - - TIM2RST - read-write - - Reset - Reset the selected module - 1 - - - - - TIM3RST - TIM3 reset - 1 - 1 - - - - TIM4RST - TIM4 reset - 2 - 1 - - - - TIM5RST - TIM5 reset - 3 - 1 - - - - TIM6RST - TIM6 reset - 4 - 1 - - - - TIM7RST - TIM7 reset - 5 - 1 - - - - TIM12RST - TIM12 reset - 6 - 1 - - - - TIM13RST - TIM13 reset - 7 - 1 - - - - TIM14RST - TIM14 reset - 8 - 1 - - - - WWDGRST - Window watchdog reset - 11 - 1 - - - - SPI2RST - SPI 2 reset - 14 - 1 - - - - SPI3RST - SPI 3 reset - 15 - 1 - - - - USART2RST - USART 2 reset - 17 - 1 - - - - USART3RST - USART 3 reset - 18 - 1 - - - - UART4RST - USART 4 reset - 19 - 1 - - - - UART5RST - USART 5 reset - 20 - 1 - - - - I2C1RST - I2C 1 reset - 21 - 1 - - - - I2C2RST - I2C 2 reset - 22 - 1 - - - - I2C3RST - I2C3 reset - 23 - 1 - - - - CAN1RST - CAN1 reset - 25 - 1 - - - - CAN2RST - CAN2 reset - 26 - 1 - - - - PWRRST - Power interface reset - 28 - 1 - - - - DACRST - DAC reset - 29 - 1 - - - - UART7RST - UART7 reset - 30 - 1 - - - - UART8RST - UART8 reset - 31 - 1 - - - - SPDIFRXRST - SPDIF-RX reset - 16 - 1 - - - - CECRST - HDMI-CEC reset - 27 - 1 - - - - LPTIM1RST - Low power timer 1 reset - 9 - 1 - - - - I2C4RST - I2C 4 reset - 24 - 1 - - - - - - APB2RSTR - APB2RSTR - APB2 peripheral reset register - 0x24 - 0x20 - read-write - 0x00000000 - - - TIM1RST - TIM1 reset - 0 - 1 - - TIM1RST - read-write - - Reset - Reset the selected module - 1 - - - - - TIM8RST - TIM8 reset - 1 - 1 - - - - USART1RST - USART1 reset - 4 - 1 - - - - USART6RST - USART6 reset - 5 - 1 - - - - ADCRST - ADC interface reset (common to all ADCs) - 8 - 1 - - - - SPI1RST - SPI 1 reset - 12 - 1 - - - - SPI4RST - SPI4 reset - 13 - 1 - - - - SYSCFGRST - System configuration controller reset - 14 - 1 - - - - TIM9RST - TIM9 reset - 16 - 1 - - - - TIM10RST - TIM10 reset - 17 - 1 - - - - TIM11RST - TIM11 reset - 18 - 1 - - - - SPI5RST - SPI5 reset - 20 - 1 - - - - SPI6RST - SPI6 reset - 21 - 1 - - - - SAI1RST - SAI1 reset - 22 - 1 - - - - LTDCRST - LTDC reset - 26 - 1 - - - - SAI2RST - SAI2 reset - 23 - 1 - - - - SDMMC1RST - SDMMC1 reset - 11 - 1 - - - - - - AHB1ENR - AHB1ENR - AHB1 peripheral clock register - 0x30 - 0x20 - read-write - 0x00100000 - - - OTGHSULPIEN - USB OTG HSULPI clock enable - 30 - 1 - - - - OTGHSEN - USB OTG HS clock enable - 29 - 1 - - - - ETHMACPTPEN - Ethernet PTP clock enable - 28 - 1 - - - - ETHMACRXEN - Ethernet Reception clock enable - 27 - 1 - - - - ETHMACTXEN - Ethernet Transmission clock enable - 26 - 1 - - - - ETHMACEN - Ethernet MAC clock enable - 25 - 1 - - - - DMA2DEN - DMA2D clock enable - 23 - 1 - - - - DMA2EN - DMA2 clock enable - 22 - 1 - - - - DMA1EN - DMA1 clock enable - 21 - 1 - - - - DTCMRAMEN - CCM data RAM clock enable - 20 - 1 - - - - BKPSRAMEN - Backup SRAM interface clock enable - 18 - 1 - - - - CRCEN - CRC clock enable - 12 - 1 - - - - GPIOKEN - IO port K clock enable - 10 - 1 - - - - GPIOJEN - IO port J clock enable - 9 - 1 - - - - GPIOIEN - IO port I clock enable - 8 - 1 - - - - GPIOHEN - IO port H clock enable - 7 - 1 - - - - GPIOGEN - IO port G clock enable - 6 - 1 - - - - GPIOFEN - IO port F clock enable - 5 - 1 - - - - GPIOEEN - IO port E clock enable - 4 - 1 - - - - GPIODEN - IO port D clock enable - 3 - 1 - - - - GPIOCEN - IO port C clock enable - 2 - 1 - - - - GPIOBEN - IO port B clock enable - 1 - 1 - - - - GPIOAEN - IO port A clock enable - 0 - 1 - - GPIOAEN - read-write - - Disabled - The selected clock is disabled - 0 - - - Enabled - The selected clock is enabled - 1 - - - - - - - AHB2ENR - AHB2ENR - AHB2 peripheral clock enable register - 0x34 - 0x20 - read-write - 0x00000000 - - - OTGFSEN - USB OTG FS clock enable - 7 - 1 - - - - RNGEN - Random number generator clock enable - 6 - 1 - - - - HASHEN - Hash modules clock enable - 5 - 1 - - - - CRYPEN - Cryptographic modules clock enable - 4 - 1 - - - - DCMIEN - Camera interface enable - 0 - 1 - - DCMIEN - read-write - - Disabled - The selected clock is disabled - 0 - - - Enabled - The selected clock is enabled - 1 - - - - - - - AHB3ENR - AHB3ENR - AHB3 peripheral clock enable register - 0x38 - 0x20 - read-write - 0x00000000 - - - FMCEN - Flexible memory controller module clock enable - 0 - 1 - - FMCEN - read-write - - Disabled - The selected clock is disabled - 0 - - - Enabled - The selected clock is enabled - 1 - - - - - QSPIEN - Quad SPI memory controller clock enable - 1 - 1 - - - - - - APB1ENR - APB1ENR - APB1 peripheral clock enable register - 0x40 - 0x20 - read-write - 0x00000000 - - - TIM2EN - TIM2 clock enable - 0 - 1 - - TIM2EN - read-write - - Disabled - The selected clock is disabled - 0 - - - Enabled - The selected clock is enabled - 1 - - - - - TIM3EN - TIM3 clock enable - 1 - 1 - - - - TIM4EN - TIM4 clock enable - 2 - 1 - - - - TIM5EN - TIM5 clock enable - 3 - 1 - - - - TIM6EN - TIM6 clock enable - 4 - 1 - - - - TIM7EN - TIM7 clock enable - 5 - 1 - - - - TIM12EN - TIM12 clock enable - 6 - 1 - - - - TIM13EN - TIM13 clock enable - 7 - 1 - - - - TIM14EN - TIM14 clock enable - 8 - 1 - - - - WWDGEN - Window watchdog clock enable - 11 - 1 - - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - - USART2EN - USART 2 clock enable - 17 - 1 - - - - USART3EN - USART3 clock enable - 18 - 1 - - - - UART4EN - UART4 clock enable - 19 - 1 - - - - UART5EN - UART5 clock enable - 20 - 1 - - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - - I2C3EN - I2C3 clock enable - 23 - 1 - - - - CAN1EN - CAN 1 clock enable - 25 - 1 - - - - CAN2EN - CAN 2 clock enable - 26 - 1 - - - - PWREN - Power interface clock enable - 28 - 1 - - - - DACEN - DAC interface clock enable - 29 - 1 - - - - UART7EN - UART7 clock enable - 30 - 1 - - - - UART8EN - UART8 clock enable - 31 - 1 - - - - SPDIFRXEN - SPDIF-RX clock enable - 16 - 1 - - - - CECEN - HDMI-CEN clock enable - 27 - 1 - - - - LPTIM1EN - Low power timer 1 clock enable - 9 - 1 - - - - I2C4EN - I2C4 clock enable - 24 - 1 - - - - - - APB2ENR - APB2ENR - APB2 peripheral clock enable register - 0x44 - 0x20 - read-write - 0x00000000 - - - TIM1EN - TIM1 clock enable - 0 - 1 - - TIM1EN - read-write - - Disabled - The selected clock is disabled - 0 - - - Enabled - The selected clock is enabled - 1 - - - - - TIM8EN - TIM8 clock enable - 1 - 1 - - - - USART1EN - USART1 clock enable - 4 - 1 - - - - USART6EN - USART6 clock enable - 5 - 1 - - - - ADC1EN - ADC1 clock enable - 8 - 1 - - - - ADC2EN - ADC2 clock enable - 9 - 1 - - - - ADC3EN - ADC3 clock enable - 10 - 1 - - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - - SPI4EN - SPI4 clock enable - 13 - 1 - - - - SYSCFGEN - System configuration controller clock enable - 14 - 1 - - - - TIM9EN - TIM9 clock enable - 16 - 1 - - - - TIM10EN - TIM10 clock enable - 17 - 1 - - - - TIM11EN - TIM11 clock enable - 18 - 1 - - - - SPI5EN - SPI5 clock enable - 20 - 1 - - - - SPI6EN - SPI6 clock enable - 21 - 1 - - - - SAI1EN - SAI1 clock enable - 22 - 1 - - - - LTDCEN - LTDC clock enable - 26 - 1 - - - - SAI2EN - SAI2 clock enable - 23 - 1 - - - - SDMMC1EN - SDMMC1 clock enable - 11 - 1 - - - - - - AHB1LPENR - AHB1LPENR - AHB1 peripheral clock enable in low power mode register - 0x50 - 0x20 - read-write - 0x7E6791FF - - - GPIOALPEN - IO port A clock enable during sleep mode - 0 - 1 - - GPIOALPEN - read-write - - DisabledInSleep - Selected module is disabled during Sleep mode - 0 - - - EnabledInSleep - Selected module is enabled during Sleep mode - 1 - - - - - GPIOBLPEN - IO port B clock enable during Sleep mode - 1 - 1 - - - - GPIOCLPEN - IO port C clock enable during Sleep mode - 2 - 1 - - - - GPIODLPEN - IO port D clock enable during Sleep mode - 3 - 1 - - - - GPIOELPEN - IO port E clock enable during Sleep mode - 4 - 1 - - - - GPIOFLPEN - IO port F clock enable during Sleep mode - 5 - 1 - - - - GPIOGLPEN - IO port G clock enable during Sleep mode - 6 - 1 - - - - GPIOHLPEN - IO port H clock enable during Sleep mode - 7 - 1 - - - - GPIOILPEN - IO port I clock enable during Sleep mode - 8 - 1 - - - - GPIOJLPEN - IO port J clock enable during Sleep mode - 9 - 1 - - - - GPIOKLPEN - IO port K clock enable during Sleep mode - 10 - 1 - - - - CRCLPEN - CRC clock enable during Sleep mode - 12 - 1 - - - - FLITFLPEN - Flash interface clock enable during Sleep mode - 15 - 1 - - - - SRAM1LPEN - SRAM 1interface clock enable during Sleep mode - 16 - 1 - - - - SRAM2LPEN - SRAM 2 interface clock enable during Sleep mode - 17 - 1 - - - - BKPSRAMLPEN - Backup SRAM interface clock enable during Sleep mode - 18 - 1 - - - - SRAM3LPEN - SRAM 3 interface clock enable during Sleep mode - 19 - 1 - - - - DMA1LPEN - DMA1 clock enable during Sleep mode - 21 - 1 - - - - DMA2LPEN - DMA2 clock enable during Sleep mode - 22 - 1 - - - - DMA2DLPEN - DMA2D clock enable during Sleep mode - 23 - 1 - - - - ETHMACLPEN - Ethernet MAC clock enable during Sleep mode - 25 - 1 - - - - ETHMACTXLPEN - Ethernet transmission clock enable during Sleep mode - 26 - 1 - - - - ETHMACRXLPEN - Ethernet reception clock enable during Sleep mode - 27 - 1 - - - - ETHMACPTPLPEN - Ethernet PTP clock enable during Sleep mode - 28 - 1 - - - - OTGHSLPEN - USB OTG HS clock enable during Sleep mode - 29 - 1 - - - - OTGHSULPILPEN - USB OTG HS ULPI clock enable during Sleep mode - 30 - 1 - - - - AXILPEN - AXI to AHB bridge clock enable during Sleep mode - 13 - 1 - - - DTCMLPEN - DTCM RAM interface clock enable during Sleep mode - 20 - 1 - - - - - AHB2LPENR - AHB2LPENR - AHB2 peripheral clock enable in low power mode register - 0x54 - 0x20 - read-write - 0x000000F1 - - - OTGFSLPEN - USB OTG FS clock enable during Sleep mode - 7 - 1 - - - - RNGLPEN - Random number generator clock enable during Sleep mode - 6 - 1 - - - - HASHLPEN - Hash modules clock enable during Sleep mode - 5 - 1 - - - - CRYPLPEN - Cryptography modules clock enable during Sleep mode - 4 - 1 - - - - DCMILPEN - Camera interface enable during Sleep mode - 0 - 1 - - DCMILPEN - read-write - - DisabledInSleep - Selected module is disabled during Sleep mode - 0 - - - EnabledInSleep - Selected module is enabled during Sleep mode - 1 - - - - - - - AHB3LPENR - AHB3LPENR - AHB3 peripheral clock enable in low power mode register - 0x58 - 0x20 - read-write - 0x00000001 - - - FMCLPEN - Flexible memory controller module clock enable during Sleep mode - 0 - 1 - - FMCLPEN - read-write - - DisabledInSleep - Selected module is disabled during Sleep mode - 0 - - - EnabledInSleep - Selected module is enabled during Sleep mode - 1 - - - - - QSPILPEN - Quand SPI memory controller clock enable during Sleep mode - 1 - 1 - - - - - - APB1LPENR - APB1LPENR - APB1 peripheral clock enable in low power mode register - 0x60 - 0x20 - read-write - 0x36FEC9FF - - - TIM2LPEN - TIM2 clock enable during Sleep mode - 0 - 1 - - TIM2LPEN - read-write - - DisabledInSleep - Selected module is disabled during Sleep mode - 0 - - - EnabledInSleep - Selected module is enabled during Sleep mode - 1 - - - - - TIM3LPEN - TIM3 clock enable during Sleep mode - 1 - 1 - - - - TIM4LPEN - TIM4 clock enable during Sleep mode - 2 - 1 - - - - TIM5LPEN - TIM5 clock enable during Sleep mode - 3 - 1 - - - - TIM6LPEN - TIM6 clock enable during Sleep mode - 4 - 1 - - - - TIM7LPEN - TIM7 clock enable during Sleep mode - 5 - 1 - - - - TIM12LPEN - TIM12 clock enable during Sleep mode - 6 - 1 - - - - TIM13LPEN - TIM13 clock enable during Sleep mode - 7 - 1 - - - - TIM14LPEN - TIM14 clock enable during Sleep mode - 8 - 1 - - - - WWDGLPEN - Window watchdog clock enable during Sleep mode - 11 - 1 - - - - SPI2LPEN - SPI2 clock enable during Sleep mode - 14 - 1 - - - - SPI3LPEN - SPI3 clock enable during Sleep mode - 15 - 1 - - - - USART2LPEN - USART2 clock enable during Sleep mode - 17 - 1 - - - - USART3LPEN - USART3 clock enable during Sleep mode - 18 - 1 - - - - UART4LPEN - UART4 clock enable during Sleep mode - 19 - 1 - - - - UART5LPEN - UART5 clock enable during Sleep mode - 20 - 1 - - - - I2C1LPEN - I2C1 clock enable during Sleep mode - 21 - 1 - - - - I2C2LPEN - I2C2 clock enable during Sleep mode - 22 - 1 - - - - I2C3LPEN - I2C3 clock enable during Sleep mode - 23 - 1 - - - - CAN1LPEN - CAN 1 clock enable during Sleep mode - 25 - 1 - - - - CAN2LPEN - CAN 2 clock enable during Sleep mode - 26 - 1 - - - - PWRLPEN - Power interface clock enable during Sleep mode - 28 - 1 - - - - DACLPEN - DAC interface clock enable during Sleep mode - 29 - 1 - - - - UART7LPEN - UART7 clock enable during Sleep mode - 30 - 1 - - - - UART8LPEN - UART8 clock enable during Sleep mode - 31 - 1 - - - - SPDIFRXLPEN - SPDIF-RX clock enable during sleep mode - 16 - 1 - - - - CECLPEN - HDMI-CEN clock enable during Sleep mode - 27 - 1 - - - - LPTIM1LPEN - low power timer 1 clock enable during Sleep mode - 9 - 1 - - - - I2C4LPEN - I2C4 clock enable during Sleep mode - 24 - 1 - - - - - - APB2LPENR - APB2LPENR - APB2 peripheral clock enabled in low power mode register - 0x64 - 0x20 - read-write - 0x00075F33 - - - TIM1LPEN - TIM1 clock enable during Sleep mode - 0 - 1 - - TIM1LPEN - read-write - - DisabledInSleep - Selected module is disabled during Sleep mode - 0 - - - EnabledInSleep - Selected module is enabled during Sleep mode - 1 - - - - - TIM8LPEN - TIM8 clock enable during Sleep mode - 1 - 1 - - - - USART1LPEN - USART1 clock enable during Sleep mode - 4 - 1 - - - - USART6LPEN - USART6 clock enable during Sleep mode - 5 - 1 - - - - ADC1LPEN - ADC1 clock enable during Sleep mode - 8 - 1 - - - - ADC2LPEN - ADC2 clock enable during Sleep mode - 9 - 1 - - - - ADC3LPEN - ADC 3 clock enable during Sleep mode - 10 - 1 - - - - SPI1LPEN - SPI 1 clock enable during Sleep mode - 12 - 1 - - - - SPI4LPEN - SPI 4 clock enable during Sleep mode - 13 - 1 - - - - SYSCFGLPEN - System configuration controller clock enable during Sleep mode - 14 - 1 - - - - TIM9LPEN - TIM9 clock enable during sleep mode - 16 - 1 - - - - TIM10LPEN - TIM10 clock enable during Sleep mode - 17 - 1 - - - - TIM11LPEN - TIM11 clock enable during Sleep mode - 18 - 1 - - - - SPI5LPEN - SPI 5 clock enable during Sleep mode - 20 - 1 - - - - SPI6LPEN - SPI 6 clock enable during Sleep mode - 21 - 1 - - - - SAI1LPEN - SAI1 clock enable during sleep mode - 22 - 1 - - - - LTDCLPEN - LTDC clock enable during sleep mode - 26 - 1 - - - - SAI2LPEN - SAI2 clock enable during sleep mode - 23 - 1 - - - - SDMMC1LPEN - SDMMC1 clock enable during Sleep mode - 11 - 1 - - - - - - BDCR - BDCR - Backup domain control register - 0x70 - 0x20 - 0x00000000 - - - BDRST - Backup domain software reset - 16 - 1 - read-write - - BDRST - read-write - - Disabled - Reset not activated - 0 - - - Enabled - Reset the entire RTC domain - 1 - - - - - RTCEN - RTC clock enable - 15 - 1 - read-write - - RTCEN - read-write - - Disabled - RTC clock disabled - 0 - - - Enabled - RTC clock enabled - 1 - - - - - LSEBYP - External low-speed oscillator bypass - 2 - 1 - read-write - - LSEBYP - read-write - - NotBypassed - LSE crystal oscillator not bypassed - 0 - - - Bypassed - LSE crystal oscillator bypassed with external clock - 1 - - - - - LSERDY - External low-speed oscillator ready - 1 - 1 - read-only - - LSERDYR - read - - NotReady - LSE oscillator not ready - 0 - - - Ready - LSE oscillator ready - 1 - - - - - LSEON - External low-speed oscillator enable - 0 - 1 - read-write - - LSEON - read-write - - Off - LSE oscillator Off - 0 - - - On - LSE oscillator On - 1 - - - - - LSEDRV - LSE oscillator drive capability - 3 - 2 - read-write - - LSEDRV - read-write - - Low - Low drive capacity - 0 - - - MediumHigh - Medium-high drive capacity - 1 - - - MediumLow - Medium-low drive capacity - 2 - - - High - High drive capacity - 3 - - - - - RTCSEL - RTC clock source selection - 8 - 2 - - RTCSEL - read-write - - NoClock - No clock - 0 - - - LSE - LSE oscillator clock used as RTC clock - 1 - - - LSI - LSI oscillator clock used as RTC clock - 2 - - - HSE - HSE oscillator clock divided by a prescaler used as RTC clock - 3 - - - - - - - CSR - CSR - clock control & status register - 0x74 - 0x20 - 0x0E000000 - - - LPWRRSTF - Low-power reset flag - 31 - 1 - read-write - - - - WWDGRSTF - Window watchdog reset flag - 30 - 1 - read-write - - - - WDGRSTF - Independent watchdog reset flag - 29 - 1 - read-write - - - - SFTRSTF - Software reset flag - 28 - 1 - read-write - - - - PORRSTF - POR/PDR reset flag - 27 - 1 - read-write - - - - PADRSTF - PIN reset flag - 26 - 1 - read-write - - - - BORRSTF - BOR reset flag - 25 - 1 - read-write - - BORRSTFR - read - - NoReset - No reset has occured - 0 - - - Reset - A reset has occured - 1 - - - - - RMVF - Remove reset flag - 24 - 1 - read-write - - RMVFW - write - - Clear - Clears the reset flag - 1 - - - - - LSIRDY - Internal low-speed oscillator ready - 1 - 1 - read-only - - LSIRDYR - read - - NotReady - LSI oscillator not ready - 0 - - - Ready - LSI oscillator ready - 1 - - - - - LSION - Internal low-speed oscillator enable - 0 - 1 - read-write - - LSION - read-write - - Off - LSI oscillator Off - 0 - - - On - LSI oscillator On - 1 - - - - - - - SSCGR - SSCGR - spread spectrum clock generation register - 0x80 - 0x20 - read-write - 0x00000000 - - - SSCGEN - Spread spectrum modulation enable - 31 - 1 - - SSCGEN - read-write - - Disabled - Spread spectrum modulation disabled - 0 - - - Enabled - Spread spectrum modulation enabled - 1 - - - - - SPREADSEL - Spread Select - 30 - 1 - - SPREADSEL - read-write - - Center - Center spread - 0 - - - Down - Down spread - 1 - - - - - INCSTEP - Incrementation step - 13 - 15 - - - 0 - 32767 - - - - - MODPER - Modulation period - 0 - 13 - - - 0 - 8191 - - - - - - - PLLI2SCFGR - PLLI2SCFGR - PLLI2S configuration register - 0x84 - 0x20 - read-write - 0x20003000 - - - PLLI2SR - PLLI2S division factor for I2S clocks - 28 - 3 - - - 2 - 7 - - - - - PLLI2SQ - PLLI2S division factor for SAI1 clock - 24 - 4 - - - 2 - 15 - - - - - PLLI2SN - PLLI2S multiplication factor for VCO - 6 - 9 - - - 50 - 432 - - - - - PLLI2SP - PLLI2S division factor for SPDIFRX clock - 16 - 2 - - PLLI2SP - read-write - - Div2 - PLL*P=2 - 0 - - - Div4 - PLL*P=4 - 1 - - - Div6 - PLL*P=6 - 2 - - - Div8 - PLL*P=8 - 3 - - - - - - - PLLSAICFGR - PLLSAICFGR - PLL configuration register - 0x88 - 0x20 - read-write - 0x20003000 - - - PLLSAIN - PLLSAI division factor for VCO - 6 - 9 - - - 50 - 432 - - - - - PLLSAIP - PLLSAI division factor for 48MHz clock - 16 - 2 - - PLLSAIP - read-write - - Div2 - PLL*P=2 - 0 - - - Div4 - PLL*P=4 - 1 - - - Div6 - PLL*P=6 - 2 - - - Div8 - PLL*P=8 - 3 - - - - - PLLSAIQ - PLLSAI division factor for SAI clock - 24 - 4 - - - 2 - 15 - - - - - PLLSAIR - PLLSAI division factor for LCD clock - 28 - 3 - - - 2 - 7 - - - - - - - DCKCFGR1 - DKCFGR1 - dedicated clocks configuration register - 0x8C - 0x20 - read-write - 0x00000000 - - - PLLI2SDIVQ - PLLI2S division factor for SAI1 clock - 0 - 5 - - PLLI2SDIVQ - read-write - - Div1 - PLLI2SDIVQ = /1 - 0 - - - Div2 - PLLI2SDIVQ = /2 - 1 - - - Div3 - PLLI2SDIVQ = /3 - 2 - - - Div4 - PLLI2SDIVQ = /4 - 3 - - - Div5 - PLLI2SDIVQ = /5 - 4 - - - Div6 - PLLI2SDIVQ = /6 - 5 - - - Div7 - PLLI2SDIVQ = /7 - 6 - - - Div8 - PLLI2SDIVQ = /8 - 7 - - - Div9 - PLLI2SDIVQ = /9 - 8 - - - Div10 - PLLI2SDIVQ = /10 - 9 - - - Div11 - PLLI2SDIVQ = /11 - 10 - - - Div12 - PLLI2SDIVQ = /12 - 11 - - - Div13 - PLLI2SDIVQ = /13 - 12 - - - Div14 - PLLI2SDIVQ = /14 - 13 - - - Div15 - PLLI2SDIVQ = /15 - 14 - - - Div16 - PLLI2SDIVQ = /16 - 15 - - - Div17 - PLLI2SDIVQ = /17 - 16 - - - Div18 - PLLI2SDIVQ = /18 - 17 - - - Div19 - PLLI2SDIVQ = /19 - 18 - - - Div20 - PLLI2SDIVQ = /20 - 19 - - - Div21 - PLLI2SDIVQ = /21 - 20 - - - Div22 - PLLI2SDIVQ = /22 - 21 - - - Div23 - PLLI2SDIVQ = /23 - 22 - - - Div24 - PLLI2SDIVQ = /24 - 23 - - - Div25 - PLLI2SDIVQ = /25 - 24 - - - Div26 - PLLI2SDIVQ = /26 - 25 - - - Div27 - PLLI2SDIVQ = /27 - 26 - - - Div28 - PLLI2SDIVQ = /28 - 27 - - - Div29 - PLLI2SDIVQ = /29 - 28 - - - Div30 - PLLI2SDIVQ = /30 - 29 - - - Div31 - PLLI2SDIVQ = /31 - 30 - - - Div32 - PLLI2SDIVQ = /32 - 31 - - - - - PLLSAIDIVQ - PLLSAI division factor for SAI1 clock - 8 - 5 - - PLLSAIDIVQ - read-write - - Div1 - PLLSAIDIVQ = /1 - 0 - - - Div2 - PLLSAIDIVQ = /2 - 1 - - - Div3 - PLLSAIDIVQ = /3 - 2 - - - Div4 - PLLSAIDIVQ = /4 - 3 - - - Div5 - PLLSAIDIVQ = /5 - 4 - - - Div6 - PLLSAIDIVQ = /6 - 5 - - - Div7 - PLLSAIDIVQ = /7 - 6 - - - Div8 - PLLSAIDIVQ = /8 - 7 - - - Div9 - PLLSAIDIVQ = /9 - 8 - - - Div10 - PLLSAIDIVQ = /10 - 9 - - - Div11 - PLLSAIDIVQ = /11 - 10 - - - Div12 - PLLSAIDIVQ = /12 - 11 - - - Div13 - PLLSAIDIVQ = /13 - 12 - - - Div14 - PLLSAIDIVQ = /14 - 13 - - - Div15 - PLLSAIDIVQ = /15 - 14 - - - Div16 - PLLSAIDIVQ = /16 - 15 - - - Div17 - PLLSAIDIVQ = /17 - 16 - - - Div18 - PLLSAIDIVQ = /18 - 17 - - - Div19 - PLLSAIDIVQ = /19 - 18 - - - Div20 - PLLSAIDIVQ = /20 - 19 - - - Div21 - PLLSAIDIVQ = /21 - 20 - - - Div22 - PLLSAIDIVQ = /22 - 21 - - - Div23 - PLLSAIDIVQ = /23 - 22 - - - Div24 - PLLSAIDIVQ = /24 - 23 - - - Div25 - PLLSAIDIVQ = /25 - 24 - - - Div26 - PLLSAIDIVQ = /26 - 25 - - - Div27 - PLLSAIDIVQ = /27 - 26 - - - Div28 - PLLSAIDIVQ = /28 - 27 - - - Div29 - PLLSAIDIVQ = /29 - 28 - - - Div30 - PLLSAIDIVQ = /30 - 29 - - - Div31 - PLLSAIDIVQ = /31 - 30 - - - Div32 - PLLSAIDIVQ = /32 - 31 - - - - - PLLSAIDIVR - division factor for LCD_CLK - 16 - 2 - - PLLSAIDIVR - read-write - - Div2 - PLLSAIDIVR = /2 - 0 - - - Div4 - PLLSAIDIVR = /4 - 1 - - - Div8 - PLLSAIDIVR = /8 - 2 - - - Div16 - PLLSAIDIVR = /16 - 3 - - - - - SAI1SEL - SAI1 clock source selection - 20 - 2 - - SAI1SEL - read-write - - PLLSAI - SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - 0 - - - PLLI2S - SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - 1 - - - AFIF - SAI1 clock frequency = Alternate function input frequency - 2 - - - HSI_HSE - SAI1 clock frequency = HSI or HSE - 3 - - - - - SAI2SEL - SAI2 clock source selection - 22 - 2 - - SAI2SEL - read-write - - PLLSAI - SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - 0 - - - PLLI2S - SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - 1 - - - AFIF - SAI2 clock frequency = Alternate function input frequency - 2 - - - HSI_HSE - SAI2 clock frequency = HSI or HSE - 3 - - - - - TIMPRE - Timers clocks prescalers selection - 24 - 1 - - TIMPRE - read-write - - Mul1Or2 - If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - 0 - - - Mul1Or4 - If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - 1 - - - - - - - DCKCFGR2 - DKCFGR2 - dedicated clocks configuration register - 0x90 - 0x20 - read-write - 0x00000000 - - - USART1SEL - USART 1 clock source selection - 0 - 2 - - USART1SEL - read-write - - APB2 - APB2 clock (PCLK2) is selected as USART clock - 0 - - - SYSCLK - System clock is selected as USART clock - 1 - - - HSI - HSI clock is selected as USART clock - 2 - - - LSE - LSE clock is selected as USART clock - 3 - - - - - USART2SEL - USART 2 clock source selection - 2 - 2 - - USART2SEL - read-write - - APB1 - APB1 clock (PCLK1) is selected as USART clock - 0 - - - SYSCLK - System clock is selected as USART clock - 1 - - - HSI - HSI clock is selected as USART clock - 2 - - - LSE - LSE clock is selected as USART clock - 3 - - - - - USART3SEL - USART 3 clock source selection - 4 - 2 - - - - UART4SEL - UART 4 clock source selection - 6 - 2 - - - - UART5SEL - UART 5 clock source selection - 8 - 2 - - - - USART6SEL - USART 6 clock source selection - 10 - 2 - - - - UART7SEL - UART 7 clock source selection - 12 - 2 - - - - UART8SEL - UART 8 clock source selection - 14 - 2 - - - - I2C1SEL - I2C1 clock source selection - 16 - 2 - - I2C1SEL - read-write - - APB - APB clock selected as I2C clock - 0 - - - SYSCLK - System clock selected as I2C clock - 1 - - - HSI - HSI clock selected as I2C clock - 2 - - - - - I2C2SEL - I2C2 clock source selection - 18 - 2 - - - - I2C3SEL - I2C3 clock source selection - 20 - 2 - - - - I2C4SEL - I2C4 clock source selection - 22 - 2 - - - - LPTIM1SEL - Low power timer 1 clock source selection - 24 - 2 - - LPTIM1SEL - read-write - - APB1 - APB1 clock (PCLK1) selected as LPTILM1 clock - 0 - - - LSI - LSI clock is selected as LPTILM1 clock - 1 - - - HSI - HSI clock is selected as LPTILM1 clock - 2 - - - LSE - LSE clock is selected as LPTILM1 clock - 3 - - - - - CECSEL - HDMI-CEC clock source selection - 26 - 1 - - CECSEL - read-write - - LSE - LSE clock is selected as HDMI-CEC clock - 0 - - - HSI_Div488 - HSI divided by 488 clock is selected as HDMI-CEC clock - 1 - - - - - CK48MSEL - 48MHz clock source selection - 27 - 1 - - CK48MSEL - read-write - - PLL - 48MHz clock from PLL is selected - 0 - - - PLLSAI - 48MHz clock from PLLSAI is selected - 1 - - - - - SDMMC1SEL - SDMMC clock source selection - 28 - 1 - - SDMMC1SEL - read-write - - CK48M - 48 MHz clock is selected as SD clock - 0 - - - SYSCLK - System clock is selected as SD clock - 1 - - - - - - - - - GPIOD - 0x40020C00 - - - GPIOC - 0x40020800 - - - GPIOK - 0x40022800 - - - GPIOJ - 0x40022400 - - - GPIOI - 0x40022000 - - - GPIOH - 0x40021C00 - - - GPIOG - 0x40021800 - - - GPIOF - 0x40021400 - - - GPIOE - 0x40021000 - - - GPIOB - 0x40020400 - - - GPIOA - General-purpose I/Os - GPIO - 0x40020000 - - 0x0 - 0x400 - registers - - - - MODER - MODER - GPIO port mode register - 0x0 - 0x20 - read-write - 0xA8000000 - - - MODER15 - Port x configuration bits (y = 0..15) - 30 - 2 - - - - MODER14 - Port x configuration bits (y = 0..15) - 28 - 2 - - - - MODER13 - Port x configuration bits (y = 0..15) - 26 - 2 - - - - MODER12 - Port x configuration bits (y = 0..15) - 24 - 2 - - - - MODER11 - Port x configuration bits (y = 0..15) - 22 - 2 - - - - MODER10 - Port x configuration bits (y = 0..15) - 20 - 2 - - - - MODER9 - Port x configuration bits (y = 0..15) - 18 - 2 - - - - MODER8 - Port x configuration bits (y = 0..15) - 16 - 2 - - - - MODER7 - Port x configuration bits (y = 0..15) - 14 - 2 - - - - MODER6 - Port x configuration bits (y = 0..15) - 12 - 2 - - - - MODER5 - Port x configuration bits (y = 0..15) - 10 - 2 - - - - MODER4 - Port x configuration bits (y = 0..15) - 8 - 2 - - - - MODER3 - Port x configuration bits (y = 0..15) - 6 - 2 - - - - MODER2 - Port x configuration bits (y = 0..15) - 4 - 2 - - - - MODER1 - Port x configuration bits (y = 0..15) - 2 - 2 - - - - MODER0 - Port x configuration bits (y = 0..15) - 0 - 2 - - MODER0 - read-write - - Input - Input mode (reset state) - 0 - - - Output - General purpose output mode - 1 - - - Alternate - Alternate function mode - 2 - - - Analog - Analog mode - 3 - - - - - - - OTYPER - OTYPER - GPIO port output type register - 0x4 - 0x20 - read-write - 0x00000000 - - - OT15 - Port x configuration bits (y = 0..15) - 15 - 1 - - - - OT14 - Port x configuration bits (y = 0..15) - 14 - 1 - - - - OT13 - Port x configuration bits (y = 0..15) - 13 - 1 - - - - OT12 - Port x configuration bits (y = 0..15) - 12 - 1 - - - - OT11 - Port x configuration bits (y = 0..15) - 11 - 1 - - - - OT10 - Port x configuration bits (y = 0..15) - 10 - 1 - - - - OT9 - Port x configuration bits (y = 0..15) - 9 - 1 - - - - OT8 - Port x configuration bits (y = 0..15) - 8 - 1 - - - - OT7 - Port x configuration bits (y = 0..15) - 7 - 1 - - - - OT6 - Port x configuration bits (y = 0..15) - 6 - 1 - - - - OT5 - Port x configuration bits (y = 0..15) - 5 - 1 - - - - OT4 - Port x configuration bits (y = 0..15) - 4 - 1 - - - - OT3 - Port x configuration bits (y = 0..15) - 3 - 1 - - - - OT2 - Port x configuration bits (y = 0..15) - 2 - 1 - - - - OT1 - Port x configuration bits (y = 0..15) - 1 - 1 - - - - OT0 - Port x configuration bits (y = 0..15) - 0 - 1 - - OT0 - read-write - - PushPull - Output push-pull (reset state) - 0 - - - OpenDrain - Output open-drain - 1 - - - - - - - OSPEEDR - GPIOB_OSPEEDR - GPIO port output speed register - 0x8 - 0x20 - read-write - 0x00000000 - - - OSPEEDR15 - Port x configuration bits (y = 0..15) - 30 - 2 - - - - OSPEEDR14 - Port x configuration bits (y = 0..15) - 28 - 2 - - - - OSPEEDR13 - Port x configuration bits (y = 0..15) - 26 - 2 - - - - OSPEEDR12 - Port x configuration bits (y = 0..15) - 24 - 2 - - - - OSPEEDR11 - Port x configuration bits (y = 0..15) - 22 - 2 - - - - OSPEEDR10 - Port x configuration bits (y = 0..15) - 20 - 2 - - - - OSPEEDR9 - Port x configuration bits (y = 0..15) - 18 - 2 - - - - OSPEEDR8 - Port x configuration bits (y = 0..15) - 16 - 2 - - - - OSPEEDR7 - Port x configuration bits (y = 0..15) - 14 - 2 - - - - OSPEEDR6 - Port x configuration bits (y = 0..15) - 12 - 2 - - - - OSPEEDR5 - Port x configuration bits (y = 0..15) - 10 - 2 - - - - OSPEEDR4 - Port x configuration bits (y = 0..15) - 8 - 2 - - - - OSPEEDR3 - Port x configuration bits (y = 0..15) - 6 - 2 - - - - OSPEEDR2 - Port x configuration bits (y = 0..15) - 4 - 2 - - - - OSPEEDR1 - Port x configuration bits (y = 0..15) - 2 - 2 - - - - OSPEEDR0 - Port x configuration bits (y = 0..15) - 0 - 2 - - OSPEEDR0 - read-write - - LowSpeed - Low speed - 0 - - - MediumSpeed - Medium speed - 1 - - - HighSpeed - High speed - 2 - - - VeryHighSpeed - Very high speed - 3 - - - - - - - PUPDR - PUPDR - GPIO port pull-up/pull-down register - 0xC - 0x20 - read-write - 0x64000000 - - - PUPDR15 - Port x configuration bits (y = 0..15) - 30 - 2 - - - - PUPDR14 - Port x configuration bits (y = 0..15) - 28 - 2 - - - - PUPDR13 - Port x configuration bits (y = 0..15) - 26 - 2 - - - - PUPDR12 - Port x configuration bits (y = 0..15) - 24 - 2 - - - - PUPDR11 - Port x configuration bits (y = 0..15) - 22 - 2 - - - - PUPDR10 - Port x configuration bits (y = 0..15) - 20 - 2 - - - - PUPDR9 - Port x configuration bits (y = 0..15) - 18 - 2 - - - - PUPDR8 - Port x configuration bits (y = 0..15) - 16 - 2 - - - - PUPDR7 - Port x configuration bits (y = 0..15) - 14 - 2 - - - - PUPDR6 - Port x configuration bits (y = 0..15) - 12 - 2 - - - - PUPDR5 - Port x configuration bits (y = 0..15) - 10 - 2 - - - - PUPDR4 - Port x configuration bits (y = 0..15) - 8 - 2 - - - - PUPDR3 - Port x configuration bits (y = 0..15) - 6 - 2 - - - - PUPDR2 - Port x configuration bits (y = 0..15) - 4 - 2 - - - - PUPDR1 - Port x configuration bits (y = 0..15) - 2 - 2 - - - - PUPDR0 - Port x configuration bits (y = 0..15) - 0 - 2 - - PUPDR0 - read-write - - Floating - No pull-up, pull-down - 0 - - - PullUp - Pull-up - 1 - - - PullDown - Pull-down - 2 - - - - - - - IDR - IDR - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - IDR15 - Port input data (y = 0..15) - 15 - 1 - - - - IDR14 - Port input data (y = 0..15) - 14 - 1 - - - - IDR13 - Port input data (y = 0..15) - 13 - 1 - - - - IDR12 - Port input data (y = 0..15) - 12 - 1 - - - - IDR11 - Port input data (y = 0..15) - 11 - 1 - - - - IDR10 - Port input data (y = 0..15) - 10 - 1 - - - - IDR9 - Port input data (y = 0..15) - 9 - 1 - - - - IDR8 - Port input data (y = 0..15) - 8 - 1 - - - - IDR7 - Port input data (y = 0..15) - 7 - 1 - - - - IDR6 - Port input data (y = 0..15) - 6 - 1 - - - - IDR5 - Port input data (y = 0..15) - 5 - 1 - - - - IDR4 - Port input data (y = 0..15) - 4 - 1 - - - - IDR3 - Port input data (y = 0..15) - 3 - 1 - - - - IDR2 - Port input data (y = 0..15) - 2 - 1 - - - - IDR1 - Port input data (y = 0..15) - 1 - 1 - - - - IDR0 - Port input data (y = 0..15) - 0 - 1 - - IDR0 - read - - Low - Input is logic low - 0 - - - High - Input is logic high - 1 - - - - - - - ODR - ODR - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - ODR15 - Port output data (y = 0..15) - 15 - 1 - - - - ODR14 - Port output data (y = 0..15) - 14 - 1 - - - - ODR13 - Port output data (y = 0..15) - 13 - 1 - - - - ODR12 - Port output data (y = 0..15) - 12 - 1 - - - - ODR11 - Port output data (y = 0..15) - 11 - 1 - - - - ODR10 - Port output data (y = 0..15) - 10 - 1 - - - - ODR9 - Port output data (y = 0..15) - 9 - 1 - - - - ODR8 - Port output data (y = 0..15) - 8 - 1 - - - - ODR7 - Port output data (y = 0..15) - 7 - 1 - - - - ODR6 - Port output data (y = 0..15) - 6 - 1 - - - - ODR5 - Port output data (y = 0..15) - 5 - 1 - - - - ODR4 - Port output data (y = 0..15) - 4 - 1 - - - - ODR3 - Port output data (y = 0..15) - 3 - 1 - - - - ODR2 - Port output data (y = 0..15) - 2 - 1 - - - - ODR1 - Port output data (y = 0..15) - 1 - 1 - - - - ODR0 - Port output data (y = 0..15) - 0 - 1 - - ODR0 - read-write - - Low - Set output to logic low - 0 - - - High - Set output to logic high - 1 - - - - - - - BSRR - BSRR - GPIO port bit set/reset register - 0x18 - 0x20 - write-only - 0x00000000 - - - BR15 - Port x reset bit y (y = 0..15) - 31 - 1 - - - - BR14 - Port x reset bit y (y = 0..15) - 30 - 1 - - - - BR13 - Port x reset bit y (y = 0..15) - 29 - 1 - - - - BR12 - Port x reset bit y (y = 0..15) - 28 - 1 - - - - BR11 - Port x reset bit y (y = 0..15) - 27 - 1 - - - - BR10 - Port x reset bit y (y = 0..15) - 26 - 1 - - - - BR9 - Port x reset bit y (y = 0..15) - 25 - 1 - - - - BR8 - Port x reset bit y (y = 0..15) - 24 - 1 - - - - BR7 - Port x reset bit y (y = 0..15) - 23 - 1 - - - - BR6 - Port x reset bit y (y = 0..15) - 22 - 1 - - - - BR5 - Port x reset bit y (y = 0..15) - 21 - 1 - - - - BR4 - Port x reset bit y (y = 0..15) - 20 - 1 - - - - BR3 - Port x reset bit y (y = 0..15) - 19 - 1 - - - - BR2 - Port x reset bit y (y = 0..15) - 18 - 1 - - - - BR1 - Port x reset bit y (y = 0..15) - 17 - 1 - - - - BR0 - Port x set bit y (y= 0..15) - 16 - 1 - - BR0W - write - - Reset - Resets the corresponding ODRx bit - 1 - - - - - BS15 - Port x set bit y (y= 0..15) - 15 - 1 - - - - BS14 - Port x set bit y (y= 0..15) - 14 - 1 - - - - BS13 - Port x set bit y (y= 0..15) - 13 - 1 - - - - BS12 - Port x set bit y (y= 0..15) - 12 - 1 - - - - BS11 - Port x set bit y (y= 0..15) - 11 - 1 - - - - BS10 - Port x set bit y (y= 0..15) - 10 - 1 - - - - BS9 - Port x set bit y (y= 0..15) - 9 - 1 - - - - BS8 - Port x set bit y (y= 0..15) - 8 - 1 - - - - BS7 - Port x set bit y (y= 0..15) - 7 - 1 - - - - BS6 - Port x set bit y (y= 0..15) - 6 - 1 - - - - BS5 - Port x set bit y (y= 0..15) - 5 - 1 - - - - BS4 - Port x set bit y (y= 0..15) - 4 - 1 - - - - BS3 - Port x set bit y (y= 0..15) - 3 - 1 - - - - BS2 - Port x set bit y (y= 0..15) - 2 - 1 - - - - BS1 - Port x set bit y (y= 0..15) - 1 - 1 - - - - BS0 - Port x set bit y (y= 0..15) - 0 - 1 - - BS0W - write - - Set - Sets the corresponding ODRx bit - 1 - - - - - - - LCKR - LCKR - GPIO port configuration lock register - 0x1C - 0x20 - read-write - 0x00000000 - - - LCKK - Port x lock bit y (y= 0..15) - 16 - 1 - - LCKK - read-write - - NotActive - Port configuration lock key not active - 0 - - - Active - Port configuration lock key active - 1 - - - - - LCK15 - Port x lock bit y (y= 0..15) - 15 - 1 - - - - LCK14 - Port x lock bit y (y= 0..15) - 14 - 1 - - - - LCK13 - Port x lock bit y (y= 0..15) - 13 - 1 - - - - LCK12 - Port x lock bit y (y= 0..15) - 12 - 1 - - - - LCK11 - Port x lock bit y (y= 0..15) - 11 - 1 - - - - LCK10 - Port x lock bit y (y= 0..15) - 10 - 1 - - - - LCK9 - Port x lock bit y (y= 0..15) - 9 - 1 - - - - LCK8 - Port x lock bit y (y= 0..15) - 8 - 1 - - - - LCK7 - Port x lock bit y (y= 0..15) - 7 - 1 - - - - LCK6 - Port x lock bit y (y= 0..15) - 6 - 1 - - - - LCK5 - Port x lock bit y (y= 0..15) - 5 - 1 - - - - LCK4 - Port x lock bit y (y= 0..15) - 4 - 1 - - - - LCK3 - Port x lock bit y (y= 0..15) - 3 - 1 - - - - LCK2 - Port x lock bit y (y= 0..15) - 2 - 1 - - - - LCK1 - Port x lock bit y (y= 0..15) - 1 - 1 - - - - LCK0 - Port x lock bit y (y= 0..15) - 0 - 1 - - LCK0 - read-write - - Unlocked - Port configuration not locked - 0 - - - Locked - Port configuration locked - 1 - - - - - - - AFRL - AFRL - GPIO alternate function low register - 0x20 - 0x20 - read-write - 0x00000000 - - - AFRL7 - Alternate function selection for port x bit y (y = 0..7) - 28 - 4 - - - - AFRL6 - Alternate function selection for port x bit y (y = 0..7) - 24 - 4 - - - - AFRL5 - Alternate function selection for port x bit y (y = 0..7) - 20 - 4 - - - - AFRL4 - Alternate function selection for port x bit y (y = 0..7) - 16 - 4 - - - - AFRL3 - Alternate function selection for port x bit y (y = 0..7) - 12 - 4 - - - - AFRL2 - Alternate function selection for port x bit y (y = 0..7) - 8 - 4 - - - - AFRL1 - Alternate function selection for port x bit y (y = 0..7) - 4 - 4 - - - - AFRL0 - Alternate function selection for port x bit y (y = 0..7) - 0 - 4 - - AFRL0 - read-write - - AF0 - AF0 - 0 - - - AF1 - AF1 - 1 - - - AF2 - AF2 - 2 - - - AF3 - AF3 - 3 - - - AF4 - AF4 - 4 - - - AF5 - AF5 - 5 - - - AF6 - AF6 - 6 - - - AF7 - AF7 - 7 - - - AF8 - AF8 - 8 - - - AF9 - AF9 - 9 - - - AF10 - AF10 - 10 - - - AF11 - AF11 - 11 - - - AF12 - AF12 - 12 - - - AF13 - AF13 - 13 - - - AF14 - AF14 - 14 - - - AF15 - AF15 - 15 - - - - - - - AFRH - AFRH - GPIO alternate function high register - 0x24 - 0x20 - read-write - 0x00000000 - - - AFRH15 - Alternate function selection for port x bit y (y = 8..15) - 28 - 4 - - - - AFRH14 - Alternate function selection for port x bit y (y = 8..15) - 24 - 4 - - - - AFRH13 - Alternate function selection for port x bit y (y = 8..15) - 20 - 4 - - - - AFRH12 - Alternate function selection for port x bit y (y = 8..15) - 16 - 4 - - - - AFRH11 - Alternate function selection for port x bit y (y = 8..15) - 12 - 4 - - - - AFRH10 - Alternate function selection for port x bit y (y = 8..15) - 8 - 4 - - - - AFRH9 - Alternate function selection for port x bit y (y = 8..15) - 4 - 4 - - - - AFRH8 - Alternate function selection for port x bit y (y = 8..15) - 0 - 4 - - AFRH8 - read-write - - AF0 - AF0 - 0 - - - AF1 - AF1 - 1 - - - AF2 - AF2 - 2 - - - AF3 - AF3 - 3 - - - AF4 - AF4 - 4 - - - AF5 - AF5 - 5 - - - AF6 - AF6 - 6 - - - AF7 - AF7 - 7 - - - AF8 - AF8 - 8 - - - AF9 - AF9 - 9 - - - AF10 - AF10 - 10 - - - AF11 - AF11 - 11 - - - AF12 - AF12 - 12 - - - AF13 - AF13 - 13 - - - AF14 - AF14 - 14 - - - AF15 - AF15 - 15 - - - - - - - BRR - BRR - GPIO port bit reset register - 0x28 - 0x20 - read-write - 0x00000000 - - - BR0 - Port A Reset bit 0 - 0 - 1 - - - BR1 - Port A Reset bit 1 - 1 - 1 - - - BR2 - Port A Reset bit 2 - 2 - 1 - - - BR3 - Port A Reset bit 3 - 3 - 1 - - - BR4 - Port A Reset bit 4 - 4 - 1 - - - BR5 - Port A Reset bit 5 - 5 - 1 - - - BR6 - Port A Reset bit 6 - 6 - 1 - - - BR7 - Port A Reset bit 7 - 7 - 1 - - - BR8 - Port A Reset bit 8 - 8 - 1 - - - BR9 - Port A Reset bit 9 - 9 - 1 - - - BR10 - Port A Reset bit 10 - 10 - 1 - - - BR11 - Port A Reset bit 11 - 11 - 1 - - - BR12 - Port A Reset bit 12 - 12 - 1 - - - BR13 - Port A Reset bit 13 - 13 - 1 - - - BR14 - Port A Reset bit 14 - 14 - 1 - - - BR15 - Port A Reset bit 15 - 15 - 1 - - - - - - - SYSCFG - System configuration controller - SYSCFG - 0x40013800 - - 0x0 - 0x400 - registers - - - - MEMRMP - MEMRM - memory remap register - 0x0 - 0x20 - read-write - 0x00000000 - - - MEM_BOOT - Memory mapping selection - 0 - 1 - - - SWP_FMC - FMC memory mapping swap - 10 - 2 - - - - - PMC - PMC - peripheral mode configuration register - 0x4 - 0x20 - read-write - 0x00000000 - - - MII_RMII_SEL - Ethernet PHY interface selection - 23 - 1 - - - ADC1DC2 - ADC1DC2 - 16 - 1 - - - ADC2DC2 - ADC2DC2 - 17 - 1 - - - ADC3DC2 - ADC3DC2 - 18 - 1 - - - - - EXTICR1 - EXTICR1 - external interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - EXTI3 - EXTI x configuration (x = 0 to 3) - 12 - 4 - - - EXTI2 - EXTI x configuration (x = 0 to 3) - 8 - 4 - - - EXTI1 - EXTI x configuration (x = 0 to 3) - 4 - 4 - - - EXTI0 - EXTI x configuration (x = 0 to 3) - 0 - 4 - - - - - EXTICR2 - EXTICR2 - external interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - EXTI7 - EXTI x configuration (x = 4 to 7) - 12 - 4 - - - EXTI6 - EXTI x configuration (x = 4 to 7) - 8 - 4 - - - EXTI5 - EXTI x configuration (x = 4 to 7) - 4 - 4 - - - EXTI4 - EXTI x configuration (x = 4 to 7) - 0 - 4 - - - - - EXTICR3 - EXTICR3 - external interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x00000000 - - - EXTI11 - EXTI x configuration (x = 8 to 11) - 12 - 4 - - - EXTI10 - EXTI10 - 8 - 4 - - - EXTI9 - EXTI x configuration (x = 8 to 11) - 4 - 4 - - - EXTI8 - EXTI x configuration (x = 8 to 11) - 0 - 4 - - - - - EXTICR4 - EXTICR4 - external interrupt configuration register 4 - 0x14 - 0x20 - read-write - 0x00000000 - - - EXTI15 - EXTI x configuration (x = 12 to 15) - 12 - 4 - - - EXTI14 - EXTI x configuration (x = 12 to 15) - 8 - 4 - - - EXTI13 - EXTI x configuration (x = 12 to 15) - 4 - 4 - - - EXTI12 - EXTI x configuration (x = 12 to 15) - 0 - 4 - - - - - CMPCR - CMPCR - Compensation cell control register - 0x20 - 0x20 - read-only - 0x00000000 - - - READY - READY - 8 - 1 - - - CMP_PD - Compensation cell power-down - 0 - 1 - - - - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - BIDIMODE - Bidirectional data mode enable - 15 - 1 - - BIDIMODE - read-write - - Unidirectional - 2-line unidirectional data mode selected - 0 - - - Bidirectional - 1-line bidirectional data mode selected - 1 - - - - - BIDIOE - Output enable in bidirectional mode - 14 - 1 - - BIDIOE - read-write - - OutputDisabled - Output disabled (receive-only mode) - 0 - - - OutputEnabled - Output enabled (transmit-only mode) - 1 - - - - - CRCEN - Hardware CRC calculation enable - 13 - 1 - - CRCEN - read-write - - Disabled - CRC calculation disabled - 0 - - - Enabled - CRC calculation enabled - 1 - - - - - CRCNEXT - CRC transfer next - 12 - 1 - - CRCNEXT - read-write - - TxBuffer - Next transmit value is from Tx buffer - 0 - - - CRC - Next transmit value is from Tx CRC register - 1 - - - - - CRCL - CRC length - 11 - 1 - - CRCL - read-write - - EightBit - 8-bit CRC length - 0 - - - SixteenBit - 16-bit CRC length - 1 - - - - - RXONLY - Receive only - 10 - 1 - - RXONLY - read-write - - FullDuplex - Full duplex (Transmit and receive) - 0 - - - OutputDisabled - Output disabled (Receive-only mode) - 1 - - - - - SSM - Software slave management - 9 - 1 - - SSM - read-write - - Disabled - Software slave management disabled - 0 - - - Enabled - Software slave management enabled - 1 - - - - - SSI - Internal slave select - 8 - 1 - - SSI - read-write - - SlaveSelected - 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored - 0 - - - SlaveNotSelected - 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored - 1 - - - - - LSBFIRST - Frame format - 7 - 1 - - LSBFIRST - read-write - - MSBFirst - Data is transmitted/received with the MSB first - 0 - - - LSBFirst - Data is transmitted/received with the LSB first - 1 - - - - - SPE - SPI enable - 6 - 1 - - SPE - read-write - - Disabled - Peripheral disabled - 0 - - - Enabled - Peripheral enabled - 1 - - - - - BR - Baud rate control - 3 - 3 - - BR - read-write - - Div2 - f_PCLK / 2 - 0 - - - Div4 - f_PCLK / 4 - 1 - - - Div8 - f_PCLK / 8 - 2 - - - Div16 - f_PCLK / 16 - 3 - - - Div32 - f_PCLK / 32 - 4 - - - Div64 - f_PCLK / 64 - 5 - - - Div128 - f_PCLK / 128 - 6 - - - Div256 - f_PCLK / 256 - 7 - - - - - MSTR - Master selection - 2 - 1 - - MSTR - read-write - - Slave - Slave configuration - 0 - - - Master - Master configuration - 1 - - - - - CPOL - Clock polarity - 1 - 1 - - CPOL - read-write - - IdleLow - CK to 0 when idle - 0 - - - IdleHigh - CK to 1 when idle - 1 - - - - - CPHA - Clock phase - 0 - 1 - - CPHA - read-write - - FirstEdge - The first clock transition is the first data capture edge - 0 - - - SecondEdge - The second clock transition is the first data capture edge - 1 - - - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x00000700 - - - RXDMAEN - Rx buffer DMA enable - 0 - 1 - - RXDMAEN - read-write - - Disabled - Rx buffer DMA disabled - 0 - - - Enabled - Rx buffer DMA enabled - 1 - - - - - TXDMAEN - Tx buffer DMA enable - 1 - 1 - - TXDMAEN - read-write - - Disabled - Tx buffer DMA disabled - 0 - - - Enabled - Tx buffer DMA enabled - 1 - - - - - SSOE - SS output enable - 2 - 1 - - SSOE - read-write - - Disabled - SS output is disabled in master mode - 0 - - - Enabled - SS output is enabled in master mode - 1 - - - - - NSSP - NSS pulse management - 3 - 1 - - NSSP - read-write - - NoPulse - No NSS pulse - 0 - - - PulseGenerated - NSS pulse generated - 1 - - - - - FRF - Frame format - 4 - 1 - - FRF - read-write - - Motorola - SPI Motorola mode - 0 - - - TI - SPI TI mode - 1 - - - - - ERRIE - Error interrupt enable - 5 - 1 - - ERRIE - read-write - - Masked - Error interrupt masked - 0 - - - NotMasked - Error interrupt not masked - 1 - - - - - RXNEIE - RX buffer not empty interrupt enable - 6 - 1 - - RXNEIE - read-write - - Masked - RXE interrupt masked - 0 - - - NotMasked - RXE interrupt not masked - 1 - - - - - TXEIE - Tx buffer empty interrupt enable - 7 - 1 - - TXEIE - read-write - - Masked - TXE interrupt masked - 0 - - - NotMasked - TXE interrupt not masked - 1 - - - - - DS - Data size - 8 - 4 - - DS - read-write - - FourBit - 4-bit - 3 - - - FiveBit - 5-bit - 4 - - - SixBit - 6-bit - 5 - - - SevenBit - 7-bit - 6 - - - EightBit - 8-bit - 7 - - - NineBit - 9-bit - 8 - - - TenBit - 10-bit - 9 - - - ElevenBit - 11-bit - 10 - - - TwelveBit - 12-bit - 11 - - - ThirteenBit - 13-bit - 12 - - - FourteenBit - 14-bit - 13 - - - FifteenBit - 15-bit - 14 - - - SixteenBit - 16-bit - 15 - - - - - FRXTH - FIFO reception threshold - 12 - 1 - - FRXTH - read-write - - Half - RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) - 0 - - - Quarter - RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) - 1 - - - - - LDMA_RX - Last DMA transfer for reception - 13 - 1 - - LDMA_RX - read-write - - Even - Number of data to transfer for receive is even - 0 - - - Odd - Number of data to transfer for receive is odd - 1 - - - - - LDMA_TX - Last DMA transfer for transmission - 14 - 1 - - LDMA_TX - read-write - - Even - Number of data to transfer for transmit is even - 0 - - - Odd - Number of data to transfer for transmit is odd - 1 - - - - - - - SR - SR - status register - 0x8 - 0x20 - 0x00000002 - - - FRE - Frame format error - 8 - 1 - read-only - - FRER - read - - NoError - No frame format error - 0 - - - Error - A frame format error occurred - 1 - - - - - BSY - Busy flag - 7 - 1 - read-only - - BSYR - read - - NotBusy - SPI not busy - 0 - - - Busy - SPI busy - 1 - - - - - OVR - Overrun flag - 6 - 1 - read-only - - OVRR - read - - NoOverrun - No overrun occurred - 0 - - - Overrun - Overrun occurred - 1 - - - - - MODF - Mode fault - 5 - 1 - read-only - - MODFR - read - - NoFault - No mode fault occurred - 0 - - - Fault - Mode fault occurred - 1 - - - - - CRCERR - CRC error flag - 4 - 1 - read-write - zeroToClear - - CRCERRR - read - - Match - CRC value received matches the SPIx_RXCRCR value - 0 - - - NoMatch - CRC value received does not match the SPIx_RXCRCR value - 1 - - - - CRCERRW - write - - Clear - Clear flag - 0 - - - - - UDR - Underrun flag - 3 - 1 - read-only - - UDRR - read - - NoUnderrun - No underrun occurred - 0 - - - Underrun - Underrun occurred - 1 - - - - - CHSIDE - Channel side - 2 - 1 - read-only - - CHSIDE - read - - Left - Channel left has to be transmitted or has been received - 0 - - - Right - Channel right has to be transmitted or has been received - 1 - - - - - TXE - Transmit buffer empty - 1 - 1 - read-only - - TXE - read - - NotEmpty - Tx buffer not empty - 0 - - - Empty - Tx buffer empty - 1 - - - - - RXNE - Receive buffer not empty - 0 - 1 - read-only - - RXNE - read - - Empty - Rx buffer empty - 0 - - - NotEmpty - Rx buffer not empty - 1 - - - - - FRLVL - FIFO reception level - 9 - 2 - read-only - - FRLVLR - read - - Empty - Rx FIFO Empty - 0 - - - Quarter - Rx 1/4 FIFO - 1 - - - Half - Rx 1/2 FIFO - 2 - - - Full - Rx FIFO full - 3 - - - - - FTLVL - FIFO Transmission Level - 11 - 2 - read-only - - FTLVLR - read - - Empty - Tx FIFO Empty - 0 - - - Quarter - Tx 1/4 FIFO - 1 - - - Half - Tx 1/2 FIFO - 2 - - - Full - Tx FIFO full - 3 - - - - - - - DR - DR - data register - 0xC - 0x20 - read-write - 0x00000000 - - - DR - Data register - 0 - 16 - - - 0 - 65535 - - - - - - - CRCPR - CRCPR - CRC polynomial register - 0x10 - 0x20 - read-write - 0x00000007 - - - CRCPOLY - CRC polynomial register - 0 - 16 - - - 0 - 65535 - - - - - - - RXCRCR - RXCRCR - RX CRC register - 0x14 - 0x20 - read-only - 0x00000000 - - - RxCRC - Rx CRC register - 0 - 16 - - - 0 - 65535 - - - - - - - TXCRCR - TXCRCR - TX CRC register - 0x18 - 0x20 - read-only - 0x00000000 - - - TxCRC - Tx CRC register - 0 - 16 - - - 0 - 65535 - - - - - - - I2SCFGR - I2SCFGR - I2S configuration register - 0x1C - 0x20 - read-write - 0x00000000 - - - I2SMOD - I2S mode selection - 11 - 1 - - I2SMOD - read-write - - SPIMode - SPI mode is selected - 0 - - - I2SMode - I2S mode is selected - 1 - - - - - I2SE - I2S Enable - 10 - 1 - - I2SE - read-write - - Disabled - I2S peripheral is disabled - 0 - - - Enabled - I2S peripheral is enabled - 1 - - - - - I2SCFG - I2S configuration mode - 8 - 2 - - I2SCFG - read-write - - SlaveTx - Slave - transmit - 0 - - - SlaveRx - Slave - receive - 1 - - - MasterTx - Master - transmit - 2 - - - MasterRx - Master - receive - 3 - - - - - PCMSYNC - PCM frame synchronization - 7 - 1 - - PCMSYNC - read-write - - Short - Short frame synchronisation - 0 - - - Long - Long frame synchronisation - 1 - - - - - I2SSTD - I2S standard selection - 4 - 2 - - I2SSTD - read-write - - Philips - I2S Philips standard - 0 - - - MSB - MSB justified standard - 1 - - - LSB - LSB justified standard - 2 - - - PCM - PCM standard - 3 - - - - - CKPOL - Steady state clock polarity - 3 - 1 - - CKPOL - read-write - - IdleLow - I2S clock inactive state is low level - 0 - - - IdleHigh - I2S clock inactive state is high level - 1 - - - - - DATLEN - Data length to be transferred - 1 - 2 - - DATLEN - read-write - - SixteenBit - 16-bit data length - 0 - - - TwentyFourBit - 24-bit data length - 1 - - - ThirtyTwoBit - 32-bit data length - 2 - - - - - CHLEN - Channel length (number of bits per audio channel) - 0 - 1 - - CHLEN - read-write - - SixteenBit - 16-bit wide - 0 - - - ThirtyTwoBit - 32-bit wide - 1 - - - - - ASTRTEN - Asynchronous start enable - 12 - 1 - - - - - I2SPR - I2SPR - I2S prescaler register - 0x20 - 0x20 - read-write - 0x0000000A - - - MCKOE - Master clock output enable - 9 - 1 - - MCKOE - read-write - - Disabled - Master clock output is disabled - 0 - - - Enabled - Master clock output is enabled - 1 - - - - - ODD - Odd factor for the prescaler - 8 - 1 - - ODD - read-write - - Even - Real divider value is I2SDIV * 2 - 0 - - - Odd - Real divider value is (I2SDIV * 2) + 1 - 1 - - - - - I2SDIV - I2S Linear prescaler - 0 - 8 - - - 2 - 255 - - - - - - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - SPI4 - 0x40013400 - - SPI4 - SPI 4 global interrupt - 84 - - - - SPI5 - 0x40015000 - - SPI5 - SPI 5 global interrupt - 85 - - - - SPI6 - 0x40015400 - - SPI6 - SPI 6 global interrupt - 86 - - - - SPI2 - Serial peripheral interface - SPI - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - ADC1 - Analog-to-digital converter - ADC - 0x40012000 - - 0x0 - 0x100 - registers - - - ADC - ADC1 global interrupt - 18 - - - - SR - SR - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OVR - Overrun - 5 - 1 - - - STRT - Regular channel start flag - 4 - 1 - zeroToClear - - STRTR - read - - NotStarted - No regular channel conversion started - 0 - - - Started - Regular channel conversion has started - 1 - - - - STRTW - write - - Clear - Clear flag - 0 - - - - - JSTRT - Injected channel start flag - 3 - 1 - zeroToClear - - JSTRTR - read - - NotStarted - No injected channel conversion started - 0 - - - Started - Injected channel conversion has started - 1 - - - - JSTRTW - write - - Clear - Clear flag - 0 - - - - - JEOC - Injected channel end of conversion - 2 - 1 - zeroToClear - - JEOCR - read - - NotComplete - Conversion is not complete - 0 - - - Complete - Conversion complete - 1 - - - - JEOCW - write - - Clear - Clear flag - 0 - - - - - EOC - Regular channel end of conversion - 1 - 1 - zeroToClear - - EOCR - read - - NotComplete - Conversion is not complete - 0 - - - Complete - Conversion complete - 1 - - - - EOCW - write - - Clear - Clear flag - 0 - - - - - AWD - Analog watchdog flag - 0 - 1 - zeroToClear - - AWDR - read - - NoEvent - No analog watchdog event occurred - 0 - - - Event - Analog watchdog event occurred - 1 - - - - AWDW - write - - Clear - Clear flag - 0 - - - - - - - CR1 - CR1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OVRIE - Overrun interrupt enable - 26 - 1 - - OVRIE - read-write - - Disabled - Overrun interrupt disabled - 0 - - - Enabled - Overrun interrupt enabled - 1 - - - - - RES - Resolution - 24 - 2 - - RES - read-write - - TwelveBit - 12-bit (15 ADCCLK cycles) - 0 - - - TenBit - 10-bit (13 ADCCLK cycles) - 1 - - - EightBit - 8-bit (11 ADCCLK cycles) - 2 - - - SixBit - 6-bit (9 ADCCLK cycles) - 3 - - - - - AWDEN - Analog watchdog enable on regular channels - 23 - 1 - - AWDEN - read-write - - Disabled - Analog watchdog disabled on regular channels - 0 - - - Enabled - Analog watchdog enabled on regular channels - 1 - - - - - JAWDEN - Analog watchdog enable on injected channels - 22 - 1 - - JAWDEN - read-write - - Disabled - Analog watchdog disabled on injected channels - 0 - - - Enabled - Analog watchdog enabled on injected channels - 1 - - - - - DISCNUM - Discontinuous mode channel count - 13 - 3 - - - 0 - 7 - - - - - JDISCEN - Discontinuous mode on injected channels - 12 - 1 - - JDISCEN - read-write - - Disabled - Discontinuous mode on injected channels disabled - 0 - - - Enabled - Discontinuous mode on injected channels enabled - 1 - - - - - DISCEN - Discontinuous mode on regular channels - 11 - 1 - - DISCEN - read-write - - Disabled - Discontinuous mode on regular channels disabled - 0 - - - Enabled - Discontinuous mode on regular channels enabled - 1 - - - - - JAUTO - Automatic injected group conversion - 10 - 1 - - JAUTO - read-write - - Disabled - Automatic injected group conversion disabled - 0 - - - Enabled - Automatic injected group conversion enabled - 1 - - - - - AWDSGL - Enable the watchdog on a single channel in scan mode - 9 - 1 - - AWDSGL - read-write - - AllChannels - Analog watchdog enabled on all channels - 0 - - - SingleChannel - Analog watchdog enabled on a single channel - 1 - - - - - SCAN - Scan mode - 8 - 1 - - SCAN - read-write - - Disabled - Scan mode disabled - 0 - - - Enabled - Scan mode enabled - 1 - - - - - JEOCIE - Interrupt enable for injected channels - 7 - 1 - - JEOCIE - read-write - - Disabled - JEOC interrupt disabled - 0 - - - Enabled - JEOC interrupt enabled - 1 - - - - - AWDIE - Analog watchdog interrupt enable - 6 - 1 - - AWDIE - read-write - - Disabled - Analogue watchdog interrupt disabled - 0 - - - Enabled - Analogue watchdog interrupt enabled - 1 - - - - - EOCIE - Interrupt enable for EOC - 5 - 1 - - EOCIE - read-write - - Disabled - EOC interrupt disabled - 0 - - - Enabled - EOC interrupt enabled - 1 - - - - - AWDCH - Analog watchdog channel select bits - 0 - 5 - - - 0 - 18 - - - - - - - CR2 - CR2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - SWSTART - Start conversion of regular channels - 30 - 1 - - SWSTARTW - write - - Start - Starts conversion of regular channels - 1 - - - - - EXTEN - External trigger enable for regular channels - 28 - 2 - - EXTEN - read-write - - Disabled - Trigger detection disabled - 0 - - - RisingEdge - Trigger detection on the rising edge - 1 - - - FallingEdge - Trigger detection on the falling edge - 2 - - - BothEdges - Trigger detection on both the rising and falling edges - 3 - - - - - EXTSEL - External event select for regular group - 24 - 4 - - EXTSEL - read-write - - TIM1CH1 - Timer 1 CH1 - 0 - - - TIM1CH2 - Timer 1 CH2 - 1 - - - TIM1CH3 - Timer 1 CH3 - 2 - - - TIM2CH2 - Timer 2 CH2 - 3 - - - TIM5TRGO - Timer 5 TRGO - 4 - - - TIM4CH4 - Timer 4 CH4 - 5 - - - TIM3CH4 - Timer 3 CH4 - 6 - - - TIM8TRGO - Timer 8 TRGO - 7 - - - TIM8TRGO2 - Timer 8 TRGO(2) - 8 - - - TIM1TRGO - Timer 1 TRGO - 9 - - - TIM1TRGO2 - Timer 1 TRGO(2) - 10 - - - TIM2TRGO - Timer 2 TRGO - 11 - - - TIM4TRGO - Timer 4 TRGO - 12 - - - TIM6TRGO - Timer 6 TRGO - 13 - - - EXTI11 - EXTI line 11 - 15 - - - - - JSWSTART - Start conversion of injected channels - 22 - 1 - - JSWSTARTW - write - - Start - Starts conversion of injected channels - 1 - - - - - JEXTEN - External trigger enable for injected channels - 20 - 2 - - JEXTEN - read-write - - Disabled - Trigger detection disabled - 0 - - - RisingEdge - Trigger detection on the rising edge - 1 - - - FallingEdge - Trigger detection on the falling edge - 2 - - - BothEdges - Trigger detection on both the rising and falling edges - 3 - - - - - JEXTSEL - External event select for injected group - 16 - 4 - - JEXTSEL - read-write - - TIM1TRGO - Timer 1 TRGO - 0 - - - TIM1CH4 - Timer 1 CH4 - 1 - - - TIM2TRGO - Timer 2 TRGO - 2 - - - TIM2CH1 - Timer 2 CH1 - 3 - - - TIM3CH4 - Timer 3 CH4 - 4 - - - TIM4TRGO - Timer 4 TRGO - 5 - - - TIM8CH4 - Timer 8 CH4 - 7 - - - TIM1TRGO2 - Timer 1 TRGO(2) - 8 - - - TIM8TRGO - Timer 8 TRGO - 9 - - - TIM8TRGO2 - Timer 8 TRGO(2) - 10 - - - TIM3CH3 - Timer 3 CH3 - 11 - - - TIM5TRGO - Timer 5 TRGO - 12 - - - TIM3CH1 - Timer 3 CH1 - 13 - - - TIM6TRGO - Timer 6 TRGO - 14 - - - - - ALIGN - Data alignment - 11 - 1 - - ALIGN - read-write - - Right - Right alignment - 0 - - - Left - Left alignment - 1 - - - - - EOCS - End of conversion selection - 10 - 1 - - EOCS - read-write - - EachSequence - The EOC bit is set at the end of each sequence of regular conversions - 0 - - - EachConversion - The EOC bit is set at the end of each regular conversion - 1 - - - - - DDS - DMA disable selection (for single ADC mode) - 9 - 1 - - DDS - read-write - - Single - No new DMA request is issued after the last transfer - 0 - - - Continuous - DMA requests are issued as long as data are converted and DMA=1 - 1 - - - - - DMA - Direct memory access mode (for single ADC mode) - 8 - 1 - - DMA - read-write - - Disabled - DMA mode disabled - 0 - - - Enabled - DMA mode enabled - 1 - - - - - CONT - Continuous conversion - 1 - 1 - - CONT - read-write - - Single - Single conversion mode - 0 - - - Continuous - Continuous conversion mode - 1 - - - - - ADON - A/D Converter ON / OFF - 0 - 1 - - ADON - read-write - - Disabled - Disable ADC conversion and go to power down mode - 0 - - - Enabled - Enable ADC - 1 - - - - - - - SMPR1 - SMPR1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - SMPx_x - Sample time bits - 0 - 32 - - SMPx_x - read-write - - Cycles3 - 3 cycles - 0 - - - Cycles15 - 15 cycles - 1 - - - Cycles28 - 28 cycles - 2 - - - Cycles56 - 56 cycles - 3 - - - Cycles84 - 84 cycles - 4 - - - Cycles112 - 112 cycles - 5 - - - Cycles144 - 144 cycles - 6 - - - Cycles480 - 480 cycles - 7 - - - - - - - SMPR2 - SMPR2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - SMPx_x - Sample time bits - 0 - 32 - - SMPx_x - read-write - - Cycles3 - 3 cycles - 0 - - - Cycles15 - 15 cycles - 1 - - - Cycles28 - 28 cycles - 2 - - - Cycles56 - 56 cycles - 3 - - - Cycles84 - 84 cycles - 4 - - - Cycles112 - 112 cycles - 5 - - - Cycles144 - 144 cycles - 6 - - - Cycles480 - 480 cycles - 7 - - - - - - - 4 - 0x4 - 1-4 - JOFR%s - JOFR1 - injected channel data offset register x - 0x14 - 0x20 - read-write - 0x00000000 - - - JOFFSET - Data offset for injected channel x - 0 - 12 - - - 0 - 4095 - - - - - - - HTR - HTR - watchdog higher threshold register - 0x24 - 0x20 - read-write - 0x00000FFF - - - HT - Analog watchdog higher threshold - 0 - 12 - - - 0 - 4095 - - - - - - - LTR - LTR - watchdog lower threshold register - 0x28 - 0x20 - read-write - 0x00000000 - - - LT - Analog watchdog lower threshold - 0 - 12 - - - 0 - 4095 - - - - - - - SQR1 - SQR1 - regular sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - L - Regular channel sequence length - 20 - 4 - - - 0 - 15 - - - - - SQ16 - 16th conversion in regular sequence - 15 - 5 - - - 0 - 18 - - - - - SQ15 - 15th conversion in regular sequence - 10 - 5 - - - 0 - 18 - - - - - SQ14 - 14th conversion in regular sequence - 5 - 5 - - - 0 - 18 - - - - - SQ13 - 13th conversion in regular sequence - 0 - 5 - - - 0 - 18 - - - - - - - SQR2 - SQR2 - regular sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - SQ12 - 12th conversion in regular sequence - 25 - 5 - - - 0 - 18 - - - - - SQ11 - 11th conversion in regular sequence - 20 - 5 - - - 0 - 18 - - - - - SQ10 - 10th conversion in regular sequence - 15 - 5 - - - 0 - 18 - - - - - SQ9 - 9th conversion in regular sequence - 10 - 5 - - - 0 - 18 - - - - - SQ8 - 8th conversion in regular sequence - 5 - 5 - - - 0 - 18 - - - - - SQ7 - 7th conversion in regular sequence - 0 - 5 - - - 0 - 18 - - - - - - - SQR3 - SQR3 - regular sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - SQ6 - 6th conversion in regular sequence - 25 - 5 - - - 0 - 18 - - - - - SQ5 - 5th conversion in regular sequence - 20 - 5 - - - 0 - 18 - - - - - SQ4 - 4th conversion in regular sequence - 15 - 5 - - - 0 - 18 - - - - - SQ3 - 3rd conversion in regular sequence - 10 - 5 - - - 0 - 18 - - - - - SQ2 - 2nd conversion in regular sequence - 5 - 5 - - - 0 - 18 - - - - - SQ1 - 1st conversion in regular sequence - 0 - 5 - - - 0 - 18 - - - - - - - JSQR - JSQR - injected sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - JL - Injected sequence length - 20 - 2 - - - 0 - 3 - - - - - JSQ4 - 4th conversion in injected sequence - 15 - 5 - - - 0 - 18 - - - - - JSQ3 - 3rd conversion in injected sequence - 10 - 5 - - - 0 - 18 - - - - - JSQ2 - 2nd conversion in injected sequence - 5 - 5 - - - 0 - 18 - - - - - JSQ1 - 1st conversion in injected sequence - 0 - 5 - - - 0 - 18 - - - - - - - 4 - 0x4 - 1-4 - JDR%s - JDR1 - injected data register x - 0x3C - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - DR - DR - regular data register - 0x4C - 0x20 - read-only - 0x00000000 - - - DATA - Regular data - 0 - 16 - - - - - - - ADC2 - 0x40012100 - - - ADC3 - 0x40012200 - - - DAC - Digital-to-analog converter - DAC - 0x40007400 - - 0x0 - 0x400 - registers - - - - CR - CR - control register - 0x0 - 0x20 - read-write - 0x00000000 - - - DMAUDRIE2 - DAC channel2 DMA underrun interrupt enable - 29 - 1 - - - - DMAEN2 - DAC channel2 DMA enable - 28 - 1 - - - - MAMP2 - DAC channel2 mask/amplitude selector - 24 - 4 - - - 0 - 15 - - - - - WAVE2 - DAC channel2 noise/triangle wave generation enable - 22 - 2 - - WAVE2 - read-write - - Disabled - Wave generation disabled - 0 - - - Noise - Noise wave generation enabled - 1 - - - Triangle - Triangle wave generation enabled - 2 - - - - - TSEL2 - DAC channel2 trigger selection - 19 - 3 - - TSEL2 - read-write - - TIM6_TRGO - Timer 6 TRGO event - 0 - - - TIM8_TRGO - Timer 8 TRGO event - 1 - - - TIM7_TRGO - Timer 7 TRGO event - 2 - - - TIM5_TRGO - Timer 5 TRGO event - 3 - - - TIM2_TRGO - Timer 2 TRGO event - 4 - - - TIM4_TRGO - Timer 4 TRGO event - 5 - - - EXTI9 - EXTI line9 - 6 - - - SOFTWARE - Software trigger - 7 - - - - - TEN2 - DAC channel2 trigger enable - 18 - 1 - - - - BOFF2 - DAC channel2 output buffer disable - 17 - 1 - - - - EN2 - DAC channel2 enable - 16 - 1 - - - - DMAUDRIE1 - DAC channel1 DMA Underrun Interrupt enable - 13 - 1 - - DMAUDRIE1 - read-write - - Disabled - DAC channel X DMA Underrun Interrupt disabled - 0 - - - Enabled - DAC channel X DMA Underrun Interrupt enabled - 1 - - - - - DMAEN1 - DAC channel1 DMA enable - 12 - 1 - - DMAEN1 - read-write - - Disabled - DAC channel X DMA mode disabled - 0 - - - Enabled - DAC channel X DMA mode enabled - 1 - - - - - MAMP1 - DAC channel1 mask/amplitude selector - 8 - 4 - - - 0 - 15 - - - - - WAVE1 - DAC channel1 noise/triangle wave generation enable - 6 - 2 - - WAVE1 - read-write - - Disabled - Wave generation disabled - 0 - - - Noise - Noise wave generation enabled - 1 - - - Triangle - Triangle wave generation enabled - 2 - - - - - TSEL1 - DAC channel1 trigger selection - 3 - 3 - - TSEL1 - read-write - - TIM6_TRGO - Timer 6 TRGO event - 0 - - - TIM3_TRGO - Timer 3 TRGO event - 1 - - - TIM7_TRGO - Timer 7 TRGO event - 2 - - - TIM15_TRGO - Timer 15 TRGO event - 3 - - - TIM2_TRGO - Timer 2 TRGO event - 4 - - - EXTI9 - EXTI line9 - 6 - - - SOFTWARE - Software trigger - 7 - - - - - TEN1 - DAC channel1 trigger enable - 2 - 1 - - TEN1 - read-write - - Disabled - DAC channel X trigger disabled - 0 - - - Enabled - DAC channel X trigger enabled - 1 - - - - - BOFF1 - DAC channel1 output buffer disable - 1 - 1 - - BOFF1 - read-write - - Enabled - DAC channel X output buffer enabled - 0 - - - Disabled - DAC channel X output buffer disabled - 1 - - - - - EN1 - DAC channel1 enable - 0 - 1 - - EN1 - read-write - - Disabled - DAC channel X disabled - 0 - - - Enabled - DAC channel X enabled - 1 - - - - - - - SWTRIGR - SWTRIGR - software trigger register - 0x4 - 0x20 - write-only - 0x00000000 - - - SWTRIG2 - DAC channel2 software trigger - 1 - 1 - - - - SWTRIG1 - DAC channel1 software trigger - 0 - 1 - - SWTRIG1 - write - - Disabled - DAC channel X software trigger disabled - 0 - - - Enabled - DAC channel X software trigger enabled - 1 - - - - - - - DHR12R1 - DHR12R1 - channel1 12-bit right-aligned data holding register - 0x8 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 12-bit right-aligned data - 0 - 12 - - - 0 - 4095 - - - - - - - DHR12L1 - DHR12L1 - channel1 12-bit left aligned data holding register - 0xC - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 12-bit left-aligned data - 4 - 12 - - - 0 - 4095 - - - - - - - DHR8R1 - DHR8R1 - channel1 8-bit right aligned data holding register - 0x10 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 8-bit right-aligned data - 0 - 8 - - - 0 - 255 - - - - - - - DHR12R2 - DHR12R2 - channel2 12-bit right aligned data holding register - 0x14 - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 12-bit right-aligned data - 0 - 12 - - - 0 - 4095 - - - - - - - DHR12L2 - DHR12L2 - channel2 12-bit left aligned data holding register - 0x18 - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 12-bit left-aligned data - 4 - 12 - - - 0 - 4095 - - - - - - - DHR8R2 - DHR8R2 - channel2 8-bit right-aligned data holding register - 0x1C - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 8-bit right-aligned data - 0 - 8 - - - 0 - 255 - - - - - - - DHR12RD - DHR12RD - Dual DAC 12-bit right-aligned data holding register - 0x20 - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 12-bit right-aligned data - 16 - 12 - - - 0 - 4095 - - - - - DACC1DHR - DAC channel1 12-bit right-aligned data - 0 - 12 - - - 0 - 4095 - - - - - - - DHR12LD - DHR12LD - DUAL DAC 12-bit left aligned data holding register - 0x24 - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 12-bit left-aligned data - 20 - 12 - - - 0 - 4095 - - - - - DACC1DHR - DAC channel1 12-bit left-aligned data - 4 - 12 - - - 0 - 4095 - - - - - - - DHR8RD - DHR8RD - DUAL DAC 8-bit right aligned data holding register - 0x28 - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 8-bit right-aligned data - 8 - 8 - - - 0 - 255 - - - - - DACC1DHR - DAC channel1 8-bit right-aligned data - 0 - 8 - - - 0 - 255 - - - - - - - DOR1 - DOR1 - channel1 data output register - 0x2C - 0x20 - read-only - 0x00000000 - - - DACC1DOR - DAC channel1 data output - 0 - 12 - - - - - DOR2 - DOR2 - channel2 data output register - 0x30 - 0x20 - read-only - 0x00000000 - - - DACC2DOR - DAC channel2 data output - 0 - 12 - - - - - SR - SR - status register - 0x34 - 0x20 - read-write - 0x00000000 - - - DMAUDR2 - DAC channel2 DMA underrun flag - 29 - 1 - - - - DMAUDR1 - DAC channel1 DMA underrun flag - 13 - 1 - - DMAUDR1 - read-write - - NoUnderrun - No DMA underrun error condition occurred for DAC channel X - 0 - - - Underrun - DMA underrun error condition occurred for DAC channel X - 1 - - - - - - - - - PWR - Power control - PWR - 0x40007000 - - 0x0 - 0x400 - registers - - - PVD - PVD through EXTI line detection interrupt - 1 - - - - CR1 - CR1 - power control register - 0x0 - 0x20 - read-write - 0x0000C000 - - - LPDS - Low-power deep sleep - 0 - 1 - - - PDDS - Power down deepsleep - 1 - 1 - - PDDS - read-write - - STOP_MODE - Enter Stop mode when the CPU enters deepsleep - 0 - - - STANDBY_MODE - Enter Standby mode when the CPU enters deepsleep - 1 - - - - - CSBF - Clear standby flag - 3 - 1 - - - PVDE - Power voltage detector enable - 4 - 1 - - - PLS - PVD level selection - 5 - 3 - - - DBP - Disable backup domain write protection - 8 - 1 - - - FPDS - Flash power down in Stop mode - 9 - 1 - - - LPUDS - Low-power regulator in deepsleep under-drive mode - 10 - 1 - - - MRUDS - Main regulator in deepsleep under-drive mode - 11 - 1 - - - ADCDC1 - ADCDC1 - 13 - 1 - - - VOS - Regulator voltage scaling output selection - 14 - 2 - - VOS - read-write - - SCALE3 - Scale 3 mode - 1 - - - SCALE2 - Scale 2 mode - 2 - - - SCALE1 - Scale 1 mode (reset value) - 3 - - - - - ODEN - Over-drive enable - 16 - 1 - - - ODSWEN - Over-drive switching enabled - 17 - 1 - - - UDEN - Under-drive enable in stop mode - 18 - 2 - - - - - CSR1 - CSR1 - power control/status register - 0x4 - 0x20 - 0x00000000 - - - WUIF - Wakeup internal flag - 0 - 1 - read-only - - - SBF - Standby flag - 1 - 1 - read-only - - - PVDO - PVD output - 2 - 1 - read-only - - - BRR - Backup regulator ready - 3 - 1 - read-only - - - BRE - Backup regulator enable - 9 - 1 - read-write - - - VOSRDY - Regulator voltage scaling output selection ready bit - 14 - 1 - read-write - - - ODRDY - Over-drive mode ready - 16 - 1 - read-write - - - ODSWRDY - Over-drive mode switching ready - 17 - 1 - read-write - - - UDRDY - Under-drive ready flag - 18 - 2 - read-write - - - - - CR2 - CR2 - power control register - 0x8 - 0x20 - 0x00000000 - - - CWUPF1 - Clear Wakeup Pin flag for PA0 - 0 - 1 - read-only - - - CWUPF2 - Clear Wakeup Pin flag for PA2 - 1 - 1 - read-only - - - CWUPF3 - Clear Wakeup Pin flag for PC1 - 2 - 1 - read-only - - - CWUPF4 - Clear Wakeup Pin flag for PC13 - 3 - 1 - read-only - - - CWUPF5 - Clear Wakeup Pin flag for PI8 - 4 - 1 - read-only - - - CWUPF6 - Clear Wakeup Pin flag for PI11 - 5 - 1 - read-only - - - WUPP1 - Wakeup pin polarity bit for PA0 - 8 - 1 - read-write - - - WUPP2 - Wakeup pin polarity bit for PA2 - 9 - 1 - read-write - - - WUPP3 - Wakeup pin polarity bit for PC1 - 10 - 1 - read-write - - - WUPP4 - Wakeup pin polarity bit for PC13 - 11 - 1 - read-write - - - WUPP5 - Wakeup pin polarity bit for PI8 - 12 - 1 - read-write - - - WUPP6 - Wakeup pin polarity bit for PI11 - 13 - 1 - read-write - - - - - CSR2 - CSR2 - power control/status register - 0xC - 0x20 - 0x00000000 - - - WUPF1 - Wakeup Pin flag for PA0 - 0 - 1 - read-only - - - WUPF2 - Wakeup Pin flag for PA2 - 1 - 1 - read-only - - - WUPF3 - Wakeup Pin flag for PC1 - 2 - 1 - read-only - - - WUPF4 - Wakeup Pin flag for PC13 - 3 - 1 - read-only - - - WUPF5 - Wakeup Pin flag for PI8 - 4 - 1 - read-only - - - WUPF6 - Wakeup Pin flag for PI11 - 5 - 1 - read-only - - - EWUP1 - Enable Wakeup pin for PA0 - 8 - 1 - read-write - - - EWUP2 - Enable Wakeup pin for PA2 - 9 - 1 - read-write - - - EWUP3 - Enable Wakeup pin for PC1 - 10 - 1 - read-write - - - EWUP4 - Enable Wakeup pin for PC13 - 11 - 1 - read-write - - - EWUP5 - Enable Wakeup pin for PI8 - 12 - 1 - read-write - - - EWUP6 - Enable Wakeup pin for PI11 - 13 - 1 - read-write - - - - - - - IWDG - Independent watchdog - IWDG - 0x40003000 - - 0x0 - 0x400 - registers - - - - KR - KR - Key register - 0x0 - 0x20 - write-only - 0x00000000 - - - KEY - Key value (write only, read 0000h) - 0 - 16 - - KEY - write - - Enable - Enable access to PR, RLR and WINR registers (0x5555) - 21845 - - - Reset - Reset the watchdog value (0xAAAA) - 43690 - - - Start - Start the watchdog (0xCCCC) - 52428 - - - - - - - PR - PR - Prescaler register - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Prescaler divider - 0 - 3 - - PR - read-write - - DivideBy4 - Divider /4 - 0 - - - DivideBy8 - Divider /8 - 1 - - - DivideBy16 - Divider /16 - 2 - - - DivideBy32 - Divider /32 - 3 - - - DivideBy64 - Divider /64 - 4 - - - DivideBy128 - Divider /128 - 5 - - - DivideBy256 - Divider /256 - 6 - - - DivideBy256bis - Divider /256 - 7 - - - - - - - RLR - RLR - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RL - Watchdog counter reload value - 0 - 12 - - - 0 - 4095 - - - - - - - SR - SR - Status register - 0xC - 0x20 - read-only - 0x00000000 - - - RVU - Watchdog counter reload value update - 1 - 1 - - - PVU - Watchdog prescaler value update - 0 - 1 - - - - - WINR - WINR - Window register - 0x10 - 0x20 - read-write - 0x00000000 - - - WIN - Watchdog counter window value - 0 - 12 - - - 0 - 4095 - - - - - - - - - WWDG - Window watchdog - WWDG - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDG - Window Watchdog interrupt - 0 - - - - CR - CR - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - WDGA - Activation bit - 7 - 1 - - WDGA - read-write - - Disabled - Watchdog disabled - 0 - - - Enabled - Watchdog enabled - 1 - - - - - T - 7-bit counter (MSB to LSB) - 0 - 7 - - - 0 - 127 - - - - - - - CFR - CFR - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - EWI - Early wakeup interrupt - 9 - 1 - - EWIW - write - - Enable - interrupt occurs whenever the counter reaches the value 0x40 - 1 - - - - - W - 7-bit window value - 0 - 7 - - - 0 - 127 - - - - - WDGTB - Timer base - 7 - 2 - - WDGTB - read-write - - Div1 - Counter clock (PCLK1 div 4096) div 1 - 0 - - - Div2 - Counter clock (PCLK1 div 4096) div 2 - 1 - - - Div4 - Counter clock (PCLK1 div 4096) div 4 - 2 - - - Div8 - Counter clock (PCLK1 div 4096) div 8 - 3 - - - - - - - SR - SR - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - EWIF - Early wakeup interrupt flag - 0 - 1 - zeroToClear - - EWIFR - read - - Finished - The EWI Interrupt Service Routine has been serviced - 0 - - - Pending - The EWI Interrupt Service Routine has been triggered - 1 - - - - EWIFW - write - - Finished - The EWI Interrupt Service Routine has been serviced - 0 - - - - - - - - - ADC_Common - Common ADC registers - ADC_Common - 0x40012300 - - 0x0 - 0x400 - registers - - - - CSR - CSR - ADC Common status register - 0x0 - 0x20 - read-only - 0x00000000 - - - OVR3 - Overrun flag of ADC3 - 21 - 1 - - - - STRT3 - Regular channel Start flag of ADC 3 - 20 - 1 - - - - JSTRT3 - Injected channel Start flag of ADC 3 - 19 - 1 - - - - JEOC3 - Injected channel end of conversion of ADC 3 - 18 - 1 - - - - EOC3 - End of conversion of ADC 3 - 17 - 1 - - - - AWD3 - Analog watchdog flag of ADC 3 - 16 - 1 - - - - OVR2 - Overrun flag of ADC 2 - 13 - 1 - - - - STRT2 - Regular channel Start flag of ADC 2 - 12 - 1 - - - - JSTRT2 - Injected channel Start flag of ADC 2 - 11 - 1 - - - - JEOC2 - Injected channel end of conversion of ADC 2 - 10 - 1 - - - - EOC2 - End of conversion of ADC 2 - 9 - 1 - - - - AWD2 - Analog watchdog flag of ADC 2 - 8 - 1 - - - - OVR1 - Overrun flag of ADC 1 - 5 - 1 - - OVR1 - read - - NoOverrun - No overrun occurred - 0 - - - Overrun - Overrun occurred - 1 - - - - - STRT1 - Regular channel Start flag of ADC 1 - 4 - 1 - - STRT1 - read - - NotStarted - No regular channel conversion started - 0 - - - Started - Regular channel conversion has started - 1 - - - - - JSTRT1 - Injected channel Start flag of ADC 1 - 3 - 1 - - JSTRT1 - read - - NotStarted - No injected channel conversion started - 0 - - - Started - Injected channel conversion has started - 1 - - - - - JEOC1 - Injected channel end of conversion of ADC 1 - 2 - 1 - - JEOC1 - read - - NotComplete - Conversion is not complete - 0 - - - Complete - Conversion complete - 1 - - - - - EOC1 - End of conversion of ADC 1 - 1 - 1 - - EOC1 - read - - NotComplete - Conversion is not complete - 0 - - - Complete - Conversion complete - 1 - - - - - AWD1 - Analog watchdog flag of ADC 1 - 0 - 1 - - AWD1 - read - - NoEvent - No analog watchdog event occurred - 0 - - - Event - Analog watchdog event occurred - 1 - - - - - - - CCR - CCR - ADC common control register - 0x4 - 0x20 - read-write - 0x00000000 - - - TSVREFE - Temperature sensor and VREFINT enable - 23 - 1 - - TSVREFE - read-write - - Disabled - Temperature sensor and V_REFINT channel disabled - 0 - - - Enabled - Temperature sensor and V_REFINT channel enabled - 1 - - - - - VBATE - VBAT enable - 22 - 1 - - VBATE - read-write - - Disabled - V_BAT channel disabled - 0 - - - Enabled - V_BAT channel enabled - 1 - - - - - ADCPRE - ADC prescaler - 16 - 2 - - ADCPRE - read-write - - Div2 - PCLK2 divided by 2 - 0 - - - Div4 - PCLK2 divided by 4 - 1 - - - Div6 - PCLK2 divided by 6 - 2 - - - Div8 - PCLK2 divided by 8 - 3 - - - - - DMA - Direct memory access mode for multi ADC mode - 14 - 2 - - DMA - read-write - - Disabled - DMA mode disabled - 0 - - - Mode1 - DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3) - 1 - - - Mode2 - DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) - 2 - - - Mode3 - DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) - 3 - - - - - DDS - DMA disable selection for multi-ADC mode - 13 - 1 - - DDS - read-write - - Single - No new DMA request is issued after the last transfer - 0 - - - Continuous - DMA requests are issued as long as data are converted and DMA=01, 10 or 11 - 1 - - - - - DELAY - Delay between 2 sampling phases - 8 - 4 - - - 0 - 15 - - - - - MULTI - Multi ADC mode selection - 0 - 5 - - MULTI - read-write - - Independent - All the ADCs independent: independent mode - 0 - - - DualRJ - Dual ADC1 and ADC2, combined regular and injected simultaneous mode - 1 - - - DualRA - Dual ADC1 and ADC2, combined regular and alternate trigger mode - 2 - - - DualJ - Dual ADC1 and ADC2, injected simultaneous mode only - 5 - - - DualR - Dual ADC1 and ADC2, regular simultaneous mode only - 6 - - - DualI - Dual ADC1 and ADC2, interleaved mode only - 7 - - - DualA - Dual ADC1 and ADC2, alternate trigger mode only - 9 - - - TripleRJ - Triple ADC, regular and injected simultaneous mode - 17 - - - TripleRA - Triple ADC, regular and alternate trigger mode - 18 - - - TripleJ - Triple ADC, injected simultaneous mode only - 21 - - - TripleR - Triple ADC, regular simultaneous mode only - 22 - - - TripleI - Triple ADC, interleaved mode only - 23 - - - TripleA - Triple ADC, alternate trigger mode only - 24 - - - - - - - CDR - CDR - ADC common regular data register for dual and triple modes - 0x8 - 0x20 - read-only - 0x00000000 - - - DATA2 - 2nd data item of a pair of regular conversions - 16 - 16 - - - DATA1 - 1st data item of a pair of regular conversions - 0 - 16 - - - - - - - TIM1 - Advanced-timers - TIM - 0x40010000 - - 0x0 - 0x400 - registers - - - TIM1_BRK_TIM9 - TIM1 Break interrupt and TIM9 global - interrupt - 24 - - - TIM1_UP_TIM10 - TIM1 Update interrupt and TIM10 - 25 - - - TIM1_TRG_COM_TIM11 - TIM1 Trigger and Commutation interrupts and - TIM11 global interrupt - 26 - - - TIM1_CC - TIM1 Capture Compare interrupt - 27 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - CKD - Clock division - 8 - 2 - - CKD - read-write - - Div1 - t_DTS = t_CK_INT - 0 - - - Div2 - t_DTS = 2 Γ— t_CK_INT - 1 - - - Div4 - t_DTS = 4 Γ— t_CK_INT - 2 - - - - - ARPE - Auto-reload preload enable - 7 - 1 - - ARPE - read-write - - Disabled - TIMx_APRR register is not buffered - 0 - - - Enabled - TIMx_APRR register is buffered - 1 - - - - - CMS - Center-aligned mode selection - 5 - 2 - - CMS - read-write - - EdgeAligned - The counter counts up or down depending on the direction bit - 0 - - - CenterAligned1 - The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. - 1 - - - CenterAligned2 - The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. - 2 - - - CenterAligned3 - The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. - 3 - - - - - DIR - Direction - 4 - 1 - - DIR - read-write - - Up - Counter used as upcounter - 0 - - - Down - Counter used as downcounter - 1 - - - - - OPM - One-pulse mode - 3 - 1 - - OPM - read-write - - Disabled - Counter is not stopped at update event - 0 - - - Enabled - Counter stops counting at the next update event (clearing the CEN bit) - 1 - - - - - URS - Update request source - 2 - 1 - - URS - read-write - - AnyEvent - Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - 0 - - - CounterOnly - Only counter overflow/underflow generates an update interrupt or DMA request - 1 - - - - - UDIS - Update disable - 1 - 1 - - UDIS - read-write - - Enabled - Update event enabled - 0 - - - Disabled - Update event disabled - 1 - - - - - CEN - Counter enable - 0 - 1 - - CEN - read-write - - Disabled - Counter disabled - 0 - - - Enabled - Counter enabled - 1 - - - - - UIFREMAP - UIF status bit remapping - 11 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - OIS4 - Output Idle state 4 - 14 - 1 - - - - OIS3N - Output Idle state 3 - 13 - 1 - - - - OIS3 - Output Idle state 3 - 12 - 1 - - - - OIS2N - Output Idle state 2 - 11 - 1 - - - - OIS2 - Output Idle state 2 - 10 - 1 - - - - OIS1N - Output Idle state 1 - 9 - 1 - - OIS1N - read-write - - Reset - OCxN=0 after a dead-time when MOE=0 - 0 - - - Set - OCxN=1 after a dead-time when MOE=0 - 1 - - - - - OIS1 - Output Idle state 1 - 8 - 1 - - OIS1 - read-write - - Reset - OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 - 0 - - - Set - OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 - 1 - - - - - TI1S - TI1 selection - 7 - 1 - - TI1S - read-write - - Normal - The TIMx_CH1 pin is connected to TI1 input - 0 - - - XOR - The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - 1 - - - - - MMS - Master mode selection - 4 - 3 - - MMS - read-write - - Reset - The UG bit from the TIMx_EGR register is used as trigger output - 0 - - - Enable - The counter enable signal, CNT_EN, is used as trigger output - 1 - - - Update - The update event is selected as trigger output - 2 - - - ComparePulse - The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - 3 - - - CompareOC1 - OC1REF signal is used as trigger output - 4 - - - CompareOC2 - OC2REF signal is used as trigger output - 5 - - - CompareOC3 - OC3REF signal is used as trigger output - 6 - - - CompareOC4 - OC4REF signal is used as trigger output - 7 - - - - - CCDS - Capture/compare DMA selection - 3 - 1 - - CCDS - read-write - - OnCompare - CCx DMA request sent when CCx event occurs - 0 - - - OnUpdate - CCx DMA request sent when update event occurs - 1 - - - - - CCUS - Capture/compare control update selection - 2 - 1 - - - CCPC - Capture/compare preloaded control - 0 - 1 - - - OIS5 - Output Idle state 5 (OC5 output) - 16 - 1 - - - - OIS6 - Output Idle state 6 (OC6 output) - 18 - 1 - - - - MMS2 - Master mode selection 2 - 20 - 4 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x00000000 - - - SMS_3 - Slave model selection - bit[3] - 16 - 1 - - - ETP - External trigger polarity - 15 - 1 - - ETP - read-write - - NotInverted - ETR is noninverted, active at high level or rising edge - 0 - - - Inverted - ETR is inverted, active at low level or falling edge - 1 - - - - - ECE - External clock enable - 14 - 1 - - ECE - read-write - - Disabled - External clock mode 2 disabled - 0 - - - Enabled - External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. - 1 - - - - - ETPS - External trigger prescaler - 12 - 2 - - ETPS - read-write - - Div1 - Prescaler OFF - 0 - - - Div2 - ETRP frequency divided by 2 - 1 - - - Div4 - ETRP frequency divided by 4 - 2 - - - Div8 - ETRP frequency divided by 8 - 3 - - - - - ETF - External trigger filter - 8 - 4 - - ETF - read-write - - NoFilter - No filter, sampling is done at fDTS - 0 - - - FCK_INT_N2 - fSAMPLING=fCK_INT, N=2 - 1 - - - FCK_INT_N4 - fSAMPLING=fCK_INT, N=4 - 2 - - - FCK_INT_N8 - fSAMPLING=fCK_INT, N=8 - 3 - - - FDTS_Div2_N6 - fSAMPLING=fDTS/2, N=6 - 4 - - - FDTS_Div2_N8 - fSAMPLING=fDTS/2, N=8 - 5 - - - FDTS_Div4_N6 - fSAMPLING=fDTS/4, N=6 - 6 - - - FDTS_Div4_N8 - fSAMPLING=fDTS/4, N=8 - 7 - - - FDTS_Div8_N6 - fSAMPLING=fDTS/8, N=6 - 8 - - - FDTS_Div8_N8 - fSAMPLING=fDTS/8, N=8 - 9 - - - FDTS_Div16_N5 - fSAMPLING=fDTS/16, N=5 - 10 - - - FDTS_Div16_N6 - fSAMPLING=fDTS/16, N=6 - 11 - - - FDTS_Div16_N8 - fSAMPLING=fDTS/16, N=8 - 12 - - - FDTS_Div32_N5 - fSAMPLING=fDTS/32, N=5 - 13 - - - FDTS_Div32_N6 - fSAMPLING=fDTS/32, N=6 - 14 - - - FDTS_Div32_N8 - fSAMPLING=fDTS/32, N=8 - 15 - - - - - MSM - Master/Slave mode - 7 - 1 - - MSM - read-write - - NoSync - No action - 0 - - - Sync - The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - 1 - - - - - TS - Trigger selection - 4 - 3 - - TS - read-write - - ITR0 - Internal Trigger 0 (ITR0) - 0 - - - ITR1 - Internal Trigger 1 (ITR1) - 1 - - - ITR2 - Internal Trigger 2 (ITR2) - 2 - - - TI1F_ED - TI1 Edge Detector (TI1F_ED) - 4 - - - TI1FP1 - Filtered Timer Input 1 (TI1FP1) - 5 - - - TI2FP2 - Filtered Timer Input 2 (TI2FP2) - 6 - - - ETRF - External Trigger input (ETRF) - 7 - - - - - SMS - Slave mode selection - bit[2:0] - 0 - 3 - - SMS - read-write - - Disabled - Slave mode disabled - if CEN = β€˜1 then the prescaler is clocked directly by the internal clock. - 0 - - - Encoder_Mode_1 - Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - 1 - - - Encoder_Mode_2 - Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - 2 - - - Encoder_Mode_3 - Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - 3 - - - Reset_Mode - Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - 4 - - - Gated_Mode - Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - 5 - - - Trigger_Mode - Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - 6 - - - Ext_Clock_Mode - External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - 7 - - - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x00000000 - - - TDE - Trigger DMA request enable - 14 - 1 - - TDE - read-write - - Disabled - Trigger DMA request disabled - 0 - - - Enabled - Trigger DMA request enabled - 1 - - - - - COMDE - COM DMA request enable - 13 - 1 - - - CC4DE - Capture/Compare 4 DMA request enable - 12 - 1 - - - - CC3DE - Capture/Compare 3 DMA request enable - 11 - 1 - - - - CC2DE - Capture/Compare 2 DMA request enable - 10 - 1 - - - - CC1DE - Capture/Compare 1 DMA request enable - 9 - 1 - - CC1DE - read-write - - Disabled - CCx DMA request disabled - 0 - - - Enabled - CCx DMA request enabled - 1 - - - - - UDE - Update DMA request enable - 8 - 1 - - UDE - read-write - - Disabled - Update DMA request disabled - 0 - - - Enabled - Update DMA request enabled - 1 - - - - - TIE - Trigger interrupt enable - 6 - 1 - - TIE - read-write - - Disabled - Trigger interrupt disabled - 0 - - - Enabled - Trigger interrupt enabled - 1 - - - - - CC4IE - Capture/Compare 4 interrupt enable - 4 - 1 - - - - CC3IE - Capture/Compare 3 interrupt enable - 3 - 1 - - - - CC2IE - Capture/Compare 2 interrupt enable - 2 - 1 - - - - CC1IE - Capture/Compare 1 interrupt enable - 1 - 1 - - CC1IE - read-write - - Disabled - CCx interrupt disabled - 0 - - - Enabled - CCx interrupt enabled - 1 - - - - - UIE - Update interrupt enable - 0 - 1 - - UIE - read-write - - Disabled - Update interrupt disabled - 0 - - - Enabled - Update interrupt enabled - 1 - - - - - BIE - Break interrupt enable - 7 - 1 - - - COMIE - COM interrupt enable - 5 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x00000000 - - - CC4OF - Capture/Compare 4 overcapture flag - 12 - 1 - zeroToClear - - read - - - write - - - - CC3OF - Capture/Compare 3 overcapture flag - 11 - 1 - zeroToClear - - read - - - write - - - - CC2OF - Capture/compare 2 overcapture flag - 10 - 1 - zeroToClear - - read - - - write - - - - CC1OF - Capture/Compare 1 overcapture flag - 9 - 1 - zeroToClear - - CC1OFR - read - - Overcapture - The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set - 1 - - - - CC1OFW - write - - Clear - Clear flag - 0 - - - - - BIF - Break interrupt flag - 7 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - zeroToClear - - TIFR - read - - NoTrigger - No trigger event occurred - 0 - - - Trigger - Trigger interrupt pending - 1 - - - - TIFW - write - - Clear - Clear flag - 0 - - - - - COMIF - COM interrupt flag - 5 - 1 - - - CC4IF - Capture/Compare 4 interrupt flag - 4 - 1 - zeroToClear - - read - - - write - - - - CC3IF - Capture/Compare 3 interrupt flag - 3 - 1 - zeroToClear - - read - - - write - - - - CC2IF - Capture/Compare 2 interrupt flag - 2 - 1 - zeroToClear - - read - - - write - - - - CC1IF - Capture/compare 1 interrupt flag - 1 - 1 - zeroToClear - - CC1IFR - read - - Match - If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. - 1 - - - - CC1IFW - write - - Clear - Clear flag - 0 - - - - - UIF - Update interrupt flag - 0 - 1 - zeroToClear - - UIFR - read - - NoUpdateOccurred - No update occurred - 0 - - - UpdatePending - Update interrupt pending - 1 - - - - UIFW - write - - Clear - Clear flag - 0 - - - - - B2IF - Break 2 interrupt flag - 8 - 1 - - - CC5IF - Compare 5 interrupt flag - 16 - 1 - - - CC6IF - Compare 6 interrupt flag - 17 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x00000000 - - - BG - Break generation - 7 - 1 - - - TG - Trigger generation - 6 - 1 - - TGW - write - - Trigger - The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. - 1 - - - - - COMG - Capture/Compare control update generation - 5 - 1 - - - CC4G - Capture/compare 4 generation - 4 - 1 - - - - CC3G - Capture/compare 3 generation - 3 - 1 - - - - CC2G - Capture/compare 2 generation - 2 - 1 - - - - CC1G - Capture/compare 1 generation - 1 - 1 - - CC1GW - write - - Trigger - If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. - 1 - - - - - UG - Update generation - 0 - 1 - - UG - write - - Update - Re-initializes the timer counter and generates an update of the registers. - 1 - - - - - B2G - Break 2 generation - 8 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - Output Compare 2 clear enable - 15 - 1 - - - OC2M - Output Compare 2 mode - 12 - 3 - - - - OC2PE - Output Compare 2 preload enable - 11 - 1 - - OC2PE - read-write - - Disabled - Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately - 0 - - - Enabled - Preload register on CCR2 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC2FE - Output Compare 2 fast enable - 10 - 1 - - - CC2S - Capture/Compare 2 selection - 8 - 2 - - CC2S - read-write - - Output - CC2 channel is configured as output - 0 - - - - - OC1CE - Output Compare 1 clear enable - 7 - 1 - - - OC1M - Output Compare 1 mode - 4 - 3 - - OC1M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved - 3 - - - ForceInactive - OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF - 4 - - - ForceActive - OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down - 6 - - - PwmMode2 - Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 - 7 - - - - - OC1PE - Output Compare 1 preload enable - 3 - 1 - - OC1PE - read-write - - Disabled - Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately - 0 - - - Enabled - Preload register on CCR1 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC1FE - Output Compare 1 fast enable - 2 - 1 - - - CC1S - Capture/Compare 1 selection - 0 - 2 - - CC1S - read-write - - Output - CC1 channel is configured as output - 0 - - - - - OC2M_3 - Output Compare 2 mode, bit 3 - 24 - 1 - - - - OC1M_3 - Output Compare 1 mode, bit 3 - 16 - 1 - - OC1M_3 - read-write - - Normal - Normal output compare mode (modes 0-7) - 0 - - - Extended - Extended output compare mode (modes 7-15) - 1 - - - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - 0 - 15 - - - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 selection - 8 - 2 - - CC2S - read-write - - TI2 - CC2 channel is configured as input, IC2 is mapped on TI2 - 1 - - - TI1 - CC2 channel is configured as input, IC2 is mapped on TI1 - 2 - - - TRC - CC2 channel is configured as input, IC2 is mapped on TRC - 3 - - - - - IC1F - Input capture 1 filter - 4 - 4 - - IC1F - read-write - - NoFilter - No filter, sampling is done at fDTS - 0 - - - FCK_INT_N2 - fSAMPLING=fCK_INT, N=2 - 1 - - - FCK_INT_N4 - fSAMPLING=fCK_INT, N=4 - 2 - - - FCK_INT_N8 - fSAMPLING=fCK_INT, N=8 - 3 - - - FDTS_Div2_N6 - fSAMPLING=fDTS/2, N=6 - 4 - - - FDTS_Div2_N8 - fSAMPLING=fDTS/2, N=8 - 5 - - - FDTS_Div4_N6 - fSAMPLING=fDTS/4, N=6 - 6 - - - FDTS_Div4_N8 - fSAMPLING=fDTS/4, N=8 - 7 - - - FDTS_Div8_N6 - fSAMPLING=fDTS/8, N=6 - 8 - - - FDTS_Div8_N8 - fSAMPLING=fDTS/8, N=8 - 9 - - - FDTS_Div16_N5 - fSAMPLING=fDTS/16, N=5 - 10 - - - FDTS_Div16_N6 - fSAMPLING=fDTS/16, N=6 - 11 - - - FDTS_Div16_N8 - fSAMPLING=fDTS/16, N=8 - 12 - - - FDTS_Div32_N5 - fSAMPLING=fDTS/32, N=5 - 13 - - - FDTS_Div32_N6 - fSAMPLING=fDTS/32, N=6 - 14 - - - FDTS_Div32_N8 - fSAMPLING=fDTS/32, N=8 - 15 - - - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 selection - 0 - 2 - - CC1S - read-write - - TI1 - CC1 channel is configured as input, IC1 is mapped on TI1 - 1 - - - TI2 - CC1 channel is configured as input, IC1 is mapped on TI2 - 2 - - - TRC - CC1 channel is configured as input, IC1 is mapped on TRC - 3 - - - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register 2 (output mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - Output compare 4 clear enable - 15 - 1 - - - OC4M - Output compare 4 mode - 12 - 3 - - - - OC4PE - Output compare 4 preload enable - 11 - 1 - - OC4PE - read-write - - Disabled - Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately - 0 - - - Enabled - Preload register on CCR4 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC4FE - Output compare 4 fast enable - 10 - 1 - - - CC4S - Capture/Compare 4 selection - 8 - 2 - - CC4S - read-write - - Output - CC4 channel is configured as output - 0 - - - - - OC3CE - Output compare 3 clear enable - 7 - 1 - - - OC3M - Output compare 3 mode - 4 - 3 - - OC3M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved - 3 - - - ForceInactive - OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF - 4 - - - ForceActive - OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down - 6 - - - PwmMode2 - Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 - 7 - - - - - OC3PE - Output compare 3 preload enable - 3 - 1 - - OC3PE - read-write - - Disabled - Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately - 0 - - - Enabled - Preload register on CCR3 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC3FE - Output compare 3 fast enable - 2 - 1 - - - CC3S - Capture/Compare 3 selection - 0 - 2 - - CC3S - read-write - - Output - CC3 channel is configured as output - 0 - - - - - OC3M_3 - Output Compare 3 mode, bit 3 - 16 - 1 - - OC3M_3 - read-write - - Normal - Normal output compare mode (modes 0-7) - 0 - - - Extended - Extended output compare mode (modes 7-15) - 1 - - - - - OC4M_3 - Output Compare 4 mode, bit 3 - 24 - 1 - - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - 0 - 15 - - - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - 0 - 3 - - - - - CC4S - Capture/Compare 4 selection - 8 - 2 - - CC4S - read-write - - TI4 - CC4 channel is configured as input, IC4 is mapped on TI4 - 1 - - - TI3 - CC4 channel is configured as input, IC4 is mapped on TI3 - 2 - - - TRC - CC4 channel is configured as input, IC4 is mapped on TRC - 3 - - - - - IC3F - Input capture 3 filter - 4 - 4 - - - 0 - 15 - - - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - 0 - 3 - - - - - CC3S - Capture/compare 3 selection - 0 - 2 - - CC3S - read-write - - TI3 - CC3 channel is configured as input, IC3 is mapped on TI3 - 1 - - - TI4 - CC3 channel is configured as input, IC3 is mapped on TI4 - 2 - - - TRC - CC3 channel is configured as input, IC3 is mapped on TRC - 3 - - - - - - - CCER - CCER - capture/compare enable register - 0x20 - 0x20 - read-write - 0x00000000 - - - CC4P - Capture/Compare 3 output Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output enable - 12 - 1 - - - CC3NP - Capture/Compare 3 output Polarity - 11 - 1 - - - CC3NE - Capture/Compare 3 complementary output enable - 10 - 1 - - - CC3P - Capture/Compare 3 output Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output enable - 8 - 1 - - - CC2NP - Capture/Compare 2 output Polarity - 7 - 1 - - - CC2NE - Capture/Compare 2 complementary output enable - 6 - 1 - - - CC2P - Capture/Compare 2 output Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output Polarity - 3 - 1 - - - CC1NE - Capture/Compare 1 complementary output enable - 2 - 1 - - - CC1P - Capture/Compare 1 output Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output enable - 0 - 1 - - - CC5E - Capture/Compare 5 output enable - 16 - 1 - - - CC5P - Capture/Compare 5 output polarity - 17 - 1 - - - CC6E - Capture/Compare 6 output enable - 20 - 1 - - - CC6P - Capture/Compare 6 output polarity - 21 - 1 - - - CC4NP - Capture/Compare 4 complementary output polarity - 15 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - 0 - 65535 - - - - - UIFCPY - UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 - - 31 - 1 - read-only - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x00000000 - - - PSC - Prescaler value - 0 - 16 - - - 0 - 65535 - - - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - 0 - 65535 - - - - - - - 4 - 0x4 - 1-4 - CCR%s - CCR1 - capture/compare register - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR - Capture/Compare value - 0 - 16 - - - 0 - 65535 - - - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x00000000 - - - DBL - DMA burst length - 8 - 5 - - - 0 - 18 - - - - - DBA - DMA base address - 0 - 5 - - - 0 - 31 - - - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x00000000 - - - DMAB - DMA register for burst accesses - 0 - 32 - - - - - RCR - RCR - repetition counter register - 0x30 - 0x20 - read-write - 0x00000000 - - - REP - Repetition counter value - 0 - 8 - - - - - BDTR - BDTR - break and dead-time register - 0x44 - 0x20 - read-write - 0x00000000 - - - MOE - Main output enable - 15 - 1 - - MOE - read-write - - DisabledIdle - OC/OCN are disabled or forced idle depending on OSSI - 0 - - - Enabled - OC/OCN are enabled if CCxE/CCxNE are set - 1 - - - - - AOE - Automatic output enable - 14 - 1 - - AOE - read-write - - Manual - MOE can be set only by software - 0 - - - Automatic - MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) - 1 - - - - - BKP - Break polarity - 13 - 1 - - BKP - read-write - - ActiveLow - Break input BRKx is active low - 0 - - - ActiveHigh - Break input BRKx is active high - 1 - - - - - BKE - Break enable - 12 - 1 - - BKE - read-write - - Disabled - Break function x disabled - 0 - - - Enabled - Break function x disabled - 1 - - - - - OSSR - Off-state selection for Run mode - 11 - 1 - - OSSR - read-write - - Disabled - When inactive, OC/OCN outputs are disabled - 0 - - - IdleLevel - When inactive, OC/OCN outputs are enabled with their inactive level - 1 - - - - - OSSI - Off-state selection for Idle mode - 10 - 1 - - OSSI - read-write - - Disabled - When inactive, OC/OCN outputs are disabled - 0 - - - IdleLevel - When inactive, OC/OCN outputs are forced to idle level - 1 - - - - - LOCK - Lock configuration - 8 - 2 - - LOCK - read-write - - Off - No bit is write protected - 0 - - - Level1 - Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written - 1 - - - Level2 - LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written - 2 - - - Level3 - LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written - 3 - - - - - DTG - Dead-time generator setup - 0 - 8 - - - 0 - 255 - - - - - BKF - Break filter - 16 - 4 - - - BK2F - Break 2 filter - 20 - 4 - - - BK2E - Break 2 enable - 24 - 1 - - - - BK2P - Break 2 polarity - 25 - 1 - - - - - - CCMR3_Output - CCMR3_Output - capture/compare mode register 3 (output mode) - 0x54 - 0x20 - read-write - 0x00000000 - - - OC5FE - Output compare 5 fast enable - 2 - 1 - - - OC5PE - Output compare 5 preload enable - 3 - 1 - - - OC5M - Output compare 5 mode - 4 - 3 - - OC5M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved - 3 - - - ForceInactive - OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF - 4 - - - ForceActive - OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down - 6 - - - PwmMode2 - Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 - 7 - - - - - OC5CE - Output compare 5 clear enable - 7 - 1 - - - OC6FE - Output compare 6 fast enable - 10 - 1 - - - OC6PE - Output compare 6 preload enable - 11 - 1 - - - OC6M - Output compare 6 mode - 12 - 3 - - - - OC6CE - Output compare 6 clear enable - 15 - 1 - - - OC5M_3 - Output Compare 5 mode - 16 - 1 - - OC5M_3 - read-write - - Normal - Normal output compare mode (modes 0-7) - 0 - - - Extended - Extended output compare mode (modes 7-15) - 1 - - - - - OC6M_3 - Output Compare 6 mode - 24 - 1 - - - - - - CCR5 - CCR5 - capture/compare register - 0x58 - 0x20 - read-write - 0x00000000 - - - CCR - Capture/Compare value - 0 - 16 - - - GC5C1 - Group Channel 5 and Channel 1 - 29 - 1 - - - GC5C2 - Group Channel 5 and Channel 2 - 30 - 1 - - - GC5C3 - Group Channel 5 and Channel 3 - 31 - 1 - - - - - CCR6 - CRR6 - capture/compare register - 0x5C - 0x20 - read-write - 0x00000000 - - - CCR - Capture/Compare value - 0 - 16 - - - - - AF1 - alternate function option register 1 - 0x60 - 0x20 - read-write - 0x00000001 - - - BKINE - BRK BKIN input enable - 0 - 1 - - - BKDFBKE - BRK DFSDM_BREAK[0] enable - 8 - 1 - - - BKINP - BRK BKIN input polarity - 9 - 1 - - - - - AF2 - alternate function option register 2 - 0x64 - 0x20 - read-write - 0x00000001 - - - BK2INE - BRK2 BKIN input enable - 0 - 1 - - - BK2DFBKE - BRK2 DFSDM_BREAK[0] enable - 8 - 1 - - - BK2INP - BRK2 BKIN input polarity - 9 - 1 - - - - - - - TIM8 - TIM - 0x40010400 - - TIM8_BRK_TIM12 - TIM8 Break interrupt and TIM12 global - interrupt - 43 - - - TIM8_UP_TIM13 - TIM8 Update interrupt and TIM13 global - interrupt - 44 - - - TIM8_TRG_COM_TIM14 - TIM8 Trigger and Commutation interrupts and - TIM14 global interrupt - 45 - - - TIM8_CC - TIM8 Capture Compare interrupt - 46 - - - - TIM2 - General purpose timers - TIM - 0x40000000 - - 0x0 - 0x400 - registers - - - TIM2 - TIM2 global interrupt - 28 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - CKD - Clock division - 8 - 2 - - CKD - read-write - - Div1 - t_DTS = t_CK_INT - 0 - - - Div2 - t_DTS = 2 Γ— t_CK_INT - 1 - - - Div4 - t_DTS = 4 Γ— t_CK_INT - 2 - - - - - ARPE - Auto-reload preload enable - 7 - 1 - - ARPE - read-write - - Disabled - TIMx_APRR register is not buffered - 0 - - - Enabled - TIMx_APRR register is buffered - 1 - - - - - CMS - Center-aligned mode selection - 5 - 2 - - CMS - read-write - - EdgeAligned - The counter counts up or down depending on the direction bit - 0 - - - CenterAligned1 - The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. - 1 - - - CenterAligned2 - The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. - 2 - - - CenterAligned3 - The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. - 3 - - - - - DIR - Direction - 4 - 1 - - DIR - read-write - - Up - Counter used as upcounter - 0 - - - Down - Counter used as downcounter - 1 - - - - - OPM - One-pulse mode - 3 - 1 - - OPM - read-write - - Disabled - Counter is not stopped at update event - 0 - - - Enabled - Counter stops counting at the next update event (clearing the CEN bit) - 1 - - - - - URS - Update request source - 2 - 1 - - URS - read-write - - AnyEvent - Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - 0 - - - CounterOnly - Only counter overflow/underflow generates an update interrupt or DMA request - 1 - - - - - UDIS - Update disable - 1 - 1 - - UDIS - read-write - - Enabled - Update event enabled - 0 - - - Disabled - Update event disabled - 1 - - - - - CEN - Counter enable - 0 - 1 - - CEN - read-write - - Disabled - Counter disabled - 0 - - - Enabled - Counter enabled - 1 - - - - - UIFREMAP - UIF status bit remapping - 11 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - TI1S - TI1 selection - 7 - 1 - - TI1S - read-write - - Normal - The TIMx_CH1 pin is connected to TI1 input - 0 - - - XOR - The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - 1 - - - - - MMS - Master mode selection - 4 - 3 - - MMS - read-write - - Reset - The UG bit from the TIMx_EGR register is used as trigger output - 0 - - - Enable - The counter enable signal, CNT_EN, is used as trigger output - 1 - - - Update - The update event is selected as trigger output - 2 - - - ComparePulse - The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - 3 - - - CompareOC1 - OC1REF signal is used as trigger output - 4 - - - CompareOC2 - OC2REF signal is used as trigger output - 5 - - - CompareOC3 - OC3REF signal is used as trigger output - 6 - - - CompareOC4 - OC4REF signal is used as trigger output - 7 - - - - - CCDS - Capture/compare DMA selection - 3 - 1 - - CCDS - read-write - - OnCompare - CCx DMA request sent when CCx event occurs - 0 - - - OnUpdate - CCx DMA request sent when update event occurs - 1 - - - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x00000000 - - - SMS - Slave mode selection - 0 - 3 - - SMS - read-write - - Disabled - Slave mode disabled - if CEN = β€˜1 then the prescaler is clocked directly by the internal clock. - 0 - - - Encoder_Mode_1 - Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - 1 - - - Encoder_Mode_2 - Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - 2 - - - Encoder_Mode_3 - Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - 3 - - - Reset_Mode - Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - 4 - - - Gated_Mode - Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - 5 - - - Trigger_Mode - Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - 6 - - - Ext_Clock_Mode - External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - 7 - - - - - TS - Trigger selection - 4 - 3 - - TS - read-write - - ITR0 - Internal Trigger 0 (ITR0) - 0 - - - ITR1 - Internal Trigger 1 (ITR1) - 1 - - - ITR2 - Internal Trigger 2 (ITR2) - 2 - - - TI1F_ED - TI1 Edge Detector (TI1F_ED) - 4 - - - TI1FP1 - Filtered Timer Input 1 (TI1FP1) - 5 - - - TI2FP2 - Filtered Timer Input 2 (TI2FP2) - 6 - - - ETRF - External Trigger input (ETRF) - 7 - - - - - MSM - Master/Slave mode - 7 - 1 - - MSM - read-write - - NoSync - No action - 0 - - - Sync - The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - 1 - - - - - ETF - External trigger filter - 8 - 4 - - ETF - read-write - - NoFilter - No filter, sampling is done at fDTS - 0 - - - FCK_INT_N2 - fSAMPLING=fCK_INT, N=2 - 1 - - - FCK_INT_N4 - fSAMPLING=fCK_INT, N=4 - 2 - - - FCK_INT_N8 - fSAMPLING=fCK_INT, N=8 - 3 - - - FDTS_Div2_N6 - fSAMPLING=fDTS/2, N=6 - 4 - - - FDTS_Div2_N8 - fSAMPLING=fDTS/2, N=8 - 5 - - - FDTS_Div4_N6 - fSAMPLING=fDTS/4, N=6 - 6 - - - FDTS_Div4_N8 - fSAMPLING=fDTS/4, N=8 - 7 - - - FDTS_Div8_N6 - fSAMPLING=fDTS/8, N=6 - 8 - - - FDTS_Div8_N8 - fSAMPLING=fDTS/8, N=8 - 9 - - - FDTS_Div16_N5 - fSAMPLING=fDTS/16, N=5 - 10 - - - FDTS_Div16_N6 - fSAMPLING=fDTS/16, N=6 - 11 - - - FDTS_Div16_N8 - fSAMPLING=fDTS/16, N=8 - 12 - - - FDTS_Div32_N5 - fSAMPLING=fDTS/32, N=5 - 13 - - - FDTS_Div32_N6 - fSAMPLING=fDTS/32, N=6 - 14 - - - FDTS_Div32_N8 - fSAMPLING=fDTS/32, N=8 - 15 - - - - - ETPS - External trigger prescaler - 12 - 2 - - ETPS - read-write - - Div1 - Prescaler OFF - 0 - - - Div2 - ETRP frequency divided by 2 - 1 - - - Div4 - ETRP frequency divided by 4 - 2 - - - Div8 - ETRP frequency divided by 8 - 3 - - - - - ECE - External clock enable - 14 - 1 - - ECE - read-write - - Disabled - External clock mode 2 disabled - 0 - - - Enabled - External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. - 1 - - - - - ETP - External trigger polarity - 15 - 1 - - ETP - read-write - - NotInverted - ETR is noninverted, active at high level or rising edge - 0 - - - Inverted - ETR is inverted, active at low level or falling edge - 1 - - - - - SMS_3 - Slave model selection - bit[3] - 16 - 1 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x00000000 - - - TDE - Trigger DMA request enable - 14 - 1 - - TDE - read-write - - Disabled - Trigger DMA request disabled - 0 - - - Enabled - Trigger DMA request enabled - 1 - - - - - CC4DE - Capture/Compare 4 DMA request enable - 12 - 1 - - - - CC3DE - Capture/Compare 3 DMA request enable - 11 - 1 - - - - CC2DE - Capture/Compare 2 DMA request enable - 10 - 1 - - - - CC1DE - Capture/Compare 1 DMA request enable - 9 - 1 - - CC1DE - read-write - - Disabled - CCx DMA request disabled - 0 - - - Enabled - CCx DMA request enabled - 1 - - - - - UDE - Update DMA request enable - 8 - 1 - - UDE - read-write - - Disabled - Update DMA request disabled - 0 - - - Enabled - Update DMA request enabled - 1 - - - - - TIE - Trigger interrupt enable - 6 - 1 - - TIE - read-write - - Disabled - Trigger interrupt disabled - 0 - - - Enabled - Trigger interrupt enabled - 1 - - - - - CC4IE - Capture/Compare 4 interrupt enable - 4 - 1 - - - - CC3IE - Capture/Compare 3 interrupt enable - 3 - 1 - - - - CC2IE - Capture/Compare 2 interrupt enable - 2 - 1 - - - - CC1IE - Capture/Compare 1 interrupt enable - 1 - 1 - - CC1IE - read-write - - Disabled - CCx interrupt disabled - 0 - - - Enabled - CCx interrupt enabled - 1 - - - - - UIE - Update interrupt enable - 0 - 1 - - UIE - read-write - - Disabled - Update interrupt disabled - 0 - - - Enabled - Update interrupt enabled - 1 - - - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x00000000 - - - CC4OF - Capture/Compare 4 overcapture flag - 12 - 1 - zeroToClear - - read - - - write - - - - CC3OF - Capture/Compare 3 overcapture flag - 11 - 1 - zeroToClear - - read - - - write - - - - CC2OF - Capture/compare 2 overcapture flag - 10 - 1 - zeroToClear - - read - - - write - - - - CC1OF - Capture/Compare 1 overcapture flag - 9 - 1 - zeroToClear - - CC1OFR - read - - Overcapture - The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set - 1 - - - - CC1OFW - write - - Clear - Clear flag - 0 - - - - - TIF - Trigger interrupt flag - 6 - 1 - zeroToClear - - TIFR - read - - NoTrigger - No trigger event occurred - 0 - - - Trigger - Trigger interrupt pending - 1 - - - - TIFW - write - - Clear - Clear flag - 0 - - - - - CC4IF - Capture/Compare 4 interrupt flag - 4 - 1 - zeroToClear - - read - - - write - - - - CC3IF - Capture/Compare 3 interrupt flag - 3 - 1 - zeroToClear - - read - - - write - - - - CC2IF - Capture/Compare 2 interrupt flag - 2 - 1 - zeroToClear - - read - - - write - - - - CC1IF - Capture/compare 1 interrupt flag - 1 - 1 - zeroToClear - - CC1IFR - read - - Match - If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. - 1 - - - - CC1IFW - write - - Clear - Clear flag - 0 - - - - - UIF - Update interrupt flag - 0 - 1 - zeroToClear - - UIFR - read - - NoUpdateOccurred - No update occurred - 0 - - - UpdatePending - Update interrupt pending - 1 - - - - UIFW - write - - Clear - Clear flag - 0 - - - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x00000000 - - - TG - Trigger generation - 6 - 1 - - TGW - write - - Trigger - The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. - 1 - - - - - CC4G - Capture/compare 4 generation - 4 - 1 - - - - CC3G - Capture/compare 3 generation - 3 - 1 - - - - CC2G - Capture/compare 2 generation - 2 - 1 - - - - CC1G - Capture/compare 1 generation - 1 - 1 - - CC1GW - write - - Trigger - If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. - 1 - - - - - UG - Update generation - 0 - 1 - - UG - write - - Update - Re-initializes the timer counter and generates an update of the registers. - 1 - - - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - OC2CE - 15 - 1 - - - OC2M - OC2M - 12 - 3 - - - - OC2PE - OC2PE - 11 - 1 - - OC2PE - read-write - - Disabled - Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately - 0 - - - Enabled - Preload register on CCR2 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC2FE - OC2FE - 10 - 1 - - - CC2S - CC2S - 8 - 2 - - CC2S - read-write - - Output - CC2 channel is configured as output - 0 - - - - - OC1CE - OC1CE - 7 - 1 - - - OC1M - OC1M - 4 - 3 - - OC1M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved - 3 - - - ForceInactive - OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF - 4 - - - ForceActive - OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down - 6 - - - PwmMode2 - Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 - 7 - - - - - OC1PE - OC1PE - 3 - 1 - - OC1PE - read-write - - Disabled - Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately - 0 - - - Enabled - Preload register on CCR1 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC1FE - OC1FE - 2 - 1 - - - CC1S - CC1S - 0 - 2 - - CC1S - read-write - - Output - CC1 channel is configured as output - 0 - - - - - OC2M_3 - Output Compare 2 mode, bit 3 - 24 - 1 - - - - OC1M_3 - Output Compare 1 mode, bit 3 - 16 - 1 - - OC1M_3 - read-write - - Normal - Normal output compare mode (modes 0-7) - 0 - - - Extended - Extended output compare mode (modes 7-15) - 1 - - - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - 0 - 15 - - - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 selection - 8 - 2 - - CC2S - read-write - - TI2 - CC2 channel is configured as input, IC2 is mapped on TI2 - 1 - - - TI1 - CC2 channel is configured as input, IC2 is mapped on TI1 - 2 - - - TRC - CC2 channel is configured as input, IC2 is mapped on TRC - 3 - - - - - IC1F - Input capture 1 filter - 4 - 4 - - IC1F - read-write - - NoFilter - No filter, sampling is done at fDTS - 0 - - - FCK_INT_N2 - fSAMPLING=fCK_INT, N=2 - 1 - - - FCK_INT_N4 - fSAMPLING=fCK_INT, N=4 - 2 - - - FCK_INT_N8 - fSAMPLING=fCK_INT, N=8 - 3 - - - FDTS_Div2_N6 - fSAMPLING=fDTS/2, N=6 - 4 - - - FDTS_Div2_N8 - fSAMPLING=fDTS/2, N=8 - 5 - - - FDTS_Div4_N6 - fSAMPLING=fDTS/4, N=6 - 6 - - - FDTS_Div4_N8 - fSAMPLING=fDTS/4, N=8 - 7 - - - FDTS_Div8_N6 - fSAMPLING=fDTS/8, N=6 - 8 - - - FDTS_Div8_N8 - fSAMPLING=fDTS/8, N=8 - 9 - - - FDTS_Div16_N5 - fSAMPLING=fDTS/16, N=5 - 10 - - - FDTS_Div16_N6 - fSAMPLING=fDTS/16, N=6 - 11 - - - FDTS_Div16_N8 - fSAMPLING=fDTS/16, N=8 - 12 - - - FDTS_Div32_N5 - fSAMPLING=fDTS/32, N=5 - 13 - - - FDTS_Div32_N6 - fSAMPLING=fDTS/32, N=6 - 14 - - - FDTS_Div32_N8 - fSAMPLING=fDTS/32, N=8 - 15 - - - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 selection - 0 - 2 - - CC1S - read-write - - TI1 - CC1 channel is configured as input, IC1 is mapped on TI1 - 1 - - - TI2 - CC1 channel is configured as input, IC1 is mapped on TI2 - 2 - - - TRC - CC1 channel is configured as input, IC1 is mapped on TRC - 3 - - - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register 2 (output mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - O24CE - 15 - 1 - - - OC4M - OC4M - 12 - 3 - - - - OC4PE - OC4PE - 11 - 1 - - OC4PE - read-write - - Disabled - Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately - 0 - - - Enabled - Preload register on CCR4 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC4FE - OC4FE - 10 - 1 - - - CC4S - CC4S - 8 - 2 - - CC4S - read-write - - Output - CC4 channel is configured as output - 0 - - - - - OC3CE - OC3CE - 7 - 1 - - - OC3M - OC3M - 4 - 3 - - OC3M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved - 3 - - - ForceInactive - OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF - 4 - - - ForceActive - OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down - 6 - - - PwmMode2 - Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 - 7 - - - - - OC3PE - OC3PE - 3 - 1 - - OC3PE - read-write - - Disabled - Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately - 0 - - - Enabled - Preload register on CCR3 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC3FE - OC3FE - 2 - 1 - - - CC3S - CC3S - 0 - 2 - - CC3S - read-write - - Output - CC3 channel is configured as output - 0 - - - - - OC3M_3 - Output Compare 3 mode, bit 3 - 16 - 1 - - OC3M_3 - read-write - - Normal - Normal output compare mode (modes 0-7) - 0 - - - Extended - Extended output compare mode (modes 7-15) - 1 - - - - - OC4M_3 - Output Compare 4 mode, bit 3 - 24 - 1 - - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - 0 - 15 - - - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - 0 - 3 - - - - - CC4S - Capture/Compare 4 selection - 8 - 2 - - CC4S - read-write - - TI4 - CC4 channel is configured as input, IC4 is mapped on TI4 - 1 - - - TI3 - CC4 channel is configured as input, IC4 is mapped on TI3 - 2 - - - TRC - CC4 channel is configured as input, IC4 is mapped on TRC - 3 - - - - - IC3F - Input capture 3 filter - 4 - 4 - - - 0 - 15 - - - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - 0 - 3 - - - - - CC3S - Capture/compare 3 selection - 0 - 2 - - CC3S - read-write - - TI3 - CC3 channel is configured as input, IC3 is mapped on TI3 - 1 - - - TI4 - CC3 channel is configured as input, IC3 is mapped on TI4 - 2 - - - TRC - CC3 channel is configured as input, IC3 is mapped on TRC - 3 - - - - - - - CCER - CCER - capture/compare enable register - 0x20 - 0x20 - read-write - 0x00000000 - - - CC4NP - Capture/Compare 4 output Polarity - 15 - 1 - - - CC4P - Capture/Compare 3 output Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output enable - 12 - 1 - - - CC3NP - Capture/Compare 3 output Polarity - 11 - 1 - - - CC3P - Capture/Compare 3 output Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output enable - 8 - 1 - - - CC2NP - Capture/Compare 2 output Polarity - 7 - 1 - - - CC2P - Capture/Compare 2 output Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - Counter value - 0 - 32 - - - 0 - 4294967295 - - - - - UIFCPY - UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 - - 31 - 1 - read-only - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x00000000 - - - PSC - Prescaler value - 0 - 16 - - - 0 - 65535 - - - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 32 - - - 0 - 4294967295 - - - - - - - 4 - 0x4 - 1-4 - CCR%s - CCR1 - capture/compare register - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR - Capture/Compare value - 0 - 32 - - - 0 - 4294967295 - - - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x00000000 - - - DBL - DMA burst length - 8 - 5 - - - 0 - 18 - - - - - DBA - DMA base address - 0 - 5 - - - 0 - 31 - - - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x00000000 - - - DMAB - DMA register for burst accesses - 0 - 32 - - - - - OR - OR1 - TIM2 option register 1 - 0x50 - 0x20 - read-write - 0x00000000 - - - ITR1_RMP - Internal trigger 1 remap - 10 - 2 - - - - - - - TIM3 - General purpose timers - TIM - 0x40000400 - - 0x0 - 0x400 - registers - - - TIM3 - TIM3 global interrupt - 29 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - CKD - Clock division - 8 - 2 - - CKD - read-write - - Div1 - t_DTS = t_CK_INT - 0 - - - Div2 - t_DTS = 2 Γ— t_CK_INT - 1 - - - Div4 - t_DTS = 4 Γ— t_CK_INT - 2 - - - - - ARPE - Auto-reload preload enable - 7 - 1 - - ARPE - read-write - - Disabled - TIMx_APRR register is not buffered - 0 - - - Enabled - TIMx_APRR register is buffered - 1 - - - - - CMS - Center-aligned mode selection - 5 - 2 - - CMS - read-write - - EdgeAligned - The counter counts up or down depending on the direction bit - 0 - - - CenterAligned1 - The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. - 1 - - - CenterAligned2 - The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. - 2 - - - CenterAligned3 - The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. - 3 - - - - - DIR - Direction - 4 - 1 - - DIR - read-write - - Up - Counter used as upcounter - 0 - - - Down - Counter used as downcounter - 1 - - - - - OPM - One-pulse mode - 3 - 1 - - OPM - read-write - - Disabled - Counter is not stopped at update event - 0 - - - Enabled - Counter stops counting at the next update event (clearing the CEN bit) - 1 - - - - - URS - Update request source - 2 - 1 - - URS - read-write - - AnyEvent - Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - 0 - - - CounterOnly - Only counter overflow/underflow generates an update interrupt or DMA request - 1 - - - - - UDIS - Update disable - 1 - 1 - - UDIS - read-write - - Enabled - Update event enabled - 0 - - - Disabled - Update event disabled - 1 - - - - - CEN - Counter enable - 0 - 1 - - CEN - read-write - - Disabled - Counter disabled - 0 - - - Enabled - Counter enabled - 1 - - - - - UIFREMAP - UIF status bit remapping - 11 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - TI1S - TI1 selection - 7 - 1 - - TI1S - read-write - - Normal - The TIMx_CH1 pin is connected to TI1 input - 0 - - - XOR - The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - 1 - - - - - MMS - Master mode selection - 4 - 3 - - MMS - read-write - - Reset - The UG bit from the TIMx_EGR register is used as trigger output - 0 - - - Enable - The counter enable signal, CNT_EN, is used as trigger output - 1 - - - Update - The update event is selected as trigger output - 2 - - - ComparePulse - The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - 3 - - - CompareOC1 - OC1REF signal is used as trigger output - 4 - - - CompareOC2 - OC2REF signal is used as trigger output - 5 - - - CompareOC3 - OC3REF signal is used as trigger output - 6 - - - CompareOC4 - OC4REF signal is used as trigger output - 7 - - - - - CCDS - Capture/compare DMA selection - 3 - 1 - - CCDS - read-write - - OnCompare - CCx DMA request sent when CCx event occurs - 0 - - - OnUpdate - CCx DMA request sent when update event occurs - 1 - - - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x00000000 - - - SMS - Slave mode selection - 0 - 3 - - SMS - read-write - - Disabled - Slave mode disabled - if CEN = β€˜1 then the prescaler is clocked directly by the internal clock. - 0 - - - Encoder_Mode_1 - Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - 1 - - - Encoder_Mode_2 - Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - 2 - - - Encoder_Mode_3 - Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - 3 - - - Reset_Mode - Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - 4 - - - Gated_Mode - Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - 5 - - - Trigger_Mode - Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - 6 - - - Ext_Clock_Mode - External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - 7 - - - - - TS - Trigger selection - 4 - 3 - - TS - read-write - - ITR0 - Internal Trigger 0 (ITR0) - 0 - - - ITR1 - Internal Trigger 1 (ITR1) - 1 - - - ITR2 - Internal Trigger 2 (ITR2) - 2 - - - TI1F_ED - TI1 Edge Detector (TI1F_ED) - 4 - - - TI1FP1 - Filtered Timer Input 1 (TI1FP1) - 5 - - - TI2FP2 - Filtered Timer Input 2 (TI2FP2) - 6 - - - ETRF - External Trigger input (ETRF) - 7 - - - - - MSM - Master/Slave mode - 7 - 1 - - MSM - read-write - - NoSync - No action - 0 - - - Sync - The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - 1 - - - - - ETF - External trigger filter - 8 - 4 - - ETF - read-write - - NoFilter - No filter, sampling is done at fDTS - 0 - - - FCK_INT_N2 - fSAMPLING=fCK_INT, N=2 - 1 - - - FCK_INT_N4 - fSAMPLING=fCK_INT, N=4 - 2 - - - FCK_INT_N8 - fSAMPLING=fCK_INT, N=8 - 3 - - - FDTS_Div2_N6 - fSAMPLING=fDTS/2, N=6 - 4 - - - FDTS_Div2_N8 - fSAMPLING=fDTS/2, N=8 - 5 - - - FDTS_Div4_N6 - fSAMPLING=fDTS/4, N=6 - 6 - - - FDTS_Div4_N8 - fSAMPLING=fDTS/4, N=8 - 7 - - - FDTS_Div8_N6 - fSAMPLING=fDTS/8, N=6 - 8 - - - FDTS_Div8_N8 - fSAMPLING=fDTS/8, N=8 - 9 - - - FDTS_Div16_N5 - fSAMPLING=fDTS/16, N=5 - 10 - - - FDTS_Div16_N6 - fSAMPLING=fDTS/16, N=6 - 11 - - - FDTS_Div16_N8 - fSAMPLING=fDTS/16, N=8 - 12 - - - FDTS_Div32_N5 - fSAMPLING=fDTS/32, N=5 - 13 - - - FDTS_Div32_N6 - fSAMPLING=fDTS/32, N=6 - 14 - - - FDTS_Div32_N8 - fSAMPLING=fDTS/32, N=8 - 15 - - - - - ETPS - External trigger prescaler - 12 - 2 - - ETPS - read-write - - Div1 - Prescaler OFF - 0 - - - Div2 - ETRP frequency divided by 2 - 1 - - - Div4 - ETRP frequency divided by 4 - 2 - - - Div8 - ETRP frequency divided by 8 - 3 - - - - - ECE - External clock enable - 14 - 1 - - ECE - read-write - - Disabled - External clock mode 2 disabled - 0 - - - Enabled - External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. - 1 - - - - - ETP - External trigger polarity - 15 - 1 - - ETP - read-write - - NotInverted - ETR is noninverted, active at high level or rising edge - 0 - - - Inverted - ETR is inverted, active at low level or falling edge - 1 - - - - - SMS_3 - Slave model selection - bit[3] - 16 - 1 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x00000000 - - - TDE - Trigger DMA request enable - 14 - 1 - - TDE - read-write - - Disabled - Trigger DMA request disabled - 0 - - - Enabled - Trigger DMA request enabled - 1 - - - - - CC4DE - Capture/Compare 4 DMA request enable - 12 - 1 - - - - CC3DE - Capture/Compare 3 DMA request enable - 11 - 1 - - - - CC2DE - Capture/Compare 2 DMA request enable - 10 - 1 - - - - CC1DE - Capture/Compare 1 DMA request enable - 9 - 1 - - CC1DE - read-write - - Disabled - CCx DMA request disabled - 0 - - - Enabled - CCx DMA request enabled - 1 - - - - - UDE - Update DMA request enable - 8 - 1 - - UDE - read-write - - Disabled - Update DMA request disabled - 0 - - - Enabled - Update DMA request enabled - 1 - - - - - TIE - Trigger interrupt enable - 6 - 1 - - TIE - read-write - - Disabled - Trigger interrupt disabled - 0 - - - Enabled - Trigger interrupt enabled - 1 - - - - - CC4IE - Capture/Compare 4 interrupt enable - 4 - 1 - - - - CC3IE - Capture/Compare 3 interrupt enable - 3 - 1 - - - - CC2IE - Capture/Compare 2 interrupt enable - 2 - 1 - - - - CC1IE - Capture/Compare 1 interrupt enable - 1 - 1 - - CC1IE - read-write - - Disabled - CCx interrupt disabled - 0 - - - Enabled - CCx interrupt enabled - 1 - - - - - UIE - Update interrupt enable - 0 - 1 - - UIE - read-write - - Disabled - Update interrupt disabled - 0 - - - Enabled - Update interrupt enabled - 1 - - - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x00000000 - - - CC4OF - Capture/Compare 4 overcapture flag - 12 - 1 - zeroToClear - - read - - - write - - - - CC3OF - Capture/Compare 3 overcapture flag - 11 - 1 - zeroToClear - - read - - - write - - - - CC2OF - Capture/compare 2 overcapture flag - 10 - 1 - zeroToClear - - read - - - write - - - - CC1OF - Capture/Compare 1 overcapture flag - 9 - 1 - zeroToClear - - CC1OFR - read - - Overcapture - The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set - 1 - - - - CC1OFW - write - - Clear - Clear flag - 0 - - - - - TIF - Trigger interrupt flag - 6 - 1 - zeroToClear - - TIFR - read - - NoTrigger - No trigger event occurred - 0 - - - Trigger - Trigger interrupt pending - 1 - - - - TIFW - write - - Clear - Clear flag - 0 - - - - - CC4IF - Capture/Compare 4 interrupt flag - 4 - 1 - zeroToClear - - read - - - write - - - - CC3IF - Capture/Compare 3 interrupt flag - 3 - 1 - zeroToClear - - read - - - write - - - - CC2IF - Capture/Compare 2 interrupt flag - 2 - 1 - zeroToClear - - read - - - write - - - - CC1IF - Capture/compare 1 interrupt flag - 1 - 1 - zeroToClear - - CC1IFR - read - - Match - If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. - 1 - - - - CC1IFW - write - - Clear - Clear flag - 0 - - - - - UIF - Update interrupt flag - 0 - 1 - zeroToClear - - UIFR - read - - NoUpdateOccurred - No update occurred - 0 - - - UpdatePending - Update interrupt pending - 1 - - - - UIFW - write - - Clear - Clear flag - 0 - - - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x00000000 - - - TG - Trigger generation - 6 - 1 - - TGW - write - - Trigger - The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. - 1 - - - - - CC4G - Capture/compare 4 generation - 4 - 1 - - - - CC3G - Capture/compare 3 generation - 3 - 1 - - - - CC2G - Capture/compare 2 generation - 2 - 1 - - - - CC1G - Capture/compare 1 generation - 1 - 1 - - CC1GW - write - - Trigger - If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. - 1 - - - - - UG - Update generation - 0 - 1 - - UG - write - - Update - Re-initializes the timer counter and generates an update of the registers. - 1 - - - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - OC2CE - 15 - 1 - - - OC2M - OC2M - 12 - 3 - - - - OC2PE - OC2PE - 11 - 1 - - OC2PE - read-write - - Disabled - Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately - 0 - - - Enabled - Preload register on CCR2 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC2FE - OC2FE - 10 - 1 - - - CC2S - CC2S - 8 - 2 - - CC2S - read-write - - Output - CC2 channel is configured as output - 0 - - - - - OC1CE - OC1CE - 7 - 1 - - - OC1M - OC1M - 4 - 3 - - OC1M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved - 3 - - - ForceInactive - OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF - 4 - - - ForceActive - OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down - 6 - - - PwmMode2 - Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 - 7 - - - - - OC1PE - OC1PE - 3 - 1 - - OC1PE - read-write - - Disabled - Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately - 0 - - - Enabled - Preload register on CCR1 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC1FE - OC1FE - 2 - 1 - - - CC1S - CC1S - 0 - 2 - - CC1S - read-write - - Output - CC1 channel is configured as output - 0 - - - - - OC2M_3 - Output Compare 2 mode, bit 3 - 24 - 1 - - - - OC1M_3 - Output Compare 1 mode, bit 3 - 16 - 1 - - OC1M_3 - read-write - - Normal - Normal output compare mode (modes 0-7) - 0 - - - Extended - Extended output compare mode (modes 7-15) - 1 - - - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - 0 - 15 - - - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 selection - 8 - 2 - - CC2S - read-write - - TI2 - CC2 channel is configured as input, IC2 is mapped on TI2 - 1 - - - TI1 - CC2 channel is configured as input, IC2 is mapped on TI1 - 2 - - - TRC - CC2 channel is configured as input, IC2 is mapped on TRC - 3 - - - - - IC1F - Input capture 1 filter - 4 - 4 - - IC1F - read-write - - NoFilter - No filter, sampling is done at fDTS - 0 - - - FCK_INT_N2 - fSAMPLING=fCK_INT, N=2 - 1 - - - FCK_INT_N4 - fSAMPLING=fCK_INT, N=4 - 2 - - - FCK_INT_N8 - fSAMPLING=fCK_INT, N=8 - 3 - - - FDTS_Div2_N6 - fSAMPLING=fDTS/2, N=6 - 4 - - - FDTS_Div2_N8 - fSAMPLING=fDTS/2, N=8 - 5 - - - FDTS_Div4_N6 - fSAMPLING=fDTS/4, N=6 - 6 - - - FDTS_Div4_N8 - fSAMPLING=fDTS/4, N=8 - 7 - - - FDTS_Div8_N6 - fSAMPLING=fDTS/8, N=6 - 8 - - - FDTS_Div8_N8 - fSAMPLING=fDTS/8, N=8 - 9 - - - FDTS_Div16_N5 - fSAMPLING=fDTS/16, N=5 - 10 - - - FDTS_Div16_N6 - fSAMPLING=fDTS/16, N=6 - 11 - - - FDTS_Div16_N8 - fSAMPLING=fDTS/16, N=8 - 12 - - - FDTS_Div32_N5 - fSAMPLING=fDTS/32, N=5 - 13 - - - FDTS_Div32_N6 - fSAMPLING=fDTS/32, N=6 - 14 - - - FDTS_Div32_N8 - fSAMPLING=fDTS/32, N=8 - 15 - - - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 selection - 0 - 2 - - CC1S - read-write - - TI1 - CC1 channel is configured as input, IC1 is mapped on TI1 - 1 - - - TI2 - CC1 channel is configured as input, IC1 is mapped on TI2 - 2 - - - TRC - CC1 channel is configured as input, IC1 is mapped on TRC - 3 - - - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register 2 (output mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - O24CE - 15 - 1 - - - OC4M - OC4M - 12 - 3 - - - - OC4PE - OC4PE - 11 - 1 - - OC4PE - read-write - - Disabled - Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately - 0 - - - Enabled - Preload register on CCR4 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC4FE - OC4FE - 10 - 1 - - - CC4S - CC4S - 8 - 2 - - CC4S - read-write - - Output - CC4 channel is configured as output - 0 - - - - - OC3CE - OC3CE - 7 - 1 - - - OC3M - OC3M - 4 - 3 - - OC3M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved - 3 - - - ForceInactive - OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF - 4 - - - ForceActive - OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down - 6 - - - PwmMode2 - Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 - 7 - - - - - OC3PE - OC3PE - 3 - 1 - - OC3PE - read-write - - Disabled - Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately - 0 - - - Enabled - Preload register on CCR3 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC3FE - OC3FE - 2 - 1 - - - CC3S - CC3S - 0 - 2 - - CC3S - read-write - - Output - CC3 channel is configured as output - 0 - - - - - OC3M_3 - Output Compare 3 mode, bit 3 - 16 - 1 - - OC3M_3 - read-write - - Normal - Normal output compare mode (modes 0-7) - 0 - - - Extended - Extended output compare mode (modes 7-15) - 1 - - - - - OC4M_3 - Output Compare 4 mode, bit 3 - 24 - 1 - - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - 0 - 15 - - - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - 0 - 3 - - - - - CC4S - Capture/Compare 4 selection - 8 - 2 - - CC4S - read-write - - TI4 - CC4 channel is configured as input, IC4 is mapped on TI4 - 1 - - - TI3 - CC4 channel is configured as input, IC4 is mapped on TI3 - 2 - - - TRC - CC4 channel is configured as input, IC4 is mapped on TRC - 3 - - - - - IC3F - Input capture 3 filter - 4 - 4 - - - 0 - 15 - - - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - 0 - 3 - - - - - CC3S - Capture/compare 3 selection - 0 - 2 - - CC3S - read-write - - TI3 - CC3 channel is configured as input, IC3 is mapped on TI3 - 1 - - - TI4 - CC3 channel is configured as input, IC3 is mapped on TI4 - 2 - - - TRC - CC3 channel is configured as input, IC3 is mapped on TRC - 3 - - - - - - - CCER - CCER - capture/compare enable register - 0x20 - 0x20 - read-write - 0x00000000 - - - CC4NP - Capture/Compare 4 output Polarity - 15 - 1 - - - CC4P - Capture/Compare 3 output Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output enable - 12 - 1 - - - CC3NP - Capture/Compare 3 output Polarity - 11 - 1 - - - CC3P - Capture/Compare 3 output Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output enable - 8 - 1 - - - CC2NP - Capture/Compare 2 output Polarity - 7 - 1 - - - CC2P - Capture/Compare 2 output Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - Counter value - 0 - 16 - - - 0 - 65535 - - - - - UIFCPY - UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 - - 31 - 1 - read-only - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x00000000 - - - PSC - Prescaler value - 0 - 16 - - - 0 - 65535 - - - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - 0 - 65535 - - - - - - - 4 - 0x4 - 1-4 - CCR%s - CCR1 - capture/compare register - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR - Capture/Compare value - 0 - 16 - - - 0 - 65535 - - - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x00000000 - - - DBL - DMA burst length - 8 - 5 - - - 0 - 18 - - - - - DBA - DMA base address - 0 - 5 - - - 0 - 31 - - - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x00000000 - - - DMAB - DMA register for burst accesses - 0 - 32 - - - - - - - TIM4 - General purpose timers - TIM - 0x40000800 - - TIM4 - TIM4 global interrupt - 30 - - - - TIM5 - General purpose timers - TIM - 0x40000C00 - - 0x0 - 0x400 - registers - - - TIM5 - TIM5 global interrupt - 50 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - CKD - Clock division - 8 - 2 - - CKD - read-write - - Div1 - t_DTS = t_CK_INT - 0 - - - Div2 - t_DTS = 2 Γ— t_CK_INT - 1 - - - Div4 - t_DTS = 4 Γ— t_CK_INT - 2 - - - - - ARPE - Auto-reload preload enable - 7 - 1 - - ARPE - read-write - - Disabled - TIMx_APRR register is not buffered - 0 - - - Enabled - TIMx_APRR register is buffered - 1 - - - - - CMS - Center-aligned mode selection - 5 - 2 - - CMS - read-write - - EdgeAligned - The counter counts up or down depending on the direction bit - 0 - - - CenterAligned1 - The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. - 1 - - - CenterAligned2 - The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. - 2 - - - CenterAligned3 - The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. - 3 - - - - - DIR - Direction - 4 - 1 - - DIR - read-write - - Up - Counter used as upcounter - 0 - - - Down - Counter used as downcounter - 1 - - - - - OPM - One-pulse mode - 3 - 1 - - OPM - read-write - - Disabled - Counter is not stopped at update event - 0 - - - Enabled - Counter stops counting at the next update event (clearing the CEN bit) - 1 - - - - - URS - Update request source - 2 - 1 - - URS - read-write - - AnyEvent - Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - 0 - - - CounterOnly - Only counter overflow/underflow generates an update interrupt or DMA request - 1 - - - - - UDIS - Update disable - 1 - 1 - - UDIS - read-write - - Enabled - Update event enabled - 0 - - - Disabled - Update event disabled - 1 - - - - - CEN - Counter enable - 0 - 1 - - CEN - read-write - - Disabled - Counter disabled - 0 - - - Enabled - Counter enabled - 1 - - - - - UIFREMAP - UIF status bit remapping - 11 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - TI1S - TI1 selection - 7 - 1 - - TI1S - read-write - - Normal - The TIMx_CH1 pin is connected to TI1 input - 0 - - - XOR - The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - 1 - - - - - MMS - Master mode selection - 4 - 3 - - MMS - read-write - - Reset - The UG bit from the TIMx_EGR register is used as trigger output - 0 - - - Enable - The counter enable signal, CNT_EN, is used as trigger output - 1 - - - Update - The update event is selected as trigger output - 2 - - - ComparePulse - The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - 3 - - - CompareOC1 - OC1REF signal is used as trigger output - 4 - - - CompareOC2 - OC2REF signal is used as trigger output - 5 - - - CompareOC3 - OC3REF signal is used as trigger output - 6 - - - CompareOC4 - OC4REF signal is used as trigger output - 7 - - - - - CCDS - Capture/compare DMA selection - 3 - 1 - - CCDS - read-write - - OnCompare - CCx DMA request sent when CCx event occurs - 0 - - - OnUpdate - CCx DMA request sent when update event occurs - 1 - - - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x00000000 - - - SMS - Slave mode selection - 0 - 3 - - SMS - read-write - - Disabled - Slave mode disabled - if CEN = β€˜1 then the prescaler is clocked directly by the internal clock. - 0 - - - Encoder_Mode_1 - Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - 1 - - - Encoder_Mode_2 - Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - 2 - - - Encoder_Mode_3 - Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - 3 - - - Reset_Mode - Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - 4 - - - Gated_Mode - Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - 5 - - - Trigger_Mode - Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - 6 - - - Ext_Clock_Mode - External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - 7 - - - - - TS - Trigger selection - 4 - 3 - - TS - read-write - - ITR0 - Internal Trigger 0 (ITR0) - 0 - - - ITR1 - Internal Trigger 1 (ITR1) - 1 - - - ITR2 - Internal Trigger 2 (ITR2) - 2 - - - TI1F_ED - TI1 Edge Detector (TI1F_ED) - 4 - - - TI1FP1 - Filtered Timer Input 1 (TI1FP1) - 5 - - - TI2FP2 - Filtered Timer Input 2 (TI2FP2) - 6 - - - ETRF - External Trigger input (ETRF) - 7 - - - - - MSM - Master/Slave mode - 7 - 1 - - MSM - read-write - - NoSync - No action - 0 - - - Sync - The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - 1 - - - - - ETF - External trigger filter - 8 - 4 - - ETF - read-write - - NoFilter - No filter, sampling is done at fDTS - 0 - - - FCK_INT_N2 - fSAMPLING=fCK_INT, N=2 - 1 - - - FCK_INT_N4 - fSAMPLING=fCK_INT, N=4 - 2 - - - FCK_INT_N8 - fSAMPLING=fCK_INT, N=8 - 3 - - - FDTS_Div2_N6 - fSAMPLING=fDTS/2, N=6 - 4 - - - FDTS_Div2_N8 - fSAMPLING=fDTS/2, N=8 - 5 - - - FDTS_Div4_N6 - fSAMPLING=fDTS/4, N=6 - 6 - - - FDTS_Div4_N8 - fSAMPLING=fDTS/4, N=8 - 7 - - - FDTS_Div8_N6 - fSAMPLING=fDTS/8, N=6 - 8 - - - FDTS_Div8_N8 - fSAMPLING=fDTS/8, N=8 - 9 - - - FDTS_Div16_N5 - fSAMPLING=fDTS/16, N=5 - 10 - - - FDTS_Div16_N6 - fSAMPLING=fDTS/16, N=6 - 11 - - - FDTS_Div16_N8 - fSAMPLING=fDTS/16, N=8 - 12 - - - FDTS_Div32_N5 - fSAMPLING=fDTS/32, N=5 - 13 - - - FDTS_Div32_N6 - fSAMPLING=fDTS/32, N=6 - 14 - - - FDTS_Div32_N8 - fSAMPLING=fDTS/32, N=8 - 15 - - - - - ETPS - External trigger prescaler - 12 - 2 - - ETPS - read-write - - Div1 - Prescaler OFF - 0 - - - Div2 - ETRP frequency divided by 2 - 1 - - - Div4 - ETRP frequency divided by 4 - 2 - - - Div8 - ETRP frequency divided by 8 - 3 - - - - - ECE - External clock enable - 14 - 1 - - ECE - read-write - - Disabled - External clock mode 2 disabled - 0 - - - Enabled - External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. - 1 - - - - - ETP - External trigger polarity - 15 - 1 - - ETP - read-write - - NotInverted - ETR is noninverted, active at high level or rising edge - 0 - - - Inverted - ETR is inverted, active at low level or falling edge - 1 - - - - - SMS_3 - Slave model selection - bit[3] - 16 - 1 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x00000000 - - - TDE - Trigger DMA request enable - 14 - 1 - - TDE - read-write - - Disabled - Trigger DMA request disabled - 0 - - - Enabled - Trigger DMA request enabled - 1 - - - - - CC4DE - Capture/Compare 4 DMA request enable - 12 - 1 - - - - CC3DE - Capture/Compare 3 DMA request enable - 11 - 1 - - - - CC2DE - Capture/Compare 2 DMA request enable - 10 - 1 - - - - CC1DE - Capture/Compare 1 DMA request enable - 9 - 1 - - CC1DE - read-write - - Disabled - CCx DMA request disabled - 0 - - - Enabled - CCx DMA request enabled - 1 - - - - - UDE - Update DMA request enable - 8 - 1 - - UDE - read-write - - Disabled - Update DMA request disabled - 0 - - - Enabled - Update DMA request enabled - 1 - - - - - TIE - Trigger interrupt enable - 6 - 1 - - TIE - read-write - - Disabled - Trigger interrupt disabled - 0 - - - Enabled - Trigger interrupt enabled - 1 - - - - - CC4IE - Capture/Compare 4 interrupt enable - 4 - 1 - - - - CC3IE - Capture/Compare 3 interrupt enable - 3 - 1 - - - - CC2IE - Capture/Compare 2 interrupt enable - 2 - 1 - - - - CC1IE - Capture/Compare 1 interrupt enable - 1 - 1 - - CC1IE - read-write - - Disabled - CCx interrupt disabled - 0 - - - Enabled - CCx interrupt enabled - 1 - - - - - UIE - Update interrupt enable - 0 - 1 - - UIE - read-write - - Disabled - Update interrupt disabled - 0 - - - Enabled - Update interrupt enabled - 1 - - - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x00000000 - - - CC4OF - Capture/Compare 4 overcapture flag - 12 - 1 - zeroToClear - - read - - - write - - - - CC3OF - Capture/Compare 3 overcapture flag - 11 - 1 - zeroToClear - - read - - - write - - - - CC2OF - Capture/compare 2 overcapture flag - 10 - 1 - zeroToClear - - read - - - write - - - - CC1OF - Capture/Compare 1 overcapture flag - 9 - 1 - zeroToClear - - CC1OFR - read - - Overcapture - The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set - 1 - - - - CC1OFW - write - - Clear - Clear flag - 0 - - - - - TIF - Trigger interrupt flag - 6 - 1 - zeroToClear - - TIFR - read - - NoTrigger - No trigger event occurred - 0 - - - Trigger - Trigger interrupt pending - 1 - - - - TIFW - write - - Clear - Clear flag - 0 - - - - - CC4IF - Capture/Compare 4 interrupt flag - 4 - 1 - zeroToClear - - read - - - write - - - - CC3IF - Capture/Compare 3 interrupt flag - 3 - 1 - zeroToClear - - read - - - write - - - - CC2IF - Capture/Compare 2 interrupt flag - 2 - 1 - zeroToClear - - read - - - write - - - - CC1IF - Capture/compare 1 interrupt flag - 1 - 1 - zeroToClear - - CC1IFR - read - - Match - If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. - 1 - - - - CC1IFW - write - - Clear - Clear flag - 0 - - - - - UIF - Update interrupt flag - 0 - 1 - zeroToClear - - UIFR - read - - NoUpdateOccurred - No update occurred - 0 - - - UpdatePending - Update interrupt pending - 1 - - - - UIFW - write - - Clear - Clear flag - 0 - - - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x00000000 - - - TG - Trigger generation - 6 - 1 - - TGW - write - - Trigger - The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. - 1 - - - - - CC4G - Capture/compare 4 generation - 4 - 1 - - - - CC3G - Capture/compare 3 generation - 3 - 1 - - - - CC2G - Capture/compare 2 generation - 2 - 1 - - - - CC1G - Capture/compare 1 generation - 1 - 1 - - CC1GW - write - - Trigger - If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. - 1 - - - - - UG - Update generation - 0 - 1 - - UG - write - - Update - Re-initializes the timer counter and generates an update of the registers. - 1 - - - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - OC2CE - 15 - 1 - - - OC2M - OC2M - 12 - 3 - - - - OC2PE - OC2PE - 11 - 1 - - OC2PE - read-write - - Disabled - Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately - 0 - - - Enabled - Preload register on CCR2 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC2FE - OC2FE - 10 - 1 - - - CC2S - CC2S - 8 - 2 - - CC2S - read-write - - Output - CC2 channel is configured as output - 0 - - - - - OC1CE - OC1CE - 7 - 1 - - - OC1M - OC1M - 4 - 3 - - OC1M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved - 3 - - - ForceInactive - OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF - 4 - - - ForceActive - OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down - 6 - - - PwmMode2 - Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 - 7 - - - - - OC1PE - OC1PE - 3 - 1 - - OC1PE - read-write - - Disabled - Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately - 0 - - - Enabled - Preload register on CCR1 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC1FE - OC1FE - 2 - 1 - - - CC1S - CC1S - 0 - 2 - - CC1S - read-write - - Output - CC1 channel is configured as output - 0 - - - - - OC2M_3 - Output Compare 2 mode, bit 3 - 24 - 1 - - - - OC1M_3 - Output Compare 1 mode, bit 3 - 16 - 1 - - OC1M_3 - read-write - - Normal - Normal output compare mode (modes 0-7) - 0 - - - Extended - Extended output compare mode (modes 7-15) - 1 - - - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - 0 - 15 - - - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 selection - 8 - 2 - - CC2S - read-write - - TI2 - CC2 channel is configured as input, IC2 is mapped on TI2 - 1 - - - TI1 - CC2 channel is configured as input, IC2 is mapped on TI1 - 2 - - - TRC - CC2 channel is configured as input, IC2 is mapped on TRC - 3 - - - - - IC1F - Input capture 1 filter - 4 - 4 - - IC1F - read-write - - NoFilter - No filter, sampling is done at fDTS - 0 - - - FCK_INT_N2 - fSAMPLING=fCK_INT, N=2 - 1 - - - FCK_INT_N4 - fSAMPLING=fCK_INT, N=4 - 2 - - - FCK_INT_N8 - fSAMPLING=fCK_INT, N=8 - 3 - - - FDTS_Div2_N6 - fSAMPLING=fDTS/2, N=6 - 4 - - - FDTS_Div2_N8 - fSAMPLING=fDTS/2, N=8 - 5 - - - FDTS_Div4_N6 - fSAMPLING=fDTS/4, N=6 - 6 - - - FDTS_Div4_N8 - fSAMPLING=fDTS/4, N=8 - 7 - - - FDTS_Div8_N6 - fSAMPLING=fDTS/8, N=6 - 8 - - - FDTS_Div8_N8 - fSAMPLING=fDTS/8, N=8 - 9 - - - FDTS_Div16_N5 - fSAMPLING=fDTS/16, N=5 - 10 - - - FDTS_Div16_N6 - fSAMPLING=fDTS/16, N=6 - 11 - - - FDTS_Div16_N8 - fSAMPLING=fDTS/16, N=8 - 12 - - - FDTS_Div32_N5 - fSAMPLING=fDTS/32, N=5 - 13 - - - FDTS_Div32_N6 - fSAMPLING=fDTS/32, N=6 - 14 - - - FDTS_Div32_N8 - fSAMPLING=fDTS/32, N=8 - 15 - - - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 selection - 0 - 2 - - CC1S - read-write - - TI1 - CC1 channel is configured as input, IC1 is mapped on TI1 - 1 - - - TI2 - CC1 channel is configured as input, IC1 is mapped on TI2 - 2 - - - TRC - CC1 channel is configured as input, IC1 is mapped on TRC - 3 - - - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register 2 (output mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - O24CE - 15 - 1 - - - OC4M - OC4M - 12 - 3 - - - - OC4PE - OC4PE - 11 - 1 - - OC4PE - read-write - - Disabled - Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately - 0 - - - Enabled - Preload register on CCR4 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC4FE - OC4FE - 10 - 1 - - - CC4S - CC4S - 8 - 2 - - CC4S - read-write - - Output - CC4 channel is configured as output - 0 - - - - - OC3CE - OC3CE - 7 - 1 - - - OC3M - OC3M - 4 - 3 - - OC3M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved - 3 - - - ForceInactive - OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF - 4 - - - ForceActive - OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down - 6 - - - PwmMode2 - Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 - 7 - - - - - OC3PE - OC3PE - 3 - 1 - - OC3PE - read-write - - Disabled - Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately - 0 - - - Enabled - Preload register on CCR3 enabled. Preload value is loaded into active register on each update event - 1 - - - - - OC3FE - OC3FE - 2 - 1 - - - CC3S - CC3S - 0 - 2 - - CC3S - read-write - - Output - CC3 channel is configured as output - 0 - - - - - OC3M_3 - Output Compare 3 mode, bit 3 - 16 - 1 - - OC3M_3 - read-write - - Normal - Normal output compare mode (modes 0-7) - 0 - - - Extended - Extended output compare mode (modes 7-15) - 1 - - - - - OC4M_3 - Output Compare 4 mode, bit 3 - 24 - 1 - - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - 0 - 15 - - - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - 0 - 3 - - - - - CC4S - Capture/Compare 4 selection - 8 - 2 - - CC4S - read-write - - TI4 - CC4 channel is configured as input, IC4 is mapped on TI4 - 1 - - - TI3 - CC4 channel is configured as input, IC4 is mapped on TI3 - 2 - - - TRC - CC4 channel is configured as input, IC4 is mapped on TRC - 3 - - - - - IC3F - Input capture 3 filter - 4 - 4 - - - 0 - 15 - - - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - 0 - 3 - - - - - CC3S - Capture/compare 3 selection - 0 - 2 - - CC3S - read-write - - TI3 - CC3 channel is configured as input, IC3 is mapped on TI3 - 1 - - - TI4 - CC3 channel is configured as input, IC3 is mapped on TI4 - 2 - - - TRC - CC3 channel is configured as input, IC3 is mapped on TRC - 3 - - - - - - - CCER - CCER - capture/compare enable register - 0x20 - 0x20 - read-write - 0x00000000 - - - CC4NP - Capture/Compare 4 output Polarity - 15 - 1 - - - CC4P - Capture/Compare 3 output Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output enable - 12 - 1 - - - CC3NP - Capture/Compare 3 output Polarity - 11 - 1 - - - CC3P - Capture/Compare 3 output Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output enable - 8 - 1 - - - CC2NP - Capture/Compare 2 output Polarity - 7 - 1 - - - CC2P - Capture/Compare 2 output Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - Counter value - 0 - 32 - - - 0 - 4294967295 - - - - - UIFCPY - UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 - - 31 - 1 - read-only - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x00000000 - - - PSC - Prescaler value - 0 - 16 - - - 0 - 65535 - - - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 32 - - - 0 - 4294967295 - - - - - - - 4 - 0x4 - 1-4 - CCR%s - CCR1 - capture/compare register - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR - Capture/Compare value - 0 - 32 - - - 0 - 4294967295 - - - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x00000000 - - - DBL - DMA burst length - 8 - 5 - - - 0 - 18 - - - - - DBA - DMA base address - 0 - 5 - - - 0 - 31 - - - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x00000000 - - - DMAB - DMA register for burst accesses - 0 - 32 - - - - - OR - OR1 - TIM2 option register 1 - 0x50 - 0x20 - read-write - 0x00000000 - - - TI4_RMP - Input Capture 4 remap - 6 - 2 - - - - - - - TIM9 - General purpose timers - TIM - 0x40014000 - - 0x0 - 0x400 - registers - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - CKD - Clock division - 8 - 2 - - CKD - read-write - - Div1 - t_DTS = t_CK_INT - 0 - - - Div2 - t_DTS = 2 Γ— t_CK_INT - 1 - - - Div4 - t_DTS = 4 Γ— t_CK_INT - 2 - - - - - ARPE - Auto-reload preload enable - 7 - 1 - - ARPE - read-write - - Disabled - TIMx_APRR register is not buffered - 0 - - - Enabled - TIMx_APRR register is buffered - 1 - - - - - OPM - One-pulse mode - 3 - 1 - - OPM - read-write - - Disabled - Counter is not stopped at update event - 0 - - - Enabled - Counter stops counting at the next update event (clearing the CEN bit) - 1 - - - - - URS - Update request source - 2 - 1 - - URS - read-write - - AnyEvent - Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - 0 - - - CounterOnly - Only counter overflow/underflow generates an update interrupt or DMA request - 1 - - - - - UDIS - Update disable - 1 - 1 - - UDIS - read-write - - Enabled - Update event enabled - 0 - - - Disabled - Update event disabled - 1 - - - - - CEN - Counter enable - 0 - 1 - - CEN - read-write - - Disabled - Counter disabled - 0 - - - Enabled - Counter enabled - 1 - - - - - UIFREMAP - UIF status bit remapping - 11 - 1 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x00000000 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - SMS - Slave mode selection - 0 - 3 - - - SMS_3 - Slave mode selection - bit 3 - 16 - 1 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x00000000 - - - TIE - Trigger interrupt enable - 6 - 1 - - - CC2IE - Capture/Compare 2 interrupt enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - UIE - read-write - - Disabled - Update interrupt disabled - 0 - - - Enabled - Update interrupt enabled - 1 - - - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x00000000 - - - CC2OF - Capture/compare 2 overcapture flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture flag - 9 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - CC2IF - Capture/Compare 2 interrupt flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - zeroToClear - - UIFR - read - - NoUpdateOccurred - No update occurred - 0 - - - UpdatePending - Update interrupt pending - 1 - - - - UIFW - write - - Clear - Clear flag - 0 - - - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x00000000 - - - TG - Trigger generation - 6 - 1 - - - CC2G - Capture/compare 2 generation - 2 - 1 - - - CC1G - Capture/compare 1 generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - UG - write - - Update - Re-initializes the timer counter and generates an update of the registers. - 1 - - - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2M - Output Compare 2 mode - 12 - 3 - - - - OC2PE - Output Compare 2 preload enable - 11 - 1 - - - OC2FE - Output Compare 2 fast enable - 10 - 1 - - - CC2S - Capture/Compare 2 selection - 8 - 2 - - - OC1M - Output Compare 1 mode - 4 - 3 - - OC1M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved - 3 - - - ForceInactive - OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF - 4 - - - ForceActive - OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved - 6 - - - PwmMode2 - Inversely to PwmMode1 / Reserved - 7 - - - - - OC1PE - Output Compare 1 preload enable - 3 - 1 - - - OC1FE - Output Compare 1 fast enable - 2 - 1 - - - CC1S - Capture/Compare 1 selection - 0 - 2 - - - OC2M_3 - Output Compare 2 mode, bit 3 - 24 - 1 - - - - OC1M_3 - Output Compare 1 mode, bit 3 - 16 - 1 - - OC1M_3 - read-write - - Normal - Normal output compare mode (modes 0-7) - 0 - - - Extended - Extended output compare mode (modes 7-15) - 1 - - - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 3 - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 3 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable register - 0x20 - 0x20 - read-write - 0x00000000 - - - CC2NP - Capture/Compare 2 output Polarity - 7 - 1 - - - CC2P - Capture/Compare 2 output Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - 0 - 65535 - - - - - UIFCPY - UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 - - 31 - 1 - read-only - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x00000000 - - - PSC - Prescaler value - 0 - 16 - - - 0 - 65535 - - - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - 0 - 65535 - - - - - - - 2 - 0x4 - 1-2 - CCR%s - CCR1 - capture/compare register - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR - Capture/Compare value - 0 - 16 - - - 0 - 65535 - - - - - - - - - TIM12 - TIM - 0x40001800 - - - TIM10 - General-purpose-timers - TIM - 0x40014400 - - 0x0 - 0x400 - registers - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - CKD - Clock division - 8 - 2 - - CKD - read-write - - Div1 - t_DTS = t_CK_INT - 0 - - - Div2 - t_DTS = 2 Γ— t_CK_INT - 1 - - - Div4 - t_DTS = 4 Γ— t_CK_INT - 2 - - - - - ARPE - Auto-reload preload enable - 7 - 1 - - ARPE - read-write - - Disabled - TIMx_APRR register is not buffered - 0 - - - Enabled - TIMx_APRR register is buffered - 1 - - - - - URS - Update request source - 2 - 1 - - URS - read-write - - AnyEvent - Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - 0 - - - CounterOnly - Only counter overflow/underflow generates an update interrupt or DMA request - 1 - - - - - UDIS - Update disable - 1 - 1 - - UDIS - read-write - - Enabled - Update event enabled - 0 - - - Disabled - Update event disabled - 1 - - - - - CEN - Counter enable - 0 - 1 - - CEN - read-write - - Disabled - Counter disabled - 0 - - - Enabled - Counter enabled - 1 - - - - - OPM - One-pulse mode - 3 - 1 - - OPM - read-write - - Disabled - Counter is not stopped at update event - 0 - - - Enabled - Counter stops counting at the next update event (clearing the CEN bit) - 1 - - - - - UIFREMAP - UIF status bit remapping - 11 - 1 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x00000000 - - - CC1IE - Capture/Compare 1 interrupt enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - UIE - read-write - - Disabled - Update interrupt disabled - 0 - - - Enabled - Update interrupt enabled - 1 - - - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x00000000 - - - CC1OF - Capture/Compare 1 overcapture flag - 9 - 1 - - - CC1IF - Capture/compare 1 interrupt flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - zeroToClear - - UIFR - read - - NoUpdateOccurred - No update occurred - 0 - - - UpdatePending - Update interrupt pending - 1 - - - - UIFW - write - - Clear - Clear flag - 0 - - - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x00000000 - - - CC1G - Capture/compare 1 generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - UG - write - - Update - Re-initializes the timer counter and generates an update of the registers. - 1 - - - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC1M - Output Compare 1 mode - 4 - 3 - - OC1M - read-write - - Frozen - The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - 0 - - - ActiveOnMatch - Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - 1 - - - InactiveOnMatch - Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - 2 - - - Toggle - OCyREF toggles when TIMx_CNT=TIMx_CCRy - 3 - - - ForceInactive - OCyREF is forced low - 4 - - - ForceActive - OCyREF is forced high - 5 - - - PwmMode1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active - 6 - - - PwmMode2 - Inversely to PwmMode1 - 7 - - - - - OC1PE - Output Compare 1 preload enable - 3 - 1 - - - OC1FE - Output Compare 1 fast enable - 2 - 1 - - - CC1S - Capture/Compare 1 selection - 0 - 2 - - - OC1M_3 - Output Compare 1 mode, bit 3 - 16 - 1 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable register - 0x20 - 0x20 - read-write - 0x00000000 - - - CC1NP - Capture/Compare 1 output Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - 0 - 65535 - - - - - UIFCPY - UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 - - 31 - 1 - read-only - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x00000000 - - - PSC - Prescaler value - 0 - 16 - - - 0 - 65535 - - - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - 0 - 65535 - - - - - - - 1 - 0x0 - 1-1 - CCR%s - CCR1 - capture/compare register - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR - Capture/Compare value - 0 - 16 - - - 0 - 65535 - - - - - - - OR - OR - option register - 0x50 - 0x20 - read-write - 0x00000000 - - - TI1_RMP - TIM11 Input 1 remapping capability - 0 - 2 - - - - - - - TIM11 - TIM - 0x40014800 - - - TIM13 - TIM - 0x40001C00 - - - TIM14 - TIM - 0x40002000 - - - TIM6 - Basic timers - TIM - 0x40001000 - - 0x0 - 0x400 - registers - - - TIM6_DAC - TIM6 global interrupt, DAC1 and DAC2 underrun - error interrupt - 54 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - ARPE - Auto-reload preload enable - 7 - 1 - - ARPE - read-write - - Disabled - TIMx_APRR register is not buffered - 0 - - - Enabled - TIMx_APRR register is buffered - 1 - - - - - OPM - One-pulse mode - 3 - 1 - - OPM - read-write - - Disabled - Counter is not stopped at update event - 0 - - - Enabled - Counter stops counting at the next update event (clearing the CEN bit) - 1 - - - - - URS - Update request source - 2 - 1 - - URS - read-write - - AnyEvent - Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - 0 - - - CounterOnly - Only counter overflow/underflow generates an update interrupt or DMA request - 1 - - - - - UDIS - Update disable - 1 - 1 - - UDIS - read-write - - Enabled - Update event enabled - 0 - - - Disabled - Update event disabled - 1 - - - - - CEN - Counter enable - 0 - 1 - - CEN - read-write - - Disabled - Counter disabled - 0 - - - Enabled - Counter enabled - 1 - - - - - UIFREMAP - UIF status bit remapping - 11 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - MMS - Master mode selection - 4 - 3 - - MMS - read-write - - Reset - Use UG bit from TIMx_EGR register - 0 - - - Enable - Use CNT bit from TIMx_CEN register - 1 - - - Update - Use the update event - 2 - - - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x00000000 - - - UDE - Update DMA request enable - 8 - 1 - - UDE - read-write - - Disabled - Update DMA request disabled - 0 - - - Enabled - Update DMA request enabled - 1 - - - - - UIE - Update interrupt enable - 0 - 1 - - UIE - read-write - - Disabled - Update interrupt disabled - 0 - - - Enabled - Update interrupt enabled - 1 - - - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x00000000 - - - UIF - Update interrupt flag - 0 - 1 - zeroToClear - - UIFR - read - - NoUpdateOccurred - No update occurred - 0 - - - UpdatePending - Update interrupt pending - 1 - - - - UIFW - write - - Clear - Clear flag - 0 - - - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x00000000 - - - UG - Update generation - 0 - 1 - - UG - write - - Update - Re-initializes the timer counter and generates an update of the registers. - 1 - - - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - Low counter value - 0 - 16 - - - 0 - 65535 - - - - - UIFCPY - UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 - - 31 - 1 - read-only - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x00000000 - - - PSC - Prescaler value - 0 - 16 - - - 0 - 65535 - - - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Low Auto-reload value - 0 - 16 - - - 0 - 65535 - - - - - - - - - TIM7 - TIM - 0x40001400 - - TIM7 - TIM7 global interrupt - 55 - - - - Ethernet_MAC - Ethernet: media access control (MAC) - Ethernet - 0x40028000 - - 0x0 - 0x100 - registers - - - - MACCR - MACCR - Ethernet MAC configuration register - 0x0 - 0x20 - read-write - 0x00008000 - - - RE - Receiver enable - 2 - 1 - - RE - read-write - - Disabled - MAC receive state machine is disabled after the completion of the reception of the current frame - 0 - - - Enabled - MAC receive state machine is enabled - 1 - - - - - TE - Transmitter enable - 3 - 1 - - TE - read-write - - Disabled - MAC transmit state machine is disabled after completion of the transmission of the current frame - 0 - - - Enabled - MAC transmit state machine is enabled - 1 - - - - - DC - Deferral check - 4 - 1 - - DC - read-write - - Disabled - MAC defers until CRS signal goes inactive - 0 - - - Enabled - Deferral check function enabled - 1 - - - - - BL - Back-off limit - 5 - 2 - - BL - read-write - - BL10 - For retransmission n, wait up to 2^min(n, 10) time slots - 0 - - - BL8 - For retransmission n, wait up to 2^min(n, 8) time slots - 1 - - - BL4 - For retransmission n, wait up to 2^min(n, 4) time slots - 2 - - - BL1 - For retransmission n, wait up to 2^min(n, 1) time slots - 3 - - - - - APCS - Automatic pad/CRC stripping - 7 - 1 - - APCS - read-write - - Disabled - MAC passes all incoming frames unmodified - 0 - - - Strip - MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes - 1 - - - - - RD - Retry disable - 9 - 1 - - RD - read-write - - Enabled - MAC attempts retries based on the settings of BL - 0 - - - Disabled - MAC attempts only 1 transmission - 1 - - - - - IPCO - IPv4 checksum offload - 10 - 1 - - IPCO - read-write - - Disabled - IPv4 checksum offload disabled - 0 - - - Offload - IPv4 checksums are checked in received frames - 1 - - - - - DM - Duplex mode - 11 - 1 - - DM - read-write - - HalfDuplex - MAC operates in half-duplex mode - 0 - - - FullDuplex - MAC operates in full-duplex mode - 1 - - - - - LM - Loopback mode - 12 - 1 - - LM - read-write - - Normal - Normal mode - 0 - - - Loopback - MAC operates in loopback mode at the MII - 1 - - - - - ROD - Receive own disable - 13 - 1 - - ROD - read-write - - Enabled - MAC receives all packets from PHY while transmitting - 0 - - - Disabled - MAC disables reception of frames in half-duplex mode - 1 - - - - - FES - Fast Ethernet speed - 14 - 1 - - FES - read-write - - FES10 - 10 Mbit/s - 0 - - - FES100 - 100 Mbit/s - 1 - - - - - CSD - Carrier sense disable - 16 - 1 - - CSD - read-write - - Enabled - Errors generated due to loss of carrier - 0 - - - Disabled - No error generated due to loss of carrier - 1 - - - - - IFG - Interframe gap - 17 - 3 - - IFG - read-write - - IFG96 - 96 bit times - 0 - - - IFG88 - 88 bit times - 1 - - - IFG80 - 80 bit times - 2 - - - IFG72 - 72 bit times - 3 - - - IFG64 - 64 bit times - 4 - - - IFG56 - 56 bit times - 5 - - - IFG48 - 48 bit times - 6 - - - IFG40 - 40 bit times - 7 - - - - - JD - Jabber disable - 22 - 1 - - JD - read-write - - Enabled - Jabber enabled, transmit frames up to 2048 bytes - 0 - - - Disabled - Jabber disabled, transmit frames up to 16384 bytes - 1 - - - - - WD - Watchdog disable - 23 - 1 - - WD - read-write - - Enabled - Watchdog enabled, receive frames limited to 2048 bytes - 0 - - - Disabled - Watchdog disabled, receive frames may be up to to 16384 bytes - 1 - - - - - CSTF - CRC stripping for type frames - 25 - 1 - - CSTF - read-write - - Disabled - CRC not stripped - 0 - - - Enabled - CRC stripped - 1 - - - - - - - MACFFR - MACFFR - Ethernet MAC frame filter register - 0x4 - 0x20 - read-write - 0x00000000 - - - PM - Promiscuous mode - 0 - 1 - - PM - read-write - - Disabled - Normal address filtering - 0 - - - Enabled - Address filters pass all incoming frames regardless of their destination or source address - 1 - - - - - HU - Hash unicast - 1 - 1 - - HU - read-write - - Perfect - MAC performs a perfect destination address filtering for unicast frames - 0 - - - Hash - MAC performs destination address filtering of received unicast frames according to the hash table - 1 - - - - - HM - Hash multicast - 2 - 1 - - HM - read-write - - Perfect - MAC performs a perfect destination address filtering for multicast frames - 0 - - - Hash - MAC performs destination address filtering of received multicast frames according to the hash table - 1 - - - - - DAIF - Destination address unique filtering - 3 - 1 - - DAIF - read-write - - Normal - Normal filtering of frames - 0 - - - Invert - Address check block operates in inverse filtering mode for the DA address comparison - 1 - - - - - PAM - Pass all multicast - 4 - 1 - - PAM - read-write - - Disabled - Filtering of multicast frames depends on HM - 0 - - - Enabled - All received frames with a multicast destination address are passed - 1 - - - - - BFD - Broadcast frames disable - 5 - 1 - - BFD - read-write - - Enabled - Address filters pass all received broadcast frames - 0 - - - Disabled - Address filters filter all incoming broadcast frames - 1 - - - - - PCF - Pass control frames - 6 - 2 - - PCF - read-write - - PreventAll - MAC prevents all control frames from reaching the application - 0 - - - ForwardAllExceptPause - MAC forwards all control frames to application except Pause - 1 - - - ForwardAll - MAC forwards all control frames to application even if they fail the address filter - 2 - - - ForwardAllFiltered - MAC forwards control frames that pass the address filter - 3 - - - - - SAIF - Source address inverse filtering - 7 - 1 - - SAIF - read-write - - Normal - Source address filter operates normally - 0 - - - Invert - Source address filter operation inverted - 1 - - - - - SAF - Source address filter - 8 - 1 - - SAF - read-write - - Disabled - Source address ignored - 0 - - - Enabled - MAC drops frames that fail the source address filter - 1 - - - - - HPF - Hash or perfect filter - 9 - 1 - - HPF - read-write - - HashOnly - If HM or HU is set, only frames that match the Hash filter are passed - 0 - - - HashOrPerfect - If HM or HU is set, frames that match either the perfect filter or the hash filter are passed - 1 - - - - - RA - Receive all - 31 - 1 - - RA - read-write - - Disabled - MAC receiver passes on to the application only those frames that have passed the SA/DA address file - 0 - - - Enabled - MAC receiver passes oll received frames on to the application - 1 - - - - - - - MACHTHR - MACHTHR - Ethernet MAC hash table high register - 0x8 - 0x20 - read-write - 0x00000000 - - - HTH - Upper 32 bits of hash table - 0 - 32 - - - 0 - 4294967295 - - - - - - - MACHTLR - MACHTLR - Ethernet MAC hash table low register - 0xC - 0x20 - read-write - 0x00000000 - - - HTL - Lower 32 bits of hash table - 0 - 32 - - - 0 - 4294967295 - - - - - - - MACMIIAR - MACMIIAR - Ethernet MAC MII address register - 0x10 - 0x20 - read-write - 0x00000000 - - - MB - MII busy - 0 - 1 - - MB - read-write - - Busy - This bit is set to 1 by the application to indicate that a read or write access is in progress - 1 - - - - - MW - MII write - 1 - 1 - - MW - read-write - - Read - Read operation - 0 - - - Write - Write operation - 1 - - - - - CR - Clock range - 2 - 3 - - CR - read-write - - CR_60_100 - 60-100MHz HCLK/42 - 0 - - - CR_100_150 - 100-150 MHz HCLK/62 - 1 - - - CR_20_35 - 20-35MHz HCLK/16 - 2 - - - CR_35_60 - 35-60MHz HCLK/16 - 3 - - - CR_150_168 - 150-168MHz HCLK/102 - 4 - - - - - MR - MII register - select the desired MII register in the PHY device - 6 - 5 - - - 0 - 31 - - - - - PA - PHY address - select which of possible 32 PHYs is being accessed - 11 - 5 - - - 0 - 31 - - - - - - - MACMIIDR - MACMIIDR - Ethernet MAC MII data register - 0x14 - 0x20 - read-write - 0x00000000 - - - MD - MII data read from/written to the PHY - 0 - 16 - - - 0 - 65535 - - - - - - - MACFCR - MACFCR - Ethernet MAC flow control register - 0x18 - 0x20 - read-write - 0x00000000 - - - FCB - Flow control busy/back pressure activate - 0 - 1 - - FCB - read-write - - DisableBackPressure - In half duplex only, deasserts back pressure - 0 - - - PauseOrBackPressure - In full duplex, initiate a Pause control frame. In half duplex, assert back pressure - 1 - - - - - TFCE - Transmit flow control enable - 1 - 1 - - TFCE - read-write - - Disabled - In full duplex, flow control is disabled. In half duplex, back pressure is disabled - 0 - - - Enabled - In full duplex, flow control is enabled. In half duplex, back pressure is enabled - 1 - - - - - RFCE - Receive flow control enable - 2 - 1 - - RFCE - read-write - - Disabled - Pause frames are not decoded - 0 - - - Enabled - MAC decodes received Pause frames and disables its transmitted for a specified time - 1 - - - - - UPFD - Unicast pause frame detect - 3 - 1 - - UPFD - read-write - - Disabled - MAC detects only a Pause frame with the multicast address specified in the 802.3x standard - 0 - - - Enabled - MAC additionally detects Pause frames with the station's unicast address - 1 - - - - - PLT - Pause low threshold - 4 - 2 - - PLT - read-write - - PLT4 - Pause time minus 4 slot times - 0 - - - PLT28 - Pause time minus 28 slot times - 1 - - - PLT144 - Pause time minus 144 slot times - 2 - - - PLT256 - Pause time minus 256 slot times - 3 - - - - - ZQPD - Zero-quanta pause disable - 7 - 1 - - ZQPD - read-write - - Enabled - Normal operation with automatic zero-quanta pause control frame generation - 0 - - - Disabled - Automatic generation of zero-quanta pause control frames is disabled - 1 - - - - - PT - Pause time - 16 - 16 - - - 0 - 65535 - - - - - - - MACVLANTR - MACVLANTR - Ethernet MAC VLAN tag register - 0x1C - 0x20 - read-write - 0x00000000 - - - VLANTI - VLAN tag identifier (for receive frames) - 0 - 16 - - - 0 - 65535 - - - - - VLANTC - 12-bit VLAN tag comparison - 16 - 1 - - VLANTC - read-write - - VLANTC16 - Full 16 bit VLAN identifiers are used for comparison and filtering - 0 - - - VLANTC12 - 12 bit VLAN identifies are used for comparison and filtering - 1 - - - - - - - MACPMTCSR - MACPMTCSR - Ethernet MAC PMT control and status register - 0x2C - 0x20 - read-write - 0x00000000 - - - PD - Power down - 0 - 1 - - PD - read-write - - Enabled - All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received - 1 - - - - - MPE - Magic packet enable - 1 - 1 - - MPE - read-write - - Disabled - No power management event generated due to Magic Packet reception - 0 - - - Enabled - Enable generation of a power management event due to Magic Packet reception - 1 - - - - - WFE - Wakeup frame enable - 2 - 1 - - WFE - read-write - - Disabled - No power management event generated due to wakeup frame reception - 0 - - - Enabled - Enable generation of a power management event due to wakeup frame reception - 1 - - - - - MPR - Magic packet received - 5 - 1 - - - WFR - Wakeup frame received - 6 - 1 - - - GU - Global unicast - 9 - 1 - - GU - read-write - - Disabled - Normal operation - 0 - - - Enabled - Any unicast packet filtered by the MAC address recognition may be a wakeup frame - 1 - - - - - WFFRPR - Wakeup frame filter register pointer reset - 31 - 1 - - WFFRPR - read-write - - Reset - Reset wakeup frame filter register point to 0b000. Automatically cleared - 1 - - - - - - - MACDBGR - MACDBGR - Ethernet MAC debug register - 0x34 - 0x20 - read-only - 0x00000000 - - - TFF - Tx FIFO full - 25 - 1 - - - TFNE - Tx FIFO not empty - 24 - 1 - - - TFWA - Tx FIFO write active - 22 - 1 - - - TFRS - Tx FIFO read status - 20 - 2 - - - MTP - MAC transmitter in pause - 19 - 1 - - - MTFCS - MAC transmit frame controller status - 17 - 2 - - - MMTEA - MAC MII transmit engine active - 16 - 1 - - - RFFL - Rx FIFO fill level - 8 - 2 - - - RFRCS - Rx FIFO read controller status - 5 - 2 - - - RFWRA - Rx FIFO write controller active - 4 - 1 - - - MSFRWCS - MAC small FIFO read/write controllers status - 1 - 2 - - - MMRPEA - MAC MII receive protocol engine active - 0 - 1 - - - - - MACSR - MACSR - Ethernet MAC interrupt status register - 0x38 - 0x20 - 0x00000000 - - - PMTS - PMT status - 3 - 1 - read-only - - - MMCS - MMC status - 4 - 1 - read-only - - - MMCRS - MMC receive status - 5 - 1 - read-only - - - MMCTS - MMC transmit status - 6 - 1 - read-only - - - TSTS - Time stamp trigger status - 9 - 1 - read-write - - - - - MACIMR - MACIMR - Ethernet MAC interrupt mask register - 0x3C - 0x20 - read-write - 0x00000000 - - - PMTIM - PMT interrupt mask - 3 - 1 - - PMTIM - read-write - - Unmasked - PMT Status interrupt generation enabled - 0 - - - Masked - PMT Status interrupt generation disabled - 1 - - - - - TSTIM - Time stamp trigger interrupt mask - 9 - 1 - - TSTIM - read-write - - Unmasked - Time stamp interrupt generation enabled - 0 - - - Masked - Time stamp interrupt generation disabled - 1 - - - - - - - MACA0HR - MACA0HR - Ethernet MAC address 0 high register - 0x40 - 0x20 - 0x0010FFFF - - - MACA0H - MAC address0 high - 0 - 16 - read-write - - - 0 - 65535 - - - - - MO - Always 1 - 31 - 1 - read-only - - - - - MACA0LR - MACA0LR - Ethernet MAC address 0 low register - 0x44 - 0x20 - read-write - 0xFFFFFFFF - - - MACA0L - 0 - 0 - 32 - - - 0 - 4294967295 - - - - - - - MACA1HR - MACA1HR - Ethernet MAC address 1 high register - 0x48 - 0x20 - read-write - 0x0000FFFF - - - MACA1H - MACA1H - 0 - 16 - - - 0 - 65535 - - - - - MBC - MBC - 24 - 6 - - - 0 - 63 - - - - - SA - SA - 30 - 1 - - SA - read-write - - Destination - This address is used for comparison with DA fields of the received frame - 0 - - - Source - This address is used for comparison with SA fields of received frames - 1 - - - - - AE - AE - 31 - 1 - - AE - read-write - - Disabled - Address filters ignore this address - 0 - - - Enabled - Address filters use this address - 1 - - - - - - - MACA1LR - MACA1LR - Ethernet MAC address1 low register - 0x4C - 0x20 - read-write - 0xFFFFFFFF - - - MACA1L - MACA1LR - 0 - 32 - - - 0 - 4294967295 - - - - - - - MACA2HR - MACA2HR - Ethernet MAC address 2 high register - 0x50 - 0x20 - read-write - 0x0000FFFF - - - MACA2H - MAC2AH - 0 - 16 - - - 0 - 65535 - - - - - MBC - MBC - 24 - 6 - - - 0 - 63 - - - - - SA - SA - 30 - 1 - - SA - read-write - - Destination - This address is used for comparison with DA fields of the received frame - 0 - - - Source - This address is used for comparison with SA fields of received frames - 1 - - - - - AE - AE - 31 - 1 - - AE - read-write - - Disabled - Address filters ignore this address - 0 - - - Enabled - Address filters use this address - 1 - - - - - - - MACA2LR - MACA2LR - Ethernet MAC address 2 low register - 0x54 - 0x20 - read-write - 0xFFFFFFFF - - - MACA2L - MACA2L - 0 - 32 - - - 0 - 4294967295 - - - - - - - MACA3HR - MACA3HR - Ethernet MAC address 3 high register - 0x58 - 0x20 - read-write - 0x0000FFFF - - - MACA3H - MACA3H - 0 - 16 - - - 0 - 65535 - - - - - MBC - MBC - 24 - 6 - - - 0 - 63 - - - - - SA - SA - 30 - 1 - - SA - read-write - - Destination - This address is used for comparison with DA fields of the received frame - 0 - - - Source - This address is used for comparison with SA fields of received frames - 1 - - - - - AE - AE - 31 - 1 - - AE - read-write - - Disabled - Address filters ignore this address - 0 - - - Enabled - Address filters use this address - 1 - - - - - - - MACA3LR - MACA3LR - Ethernet MAC address 3 low register - 0x5C - 0x20 - read-write - 0xFFFFFFFF - - - MACA3L - MBCA3L - 0 - 32 - - - 0 - 4294967295 - - - - - - - MACRWUFFER - MACRWUFFER - Ethernet MAC remote wakeup frame filter register - 0x60 - 0x20 - read-write - 0xFFFFFFFF - - - - - Ethernet_MMC - Ethernet: MAC management counters - Ethernet - 0x40028100 - - 0x0 - 0x400 - registers - - - - MMCCR - MMCCR - Ethernet MMC control register - 0x0 - 0x20 - read-write - 0x00000000 - - - CR - Counter reset - 0 - 1 - - CR - read-write - - Reset - Reset all counters. Cleared automatically - 1 - - - - - CSR - Counter stop rollover - 1 - 1 - - CSR - read-write - - Disabled - Counters roll over to zero after reaching the maximum value - 0 - - - Enabled - Counters do not roll over to zero after reaching the maximum value - 1 - - - - - ROR - Reset on read - 2 - 1 - - ROR - read-write - - Disabled - MMC counters do not reset on read - 0 - - - Enabled - MMC counters reset to zero after read - 1 - - - - - MCF - MMC counter freeze - 3 - 1 - - MCF - read-write - - Unfrozen - All MMC counters update normally - 0 - - - Frozen - All MMC counters frozen to their current value - 1 - - - - - MCP - MMC counter preset - 4 - 1 - - MCP - read-write - - Preset - MMC counters will be preset to almost full or almost half. Cleared automatically - 1 - - - - - MCFHP - MMC counter Full-Half preset - 5 - 1 - - MCFHP - read-write - - AlmostHalf - When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0 - 0 - - - AlmostFull - When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0 - 1 - - - - - - - MMCRIR - MMCRIR - Ethernet MMC receive interrupt register - 0x4 - 0x20 - read-write - 0x00000000 - - - RFCES - Received frames CRC error status - 5 - 1 - - - RFAES - Received frames alignment error status - 6 - 1 - - - RGUFS - Received good Unicast frames status - 17 - 1 - - - - - MMCTIR - MMCTIR - Ethernet MMC transmit interrupt register - 0x8 - 0x20 - read-only - 0x00000000 - - - TGFSCS - Transmitted good frames single collision status - 14 - 1 - - - TGFMSCS - Transmitted good frames more than single collision status - 15 - 1 - - - TGFS - Transmitted good frames status - 21 - 1 - - - - - MMCRIMR - MMCRIMR - Ethernet MMC receive interrupt mask register - 0xC - 0x20 - read-write - 0x00000000 - - - RFCEM - Received frame CRC error mask - 5 - 1 - - RFCEM - read-write - - Unmasked - Received-crc-error counter half-full interrupt enabled - 0 - - - Masked - Received-crc-error counter half-full interrupt disabled - 1 - - - - - RFAEM - Received frames alignment error mask - 6 - 1 - - RFAEM - read-write - - Unmasked - Received-alignment-error counter half-full interrupt enabled - 0 - - - Masked - Received-alignment-error counter half-full interrupt disabled - 1 - - - - - RGUFM - Received good Unicast frames mask - 17 - 1 - - RGUFM - read-write - - Unmasked - Received-good-unicast counter half-full interrupt enabled - 0 - - - Masked - Received-good-unicast counter half-full interrupt disabled - 1 - - - - - - - MMCTIMR - MMCTIMR - Ethernet MMC transmit interrupt mask register - 0x10 - 0x20 - read-write - 0x00000000 - - - TGFSCM - Transmitted good frames single collision mask - 14 - 1 - - TGFSCM - read-write - - Unmasked - Transmitted-good-single-collision half-full interrupt enabled - 0 - - - Masked - Transmitted-good-single-collision half-full interrupt disabled - 1 - - - - - TGFMSCM - Transmitted good frames more than single collision mask - 15 - 1 - - TGFMSCM - read-write - - Unmasked - Transmitted-good-multiple-collision half-full interrupt enabled - 0 - - - Masked - Transmitted-good-multiple-collision half-full interrupt disabled - 1 - - - - - TGFM - Transmitted good frames mask - 21 - 1 - - TGFM - read-write - - Unmasked - Transmitted-good counter half-full interrupt enabled - 0 - - - Masked - Transmitted-good counter half-full interrupt disabled - 1 - - - - - - - MMCTGFSCCR - MMCTGFSCCR - Ethernet MMC transmitted good frames after a single collision counter - 0x4C - 0x20 - read-only - 0x00000000 - - - TGFSCC - Transmitted good frames single collision counter - 0 - 32 - - - - - MMCTGFMSCCR - MMCTGFMSCCR - Ethernet MMC transmitted good frames after more than a single collision - 0x50 - 0x20 - read-only - 0x00000000 - - - TGFMSCC - TGFMSCC - 0 - 32 - - - - - MMCTGFCR - MMCTGFCR - Ethernet MMC transmitted good frames counter register - 0x68 - 0x20 - read-only - 0x00000000 - - - TGFC - HTL - 0 - 32 - - - - - MMCRFCECR - MMCRFCECR - Ethernet MMC received frames with CRC error counter register - 0x94 - 0x20 - read-only - 0x00000000 - - - RFCFC - RFCFC - 0 - 32 - - - - - MMCRFAECR - MMCRFAECR - Ethernet MMC received frames with alignment error counter register - 0x98 - 0x20 - read-only - 0x00000000 - - - RFAEC - RFAEC - 0 - 32 - - - - - MMCRGUFCR - MMCRGUFCR - MMC received good unicast frames counter register - 0xC4 - 0x20 - read-only - 0x00000000 - - - RGUFC - RGUFC - 0 - 32 - - - - - - - Ethernet_PTP - Ethernet: Precision time protocol - Ethernet - 0x40028700 - - 0x0 - 0x400 - registers - - - - PTPTSCR - PTPTSCR - Ethernet PTP time stamp control register - 0x0 - 0x20 - read-write - 0x00002000 - - - TSE - TSE - 0 - 1 - - - TSFCU - TSFCU - 1 - 1 - - - TSPTPPSV2E - TSPTPPSV2E - 10 - 1 - - - TSSPTPOEFE - TSSPTPOEFE - 11 - 1 - - - TSSIPV6FE - TSSIPV6FE - 12 - 1 - - - TSSIPV4FE - TSSIPV4FE - 13 - 1 - - - TSSEME - TSSEME - 14 - 1 - - - TSSMRME - TSSMRME - 15 - 1 - - - TSCNT - TSCNT - 16 - 2 - - - TSPFFMAE - TSPFFMAE - 18 - 1 - - - TSSTI - TSSTI - 2 - 1 - - - TSSTU - TSSTU - 3 - 1 - - - TSITE - TSITE - 4 - 1 - - - TTSARU - TTSARU - 5 - 1 - - - TSSARFE - TSSARFE - 8 - 1 - - - TSSSR - TSSSR - 9 - 1 - - - - - PTPSSIR - PTPSSIR - Ethernet PTP subsecond increment register - 0x4 - 0x20 - read-write - 0x00000000 - - - STSSI - STSSI - 0 - 8 - - - - - PTPTSHR - PTPTSHR - Ethernet PTP time stamp high register - 0x8 - 0x20 - read-only - 0x00000000 - - - STS - STS - 0 - 32 - - - - - PTPTSLR - PTPTSLR - Ethernet PTP time stamp low register - 0xC - 0x20 - read-only - 0x00000000 - - - STSS - STSS - 0 - 31 - - - STPNS - STPNS - 31 - 1 - - - - - PTPTSHUR - PTPTSHUR - Ethernet PTP time stamp high update register - 0x10 - 0x20 - read-write - 0x00000000 - - - TSUS - TSUS - 0 - 32 - - - - - PTPTSLUR - PTPTSLUR - Ethernet PTP time stamp low update register - 0x14 - 0x20 - read-write - 0x00000000 - - - TSUSS - TSUSS - 0 - 31 - - - TSUPNS - TSUPNS - 31 - 1 - - - - - PTPTSAR - PTPTSAR - Ethernet PTP time stamp addend register - 0x18 - 0x20 - read-write - 0x00000000 - - - TSA - TSA - 0 - 32 - - - - - PTPTTHR - PTPTTHR - Ethernet PTP target time high register - 0x1C - 0x20 - read-write - 0x00000000 - - - TTSH - 0 - 0 - 32 - - - - - PTPTTLR - PTPTTLR - Ethernet PTP target time low register - 0x20 - 0x20 - read-write - 0x00000000 - - - TTSL - TTSL - 0 - 32 - - - - - PTPTSSR - PTPTSSR - Ethernet PTP time stamp status register - 0x28 - 0x20 - read-only - 0x00000000 - - - TSSO - TSSO - 0 - 1 - - - TSTTR - TSTTR - 1 - 1 - - - - - PTPPPSCR - PTPPPSCR - Ethernet PTP PPS control register - 0x2C - 0x20 - read-only - 0x00000000 - - - TSSO - TSSO - 0 - 1 - - - TSTTR - TSTTR - 1 - 1 - - - - - - - Ethernet_DMA - Ethernet: DMA controller operation - Ethernet - 0x40029000 - - 0x0 - 0x400 - registers - - - ETH - Ethernet global interrupt - 61 - - - ETH_WKUP - Ethernet Wakeup through EXTI line - interrupt - 62 - - - - DMABMR - DMABMR - Ethernet DMA bus mode register - 0x0 - 0x20 - read-write - 0x00002101 - - - SR - Software reset - 0 - 1 - - SR - read-write - - Reset - Reset all MAC subsystem internal registers and logic. Cleared automatically - 1 - - - - - DA - DMA arbitration - 1 - 1 - - DA - read-write - - RoundRobin - Round-robin with Rx:Tx priority given by PM - 0 - - - RxPriority - Rx has priority over Tx - 1 - - - - - DSL - Descriptor skip length - 2 - 5 - - - 0 - 31 - - - - - EDFE - Enhanced descriptor format enable - 7 - 1 - - EDFE - read-write - - Disabled - Normal descriptor format - 0 - - - Enabled - Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload - 1 - - - - - PBL - Programmable burst length - 8 - 6 - - PBL - read-write - - PBL1 - Maximum of 1 beat per DMA transaction - 1 - - - PBL2 - Maximum of 2 beats per DMA transaction - 2 - - - PBL4 - Maximum of 4 beats per DMA transaction - 4 - - - PBL8 - Maximum of 8 beats per DMA transaction - 8 - - - PBL16 - Maximum of 16 beats per DMA transaction - 16 - - - PBL32 - Maximum of 32 beats per DMA transaction - 32 - - - - - PM - Rx-Tx priority ratio - 14 - 2 - - PM - read-write - - OneToOne - RxDMA priority over TxDMA is 1:1 - 0 - - - TwoToOne - RxDMA priority over TxDMA is 2:1 - 1 - - - ThreeToOne - RxDMA priority over TxDMA is 3:1 - 2 - - - FourToOne - RxDMA priority over TxDMA is 4:1 - 3 - - - - - FB - Fixed burst - 16 - 1 - - FB - read-write - - Variable - AHB uses SINGLE and INCR burst transfers - 0 - - - Fixed - AHB uses only fixed burst transfers - 1 - - - - - RDP - Rx DMA PBL - 17 - 6 - - RDP - read-write - - RDP1 - 1 beat per RxDMA transaction - 1 - - - RDP2 - 2 beats per RxDMA transaction - 2 - - - RDP4 - 4 beats per RxDMA transaction - 4 - - - RDP8 - 8 beats per RxDMA transaction - 8 - - - RDP16 - 16 beats per RxDMA transaction - 16 - - - RDP32 - 32 beats per RxDMA transaction - 32 - - - - - USP - Use separate PBL - 23 - 1 - - USP - read-write - - Combined - PBL value used for both Rx and Tx DMA - 0 - - - Separate - RxDMA uses RDP value, TxDMA uses PBL value - 1 - - - - - FPM - 4xPBL mode - 24 - 1 - - FPM - read-write - - x1 - PBL values used as-is - 0 - - - x4 - PBL values multiplied by 4 - 1 - - - - - AAB - Address-aligned beats - 25 - 1 - - AAB - read-write - - Unaligned - Bursts are not aligned - 0 - - - Aligned - Align bursts to start address LS bits. First burst alignment depends on FB bit - 1 - - - - - MB - Mixed burst - 26 - 1 - - MB - read-write - - Normal - Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below - 0 - - - Mixed - If FB is low, start all bursts greater than 16 with INCR (undefined burst) - 1 - - - - - - - DMATPDR - DMATPDR - Ethernet DMA transmit poll demand register - 0x4 - 0x20 - read-write - 0x00000000 - - - TPD - Transmit poll demand - 0 - 32 - - TPD - read-write - - Poll - Poll the transmit descriptor list - 0 - - - - - - - DMARPDR - DMARPDR - EHERNET DMA receive poll demand register - 0x8 - 0x20 - read-write - 0x00000000 - - - RPD - Receive poll demand - 0 - 32 - - RPD - read-write - - Poll - Poll the receive descriptor list - 0 - - - - - - - DMARDLAR - DMARDLAR - Ethernet DMA receive descriptor list address register - 0xC - 0x20 - read-write - 0x00000000 - - - SRL - Start of receive list - 0 - 32 - - - - - DMATDLAR - DMATDLAR - Ethernet DMA transmit descriptor list address register - 0x10 - 0x20 - read-write - 0x00000000 - - - STL - Start of transmit list - 0 - 32 - - - - - DMASR - DMASR - Ethernet DMA status register - 0x14 - 0x20 - 0x00000000 - - - TS - Transmit status - 0 - 1 - read-write - - - TPSS - Transmit process stopped status - 1 - 1 - read-write - - - TBUS - Transmit buffer unavailable status - 2 - 1 - read-write - - - TJTS - Transmit jabber timeout status - 3 - 1 - read-write - - - ROS - Receive overflow status - 4 - 1 - read-write - - - TUS - Transmit underflow status - 5 - 1 - read-write - - - RS - Receive status - 6 - 1 - read-write - - - RBUS - Receive buffer unavailable status - 7 - 1 - read-write - - - RPSS - Receive process stopped status - 8 - 1 - read-write - - - PWTS - PWTS - 9 - 1 - read-write - - - ETS - Early transmit status - 10 - 1 - read-write - - - FBES - Fatal bus error status - 13 - 1 - read-write - - - ERS - Early receive status - 14 - 1 - read-write - - - AIS - Abnormal interrupt summary - 15 - 1 - read-write - - - NIS - Normal interrupt summary - 16 - 1 - read-write - - - RPS - Receive process state - 17 - 3 - read-only - - RPS - read - - Stopped - Stopped, reset or Stop Receive command issued - 0 - - - RunningFetching - Running, fetching receive transfer descriptor - 1 - - - RunningWaiting - Running, waiting for receive packet - 3 - - - Suspended - Suspended, receive descriptor unavailable - 4 - - - RunningWriting - Running, writing data to host memory buffer - 7 - - - - - TPS - Transmit process state - 20 - 3 - read-only - - TPS - read - - Stopped - Stopped, Reset or Stop Transmit command issued - 0 - - - RunningFetching - Running, fetching transmit transfer descriptor - 1 - - - RunningWaiting - Running, waiting for status - 2 - - - RunningReading - Running, reading data from host memory buffer - 3 - - - Suspended - Suspended, transmit descriptor unavailable or transmit buffer underflow - 6 - - - Running - Running, closing transmit descriptor - 7 - - - - - EBS - Error bits status - 23 - 3 - read-only - - - MMCS - MMC status - 27 - 1 - read-only - - - PMTS - PMT status - 28 - 1 - read-only - - - TSTS - Time stamp trigger status - 29 - 1 - read-only - - - - - DMAOMR - DMAOMR - Ethernet DMA operation mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - SR - Start/stop receive - 1 - 1 - - SR - read-write - - Stopped - Reception is stopped after transfer of the current frame - 0 - - - Started - Reception is placed in the Running state - 1 - - - - - OSF - Operate on second frame - 2 - 1 - - - RTC - Receive threshold control - 3 - 2 - - RTC - read-write - - RTC64 - 64 bytes - 0 - - - RTC32 - 32 bytes - 1 - - - RTC96 - 96 bytes - 2 - - - RTC128 - 128 bytes - 3 - - - - - FUGF - Forward undersized good frames - 6 - 1 - - FUGF - read-write - - Drop - Rx FIFO drops all frames of less than 64 bytes - 0 - - - Forward - Rx FIFO forwards undersized frames - 1 - - - - - FEF - Forward error frames - 7 - 1 - - FEF - read-write - - Drop - Rx FIFO drops frames with error status - 0 - - - Forward - All frames except runt error frames are forwarded to the DMA - 1 - - - - - ST - Start/stop transmission - 13 - 1 - - ST - read-write - - Stopped - Transmission is placed in the Stopped state - 0 - - - Started - Transmission is placed in Running state - 1 - - - - - TTC - Transmit threshold control - 14 - 3 - - TTC - read-write - - TTC64 - 64 bytes - 0 - - - TTC128 - 128 bytes - 1 - - - TTC192 - 192 bytes - 2 - - - TTC256 - 256 bytes - 3 - - - TTC40 - 40 bytes - 4 - - - TTC32 - 32 bytes - 5 - - - TTC24 - 24 bytes - 6 - - - TTC16 - 16 bytes - 7 - - - - - FTF - Flush transmit FIFO - 20 - 1 - - FTF - read-write - - Flush - Transmit FIFO controller logic is reset to its default values. Cleared automatically - 1 - - - - - TSF - Transmit store and forward - 21 - 1 - - TSF - read-write - - CutThrough - Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold - 0 - - - StoreForward - Transmission starts when a full frame is in the Tx FIFO - 1 - - - - - DFRF - Disable flushing of received frames - 24 - 1 - - - RSF - Receive store and forward - 25 - 1 - - RSF - read-write - - CutThrough - Rx FIFO operates in cut-through mode, subject to RTC bits - 0 - - - StoreForward - Frames are read from Rx FIFO after complete frame has been written - 1 - - - - - DTCEFD - Dropping of TCP/IP checksum error frames disable - 26 - 1 - - DTCEFD - read-write - - Enabled - Drop frames with errors only in the receive checksum offload engine - 0 - - - Disabled - Do not drop frames that only have errors in the receive checksum offload engine - 1 - - - - - - - DMAIER - DMAIER - Ethernet DMA interrupt enable register - 0x1C - 0x20 - read-write - 0x00000000 - - - TIE - Transmit interrupt enable - 0 - 1 - - - TPSIE - Transmit process stopped interrupt enable - 1 - 1 - - - TBUIE - Transmit buffer unavailable interrupt enable - 2 - 1 - - - TJTIE - Transmit jabber timeout interrupt enable - 3 - 1 - - - ROIE - Receive overflow interrupt enable - 4 - 1 - - - TUIE - Transmit underflow interrupt enable - 5 - 1 - - - RIE - Receive interrupt enable - 6 - 1 - - - RBUIE - Receive buffer unavailable interrupt enable - 7 - 1 - - - RPSIE - Receive process stopped interrupt enable - 8 - 1 - - - RWTIE - Receive watchdog timeout interrupt enable - 9 - 1 - - - ETIE - Early transmit interrupt enable - 10 - 1 - - - FBEIE - Fatal bus error interrupt enable - 13 - 1 - - - ERIE - Early receive interrupt enable - 14 - 1 - - - AISE - Abnormal interrupt summary enable - 15 - 1 - - - NISE - Normal interrupt summary enable - 16 - 1 - - - - - DMAMFBOCR - DMAMFBOCR - Ethernet DMA missed frame and buffer overflow counter register - 0x20 - 0x20 - read-write - 0x00000000 - - - MFC - Missed frames by the controller - 0 - 16 - - - OMFC - Overflow bit for missed frame counter - 16 - 1 - - - MFA - Missed frames by the application - 17 - 11 - - - OFOC - Overflow bit for FIFO overflow counter - 28 - 1 - - - - - DMARSWTR - DMARSWTR - Ethernet DMA receive status watchdog timer register - 0x24 - 0x20 - read-write - 0x00000000 - - - RSWTC - Receive status watchdog timer count - 0 - 8 - - - 0 - 255 - - - - - - - DMACHTDR - DMACHTDR - Ethernet DMA current host transmit descriptor register - 0x48 - 0x20 - read-only - 0x00000000 - - - HTDAP - Host transmit descriptor address pointer - 0 - 32 - - - - - DMACHRDR - DMACHRDR - Ethernet DMA current host receive descriptor register - 0x4C - 0x20 - read-only - 0x00000000 - - - HRDAP - Host receive descriptor address pointer - 0 - 32 - - - - - DMACHTBAR - DMACHTBAR - Ethernet DMA current host transmit buffer address register - 0x50 - 0x20 - read-only - 0x00000000 - - - HTBAP - Host transmit buffer address pointer - 0 - 32 - - - - - DMACHRBAR - DMACHRBAR - Ethernet DMA current host receive buffer address register - 0x54 - 0x20 - read-only - 0x00000000 - - - HRBAP - Host receive buffer address pointer - 0 - 32 - - - - - - - CRC - Cryptographic processor - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - HDMI_CEC - HDMI-CEC global interrupt - 94 - - - - DR - DR - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DR - Data Register - 0 - 32 - - - 0 - 4294967295 - - - - - - - IDR - IDR - Independent Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - IDR - Independent Data register - 0 - 8 - - - 0 - 255 - - - - - - - CR - CR - Control register - 0x8 - 0x20 - write-only - 0x00000000 - - - RESET - RESET bit - 0 - 1 - - RESETW - write - - Reset - Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF - 1 - - - - - REV_OUT - Reverse output data - 7 - 1 - read-write - - REV_OUT - read-write - - Normal - Bit order not affected - 0 - - - Reversed - Bit reversed output - 1 - - - - - REV_IN - Reverse input data - 5 - 2 - read-write - - REV_IN - read-write - - Normal - Bit order not affected - 0 - - - Byte - Bit reversal done by byte - 1 - - - HalfWord - Bit reversal done by half-word - 2 - - - Word - Bit reversal done by word - 3 - - - - - POLYSIZE - Polynomial size - 3 - 2 - read-write - - POLYSIZE - read-write - - Polysize32 - 32-bit polynomial - 0 - - - Polysize16 - 16-bit polynomial - 1 - - - Polysize8 - 8-bit polynomial - 2 - - - Polysize7 - 7-bit polynomial - 3 - - - - - - - INIT - INIT - Initial CRC value - 0x10 - 0x20 - read-write - 0x00000000 - - - INIT - Programmable initial CRC value - 0 - 32 - - - 0 - 4294967295 - - - - - - - POL - POL - CRC polynomial - 0x14 - 0x20 - read-write - 0x00000000 - - - POL - Programmable polynomial - 0 - 32 - - - 0 - 4294967295 - - - - - - - DR8 - Data register - byte sized - DR - 0x0 - 0x8 - read-write - 0x000000FF - - - DR8 - Data register bits - 0 - 8 - - - 0 - 255 - - - - - - - DR16 - Data register - half-word sized - DR - 0x0 - 0x10 - read-write - 0x0000FFFF - - - DR16 - Data register bits - 0 - 16 - - - 0 - 65535 - - - - - - - - - CAN1 - Controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupts - 19 - - - CAN1_RX0 - CAN1 RX0 interrupts - 20 - - - CAN1_RX1 - CAN1 RX1 interrupts - 21 - - - CAN1_SCE - CAN1 SCE interrupt - 22 - - - - MCR - MCR - master control register - 0x0 - 0x20 - read-write - 0x00010002 - - - DBF - DBF - 16 - 1 - - - RESET - RESET - 15 - 1 - - - TTCM - TTCM - 7 - 1 - - - ABOM - ABOM - 6 - 1 - - - AWUM - AWUM - 5 - 1 - - - NART - NART - 4 - 1 - - - RFLM - RFLM - 3 - 1 - - - TXFP - TXFP - 2 - 1 - - - SLEEP - SLEEP - 1 - 1 - - - INRQ - INRQ - 0 - 1 - - - - - MSR - MSR - master status register - 0x4 - 0x20 - 0x00000C02 - - - RX - RX - 11 - 1 - read-only - - - SAMP - SAMP - 10 - 1 - read-only - - - RXM - RXM - 9 - 1 - read-only - - - TXM - TXM - 8 - 1 - read-only - - - SLAKI - SLAKI - 4 - 1 - read-write - - - WKUI - WKUI - 3 - 1 - read-write - - - ERRI - ERRI - 2 - 1 - read-write - - - SLAK - SLAK - 1 - 1 - read-only - - - INAK - INAK - 0 - 1 - read-only - - - - - TSR - TSR - transmit status register - 0x8 - 0x20 - 0x1C000000 - - - LOW2 - Lowest priority flag for mailbox 2 - 31 - 1 - read-only - - - LOW1 - Lowest priority flag for mailbox 1 - 30 - 1 - read-only - - - LOW0 - Lowest priority flag for mailbox 0 - 29 - 1 - read-only - - - TME2 - Lowest priority flag for mailbox 2 - 28 - 1 - read-only - - - TME1 - Lowest priority flag for mailbox 1 - 27 - 1 - read-only - - - TME0 - Lowest priority flag for mailbox 0 - 26 - 1 - read-only - - - CODE - CODE - 24 - 2 - read-only - - - ABRQ2 - ABRQ2 - 23 - 1 - read-write - - - TERR2 - TERR2 - 19 - 1 - read-write - - - ALST2 - ALST2 - 18 - 1 - read-write - - - TXOK2 - TXOK2 - 17 - 1 - read-write - - - RQCP2 - RQCP2 - 16 - 1 - read-write - - - ABRQ1 - ABRQ1 - 15 - 1 - read-write - - - TERR1 - TERR1 - 11 - 1 - read-write - - - ALST1 - ALST1 - 10 - 1 - read-write - - - TXOK1 - TXOK1 - 9 - 1 - read-write - - - RQCP1 - RQCP1 - 8 - 1 - read-write - - - ABRQ0 - ABRQ0 - 7 - 1 - read-write - - - TERR0 - TERR0 - 3 - 1 - read-write - - - ALST0 - ALST0 - 2 - 1 - read-write - - - TXOK0 - TXOK0 - 1 - 1 - read-write - - - RQCP0 - RQCP0 - 0 - 1 - read-write - - - - - 2 - 0x4 - 0-1 - RF%sR - RF0R - receive FIFO %s register - 0xC - 0x20 - 0x00000000 - - - RFOM - RFOM0 - 5 - 1 - read-write - - RFOM0W - write - - Release - Set by software to release the output mailbox of the FIFO - 1 - - - - - FOVR - FOVR0 - 4 - 1 - read-write - - FOVR0R - read - - NoOverrun - No FIFO x overrun - 0 - - - Overrun - FIFO x overrun - 1 - - - - FOVR0W - write - - Clear - Clear flag - 1 - - - - - FULL - FULL0 - 3 - 1 - read-write - - FULL0R - read - - NotFull - FIFO x is not full - 0 - - - Full - FIFO x is full - 1 - - - - FULL0W - write - - Clear - Clear flag - 1 - - - - - FMP - FMP0 - 0 - 2 - read-only - - - - - IER - IER - interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - SLKIE - SLKIE - 17 - 1 - - SLKIE - read-write - - Disabled - No interrupt when SLAKI bit is set - 0 - - - Enabled - Interrupt generated when SLAKI bit is set - 1 - - - - - WKUIE - WKUIE - 16 - 1 - - WKUIE - read-write - - Disabled - No interrupt when WKUI is set - 0 - - - Enabled - Interrupt generated when WKUI bit is set - 1 - - - - - ERRIE - ERRIE - 15 - 1 - - ERRIE - read-write - - Disabled - No interrupt will be generated when an error condition is pending in the CAN_ESR - 0 - - - Enabled - An interrupt will be generation when an error condition is pending in the CAN_ESR - 1 - - - - - LECIE - LECIE - 11 - 1 - - LECIE - read-write - - Disabled - ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection - 0 - - - Enabled - ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection - 1 - - - - - BOFIE - BOFIE - 10 - 1 - - BOFIE - read-write - - Disabled - ERRI bit will not be set when BOFF is set - 0 - - - Enabled - ERRI bit will be set when BOFF is set - 1 - - - - - EPVIE - EPVIE - 9 - 1 - - EPVIE - read-write - - Disabled - ERRI bit will not be set when EPVF is set - 0 - - - Enabled - ERRI bit will be set when EPVF is set - 1 - - - - - EWGIE - EWGIE - 8 - 1 - - EWGIE - read-write - - Disabled - ERRI bit will not be set when EWGF is set - 0 - - - Enabled - ERRI bit will be set when EWGF is set - 1 - - - - - FOVIE1 - FOVIE1 - 6 - 1 - - FOVIE1 - read-write - - Disabled - No interrupt when FOVR is set - 0 - - - Enabled - Interrupt generation when FOVR is set - 1 - - - - - FFIE1 - FFIE1 - 5 - 1 - - FFIE1 - read-write - - Disabled - No interrupt when FULL bit is set - 0 - - - Enabled - Interrupt generated when FULL bit is set - 1 - - - - - FMPIE1 - FMPIE1 - 4 - 1 - - FMPIE1 - read-write - - Disabled - No interrupt generated when state of FMP[1:0] bits are not 00b - 0 - - - Enabled - Interrupt generated when state of FMP[1:0] bits are not 00b - 1 - - - - - FOVIE0 - FOVIE0 - 3 - 1 - - FOVIE0 - read-write - - Disabled - No interrupt when FOVR bit is set - 0 - - - Enabled - Interrupt generated when FOVR bit is set - 1 - - - - - FFIE0 - FFIE0 - 2 - 1 - - FFIE0 - read-write - - Disabled - No interrupt when FULL bit is set - 0 - - - Enabled - Interrupt generated when FULL bit is set - 1 - - - - - FMPIE0 - FMPIE0 - 1 - 1 - - FMPIE0 - read-write - - Disabled - No interrupt generated when state of FMP[1:0] bits are not 00 - 0 - - - Enabled - Interrupt generated when state of FMP[1:0] bits are not 00b - 1 - - - - - TMEIE - TMEIE - 0 - 1 - - TMEIE - read-write - - Disabled - No interrupt when RQCPx bit is set - 0 - - - Enabled - Interrupt generated when RQCPx bit is set - 1 - - - - - - - ESR - ESR - interrupt enable register - 0x18 - 0x20 - 0x00000000 - - - REC - REC - 24 - 8 - read-only - - - TEC - TEC - 16 - 8 - read-only - - - LEC - LEC - 4 - 3 - read-write - - LEC - read-write - - NoError - No Error - 0 - - - Stuff - Stuff Error - 1 - - - Form - Form Error - 2 - - - Ack - Acknowledgment Error - 3 - - - BitRecessive - Bit recessive Error - 4 - - - BitDominant - Bit dominant Error - 5 - - - Crc - CRC Error - 6 - - - Custom - Set by software - 7 - - - - - BOFF - BOFF - 2 - 1 - read-only - - - EPVF - EPVF - 1 - 1 - read-only - - - EWGF - EWGF - 0 - 1 - read-only - - - - - BTR - BTR - bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - SILM - SILM - 31 - 1 - - SILM - read-write - - Normal - Normal operation - 0 - - - Silent - Silent Mode - 1 - - - - - LBKM - LBKM - 30 - 1 - - LBKM - read-write - - Disabled - Loop Back Mode disabled - 0 - - - Enabled - Loop Back Mode enabled - 1 - - - - - SJW - SJW - 24 - 2 - - - TS2 - TS2 - 20 - 3 - - - TS1 - TS1 - 16 - 4 - - - BRP - BRP - 0 - 10 - - - - - 3 - 0x10 - 0-2 - TX%s - CAN Transmit cluster - 0x180 - - TIR - TI0R - TX mailbox identifier register - 0x0 - 0x20 - read-write - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - IDE - read-write - - Standard - Standard identifier - 0 - - - Extended - Extended identifier - 1 - - - - - RTR - RTR - 1 - 1 - - RTR - read-write - - Data - Data frame - 0 - - - Remote - Remote frame - 1 - - - - - TXRQ - TXRQ - 0 - 1 - - - - - TDTR - TDT0R - mailbox data length control and time stamp register - 0x4 - 0x20 - read-write - 0x00000000 - - - TIME - TIME - 16 - 16 - - - TGT - TGT - 8 - 1 - - - DLC - DLC - 0 - 4 - - - 0 - 8 - - - - - - - TDLR - TDL0R - mailbox data low register - 0x8 - 0x20 - read-write - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - TDHR - TDH0R - mailbox data high register - 0xC - 0x20 - read-write - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - - 2 - 0x10 - 0-1 - RX%s - CAN Receive cluster - 0x1B0 - - RIR - RI0R - receive FIFO mailbox identifier register - 0x0 - 0x20 - read-only - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - IDE - read - - Standard - Standard identifier - 0 - - - Extended - Extended identifier - 1 - - - - - RTR - RTR - 1 - 1 - - RTR - read - - Data - Data frame - 0 - - - Remote - Remote frame - 1 - - - - - - - RDTR - RDT0R - mailbox data high register - 0x4 - 0x20 - read-only - 0x00000000 - - - TIME - TIME - 16 - 16 - - - FMI - FMI - 8 - 8 - - - DLC - DLC - 0 - 4 - - - 0 - 8 - - - - - - - RDLR - RDL0R - mailbox data high register - 0x8 - 0x20 - read-only - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - RDHR - RDH0R - receive FIFO mailbox data high register - 0xC - 0x20 - read-only - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - - FMR - FMR - filter master register - 0x200 - 0x20 - read-write - 0x2A1C0E01 - - - CAN2SB - CAN2SB - 8 - 6 - - - FINIT - FINIT - 0 - 1 - - - - - FM1R - FM1R - filter mode register - 0x204 - 0x20 - read-write - 0x00000000 - - - FBM0 - Filter mode - 0 - 1 - - - FBM1 - Filter mode - 1 - 1 - - - FBM2 - Filter mode - 2 - 1 - - - FBM3 - Filter mode - 3 - 1 - - - FBM4 - Filter mode - 4 - 1 - - - FBM5 - Filter mode - 5 - 1 - - - FBM6 - Filter mode - 6 - 1 - - - FBM7 - Filter mode - 7 - 1 - - - FBM8 - Filter mode - 8 - 1 - - - FBM9 - Filter mode - 9 - 1 - - - FBM10 - Filter mode - 10 - 1 - - - FBM11 - Filter mode - 11 - 1 - - - FBM12 - Filter mode - 12 - 1 - - - FBM13 - Filter mode - 13 - 1 - - - FBM14 - Filter mode - 14 - 1 - - - FBM15 - Filter mode - 15 - 1 - - - FBM16 - Filter mode - 16 - 1 - - - FBM17 - Filter mode - 17 - 1 - - - FBM18 - Filter mode - 18 - 1 - - - FBM19 - Filter mode - 19 - 1 - - - FBM20 - Filter mode - 20 - 1 - - - FBM21 - Filter mode - 21 - 1 - - - FBM22 - Filter mode - 22 - 1 - - - FBM23 - Filter mode - 23 - 1 - - - FBM24 - Filter mode - 24 - 1 - - - FBM25 - Filter mode - 25 - 1 - - - FBM26 - Filter mode - 26 - 1 - - - FBM27 - Filter mode - 27 - 1 - - - - - FS1R - FS1R - filter scale register - 0x20C - 0x20 - read-write - 0x00000000 - - - FSC0 - Filter scale configuration - 0 - 1 - - - FSC1 - Filter scale configuration - 1 - 1 - - - FSC2 - Filter scale configuration - 2 - 1 - - - FSC3 - Filter scale configuration - 3 - 1 - - - FSC4 - Filter scale configuration - 4 - 1 - - - FSC5 - Filter scale configuration - 5 - 1 - - - FSC6 - Filter scale configuration - 6 - 1 - - - FSC7 - Filter scale configuration - 7 - 1 - - - FSC8 - Filter scale configuration - 8 - 1 - - - FSC9 - Filter scale configuration - 9 - 1 - - - FSC10 - Filter scale configuration - 10 - 1 - - - FSC11 - Filter scale configuration - 11 - 1 - - - FSC12 - Filter scale configuration - 12 - 1 - - - FSC13 - Filter scale configuration - 13 - 1 - - - FSC14 - Filter scale configuration - 14 - 1 - - - FSC15 - Filter scale configuration - 15 - 1 - - - FSC16 - Filter scale configuration - 16 - 1 - - - FSC17 - Filter scale configuration - 17 - 1 - - - FSC18 - Filter scale configuration - 18 - 1 - - - FSC19 - Filter scale configuration - 19 - 1 - - - FSC20 - Filter scale configuration - 20 - 1 - - - FSC21 - Filter scale configuration - 21 - 1 - - - FSC22 - Filter scale configuration - 22 - 1 - - - FSC23 - Filter scale configuration - 23 - 1 - - - FSC24 - Filter scale configuration - 24 - 1 - - - FSC25 - Filter scale configuration - 25 - 1 - - - FSC26 - Filter scale configuration - 26 - 1 - - - FSC27 - Filter scale configuration - 27 - 1 - - - - - FFA1R - FFA1R - filter FIFO assignment register - 0x214 - 0x20 - read-write - 0x00000000 - - - FFA0 - Filter FIFO assignment for filter 0 - 0 - 1 - - - FFA1 - Filter FIFO assignment for filter 1 - 1 - 1 - - - FFA2 - Filter FIFO assignment for filter 2 - 2 - 1 - - - FFA3 - Filter FIFO assignment for filter 3 - 3 - 1 - - - FFA4 - Filter FIFO assignment for filter 4 - 4 - 1 - - - FFA5 - Filter FIFO assignment for filter 5 - 5 - 1 - - - FFA6 - Filter FIFO assignment for filter 6 - 6 - 1 - - - FFA7 - Filter FIFO assignment for filter 7 - 7 - 1 - - - FFA8 - Filter FIFO assignment for filter 8 - 8 - 1 - - - FFA9 - Filter FIFO assignment for filter 9 - 9 - 1 - - - FFA10 - Filter FIFO assignment for filter 10 - 10 - 1 - - - FFA11 - Filter FIFO assignment for filter 11 - 11 - 1 - - - FFA12 - Filter FIFO assignment for filter 12 - 12 - 1 - - - FFA13 - Filter FIFO assignment for filter 13 - 13 - 1 - - - FFA14 - Filter FIFO assignment for filter 14 - 14 - 1 - - - FFA15 - Filter FIFO assignment for filter 15 - 15 - 1 - - - FFA16 - Filter FIFO assignment for filter 16 - 16 - 1 - - - FFA17 - Filter FIFO assignment for filter 17 - 17 - 1 - - - FFA18 - Filter FIFO assignment for filter 18 - 18 - 1 - - - FFA19 - Filter FIFO assignment for filter 19 - 19 - 1 - - - FFA20 - Filter FIFO assignment for filter 20 - 20 - 1 - - - FFA21 - Filter FIFO assignment for filter 21 - 21 - 1 - - - FFA22 - Filter FIFO assignment for filter 22 - 22 - 1 - - - FFA23 - Filter FIFO assignment for filter 23 - 23 - 1 - - - FFA24 - Filter FIFO assignment for filter 24 - 24 - 1 - - - FFA25 - Filter FIFO assignment for filter 25 - 25 - 1 - - - FFA26 - Filter FIFO assignment for filter 26 - 26 - 1 - - - FFA27 - Filter FIFO assignment for filter 27 - 27 - 1 - - - - - FA1R - FA1R - filter activation register - 0x21C - 0x20 - read-write - 0x00000000 - - - FACT0 - Filter active - 0 - 1 - - - FACT1 - Filter active - 1 - 1 - - - FACT2 - Filter active - 2 - 1 - - - FACT3 - Filter active - 3 - 1 - - - FACT4 - Filter active - 4 - 1 - - - FACT5 - Filter active - 5 - 1 - - - FACT6 - Filter active - 6 - 1 - - - FACT7 - Filter active - 7 - 1 - - - FACT8 - Filter active - 8 - 1 - - - FACT9 - Filter active - 9 - 1 - - - FACT10 - Filter active - 10 - 1 - - - FACT11 - Filter active - 11 - 1 - - - FACT12 - Filter active - 12 - 1 - - - FACT13 - Filter active - 13 - 1 - - - FACT14 - Filter active - 14 - 1 - - - FACT15 - Filter active - 15 - 1 - - - FACT16 - Filter active - 16 - 1 - - - FACT17 - Filter active - 17 - 1 - - - FACT18 - Filter active - 18 - 1 - - - FACT19 - Filter active - 19 - 1 - - - FACT20 - Filter active - 20 - 1 - - - FACT21 - Filter active - 21 - 1 - - - FACT22 - Filter active - 22 - 1 - - - FACT23 - Filter active - 23 - 1 - - - FACT24 - Filter active - 24 - 1 - - - FACT25 - Filter active - 25 - 1 - - - FACT26 - Filter active - 26 - 1 - - - FACT27 - Filter active - 27 - 1 - - - - - 28 - 0x8 - 0-27 - FB%s - CAN Filter Bank cluster - 0x240 - - FR1 - F0R1 - Filter bank 0 register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - FB - Filter bits - 0 - 32 - - - - - FR2 - F0R2 - Filter bank 0 register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - FB - Filter bits - 0 - 32 - - - - - - - - CAN2 - 0x40006800 - - CAN2_TX - CAN2 TX interrupts - 63 - - - CAN2_RX0 - CAN2 RX0 interrupts - 64 - - - CAN2_RX1 - CAN2 RX1 interrupts - 65 - - - CAN2_SCE - CAN2 SCE interrupt - 66 - - - - FLASH - FLASH - FLASH - 0x40023C00 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - ACR - ACR - Flash access control register - 0x0 - 0x20 - read-write - 0x00000000 - - - LATENCY - Latency - 0 - 4 - - LATENCY - read-write - - WS0 - 0 wait states - 0 - - - WS1 - 1 wait states - 1 - - - WS2 - 2 wait states - 2 - - - WS3 - 3 wait states - 3 - - - WS4 - 4 wait states - 4 - - - WS5 - 5 wait states - 5 - - - WS6 - 6 wait states - 6 - - - WS7 - 7 wait states - 7 - - - WS8 - 8 wait states - 8 - - - WS9 - 9 wait states - 9 - - - WS10 - 10 wait states - 10 - - - WS11 - 11 wait states - 11 - - - WS12 - 12 wait states - 12 - - - WS13 - 13 wait states - 13 - - - WS14 - 14 wait states - 14 - - - WS15 - 15 wait states - 15 - - - - - PRFTEN - Prefetch enable - 8 - 1 - - PRFTEN - read-write - - Disabled - Prefetch is disabled - 0 - - - Enabled - Prefetch is enabled - 1 - - - - - ARTEN - ART Accelerator Enable - 9 - 1 - - ARTEN - read-write - - Disabled - ART Accelerator is disabled - 0 - - - Enabled - ART Accelerator is enabled - 1 - - - - - ARTRST - ART Accelerator reset - 11 - 1 - - ARTRST - read-write - - NotReset - Accelerator is not reset - 0 - - - Reset - Accelerator is reset - 1 - - - - - - - KEYR - KEYR - Flash key register - 0x4 - 0x20 - write-only - 0x00000000 - - - KEY - FPEC key - 0 - 32 - - - 0 - 4294967295 - - - - - - - OPTKEYR - OPTKEYR - Flash option key register - 0x8 - 0x20 - write-only - 0x00000000 - - - OPTKEYR - Option byte key - 0 - 32 - - - 0 - 4294967295 - - - - - - - SR - SR - Status register - 0xC - 0x20 - 0x00000000 - - - EOP - End of operation - 0 - 1 - read-write - oneToClear - - EOPW - write - - Clear - Clear error flag - 1 - - - - - OPERR - Operation error - 1 - 1 - read-write - oneToClear - - OPERRW - write - - Clear - Clear error flag - 1 - - - - - WRPERR - Write protection error - 4 - 1 - read-write - oneToClear - - WRPERRW - write - - Clear - Clear error flag - 1 - - - - - PGAERR - Programming alignment error - 5 - 1 - read-write - oneToClear - - PGAERRW - write - - Clear - Clear error flag - 1 - - - - - PGPERR - Programming parallelism error - 6 - 1 - read-write - oneToClear - - PGPERRW - write - - Clear - Clear error flag - 1 - - - - - ERSERR - Programming sequence error - 7 - 1 - read-write - oneToClear - - ERSERRW - write - - Clear - Clear error flag - 1 - - - - - BSY - Busy - 16 - 1 - read-only - - BSYR - read - - NotBusy - no Flash memory operation ongoing - 0 - - - Busy - Flash memory operation ongoing - 1 - - - - - - - CR - CR - Control register - 0x10 - 0x20 - read-write - 0x80000000 - - - PG - Programming - 0 - 1 - - PG - read-write - - Program - Flash programming activated - 1 - - - - - SER - Sector Erase - 1 - 1 - - SER - read-write - - SectorErase - Erase activated for selected sector - 1 - - - - - MER - Mass Erase of sectors 0 to 11 - 2 - 1 - - MER - read-write - - MassErase - Erase activated for all user sectors - 1 - - - - - SNB - Sector number - 3 - 4 - - - 0 - 11 - - - - - PSIZE - Program size - 8 - 2 - - PSIZE - read-write - - PSIZE8 - Program x8 - 0 - - - PSIZE16 - Program x16 - 1 - - - PSIZE32 - Program x32 - 2 - - - PSIZE64 - Program x64 - 3 - - - - - STRT - Start - 16 - 1 - - STRT - read-write - - Start - Trigger an erase operation - 1 - - - - - EOPIE - End of operation interrupt enable - 24 - 1 - - EOPIE - read-write - - Disabled - End of operation interrupt disabled - 0 - - - Enabled - End of operation interrupt enabled - 1 - - - - - ERRIE - Error interrupt enable - 25 - 1 - - ERRIE - read-write - - Disabled - Error interrupt generation disabled - 0 - - - Enabled - Error interrupt generation enabled - 1 - - - - - LOCK - Lock - 31 - 1 - - LOCK - read-write - - Unlocked - FLASH_CR register is unlocked - 0 - - - Locked - FLASH_CR register is locked - 1 - - - - - - - OPTCR - OPTCR - Flash option control register - 0x14 - 0x20 - read-write - 0x0FFFAAED - - - OPTLOCK - Option lock - 0 - 1 - - - OPTSTRT - Option start - 1 - 1 - - - BOR_LEV - BOR reset Level - 2 - 2 - - - WWDG_SW - User option bytes - 4 - 1 - - - IWDG_SW - User option bytes - 5 - 1 - - - nRST_STOP - User option bytes - 6 - 1 - - - nRST_STDBY - User option bytes - 7 - 1 - - - RDP - Read protect - 8 - 8 - - - nWRP - Not write protect - 16 - 8 - - - IWDG_STDBY - Independent watchdog counter freeze in standby mode - 30 - 1 - - - IWDG_STOP - Independent watchdog counter freeze in Stop mode - 31 - 1 - - - - - OPTCR1 - OPTCR1 - Flash option control register 1 - 0x18 - 0x20 - read-write - 0x0FFF0000 - - - BOOT_ADD0 - Boot base address when Boot pin =0 - 0 - 16 - - - BOOT_ADD1 - Boot base address when Boot pin =1 - 16 - 16 - - - - - - - EXTI - External interrupt/event controller - EXTI - 0x40013C00 - - 0x0 - 0x400 - registers - - - PVD - PVD through EXTI line detection INTERRUPT - 1 - - - TAMP_STAMP - Tamper and TimeStamp interrupts through the - EXTI line - 2 - - - EXTI0 - EXTI Line0 interrupt - 6 - - - EXTI1 - EXTI Line1 interrupt - 7 - - - EXTI2 - EXTI Line2 interrupt - 8 - - - EXTI3 - EXTI Line3 interrupt - 9 - - - EXTI4 - EXTI Line4 interrupt - 10 - - - EXTI9_5 - EXTI Line[9:5] interrupts - 23 - - - EXTI15_10 - EXTI Line[15:10] interrupts - 40 - - - - IMR - IMR - Interrupt mask register (EXTI_IMR) - 0x0 - 0x20 - read-write - 0x00000000 - - - MR0 - Interrupt Mask on line 0 - 0 - 1 - - MR0 - read-write - - Masked - Interrupt request line is masked - 0 - - - Unmasked - Interrupt request line is unmasked - 1 - - - - - MR1 - Interrupt Mask on line 1 - 1 - 1 - - - - MR2 - Interrupt Mask on line 2 - 2 - 1 - - - - MR3 - Interrupt Mask on line 3 - 3 - 1 - - - - MR4 - Interrupt Mask on line 4 - 4 - 1 - - - - MR5 - Interrupt Mask on line 5 - 5 - 1 - - - - MR6 - Interrupt Mask on line 6 - 6 - 1 - - - - MR7 - Interrupt Mask on line 7 - 7 - 1 - - - - MR8 - Interrupt Mask on line 8 - 8 - 1 - - - - MR9 - Interrupt Mask on line 9 - 9 - 1 - - - - MR10 - Interrupt Mask on line 10 - 10 - 1 - - - - MR11 - Interrupt Mask on line 11 - 11 - 1 - - - - MR12 - Interrupt Mask on line 12 - 12 - 1 - - - - MR13 - Interrupt Mask on line 13 - 13 - 1 - - - - MR14 - Interrupt Mask on line 14 - 14 - 1 - - - - MR15 - Interrupt Mask on line 15 - 15 - 1 - - - - MR16 - Interrupt Mask on line 16 - 16 - 1 - - - - MR17 - Interrupt Mask on line 17 - 17 - 1 - - - - MR18 - Interrupt Mask on line 18 - 18 - 1 - - - - MR19 - Interrupt Mask on line 19 - 19 - 1 - - - - MR20 - Interrupt Mask on line 20 - 20 - 1 - - - - MR21 - Interrupt Mask on line 21 - 21 - 1 - - - - MR22 - Interrupt Mask on line 22 - 22 - 1 - - - - - - EMR - EMR - Event mask register (EXTI_EMR) - 0x4 - 0x20 - read-write - 0x00000000 - - - MR0 - Event Mask on line 0 - 0 - 1 - - MR0 - read-write - - Masked - Interrupt request line is masked - 0 - - - Unmasked - Interrupt request line is unmasked - 1 - - - - - MR1 - Event Mask on line 1 - 1 - 1 - - - - MR2 - Event Mask on line 2 - 2 - 1 - - - - MR3 - Event Mask on line 3 - 3 - 1 - - - - MR4 - Event Mask on line 4 - 4 - 1 - - - - MR5 - Event Mask on line 5 - 5 - 1 - - - - MR6 - Event Mask on line 6 - 6 - 1 - - - - MR7 - Event Mask on line 7 - 7 - 1 - - - - MR8 - Event Mask on line 8 - 8 - 1 - - - - MR9 - Event Mask on line 9 - 9 - 1 - - - - MR10 - Event Mask on line 10 - 10 - 1 - - - - MR11 - Event Mask on line 11 - 11 - 1 - - - - MR12 - Event Mask on line 12 - 12 - 1 - - - - MR13 - Event Mask on line 13 - 13 - 1 - - - - MR14 - Event Mask on line 14 - 14 - 1 - - - - MR15 - Event Mask on line 15 - 15 - 1 - - - - MR16 - Event Mask on line 16 - 16 - 1 - - - - MR17 - Event Mask on line 17 - 17 - 1 - - - - MR18 - Event Mask on line 18 - 18 - 1 - - - - MR19 - Event Mask on line 19 - 19 - 1 - - - - MR20 - Event Mask on line 20 - 20 - 1 - - - - MR21 - Event Mask on line 21 - 21 - 1 - - - - MR22 - Event Mask on line 22 - 22 - 1 - - - - - - RTSR - RTSR - Rising Trigger selection register (EXTI_RTSR) - 0x8 - 0x20 - read-write - 0x00000000 - - - TR0 - Rising trigger event configuration of line 0 - 0 - 1 - - TR0 - read-write - - Disabled - Rising edge trigger is disabled - 0 - - - Enabled - Rising edge trigger is enabled - 1 - - - - - TR1 - Rising trigger event configuration of line 1 - 1 - 1 - - - - TR2 - Rising trigger event configuration of line 2 - 2 - 1 - - - - TR3 - Rising trigger event configuration of line 3 - 3 - 1 - - - - TR4 - Rising trigger event configuration of line 4 - 4 - 1 - - - - TR5 - Rising trigger event configuration of line 5 - 5 - 1 - - - - TR6 - Rising trigger event configuration of line 6 - 6 - 1 - - - - TR7 - Rising trigger event configuration of line 7 - 7 - 1 - - - - TR8 - Rising trigger event configuration of line 8 - 8 - 1 - - - - TR9 - Rising trigger event configuration of line 9 - 9 - 1 - - - - TR10 - Rising trigger event configuration of line 10 - 10 - 1 - - - - TR11 - Rising trigger event configuration of line 11 - 11 - 1 - - - - TR12 - Rising trigger event configuration of line 12 - 12 - 1 - - - - TR13 - Rising trigger event configuration of line 13 - 13 - 1 - - - - TR14 - Rising trigger event configuration of line 14 - 14 - 1 - - - - TR15 - Rising trigger event configuration of line 15 - 15 - 1 - - - - TR16 - Rising trigger event configuration of line 16 - 16 - 1 - - - - TR17 - Rising trigger event configuration of line 17 - 17 - 1 - - - - TR18 - Rising trigger event configuration of line 18 - 18 - 1 - - - - TR19 - Rising trigger event configuration of line 19 - 19 - 1 - - - - TR20 - Rising trigger event configuration of line 20 - 20 - 1 - - - - TR21 - Rising trigger event configuration of line 21 - 21 - 1 - - - - TR22 - Rising trigger event configuration of line 22 - 22 - 1 - - - - - - FTSR - FTSR - Falling Trigger selection register (EXTI_FTSR) - 0xC - 0x20 - read-write - 0x00000000 - - - TR0 - Falling trigger event configuration of line 0 - 0 - 1 - - TR0 - read-write - - Disabled - Falling edge trigger is disabled - 0 - - - Enabled - Falling edge trigger is enabled - 1 - - - - - TR1 - Falling trigger event configuration of line 1 - 1 - 1 - - - - TR2 - Falling trigger event configuration of line 2 - 2 - 1 - - - - TR3 - Falling trigger event configuration of line 3 - 3 - 1 - - - - TR4 - Falling trigger event configuration of line 4 - 4 - 1 - - - - TR5 - Falling trigger event configuration of line 5 - 5 - 1 - - - - TR6 - Falling trigger event configuration of line 6 - 6 - 1 - - - - TR7 - Falling trigger event configuration of line 7 - 7 - 1 - - - - TR8 - Falling trigger event configuration of line 8 - 8 - 1 - - - - TR9 - Falling trigger event configuration of line 9 - 9 - 1 - - - - TR10 - Falling trigger event configuration of line 10 - 10 - 1 - - - - TR11 - Falling trigger event configuration of line 11 - 11 - 1 - - - - TR12 - Falling trigger event configuration of line 12 - 12 - 1 - - - - TR13 - Falling trigger event configuration of line 13 - 13 - 1 - - - - TR14 - Falling trigger event configuration of line 14 - 14 - 1 - - - - TR15 - Falling trigger event configuration of line 15 - 15 - 1 - - - - TR16 - Falling trigger event configuration of line 16 - 16 - 1 - - - - TR17 - Falling trigger event configuration of line 17 - 17 - 1 - - - - TR18 - Falling trigger event configuration of line 18 - 18 - 1 - - - - TR19 - Falling trigger event configuration of line 19 - 19 - 1 - - - - TR20 - Falling trigger event configuration of line 20 - 20 - 1 - - - - TR21 - Falling trigger event configuration of line 21 - 21 - 1 - - - - TR22 - Falling trigger event configuration of line 22 - 22 - 1 - - - - - - SWIER - SWIER - Software interrupt event register (EXTI_SWIER) - 0x10 - 0x20 - read-write - 0x00000000 - - - SWIER0 - Software Interrupt on line 0 - 0 - 1 - - SWIER0W - write - - Pend - Generates an interrupt request - 1 - - - - - SWIER1 - Software Interrupt on line 1 - 1 - 1 - - - - SWIER2 - Software Interrupt on line 2 - 2 - 1 - - - - SWIER3 - Software Interrupt on line 3 - 3 - 1 - - - - SWIER4 - Software Interrupt on line 4 - 4 - 1 - - - - SWIER5 - Software Interrupt on line 5 - 5 - 1 - - - - SWIER6 - Software Interrupt on line 6 - 6 - 1 - - - - SWIER7 - Software Interrupt on line 7 - 7 - 1 - - - - SWIER8 - Software Interrupt on line 8 - 8 - 1 - - - - SWIER9 - Software Interrupt on line 9 - 9 - 1 - - - - SWIER10 - Software Interrupt on line 10 - 10 - 1 - - - - SWIER11 - Software Interrupt on line 11 - 11 - 1 - - - - SWIER12 - Software Interrupt on line 12 - 12 - 1 - - - - SWIER13 - Software Interrupt on line 13 - 13 - 1 - - - - SWIER14 - Software Interrupt on line 14 - 14 - 1 - - - - SWIER15 - Software Interrupt on line 15 - 15 - 1 - - - - SWIER16 - Software Interrupt on line 16 - 16 - 1 - - - - SWIER17 - Software Interrupt on line 17 - 17 - 1 - - - - SWIER18 - Software Interrupt on line 18 - 18 - 1 - - - - SWIER19 - Software Interrupt on line 19 - 19 - 1 - - - - SWIER20 - Software Interrupt on line 20 - 20 - 1 - - - - SWIER21 - Software Interrupt on line 21 - 21 - 1 - - - - SWIER22 - Software Interrupt on line 22 - 22 - 1 - - - - - - PR - PR - Pending register (EXTI_PR) - 0x14 - 0x20 - read-write - 0x00000000 - - - PR0 - Pending bit 0 - 0 - 1 - oneToClear - - PR0R - read - - NotPending - No trigger request occurred - 0 - - - Pending - Selected trigger request occurred - 1 - - - - PR0W - write - - Clear - Clears pending bit - 1 - - - - - PR1 - Pending bit 1 - 1 - 1 - oneToClear - - read - - - write - - - - PR2 - Pending bit 2 - 2 - 1 - oneToClear - - read - - - write - - - - PR3 - Pending bit 3 - 3 - 1 - oneToClear - - read - - - write - - - - PR4 - Pending bit 4 - 4 - 1 - oneToClear - - read - - - write - - - - PR5 - Pending bit 5 - 5 - 1 - oneToClear - - read - - - write - - - - PR6 - Pending bit 6 - 6 - 1 - oneToClear - - read - - - write - - - - PR7 - Pending bit 7 - 7 - 1 - oneToClear - - read - - - write - - - - PR8 - Pending bit 8 - 8 - 1 - oneToClear - - read - - - write - - - - PR9 - Pending bit 9 - 9 - 1 - oneToClear - - read - - - write - - - - PR10 - Pending bit 10 - 10 - 1 - oneToClear - - read - - - write - - - - PR11 - Pending bit 11 - 11 - 1 - oneToClear - - read - - - write - - - - PR12 - Pending bit 12 - 12 - 1 - oneToClear - - read - - - write - - - - PR13 - Pending bit 13 - 13 - 1 - oneToClear - - read - - - write - - - - PR14 - Pending bit 14 - 14 - 1 - oneToClear - - read - - - write - - - - PR15 - Pending bit 15 - 15 - 1 - oneToClear - - read - - - write - - - - PR16 - Pending bit 16 - 16 - 1 - oneToClear - - read - - - write - - - - PR17 - Pending bit 17 - 17 - 1 - oneToClear - - read - - - write - - - - PR18 - Pending bit 18 - 18 - 1 - oneToClear - - read - - - write - - - - PR19 - Pending bit 19 - 19 - 1 - oneToClear - - read - - - write - - - - PR20 - Pending bit 20 - 20 - 1 - oneToClear - - read - - - write - - - - PR21 - Pending bit 21 - 21 - 1 - oneToClear - - read - - - write - - - - PR22 - Pending bit 22 - 22 - 1 - oneToClear - - read - - - write - - - - - - - - LTDC - LCD-TFT Controller - LTDC - 0x40016800 - - 0x0 - 0x400 - registers - - - LTDC - LTDC global interrupt - 88 - - - LTDC_ER - LTDC global error interrupt - 89 - - - - SSCR - SSCR - Synchronization Size Configuration Register - 0x8 - 0x20 - read-write - 0x00000000 - - - HSW - Horizontal Synchronization Width (in units of pixel clock period) - 16 - 12 - - - 0 - 4095 - - - - - VSH - Vertical Synchronization Height (in units of horizontal scan line) - 0 - 11 - - - 0 - 2047 - - - - - - - BPCR - BPCR - Back Porch Configuration Register - 0xC - 0x20 - read-write - 0x00000000 - - - AHBP - Accumulated Horizontal back porch (in units of pixel clock period) - 16 - 12 - - - 0 - 4095 - - - - - AVBP - Accumulated Vertical back porch (in units of horizontal scan line) - 0 - 11 - - - 0 - 2047 - - - - - - - AWCR - AWCR - Active Width Configuration Register - 0x10 - 0x20 - read-write - 0x00000000 - - - AAW - Accumulated Active Width (in units of pixel clock period) - 16 - 12 - - - 0 - 4095 - - - - - AAH - Accumulated Active Height (in units of horizontal scan line) - 0 - 11 - - - 0 - 2047 - - - - - - - TWCR - TWCR - Total Width Configuration Register - 0x14 - 0x20 - read-write - 0x00000000 - - - TOTALW - Total Width (in units of pixel clock period) - 16 - 12 - - - 0 - 4095 - - - - - TOTALH - Total Height (in units of horizontal scan line) - 0 - 11 - - - 0 - 2047 - - - - - - - GCR - GCR - Global Control Register - 0x18 - 0x20 - 0x00002220 - - - HSPOL - Horizontal Synchronization Polarity - 31 - 1 - read-write - - HSPOL - read-write - - ActiveLow - Horizontal synchronization polarity is active low - 0 - - - ActiveHigh - Horizontal synchronization polarity is active high - 1 - - - - - VSPOL - Vertical Synchronization Polarity - 30 - 1 - read-write - - VSPOL - read-write - - ActiveLow - Vertical synchronization polarity is active low - 0 - - - ActiveHigh - Vertical synchronization polarity is active high - 1 - - - - - DEPOL - Data Enable Polarity - 29 - 1 - read-write - - DEPOL - read-write - - ActiveLow - Data enable polarity is active low - 0 - - - ActiveHigh - Data enable polarity is active high - 1 - - - - - PCPOL - Pixel Clock Polarity - 28 - 1 - read-write - - PCPOL - read-write - - RisingEdge - Pixel clock on rising edge - 0 - - - FallingEdge - Pixel clock on falling edge - 1 - - - - - DEN - Dither Enable - 16 - 1 - read-write - - DEN - read-write - - Disabled - Dither disabled - 0 - - - Enabled - Dither enabled - 1 - - - - - DRW - Dither Red Width - 12 - 3 - read-only - - - DGW - Dither Green Width - 8 - 3 - read-only - - - DBW - Dither Blue Width - 4 - 3 - read-only - - - LTDCEN - LCD-TFT controller enable bit - 0 - 1 - read-write - - LTDCEN - read-write - - Disabled - LCD-TFT controller disabled - 0 - - - Enabled - LCD-TFT controller enabled - 1 - - - - - - - SRCR - SRCR - Shadow Reload Configuration Register - 0x24 - 0x20 - read-write - 0x00000000 - - - VBR - Vertical Blanking Reload - 1 - 1 - - VBR - read-write - - NoEffect - This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - 0 - - - Reload - The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). - 1 - - - - - IMR - Immediate Reload - 0 - 1 - - IMR - read-write - - NoEffect - This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - 0 - - - Reload - The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload - 1 - - - - - - - BCCR - BCCR - Background Color Configuration Register - 0x2C - 0x20 - read-write - 0x00000000 - - - BCBLUE - Background color blue value - 0 - 8 - - - 0 - 255 - - - - - BCGREEN - Background color green value - 8 - 8 - - - 0 - 255 - - - - - BCRED - Background color red value - 16 - 8 - - - 0 - 255 - - - - - - - IER - IER - Interrupt Enable Register - 0x34 - 0x20 - read-write - 0x00000000 - - - RRIE - Register Reload interrupt enable - 3 - 1 - - RRIE - read-write - - Disabled - Register reload interrupt disabled - 0 - - - Enabled - Register reload interrupt enabled - 1 - - - - - TERRIE - Transfer Error Interrupt Enable - 2 - 1 - - TERRIE - read-write - - Disabled - Transfer error interrupt disabled - 0 - - - Enabled - Transfer error interrupt enabled - 1 - - - - - FUIE - FIFO Underrun Interrupt Enable - 1 - 1 - - FUIE - read-write - - Disabled - FIFO underrun interrupt disabled - 0 - - - Enabled - FIFO underrun interrupt enabled - 1 - - - - - LIE - Line Interrupt Enable - 0 - 1 - - LIE - read-write - - Disabled - Line interrupt disabled - 0 - - - Enabled - Line interrupt enabled - 1 - - - - - - - ISR - ISR - Interrupt Status Register - 0x38 - 0x20 - read-only - 0x00000000 - - - RRIF - Register Reload Interrupt Flag - 3 - 1 - - RRIF - read - - NoReload - No register reload - 0 - - - Reload - Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) - 1 - - - - - TERRIF - Transfer Error interrupt flag - 2 - 1 - - TERRIF - read - - NoError - No transfer error - 0 - - - Error - Transfer error interrupt generated when a bus error occurs - 1 - - - - - FUIF - FIFO Underrun Interrupt flag - 1 - 1 - - FUIF - read - - NoUnderrun - No FIFO underrun - 0 - - - Underrun - FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO - 1 - - - - - LIF - Line Interrupt flag - 0 - 1 - - LIF - read - - NotReached - Programmed line not reached - 0 - - - Reached - Line interrupt generated when a programmed line is reached - 1 - - - - - - - ICR - ICR - Interrupt Clear Register - 0x3C - 0x20 - write-only - 0x00000000 - - - CRRIF - Clears Register Reload Interrupt Flag - 3 - 1 - oneToClear - - CRRIFW - write - - Clear - Clears the RRIF flag in the ISR register - 1 - - - - - CTERRIF - Clears the Transfer Error Interrupt Flag - 2 - 1 - oneToClear - - CTERRIFW - write - - Clear - Clears the TERRIF flag in the ISR register - 1 - - - - - CFUIF - Clears the FIFO Underrun Interrupt flag - 1 - 1 - oneToClear - - CFUIFW - write - - Clear - Clears the FUIF flag in the ISR register - 1 - - - - - CLIF - Clears the Line Interrupt Flag - 0 - 1 - oneToClear - - CLIFW - write - - Clear - Clears the LIF flag in the ISR register - 1 - - - - - - - LIPCR - LIPCR - Line Interrupt Position Configuration Register - 0x40 - 0x20 - read-write - 0x00000000 - - - LIPOS - Line Interrupt Position - 0 - 11 - - - 0 - 2047 - - - - - - - CPSR - CPSR - Current Position Status Register - 0x44 - 0x20 - read-only - 0x00000000 - - - CXPOS - Current X Position - 16 - 16 - - - CYPOS - Current Y Position - 0 - 16 - - - - - CDSR - CDSR - Current Display Status Register - 0x48 - 0x20 - read-only - 0x0000000F - - - HSYNCS - Horizontal Synchronization display Status - 3 - 1 - - HSYNCS - read - - NotActive - Currently not in HSYNC phase - 0 - - - Active - Currently in HSYNC phase - 1 - - - - - VSYNCS - Vertical Synchronization display Status - 2 - 1 - - VSYNCS - read - - NotActive - Currently not in VSYNC phase - 0 - - - Active - Currently in VSYNC phase - 1 - - - - - HDES - Horizontal Data Enable display Status - 1 - 1 - - HDES - read - - NotActive - Currently not in horizontal Data Enable phase - 0 - - - Active - Currently in horizontal Data Enable phase - 1 - - - - - VDES - Vertical Data Enable display Status - 0 - 1 - - VDES - read - - NotActive - Currently not in vertical Data Enable phase - 0 - - - Active - Currently in vertical Data Enable phase - 1 - - - - - - - 2 - 0x80 - 1-2 - LAYER%s - Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR - 0x84 - - CR - L1CR - Layerx Control Register - 0x0 - 0x20 - read-write - 0x00000000 - - - CLUTEN - Color Look-Up Table Enable - 4 - 1 - - CLUTEN - read-write - - Disabled - Color look-up table disabled - 0 - - - Enabled - Color look-up table enabled - 1 - - - - - COLKEN - Color Keying Enable - 1 - 1 - - COLKEN - read-write - - Disabled - Color keying disabled - 0 - - - Enabled - Color keying enabled - 1 - - - - - LEN - Layer Enable - 0 - 1 - - LEN - read-write - - Disabled - Layer disabled - 0 - - - Enabled - Layer enabled - 1 - - - - - - - WHPCR - L1WHPCR - Layerx Window Horizontal Position Configuration Register - 0x4 - 0x20 - read-write - 0x00000000 - - - WHSPPOS - Window Horizontal Stop Position - 16 - 12 - - - 0 - 4095 - - - - - WHSTPOS - Window Horizontal Start Position - 0 - 12 - - - 0 - 4095 - - - - - - - WVPCR - L1WVPCR - Layerx Window Vertical Position Configuration Register - 0x8 - 0x20 - read-write - 0x00000000 - - - WVSPPOS - Window Vertical Stop Position - 16 - 11 - - - 0 - 2047 - - - - - WVSTPOS - Window Vertical Start Position - 0 - 11 - - - 0 - 2047 - - - - - - - CKCR - L1CKCR - Layerx Color Keying Configuration Register - 0xC - 0x20 - read-write - 0x00000000 - - - CKRED - Color Key Red value - 16 - 8 - - - 0 - 255 - - - - - CKGREEN - Color Key Green value - 8 - 8 - - - 0 - 255 - - - - - CKBLUE - Color Key Blue value - 0 - 8 - - - 0 - 255 - - - - - - - PFCR - L1PFCR - Layerx Pixel Format Configuration Register - 0x10 - 0x20 - read-write - 0x00000000 - - - PF - Pixel Format - 0 - 3 - - PF - read-write - - ARGB8888 - ARGB8888 - 0 - - - RGB888 - RGB888 - 1 - - - RGB565 - RGB565 - 2 - - - ARGB1555 - ARGB1555 - 3 - - - ARGB4444 - ARGB4444 - 4 - - - L8 - L8 (8-bit luminance) - 5 - - - AL44 - AL44 (4-bit alpha, 4-bit luminance) - 6 - - - AL88 - AL88 (8-bit alpha, 8-bit luminance) - 7 - - - - - - - CACR - L1CACR - Layerx Constant Alpha Configuration Register - 0x14 - 0x20 - read-write - 0x00000000 - - - CONSTA - Constant Alpha - 0 - 8 - - - 0 - 255 - - - - - - - DCCR - L1DCCR - Layerx Default Color Configuration Register - 0x18 - 0x20 - read-write - 0x00000000 - - - DCALPHA - Default Color Alpha - 24 - 8 - - - 0 - 255 - - - - - DCRED - Default Color Red - 16 - 8 - - - 0 - 255 - - - - - DCGREEN - Default Color Green - 8 - 8 - - - 0 - 255 - - - - - DCBLUE - Default Color Blue - 0 - 8 - - - 0 - 255 - - - - - - - BFCR - L1BFCR - Layerx Blending Factors Configuration Register - 0x1C - 0x20 - read-write - 0x00000607 - - - BF1 - Blending Factor 1 - 8 - 3 - - BF1 - read-write - - Constant - BF1 = constant alpha - 4 - - - Pixel - BF1 = pixel alpha * constant alpha - 6 - - - - - BF2 - Blending Factor 2 - 0 - 3 - - BF2 - read-write - - Constant - BF2 = 1 - constant alpha - 5 - - - Pixel - BF2 = 1 - pixel alpha * constant alpha - 7 - - - - - - - CFBAR - L1CFBAR - Layerx Color Frame Buffer Address Register - 0x28 - 0x20 - read-write - 0x00000000 - - - CFBADD - Color Frame Buffer Start Address - 0 - 32 - - - 0 - 4294967295 - - - - - - - CFBLR - L1CFBLR - Layerx Color Frame Buffer Length Register - 0x2C - 0x20 - read-write - 0x00000000 - - - CFBP - Color Frame Buffer Pitch in bytes - 16 - 13 - - - 0 - 8191 - - - - - CFBLL - Color Frame Buffer Line Length - 0 - 13 - - - 0 - 8191 - - - - - - - CFBLNR - L1CFBLNR - Layerx ColorFrame Buffer Line Number Register - 0x30 - 0x20 - read-write - 0x00000000 - - - CFBLNBR - Frame Buffer Line Number - 0 - 11 - - - 0 - 2047 - - - - - - - CLUTWR - L1CLUTWR - Layerx CLUT Write Register - 0x40 - 0x20 - write-only - 0x00000000 - - - CLUTADD - CLUT Address - 24 - 8 - - - 0 - 255 - - - - - RED - Red value - 16 - 8 - - - 0 - 255 - - - - - GREEN - Green value - 8 - 8 - - - 0 - 255 - - - - - BLUE - Blue value - 0 - 8 - - - 0 - 255 - - - - - - - - - - SAI1 - Serial audio interface - SAI - 0x40015800 - - 0x0 - 0x400 - registers - - - SAI1 - SAI1 global interrupt - 87 - - - SAI2 - SAI2 global interrupt - 91 - - - - 2 - 0x20 - A,B - CH%s - Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - 0x4 - - CR1 - ACR1 - AConfiguration register 1 - 0x0 - 0x20 - read-write - 0x00000040 - - - MCKDIV - Master clock divider - 20 - 4 - - - NODIV - No divider - 19 - 1 - - NODIV - read-write - - MasterClock - MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - 0 - - - NoDiv - MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. - 1 - - - - - DMAEN - DMA enable - 17 - 1 - - DMAEN - read-write - - Disabled - DMA disabled - 0 - - - Enabled - DMA enabled - 1 - - - - - SAIEN - Audio block A enable - 16 - 1 - - SAIEN - read-write - - Disabled - SAI audio block disabled - 0 - - - Enabled - SAI audio block enabled - 1 - - - - - OUTDRIV - Output drive - 13 - 1 - - OUTDRIV - read-write - - OnStart - Audio block output driven when SAIEN is set - 0 - - - Immediately - Audio block output driven immediately after the setting of this bit - 1 - - - - - MONO - Mono mode - 12 - 1 - - MONO - read-write - - Stereo - Stereo mode - 0 - - - Mono - Mono mode - 1 - - - - - SYNCEN - Synchronization enable - 10 - 2 - - SYNCEN - read-write - - Asynchronous - audio sub-block in asynchronous mode - 0 - - - Internal - audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode - 1 - - - External - audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - 2 - - - - - CKSTR - Clock strobing edge - 9 - 1 - - CKSTR - read-write - - FallingEdge - Data strobing edge is falling edge of SCK - 0 - - - RisingEdge - Data strobing edge is rising edge of SCK - 1 - - - - - LSBFIRST - Least significant bit first - 8 - 1 - - LSBFIRST - read-write - - MsbFirst - Data are transferred with MSB first - 0 - - - LsbFirst - Data are transferred with LSB first - 1 - - - - - DS - Data size - 5 - 3 - - DS - read-write - - Bit8 - 8 bits - 2 - - - Bit10 - 10 bits - 3 - - - Bit16 - 16 bits - 4 - - - Bit20 - 20 bits - 5 - - - Bit24 - 24 bits - 6 - - - Bit32 - 32 bits - 7 - - - - - PRTCFG - Protocol configuration - 2 - 2 - - PRTCFG - read-write - - Free - Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - 0 - - - Spdif - SPDIF protocol - 1 - - - Ac97 - AC’97 protocol - 2 - - - - - MODE - Audio block mode - 0 - 2 - - MODE - read-write - - MasterTx - Master transmitter - 0 - - - MasterRx - Master receiver - 1 - - - SlaveTx - Slave transmitter - 2 - - - SlaveRx - Slave receiver - 3 - - - - - - - CR2 - ACR2 - AConfiguration register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - COMP - Companding mode - 14 - 2 - read-write - - COMP - read-write - - NoCompanding - No companding algorithm - 0 - - - MuLaw - ΞΌ-Law algorithm - 2 - - - ALaw - A-Law algorithm - 3 - - - - - CPL - Complement bit - 13 - 1 - read-write - - CPL - read-write - - OnesComplement - 1’s complement representation - 0 - - - TwosComplement - 2’s complement representation - 1 - - - - - MUTECNT - Mute counter - 7 - 6 - read-write - - - MUTEVAL - Mute value - 6 - 1 - read-write - - MUTEVAL - read-write - - SendZero - Bit value 0 is sent during the mute mode - 0 - - - SendLast - Last values are sent during the mute mode - 1 - - - - - MUTE - Mute - 5 - 1 - read-write - - MUTE - read-write - - Disabled - No mute mode - 0 - - - Enabled - Mute mode enabled - 1 - - - - - TRIS - Tristate management on data line - 4 - 1 - read-write - - - FFLUSH - FIFO flush - 3 - 1 - - FFLUSH - read-write - - NoFlush - No FIFO flush - 0 - - - Flush - FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared - 1 - - - - - FTH - FIFO threshold - 0 - 3 - read-write - - FTH - read-write - - Empty - FIFO empty - 0 - - - Quarter1 - 1⁄4 FIFO - 1 - - - Quarter2 - 1⁄2 FIFO - 2 - - - Quarter3 - 3⁄4 FIFO - 3 - - - Full - FIFO full - 4 - - - - - - - FRCR - AFRCR - AFRCR - 0x8 - 0x20 - read-write - 0x00000007 - - - FSOFF - Frame synchronization offset - 18 - 1 - read-write - - FSOFF - read-write - - OnFirst - FS is asserted on the first bit of the slot 0 - 0 - - - BeforeFirst - FS is asserted one bit before the first bit of the slot 0 - 1 - - - - - FSPOL - Frame synchronization polarity - 17 - 1 - read-write - - FSPOL - read-write - - FallingEdge - FS is active low (falling edge) - 0 - - - RisingEdge - FS is active high (rising edge) - 1 - - - - - FSDEF - Frame synchronization definition - 16 - 1 - read-write - - - FSALL - Frame synchronization active level length - 8 - 7 - read-write - - - FRL - Frame length - 0 - 8 - read-write - - - - - SLOTR - ASLOTR - ASlot register - 0xC - 0x20 - read-write - 0x00000000 - - - SLOTEN - Slot enable - 16 - 16 - - SLOTEN - read-write - - Inactive - Inactive slot - 0 - - - Active - Active slot - 1 - - - - - NBSLOT - Number of slots in an audio frame - 8 - 4 - - - SLOTSZ - Slot size - 6 - 2 - - SLOTSZ - read-write - - DataSize - The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) - 0 - - - Bit16 - 16-bit - 1 - - - Bit32 - 32-bit - 2 - - - - - FBOFF - First bit offset - 0 - 5 - - - - - IM - AIM - AInterrupt mask register2 - 0x10 - 0x20 - read-write - 0x00000000 - - - LFSDETIE - Late frame synchronization detection interrupt enable - 6 - 1 - - LFSDETIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is enabled - 1 - - - - - AFSDETIE - Anticipated frame synchronization detection interrupt enable - 5 - 1 - - AFSDETIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is enabled - 1 - - - - - CNRDYIE - Codec not ready interrupt enable - 4 - 1 - - CNRDYIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is enabled - 1 - - - - - FREQIE - FIFO request interrupt enable - 3 - 1 - - FREQIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is enabled - 1 - - - - - WCKCFGIE - Wrong clock configuration interrupt enable - 2 - 1 - - WCKCFGIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is enabled - 1 - - - - - MUTEDETIE - Mute detection interrupt enable - 1 - 1 - - MUTEDETIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is enabled - 1 - - - - - OVRUDRIE - Overrun/underrun interrupt enable - 0 - 1 - - OVRUDRIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is enabled - 1 - - - - - - - SR - ASR - AStatus register - 0x14 - 0x20 - read-only - 0x00000008 - - - FLVL - FIFO level threshold - 16 - 3 - - FLVLR - read - - Empty - FIFO empty - 0 - - - Quarter1 - FIFO <= 1⁄4 but not empty - 1 - - - Quarter2 - 1⁄4 < FIFO <= 1⁄2 - 2 - - - Quarter3 - 1⁄2 < FIFO <= 3⁄4 - 3 - - - Quarter4 - 3⁄4 < FIFO but not full - 4 - - - Full - FIFO full - 5 - - - - - LFSDET - Late frame synchronization detection - 6 - 1 - - LFSDETR - read - - NoError - No error - 0 - - - NoSync - Frame synchronization signal is not present at the right time - 1 - - - - - AFSDET - Anticipated frame synchronization detection - 5 - 1 - - AFSDETR - read - - NoError - No error - 0 - - - EarlySync - Frame synchronization signal is detected earlier than expected - 1 - - - - - CNRDY - Codec not ready - 4 - 1 - - CNRDYR - read - - Ready - External AC’97 Codec is ready - 0 - - - NotReady - External AC’97 Codec is not ready - 1 - - - - - FREQ - FIFO request - 3 - 1 - - FREQR - read - - NoRequest - No FIFO request - 0 - - - Request - FIFO request to read or to write the SAI_xDR - 1 - - - - - WCKCFG - Wrong clock configuration flag. This bit is read only. - 2 - 1 - - WCKCFGR - read - - Correct - Clock configuration is correct - 0 - - - Wrong - Clock configuration does not respect the rule concerning the frame length specification - 1 - - - - - MUTEDET - Mute detection - 1 - 1 - - MUTEDETR - read - - NoMute - No MUTE detection on the SD input line - 0 - - - Mute - MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame - 1 - - - - - OVRUDR - Overrun / underrun - 0 - 1 - - OVRUDRR - read - - NoError - No overrun/underrun error - 0 - - - Overrun - Overrun/underrun error detection - 1 - - - - - - - CLRFR - ACLRFR - AClear flag register - 0x18 - 0x20 - write-only - 0x00000000 - - - CLFSDET - Clear late frame synchronization detection flag - 6 - 1 - - CLFSDETW - write - - Clear - Clears the LFSDET flag - 1 - - - - - CAFSDET - Clear anticipated frame synchronization detection flag. - 5 - 1 - - CAFSDETW - write - - Clear - Clears the AFSDET flag - 1 - - - - - CCNRDY - Clear codec not ready flag - 4 - 1 - - CCNRDYW - write - - Clear - Clears the CNRDY flag - 1 - - - - - CWCKCFG - Clear wrong clock configuration flag - 2 - 1 - - CWCKCFGW - write - - Clear - Clears the WCKCFG flag - 1 - - - - - CMUTEDET - Mute detection flag - 1 - 1 - - CMUTEDETW - write - - Clear - Clears the MUTEDET flag - 1 - - - - - COVRUDR - Clear overrun / underrun - 0 - 1 - - COVRUDRW - write - - Clear - Clears the OVRUDR flag - 1 - - - - - - - DR - ADR - AData register - 0x1C - 0x20 - read-write - 0x00000000 - - - DATA - Data - 0 - 32 - - - - - - GCR - GCR - Global configuration register - 0x0 - 0x20 - read-write - 0x00000000 - - - SYNCIN - Synchronization inputs - 0 - 2 - - - SYNCOUT - Synchronization outputs - 4 - 2 - - - - - - - SAI2 - 0x40015C00 - - SAI2 - SAI2 global interrupt - 91 - - - - DMA2D - DMA2D controller - DMA2D - 0x4002B000 - - 0x0 - 0xC00 - registers - - - DMA2D - DMA2D global interrupt - 90 - - - - CR - CR - control register - 0x0 - 0x20 - read-write - 0x00000000 - - - MODE - DMA2D mode - 16 - 2 - - MODE - read-write - - MemoryToMemory - Memory-to-memory (FG fetch only) - 0 - - - MemoryToMemoryPFC - Memory-to-memory with PFC (FG fetch only with FG PFC active) - 1 - - - MemoryToMemoryPFCBlending - Memory-to-memory with blending (FG and BG fetch with PFC and blending) - 2 - - - RegisterToMemory - Register-to-memory - 3 - - - - - CEIE - Configuration Error Interrupt Enable - 13 - 1 - - CEIE - read-write - - Disabled - CE interrupt disabled - 0 - - - Enabled - CE interrupt enabled - 1 - - - - - CTCIE - CLUT transfer complete interrupt enable - 12 - 1 - - CTCIE - read-write - - Disabled - CTC interrupt disabled - 0 - - - Enabled - CTC interrupt enabled - 1 - - - - - CAEIE - CLUT access error interrupt enable - 11 - 1 - - CAEIE - read-write - - Disabled - CAE interrupt disabled - 0 - - - Enabled - CAE interrupt enabled - 1 - - - - - TWIE - Transfer watermark interrupt enable - 10 - 1 - - TWIE - read-write - - Disabled - TW interrupt disabled - 0 - - - Enabled - TW interrupt enabled - 1 - - - - - TCIE - Transfer complete interrupt enable - 9 - 1 - - TCIE - read-write - - Disabled - TC interrupt disabled - 0 - - - Enabled - TC interrupt enabled - 1 - - - - - TEIE - Transfer error interrupt enable - 8 - 1 - - TEIE - read-write - - Disabled - TE interrupt disabled - 0 - - - Enabled - TE interrupt enabled - 1 - - - - - ABORT - Abort - 2 - 1 - - ABORT - read-write - - AbortRequest - Transfer abort requested - 1 - - - - - SUSP - Suspend - 1 - 1 - - SUSP - read-write - - NotSuspended - Transfer not suspended - 0 - - - Suspended - Transfer suspended - 1 - - - - - START - Start - 0 - 1 - - START - read-write - - Start - Launch the DMA2D - 1 - - - - - - - ISR - ISR - Interrupt Status Register - 0x4 - 0x20 - read-only - 0x00000000 - - - CEIF - Configuration error interrupt flag - 5 - 1 - - - CTCIF - CLUT transfer complete interrupt flag - 4 - 1 - - - CAEIF - CLUT access error interrupt flag - 3 - 1 - - - TWIF - Transfer watermark interrupt flag - 2 - 1 - - - TCIF - Transfer complete interrupt flag - 1 - 1 - - - TEIF - Transfer error interrupt flag - 0 - 1 - - - - - IFCR - IFCR - interrupt flag clear register - 0x8 - 0x20 - read-write - 0x00000000 - - - CCEIF - Clear configuration error interrupt flag - 5 - 1 - - CCEIF - read-write - - Clear - Clear the CEIF flag in the ISR register - 1 - - - - - CCTCIF - Clear CLUT transfer complete interrupt flag - 4 - 1 - - CCTCIF - read-write - - Clear - Clear the CTCIF flag in the ISR register - 1 - - - - - CAECIF - Clear CLUT access error interrupt flag - 3 - 1 - - CAECIF - read-write - - Clear - Clear the CAEIF flag in the ISR register - 1 - - - - - CTWIF - Clear transfer watermark interrupt flag - 2 - 1 - - CTWIF - read-write - - Clear - Clear the TWIF flag in the ISR register - 1 - - - - - CTCIF - Clear transfer complete interrupt flag - 1 - 1 - - CTCIF - read-write - - Clear - Clear the TCIF flag in the ISR register - 1 - - - - - CTEIF - Clear Transfer error interrupt flag - 0 - 1 - - CTEIF - read-write - - Clear - Clear the TEIF flag in the ISR register - 1 - - - - - - - FGMAR - FGMAR - foreground memory address register - 0xC - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - FGOR - FGOR - foreground offset register - 0x10 - 0x20 - read-write - 0x00000000 - - - LO - Line offset - 0 - 14 - - - 0 - 16383 - - - - - - - BGMAR - BGMAR - background memory address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - BGOR - BGOR - background offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - LO - Line offset - 0 - 14 - - - 0 - 16383 - - - - - - - FGPFCCR - FGPFCCR - foreground PFC control register - 0x1C - 0x20 - read-write - 0x00000000 - - - ALPHA - Alpha value - 24 - 8 - - - 0 - 255 - - - - - AM - Alpha mode - 16 - 2 - - AM - read-write - - NoModify - No modification of alpha channel - 0 - - - Replace - Replace with value in ALPHA[7:0] - 1 - - - Multiply - Multiply with value in ALPHA[7:0] - 2 - - - - - CS - CLUT size - 8 - 8 - - - 0 - 255 - - - - - START - Start - 5 - 1 - - START - read-write - - Start - Start the automatic loading of the CLUT - 1 - - - - - CCM - CLUT color mode - 4 - 1 - - CCM - read-write - - ARGB8888 - CLUT color format ARGB8888 - 0 - - - RGB888 - CLUT color format RGB888 - 1 - - - - - CM - Color mode - 0 - 4 - - CM - read-write - - ARGB8888 - Color mode ARGB8888 - 0 - - - RGB888 - Color mode RGB888 - 1 - - - RGB565 - Color mode RGB565 - 2 - - - ARGB1555 - Color mode ARGB1555 - 3 - - - ARGB4444 - Color mode ARGB4444 - 4 - - - L8 - Color mode L8 - 5 - - - AL44 - Color mode AL44 - 6 - - - AL88 - Color mode AL88 - 7 - - - L4 - Color mode L4 - 8 - - - A8 - Color mode A8 - 9 - - - A4 - Color mode A4 - 10 - - - - - - - FGCOLR - FGCOLR - foreground color register - 0x20 - 0x20 - read-write - 0x00000000 - - - RED - Red Value - 16 - 8 - - - 0 - 255 - - - - - GREEN - Green Value - 8 - 8 - - - 0 - 255 - - - - - BLUE - Blue Value - 0 - 8 - - - 0 - 255 - - - - - - - BGPFCCR - BGPFCCR - background PFC control register - 0x24 - 0x20 - read-write - 0x00000000 - - - ALPHA - Alpha value - 24 - 8 - - - 0 - 255 - - - - - AM - Alpha mode - 16 - 2 - - AM - read-write - - NoModify - No modification of alpha channel - 0 - - - Replace - Replace with value in ALPHA[7:0] - 1 - - - Multiply - Multiply with value in ALPHA[7:0] - 2 - - - - - CS - CLUT size - 8 - 8 - - - 0 - 255 - - - - - START - Start - 5 - 1 - - START - read-write - - Start - Start the automatic loading of the CLUT - 1 - - - - - CCM - CLUT Color mode - 4 - 1 - - CCM - read-write - - ARGB8888 - CLUT color format ARGB8888 - 0 - - - RGB888 - CLUT color format RGB888 - 1 - - - - - CM - Color mode - 0 - 4 - - CM - read-write - - ARGB8888 - Color mode ARGB8888 - 0 - - - RGB888 - Color mode RGB888 - 1 - - - RGB565 - Color mode RGB565 - 2 - - - ARGB1555 - Color mode ARGB1555 - 3 - - - ARGB4444 - Color mode ARGB4444 - 4 - - - L8 - Color mode L8 - 5 - - - AL44 - Color mode AL44 - 6 - - - AL88 - Color mode AL88 - 7 - - - L4 - Color mode L4 - 8 - - - A8 - Color mode A8 - 9 - - - A4 - Color mode A4 - 10 - - - - - - - BGCOLR - BGCOLR - background color register - 0x28 - 0x20 - read-write - 0x00000000 - - - RED - Red Value - 16 - 8 - - - 0 - 255 - - - - - GREEN - Green Value - 8 - 8 - - - 0 - 255 - - - - - BLUE - Blue Value - 0 - 8 - - - 0 - 255 - - - - - - - FGCMAR - FGCMAR - foreground CLUT memory address register - 0x2C - 0x20 - read-write - 0x00000000 - - - MA - Memory Address - 0 - 32 - - - - - BGCMAR - BGCMAR - background CLUT memory address register - 0x30 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - OPFCCR - OPFCCR - output PFC control register - 0x34 - 0x20 - read-write - 0x00000000 - - - CM - Color mode - 0 - 3 - - CM - read-write - - ARGB8888 - ARGB8888 - 0 - - - RGB888 - RGB888 - 1 - - - RGB565 - RGB565 - 2 - - - ARGB1555 - ARGB1555 - 3 - - - ARGB4444 - ARGB4444 - 4 - - - - - - - OCOLR - OCOLR - output color register - 0x38 - 0x20 - read-write - 0x00000000 - - - APLHA - Alpha Channel Value - 24 - 8 - - - RED - Red Value - 16 - 8 - - - GREEN - Green Value - 8 - 8 - - - BLUE - Blue Value - 0 - 8 - - - - - OMAR - OMAR - output memory address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MA - Memory Address - 0 - 32 - - - - - OOR - OOR - output offset register - 0x40 - 0x20 - read-write - 0x00000000 - - - LO - Line Offset - 0 - 14 - - - 0 - 16383 - - - - - - - NLR - NLR - number of line register - 0x44 - 0x20 - read-write - 0x00000000 - - - PL - Pixel per lines - 16 - 14 - - - 0 - 16383 - - - - - NL - Number of lines - 0 - 16 - - - 0 - 65535 - - - - - - - LWR - LWR - line watermark register - 0x48 - 0x20 - read-write - 0x00000000 - - - LW - Line watermark - 0 - 16 - - - - - AMTCR - AMTCR - AHB master timer configuration register - 0x4C - 0x20 - read-write - 0x00000000 - - - DT - Dead Time - 8 - 8 - - - 0 - 255 - - - - - EN - Enable - 0 - 1 - - EN - read-write - - Disabled - Disabled AHB/AXI dead-time functionality - 0 - - - Enabled - Enabled AHB/AXI dead-time functionality - 1 - - - - - - - FGCLUT - FGCLUT - FGCLUT - 0x400 - 0x20 - read-write - 0x00000000 - - - APLHA - APLHA - 24 - 8 - - - RED - RED - 16 - 8 - - - GREEN - GREEN - 8 - 8 - - - BLUE - BLUE - 0 - 8 - - - - - BGCLUT - BGCLUT - BGCLUT - 0x800 - 0x20 - read-write - 0x00000000 - - - APLHA - APLHA - 24 - 8 - - - RED - RED - 16 - 8 - - - GREEN - GREEN - 8 - 8 - - - BLUE - BLUE - 0 - 8 - - - - - - - QUADSPI - QuadSPI interface - QUADSPI - 0xA0001000 - - 0x0 - 0x1000 - registers - - - QuadSPI - QuadSPI global interrupt - 92 - - - - CR - CR - control register - 0x0 - 0x20 - read-write - 0x00000000 - - - PRESCALER - Clock prescaler - 24 - 8 - - - PMM - Polling match mode - 23 - 1 - - - APMS - Automatic poll mode stop - 22 - 1 - - - TOIE - TimeOut interrupt enable - 20 - 1 - - - SMIE - Status match interrupt enable - 19 - 1 - - - FTIE - FIFO threshold interrupt enable - 18 - 1 - - - TCIE - Transfer complete interrupt enable - 17 - 1 - - - TEIE - Transfer error interrupt enable - 16 - 1 - - - FTHRES - IFO threshold level - 8 - 5 - - - FSEL - FLASH memory selection - 7 - 1 - - - DFM - Dual-flash mode - 6 - 1 - - - SSHIFT - Sample shift - 4 - 1 - - - TCEN - Timeout counter enable - 3 - 1 - - - DMAEN - DMA enable - 2 - 1 - - - ABORT - Abort request - 1 - 1 - - - EN - Enable - 0 - 1 - - - - - DCR - DCR - device configuration register - 0x4 - 0x20 - read-write - 0x00000000 - - - FSIZE - FLASH memory size - 16 - 5 - - - CSHT - Chip select high time - 8 - 3 - - - CKMODE - Mode 0 / mode 3 - 0 - 1 - - - - - SR - SR - status register - 0x8 - 0x20 - read-only - 0x00000000 - - - FLEVEL - FIFO level - 8 - 7 - - - BUSY - Busy - 5 - 1 - - - TOF - Timeout flag - 4 - 1 - - - SMF - Status match flag - 3 - 1 - - - FTF - FIFO threshold flag - 2 - 1 - - - TCF - Transfer complete flag - 1 - 1 - - - TEF - Transfer error flag - 0 - 1 - - - - - FCR - FCR - flag clear register - 0xC - 0x20 - read-write - 0x00000000 - - - CTOF - Clear timeout flag - 4 - 1 - - - CSMF - Clear status match flag - 3 - 1 - - - CTCF - Clear transfer complete flag - 1 - 1 - - - CTEF - Clear transfer error flag - 0 - 1 - - - - - DLR - DLR - data length register - 0x10 - 0x20 - read-write - 0x00000000 - - - DL - Data length - 0 - 32 - - - - - CCR - CCR - communication configuration register - 0x14 - 0x20 - read-write - 0x00000000 - - - DDRM - Double data rate mode - 31 - 1 - - - DHHC - DDR hold half cycle - 30 - 1 - - - SIOO - Send instruction only once mode - 28 - 1 - - - FMODE - Functional mode - 26 - 2 - - - DMODE - Data mode - 24 - 2 - - - DCYC - Number of dummy cycles - 18 - 5 - - - ABSIZE - Alternate bytes size - 16 - 2 - - - ABMODE - Alternate bytes mode - 14 - 2 - - - ADSIZE - Address size - 12 - 2 - - - ADMODE - Address mode - 10 - 2 - - - IMODE - Instruction mode - 8 - 2 - - - INSTRUCTION - Instruction - 0 - 8 - - - - - AR - AR - address register - 0x18 - 0x20 - read-write - 0x00000000 - - - ADDRESS - Address - 0 - 32 - - - - - ABR - ABR - ABR - 0x1C - 0x20 - read-write - 0x00000000 - - - ALTERNATE - ALTERNATE - 0 - 32 - - - - - DR - DR - data register - 0x20 - 0x20 - read-write - 0x00000000 - - - DATA - Data - 0 - 32 - - - - - PSMKR - PSMKR - polling status mask register - 0x24 - 0x20 - read-write - 0x00000000 - - - MASK - Status mask - 0 - 32 - - - - - PSMAR - PSMAR - polling status match register - 0x28 - 0x20 - read-write - 0x00000000 - - - MATCH - Status match - 0 - 32 - - - - - PIR - PIR - polling interval register - 0x2C - 0x20 - read-write - 0x00000000 - - - INTERVAL - Polling interval - 0 - 16 - - - - - LPTR - LPTR - low-power timeout register - 0x30 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Timeout period - 0 - 16 - - - - - - - CEC - HDMI-CEC controller - CEC - 0x40006C00 - - 0x0 - 0x400 - registers - - - HDMI_CEC - HDMI-CEC global interrupt - 94 - - - - CR - CR - control register - 0x0 - 0x20 - read-write - 0x00000000 - - - TXEOM - Tx End Of Message - 2 - 1 - - - TXSOM - Tx start of message - 1 - 1 - - - CECEN - CEC Enable - 0 - 1 - - - - - CFGR - CFGR - configuration register - 0x4 - 0x20 - read-write - 0x00000000 - - - SFT - Signal Free Time - 0 - 3 - - - RXTOL - Rx-Tolerance - 3 - 1 - - - BRESTP - Rx-stop on bit rising error - 4 - 1 - - - BREGEN - Generate error-bit on bit rising error - 5 - 1 - - - LBPEGEN - Generate Error-Bit on Long Bit Period Error - 6 - 1 - - - BRDNOGEN - Avoid Error-Bit Generation in Broadcast - 7 - 1 - - - SFTOP - SFT Option Bit - 8 - 1 - - - OAR - Own addresses configuration - 16 - 15 - - - LSTN - Listen mode - 31 - 1 - - - - - TXDR - TXDR - Tx data register - 0x8 - 0x20 - write-only - 0x00000000 - - - TXD - Tx Data register - 0 - 8 - - - - - RXDR - RXDR - Rx Data Register - 0xC - 0x20 - read-only - 0x00000000 - - - RXDR - CEC Rx Data Register - 0 - 8 - - - - - ISR - ISR - Interrupt and Status Register - 0x10 - 0x20 - read-write - 0x00000000 - - - TXACKE - Tx-Missing acknowledge error - 12 - 1 - - - TXERR - Tx-Error - 11 - 1 - - - TXUDR - Tx-Buffer Underrun - 10 - 1 - - - TXEND - End of Transmission - 9 - 1 - - - TXBR - Tx-Byte Request - 8 - 1 - - - ARBLST - Arbitration Lost - 7 - 1 - - - RXACKE - Rx-Missing Acknowledge - 6 - 1 - - - LBPE - Rx-Long Bit Period Error - 5 - 1 - - - SBPE - Rx-Short Bit period error - 4 - 1 - - - BRE - Rx-Bit rising error - 3 - 1 - - - RXOVR - Rx-Overrun - 2 - 1 - - - RXEND - End Of Reception - 1 - 1 - - - RXBR - Rx-Byte Received - 0 - 1 - - - - - IER - IER - interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - TXACKIE - Tx-Missing Acknowledge Error Interrupt Enable - 12 - 1 - - - TXERRIE - Tx-Error Interrupt Enable - 11 - 1 - - - TXUDRIE - Tx-Underrun interrupt enable - 10 - 1 - - - TXENDIE - Tx-End of message interrupt enable - 9 - 1 - - - TXBRIE - Tx-Byte Request Interrupt Enable - 8 - 1 - - - ARBLSTIE - Arbitration Lost Interrupt Enable - 7 - 1 - - - RXACKIE - Rx-Missing Acknowledge Error Interrupt Enable - 6 - 1 - - - LBPEIE - Long Bit Period Error Interrupt Enable - 5 - 1 - - - SBPEIE - Short Bit Period Error Interrupt Enable - 4 - 1 - - - BREIE - Bit Rising Error Interrupt Enable - 3 - 1 - - - RXOVRIE - Rx-Buffer Overrun Interrupt Enable - 2 - 1 - - - RXENDIE - End Of Reception Interrupt Enable - 1 - 1 - - - RXBRIE - Rx-Byte Received Interrupt Enable - 0 - 1 - - - - - - - SPDIFRX - Receiver Interface - SPDIF_RX - 0x40004000 - - 0x0 - 0x400 - registers - - - SPDIFRX - SPDIFRX global interrupt - 97 - - - - CR - CR - Control register - 0x0 - 0x20 - read-write - 0x00000000 - - - SPDIFEN - Peripheral Block Enable - 0 - 2 - - - RXDMAEN - Receiver DMA ENable for data flow - 2 - 1 - - - RXSTEO - STerEO Mode - 3 - 1 - - - DRFMT - RX Data format - 4 - 2 - - - PMSK - Mask Parity error bit - 6 - 1 - - - VMSK - Mask of Validity bit - 7 - 1 - - - CUMSK - Mask of channel status and user bits - 8 - 1 - - - PTMSK - Mask of Preamble Type bits - 9 - 1 - - - CBDMAEN - Control Buffer DMA ENable for control flow - 10 - 1 - - - CHSEL - Channel Selection - 11 - 1 - - - NBTR - Maximum allowed re-tries during synchronization phase - 12 - 2 - - - WFA - Wait For Activity - 14 - 1 - - - INSEL - input selection - 16 - 3 - - - - - IMR - IMR - Interrupt mask register - 0x4 - 0x20 - read-write - 0x00000000 - - - RXNEIE - RXNE interrupt enable - 0 - 1 - - - CSRNEIE - Control Buffer Ready Interrupt Enable - 1 - 1 - - - PERRIE - Parity error interrupt enable - 2 - 1 - - - OVRIE - Overrun error Interrupt Enable - 3 - 1 - - - SBLKIE - Synchronization Block Detected Interrupt Enable - 4 - 1 - - - SYNCDIE - Synchronization Done - 5 - 1 - - - IFEIE - Serial Interface Error Interrupt Enable - 6 - 1 - - - - - SR - SR - Status register - 0x8 - 0x20 - read-only - 0x00000000 - - - RXNE - Read data register not empty - 0 - 1 - - - CSRNE - Control Buffer register is not empty - 1 - 1 - - - PERR - Parity error - 2 - 1 - - - OVR - Overrun error - 3 - 1 - - - SBD - Synchronization Block Detected - 4 - 1 - - - SYNCD - Synchronization Done - 5 - 1 - - - FERR - Framing error - 6 - 1 - - - SERR - Synchronization error - 7 - 1 - - - TERR - Time-out error - 8 - 1 - - - WIDTH5 - Duration of 5 symbols counted with SPDIF_CLK - 16 - 15 - - - - - IFCR - IFCR - Interrupt Flag Clear register - 0xC - 0x20 - write-only - 0x00000000 - - - PERRCF - Clears the Parity error flag - 2 - 1 - - - OVRCF - Clears the Overrun error flag - 3 - 1 - - - SBDCF - Clears the Synchronization Block Detected flag - 4 - 1 - - - SYNCDCF - Clears the Synchronization Done flag - 5 - 1 - - - - - DR - DR - Data input register - 0x10 - 0x20 - read-only - 0x00000000 - - - DR - Parity Error bit - 0 - 24 - - - PE - Parity Error bit - 24 - 1 - - - V - Validity bit - 25 - 1 - - - U - User bit - 26 - 1 - - - C - Channel Status bit - 27 - 1 - - - PT - Preamble Type - 28 - 2 - - - - - CSR - CSR - Channel Status register - 0x14 - 0x20 - read-only - 0x00000000 - - - USR - User data information - 0 - 16 - - - CS - Channel A status information - 16 - 8 - - - SOB - Start Of Block - 24 - 1 - - - - - DIR - DIR - Debug Information register - 0x18 - 0x20 - read-only - 0x00000000 - - - THI - Threshold HIGH - 0 - 13 - - - TLO - Threshold LOW - 16 - 13 - - - - - - - SDMMC1 - Secure digital input/output interface - SDMMC - 0x40012C00 - - 0x0 - 0x400 - registers - - - SDMMC1 - SDMMC1 global interrupt - 49 - - - - POWER - POWER - power control register - 0x0 - 0x20 - read-write - 0x00000000 - - - PWRCTRL - PWRCTRL - 0 - 2 - - - - - CLKCR - CLKCR - SDI clock control register - 0x4 - 0x20 - read-write - 0x00000000 - - - HWFC_EN - HW Flow Control enable - 14 - 1 - - - NEGEDGE - SDIO_CK dephasing selection bit - 13 - 1 - - - WIDBUS - Wide bus mode enable bit - 11 - 2 - - - BYPASS - Clock divider bypass enable bit - 10 - 1 - - - PWRSAV - Power saving configuration bit - 9 - 1 - - - CLKEN - Clock enable bit - 8 - 1 - - - CLKDIV - Clock divide factor - 0 - 8 - - - - - ARG - ARG - argument register - 0x8 - 0x20 - read-write - 0x00000000 - - - CMDARG - Command argument - 0 - 32 - - - - - CMD - CMD - command register - 0xC - 0x20 - read-write - 0x00000000 - - - SDIOSuspend - SD I/O suspend command - 11 - 1 - - - CPSMEN - Command path state machine (CPSM) Enable bit - 10 - 1 - - - WAITPEND - CPSM Waits for ends of data transfer (CmdPend internal signal) - 9 - 1 - - - WAITINT - CPSM waits for interrupt request - 8 - 1 - - - WAITRESP - Wait for response bits - 6 - 2 - - - CMDINDEX - Command index - 0 - 6 - - - - - RESPCMD - RESPCMD - command response register - 0x10 - 0x20 - read-only - 0x00000000 - - - RESPCMD - Response command index - 0 - 6 - - - - - RESP1 - RESP1 - response 1..4 register - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTATUS1 - see Table 132 - 0 - 32 - - - - - RESP2 - RESP2 - response 1..4 register - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTATUS2 - see Table 132 - 0 - 32 - - - - - RESP3 - RESP3 - response 1..4 register - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTATUS3 - see Table 132 - 0 - 32 - - - - - RESP4 - RESP4 - response 1..4 register - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTATUS4 - see Table 132 - 0 - 32 - - - - - DTIMER - DTIMER - data timer register - 0x24 - 0x20 - read-write - 0x00000000 - - - DATATIME - Data timeout period - 0 - 32 - - - - - DLEN - DLEN - data length register - 0x28 - 0x20 - read-write - 0x00000000 - - - DATALENGTH - Data length value - 0 - 25 - - - - - DCTRL - DCTRL - data control register - 0x2C - 0x20 - read-write - 0x00000000 - - - SDIOEN - SD I/O enable functions - 11 - 1 - - - RWMOD - Read wait mode - 10 - 1 - - - RWSTOP - Read wait stop - 9 - 1 - - - RWSTART - Read wait start - 8 - 1 - - - DBLOCKSIZE - Data block size - 4 - 4 - - - DMAEN - DMA enable bit - 3 - 1 - - - DTMODE - Data transfer mode selection 1: Stream or SDIO multibyte data transfer - 2 - 1 - - - DTDIR - Data transfer direction selection - 1 - 1 - - - DTEN - DTEN - 0 - 1 - - - - - DCOUNT - DCOUNT - data counter register - 0x30 - 0x20 - read-only - 0x00000000 - - - DATACOUNT - Data count value - 0 - 25 - - - - - STA - STA - status register - 0x34 - 0x20 - read-only - 0x00000000 - - - SDIOIT - SDIO interrupt received - 22 - 1 - - - RXDAVL - Data available in receive FIFO - 21 - 1 - - - TXDAVL - Data available in transmit FIFO - 20 - 1 - - - RXFIFOE - Receive FIFO empty - 19 - 1 - - - TXFIFOE - Transmit FIFO empty - 18 - 1 - - - RXFIFOF - Receive FIFO full - 17 - 1 - - - TXFIFOF - Transmit FIFO full - 16 - 1 - - - RXFIFOHF - Receive FIFO half full: there are at least 8 words in the FIFO - 15 - 1 - - - TXFIFOHE - Transmit FIFO half empty: at least 8 words can be written into the FIFO - 14 - 1 - - - RXACT - Data receive in progress - 13 - 1 - - - TXACT - Data transmit in progress - 12 - 1 - - - CMDACT - Command transfer in progress - 11 - 1 - - - DBCKEND - Data block sent/received (CRC check passed) - 10 - 1 - - - DATAEND - Data end (data counter, SDIDCOUNT, is zero) - 8 - 1 - - - CMDSENT - Command sent (no response required) - 7 - 1 - - - CMDREND - Command response received (CRC check passed) - 6 - 1 - - - RXOVERR - Received FIFO overrun error - 5 - 1 - - - TXUNDERR - Transmit FIFO underrun error - 4 - 1 - - - DTIMEOUT - Data timeout - 3 - 1 - - - CTIMEOUT - Command response timeout - 2 - 1 - - - DCRCFAIL - Data block sent/received (CRC check failed) - 1 - 1 - - - CCRCFAIL - Command response received (CRC check failed) - 0 - 1 - - - - - ICR - ICR - interrupt clear register - 0x38 - 0x20 - read-write - 0x00000000 - - - SDIOITC - SDIOIT flag clear bit - 22 - 1 - - - DBCKENDC - DBCKEND flag clear bit - 10 - 1 - - - DATAENDC - DATAEND flag clear bit - 8 - 1 - - - CMDSENTC - CMDSENT flag clear bit - 7 - 1 - - - CMDRENDC - CMDREND flag clear bit - 6 - 1 - - - RXOVERRC - RXOVERR flag clear bit - 5 - 1 - - - TXUNDERRC - TXUNDERR flag clear bit - 4 - 1 - - - DTIMEOUTC - DTIMEOUT flag clear bit - 3 - 1 - - - CTIMEOUTC - CTIMEOUT flag clear bit - 2 - 1 - - - DCRCFAILC - DCRCFAIL flag clear bit - 1 - 1 - - - CCRCFAILC - CCRCFAIL flag clear bit - 0 - 1 - - - - - MASK - MASK - mask register - 0x3C - 0x20 - read-write - 0x00000000 - - - SDIOITIE - SDIO mode interrupt received interrupt enable - 22 - 1 - - - RXDAVLIE - Data available in Rx FIFO interrupt enable - 21 - 1 - - - TXDAVLIE - Data available in Tx FIFO interrupt enable - 20 - 1 - - - RXFIFOEIE - Rx FIFO empty interrupt enable - 19 - 1 - - - TXFIFOEIE - Tx FIFO empty interrupt enable - 18 - 1 - - - RXFIFOFIE - Rx FIFO full interrupt enable - 17 - 1 - - - TXFIFOFIE - Tx FIFO full interrupt enable - 16 - 1 - - - RXFIFOHFIE - Rx FIFO half full interrupt enable - 15 - 1 - - - TXFIFOHEIE - Tx FIFO half empty interrupt enable - 14 - 1 - - - RXACTIE - Data receive acting interrupt enable - 13 - 1 - - - TXACTIE - Data transmit acting interrupt enable - 12 - 1 - - - CMDACTIE - Command acting interrupt enable - 11 - 1 - - - DBCKENDIE - Data block end interrupt enable - 10 - 1 - - - DATAENDIE - Data end interrupt enable - 8 - 1 - - - CMDSENTIE - Command sent interrupt enable - 7 - 1 - - - CMDRENDIE - Command response received interrupt enable - 6 - 1 - - - RXOVERRIE - Rx FIFO overrun error interrupt enable - 5 - 1 - - - TXUNDERRIE - Tx FIFO underrun error interrupt enable - 4 - 1 - - - DTIMEOUTIE - Data timeout interrupt enable - 3 - 1 - - - CTIMEOUTIE - Command timeout interrupt enable - 2 - 1 - - - DCRCFAILIE - Data CRC fail interrupt enable - 1 - 1 - - - CCRCFAILIE - Command CRC fail interrupt enable - 0 - 1 - - - - - FIFOCNT - FIFOCNT - FIFO counter register - 0x48 - 0x20 - read-only - 0x00000000 - - - FIFOCOUNT - Remaining number of words to be written to or read from the FIFO - 0 - 24 - - - - - FIFO - FIFO - data FIFO register - 0x80 - 0x20 - read-write - 0x00000000 - - - FIFOData - Receive and transmit FIFO data - 0 - 32 - - - - - - - LPTIM1 - Low power timer - LPTIM - 0x40002400 - - 0x0 - 0x400 - registers - - - LPTimer1 - LP Timer1 global interrupt - 93 - - - LP_Timer1 - LP Timer1 global interrupt - 93 - - - - ISR - ISR - Interrupt and Status Register - 0x0 - 0x20 - read-only - 0x00000000 - - - DOWN - Counter direction change up to down - 6 - 1 - - - UP - Counter direction change down to up - 5 - 1 - - - ARROK - Autoreload register update OK - 4 - 1 - - - CMPOK - Compare register update OK - 3 - 1 - - - EXTTRIG - External trigger edge event - 2 - 1 - - - ARRM - Autoreload match - 1 - 1 - - - CMPM - Compare match - 0 - 1 - - - - - ICR - ICR - Interrupt Clear Register - 0x4 - 0x20 - write-only - 0x00000000 - - - DOWNCF - Direction change to down Clear Flag - 6 - 1 - - - UPCF - Direction change to UP Clear Flag - 5 - 1 - - - ARROKCF - Autoreload register update OK Clear Flag - 4 - 1 - - - CMPOKCF - Compare register update OK Clear Flag - 3 - 1 - - - EXTTRIGCF - External trigger valid edge Clear Flag - 2 - 1 - - - ARRMCF - Autoreload match Clear Flag - 1 - 1 - - - CMPMCF - compare match Clear Flag - 0 - 1 - - - - - IER - IER - Interrupt Enable Register - 0x8 - 0x20 - read-write - 0x00000000 - - - DOWNIE - Direction change to down Interrupt Enable - 6 - 1 - - - UPIE - Direction change to UP Interrupt Enable - 5 - 1 - - - ARROKIE - Autoreload register update OK Interrupt Enable - 4 - 1 - - - CMPOKIE - Compare register update OK Interrupt Enable - 3 - 1 - - - EXTTRIGIE - External trigger valid edge Interrupt Enable - 2 - 1 - - - ARRMIE - Autoreload match Interrupt Enable - 1 - 1 - - - CMPMIE - Compare match Interrupt Enable - 0 - 1 - - - - - CFGR - CFGR - Configuration Register - 0xC - 0x20 - read-write - 0x00000000 - - - ENC - Encoder mode enable - 24 - 1 - - - COUNTMODE - counter mode enabled - 23 - 1 - - - PRELOAD - Registers update mode - 22 - 1 - - - WAVPOL - Waveform shape polarity - 21 - 1 - - - WAVE - Waveform shape - 20 - 1 - - - TIMOUT - Timeout enable - 19 - 1 - - - TRIGEN - Trigger enable and polarity - 17 - 2 - - - TRIGSEL - Trigger selector - 13 - 3 - - - PRESC - Clock prescaler - 9 - 3 - - - TRGFLT - Configurable digital filter for trigger - 6 - 2 - - - CKFLT - Configurable digital filter for external clock - 3 - 2 - - - CKPOL - Clock Polarity - 1 - 2 - - - CKSEL - Clock selector - 0 - 1 - - - - - CR - CR - Control Register - 0x10 - 0x20 - read-write - 0x00000000 - - - CNTSTRT - Timer start in continuous mode - 2 - 1 - - - SNGSTRT - LPTIM start in single mode - 1 - 1 - - - ENABLE - LPTIM Enable - 0 - 1 - - - - - CMP - CMP - Compare Register - 0x14 - 0x20 - read-write - 0x00000000 - - - CMP - Compare value - 0 - 16 - - - - - ARR - ARR - Autoreload Register - 0x18 - 0x20 - read-write - 0x00000001 - - - ARR - Auto reload value - 0 - 16 - - - - - CNT - CNT - Counter Register - 0x1C - 0x20 - read-only - 0x00000000 - - - CNT - Counter value - 0 - 16 - - - - - - - I2C1 - Inter-integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EV - I2C1 event interrupt - 31 - - - I2C1_ER - I2C1 error interrupt - 32 - - - I2C2_EV - I2C2 event interrupt - 33 - - - I2C2_ER - I2C2 error interrupt - 34 - - - I2C3_EV - I2C3 event interrupt - 72 - - - I2C3_ER - I2C3 error interrupt - 73 - - - I2C4_EV - I2C4 event interrupt - 95 - - - I2C4_ER - I2C4 error interrupt - 96 - - - - CR1 - CR1 - Control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - PE - Peripheral enable - 0 - 1 - - PE - read-write - - Disabled - Peripheral disabled - 0 - - - Enabled - Peripheral enabled - 1 - - - - - TXIE - TX Interrupt enable - 1 - 1 - - TXIE - read-write - - Disabled - Transmit (TXIS) interrupt disabled - 0 - - - Enabled - Transmit (TXIS) interrupt enabled - 1 - - - - - RXIE - RX Interrupt enable - 2 - 1 - - RXIE - read-write - - Disabled - Receive (RXNE) interrupt disabled - 0 - - - Enabled - Receive (RXNE) interrupt enabled - 1 - - - - - ADDRIE - Address match interrupt enable (slave only) - 3 - 1 - - ADDRIE - read-write - - Disabled - Address match (ADDR) interrupts disabled - 0 - - - Enabled - Address match (ADDR) interrupts enabled - 1 - - - - - NACKIE - Not acknowledge received interrupt enable - 4 - 1 - - NACKIE - read-write - - Disabled - Not acknowledge (NACKF) received interrupts disabled - 0 - - - Enabled - Not acknowledge (NACKF) received interrupts enabled - 1 - - - - - STOPIE - STOP detection Interrupt enable - 5 - 1 - - STOPIE - read-write - - Disabled - Stop detection (STOPF) interrupt disabled - 0 - - - Enabled - Stop detection (STOPF) interrupt enabled - 1 - - - - - TCIE - Transfer Complete interrupt enable - 6 - 1 - - TCIE - read-write - - Disabled - Transfer Complete interrupt disabled - 0 - - - Enabled - Transfer Complete interrupt enabled - 1 - - - - - ERRIE - Error interrupts enable - 7 - 1 - - ERRIE - read-write - - Disabled - Error detection interrupts disabled - 0 - - - Enabled - Error detection interrupts enabled - 1 - - - - - DNF - Digital noise filter - 8 - 4 - - DNF - read-write - - NoFilter - Digital filter disabled - 0 - - - Filter1 - Digital filter enabled and filtering capability up to 1 tI2CCLK - 1 - - - Filter2 - Digital filter enabled and filtering capability up to 2 tI2CCLK - 2 - - - Filter3 - Digital filter enabled and filtering capability up to 3 tI2CCLK - 3 - - - Filter4 - Digital filter enabled and filtering capability up to 4 tI2CCLK - 4 - - - Filter5 - Digital filter enabled and filtering capability up to 5 tI2CCLK - 5 - - - Filter6 - Digital filter enabled and filtering capability up to 6 tI2CCLK - 6 - - - Filter7 - Digital filter enabled and filtering capability up to 7 tI2CCLK - 7 - - - Filter8 - Digital filter enabled and filtering capability up to 8 tI2CCLK - 8 - - - Filter9 - Digital filter enabled and filtering capability up to 9 tI2CCLK - 9 - - - Filter10 - Digital filter enabled and filtering capability up to 10 tI2CCLK - 10 - - - Filter11 - Digital filter enabled and filtering capability up to 11 tI2CCLK - 11 - - - Filter12 - Digital filter enabled and filtering capability up to 12 tI2CCLK - 12 - - - Filter13 - Digital filter enabled and filtering capability up to 13 tI2CCLK - 13 - - - Filter14 - Digital filter enabled and filtering capability up to 14 tI2CCLK - 14 - - - Filter15 - Digital filter enabled and filtering capability up to 15 tI2CCLK - 15 - - - - - ANFOFF - Analog noise filter OFF - 12 - 1 - - ANFOFF - read-write - - Enabled - Analog noise filter enabled - 0 - - - Disabled - Analog noise filter disabled - 1 - - - - - TXDMAEN - DMA transmission requests enable - 14 - 1 - - TXDMAEN - read-write - - Disabled - DMA mode disabled for transmission - 0 - - - Enabled - DMA mode enabled for transmission - 1 - - - - - RXDMAEN - DMA reception requests enable - 15 - 1 - - RXDMAEN - read-write - - Disabled - DMA mode disabled for reception - 0 - - - Enabled - DMA mode enabled for reception - 1 - - - - - SBC - Slave byte control - 16 - 1 - - SBC - read-write - - Disabled - Slave byte control disabled - 0 - - - Enabled - Slave byte control enabled - 1 - - - - - NOSTRETCH - Clock stretching disable - 17 - 1 - - NOSTRETCH - read-write - - Enabled - Clock stretching enabled - 0 - - - Disabled - Clock stretching disabled - 1 - - - - - WUPEN - Wakeup from STOP enable - 18 - 1 - - WUPEN - read-write - - Disabled - Wakeup from Stop mode disabled - 0 - - - Enabled - Wakeup from Stop mode enabled - 1 - - - - - GCEN - General call enable - 19 - 1 - - GCEN - read-write - - Disabled - General call disabled. Address 0b00000000 is NACKed - 0 - - - Enabled - General call enabled. Address 0b00000000 is ACKed - 1 - - - - - SMBHEN - SMBus Host address enable - 20 - 1 - - SMBHEN - read-write - - Disabled - Host address disabled. Address 0b0001000x is NACKed - 0 - - - Enabled - Host address enabled. Address 0b0001000x is ACKed - 1 - - - - - SMBDEN - SMBus Device Default address enable - 21 - 1 - - SMBDEN - read-write - - Disabled - Device default address disabled. Address 0b1100001x is NACKed - 0 - - - Enabled - Device default address enabled. Address 0b1100001x is ACKed - 1 - - - - - ALERTEN - SMBUS alert enable - 22 - 1 - - ALERTEN - read-write - - Disabled - In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported - 0 - - - Enabled - In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported - 1 - - - - - PECEN - PEC enable - 23 - 1 - - PECEN - read-write - - Disabled - PEC calculation disabled - 0 - - - Enabled - PEC calculation enabled - 1 - - - - - - - CR2 - CR2 - Control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - PECBYTE - Packet error checking byte - 26 - 1 - oneToSet - - PECBYTER - read - - NoPec - No PEC transfer - 0 - - - Pec - PEC transmission/reception is requested - 1 - - - - PECBYTEW - write - - Pec - PEC transmission/reception is requested - 1 - - - - - AUTOEND - Automatic end mode (master mode) - 25 - 1 - - AUTOEND - read-write - - Software - Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low - 0 - - - Automatic - Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred - 1 - - - - - RELOAD - NBYTES reload mode - 24 - 1 - - RELOAD - read-write - - Completed - The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) - 0 - - - NotCompleted - The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) - 1 - - - - - NBYTES - Number of bytes - 16 - 8 - - - 0 - 255 - - - - - NACK - NACK generation (slave mode) - 15 - 1 - oneToSet - - NACKR - read - - Ack - an ACK is sent after current received byte - 0 - - - Nack - a NACK is sent after current received byte - 1 - - - - NACKW - write - - Nack - a NACK is sent after current received byte - 1 - - - - - STOP - Stop generation (master mode) - 14 - 1 - oneToSet - - STOPR - read - - NoStop - No Stop generation - 0 - - - Stop - Stop generation after current byte transfer - 1 - - - - STOPW - write - - Stop - Stop generation after current byte transfer - 1 - - - - - START - Start generation - 13 - 1 - oneToSet - - STARTR - read - - NoStart - No Start generation - 0 - - - Start - Restart/Start generation - 1 - - - - STARTW - write - - Start - Restart/Start generation - 1 - - - - - HEAD10R - 10-bit address header only read direction (master receiver mode) - 12 - 1 - - HEAD10R - read-write - - Complete - The master sends the complete 10 bit slave address read sequence - 0 - - - Partial - The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction - 1 - - - - - ADD10 - 10-bit addressing mode (master mode) - 11 - 1 - - ADD10 - read-write - - Bit7 - The master operates in 7-bit addressing mode - 0 - - - Bit10 - The master operates in 10-bit addressing mode - 1 - - - - - RD_WRN - Transfer direction (master mode) - 10 - 1 - - RD_WRN - read-write - - Write - Master requests a write transfer - 0 - - - Read - Master requests a read transfer - 1 - - - - - SADD - Slave address bit (master mode) - 0 - 10 - - - 0 - 1023 - - - - - - - OAR1 - OAR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - OA1 - Interface address - 0 - 10 - - - 0 - 1023 - - - - - OA1MODE - Own Address 1 10-bit mode - 10 - 1 - - OA1MODE - read-write - - Bit7 - Own address 1 is a 7-bit address - 0 - - - Bit10 - Own address 1 is a 10-bit address - 1 - - - - - OA1EN - Own Address 1 enable - 15 - 1 - - OA1EN - read-write - - Disabled - Own address 1 disabled. The received slave address OA1 is NACKed - 0 - - - Enabled - Own address 1 enabled. The received slave address OA1 is ACKed - 1 - - - - - - - OAR2 - OAR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - OA2 - Interface address - 1 - 7 - - - 0 - 127 - - - - - OA2MSK - Own Address 2 masks - 8 - 3 - - OA2MSK - read-write - - NoMask - No mask - 0 - - - Mask1 - OA2[1] is masked and don’t care. Only OA2[7:2] are compared - 1 - - - Mask2 - OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared - 2 - - - Mask3 - OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared - 3 - - - Mask4 - OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared - 4 - - - Mask5 - OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared - 5 - - - Mask6 - OA2[6:1] are masked and don’t care. Only OA2[7] is compared. - 6 - - - Mask7 - OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged - 7 - - - - - OA2EN - Own Address 2 enable - 15 - 1 - - OA2EN - read-write - - Disabled - Own address 2 disabled. The received slave address OA2 is NACKed - 0 - - - Enabled - Own address 2 enabled. The received slave address OA2 is ACKed - 1 - - - - - - - TIMINGR - TIMINGR - Timing register - 0x10 - 0x20 - read-write - 0x00000000 - - - SCLL - SCL low period (master mode) - 0 - 8 - - - 0 - 255 - - - - - SCLH - SCL high period (master mode) - 8 - 8 - - - 0 - 255 - - - - - SDADEL - Data hold time - 16 - 4 - - - 0 - 15 - - - - - SCLDEL - Data setup time - 20 - 4 - - - 0 - 15 - - - - - PRESC - Timing prescaler - 28 - 4 - - - 0 - 15 - - - - - - - TIMEOUTR - TIMEOUTR - Status register 1 - 0x14 - 0x20 - read-write - 0x00000000 - - - TIMEOUTA - Bus timeout A - 0 - 12 - - - 0 - 4095 - - - - - TIDLE - Idle clock timeout detection - 12 - 1 - - TIDLE - read-write - - Disabled - TIMEOUTA is used to detect SCL low timeout - 0 - - - Enabled - TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) - 1 - - - - - TIMOUTEN - Clock timeout enable - 15 - 1 - - TIMOUTEN - read-write - - Disabled - SCL timeout detection is disabled - 0 - - - Enabled - SCL timeout detection is enabled - 1 - - - - - TIMEOUTB - Bus timeout B - 16 - 12 - - - 0 - 4095 - - - - - TEXTEN - Extended clock timeout enable - 31 - 1 - - TEXTEN - read-write - - Disabled - Extended clock timeout detection is disabled - 0 - - - Enabled - Extended clock timeout detection is enabled - 1 - - - - - - - ISR - ISR - Interrupt and Status register - 0x18 - 0x20 - 0x00000001 - - - ADDCODE - Address match code (Slave mode) - 17 - 7 - read-only - - - 0 - 127 - - - - - DIR - Transfer direction (Slave mode) - 16 - 1 - read-only - - DIR - read - - Write - Write transfer, slave enters receiver mode - 0 - - - Read - Read transfer, slave enters transmitter mode - 1 - - - - - BUSY - Bus busy - 15 - 1 - read-only - - BUSY - read - - NotBusy - No communication is in progress on the bus - 0 - - - Busy - A communication is in progress on the bus - 1 - - - - - ALERT - SMBus alert - 13 - 1 - read-only - - ALERT - read - - NoAlert - SMBA alert is not detected - 0 - - - Alert - SMBA alert event is detected on SMBA pin - 1 - - - - - TIMEOUT - Timeout or t_low detection flag - 12 - 1 - read-only - - TIMEOUT - read - - NoTimeout - No timeout occured - 0 - - - Timeout - Timeout occured - 1 - - - - - PECERR - PEC Error in reception - 11 - 1 - read-only - - PECERR - read - - Match - Received PEC does match with PEC register - 0 - - - NoMatch - Received PEC does not match with PEC register - 1 - - - - - OVR - Overrun/Underrun (slave mode) - 10 - 1 - read-only - - OVR - read - - NoOverrun - No overrun/underrun error occurs - 0 - - - Overrun - slave mode with NOSTRETCH=1, when an overrun/underrun error occurs - 1 - - - - - ARLO - Arbitration lost - 9 - 1 - read-only - - ARLO - read - - NotLost - No arbitration lost - 0 - - - Lost - Arbitration lost - 1 - - - - - BERR - Bus error - 8 - 1 - read-only - - BERR - read - - NoError - No bus error - 0 - - - Error - Misplaced Start and Stop condition is detected - 1 - - - - - TCR - Transfer Complete Reload - 7 - 1 - read-only - - TCR - read - - NotComplete - Transfer is not complete - 0 - - - Complete - NBYTES has been transfered - 1 - - - - - TC - Transfer Complete (master mode) - 6 - 1 - read-only - - TC - read - - NotComplete - Transfer is not complete - 0 - - - Complete - NBYTES has been transfered - 1 - - - - - STOPF - Stop detection flag - 5 - 1 - read-only - - STOPF - read - - NoStop - No Stop condition detected - 0 - - - Stop - Stop condition detected - 1 - - - - - NACKF - Not acknowledge received flag - 4 - 1 - read-only - - NACKF - read - - NoNack - No NACK has been received - 0 - - - Nack - NACK has been received - 1 - - - - - ADDR - Address matched (slave mode) - 3 - 1 - read-only - - ADDR - read - - NotMatch - Adress mismatched or not received - 0 - - - Match - Received slave address matched with one of the enabled slave addresses - 1 - - - - - RXNE - Receive data register not empty (receivers) - 2 - 1 - read-only - - RXNE - read - - Empty - The RXDR register is empty - 0 - - - NotEmpty - Received data is copied into the RXDR register, and is ready to be read - 1 - - - - - TXIS - Transmit interrupt status (transmitters) - 1 - 1 - read-write - oneToSet - - TXISR - read - - NotEmpty - The TXDR register is not empty - 0 - - - Empty - The TXDR register is empty and the data to be transmitted must be written in the TXDR register - 1 - - - - TXISW - write - - Trigger - Generate a TXIS event - 1 - - - - - TXE - Transmit data register empty (transmitters) - 0 - 1 - read-write - oneToSet - - TXER - read - - NotEmpty - TXDR register not empty - 0 - - - Empty - TXDR register empty - 1 - - - - TXEW - write - - Flush - Flush the transmit data register - 1 - - - - - - - ICR - ICR - Interrupt clear register - 0x1C - 0x20 - write-only - 0x00000000 - - - ALERTCF - Alert flag clear - 13 - 1 - - ALERTCF - write - - Clear - Clears the ALERT flag in ISR register - 1 - - - - - TIMOUTCF - Timeout detection flag clear - 12 - 1 - - TIMOUTCF - write - - Clear - Clears the TIMOUT flag in ISR register - 1 - - - - - PECCF - PEC Error flag clear - 11 - 1 - - PECCF - write - - Clear - Clears the PEC flag in ISR register - 1 - - - - - OVRCF - Overrun/Underrun flag clear - 10 - 1 - - OVRCF - write - - Clear - Clears the OVR flag in ISR register - 1 - - - - - ARLOCF - Arbitration lost flag clear - 9 - 1 - - ARLOCF - write - - Clear - Clears the ARLO flag in ISR register - 1 - - - - - BERRCF - Bus error flag clear - 8 - 1 - - BERRCF - write - - Clear - Clears the BERR flag in ISR register - 1 - - - - - STOPCF - Stop detection flag clear - 5 - 1 - - STOPCF - write - - Clear - Clears the STOP flag in ISR register - 1 - - - - - NACKCF - Not Acknowledge flag clear - 4 - 1 - - NACKCF - write - - Clear - Clears the NACK flag in ISR register - 1 - - - - - ADDRCF - Address Matched flag clear - 3 - 1 - - ADDRCF - write - - Clear - Clears the ADDR flag in ISR register - 1 - - - - - - - PECR - PECR - PEC register - 0x20 - 0x20 - read-only - 0x00000000 - - - PEC - Packet error checking register - 0 - 8 - - - 0 - 255 - - - - - - - RXDR - RXDR - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - RXDATA - 8-bit receive data - 0 - 8 - - - 0 - 255 - - - - - - - TXDR - TXDR - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - TXDATA - 8-bit transmit data - 0 - 8 - - - 0 - 255 - - - - - - - - - I2C2 - 0x40005800 - - I2C2_EV - I2C2 event interrupt - 33 - - - I2C2_ER - I2C2 error interrupt - 34 - - - - I2C3 - 0x40005C00 - - I2C3_EV - I2C3 event interrupt - 72 - - - I2C3_ER - I2C3 error interrupt - 73 - - - - I2C4 - 0x40006000 - - I2C4_EV - I2C4 event interrupt - 95 - - - I2C4_ER - I2C4 Error interrupt - 96 - - - - RTC - Real-time clock - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC_WKUP - RTC Tamper or TimeStamp /CSS on LSE through - EXTI line 19 interrupts - 3 - - - RTC_ALARM - RTC alarms through EXTI line 18 - interrupts - 41 - - - - TR - TR - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - PM - AM/PM notation - 22 - 1 - - PM - read-write - - AM - AM or 24-hour format - 0 - - - PM - PM - 1 - - - - - HT - Hour tens in BCD format - 20 - 2 - - - 0 - 3 - - - - - HU - Hour units in BCD format - 16 - 4 - - - 0 - 15 - - - - - MNT - Minute tens in BCD format - 12 - 3 - - - 0 - 7 - - - - - MNU - Minute units in BCD format - 8 - 4 - - - 0 - 15 - - - - - ST - Second tens in BCD format - 4 - 3 - - - 0 - 7 - - - - - SU - Second units in BCD format - 0 - 4 - - - 0 - 15 - - - - - - - DR - DR - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens in BCD format - 20 - 4 - - - 0 - 15 - - - - - YU - Year units in BCD format - 16 - 4 - - - 0 - 15 - - - - - WDU - Week day units - 13 - 3 - - - 1 - 7 - - - - - MT - Month tens in BCD format - 12 - 1 - - MT - read-write - - Zero - Month tens is 0 - 0 - - - One - Month tens is 1 - 1 - - - - - MU - Month units in BCD format - 8 - 4 - - - 0 - 15 - - - - - DT - Date tens in BCD format - 4 - 2 - - - 0 - 3 - - - - - DU - Date units in BCD format - 0 - 4 - - - 0 - 15 - - - - - - - CR - CR - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - WUCKSEL - Wakeup clock selection - 0 - 3 - - WUCKSEL - read-write - - Div16 - RTC/16 clock is selected - 0 - - - Div8 - RTC/8 clock is selected - 1 - - - Div4 - RTC/4 clock is selected - 2 - - - Div2 - RTC/2 clock is selected - 3 - - - ClockSpare - ck_spre (usually 1 Hz) clock is selected - 4 - - - ClockSpareWithOffset - ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - 6 - - - - - TSEDGE - Time-stamp event active edge - 3 - 1 - - TSEDGE - read-write - - RisingEdge - RTC_TS input rising edge generates a time-stamp event - 0 - - - FallingEdge - RTC_TS input falling edge generates a time-stamp event - 1 - - - - - REFCKON - Reference clock detection enable (50 or 60 Hz) - 4 - 1 - - REFCKON - read-write - - Disabled - RTC_REFIN detection disabled - 0 - - - Enabled - RTC_REFIN detection enabled - 1 - - - - - BYPSHAD - Bypass the shadow registers - 5 - 1 - - BYPSHAD - read-write - - ShadowReg - Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles - 0 - - - BypassShadowReg - Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters - 1 - - - - - FMT - Hour format - 6 - 1 - - FMT - read-write - - Twenty_Four_Hour - 24 hour/day format - 0 - - - AM_PM - AM/PM hour format - 1 - - - - - ALRAE - Alarm A enable - 8 - 1 - - ALRAE - read-write - - Disabled - Alarm A disabled - 0 - - - Enabled - Alarm A enabled - 1 - - - - - ALRBE - Alarm B enable - 9 - 1 - - ALRBE - read-write - - Disabled - Alarm B disabled - 0 - - - Enabled - Alarm B enabled - 1 - - - - - WUTE - Wakeup timer enable - 10 - 1 - - WUTE - read-write - - Disabled - Wakeup timer disabled - 0 - - - Enabled - Wakeup timer enabled - 1 - - - - - TSE - Time stamp enable - 11 - 1 - - TSE - read-write - - Disabled - Timestamp disabled - 0 - - - Enabled - Timestamp enabled - 1 - - - - - ALRAIE - Alarm A interrupt enable - 12 - 1 - - ALRAIE - read-write - - Disabled - Alarm A interrupt disabled - 0 - - - Enabled - Alarm A interrupt enabled - 1 - - - - - ALRBIE - Alarm B interrupt enable - 13 - 1 - - ALRBIE - read-write - - Disabled - Alarm B Interrupt disabled - 0 - - - Enabled - Alarm B Interrupt enabled - 1 - - - - - WUTIE - Wakeup timer interrupt enable - 14 - 1 - - WUTIE - read-write - - Disabled - Wakeup timer interrupt disabled - 0 - - - Enabled - Wakeup timer interrupt enabled - 1 - - - - - TSIE - Time-stamp interrupt enable - 15 - 1 - - TSIE - read-write - - Disabled - Time-stamp Interrupt disabled - 0 - - - Enabled - Time-stamp Interrupt enabled - 1 - - - - - ADD1H - Add 1 hour (summer time change) - 16 - 1 - - ADD1HW - write - - Add1 - Adds 1 hour to the current time. This can be used for summer time change outside initialization mode - 1 - - - - - SUB1H - Subtract 1 hour (winter time change) - 17 - 1 - - SUB1HW - write - - Sub1 - Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode - 1 - - - - - BKP - Backup - 18 - 1 - - BKP - read-write - - DST_Not_Changed - Daylight Saving Time change has not been performed - 0 - - - DST_Changed - Daylight Saving Time change has been performed - 1 - - - - - COSEL - Calibration output selection - 19 - 1 - - COSEL - read-write - - CalFreq_512Hz - Calibration output is 512 Hz (with default prescaler setting) - 0 - - - CalFreq_1Hz - Calibration output is 1 Hz (with default prescaler setting) - 1 - - - - - POL - Output polarity - 20 - 1 - - POL - read-write - - High - The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - 0 - - - Low - The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - 1 - - - - - OSEL - Output selection - 21 - 2 - - OSEL - read-write - - Disabled - Output disabled - 0 - - - AlarmA - Alarm A output enabled - 1 - - - AlarmB - Alarm B output enabled - 2 - - - Wakeup - Wakeup output enabled - 3 - - - - - COE - Calibration output enable - 23 - 1 - - COE - read-write - - Disabled - Calibration output disabled - 0 - - - Enabled - Calibration output enabled - 1 - - - - - ITSE - timestamp on internal event enable - 24 - 1 - - - - - ISR - ISR - initialization and status register - 0xC - 0x20 - 0x00000007 - - - ALRAWF - Alarm A write flag - 0 - 1 - read-only - - ALRAWFR - read - - UpdateNotAllowed - Alarm update not allowed - 0 - - - UpdateAllowed - Alarm update allowed - 1 - - - - - ALRBWF - Alarm B write flag - 1 - 1 - read-only - - - - WUTWF - Wakeup timer write flag - 2 - 1 - read-only - - WUTWFR - read - - UpdateNotAllowed - Wakeup timer configuration update not allowed - 0 - - - UpdateAllowed - Wakeup timer configuration update allowed - 1 - - - - - SHPF - Shift operation pending - 3 - 1 - read-write - - SHPFR - read - - NoShiftPending - No shift operation is pending - 0 - - - ShiftPending - A shift operation is pending - 1 - - - - - INITS - Initialization status flag - 4 - 1 - read-only - - INITSR - read - - NotInitalized - Calendar has not been initialized - 0 - - - Initalized - Calendar has been initialized - 1 - - - - - RSF - Registers synchronization flag - 5 - 1 - read-write - zeroToClear - - RSFR - read - - NotSynced - Calendar shadow registers not yet synchronized - 0 - - - Synced - Calendar shadow registers synchronized - 1 - - - - RSFW - write - - Clear - This flag is cleared by software by writing 0 - 0 - - - - - INITF - Initialization flag - 6 - 1 - read-only - - INITFR - read - - NotAllowed - Calendar registers update is not allowed - 0 - - - Allowed - Calendar registers update is allowed - 1 - - - - - INIT - Initialization mode - 7 - 1 - read-write - - INIT - read-write - - FreeRunningMode - Free running mode - 0 - - - InitMode - Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. - 1 - - - - - ALRAF - Alarm A flag - 8 - 1 - read-write - zeroToClear - - ALRAFR - read - - Match - This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - 1 - - - - ALRAFW - write - - Clear - This flag is cleared by software by writing 0 - 0 - - - - - ALRBF - Alarm B flag - 9 - 1 - read-write - zeroToClear - - ALRBFR - read - - Match - This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) - 1 - - - - ALRBFW - write - - Clear - This flag is cleared by software by writing 0 - 0 - - - - - WUTF - Wakeup timer flag - 10 - 1 - read-write - zeroToClear - - WUTFR - read - - Zero - This flag is set by hardware when the wakeup auto-reload counter reaches 0 - 1 - - - - WUTFW - write - - Clear - This flag is cleared by software by writing 0 - 0 - - - - - TSF - Time-stamp flag - 11 - 1 - read-write - zeroToClear - - TSFR - read - - TimestampEvent - This flag is set by hardware when a time-stamp event occurs - 1 - - - - TSFW - write - - Clear - This flag is cleared by software by writing 0 - 0 - - - - - TSOVF - Time-stamp overflow flag - 12 - 1 - read-write - zeroToClear - - TSOVFR - read - - Overflow - This flag is set by hardware when a time-stamp event occurs while TSF is already set - 1 - - - - TSOVFW - write - - Clear - This flag is cleared by software by writing 0 - 0 - - - - - TAMP1F - Tamper detection flag - 13 - 1 - read-write - zeroToClear - - TAMP1FR - read - - Tampered - This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - 1 - - - - TAMP1FW - write - - Clear - Flag cleared by software writing 0 - 0 - - - - - TAMP2F - RTC_TAMP2 detection flag - 14 - 1 - read-write - zeroToClear - - read - - - write - - - - TAMP3F - RTC_TAMP3 detection flag - 15 - 1 - read-write - zeroToClear - - read - - - write - - - - RECALPF - Recalibration pending Flag - 16 - 1 - read-only - - RECALPFR - read - - Pending - The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - 1 - - - - - - - PRER - PRER - prescaler register - 0x10 - 0x20 - read-write - 0x007F00FF - - - PREDIV_A - Asynchronous prescaler factor - 16 - 7 - - - 0 - 127 - - - - - PREDIV_S - Synchronous prescaler factor - 0 - 15 - - - 0 - 32767 - - - - - - - WUTR - WUTR - wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - WUT - Wakeup auto-reload value bits - 0 - 16 - - - 0 - 65535 - - - - - - - 2 - 0x4 - A,B - ALRM%sR - ALRMAR - Alarm register - 0x1C - 0x20 - read-write - 0x00000000 - - - MSK4 - Alarm date mask - 31 - 1 - - - - WDSEL - Week day selection - 30 - 1 - - WDSEL - read-write - - DateUnits - DU[3:0] represents the date units - 0 - - - WeekDay - DU[3:0] represents the week day. DT[1:0] is don’t care. - 1 - - - - - DT - Date tens in BCD format - 28 - 2 - - - 0 - 3 - - - - - DU - Date units or day in BCD format - 24 - 4 - - - 0 - 15 - - - - - MSK3 - Alarm hours mask - 23 - 1 - - - - PM - AM/PM notation - 22 - 1 - - PM - read-write - - AM - AM or 24-hour format - 0 - - - PM - PM - 1 - - - - - HT - Hour tens in BCD format - 20 - 2 - - - 0 - 3 - - - - - HU - Hour units in BCD format - 16 - 4 - - - 0 - 15 - - - - - MSK2 - Alarm minutes mask - 15 - 1 - - - - MNT - Minute tens in BCD format - 12 - 3 - - - 0 - 7 - - - - - MNU - Minute units in BCD format - 8 - 4 - - - 0 - 15 - - - - - MSK1 - Alarm seconds mask - 7 - 1 - - MSK1 - read-write - - Mask - Alarm set if the date/day match - 0 - - - NotMask - Date/day don’t care in Alarm comparison - 1 - - - - - ST - Second tens in BCD format - 4 - 3 - - - 0 - 7 - - - - - SU - Second units in BCD format - 0 - 4 - - - 0 - 15 - - - - - - - WPR - WPR - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - KEY - Write protection key - 0 - 8 - - - 0 - 255 - - - - - - - SSR - SSR - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SS - Sub second value - 0 - 16 - - - 0 - 65535 - - - - - - - SHIFTR - SHIFTR - shift control register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add one second - 31 - 1 - - ADD1SW - write - - Add1 - Add one second to the clock/calendar - 1 - - - - - SUBFS - Subtract a fraction of a second - 0 - 15 - - - 0 - 32767 - - - - - - - TSTR - TSTR - time stamp time register - 0x30 - - - TSDR - TSDR - time stamp date register - 0x34 - - - TSSSR - TSSSR - timestamp sub second register - 0x38 - - - CALR - CALR - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - CALP - Increase frequency of RTC by 488.5 ppm - 15 - 1 - - CALP - read-write - - NoChange - No RTCCLK pulses are added - 0 - - - IncreaseFreq - One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - 1 - - - - - CALW8 - Use an 8-second calibration cycle period - 14 - 1 - - CALW8 - read-write - - Eight_Second - When CALW8 is set to β€˜1’, the 8-second calibration cycle period is selected - 1 - - - - - CALW16 - Use a 16-second calibration cycle period - 13 - 1 - - CALW16 - read-write - - Sixteen_Second - When CALW16 is set to β€˜1’, the 16-second calibration cycle period is selected.This bit must not be set to β€˜1’ if CALW8=1 - 1 - - - - - CALM - Calibration minus - 0 - 9 - - - 0 - 511 - - - - - - - TAMPCR - TAMPCR - tamper configuration register - 0x40 - 0x20 - read-write - 0x00000000 - - - TAMP1E - Tamper 1 detection enable - 0 - 1 - - - TAMP1TRG - Active level for tamper 1 - 1 - 1 - - - TAMPIE - Tamper interrupt enable - 2 - 1 - - - TAMP2E - Tamper 2 detection enable - 3 - 1 - - - TAMP2TRG - Active level for tamper 2 - 4 - 1 - - - TAMP3E - Tamper 3 detection enable - 5 - 1 - - - TAMP3TRG - Active level for tamper 3 - 6 - 1 - - - TAMPTS - Activate timestamp on tamper detection event - 7 - 1 - - - TAMPFREQ - Tamper sampling frequency - 8 - 3 - - - TAMPFLT - Tamper filter count - 11 - 2 - - - TAMPPRCH - Tamper precharge duration - 13 - 2 - - - TAMPPUDIS - TAMPER pull-up disable - 15 - 1 - - - TAMP1IE - Tamper 1 interrupt enable - 16 - 1 - - - TAMP1NOERASE - Tamper 1 no erase - 17 - 1 - - - TAMP1MF - Tamper 1 mask flag - 18 - 1 - - - TAMP2IE - Tamper 2 interrupt enable - 19 - 1 - - - TAMP2NOERASE - Tamper 2 no erase - 20 - 1 - - - TAMP2MF - Tamper 2 mask flag - 21 - 1 - - - TAMP3IE - Tamper 3 interrupt enable - 22 - 1 - - - TAMP3NOERASE - Tamper 3 no erase - 23 - 1 - - - TAMP3MF - Tamper 3 mask flag - 24 - 1 - - - - - 2 - 0x4 - A,B - ALRM%sSSR - ALRMASSR - Alarm sub-second register - 0x44 - 0x20 - read-write - 0x00000000 - - - MASKSS - Mask the most-significant bits starting at this bit - 24 - 4 - - - 0 - 15 - - - - - SS - Sub seconds value - 0 - 15 - - - 0 - 32767 - - - - - - - OR - OR - option register - 0x4C - 0x20 - read-write - 0x00000000 - - - RTC_ALARM_TYPE - RTC_ALARM on PC13 output type - 0 - 1 - - - RTC_OUT_RMP - RTC_OUT remap - 1 - 1 - - - - - 32 - 0x4 - 0-31 - BKP%sR - BKP0R - backup register - 0x50 - 0x20 - read-write - 0x00000000 - - - BKP - BKP - 0 - 32 - - - 0 - 4294967295 - - - - - - - - - USART6 - 0x40011400 - - USART6 - USART6 global interrupt - 71 - - - - USART1 - Universal synchronous asynchronous receiver transmitter - USART - 0x40011000 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - USART6 - USART6 global interrupt - 71 - - - UART4 - UART4 global interrupt - 52 - - - UART7 - UART7 global interrupt - 82 - - - - CR1 - CR1 - Control register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - M1 - Word length - 28 - 1 - - M1 - read-write - - M0 - Use M0 to set the data bits - 0 - - - Bit7 - 1 start bit, 7 data bits, n stop bits - 1 - - - - - EOBIE - End of Block interrupt enable - 27 - 1 - - EOBIE - read-write - - Disabled - Interrupt is inhibited - 0 - - - Enabled - A USART interrupt is generated when the EOBF flag is set in the ISR register - 1 - - - - - RTOIE - Receiver timeout interrupt enable - 26 - 1 - - RTOIE - read-write - - Disabled - Interrupt is inhibited - 0 - - - Enabled - An USART interrupt is generated when the RTOF bit is set in the ISR register - 1 - - - - - OVER8 - Oversampling mode - 15 - 1 - - OVER8 - read-write - - Oversampling16 - Oversampling by 16 - 0 - - - Oversampling8 - Oversampling by 8 - 1 - - - - - CMIE - Character match interrupt enable - 14 - 1 - - CMIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is generated when the CMF bit is set in the ISR register - 1 - - - - - MME - Mute mode enable - 13 - 1 - - MME - read-write - - Disabled - Receiver in active mode permanently - 0 - - - Enabled - Receiver can switch between mute mode and active mode - 1 - - - - - M0 - Word length - 12 - 1 - - M0 - read-write - - Bit8 - 1 start bit, 8 data bits, n stop bits - 0 - - - Bit9 - 1 start bit, 9 data bits, n stop bits - 1 - - - - - WAKE - Receiver wakeup method - 11 - 1 - - WAKE - read-write - - Idle - Idle line - 0 - - - Address - Address mask - 1 - - - - - PCE - Parity control enable - 10 - 1 - - PCE - read-write - - Disabled - Parity control disabled - 0 - - - Enabled - Parity control enabled - 1 - - - - - PS - Parity selection - 9 - 1 - - PS - read-write - - Even - Even parity - 0 - - - Odd - Odd parity - 1 - - - - - PEIE - PE interrupt enable - 8 - 1 - - PEIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is generated whenever PE=1 in the ISR register - 1 - - - - - TXEIE - interrupt enable - 7 - 1 - - TXEIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is generated whenever TXE=1 in the ISR register - 1 - - - - - TCIE - Transmission complete interrupt enable - 6 - 1 - - TCIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is generated whenever TC=1 in the ISR register - 1 - - - - - RXNEIE - RXNE interrupt enable - 5 - 1 - - RXNEIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register - 1 - - - - - IDLEIE - IDLE interrupt enable - 4 - 1 - - IDLEIE - read-write - - Disabled - Interrupt is disabled - 0 - - - Enabled - Interrupt is generated whenever IDLE=1 in the ISR register - 1 - - - - - TE - Transmitter enable - 3 - 1 - - TE - read-write - - Disabled - Transmitter is disabled - 0 - - - Enabled - Transmitter is enabled - 1 - - - - - RE - Receiver enable - 2 - 1 - - RE - read-write - - Disabled - Receiver is disabled - 0 - - - Enabled - Receiver is enabled - 1 - - - - - UESM - USART enable in Stop mode - 1 - 1 - - UESM - read-write - - Disabled - USART not able to wake up the MCU from Stop mode - 0 - - - Enabled - USART able to wake up the MCU from Stop mode - 1 - - - - - UE - USART enable - 0 - 1 - - UE - read-write - - Disabled - UART is disabled - 0 - - - Enabled - UART is enabled - 1 - - - - - DEAT - Driver Enable assertion time - 21 - 5 - - - 0 - 31 - - - - - DEDT - Driver Enable de-assertion time - 16 - 5 - - - 0 - 31 - - - - - - - CR2 - CR2 - Control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - RTOEN - Receiver timeout enable - 23 - 1 - - RTOEN - read-write - - Disabled - Receiver timeout feature disabled - 0 - - - Enabled - Receiver timeout feature enabled - 1 - - - - - ABREN - Auto baud rate enable - 20 - 1 - - ABREN - read-write - - Disabled - Auto baud rate detection is disabled - 0 - - - Enabled - Auto baud rate detection is enabled - 1 - - - - - MSBFIRST - Most significant bit first - 19 - 1 - - MSBFIRST - read-write - - LSB - data is transmitted/received with data bit 0 first, following the start bit - 0 - - - MSB - data is transmitted/received with MSB (bit 7/8/9) first, following the start bit - 1 - - - - - DATAINV - Binary data inversion - 18 - 1 - - DATAINV - read-write - - Positive - Logical data from the data register are send/received in positive/direct logic - 0 - - - Negative - Logical data from the data register are send/received in negative/inverse logic - 1 - - - - - TXINV - TX pin active level inversion - 17 - 1 - - TXINV - read-write - - Standard - TX pin signal works using the standard logic levels - 0 - - - Inverted - TX pin signal values are inverted - 1 - - - - - RXINV - RX pin active level inversion - 16 - 1 - - RXINV - read-write - - Standard - RX pin signal works using the standard logic levels - 0 - - - Inverted - RX pin signal values are inverted - 1 - - - - - SWAP - Swap TX/RX pins - 15 - 1 - - SWAP - read-write - - Standard - TX/RX pins are used as defined in standard pinout - 0 - - - Swapped - The TX and RX pins functions are swapped - 1 - - - - - LINEN - LIN mode enable - 14 - 1 - - LINEN - read-write - - Disabled - LIN mode disabled - 0 - - - Enabled - LIN mode enabled - 1 - - - - - STOP - STOP bits - 12 - 2 - - STOP - read-write - - Stop1 - 1 stop bit - 0 - - - Stop0p5 - 0.5 stop bit - 1 - - - Stop2 - 2 stop bit - 2 - - - Stop1p5 - 1.5 stop bit - 3 - - - - - CLKEN - Clock enable - 11 - 1 - - CLKEN - read-write - - Disabled - CK pin disabled - 0 - - - Enabled - CK pin enabled - 1 - - - - - CPOL - Clock polarity - 10 - 1 - - CPOL - read-write - - Low - Steady low value on CK pin outside transmission window - 0 - - - High - Steady high value on CK pin outside transmission window - 1 - - - - - CPHA - Clock phase - 9 - 1 - - CPHA - read-write - - First - The first clock transition is the first data capture edge - 0 - - - Second - The second clock transition is the first data capture edge - 1 - - - - - LBCL - Last bit clock pulse - 8 - 1 - - LBCL - read-write - - NotOutput - The clock pulse of the last data bit is not output to the CK pin - 0 - - - Output - The clock pulse of the last data bit is output to the CK pin - 1 - - - - - LBDIE - LIN break detection interrupt enable - 6 - 1 - - LBDIE - read-write - - Disabled - Interrupt is inhibited - 0 - - - Enabled - An interrupt is generated whenever LBDF=1 in the ISR register - 1 - - - - - LBDL - LIN break detection length - 5 - 1 - - LBDL - read-write - - Bit10 - 10-bit break detection - 0 - - - Bit11 - 11-bit break detection - 1 - - - - - ADDM7 - 7-bit Address Detection/4-bit Address Detection - 4 - 1 - - ADDM7 - read-write - - Bit4 - 4-bit address detection - 0 - - - Bit7 - 7-bit address detection - 1 - - - - - ABRMOD - Auto baud rate mode - 21 - 2 - - ABRMOD - read-write - - Start - Measurement of the start bit is used to detect the baud rate - 0 - - - Edge - Falling edge to falling edge measurement - 1 - - - Frame7F - 0x7F frame detection - 2 - - - Frame55 - 0x55 frame detection - 3 - - - - - ADD - Address of the USART node - 24 - 8 - - - 0 - 255 - - - - - - - CR3 - CR3 - Control register 3 - 0x8 - 0x20 - read-write - 0x00000000 - - - WUFIE - Wakeup from Stop mode interrupt enable - 22 - 1 - - WUFIE - read-write - - Disabled - Interrupt is inhibited - 0 - - - Enabled - An USART interrupt is generated whenever WUF=1 in the ISR register - 1 - - - - - WUS - Wakeup from Stop mode interrupt flag selection - 20 - 2 - - WUS - read-write - - Address - WUF active on address match - 0 - - - Start - WuF active on Start bit detection - 2 - - - RXNE - WUF active on RXNE - 3 - - - - - SCARCNT - Smartcard auto-retry count - 17 - 3 - - - 0 - 7 - - - - - DEP - Driver enable polarity selection - 15 - 1 - - DEP - read-write - - High - DE signal is active high - 0 - - - Low - DE signal is active low - 1 - - - - - DEM - Driver enable mode - 14 - 1 - - DEM - read-write - - Disabled - DE function is disabled - 0 - - - Enabled - The DE signal is output on the RTS pin - 1 - - - - - DDRE - DMA Disable on Reception Error - 13 - 1 - - DDRE - read-write - - NotDisabled - DMA is not disabled in case of reception error - 0 - - - Disabled - DMA is disabled following a reception error - 1 - - - - - OVRDIS - Overrun Disable - 12 - 1 - - OVRDIS - read-write - - Enabled - Overrun Error Flag, ORE, is set when received data is not read before receiving new data - 0 - - - Disabled - Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register - 1 - - - - - ONEBIT - One sample bit method enable - 11 - 1 - - ONEBIT - read-write - - Sample3 - Three sample bit method - 0 - - - Sample1 - One sample bit method - 1 - - - - - CTSIE - CTS interrupt enable - 10 - 1 - - CTSIE - read-write - - Disabled - Interrupt is inhibited - 0 - - - Enabled - An interrupt is generated whenever CTSIF=1 in the ISR register - 1 - - - - - CTSE - CTS enable - 9 - 1 - - CTSE - read-write - - Disabled - CTS hardware flow control disabled - 0 - - - Enabled - CTS mode enabled, data is only transmitted when the CTS input is asserted - 1 - - - - - RTSE - RTS enable - 8 - 1 - - RTSE - read-write - - Disabled - RTS hardware flow control disabled - 0 - - - Enabled - RTS output enabled, data is only requested when there is space in the receive buffer - 1 - - - - - DMAT - DMA enable transmitter - 7 - 1 - - DMAT - read-write - - Disabled - DMA mode is disabled for transmission - 0 - - - Enabled - DMA mode is enabled for transmission - 1 - - - - - DMAR - DMA enable receiver - 6 - 1 - - DMAR - read-write - - Disabled - DMA mode is disabled for reception - 0 - - - Enabled - DMA mode is enabled for reception - 1 - - - - - SCEN - Smartcard mode enable - 5 - 1 - - SCEN - read-write - - Disabled - Smartcard Mode disabled - 0 - - - Enabled - Smartcard Mode enabled - 1 - - - - - NACK - Smartcard NACK enable - 4 - 1 - - NACK - read-write - - Disabled - NACK transmission in case of parity error is disabled - 0 - - - Enabled - NACK transmission during parity error is enabled - 1 - - - - - HDSEL - Half-duplex selection - 3 - 1 - - HDSEL - read-write - - NotSelected - Half duplex mode is not selected - 0 - - - Selected - Half duplex mode is selected - 1 - - - - - IRLP - Ir low-power - 2 - 1 - - IRLP - read-write - - Normal - Normal mode - 0 - - - LowPower - Low-power mode - 1 - - - - - IREN - Ir mode enable - 1 - 1 - - IREN - read-write - - Disabled - IrDA disabled - 0 - - - Enabled - IrDA enabled - 1 - - - - - EIE - Error interrupt enable - 0 - 1 - - EIE - read-write - - Disabled - Interrupt is inhibited - 0 - - - Enabled - An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register - 1 - - - - - - - BRR - BRR - Baud rate register - 0xC - 0x20 - read-write - 0x00000000 - - - BRR - DIV_Mantissa - 0 - 16 - - - 0 - 65535 - - - - - - - GTPR - GTPR - Guard time and prescaler register - 0x10 - 0x20 - read-write - 0x00000000 - - - GT - Guard time value - 8 - 8 - - - 0 - 255 - - - - - PSC - Prescaler value - 0 - 8 - - - 0 - 255 - - - - - - - RTOR - RTOR - Receiver timeout register - 0x14 - 0x20 - read-write - 0x00000000 - - - BLEN - Block Length - 24 - 8 - - - 0 - 255 - - - - - RTO - Receiver timeout value - 0 - 24 - - - 0 - 16777215 - - - - - - - RQR - RQR - Request register - 0x18 - 0x20 - write-only - 0x00000000 - - - TXFRQ - Transmit data flush request - 4 - 1 - - TXFRQ - write - - Discard - Set the TXE flags. This allows to discard the transmit data - 1 - - - - - RXFRQ - Receive data flush request - 3 - 1 - - RXFRQ - write - - Discard - clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition - 1 - - - - - MMRQ - Mute mode request - 2 - 1 - - MMRQ - write - - Mute - Puts the USART in mute mode and sets the RWU flag - 1 - - - - - SBKRQ - Send break request - 1 - 1 - - SBKRQ - write - - Break - sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available - 1 - - - - - ABRRQ - Auto baud rate request - 0 - 1 - - ABRRQ - write - - Request - resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame - 1 - - - - - - - ISR - ISR - Interrupt & status register - 0x1C - 0x20 - read-only - 0x000000C0 - - - REACK - REACK - 22 - 1 - - - TEACK - TEACK - 21 - 1 - - - WUF - WUF - 20 - 1 - - - RWU - RWU - 19 - 1 - - - SBKF - SBKF - 18 - 1 - - - CMF - CMF - 17 - 1 - - - BUSY - BUSY - 16 - 1 - - - ABRF - ABRF - 15 - 1 - - - ABRE - ABRE - 14 - 1 - - - EOBF - EOBF - 12 - 1 - - - RTOF - RTOF - 11 - 1 - - - CTS - CTS - 10 - 1 - - - CTSIF - CTSIF - 9 - 1 - - - LBDF - LBDF - 8 - 1 - - - TXE - TXE - 7 - 1 - - - TC - TC - 6 - 1 - - - RXNE - RXNE - 5 - 1 - - - IDLE - IDLE - 4 - 1 - - - ORE - ORE - 3 - 1 - - - NF - NF - 2 - 1 - - - FE - FE - 1 - 1 - - - PE - PE - 0 - 1 - - - - - ICR - ICR - Interrupt flag clear register - 0x20 - 0x20 - write-only - 0x00000000 - - - WUCF - Wakeup from Stop mode clear flag - 20 - 1 - - WUCF - write - - Clear - Clears the WUF flag in the ISR register - 1 - - - - - CMCF - Character match clear flag - 17 - 1 - - CMCF - write - - Clear - Clears the CMF flag in the ISR register - 1 - - - - - EOBCF - End of block clear flag - 12 - 1 - - EOBCF - write - - Clear - Clears the EOBF flag in the ISR register - 1 - - - - - RTOCF - Receiver timeout clear flag - 11 - 1 - - RTOCF - write - - Clear - Clears the RTOF flag in the ISR register - 1 - - - - - CTSCF - CTS clear flag - 9 - 1 - - CTSCF - write - - Clear - Clears the CTSIF flag in the ISR register - 1 - - - - - LBDCF - LIN break detection clear flag - 8 - 1 - - LBDCF - write - - Clear - Clears the LBDF flag in the ISR register - 1 - - - - - TCCF - Transmission complete clear flag - 6 - 1 - - TCCF - write - - Clear - Clears the TC flag in the ISR register - 1 - - - - - IDLECF - Idle line detected clear flag - 4 - 1 - - IDLECF - write - - Clear - Clears the IDLE flag in the ISR register - 1 - - - - - ORECF - Overrun error clear flag - 3 - 1 - - ORECF - write - - Clear - Clears the ORE flag in the ISR register - 1 - - - - - NCF - Noise detected clear flag - 2 - 1 - - NCF - write - - Clear - Clears the NF flag in the ISR register - 1 - - - - - FECF - Framing error clear flag - 1 - 1 - - FECF - write - - Clear - Clears the FE flag in the ISR register - 1 - - - - - PECF - Parity error clear flag - 0 - 1 - - PECF - write - - Clear - Clears the PE flag in the ISR register - 1 - - - - - - - RDR - RDR - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - RDR - Receive data value - 0 - 9 - - - 0 - 511 - - - - - - - TDR - TDR - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - TDR - Transmit data value - 0 - 9 - - - 0 - 511 - - - - - - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - UART5 - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - UART4 - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART8 - 0x40007C00 - - UART8 - UART 8 global interrupt - 83 - - - - UART7 - 0x40007800 - - UART7 - UART7 global interrupt - 82 - - - - OTG_FS_GLOBAL - USB on the go full speed - USB_OTG_FS - 0x50000000 - - 0x0 - 0x400 - registers - - - - GOTGCTL - GOTGCTL - OTG_FS control and status register (OTG_FS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - SRQSCS - Session request success - 0 - 1 - read-only - - - SRQ - Session request - 1 - 1 - read-write - - - HNGSCS - Host negotiation success - 8 - 1 - read-only - - - HNPRQ - HNP request - 9 - 1 - read-write - - - HSHNPEN - Host set HNP enable - 10 - 1 - read-write - - - DHNPEN - Device HNP enabled - 11 - 1 - read-write - - - CIDSTS - Connector ID status - 16 - 1 - read-only - - - DBCT - Long/short debounce time - 17 - 1 - read-only - - - ASVLD - A-session valid - 18 - 1 - read-only - - - BSVLD - B-session valid - 19 - 1 - read-only - - - VBVALOEN - VBUS valid override enable - 2 - 1 - read-write - - - VBVALOVAL - VBUS valid override value - 3 - 1 - read-write - - - AVALOEN - A-peripheral session valid override enable - 4 - 1 - read-write - - - AVALOVAL - A-peripheral session valid override value - 5 - 1 - read-write - - - BVALOEN - B-peripheral session valid override enable - 6 - 1 - read-write - - - BVALOVAL - B-peripheral session valid override value - 7 - 1 - read-write - - - EHEN - Embedded host enable - 12 - 1 - read-write - - - OTGVER - OTG version - 20 - 1 - read-write - - - CURMOD - Current mode of operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTG_FS interrupt register (OTG_FS_GOTGINT) - 0x4 - 0x20 - read-write - 0x00000000 - - - SEDET - Session end detected - 2 - 1 - - - SRSSCHG - Session request success status change - 8 - 1 - - - HNSSCHG - Host negotiation success status change - 9 - 1 - - - HNGDET - Host negotiation detected - 17 - 1 - - - ADTOCHG - A-device timeout change - 18 - 1 - - - DBCDNE - Debounce done - 19 - 1 - - - IDCHNG - ID input pin changed - 20 - 1 - - - - - GAHBCFG - GAHBCFG - OTG_FS AHB configuration register (OTG_FS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GINT - Global interrupt mask - 0 - 1 - - - TXFELVL - TxFIFO empty level - 7 - 1 - - - PTXFELVL - Periodic TxFIFO empty level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - OTG_FS USB configuration register (OTG_FS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOCAL - FS timeout calibration - 0 - 3 - read-write - - - PHYSEL - Full Speed serial transceiver select - 6 - 1 - write-only - - - SRPCAP - SRP-capable - 8 - 1 - read-write - - - HNPCAP - HNP-capable - 9 - 1 - read-write - - - TRDT - USB turnaround time - 10 - 4 - read-write - - - FHMOD - Force host mode - 29 - 1 - read-write - - - FDMOD - Force device mode - 30 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTG_FS reset register (OTG_FS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSRST - Core soft reset - 0 - 1 - read-write - - - HSRST - HCLK soft reset - 1 - 1 - read-write - - - FCRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDL - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTG_FS core interrupt register (OTG_FS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CMOD - Current mode of operation - 0 - 1 - read-only - - - MMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFE - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINAKEFF - Global IN non-periodic NAK effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ESUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDNE - Enumeration done - 13 - 1 - read-write - - - ISOODRP - Isochronous OUT packet dropped interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame interrupt - 15 - 1 - read-write - - - IEPINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPINT - OUT endpoint interrupt - 19 - 1 - read-only - - - IISOIXFR - Incomplete isochronous IN transfer - 20 - 1 - read-write - - - IPXFR_INCOMPISOOUT - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) - 21 - 1 - read-write - - - HPRTINT - Host port interrupt - 24 - 1 - read-only - - - HCINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFE - Periodic TxFIFO empty - 26 - 1 - read-only - - - CIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCINT - Disconnect detected interrupt - 29 - 1 - read-write - - - SRQINT - Session request/new session detected interrupt - 30 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected interrupt - 31 - 1 - read-write - - - RSTDET - Reset detected interrupt - 23 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MMISM - Mode mismatch interrupt mask - 1 - 1 - read-write - - - OTGINT - OTG interrupt mask - 2 - 1 - read-write - - - SOFM - Start of frame mask - 3 - 1 - read-write - - - RXFLVLM - Receive FIFO non-empty mask - 4 - 1 - read-write - - - NPTXFEM - Non-periodic TxFIFO empty mask - 5 - 1 - read-write - - - GINAKEFFM - Global non-periodic IN NAK effective mask - 6 - 1 - read-write - - - GONAKEFFM - Global OUT NAK effective mask - 7 - 1 - read-write - - - ESUSPM - Early suspend mask - 10 - 1 - read-write - - - USBSUSPM - USB suspend mask - 11 - 1 - read-write - - - USBRST - USB reset mask - 12 - 1 - read-write - - - ENUMDNEM - Enumeration done mask - 13 - 1 - read-write - - - ISOODRPM - Isochronous OUT packet dropped interrupt mask - 14 - 1 - read-write - - - EOPFM - End of periodic frame interrupt mask - 15 - 1 - read-write - - - IEPINT - IN endpoints interrupt mask - 18 - 1 - read-write - - - OEPINT - OUT endpoints interrupt mask - 19 - 1 - read-write - - - IISOIXFRM - Incomplete isochronous IN transfer mask - 20 - 1 - read-write - - - IPXFRM_IISOOXFRM - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) - 21 - 1 - read-write - - - PRTIM - Host port interrupt mask - 24 - 1 - read-write - - - HCIM - Host channels interrupt mask - 25 - 1 - read-write - - - PTXFEM - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CIDSCHGM - Connector ID status change mask - 28 - 1 - read-write - - - DISCINT - Disconnect detected interrupt mask - 29 - 1 - read-write - - - SRQIM - Session request/new session detected interrupt mask - 30 - 1 - read-write - - - WUIM - Resume/remote wakeup detected interrupt mask - 31 - 1 - read-write - - - RSTDETM - Reset detected interrupt mask - 23 - 1 - read-write - - - LPMIN - LPM interrupt mask - 27 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTG_FS Receive status debug read(Device mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FRMNUM - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTG_FS Receive status debug read(Host mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - STSPHST - Status phase start - 27 - 1 - - - - - GRXFSIZ - GRXFSIZ - OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFD - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0_Device - OTG_FS Endpoint 0 Transmit FIFO size - 0x28 - 0x20 - read-write - 0x00000200 - - - TX0FSA - Endpoint 0 transmit RAM start address - 0 - 16 - - - TX0FD - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - HNPTXFSIZ_Host - HNPTXFSIZ_Host - OTG_FS Host non-periodic transmit FIFO size register - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSA - Non-periodic transmit RAM start address - 0 - 16 - - - NPTXFD - Non-periodic TxFIFO depth - 16 - 16 - - - - - HNPTXSTS - HNPTXSTS - OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSAV - Non-periodic TxFIFO space available - 0 - 16 - - - NPTQXSAV - Non-periodic transmit request queue space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request queue - 24 - 7 - - - - - GCCFG - GCCFG - OTG_FS general core configuration register (OTG_FS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDWN - Power down - 16 - 1 - - - BCDEN - Battery charging detector (BCD) enable - 17 - 1 - - - DCDEN - Data contact detection (DCD) mode enable - 18 - 1 - - - PDEN - Primary detection (PD) mode enable - 19 - 1 - - - SDEN - Secondary detection (SD) mode enable - 20 - 1 - - - VBDEN - USB VBUS detection enable - 21 - 1 - - - DCDET - Data contact detection (DCD) status - 0 - 1 - - - PDET - Primary detection (PD) status - 1 - 1 - - - SDET - Secondary detection (SD) status - 2 - 1 - - - PS2DET - DM pull-up detection status - 3 - 1 - - - - - CID - CID - core ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - PRODUCT_ID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXSA - Host periodic TxFIFO start address - 0 - 16 - - - PTXFSIZ - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXSA - IN endpoint FIFO2 transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXSA - IN endpoint FIFO3 transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXSA - IN endpoint FIFO4 transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - GRXSTSP_Device - GRXSTSP_Device - OTG status read and pop register (Device mode) - 0x20 - 0x20 - read-only - 0x02000400 - - - EPNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FRMNUM - Frame number - 21 - 4 - - - - - GRXSTSP_Host - GRXSTSP_Host - OTG status read and pop register (Host mode) - GRXSTSP_Device - 0x20 - 0x20 - read-only - 0x02000400 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - STSPHST - Status phase start - 27 - 1 - - - - - GI2CCTL - GI2CCTL - OTG I2C access register - 0x30 - 0x20 - read-write - 0x02000400 - - - RWDATA - I2C Read/Write Data - 0 - 8 - - - REGADDR - I2C Register Address - 8 - 8 - - - ADDR - I2C Address - 16 - 7 - - - I2CEN - I2C Enable - 23 - 1 - - - ACK - I2C ACK - 24 - 1 - - - I2CDEVADR - I2C Device Address - 26 - 2 - - - I2CDATSE0 - I2C DatSe0 USB mode - 28 - 1 - - - RW - Read/Write Indicator - 30 - 1 - - - BSYDNE - I2C Busy/Done - 31 - 1 - - - - - GPWRDN - GPWRDN - OTG power down register - 0x58 - 0x20 - read-write - 0x02000400 - - - ADPMEN - ADP module enable - 0 - 1 - - - ADPIF - ADP interrupt flag - 23 - 1 - - - - - GADPCTL - GADPCTL - OTG ADP timer, control and status register - 0x60 - 0x20 - 0x02000400 - - - PRBDSCHG - Probe discharge - 0 - 2 - read-write - - - PRBDELTA - Probe delta - 2 - 2 - read-write - - - PRBPER - Probe period - 4 - 2 - read-write - - - RTIM - Ramp time - 6 - 11 - read-only - - - ENAPRB - Enable probe - 17 - 1 - read-write - - - ENASNS - Enable sense - 18 - 1 - read-write - - - ADPRST - ADP reset - 19 - 1 - read-only - - - ADPEN - ADP enable - 20 - 1 - read-write - - - ADPPRBIF - ADP probe interrupt flag - 21 - 1 - read-write - - - ADPSNSIF - ADP sense interrupt flag - 22 - 1 - read-write - - - ADPTOIF - ADP timeout interrupt flag - 23 - 1 - read-write - - - ADPPRBIM - ADP probe interrupt mask - 24 - 1 - read-write - - - ADPSNSIM - ADP sense interrupt mask - 25 - 1 - read-write - - - ADPTOIM - ADP timeout interrupt mask - 26 - 1 - read-write - - - AR - Access request - 27 - 2 - read-write - - - - - DIEPTXF4 - DIEPTXF4 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXSA - IN endpoint FIFOx transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint Tx FIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXSA - IN endpoint FIFOx transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint Tx FIFO depth - 16 - 16 - - - - - GLPMCFG - GLPMCFG - OTG core LPM configuration register - 0x54 - 0x20 - 0x00000000 - - - LPMEN - LPM support enable - 0 - 1 - read-write - - - LPMACK - LPM token acknowledge enable - 1 - 1 - read-write - - - BESL - Best effort service latency - 2 - 4 - read-write - - - REMWAKE - bRemoteWake value - 6 - 1 - read-write - - - L1SSEN - L1 Shallow Sleep enable - 7 - 1 - read-write - - - BESLTHRS - BESL threshold - 8 - 4 - read-write - - - L1DSEN - L1 deep sleep enable - 12 - 1 - read-write - - - LPMRST - LPM response - 13 - 2 - read-only - - - SLPSTS - Port sleep status - 15 - 1 - read-only - - - L1RSMOK - Sleep State Resume OK - 16 - 1 - read-only - - - LPMCHIDX - LPM Channel Index - 17 - 4 - read-write - - - LPMRCNT - LPM retry count - 21 - 3 - read-write - - - SNDLPM - Send LPM transaction - 24 - 1 - read-write - - - LPMRCNTSTS - LPM retry count status - 25 - 3 - read-only - - - ENBESL - Enable best effort service latency - 28 - 1 - read-write - - - - - - - OTG_FS_HOST - USB on the go full speed - USB_OTG_FS - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTG_FS host configuration register (OTG_FS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCS - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSS - FS- and LS-only support - 2 - 1 - read-write - - - - - HFIR - HFIR - OTG_FS Host frame interval register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRIVL - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSAVL - Periodic transmit data FIFO space available - 0 - 16 - read-write - - - PTXQSAV - Periodic transmit request queue space available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTG_FS Host all channels interrupt register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTG_FS host all channels interrupt mask register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTM - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTG_FS host port control and status register (OTG_FS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PCSTS - Port connect status - 0 - 1 - read-only - - - PCDET - Port connect detected - 1 - 1 - read-write - - - PENA - Port enable - 2 - 1 - read-write - - - PENCHNG - Port enable/disable change - 3 - 1 - read-write - - - POCA - Port overcurrent active - 4 - 1 - read-only - - - POCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRES - Port resume - 6 - 1 - read-write - - - PSUSP - Port suspend - 7 - 1 - read-write - - - PRST - Port reset - 8 - 1 - read-write - - - PLSTS - Port line status - 10 - 2 - read-only - - - PPWR - Port power - 12 - 1 - read-write - - - PTCTL - Port test control - 13 - 4 - read-write - - - PSPD - Port speed - 17 - 2 - read-only - - - - - 12 - 0x20 - 0-11 - HC%s - Host channel - 0x100 - - CHAR - HCCHAR0 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) - 0x0 - 0x20 - read-write - 0x00000000 - - - MPSIZ - Maximum packet size - 0 - 11 - - - EPNUM - Endpoint number - 11 - 4 - - - EPDIR - Endpoint direction - 15 - 1 - - - LSDEV - Low-speed device - 17 - 1 - - - EPTYP - Endpoint type - 18 - 2 - - - MCNT - Multicount - 20 - 2 - - - DAD - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - INT - HCINT0 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) - 0x8 - 0x20 - read-write - 0x00000000 - - - XFRC - Transfer completed - 0 - 1 - - - CHH - Channel halted - 1 - 1 - - - STALL - STALL response received interrupt - 3 - 1 - - - NAK - NAK response received interrupt - 4 - 1 - - - ACK - ACK response received/transmitted interrupt - 5 - 1 - - - TXERR - Transaction error - 7 - 1 - - - BBERR - Babble error - 8 - 1 - - - FRMOR - Frame overrun - 9 - 1 - - - DTERR - Data toggle error - 10 - 1 - - - - - INTMSK - HCINTMSK0 - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) - 0xC - 0x20 - read-write - 0x00000000 - - - XFRCM - Transfer completed mask - 0 - 1 - - - CHHM - Channel halted mask - 1 - 1 - - - STALLM - STALL response received interrupt mask - 3 - 1 - - - NAKM - NAK response received interrupt mask - 4 - 1 - - - ACKM - ACK response received/transmitted interrupt mask - 5 - 1 - - - NYET - response received interrupt mask - 6 - 1 - - - TXERRM - Transaction error mask - 7 - 1 - - - BBERRM - Babble error mask - 8 - 1 - - - FRMORM - Frame overrun mask - 9 - 1 - - - DTERRM - Data toggle error mask - 10 - 1 - - - - - TSIZ - HCTSIZ0 - OTG_FS host channel-0 transfer size register - 0x10 - 0x20 - read-write - 0x00000000 - - - XFRSIZ - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - DPID - Data PID - 29 - 2 - - - - - - - - OTG_FS_DEVICE - USB on the go full speed - USB_OTG_FS - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTG_FS device configuration register (OTG_FS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DSPD - Device speed - 0 - 2 - - - NZLSOHSK - Non-zero-length status OUT handshake - 2 - 1 - - - DAD - Device address - 4 - 7 - - - PFIVL - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTG_FS device control register (OTG_FS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWUSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SDIS - Soft disconnect - 1 - 1 - read-write - - - GINSTS - Global IN NAK status - 2 - 1 - read-only - - - GONSTS - Global OUT NAK status - 3 - 1 - read-only - - - TCTL - Test control - 4 - 3 - read-write - - - SGINAK - Set global IN NAK - 7 - 1 - read-write - - - CGINAK - Clear global IN NAK - 8 - 1 - read-write - - - SGONAK - Set global OUT NAK - 9 - 1 - read-write - - - CGONAK - Clear global OUT NAK - 10 - 1 - read-write - - - POPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTG_FS device status register (OTG_FS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - EERR - Erratic error - 3 - 1 - - - FNSOF - Frame number of the received SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFRCM - Transfer completed interrupt mask - 0 - 1 - - - EPDM - Endpoint disabled interrupt mask - 1 - 1 - - - TOM - Timeout condition mask (Non-isochronous endpoints) - 3 - 1 - - - ITTXFEMSK - IN token received when TxFIFO empty mask - 4 - 1 - - - INEPNMM - IN token received with EP mismatch mask - 5 - 1 - - - INEPNEM - IN endpoint NAK effective mask - 6 - 1 - - - - - DOEPMSK - DOEPMSK - OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFRCM - Transfer completed interrupt mask - 0 - 1 - - - EPDM - Endpoint disabled interrupt mask - 1 - 1 - - - STUPM - SETUP phase done mask - 3 - 1 - - - OTEPDM - OUT token received when endpoint disabled mask - 4 - 1 - - - - - DAINT - DAINT - OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - IEPINT - IN endpoint interrupt bits - 0 - 16 - - - OEPINT - OUT endpoint interrupt bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - IEPM - IN EP interrupt mask bits - 0 - 16 - - - OEPM - OUT EP interrupt mask bits - 16 - 16 - - - - - DVBUSDIS - DVBUSDIS - OTG_FS device VBUS discharge time register - 0x28 - 0x20 - read-write - 0x000017D7 - - - VBUSDT - Device VBUS discharge time - 0 - 16 - - - - - DVBUSPULSE - DVBUSPULSE - OTG_FS device VBUS pulsing time register - 0x2C - 0x20 - read-write - 0x000005B8 - - - DVBUSP - Device VBUS pulsing time - 0 - 12 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTG_FS device IN endpoint FIFO empty interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEM - IN EP Tx FIFO empty interrupt mask bits - 0 - 16 - - - - - DIEP0 - Device IN endpoint 0 - 0x100 - - CTL - DIEPCTL0 - OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) - 0x0 - 0x20 - 0x00000000 - - - MPSIZ - Maximum packet size - 0 - 2 - read-write - - - USBAEP - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYP - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPDIS - Endpoint disable - 30 - 1 - read-only - - - EPENA - Endpoint enable - 31 - 1 - read-write - - - - - INT - DIEPINT0 - device endpoint-x interrupt register - 0x8 - 0x20 - 0x00000080 - - - TXFE - TXFE - 7 - 1 - read-only - - - INEPNE - INEPNE - 6 - 1 - read-write - - - ITTXFE - ITTXFE - 4 - 1 - read-write - - - TOC - TOC - 3 - 1 - read-write - - - EPDISD - EPDISD - 1 - 1 - read-write - - - XFRC - XFRC - 0 - 1 - read-write - - - - - TSIZ - DIEPTSIZ0 - device endpoint-0 transfer size register - 0x10 - 0x20 - read-write - 0x00000000 - - - PKTCNT - Packet count - 19 - 2 - - - XFRSIZ - Transfer size - 0 - 7 - - - - - TXFSTS - DTXFSTS0 - OTG_FS device IN endpoint transmit FIFO status register - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTFSAV - IN endpoint TxFIFO space available - 0 - 16 - - - - - - 5 - 0x20 - 1-5 - DIEP%s - Device IN endpoint X - 0x120 - - CTL - DIEPCTL1 - OTG device endpoint-1 control register - 0x0 - 0x20 - 0x00000000 - - - EPENA - EPENA - 31 - 1 - read-write - - - EPDIS - EPDIS - 30 - 1 - read-write - - - SODDFRM_SD1PID - SODDFRM/SD1PID - 29 - 1 - write-only - - - SD0PID_SEVNFRM - SD0PID/SEVNFRM - 28 - 1 - write-only - - - SNAK - SNAK - 27 - 1 - write-only - - - CNAK - CNAK - 26 - 1 - write-only - - - TXFNUM - TXFNUM - 22 - 4 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - EPTYP - EPTYP - 18 - 2 - read-write - - - NAKSTS - NAKSTS - 17 - 1 - read-only - - - EONUM_DPID - EONUM/DPID - 16 - 1 - read-only - - - USBAEP - USBAEP - 15 - 1 - read-write - - - MPSIZ - MPSIZ - 0 - 11 - read-write - - - - - INT - DIEPINT1 - device endpoint-1 interrupt register - 0x8 - 0x20 - 0x00000080 - - - TXFE - TXFE - 7 - 1 - read-only - - - INEPNE - INEPNE - 6 - 1 - read-write - - - ITTXFE - ITTXFE - 4 - 1 - read-write - - - TOC - TOC - 3 - 1 - read-write - - - EPDISD - EPDISD - 1 - 1 - read-write - - - XFRC - XFRC - 0 - 1 - read-write - - - - - TSIZ - DIEPTSIZ1 - device endpoint-1 transfer size register - 0x10 - 0x20 - read-write - 0x00000000 - - - MCNT - Multi count - 29 - 2 - - - PKTCNT - Packet count - 19 - 10 - - - XFRSIZ - Transfer size - 0 - 19 - - - - - TXFSTS - DTXFSTS1 - OTG_FS device IN endpoint transmit FIFO status register - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTFSAV - IN endpoint TxFIFO space available - 0 - 16 - - - - - - DOEP0 - Device OUT endpoint 0 - 0x300 - - CTL - DOEPCTL0 - device endpoint-0 control register - 0x0 - 0x20 - 0x00008000 - - - EPENA - EPENA - 31 - 1 - read-write - - - EPDIS - EPDIS - 30 - 1 - read-only - - - SNAK - SNAK - 27 - 1 - write-only - - - CNAK - CNAK - 26 - 1 - write-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - SNPM - SNPM - 20 - 1 - read-write - - - EPTYP - EPTYP - 18 - 2 - read-only - - - NAKSTS - NAKSTS - 17 - 1 - read-only - - - USBAEP - USBAEP - 15 - 1 - read-only - - - MPSIZ - MPSIZ - 0 - 2 - read-only - - - - - INT - DOEPINT0 - device endpoint-0 interrupt register - 0x8 - 0x20 - read-write - 0x00000080 - - - B2BSTUP - B2BSTUP - 6 - 1 - - - OTEPDIS - OTEPDIS - 4 - 1 - - - STUP - STUP - 3 - 1 - - - EPDISD - EPDISD - 1 - 1 - - - XFRC - XFRC - 0 - 1 - - - - - TSIZ - DOEPTSIZ0 - device OUT endpoint-0 transfer size register - 0x10 - 0x20 - read-write - 0x00000000 - - - STUPCNT - SETUP packet count - 29 - 2 - - - PKTCNT - Packet count - 19 - 1 - - - XFRSIZ - Transfer size - 0 - 7 - - - - - - 5 - 0x20 - 1-5 - DOEP%s - Device IN endpoint X - 0x320 - - CTL - DOEPCTL1 - device endpoint-1 control register - 0x0 - 0x20 - 0x00000000 - - - EPENA - EPENA - 31 - 1 - read-write - - - EPDIS - EPDIS - 30 - 1 - read-write - - - SODDFRM - SODDFRM - 29 - 1 - write-only - - - SD0PID_SEVNFRM - SD0PID/SEVNFRM - 28 - 1 - write-only - - - SNAK - SNAK - 27 - 1 - write-only - - - CNAK - CNAK - 26 - 1 - write-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - SNPM - SNPM - 20 - 1 - read-write - - - EPTYP - EPTYP - 18 - 2 - read-write - - - NAKSTS - NAKSTS - 17 - 1 - read-only - - - EONUM_DPID - EONUM/DPID - 16 - 1 - read-only - - - USBAEP - USBAEP - 15 - 1 - read-write - - - MPSIZ - MPSIZ - 0 - 11 - read-write - - - - - INT - DOEPINT1 - device endpoint-1 interrupt register - 0x8 - 0x20 - read-write - 0x00000080 - - - B2BSTUP - B2BSTUP - 6 - 1 - - - OTEPDIS - OTEPDIS - 4 - 1 - - - STUP - STUP - 3 - 1 - - - EPDISD - EPDISD - 1 - 1 - - - XFRC - XFRC - 0 - 1 - - - - - TSIZ - DOEPTSIZ1 - device OUT endpoint-1 transfer size register - 0x10 - 0x20 - read-write - 0x00000000 - - - RXDPID_STUPCNT - Received data PID/SETUP packet count - 29 - 2 - - - PKTCNT - Packet count - 19 - 10 - - - XFRSIZ - Transfer size - 0 - 19 - - - - - - - - OTG_FS_PWRCLK - USB on the go full speed - USB_OTG_FS - 0x50000E00 - - 0x0 - 0x400 - registers - - - OTG_FS_WKUP - USB On-The-Go FS Wakeup through EXTI line - interrupt - 42 - - - OTG_FS - USB On The Go FS global - interrupt - 67 - - - - PCGCCTL - PCGCCTL - OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) - 0x0 - 0x20 - read-write - 0x00000000 - - - STPPCLK - Stop PHY clock - 0 - 1 - - - GATEHCLK - Gate HCLK - 1 - 1 - - - PHYSUSP - PHY Suspended - 4 - 1 - - - - - - - OTG_HS_GLOBAL - USB on the go high speed - USB_OTG_HS - 0x40040000 - - 0x0 - 0x400 - registers - - - - GOTGCTL - GOTGCTL - OTG_HS control and status register - 0x0 - 0x20 - 0x00000800 - - - SRQSCS - Session request success - 0 - 1 - read-only - - - SRQ - Session request - 1 - 1 - read-write - - - HNGSCS - Host negotiation success - 8 - 1 - read-only - - - HNPRQ - HNP request - 9 - 1 - read-write - - - HSHNPEN - Host set HNP enable - 10 - 1 - read-write - - - DHNPEN - Device HNP enabled - 11 - 1 - read-write - - - CIDSTS - Connector ID status - 16 - 1 - read-only - - - DBCT - Long/short debounce time - 17 - 1 - read-only - - - ASVLD - A-session valid - 18 - 1 - read-only - - - BSVLD - B-session valid - 19 - 1 - read-only - - - EHEN - Embedded host enable - 12 - 1 - read-write - - - VBVALOEN - V_BUS valid override enable - 2 - 1 - read-write - - - VBVALOVAL - V_BUS valid override value - 3 - 1 - read-write - - - AVALOEN - A-peripheral session valid override enable - 4 - 1 - read-write - - - AVALOVAL - A-peripheral session valid override value - 5 - 1 - read-write - - - BVALOEN - B-peripheral session valid override enable - 6 - 1 - read-write - - - BVALOVAL - B-peripheral session valid override value - 7 - 1 - read-write - - - OTGVER - OTG version - 20 - 1 - read-write - - - CURMOD - Current mode of operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTG_HS interrupt register - 0x4 - 0x20 - read-write - 0x00000000 - - - SEDET - Session end detected - 2 - 1 - - - SRSSCHG - Session request success status change - 8 - 1 - - - HNSSCHG - Host negotiation success status change - 9 - 1 - - - HNGDET - Host negotiation detected - 17 - 1 - - - ADTOCHG - A-device timeout change - 18 - 1 - - - DBCDNE - Debounce done - 19 - 1 - - - IDCHNG - ID input pin changed - 20 - 1 - - - - - GAHBCFG - GAHBCFG - OTG_HS AHB configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - GINT - Global interrupt mask - 0 - 1 - - - HBSTLEN - Burst length/type - 1 - 4 - - - DMAEN - DMA enable - 5 - 1 - - - TXFELVL - TxFIFO empty level - 7 - 1 - - - PTXFELVL - Periodic TxFIFO empty level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - OTG_HS USB configuration register - 0xC - 0x20 - 0x00000A00 - - - TOCAL - FS timeout calibration - 0 - 3 - read-write - - - PHYSEL - USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select - 6 - 1 - write-only - - - SRPCAP - SRP-capable - 8 - 1 - read-write - - - HNPCAP - HNP-capable - 9 - 1 - read-write - - - TRDT - USB turnaround time - 10 - 4 - read-write - - - PHYLPCS - PHY Low-power clock select - 15 - 1 - read-write - - - ULPIFSLS - ULPI FS/LS select - 17 - 1 - read-write - - - ULPIAR - ULPI Auto-resume - 18 - 1 - read-write - - - ULPICSM - ULPI Clock SuspendM - 19 - 1 - read-write - - - ULPIEVBUSD - ULPI External VBUS Drive - 20 - 1 - read-write - - - ULPIEVBUSI - ULPI external VBUS indicator - 21 - 1 - read-write - - - TSDPS - TermSel DLine pulsing selection - 22 - 1 - read-write - - - PCCI - Indicator complement - 23 - 1 - read-write - - - PTCI - Indicator pass through - 24 - 1 - read-write - - - ULPIIPD - ULPI interface protect disable - 25 - 1 - read-write - - - FHMOD - Forced host mode - 29 - 1 - read-write - - - FDMOD - Forced peripheral mode - 30 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTG_HS reset register - 0x10 - 0x20 - 0x20000000 - - - CSRST - Core soft reset - 0 - 1 - read-write - - - HSRST - HCLK soft reset - 1 - 1 - read-write - - - FCRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDL - AHB master idle - 31 - 1 - read-only - - - DMAREQ - DMA request signal enabled for USB OTG HS - 30 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTG_HS core interrupt register - 0x14 - 0x20 - 0x04000020 - - - CMOD - Current mode of operation - 0 - 1 - read-only - - - MMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO nonempty - 4 - 1 - read-only - - - NPTXFE - Nonperiodic TxFIFO empty - 5 - 1 - read-only - - - GINAKEFF - Global IN nonperiodic NAK effective - 6 - 1 - read-only - - - BOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ESUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDNE - Enumeration done - 13 - 1 - read-write - - - ISOODRP - Isochronous OUT packet dropped interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame interrupt - 15 - 1 - read-write - - - IEPINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPINT - OUT endpoint interrupt - 19 - 1 - read-only - - - IISOIXFR - Incomplete isochronous IN transfer - 20 - 1 - read-write - - - PXFR_INCOMPISOOUT - Incomplete periodic transfer - 21 - 1 - read-write - - - DATAFSUSP - Data fetch suspended - 22 - 1 - read-write - - - HPRTINT - Host port interrupt - 24 - 1 - read-only - - - HCINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFE - Periodic TxFIFO empty - 26 - 1 - read-only - - - CIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCINT - Disconnect detected interrupt - 29 - 1 - read-write - - - SRQINT - Session request/new session detected interrupt - 30 - 1 - read-write - - - WKUINT - Resume/remote wakeup detected interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_HS interrupt mask register - 0x18 - 0x20 - 0x00000000 - - - MMISM - Mode mismatch interrupt mask - 1 - 1 - read-write - - - OTGINT - OTG interrupt mask - 2 - 1 - read-write - - - SOFM - Start of frame mask - 3 - 1 - read-write - - - RXFLVLM - Receive FIFO nonempty mask - 4 - 1 - read-write - - - NPTXFEM - Nonperiodic TxFIFO empty mask - 5 - 1 - read-write - - - GINAKEFFM - Global nonperiodic IN NAK effective mask - 6 - 1 - read-write - - - GONAKEFFM - Global OUT NAK effective mask - 7 - 1 - read-write - - - ESUSPM - Early suspend mask - 10 - 1 - read-write - - - USBSUSPM - USB suspend mask - 11 - 1 - read-write - - - USBRST - USB reset mask - 12 - 1 - read-write - - - ENUMDNEM - Enumeration done mask - 13 - 1 - read-write - - - ISOODRPM - Isochronous OUT packet dropped interrupt mask - 14 - 1 - read-write - - - EOPFM - End of periodic frame interrupt mask - 15 - 1 - read-write - - - IEPINT - IN endpoints interrupt mask - 18 - 1 - read-write - - - OEPINT - OUT endpoints interrupt mask - 19 - 1 - read-write - - - IISOIXFRM - Incomplete isochronous IN transfer mask - 20 - 1 - read-write - - - PXFRM_IISOOXFRM - Incomplete periodic transfer mask - 21 - 1 - read-write - - - FSUSPM - Data fetch suspended mask - 22 - 1 - read-write - - - PRTIM - Host port interrupt mask - 24 - 1 - read-only - - - HCIM - Host channels interrupt mask - 25 - 1 - read-write - - - PTXFEM - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CIDSCHGM - Connector ID status change mask - 28 - 1 - read-write - - - DISCINT - Disconnect detected interrupt mask - 29 - 1 - read-write - - - SRQIM - Session request/new session detected interrupt mask - 30 - 1 - read-write - - - WUIM - Resume/remote wakeup detected interrupt mask - 31 - 1 - read-write - - - RSTDE - Reset detected interrupt mask - 23 - 1 - read-write - - - LPMINTM - LPM interrupt mask - 27 - 1 - read-write - - - - - GRXSTSR_Host - GRXSTSR_Host - OTG_HS Receive status debug read register (host mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXSTSP_Host - GRXSTSP_Host - OTG_HS status read and pop register (host mode) - 0x20 - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTG_HS Receive FIFO size register - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFD - RxFIFO depth - 0 - 16 - - - - - HNPTXFSIZ - HNPTXFSIZ_Host - OTG_HS nonperiodic transmit FIFO size register (host mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSA - Nonperiodic transmit RAM start address - 0 - 16 - - - NPTXFD - Nonperiodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF0 - DIEPTXF0_Device - Endpoint 0 transmit FIFO size (peripheral mode) - HNPTXFSIZ - 0x28 - 0x20 - read-write - 0x00000200 - - - TX0FSA - Endpoint 0 transmit RAM start address - 0 - 16 - - - TX0FD - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - HNPTXSTS - GNPTXSTS - OTG_HS nonperiodic transmit FIFO/queue status register - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSAV - Nonperiodic TxFIFO space available - 0 - 16 - - - NPTQXSAV - Nonperiodic transmit request queue space available - 16 - 8 - - - NPTXQTOP - Top of the nonperiodic transmit request queue - 24 - 7 - - - - - GCCFG - GCCFG - OTG_HS general core configuration register - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDWN - Power down - 16 - 1 - - - BCDEN - Battery charging detector (BCD) enable - 17 - 1 - - - DCDEN - Data contact detection (DCD) mode enable - 18 - 1 - - - PDEN - Primary detection (PD) mode enable - 19 - 1 - - - SDEN - Secondary detection (SD) mode enable - 20 - 1 - - - VBDEN - USB VBUS detection enable - 21 - 1 - - - DCDET - Data contact detection (DCD) status - 0 - 1 - - - PDET - Primary detection (PD) status - 1 - 1 - - - SDET - Secondary detection (SD) status - 2 - 1 - - - PS2DET - DM pull-up detection status - 3 - 1 - - - - - CID - CID - OTG_HS core ID register - 0x3C - 0x20 - read-write - 0x00001200 - - - PRODUCT_ID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTG_HS Host periodic transmit FIFO size register - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXSA - Host periodic TxFIFO start address - 0 - 16 - - - PTXFD - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTG_HS device IN endpoint transmit FIFO size register - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXSA - IN endpoint FIFOx transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTG_HS device IN endpoint transmit FIFO size register - 0x108 - 0x20 - read-write - 0x02000600 - - - INEPTXSA - IN endpoint FIFOx transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTG_HS device IN endpoint transmit FIFO size register - 0x10C - 0x20 - read-write - 0x02000800 - - - INEPTXSA - IN endpoint FIFOx transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTG_HS device IN endpoint transmit FIFO size register - 0x110 - 0x20 - read-write - 0x02000A00 - - - INEPTXSA - IN endpoint FIFOx transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTG_HS device IN endpoint transmit FIFO size register - 0x114 - 0x20 - read-write - 0x02000C00 - - - INEPTXSA - IN endpoint FIFOx transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTG_HS device IN endpoint transmit FIFO size register - 0x118 - 0x20 - read-write - 0x02000E00 - - - INEPTXSA - IN endpoint FIFOx transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTG_HS device IN endpoint transmit FIFO size register - 0x11C - 0x20 - read-write - 0x02001000 - - - INEPTXSA - IN endpoint FIFOx transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - GRXSTSR_Device - GRXSTSR_Device - OTG_HS Receive status debug read register (peripheral mode mode) - GRXSTSR_Host - 0x1C - 0x20 - read-only - 0x00000000 - - - EPNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FRMNUM - Frame number - 21 - 4 - - - - - GRXSTSP_Device - GRXSTSP_Device - OTG_HS status read and pop register (peripheral mode) - GRXSTSP_Host - 0x20 - 0x20 - read-only - 0x00000000 - - - EPNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FRMNUM - Frame number - 21 - 4 - - - - - GLPMCFG - GLPMCFG - OTG core LPM configuration register - 0x54 - 0x20 - 0x00000000 - - - LPMEN - LPM support enable - 0 - 1 - read-write - - - LPMACK - LPM token acknowledge enable - 1 - 1 - read-write - - - BESL - Best effort service latency - 2 - 4 - read-only - - - REMWAKE - bRemoteWake value - 6 - 1 - read-only - - - L1SSEN - L1 Shallow Sleep enable - 7 - 1 - read-write - - - BESLTHRS - BESL threshold - 8 - 4 - read-write - - - L1DSEN - L1 deep sleep enable - 12 - 1 - read-write - - - LPMRST - LPM response - 13 - 2 - read-only - - - SLPSTS - Port sleep status - 15 - 1 - read-only - - - L1RSMOK - Sleep State Resume OK - 16 - 1 - read-only - - - LPMCHIDX - LPM Channel Index - 17 - 4 - read-write - - - LPMRCNT - LPM retry count - 21 - 3 - read-write - - - SNDLPM - Send LPM transaction - 24 - 1 - read-write - - - LPMRCNTSTS - LPM retry count status - 25 - 3 - read-only - - - ENBESL - Enable best effort service latency - 28 - 1 - read-write - - - - - DIEPTXF8 - OTG_HS device IN endpoint transmit FIFO size register - 0x120 - 0x20 - read-write - 0x02001200 - - - INEPTXSA - IN endpoint FIFOx transmit RAM start address - 0 - 16 - - - INEPTXFD - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - OTG_HS_HOST - USB on the go high speed - USB_OTG_HS - 0x40040400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTG_HS host configuration register - 0x0 - 0x20 - 0x00000000 - - - FSLSPCS - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSS - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTG_HS Host frame interval register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRIVL - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTG_HS host frame number/frame time remaining register - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTG_HS_Host periodic transmit FIFO/queue status register - 0x10 - 0x20 - 0x00080100 - - - PTXFSAVL - Periodic transmit data FIFO space available - 0 - 16 - read-write - - - PTXQSAV - Periodic transmit request queue space available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTG_HS Host all channels interrupt register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTG_HS host all channels interrupt mask register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTM - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTG_HS host port control and status register - 0x40 - 0x20 - 0x00000000 - - - PCSTS - Port connect status - 0 - 1 - read-only - - - PCDET - Port connect detected - 1 - 1 - read-write - - - PENA - Port enable - 2 - 1 - read-write - - - PENCHNG - Port enable/disable change - 3 - 1 - read-write - - - POCA - Port overcurrent active - 4 - 1 - read-only - - - POCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRES - Port resume - 6 - 1 - read-write - - - PSUSP - Port suspend - 7 - 1 - read-write - - - PRST - Port reset - 8 - 1 - read-write - - - PLSTS - Port line status - 10 - 2 - read-only - - - PPWR - Port power - 12 - 1 - read-write - - - PTCTL - Port test control - 13 - 4 - read-write - - - PSPD - Port speed - 17 - 2 - read-only - - - - - 16 - 0x20 - 0-15 - HC%s - Host channel - 0x100 - - CHAR - HCCHAR0 - OTG_HS host channel-0 characteristics register - 0x0 - 0x20 - read-write - 0x00000000 - - - MPSIZ - Maximum packet size - 0 - 11 - - - EPNUM - Endpoint number - 11 - 4 - - - EPDIR - Endpoint direction - 15 - 1 - - - LSDEV - Low-speed device - 17 - 1 - - - EPTYP - Endpoint type - 18 - 2 - - - MC - Multi Count (MC) / Error Count (EC) - 20 - 2 - - - DAD - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - SPLT - HCSPLT0 - OTG_HS host channel-0 split control register - 0x4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port address - 0 - 7 - - - HUBADDR - Hub address - 7 - 7 - - - XACTPOS - XACTPOS - 14 - 2 - - - COMPLSPLT - Do complete split - 16 - 1 - - - SPLITEN - Split enable - 31 - 1 - - - - - INT - HCINT0 - OTG_HS host channel-11 interrupt register - 0x8 - 0x20 - read-write - 0x00000000 - - - XFRC - Transfer completed - 0 - 1 - - - CHH - Channel halted - 1 - 1 - - - AHBERR - AHB error - 2 - 1 - - - STALL - STALL response received interrupt - 3 - 1 - - - NAK - NAK response received interrupt - 4 - 1 - - - ACK - ACK response received/transmitted interrupt - 5 - 1 - - - NYET - Response received interrupt - 6 - 1 - - - TXERR - Transaction error - 7 - 1 - - - BBERR - Babble error - 8 - 1 - - - FRMOR - Frame overrun - 9 - 1 - - - DTERR - Data toggle error - 10 - 1 - - - - - INTMSK - HCINTMSK0 - OTG_HS host channel-11 interrupt mask register - 0xC - 0x20 - read-write - 0x00000000 - - - XFRCM - Transfer completed mask - 0 - 1 - - - CHHM - Channel halted mask - 1 - 1 - - - AHBERR - AHB error - 2 - 1 - - - STALLM - STALL response received interrupt mask - 3 - 1 - - - NAKM - NAK response received interrupt mask - 4 - 1 - - - ACKM - ACK response received/transmitted interrupt mask - 5 - 1 - - - NYET - response received interrupt mask - 6 - 1 - - - TXERRM - Transaction error mask - 7 - 1 - - - BBERRM - Babble error mask - 8 - 1 - - - FRMORM - Frame overrun mask - 9 - 1 - - - DTERRM - Data toggle error mask - 10 - 1 - - - - - TSIZ - HCTSIZ0 - OTG_HS host channel-11 transfer size register - 0x10 - 0x20 - read-write - 0x00000000 - - - XFRSIZ - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - DPID - Data PID - 29 - 2 - - - - - DMA - HCDMA0 - OTG_HS host channel-0 DMA address register - 0x14 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA address - 0 - 32 - - - - - - - - OTG_HS_DEVICE - USB on the go high speed - USB_OTG_HS - 0x40040800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTG_HS device configuration register - 0x0 - 0x20 - read-write - 0x02200000 - - - DSPD - Device speed - 0 - 2 - - - NZLSOHSK - Nonzero-length status OUT handshake - 2 - 1 - - - DAD - Device address - 4 - 7 - - - PFIVL - Periodic (micro)frame interval - 11 - 2 - - - PERSCHIVL - Periodic scheduling interval - 24 - 2 - - - - - DCTL - DCTL - OTG_HS device control register - 0x4 - 0x20 - 0x00000000 - - - RWUSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SDIS - Soft disconnect - 1 - 1 - read-write - - - GINSTS - Global IN NAK status - 2 - 1 - read-only - - - GONSTS - Global OUT NAK status - 3 - 1 - read-only - - - TCTL - Test control - 4 - 3 - read-write - - - SGINAK - Set global IN NAK - 7 - 1 - write-only - - - CGINAK - Clear global IN NAK - 8 - 1 - write-only - - - SGONAK - Set global OUT NAK - 9 - 1 - write-only - - - CGONAK - Clear global OUT NAK - 10 - 1 - write-only - - - POPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTG_HS device status register - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - EERR - Erratic error - 3 - 1 - - - FNSOF - Frame number of the received SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTG_HS device IN endpoint common interrupt mask register - 0x10 - 0x20 - read-write - 0x00000000 - - - XFRCM - Transfer completed interrupt mask - 0 - 1 - - - EPDM - Endpoint disabled interrupt mask - 1 - 1 - - - TOM - Timeout condition mask (nonisochronous endpoints) - 3 - 1 - - - ITTXFEMSK - IN token received when TxFIFO empty mask - 4 - 1 - - - INEPNMM - IN token received with EP mismatch mask - 5 - 1 - - - INEPNEM - IN endpoint NAK effective mask - 6 - 1 - - - TXFURM - FIFO underrun mask - 8 - 1 - - - BIM - BNA interrupt mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTG_HS device OUT endpoint common interrupt mask register - 0x14 - 0x20 - read-write - 0x00000000 - - - XFRCM - Transfer completed interrupt mask - 0 - 1 - - - EPDM - Endpoint disabled interrupt mask - 1 - 1 - - - STUPM - SETUP phase done mask - 3 - 1 - - - OTEPDM - OUT token received when endpoint disabled mask - 4 - 1 - - - B2BSTUP - Back-to-back SETUP packets received mask - 6 - 1 - - - OPEM - OUT packet error mask - 8 - 1 - - - BOIM - BNA interrupt mask - 9 - 1 - - - - - DAINT - DAINT - OTG_HS device all endpoints interrupt register - 0x18 - 0x20 - read-only - 0x00000000 - - - IEPINT - IN endpoint interrupt bits - 0 - 16 - - - OEPINT - OUT endpoint interrupt bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTG_HS all endpoints interrupt mask register - 0x1C - 0x20 - read-write - 0x00000000 - - - IEPM - IN EP interrupt mask bits - 0 - 16 - - - OEPM - OUT EP interrupt mask bits - 16 - 16 - - - - - DVBUSDIS - DVBUSDIS - OTG_HS device VBUS discharge time register - 0x28 - 0x20 - read-write - 0x000017D7 - - - VBUSDT - Device VBUS discharge time - 0 - 16 - - - - - DVBUSPULSE - DVBUSPULSE - OTG_HS device VBUS pulsing time register - 0x2C - 0x20 - read-write - 0x000005B8 - - - DVBUSP - Device VBUS pulsing time - 0 - 12 - - - - - DTHRCTL - DTHRCTL - OTG_HS Device threshold control register - 0x30 - 0x20 - read-write - 0x00000000 - - - NONISOTHREN - Nonisochronous IN endpoints threshold enable - 0 - 1 - - - ISOTHREN - ISO IN endpoint threshold enable - 1 - 1 - - - TXTHRLEN - Transmit threshold length - 2 - 9 - - - RXTHREN - Receive threshold enable - 16 - 1 - - - RXTHRLEN - Receive threshold length - 17 - 9 - - - ARPEN - Arbiter parking enable - 27 - 1 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTG_HS device IN endpoint FIFO empty interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEM - IN EP Tx FIFO empty interrupt mask bits - 0 - 16 - - - - - DEACHINT - DEACHINT - OTG_HS device each endpoint interrupt register - 0x38 - 0x20 - read-write - 0x00000000 - - - IEP1INT - IN endpoint 1interrupt bit - 1 - 1 - - - OEP1INT - OUT endpoint 1 interrupt bit - 17 - 1 - - - - - DEACHINTMSK - DEACHINTMSK - OTG_HS device each endpoint interrupt register mask - 0x3C - 0x20 - read-write - 0x00000000 - - - IEP1INTM - IN Endpoint 1 interrupt mask bit - 1 - 1 - - - OEP1INTM - OUT Endpoint 1 interrupt mask bit - 17 - 1 - - - - - DIEP0 - Device IN endpoint 0 - 0x100 - - CTL - DIEPCTL0 - OTG device endpoint-0 control register - 0x0 - 0x20 - 0x00000000 - - - MPSIZ - Maximum packet size - 0 - 11 - read-write - - - USBAEP - USB active endpoint - 15 - 1 - read-write - - - EONUM_DPID - Even/odd frame - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYP - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SD0PID_SEVNFRM - Set DATA0 PID - 28 - 1 - write-only - - - SODDFRM - Set odd frame - 29 - 1 - write-only - - - EPDIS - Endpoint disable - 30 - 1 - read-write - - - EPENA - Endpoint enable - 31 - 1 - read-write - - - - - INT - DIEPINT0 - OTG device endpoint-0 interrupt register - 0x8 - 0x20 - 0x00000080 - - - XFRC - Transfer completed interrupt - 0 - 1 - read-write - - - EPDISD - Endpoint disabled interrupt - 1 - 1 - read-write - - - TOC - Timeout condition - 3 - 1 - read-write - - - ITTXFE - IN token received when TxFIFO is empty - 4 - 1 - read-write - - - INEPNE - IN endpoint NAK effective - 6 - 1 - read-write - - - TXFE - Transmit FIFO empty - 7 - 1 - read-only - - - TXFIFOUDRN - Transmit Fifo Underrun - 8 - 1 - read-write - - - BNA - Buffer not available interrupt - 9 - 1 - read-write - - - PKTDRPSTS - Packet dropped status - 11 - 1 - read-write - - - BERR - Babble error interrupt - 12 - 1 - read-write - - - NAK - NAK interrupt - 13 - 1 - read-write - - - - - TSIZ - DIEPTSIZ0 - OTG_HS device IN endpoint 0 transfer size register - 0x10 - 0x20 - read-write - 0x00000000 - - - XFRSIZ - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DMA - OTG_HS device endpoint-0 DMA address register - 0x14 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA address - 0 - 32 - - - - - TXFSTS - DTXFSTS0 - OTG_HS device IN endpoint transmit FIFO status register - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTFSAV - IN endpoint TxFIFO space avail - 0 - 16 - - - - - - 8 - 0x20 - 1-8 - DIEP%s - Device IN endpoint X - 0x120 - - CTL - DIEPCTL1 - OTG device endpoint-1 control register - 0x0 - 0x20 - 0x00000000 - - - MPSIZ - Maximum packet size - 0 - 11 - read-write - - - USBAEP - USB active endpoint - 15 - 1 - read-write - - - EONUM_DPID - Even/odd frame - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYP - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SD0PID_SEVNFRM - Set DATA0 PID - 28 - 1 - write-only - - - SODDFRM - Set odd frame - 29 - 1 - write-only - - - EPDIS - Endpoint disable - 30 - 1 - read-write - - - EPENA - Endpoint enable - 31 - 1 - read-write - - - - - INT - DIEPINT1 - OTG device endpoint-1 interrupt register - 0x8 - 0x20 - 0x00000000 - - - XFRC - Transfer completed interrupt - 0 - 1 - read-write - - - EPDISD - Endpoint disabled interrupt - 1 - 1 - read-write - - - TOC - Timeout condition - 3 - 1 - read-write - - - ITTXFE - IN token received when TxFIFO is empty - 4 - 1 - read-write - - - INEPNE - IN endpoint NAK effective - 6 - 1 - read-write - - - TXFE - Transmit FIFO empty - 7 - 1 - read-only - - - TXFIFOUDRN - Transmit Fifo Underrun - 8 - 1 - read-write - - - BNA - Buffer not available interrupt - 9 - 1 - read-write - - - PKTDRPSTS - Packet dropped status - 11 - 1 - read-write - - - BERR - Babble error interrupt - 12 - 1 - read-write - - - NAK - NAK interrupt - 13 - 1 - read-write - - - - - TSIZ - DIEPTSIZ1 - OTG_HS device endpoint transfer size register - 0x10 - 0x20 - read-write - 0x00000000 - - - XFRSIZ - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MCNT - Multi count - 29 - 2 - - - - - DMA - DIEPDMA1 - OTG_HS device endpoint-1 DMA address register - 0x14 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA address - 0 - 32 - - - - - TXFSTS - DTXFSTS1 - OTG_HS device IN endpoint transmit FIFO status register - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTFSAV - IN endpoint TxFIFO space avail - 0 - 16 - - - - - - DOEP0 - Device OUT endpoint 0 - 0x300 - - CTL - DOEPCTL0 - OTG_HS device control OUT endpoint 0 control register - 0x0 - 0x20 - 0x00008000 - - - MPSIZ - Maximum packet size - 0 - 2 - read-only - - - USBAEP - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYP - Endpoint type - 18 - 2 - read-only - - - SNPM - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPDIS - Endpoint disable - 30 - 1 - read-only - - - EPENA - Endpoint enable - 31 - 1 - read-write - - - - - INT - DOEPINT0 - OTG_HS device endpoint-0 interrupt register - 0x8 - 0x20 - read-write - 0x00000080 - - - XFRC - Transfer completed interrupt - 0 - 1 - - - EPDISD - Endpoint disabled interrupt - 1 - 1 - - - STUP - SETUP phase done - 3 - 1 - - - OTEPDIS - OUT token received when endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP packets received - 6 - 1 - - - NYET - NYET interrupt - 14 - 1 - - - - - TSIZ - DOEPTSIZ0 - OTG_HS device endpoint-0 transfer size register - 0x10 - 0x20 - read-write - 0x00000000 - - - XFRSIZ - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - STUPCNT - SETUP packet count - 29 - 2 - - - - - DMA - OTG_HS device endpoint-0 DMA address register - 0x14 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA address - 0 - 32 - - - - - - 8 - 0x20 - 1-8 - DOEP%s - Device IN endpoint X - 0x320 - - CTL - DOEPCTL1 - OTG device endpoint-1 control register - 0x0 - 0x20 - 0x00000000 - - - MPSIZ - Maximum packet size - 0 - 11 - read-write - - - USBAEP - USB active endpoint - 15 - 1 - read-write - - - EONUM_DPID - Even odd frame/Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYP - Endpoint type - 18 - 2 - read-write - - - SNPM - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SD0PID_SEVNFRM - Set DATA0 PID/Set even frame - 28 - 1 - write-only - - - SODDFRM - Set odd frame - 29 - 1 - write-only - - - EPDIS - Endpoint disable - 30 - 1 - read-write - - - EPENA - Endpoint enable - 31 - 1 - read-write - - - - - INT - DOEPINT1 - OTG_HS device endpoint-1 interrupt register - 0x8 - 0x20 - read-write - 0x00000000 - - - XFRC - Transfer completed interrupt - 0 - 1 - - - EPDISD - Endpoint disabled interrupt - 1 - 1 - - - STUP - SETUP phase done - 3 - 1 - - - OTEPDIS - OUT token received when endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP packets received - 6 - 1 - - - NYET - NYET interrupt - 14 - 1 - - - - - DMA - OTG_HS device endpoint-1 DMA address register - 0x14 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA address - 0 - 32 - - - - - TSIZ - DOEPTSIZ1 - OTG_HS device endpoint-1 transfer size register - 0x10 - 0x20 - read-write - 0x00000000 - - - XFRSIZ - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID_STUPCNT - Received data PID/SETUP packet count - 29 - 2 - - - - - - DIEPEACHMSK1 - 0x44 - 0x20 - read-write - 0x00000000 - - - XFRCM - Transfer completed interrupt mask - 0 - 1 - - - EPDM - Endpoint disabled interrupt mask - 1 - 1 - - - AHBERRM - AHB error mask - 2 - 1 - - - TOM - Timeout condition mask (Non-isochronous endpoints) - 3 - 1 - - - ITTXFEMSK - IN token received when TxFIFO empty mask - 4 - 1 - - - INEPNEM - IN endpoint NAK effective mask - 6 - 1 - - - TXFURM - FIFO underrun mask - 8 - 1 - - - BNAM - BNA interrupt mask - 9 - 1 - - - NAKM - NAK interrupt mask - 13 - 1 - - - - - DOEPEACHMSK1 - 0x84 - 0x20 - read-write - 0x00000000 - - - XFRCM - Transfer completed interrupt mask - 0 - 1 - - - EPDM - Endpoint disabled interrupt mask - 1 - 1 - - - AHBERRM - AHB error mask - 2 - 1 - - - STUPM - SETUP phase done mask - 3 - 1 - - - OTEPDM - OUT token received when endpoint disabled mask - 4 - 1 - - - B2BSTUPM - Back-to-back SETUP packets received mask - 6 - 1 - - - OUTPKTERRM - Out packet error mask - 8 - 1 - - - BNAM - BNA interrupt mask - 9 - 1 - - - BERRM - Babble error interrupt mask - 12 - 1 - - - NAKMSK - NAK interrupt mask - 13 - 1 - - - NYETMSK - NYET interrupt mask - 14 - 1 - - - - - - - OTG_HS_PWRCLK - USB on the go high speed - USB_OTG_HS - 0x40040E00 - - 0x0 - 0x3F200 - registers - - - OTG_HS_EP1_OUT - USB On The Go HS End Point 1 Out global - interrupt - 74 - - - OTG_HS_EP1_IN - USB On The Go HS End Point 1 In global - interrupt - 75 - - - OTG_HS_WKUP - USB On The Go HS Wakeup through EXTI - interrupt - 76 - - - OTG_HS - USB On The Go HS global - interrupt - 77 - - - - PCGCR - PCGCR - Power and clock gating control register - 0x0 - 0x20 - read-write - 0x00000000 - - - STPPCLK - Stop PHY clock - 0 - 1 - - - GATEHCLK - Gate HCLK - 1 - 1 - - - PHYSUSP - PHY suspended - 4 - 1 - - - - - - - NVIC - Nested Vectored Interrupt Controller - NVIC - 0xE000E100 - - 0x0 - 0x369 - registers - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x0 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x4 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER2 - ISER2 - Interrupt Set-Enable Register - 0x8 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable Register - 0x80 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable Register - 0x84 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER2 - ICER2 - Interrupt Clear-Enable Register - 0x88 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR2 - ISPR2 - Interrupt Set-Pending Register - 0x108 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR2 - ICPR2 - Interrupt Clear-Pending Register - 0x188 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x200 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x204 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR2 - IABR2 - Interrupt Active Bit Register - 0x208 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x300 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x304 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x308 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x30C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x310 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x314 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x318 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x31C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x320 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x324 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x328 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x32C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x330 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x334 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x338 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR15 - IPR15 - Interrupt Priority Register - 0x33C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR16 - IPR16 - Interrupt Priority Register - 0x340 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR17 - IPR17 - Interrupt Priority Register - 0x344 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR18 - IPR18 - Interrupt Priority Register - 0x348 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR19 - IPR19 - Interrupt Priority Register - 0x34C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR20 - IPR20 - Interrupt Priority Register - 0x350 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR21 - IPR21 - Interrupt Priority Register - 0x354 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR22 - IPR22 - Interrupt Priority Register - 0x358 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR23 - IPR23 - Interrupt Priority Register - 0x35C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR24 - IPR24 - Interrupt Priority Register - 0x360 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR25 - IPR25 - Interrupt Priority Register - 0x364 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - MPU - Memory protection unit - MPU - 0xE000ED90 - - 0x0 - 0x15 - registers - - - - TYPER - TYPER - MPU type register - 0x0 - 0x20 - read-only - 0x00000800 - - - SEPARATE - Separate flag - 0 - 1 - - - DREGION - Number of MPU data regions - 8 - 8 - - - IREGION - Number of MPU instruction regions - 16 - 8 - - - - - CTRL - CTRL - MPU control register - 0x4 - 0x20 - read-only - 0x00000000 - - - ENABLE - Enables the MPU - 0 - 1 - - - HFNMIENA - Enables the operation of MPU during hard fault - 1 - 1 - - - PRIVDEFENA - Enable priviliged software access to default memory map - 2 - 1 - - - - - RNR - RNR - MPU region number register - 0x8 - 0x20 - read-write - 0x00000000 - - - REGION - MPU region - 0 - 8 - - - - - RBAR - RBAR - MPU region base address register - 0xC - 0x20 - read-write - 0x00000000 - - - REGION - MPU region field - 0 - 4 - - - VALID - MPU region number valid - 4 - 1 - - - ADDR - Region base address field - 5 - 27 - - - - - RASR - RASR - MPU region attribute and size register - 0x10 - 0x20 - read-write - 0x00000000 - - - ENABLE - Region enable bit. - 0 - 1 - - - SIZE - Size of the MPU protection region - 1 - 5 - - - SRD - Subregion disable bits - 8 - 8 - - - B - memory attribute - 16 - 1 - - - C - memory attribute - 17 - 1 - - - S - Shareable memory attribute - 18 - 1 - - - TEX - memory attribute - 19 - 3 - - - AP - Access permission - 24 - 3 - - - XN - Instruction access disable bit - 28 - 1 - - - - - - - STK - SysTick timer - STK - 0xE000E010 - - 0x0 - 0x11 - registers - - - - CSR - CSR - SysTick control and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - ENABLE - Counter enable - 0 - 1 - - - TICKINT - SysTick exception request enable - 1 - 1 - - - CLKSOURCE - Clock source selection - 2 - 1 - - - COUNTFLAG - COUNTFLAG - 16 - 1 - - - - - RVR - RVR - SysTick reload value register - 0x4 - 0x20 - read-write - 0x00000000 - - - RELOAD - RELOAD value - 0 - 24 - - - - - CVR - CVR - SysTick current value register - 0x8 - 0x20 - read-write - 0x00000000 - - - CURRENT - Current counter value - 0 - 24 - - - - - CALIB - CALIB - SysTick calibration value register - 0xC - 0x20 - read-write - 0x00000000 - - - TENMS - Calibration value - 0 - 24 - - - SKEW - SKEW flag: Indicates whether the TENMS value is exact - 30 - 1 - - - NOREF - NOREF flag. Reads as zero - 31 - 1 - - - - - - - NVIC_STIR - Nested vectored interrupt controller - NVIC - 0xE000EF00 - - 0x0 - 0x5 - registers - - - - STIR - STIR - Software trigger interrupt register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTID - Software generated interrupt ID - 0 - 9 - - - - - - - FPU_CPACR - Floating point unit CPACR - FPU - 0xE000ED88 - - 0x0 - 0x5 - registers - - - - CPACR - CPACR - Coprocessor access control register - 0x0 - 0x20 - read-write - 0x00000000 - - - CP - CP - 20 - 4 - - - - - - - SCB_ACTRL - System control block ACTLR - SCB - 0xE000E008 - - 0x0 - 0x5 - registers - - - - ACTRL - ACTRL - Auxiliary control register - 0x0 - 0x20 - read-write - 0x00000000 - - - DISFOLD - DISFOLD - 2 - 1 - - - FPEXCODIS - FPEXCODIS - 10 - 1 - - - DISRAMODE - DISRAMODE - 11 - 1 - - - DISITMATBFLUSH - DISITMATBFLUSH - 12 - 1 - - - - - - - FPU - Floting point unit - FPU - 0xE000EF34 - - 0x0 - 0xD - registers - - - FPU - Floating point unit interrupt - 81 - - - - FPCCR - FPCCR - Floating-point context control register - 0x0 - 0x20 - read-write - 0x00000000 - - - LSPACT - LSPACT - 0 - 1 - - - USER - USER - 1 - 1 - - - THREAD - THREAD - 3 - 1 - - - HFRDY - HFRDY - 4 - 1 - - - MMRDY - MMRDY - 5 - 1 - - - BFRDY - BFRDY - 6 - 1 - - - MONRDY - MONRDY - 8 - 1 - - - LSPEN - LSPEN - 30 - 1 - - - ASPEN - ASPEN - 31 - 1 - - - - - FPCAR - FPCAR - Floating-point context address register - 0x4 - 0x20 - read-write - 0x00000000 - - - ADDRESS - Location of unpopulated floating-point - 3 - 29 - - - - - FPSCR - FPSCR - Floating-point status control register - 0x8 - 0x20 - read-write - 0x00000000 - - - IOC - Invalid operation cumulative exception bit - 0 - 1 - - - DZC - Division by zero cumulative exception bit. - 1 - 1 - - - OFC - Overflow cumulative exception bit - 2 - 1 - - - UFC - Underflow cumulative exception bit - 3 - 1 - - - IXC - Inexact cumulative exception bit - 4 - 1 - - - IDC - Input denormal cumulative exception bit. - 7 - 1 - - - RMode - Rounding Mode control field - 22 - 2 - - - FZ - Flush-to-zero mode control bit: - 24 - 1 - - - DN - Default NaN mode control bit - 25 - 1 - - - AHP - Alternative half-precision control bit - 26 - 1 - - - V - Overflow condition code flag - 28 - 1 - - - C - Carry condition code flag - 29 - 1 - - - Z - Zero condition code flag - 30 - 1 - - - N - Negative condition code flag - 31 - 1 - - - - - - - SCB - System control block - SCB - 0xE000ED00 - - 0x0 - 0x41 - registers - - - - CPUID - CPUID - CPUID base register - 0x0 - 0x20 - read-only - 0x410FC241 - - - Revision - Revision number - 0 - 4 - - - PartNo - Part number of the processor - 4 - 12 - - - Constant - Reads as 0xF - 16 - 4 - - - Variant - Variant number - 20 - 4 - - - Implementer - Implementer code - 24 - 8 - - - - - ICSR - ICSR - Interrupt control and state register - 0x4 - 0x20 - read-write - 0x00000000 - - - VECTACTIVE - Active vector - 0 - 9 - - - RETTOBASE - Return to base level - 11 - 1 - - - VECTPENDING - Pending vector - 12 - 7 - - - ISRPENDING - Interrupt pending flag - 22 - 1 - - - PENDSTCLR - SysTick exception clear-pending bit - 25 - 1 - - - PENDSTSET - SysTick exception set-pending bit - 26 - 1 - - - PENDSVCLR - PendSV clear-pending bit - 27 - 1 - - - PENDSVSET - PendSV set-pending bit - 28 - 1 - - - NMIPENDSET - NMI set-pending bit. - 31 - 1 - - - - - VTOR - VTOR - Vector table offset register - 0x8 - 0x20 - read-write - 0x00000000 - - - TBLOFF - Vector table base offset field - 9 - 21 - - - - - AIRCR - AIRCR - Application interrupt and reset control register - 0xC - 0x20 - read-write - 0x00000000 - - - VECTRESET - VECTRESET - 0 - 1 - - - VECTCLRACTIVE - VECTCLRACTIVE - 1 - 1 - - - SYSRESETREQ - SYSRESETREQ - 2 - 1 - - - PRIGROUP - PRIGROUP - 8 - 3 - - - ENDIANESS - ENDIANESS - 15 - 1 - - - VECTKEYSTAT - Register key - 16 - 16 - - - - - SCR - SCR - System control register - 0x10 - 0x20 - read-write - 0x00000000 - - - SLEEPONEXIT - SLEEPONEXIT - 1 - 1 - - - SLEEPDEEP - SLEEPDEEP - 2 - 1 - - - SEVEONPEND - Send Event on Pending bit - 4 - 1 - - - - - CCR - CCR - Configuration and control register - 0x14 - 0x20 - read-write - 0x00000000 - - - NONBASETHRDENA - Configures how the processor enters Thread mode - 0 - 1 - - - USERSETMPEND - USERSETMPEND - 1 - 1 - - - UNALIGN__TRP - UNALIGN_ TRP - 3 - 1 - - - DIV_0_TRP - DIV_0_TRP - 4 - 1 - - - BFHFNMIGN - BFHFNMIGN - 8 - 1 - - - STKALIGN - STKALIGN - 9 - 1 - - - DC - DC - 16 - 1 - - - IC - IC - 17 - 1 - - - BP - BP - 18 - 1 - - - - - SHPR1 - SHPR1 - System handler priority registers - 0x18 - 0x20 - read-write - 0x00000000 - - - PRI_4 - Priority of system handler 4 - 0 - 8 - - - PRI_5 - Priority of system handler 5 - 8 - 8 - - - PRI_6 - Priority of system handler 6 - 16 - 8 - - - - - SHPR2 - SHPR2 - System handler priority registers - 0x1C - 0x20 - read-write - 0x00000000 - - - PRI_11 - Priority of system handler 11 - 24 - 8 - - - - - SHPR3 - SHPR3 - System handler priority registers - 0x20 - 0x20 - read-write - 0x00000000 - - - PRI_14 - Priority of system handler 14 - 16 - 8 - - - PRI_15 - Priority of system handler 15 - 24 - 8 - - - - - SHCRS - SHCRS - System handler control and state register - 0x24 - 0x20 - read-write - 0x00000000 - - - MEMFAULTACT - Memory management fault exception active bit - 0 - 1 - - - BUSFAULTACT - Bus fault exception active bit - 1 - 1 - - - USGFAULTACT - Usage fault exception active bit - 3 - 1 - - - SVCALLACT - SVC call active bit - 7 - 1 - - - MONITORACT - Debug monitor active bit - 8 - 1 - - - PENDSVACT - PendSV exception active bit - 10 - 1 - - - SYSTICKACT - SysTick exception active bit - 11 - 1 - - - USGFAULTPENDED - Usage fault exception pending bit - 12 - 1 - - - MEMFAULTPENDED - Memory management fault exception pending bit - 13 - 1 - - - BUSFAULTPENDED - Bus fault exception pending bit - 14 - 1 - - - SVCALLPENDED - SVC call pending bit - 15 - 1 - - - MEMFAULTENA - Memory management fault enable bit - 16 - 1 - - - BUSFAULTENA - Bus fault enable bit - 17 - 1 - - - USGFAULTENA - Usage fault enable bit - 18 - 1 - - - - - CFSR_UFSR_BFSR_MMFSR - CFSR_UFSR_BFSR_MMFSR - Configurable fault status register - 0x28 - 0x20 - read-write - 0x00000000 - - - IACCVIOL - IACCVIOL - 0 - 1 - - - DACCVIOL - DACCVIOL - 1 - 1 - - - MUNSTKERR - MUNSTKERR - 3 - 1 - - - MSTKERR - MSTKERR - 4 - 1 - - - MLSPERR - MLSPERR - 5 - 1 - - - MMARVALID - MMARVALID - 7 - 1 - - - IBUSERR - Instruction bus error - 8 - 1 - - - PRECISERR - Precise data bus error - 9 - 1 - - - IMPRECISERR - Imprecise data bus error - 10 - 1 - - - UNSTKERR - Bus fault on unstacking for a return from exception - 11 - 1 - - - STKERR - Bus fault on stacking for exception entry - 12 - 1 - - - LSPERR - Bus fault on floating-point lazy state preservation - 13 - 1 - - - BFARVALID - Bus Fault Address Register (BFAR) valid flag - 15 - 1 - - - UNDEFINSTR - Undefined instruction usage fault - 16 - 1 - - - INVSTATE - Invalid state usage fault - 17 - 1 - - - INVPC - Invalid PC load usage fault - 18 - 1 - - - NOCP - No coprocessor usage fault. - 19 - 1 - - - UNALIGNED - Unaligned access usage fault - 24 - 1 - - - DIVBYZERO - Divide by zero usage fault - 25 - 1 - - - - - HFSR - HFSR - Hard fault status register - 0x2C - 0x20 - read-write - 0x00000000 - - - VECTTBL - Vector table hard fault - 1 - 1 - - - FORCED - Forced hard fault - 30 - 1 - - - DEBUG_VT - Reserved for Debug use - 31 - 1 - - - - - MMFAR - MMFAR - Memory management fault address register - 0x34 - 0x20 - read-write - 0x00000000 - - - ADDRESS - Memory management fault address - 0 - 32 - - - - - BFAR - BFAR - Bus fault address register - 0x38 - 0x20 - read-write - 0x00000000 - - - ADDRESS - Bus fault address - 0 - 32 - - - - - - - PF - Processor features - PF - 0xE000ED78 - - 0x0 - 0xD - registers - - - - CLIDR - CLIDR - Cache Level ID register - 0x0 - 0x20 - read-only - 0x09000003 - - - CL1 - CL1 - 0 - 3 - - - CL2 - CL2 - 3 - 3 - - - CL3 - CL3 - 6 - 3 - - - CL4 - CL4 - 9 - 3 - - - CL5 - CL5 - 12 - 3 - - - CL6 - CL6 - 15 - 3 - - - CL7 - CL7 - 18 - 3 - - - LoUIS - LoUIS - 21 - 3 - - - LoC - LoC - 24 - 3 - - - LoU - LoU - 27 - 3 - - - - - CTR - CTR - Cache Type register - 0x4 - 0x20 - read-only - 0x8303C003 - - - _IminLine - IminLine - 0 - 4 - - - DMinLine - DMinLine - 16 - 4 - - - ERG - ERG - 20 - 4 - - - CWG - CWG - 24 - 4 - - - Format - Format - 29 - 3 - - - - - CCSIDR - CCSIDR - Cache Size ID register - 0x8 - 0x20 - read-only - 0x00000000 - - - LineSize - LineSize - 0 - 3 - - - Associativity - Associativity - 3 - 10 - - - NumSets - NumSets - 13 - 15 - - - WA - WA - 28 - 1 - - - RA - RA - 29 - 1 - - - WB - WB - 30 - 1 - - - WT - WT - 31 - 1 - - - - - - - AC - Access control - AC - 0xE000EF90 - - 0x0 - 0x1D - registers - - - - ITCMCR - ITCMCR - Instruction and Data Tightly-Coupled Memory Control Registers - 0x0 - 0x20 - read-write - 0x00000000 - - - EN - EN - 0 - 1 - - - RMW - RMW - 1 - 1 - - - RETEN - RETEN - 2 - 1 - - - SZ - SZ - 3 - 4 - - - - - DTCMCR - DTCMCR - Instruction and Data Tightly-Coupled Memory Control Registers - 0x4 - 0x20 - read-write - 0x00000000 - - - EN - EN - 0 - 1 - - - RMW - RMW - 1 - 1 - - - RETEN - RETEN - 2 - 1 - - - SZ - SZ - 3 - 4 - - - - - AHBPCR - AHBPCR - AHBP Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - EN - EN - 0 - 1 - - - SZ - SZ - 1 - 3 - - - - - CACR - CACR - Auxiliary Cache Control register - 0xC - 0x20 - read-write - 0x00000000 - - - SIWT - SIWT - 0 - 1 - - - ECCEN - ECCEN - 1 - 1 - - - FORCEWT - FORCEWT - 2 - 1 - - - - - AHBSCR - AHBSCR - AHB Slave Control register - 0x10 - 0x20 - read-write - 0x00000000 - - - CTL - CTL - 0 - 2 - - - TPRI - TPRI - 2 - 9 - - - INITCOUNT - INITCOUNT - 11 - 5 - - - - - ABFSR - ABFSR - Auxiliary Bus Fault Status register - 0x18 - 0x20 - read-write - 0x00000000 - - - ITCM - ITCM - 0 - 1 - - - DTCM - DTCM - 1 - 1 - - - AHBP - AHBP - 2 - 1 - - - AXIM - AXIM - 3 - 1 - - - EPPB - EPPB - 4 - 1 - - - AXIMTYPE - AXIMTYPE - 8 - 2 - - - - - - - \ No newline at end of file diff --git a/Tools/Toolsets/pico.json b/Tools/Toolsets/pico.json deleted file mode 100644 index 15f589c1..00000000 --- a/Tools/Toolsets/pico.json +++ /dev/null @@ -1,24 +0,0 @@ -{ - "schemaVersion": "1.0", - "swiftCompiler": { - "extraCLIOptions": [ - "-Xfrontend", "-disable-stack-protector", - "-enable-experimental-feature", "Embedded", - "-Xcc", "-mcpu=cortex-m0plus" - ] - }, - "linker": { - "extraCLIOptions": [ - "-arch", "armv6m", - "-dead_strip", - "-static", - "-e", "_reset", - "-no_zero_fill_sections", - "-segalign", "4", - "-segaddr", "__RESET", "0x20000000", - "-segaddr", "__VECTORS", "0x20000100", - "-seg1addr", "0x20000200", - "-pagezero_size", "0" - ] - } -} diff --git a/Tools/Toolsets/pico2.json b/Tools/Toolsets/pico2.json deleted file mode 100644 index 873afca3..00000000 --- a/Tools/Toolsets/pico2.json +++ /dev/null @@ -1,23 +0,0 @@ -{ - "schemaVersion": "1.0", - "swiftCompiler": { - "extraCLIOptions": [ - "-Xfrontend", "-disable-stack-protector", - "-enable-experimental-feature", "Embedded" - ] - }, - "linker": { - "extraCLIOptions": [ - "-arch", "armv7em", - "-dead_strip", - "-static", - "-e", "_reset", - "-no_zero_fill_sections", - "-segalign", "4", - "-segaddr", "__VECTORS", "0x20000000", - "-segaddr", "__RESET", "0x20000200", - "-seg1addr", "0x20000300", - "-pagezero_size", "0" - ] - } -} diff --git a/Tools/Toolsets/rpi-5-elf.json b/Tools/Toolsets/rpi-5-elf.json deleted file mode 100644 index 88d9a133..00000000 --- a/Tools/Toolsets/rpi-5-elf.json +++ /dev/null @@ -1,19 +0,0 @@ -{ - "schemaVersion": "1.0", - "swiftCompiler": { - "extraCLIOptions": [ - "-Xfrontend", "-disable-stack-protector", - "-Xfrontend", "-function-sections", - "-enable-experimental-feature", "Embedded", - "-Xfrontend", "-mergeable-symbols", - "-Xclang-linker", "-fuse-ld=lld", - "-Xclang-linker", "-nostdlib" - ] - }, - "linker": { - "extraCLIOptions": [ - "-T", "Sources/Support/linkerscript.ld", - "--unresolved-symbols=ignore-in-object-files" - ] - } -} diff --git a/Tools/Toolsets/stm32f74x-lcd.json b/Tools/Toolsets/stm32f74x-lcd.json deleted file mode 100644 index e6983782..00000000 --- a/Tools/Toolsets/stm32f74x-lcd.json +++ /dev/null @@ -1,22 +0,0 @@ -{ - "schemaVersion": "1.0", - "swiftCompiler": { - "extraCLIOptions": [ - "-Xfrontend", "-disable-stack-protector", - "-enable-experimental-feature", "Embedded" - ] - }, - "linker": { - "extraCLIOptions": [ - "-arch", "armv7em", - "-dead_strip", - "-static", - "-e", "_reset", - "-no_zero_fill_sections", - "-segalign", "4", - "-segaddr", "__VECTORS", "0x00200000", - "-seg1addr", "0x00200200", - "-pagezero_size", "0" - ] - } -} diff --git a/Tools/Toolsets/stm32f74x.json b/Tools/Toolsets/stm32f74x.json deleted file mode 100644 index b22fb6e6..00000000 --- a/Tools/Toolsets/stm32f74x.json +++ /dev/null @@ -1,22 +0,0 @@ -{ - "schemaVersion": "1.0", - "swiftCompiler": { - "extraCLIOptions": [ - "-Xfrontend", "-disable-stack-protector", - "-enable-experimental-feature", "Embedded" - ] - }, - "linker": { - "extraCLIOptions": [ - "-arch", "armv7em", - "-dead_strip", - "-static", - "-e", "_reset", - "-no_zero_fill_sections", - "-segalign", "4", - "-segaddr", "__VECTORS", "0x20010000", - "-seg1addr", "0x20010200", - "-pagezero_size", "0" - ] - } -} diff --git a/Tools/elf2hex.py b/Tools/elf2hex.py deleted file mode 100755 index acb84502..00000000 --- a/Tools/elf2hex.py +++ /dev/null @@ -1,139 +0,0 @@ -#! /usr/bin/env -S uv run --script - -# /// script -# dependencies = [ -# "pyelftools==0.31", -# ] -# /// - -# This source file is part of the Swift open source project -# -# Copyright (c) 2023 Apple Inc. and the Swift project authors. -# Licensed under Apache License v2.0 with Runtime Library Exception -# -# See https://swift.org/LICENSE.txt for license information - -# -# elf2hex -- Converts a statically-linked ELF executable into an "Intel HEX" -# file format suitable for flashing onto some embedded devices. -# -# Usage: -# $ elf2hex.py [--symbol-map ] [--relocate-data-segment] -# -# Example: -# $ elf2hex.py ./blink ./blink.hex --symbol-map ./blink.symbols -# -# The --relocate-data-segment option expects to be able to locate symbols with names -# - __data_start -# - __flash_data_start -# - __flash_data_len -# and then it physically relocates a segment located at __data_start to -# __flash_data_start, without changing virtual/physical addresses of any ELF -# headers. This means that the .hex file is not validly mapped until a boot-time -# reverse relocation step. -# -# See the linker script used in a particular demo folder for a detailed -# explanation of the linking, packing, and runtime relocation scheme. -# - -import argparse -import json -import pathlib - -import elftools.elf.elffile - - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument('input') - parser.add_argument('output') - parser.add_argument('--symbol-map') - parser.add_argument('--relocate-data-segment', action='store_true') - args = parser.parse_args() - - inf = open(args.input, "rb") - outf = open(args.output, "wb") - - def emitrecord(record): - checksum = 0 - pos = 0 - while pos < len(record): - checksum = (checksum + int(record[pos:pos + 2], 16)) % 256 - pos += 2 - checksum = (256 - checksum) % 256 - outf.write((":" + record + f"{checksum:02X}" + "\n").encode()) - - def emit(vmaddr, data): - pos = 0 - while pos < len(data): - chunklen = min(16, len(data) - pos) - chunk = data[pos:pos + chunklen] - chunkhex = chunk.hex().upper() - - assert vmaddr < 0x100000000, f"vmaddr: {vmaddr:x}" - vmaddr_high = (vmaddr >> 16) & 0xffff - recordtype = "04" # Extended Linear Address - emitrecord(f"{2:02X}{0:04X}{recordtype}{vmaddr_high:04X}") - - vmaddr_low = vmaddr & 0xffff - recordtype = "00" # Data - emitrecord(f"{chunklen:02X}{vmaddr_low:04X}{recordtype}{chunkhex}") - - pos += chunklen - vmaddr += chunklen - - elffile = elftools.elf.elffile.ELFFile(inf) - - symbol_map = {} - symtab_section = elffile.get_section_by_name(".symtab") - for s in symtab_section.iter_symbols(): - if s.entry.st_info.type not in ["STT_FUNC", "STT_NOTYPE"]: - continue - if s.name == "": - continue - symbol_map[s.name] = s.entry.st_value - - if args.symbol_map is not None: - pathlib.Path(args.symbol_map).write_text(json.dumps(symbol_map)) - - relocations = {} - if args.relocate_data_segment: - __flash_data_start = symbol_map["__flash_data_start"] - __data_start = symbol_map["__data_start"] - __flash_data_len = symbol_map["__flash_data_len"] - print("Relocation info:") - print(f" __flash_data_start = 0x{__flash_data_start:08x}") - print(f" __data_start = 0x{__data_start:08x}") - print(f" __flash_data_len = 0x{__flash_data_len:08x}") - relocations = {__data_start: __flash_data_start} - - for segment in elffile.iter_segments(): - if segment.header.p_type != "PT_LOAD": - continue - vmaddr = segment.header.p_paddr - data = segment.data() - flags = "" - flags += "r" if segment.header.p_flags & 0x4 else "-" - flags += "w" if segment.header.p_flags & 0x2 else "-" - flags += "x" if segment.header.p_flags & 0x1 else "-" - print(f"PT_LOAD {flags} at 0x{segment.header.p_paddr:08x} - " - f"0x{segment.header.p_paddr + len(data):08x}, " - f"size {len(data)} " - f"(0x{len(data):04x})") - placement_addr = segment.header.p_paddr - if segment.header.p_paddr in relocations: - placement_addr = relocations[segment.header.p_paddr] - print(f" ... relocating to 0x{placement_addr:08x}") - emit(placement_addr, data) - - chunklen = 0 - vmaddr = 0 - recordtype = "01" # EOF - emitrecord(f"{chunklen:02X}{vmaddr:04X}{recordtype}") - - inf.close() - outf.close() - - -if __name__ == '__main__': - main() diff --git a/Tools/macho2bin.py b/Tools/macho2bin.py deleted file mode 100755 index 842b4b2f..00000000 --- a/Tools/macho2bin.py +++ /dev/null @@ -1,111 +0,0 @@ -#! /usr/bin/env -S uv run --script - -# /// script -# dependencies = [ -# "macholib==1.16.3", -# ] -# /// - -# This source file is part of the Swift open source project -# -# Copyright (c) 2023 Apple Inc. and the Swift project authors. -# Licensed under Apache License v2.0 with Runtime Library Exception -# -# See https://swift.org/LICENSE.txt for license information - -# -# macho2bin -- Converts a statically-linked executable Mach-O into a flat "BIN" file -# suitable for flashing as a single contiguous blob onto some embedded devices. Note -# that this format assumes the embedded device can boot from a state where the entire -# firmware (all segments) are flashed contigously into one smalle address range. This -# is true for e.g. the STM32F746 devices if we place the vector table at 0x00200000, -# and code and data right after it, as the vector table also contains a pointer to the -# initial PC. This setup might not work for other devices. -# -# Usage: -# $ macho2bin.py --base-address --segments -# -# -# Example: -# $ macho2bin.py ./blink ./blink.bin --base-address 0x00200000 --segments -# '__TEXT,__DATA,__VECTORS' -# -# Requirements and notes: -# * The output BIN file is a flat contiguous representation of the segments -# (--segments) based on their VM addresses. -# * The BIN file's first byte corresponds to the specified base address -# (--base-address). -# * Any gaps between segments are filled with zero bytes. -# * Because of that, you want the input Mach-O to have all segments "close", and not -# have gaps. -# - -import argparse -import os - -from macholib import MachO -from macholib import mach_o - - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument("input") - parser.add_argument("output") - parser.add_argument("--base-address", required=True) - parser.add_argument("--segments", required=True) - args = parser.parse_args() - args.base_address = int(args.base_address, 16) - args.segments = args.segments.split(",") - - segments = [] - macho = MachO.MachO(args.input) - assert len(macho.headers) == 1 - mh = macho.headers[0] - for command in mh.commands: - if isinstance(command[1], mach_o.segment_command): - (_, segment, sections) = command - segname = segment.segname.decode().strip("\0") - if segname not in args.segments: - continue - - with open(args.input, "rb") as f: - f.seek(mh.offset + segment.fileoff) - data = f.read(segment.filesize) - segments.append( - {"vmaddr": segment.vmaddr, "data": data, "name": segname} - ) - - segments = sorted(segments, key=lambda x: x["vmaddr"]) - - assert segments[0]["vmaddr"] == args.base_address, ( - f"first segment's vmaddr 0x{segments[0]['vmaddr']:08x} does not match the" - f" passed --base-address 0x{args.base_address:08x}" - ) - - if os.path.exists(args.output): - os.unlink(args.output) - - vmaddr = segments[0]["vmaddr"] - with open(args.output, "wb") as f: - for segment in segments: - gap = segment["vmaddr"] - vmaddr - if gap != 0: - print( - f"Writing gap of size {gap} (0x{gap:0x}) at vmaddr 0x{vmaddr:08x}" - ) - f.write(b"\0" * gap) - assert gap >= 0 - vmaddr = segment["vmaddr"] - print( - f"Writing segment {segment['name']} size" - f" {len(segment['data'])} (0x{len(segment['data']):x}) at vmaddr" - f" 0x{vmaddr:08x}" - ) - f.write(segment["data"]) - vmaddr = segment["vmaddr"] + len(segment["data"]) - - print(f"Produced {args.output} with {vmaddr - args.base_address} bytes") - - -if __name__ == "__main__": - main() diff --git a/Tools/macho2uf2.py b/Tools/macho2uf2.py deleted file mode 100755 index 39acd6c3..00000000 --- a/Tools/macho2uf2.py +++ /dev/null @@ -1,139 +0,0 @@ -#! /usr/bin/env -S uv run --script - -# /// script -# dependencies = [ -# "macholib==1.16.3", -# ] -# /// - -# This source file is part of the Swift open source project -# -# Copyright (c) 2023 Apple Inc. and the Swift project authors. -# Licensed under Apache License v2.0 with Runtime Library Exception -# -# See https://swift.org/LICENSE.txt for license information - -# -# macho2uf2 -- Converts a statically-linked executable Mach-O into a flat "UF2" file -# suitable for flashing as a single contiguous blob onto some embedded devices, in -# particular Raspberry Pi Pico (W). Note that the UF2 format allows for discontiguous -# memory regions, but this utility does not support that. -# -# Usage: -# $ macho2uf2.py --base-address --segments -# -# -# Example: -# $ macho2uf2.py ./blink ./blink.uf2 --base-address 0x00200000 --segments -# '__TEXT,__DATA,__VECTORS' -# -# Requirements and notes: -# * The output UF2 file is a flat contiguous representation of the segments -# (--segments) based on their VM addresses. -# * The UF2 file's first byte corresponds to the specified base address -# (--base-address). -# * Any gaps between segments are filled with zero bytes. -# * Because of that, you want the input Mach-O to have all segments "close", and not -# have gaps. -# - -import argparse -import os -import struct -import subprocess - -MY_DIR = os.path.dirname(os.path.abspath(__file__)) - - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument("input") - parser.add_argument("output") - parser.add_argument("--base-address", required=True) - parser.add_argument("--segments", required=True) - parser.add_argument("--pico-family", required=True) - args = parser.parse_args() - args.base_address = int(args.base_address, 16) - args.segments = args.segments.split(",") - if args.pico_family == "rp2040": - family_id = 0xE48BFF56 - add_errata_block = False - elif args.pico_family == "rp2350": - family_id = 0xE48BFF59 - add_errata_block = True - else: - assert False - - subprocess.check_call( - [ - MY_DIR + "/macho2bin.py", - args.input, - args.input + ".bin", - "--base-address", - "0x%08x" % args.base_address, - "--segments", - ",".join(args.segments), - ] - ) - - def emit_block(output, block, vmaddr, block_number, num_blocks, family_id): - assert len(block) <= 256 - - if len(block) < 256: - block += b"\0" * (256 - len(block)) - - # UF2_Block header - output += struct.pack("/export.sh +idf.py set-target esp32c6 +idf.py build +``` + +## Running + +- Connect the Esp32-C6-Bug board (or any other board with integrated LED on GPIO pin 8) over a USB cable to your Mac. Alternatively you can just connect external LED to GPIO pin 8 on any other board. +- Connect RX pin of USB-UART converter to TX0 pin of your board if you need serial output. You may also need to connect GND converter pin to the GND pin of the board. +- Use `idf.py` to upload the firmware and to run it: + +```sh +idf.py flash +``` + +- The LED should be blinking now. + +### Simulating in VS Code + +- Build the project, to generate binaries for simulation +- Install [Wokwi for VS Code](https://docs.wokwi.com/vscode/getting-started/). +- Open the `diagram.json` file. +- Click the Play button to start simulation. +- Click the Pause button to freeze simulation and display states of GPIOs. + diff --git a/esp32-led-blink-sdk/diagram.json b/arduino-esp32-led-blink-sdk/diagram.json similarity index 100% rename from esp32-led-blink-sdk/diagram.json rename to arduino-esp32-led-blink-sdk/diagram.json diff --git a/esp32-led-blink-sdk/main/BridgingHeader.h b/arduino-esp32-led-blink-sdk/main/BridgingHeader.h similarity index 55% rename from esp32-led-blink-sdk/main/BridgingHeader.h rename to arduino-esp32-led-blink-sdk/main/BridgingHeader.h index 4c7c46cf..c0a19063 100644 --- a/esp32-led-blink-sdk/main/BridgingHeader.h +++ b/arduino-esp32-led-blink-sdk/main/BridgingHeader.h @@ -2,16 +2,26 @@ // // This source file is part of the Swift open source project // -// Copyright (c) 2024 Apple Inc. and the Swift project authors. +// Copyright (c) 2025 Apple Inc. and the Swift project authors. // Licensed under Apache License v2.0 with Runtime Library Exception // // See https://swift.org/LICENSE.txt for license information // //===----------------------------------------------------------------------===// +// For some reason swiftc's clang++ defines `__UINT32_TYPE__` as `unsigned int` (g++'s x86 behaviour) not `long unsigned int` (g++'s riscv32 behaviour) +#undef __UINT32_TYPE__ +#undef uint32_t +#define __UINT32_TYPE__ long unsigned int +#define uint32_t __UINT32_TYPE__ +#define _UINT32_T_DECLARED + #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "driver/gpio.h" #include "sdkconfig.h" + +#include diff --git a/esp32-led-blink-sdk/main/CMakeLists.txt b/arduino-esp32-led-blink-sdk/main/CMakeLists.txt similarity index 95% rename from esp32-led-blink-sdk/main/CMakeLists.txt rename to arduino-esp32-led-blink-sdk/main/CMakeLists.txt index be495aab..a1314a17 100644 --- a/esp32-led-blink-sdk/main/CMakeLists.txt +++ b/arduino-esp32-led-blink-sdk/main/CMakeLists.txt @@ -2,6 +2,7 @@ idf_component_register( SRCS /dev/null # We don't have any C++ sources PRIV_INCLUDE_DIRS "." + REQUIRES arduino ) idf_build_get_property(target IDF_TARGET) @@ -39,12 +40,12 @@ endforeach() # Swift compiler flags to build in Embedded Swift mode, optimize for size, choose the right ISA, ABI, etc. target_compile_options(${COMPONENT_LIB} PUBLIC "$<$:SHELL: -target riscv32-none-none-eabi - -Xfrontend -function-sections -enable-experimental-feature Embedded -wmo -parse-as-library -Osize - -Xcc ${march_flag} -Xcc ${mabi_flag} -Xcc -fno-pic -Xcc -fno-pie - + -Xfrontend -function-sections -enable-experimental-feature Embedded -wmo -parse-as-library -Osize -cxx-interoperability-mode=default + -Xcc ${march_flag} -Xcc ${mabi_flag} -Xcc -fno-pic -Xcc -fno-pie -Xcc -fno-exceptions + -pch-output-dir /tmp -Xfrontend -enable-single-module-llvm-emission - + ${SWIFT_INCLUDES} -import-bridging-header ${CMAKE_CURRENT_LIST_DIR}/BridgingHeader.h diff --git a/arduino-esp32-led-blink-sdk/main/Kconfig.projbuild b/arduino-esp32-led-blink-sdk/main/Kconfig.projbuild new file mode 100644 index 00000000..94f2f0e1 --- /dev/null +++ b/arduino-esp32-led-blink-sdk/main/Kconfig.projbuild @@ -0,0 +1,8 @@ +# put here your custom config value +menu "Example Configuration" +config LED_BLINK_INTERVAL_MS + int "LED blinking interval / ms" + default 500 + help + Interval in milliseconds between turning the LED on/off +endmenu diff --git a/rpi-4b-blink/Sources/Support/include/Support.h b/arduino-esp32-led-blink-sdk/main/Led.swift similarity index 62% rename from rpi-4b-blink/Sources/Support/include/Support.h rename to arduino-esp32-led-blink-sdk/main/Led.swift index deac9bed..8a504146 100644 --- a/rpi-4b-blink/Sources/Support/include/Support.h +++ b/arduino-esp32-led-blink-sdk/main/Led.swift @@ -9,8 +9,15 @@ // //===----------------------------------------------------------------------===// -#pragma once +// A simple "overlay" to provide nicer APIs in Swift +struct Led { + var ledPin: UInt8 + init(gpioPin: gpio_num_t) { + ledPin = UInt8(gpioPin.rawValue) + pinMode(ledPin, UInt8(OUTPUT)) + } -static inline __attribute((always_inline)) void nop() { - asm volatile("nop"); + func setLed(value: Bool) { + digitalWrite(ledPin, value ? 1 : 0) + } } diff --git a/esp32-led-blink-sdk/main/Main.swift b/arduino-esp32-led-blink-sdk/main/Main.swift similarity index 55% rename from esp32-led-blink-sdk/main/Main.swift rename to arduino-esp32-led-blink-sdk/main/Main.swift index 9b2d4cc0..7509e935 100644 --- a/esp32-led-blink-sdk/main/Main.swift +++ b/arduino-esp32-led-blink-sdk/main/Main.swift @@ -2,25 +2,27 @@ // // This source file is part of the Swift open source project // -// Copyright (c) 2024 Apple Inc. and the Swift project authors. +// Copyright (c) 2025 Apple Inc. and the Swift project authors. // Licensed under Apache License v2.0 with Runtime Library Exception // // See https://swift.org/LICENSE.txt for license information // //===----------------------------------------------------------------------===// -// The code will blink an LED on GPIO8. To change the pin, modify Led(gpioPin: 8) -@_cdecl("app_main") -func main() { - print("Hello from Swift on ESP32-C6!") +// The code will blink an LED on GPIO8. To change the pin, modify Led(gpioPin: GPIO_NUM_8) + +var ledValue: Bool = false +var led: Led? - var ledValue: Bool = false - let blinkDelayMs: UInt32 = 500 - let led = Led(gpioPin: 8) +@_cdecl("_Z5setupv") +func setup() { + print("Hello from Swift on ESP32-C6!") + led = Led(gpioPin: GPIO_NUM_8) +} - while true { - led.setLed(value: ledValue) - ledValue.toggle() // Toggle the boolean value - vTaskDelay(blinkDelayMs / (1000 / UInt32(configTICK_RATE_HZ))) - } +@_cdecl("_Z4loopv") +func loop() { + led?.setLed(value: ledValue) + ledValue.toggle() // Toggle the boolean value + delay(UInt(CONFIG_LED_BLINK_INTERVAL_MS)) } diff --git a/arduino-esp32-led-blink-sdk/main/component.mk b/arduino-esp32-led-blink-sdk/main/component.mk new file mode 100644 index 00000000..61f8990c --- /dev/null +++ b/arduino-esp32-led-blink-sdk/main/component.mk @@ -0,0 +1,8 @@ +# +# Main component makefile. +# +# This Makefile can be left empty. By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# diff --git a/arduino-esp32-led-blink-sdk/main/idf_component.yml b/arduino-esp32-led-blink-sdk/main/idf_component.yml new file mode 100644 index 00000000..cdf6c3da --- /dev/null +++ b/arduino-esp32-led-blink-sdk/main/idf_component.yml @@ -0,0 +1,19 @@ +## IDF Component Manager Manifest File +dependencies: + # # Put list of dependencies here + # # For components maintained by Espressif: + # component: "~1.0.0" + # # For 3rd party components: + # username/component: ">=1.0.0,<2.0.0" + # username2/component2: + # version: "~1.0.0" + # # For transient dependencies `public` flag can be set. + # # `public` flag doesn't have an effect dependencies of the `main` component. + # # All dependencies of `main` are public by default. + # public: true + + ## Required IDF version + idf: ">=5.3,<5.5" + arduino: # Can't be defined as the espressif/arduino-esp32 shorthand since the library name must be 'arduino' for libraries that depend on it + git: https://github.com/espressif/arduino-esp32.git + version: 3.2.0 diff --git a/arduino-esp32-led-blink-sdk/sdkconfig.defaults b/arduino-esp32-led-blink-sdk/sdkconfig.defaults new file mode 100644 index 00000000..d4f9762e --- /dev/null +++ b/arduino-esp32-led-blink-sdk/sdkconfig.defaults @@ -0,0 +1,4 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_MBEDTLS_PSK_MODES=y +CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y +CONFIG_AUTOSTART_ARDUINO=y diff --git a/esp32-led-blink-sdk/wokwi.toml b/arduino-esp32-led-blink-sdk/wokwi.toml similarity index 100% rename from esp32-led-blink-sdk/wokwi.toml rename to arduino-esp32-led-blink-sdk/wokwi.toml diff --git a/arduino-esp32-wifi-scan-sdk/CMakeLists.txt b/arduino-esp32-wifi-scan-sdk/CMakeLists.txt new file mode 100644 index 00000000..bda69778 --- /dev/null +++ b/arduino-esp32-wifi-scan-sdk/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.5) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(app-template) diff --git a/arduino-esp32-wifi-scan-sdk/README.md b/arduino-esp32-wifi-scan-sdk/README.md new file mode 100644 index 00000000..b7f3389d --- /dev/null +++ b/arduino-esp32-wifi-scan-sdk/README.md @@ -0,0 +1,48 @@ +# arduino-esp32-wifi-scan-sdk + +This example demonstrates how to integrate with the ESP-IDF SDK via CMake and how to use the Arduino Wi-Fi library to scan for nearby networks from Swift. This example is specifically made for the RISC-V MCUs from ESP32 (the Xtensa MCUs are not currently supported by Swift). + +## Requirements + +- Set up **version v5.4** (required for this `arduino-esp32` version) of the [ESP-IDF](https://docs.espressif.com/projects/esp-idf/en/v5.4/esp32/) development environment. Follow the steps in the [ESP32-C6 "Get Started" guide](https://docs.espressif.com/projects/esp-idf/en/v5.4/esp32c6/get-started/index.html). + - Make sure you specifically set up development for the RISC-V ESP32-C6, and not the Xtensa based products. + - If you have a different version of ESP-IDF installed, make sure to also delete `~/.espressif` before running `install.sh` + +```sh +rm -rf ~/esp-idf ~/.espressif # Remove old installation files +git clone --recurse-submodules https://github.com/espressif/esp-idf.git ~/esp-idf +cd ~/esp-idf +git checkout release/v5.4 +git submodule update --init --recursive +./install.sh +idf_tools.py install-python-env +. ./export.sh +``` + +- Before trying to use Swift with the ESP-IDF SDK, make sure your environment works and can build the provided C/C++ sample projects, in particular: + - Try building and running the "get-started/blink" example from ESP-IDF written in C. + +## Building + +- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. +- If needed, run export.sh to get access to the idf.py script from ESP-IDF. +- Specify the nightly toolchain to be used via the `TOOLCHAINS` environment variable and the target board type by using `idf.py set-target`. +```sh +cd arduino-esp32-wifi-scan-sdk +export TOOLCHAINS=... +. /export.sh +idf.py set-target esp32c6 +idf.py build +``` + +## Running + +- Connect any board with an ESP32-C6 +- Connect the RX and TX pins of your USB-UART converter to the TX0 and RX0 respective pins of your board. You may also need to connect the GND converter pin to the GND pin of the board. +- Use `idf.py` to upload the firmware and to run it: + +```sh +idf.py flash monitor +``` + +- You should see a list of discovered Wi-Fi APs being printed every 5 seconds diff --git a/stm32-lvgl/Sources/CLVGL/include/module.modulemap b/arduino-esp32-wifi-scan-sdk/main/ArduinoString.swift similarity index 52% rename from stm32-lvgl/Sources/CLVGL/include/module.modulemap rename to arduino-esp32-wifi-scan-sdk/main/ArduinoString.swift index 0961fcc6..a3610a63 100644 --- a/stm32-lvgl/Sources/CLVGL/include/module.modulemap +++ b/arduino-esp32-wifi-scan-sdk/main/ArduinoString.swift @@ -9,7 +9,15 @@ // //===----------------------------------------------------------------------===// -module CLVGL [system] { - header "CLVGL.h" - export * +public typealias ArduinoString = String + +extension ArduinoString: CustomStringConvertible { + public var description: Swift.String { + let size = self.length() + 1 + let buffer = UnsafeMutablePointer.allocate(capacity: Int(size)) + self.getBytes(buffer, size) + let result = Swift.String(cString: UnsafePointer(buffer)) + buffer.deallocate() + return result + } } diff --git a/arduino-esp32-wifi-scan-sdk/main/BridgingHeader.h b/arduino-esp32-wifi-scan-sdk/main/BridgingHeader.h new file mode 100644 index 00000000..3d6ac7e7 --- /dev/null +++ b/arduino-esp32-wifi-scan-sdk/main/BridgingHeader.h @@ -0,0 +1,31 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +// For some reason swiftc's clang++ defines `__UINT32_TYPE__` as `unsigned int` (g++'s x86 behaviour) not `long unsigned int` (g++'s riscv32 behaviour) +#undef __UINT32_TYPE__ +#undef uint32_t +#define __UINT32_TYPE__ long unsigned int +#define uint32_t __UINT32_TYPE__ +#define _UINT32_T_DECLARED + +#include +#include +#include +#include + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "driver/gpio.h" +#include "sdkconfig.h" + +#include +#include +#include diff --git a/esp32-led-strip-sdk/main/CMakeLists.txt b/arduino-esp32-wifi-scan-sdk/main/CMakeLists.txt similarity index 94% rename from esp32-led-strip-sdk/main/CMakeLists.txt rename to arduino-esp32-wifi-scan-sdk/main/CMakeLists.txt index fc2ecd0f..a50a389f 100644 --- a/esp32-led-strip-sdk/main/CMakeLists.txt +++ b/arduino-esp32-wifi-scan-sdk/main/CMakeLists.txt @@ -2,6 +2,7 @@ idf_component_register( SRCS /dev/null # We don't have any C++ sources PRIV_INCLUDE_DIRS "." + REQUIRES arduino ) idf_build_get_property(target IDF_TARGET) @@ -39,12 +40,12 @@ endforeach() # Swift compiler flags to build in Embedded Swift mode, optimize for size, choose the right ISA, ABI, etc. target_compile_options(${COMPONENT_LIB} PUBLIC "$<$:SHELL: -target riscv32-none-none-eabi - -Xfrontend -function-sections -enable-experimental-feature Embedded -wmo -parse-as-library -Osize - -Xcc ${march_flag} -Xcc ${mabi_flag} -Xcc -fno-pic -Xcc -fno-pie - + -Xfrontend -function-sections -enable-experimental-feature Embedded -wmo -parse-as-library -Osize -cxx-interoperability-mode=default + -Xcc ${march_flag} -Xcc ${mabi_flag} -Xcc -fno-pic -Xcc -fno-pie -Xcc -fno-exceptions + -pch-output-dir /tmp -Xfrontend -enable-single-module-llvm-emission - + ${SWIFT_INCLUDES} -import-bridging-header ${CMAKE_CURRENT_LIST_DIR}/BridgingHeader.h @@ -61,7 +62,7 @@ enable_language(Swift) target_sources(${COMPONENT_LIB} PRIVATE Main.swift - LedStrip.swift + ArduinoString.swift ) add_custom_command( diff --git a/arduino-esp32-wifi-scan-sdk/main/Kconfig.projbuild b/arduino-esp32-wifi-scan-sdk/main/Kconfig.projbuild new file mode 100644 index 00000000..befc4efa --- /dev/null +++ b/arduino-esp32-wifi-scan-sdk/main/Kconfig.projbuild @@ -0,0 +1,8 @@ +# put here your custom config value +menu "Example Configuration" +config WIFI_SCAN_INTERVAL_MS + int "WiFi network scanning interval / ms" + default 5000 + help + Interval in milliseconds between scanning for networks +endmenu diff --git a/rpi-5-blink/Sources/Support/include/Support.h b/arduino-esp32-wifi-scan-sdk/main/Main.swift similarity index 55% rename from rpi-5-blink/Sources/Support/include/Support.h rename to arduino-esp32-wifi-scan-sdk/main/Main.swift index deac9bed..6326eca3 100644 --- a/rpi-5-blink/Sources/Support/include/Support.h +++ b/arduino-esp32-wifi-scan-sdk/main/Main.swift @@ -9,8 +9,18 @@ // //===----------------------------------------------------------------------===// -#pragma once +@_cdecl("_Z5setupv") +func setup() { + print("Hello from Swift on a ESP32-C6!") +} -static inline __attribute((always_inline)) void nop() { - asm volatile("nop"); +@_cdecl("_Z4loopv") +func loop() { + print("Scanning...") + let count = WiFi.scanNetworks(false, true) + print("Found \(count) networks:") + for i in 0..=1.0.0,<2.0.0" + # username2/component2: + # version: "~1.0.0" + # # For transient dependencies `public` flag can be set. + # # `public` flag doesn't have an effect dependencies of the `main` component. + # # All dependencies of `main` are public by default. + # public: true + + ## Required IDF version + idf: ">=5.3,<5.5" + arduino: # Can't be defined as the espressif/arduino-esp32 shorthand since the library name must be 'arduino' for libraries that depend on it + git: https://github.com/espressif/arduino-esp32.git + version: 3.2.0 diff --git a/arduino-esp32-wifi-scan-sdk/sdkconfig.defaults b/arduino-esp32-wifi-scan-sdk/sdkconfig.defaults new file mode 100644 index 00000000..d4f9762e --- /dev/null +++ b/arduino-esp32-wifi-scan-sdk/sdkconfig.defaults @@ -0,0 +1,4 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_MBEDTLS_PSK_MODES=y +CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y +CONFIG_AUTOSTART_ARDUINO=y diff --git a/esp32-led-blink-sdk/CMakeLists.txt b/esp32-led-blink-sdk/CMakeLists.txt deleted file mode 100644 index bdc05581..00000000 --- a/esp32-led-blink-sdk/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -cmake_minimum_required(VERSION 3.29) -include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(main) diff --git a/esp32-led-blink-sdk/README.md b/esp32-led-blink-sdk/README.md deleted file mode 100644 index 53b4ff4e..00000000 --- a/esp32-led-blink-sdk/README.md +++ /dev/null @@ -1,47 +0,0 @@ -# esp32-led-blink-sdk - -This example demonstrates how to integrate with the ESP-IDF SDK via CMake and how to use the standard GPIO library to control LED from Swift. This example is specifically made for the RISC-V MCUs from ESP32 (the Xtensa MCUs are not currently supported by Swift). - -![Led on](assets/images/ledon.jpg) -![Led off](assets/images/ledoff.jpg) - -## Requirements - -- Set up the [ESP-IDF](https://docs.espressif.com/projects/esp-idf/en/stable/esp32/) development environment. Follow the steps in the [ESP32-C6 "Get Started" guide](https://docs.espressif.com/projects/esp-idf/en/v5.2/esp32c6/get-started/index.html). - - Make sure you specifically set up development for the RISC-V ESP32-C6, and not the Xtensa based products. - -- Before trying to use Swift with the ESP-IDF SDK, make sure your environment works and can build the provided C/C++ sample projects, in particular: - - Try building and running the "get-started/blink" example from ESP-IDF written in C. - -## Building - -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- If needed, run export.sh to get access to the idf.py script from ESP-IDF. -- Specify the target board type by using `idf.py set-target`. -``` console -$ cd esp32-led-blink-sdk -$ . /export.sh -$ idf.py set-target esp32c6 -$ idf.py build -``` - -## Running - -- Connect the Esp32-C6-Bug board (or any other board with integrated LED on GPIO pin 8) over a USB cable to your Mac. Alternatively you can just connect external LED to GPIO pin 8 on any other board. -- Connect RX pin of USB-UART converter to TX0 pin of your board if you need serial ouput. You may also need to connect GND converter pin to the GND pin of the board. -- Use `idf.py` to upload the firmware and to run it: - -```console -$ idf.py flash -``` - -- The LED should be blinking now. - -### Simulating in VS Code - -- Build the project, to generate binaries for simulation -- Install [Wokwi for VS Code](https://docs.wokwi.com/vscode/getting-started/). -- Open the `diagram.json` file. -- Click the Play button to start simulation. -- Click the Pause button to freeze simulation and display states of GPIOs. - diff --git a/esp32-led-blink-sdk/assets/images/ledoff.jpg b/esp32-led-blink-sdk/assets/images/ledoff.jpg deleted file mode 100644 index 81d3b93d..00000000 Binary files a/esp32-led-blink-sdk/assets/images/ledoff.jpg and /dev/null differ diff --git a/esp32-led-blink-sdk/assets/images/ledon.jpg b/esp32-led-blink-sdk/assets/images/ledon.jpg deleted file mode 100644 index 2446ec6c..00000000 Binary files a/esp32-led-blink-sdk/assets/images/ledon.jpg and /dev/null differ diff --git a/esp32-led-blink-sdk/main/Led.swift b/esp32-led-blink-sdk/main/Led.swift deleted file mode 100644 index 5fdd4d96..00000000 --- a/esp32-led-blink-sdk/main/Led.swift +++ /dev/null @@ -1,30 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// A simple "overlay" to provide nicer APIs in Swift -struct Led { - var ledPin: gpio_num_t - init(gpioPin: Int) { - ledPin = gpio_num_t(Int32(gpioPin)) - - guard gpio_reset_pin(ledPin) == ESP_OK else { - fatalError("cannot reset led") - } - - guard gpio_set_direction(ledPin, GPIO_MODE_OUTPUT) == ESP_OK else { - fatalError("cannot reset led") - } - } - func setLed(value: Bool) { - let level: UInt32 = value ? 1 : 0 - gpio_set_level(ledPin, level) - } -} diff --git a/esp32-led-blink-sdk/main/idf_component.yml b/esp32-led-blink-sdk/main/idf_component.yml deleted file mode 100644 index e69de29b..00000000 diff --git a/esp32-led-strip-sdk/CMakeLists.txt b/esp32-led-strip-sdk/CMakeLists.txt deleted file mode 100644 index bdc05581..00000000 --- a/esp32-led-strip-sdk/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -cmake_minimum_required(VERSION 3.29) -include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(main) diff --git a/esp32-led-strip-sdk/README.md b/esp32-led-strip-sdk/README.md deleted file mode 100644 index 4f50c021..00000000 --- a/esp32-led-strip-sdk/README.md +++ /dev/null @@ -1,46 +0,0 @@ -# esp32-led-strip-sdk - -This example demonstrates how to integrate with the ESP-IDF SDK via CMake and how to use the existing LED strip library to control WS8212 lights from Swift. This example is specifically made for the RISC-V MCUs from ESP32 (the Xtensa MCUs are not currently supported by Swift). - - - -## Requirements - -- Set up the [ESP-IDF](https://docs.espressif.com/projects/esp-idf/en/stable/esp32/) development environment. Follow the steps in the [ESP32-C6 "Get Started" guide](https://docs.espressif.com/projects/esp-idf/en/v5.2/esp32c6/get-started/index.html). - - Make sure you specifically set up development for the RISC-V ESP32-C6, and not the Xtensa based products. - -- Before trying to use Swift with the ESP-IDF SDK, make sure your environment works and can build the provided C/C++ sample projects, in particular: - - Try building and running the "get-started/blink" example from ESP-IDF written in C. - -## Building - -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- If needed, run export.sh to get access to the idf.py script from ESP-IDF. -- Specify and the target board type by using `idf.py set-target`. -``` console -$ cd esp32-led-strip-sdk -$ . /export.sh -$ idf.py set-target esp32c6 -$ idf.py build -``` - -## Running - -- Connect the ESP32-C6-DevKitC-1 board over a USB cable to your Mac. -- Wire up an external WS8212 LED strip and use GPIO pin 0 as the data pin. You might need to use a level shifter. -- Use `idf.py` to upload the firmware and to run it: - -```console -$ idf.py flash -``` - -- The LED strip should now be animating a sequence of random colors moving in one direction. - -### Simulating in VS Code - -- Build the project, to generate binaries for simulation -- Install [Wokwi for VS Code](https://docs.wokwi.com/vscode/getting-started/). -- Open the `diagram.json` file. -- Click the Play button to start simulation. -- Click the Pause button to freeze simulation and display states of GPIOs. - diff --git a/esp32-led-strip-sdk/diagram.json b/esp32-led-strip-sdk/diagram.json deleted file mode 100644 index f8e70fe3..00000000 --- a/esp32-led-strip-sdk/diagram.json +++ /dev/null @@ -1,44 +0,0 @@ -{ - "version": 1, - "author": "", - "editor": "wokwi", - "parts": [ - { - "type": "board-esp32-c6-devkitc-1", - "id": "esp", - "top": -13.91, - "left": 90.52, - "attrs": { "builder": "esp-idf" } - }, - { "type": "wokwi-neopixel", "id": "rgb1", "top": 73.3, "left": -20.2, "attrs": {} }, - { "type": "wokwi-neopixel", "id": "rgb2", "top": 73.3, "left": 18.2, "attrs": {} }, - { "type": "wokwi-neopixel", "id": "rgb3", "top": 73.3, "left": -250.6, "attrs": {} }, - { "type": "wokwi-neopixel", "id": "rgb4", "top": 73.3, "left": -212.2, "attrs": {} }, - { "type": "wokwi-neopixel", "id": "rgb5", "top": 73.3, "left": -58.6, "attrs": {} }, - { "type": "wokwi-neopixel", "id": "rgb6", "top": 73.3, "left": -173.8, "attrs": {} }, - { "type": "wokwi-neopixel", "id": "rgb7", "top": 73.3, "left": -97, "attrs": {} }, - { "type": "wokwi-neopixel", "id": "rgb8", "top": 73.3, "left": -135.4, "attrs": {} } - ], - "connections": [ - [ "esp:TX", "$serialMonitor:RX", "", [] ], - [ "esp:RX", "$serialMonitor:TX", "", [] ], - [ "rgb2:DIN", "esp:0", "green", [ "h28", "v-38.4" ] ], - [ "rgb2:DOUT", "rgb1:DIN", "green", [ "h-9.6", "v-10.5" ] ], - [ "rgb5:DOUT", "rgb7:DIN", "green", [ "h-9.6", "v-10.5" ] ], - [ "rgb8:DOUT", "rgb6:DIN", "green", [ "h-9.6", "v-10.5" ] ], - [ "rgb6:DOUT", "rgb4:DIN", "green", [ "v-0.9", "h-9.6", "v-9.6" ] ], - [ "rgb4:DOUT", "rgb3:DIN", "green", [ "v-0.9", "h-9.6", "v-9.6" ] ], - [ "rgb1:DOUT", "rgb5:DIN", "green", [ "h-9.6", "v-10.5" ] ], - [ "rgb2:VSS", "esp:5V", "red", [ "h18.4", "v75.9" ] ], - [ "rgb2:VDD", "rgb1:VSS", "red", [ "h-9.6", "v10.5" ] ], - [ "rgb1:VDD", "rgb5:VSS", "red", [ "h-9.6", "v10.5" ] ], - [ "rgb5:VDD", "rgb7:VSS", "red", [ "h-9.6", "v10.5" ] ], - [ "rgb7:VDD", "rgb8:VSS", "red", [ "h-9.6", "v10.5" ] ], - [ "rgb8:VDD", "rgb6:VSS", "red", [ "h-9.6", "v10.5" ] ], - [ "rgb6:VDD", "rgb4:VSS", "red", [ "h-9.6", "v10.5" ] ], - [ "rgb4:VDD", "rgb3:VSS", "red", [ "h-9.6", "v10.5" ] ], - [ "rgb3:VDD", "esp:GND.1", "black", [ "h-9.6", "v96" ] ], - [ "rgb8:DIN", "rgb7:DOUT", "green", [ "h8.8", "v9.6", "h9.6" ] ] - ], - "dependencies": {} -} diff --git a/esp32-led-strip-sdk/main/BridgingHeader.h b/esp32-led-strip-sdk/main/BridgingHeader.h deleted file mode 100644 index 5feff4bc..00000000 --- a/esp32-led-strip-sdk/main/BridgingHeader.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include - -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "led_strip.h" -#include "sdkconfig.h" diff --git a/esp32-led-strip-sdk/main/LedStrip.swift b/esp32-led-strip-sdk/main/LedStrip.swift deleted file mode 100644 index ed275379..00000000 --- a/esp32-led-strip-sdk/main/LedStrip.swift +++ /dev/null @@ -1,56 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// A simple "overlay" to provide nicer APIs in Swift -struct LedStrip { - private let handle: led_strip_handle_t - - init(gpioPin: Int, maxLeds: Int) { - var handle = led_strip_handle_t(bitPattern: 0) - var stripConfig = led_strip_config_t( - strip_gpio_num: Int32(gpioPin), - max_leds: UInt32(maxLeds), - led_pixel_format: LED_PIXEL_FORMAT_GRB, - led_model: LED_MODEL_WS2812, - flags: .init(invert_out: 0) - ) - var spiConfig = led_strip_spi_config_t( - clk_src: SPI_CLK_SRC_DEFAULT, - spi_bus: SPI2_HOST, - flags: .init(with_dma: 1) - ) - guard led_strip_new_spi_device(&stripConfig, &spiConfig, &handle) == ESP_OK, - let handle = handle - else { fatalError("cannot configure spi device") } - self.handle = handle - } - - struct Color { - static var white = Color(r: 255, g: 255, b: 255) - static var lightWhite = Color(r: 16, g: 16, b: 16) - static var lightRandom: Color { - Color( - r: .random(in: 0...16), g: .random(in: 0...16), b: .random(in: 0...16)) - } - static var off = Color(r: 0, g: 0, b: 0) - - var r, g, b: UInt8 - } - - func setPixel(index: Int, color: Color) { - led_strip_set_pixel( - handle, UInt32(index), UInt32(color.r), UInt32(color.g), UInt32(color.b)) - } - - func refresh() { led_strip_refresh(handle) } - - func clear() { led_strip_clear(handle) } -} diff --git a/esp32-led-strip-sdk/main/Main.swift b/esp32-led-strip-sdk/main/Main.swift deleted file mode 100644 index 8a4d3a71..00000000 --- a/esp32-led-strip-sdk/main/Main.swift +++ /dev/null @@ -1,33 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -@_cdecl("app_main") -func main() { - print("Hello from Swift on ESP32-C6!") - - let n = 8 - let ledStrip = LedStrip(gpioPin: 0, maxLeds: n) - ledStrip.clear() - - var colors: [LedStrip.Color] = .init(repeating: .off, count: n) - while true { - colors.removeLast() - colors.insert(.lightRandom, at: 0) - - for index in 0.." "$" COMPILE_DEFINITIONS "${COMPILE_DEFINITIONS}") -string(REPLACE ";" " -Xcc -D" COMPILE_DEFINITIONS "${COMPILE_DEFINITIONS} ") -message("COMPILE_DEFINITIONS: ${COMPILE_DEFINITIONS}") - -get_target_property(var pico_standard_link INTERFACE_COMPILE_OPTIONS) -set_target_properties(pico_standard_link PROPERTIES INTERFACE_COMPILE_OPTIONS "") - -# Compute -Xcc flags to set up the C and C++ header search paths for Swift (for -# the bridging header). -set(SWIFT_INCLUDES) -foreach(dir ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES}) - string(CONCAT SWIFT_INCLUDES ${SWIFT_INCLUDES} "-Xcc ") - string(CONCAT SWIFT_INCLUDES ${SWIFT_INCLUDES} "-I${dir} ") -endforeach() -foreach(dir ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES}) - string(CONCAT SWIFT_INCLUDES ${SWIFT_INCLUDES} "-Xcc ") - string(CONCAT SWIFT_INCLUDES ${SWIFT_INCLUDES} "-I${dir} ") -endforeach() - -# Swift compiler flags to build in Embedded Swift mode, optimize for size, -# choose the right ISA, ABI, etc. -target_compile_options(app PUBLIC "$<$:SHELL: - -target armv6m-none-none-eabi - -Xfrontend -function-sections -wmo -parse-as-library -Osize - -enable-experimental-feature Embedded - -enable-experimental-feature Extern - -enable-experimental-feature Span - -enable-experimental-feature SymbolLinkageMarkers - - -assert-config Debug - - -Xcc -mfloat-abi=soft -Xcc -fshort-enums - -Xcc -D__APPLE_CC__ - - -Xcc -I${CMAKE_CURRENT_LIST_DIR}/include - - -pch-output-dir /tmp - -Xfrontend -enable-single-module-llvm-emission - - ${SWIFT_INCLUDES} - ${COMPILE_DEFINITIONS} - - -import-bridging-header ${CMAKE_CURRENT_LIST_DIR}/Sources/Application/BridgingHeader.h - >") - -# Enable Swift support in CMake, force Whole Module builds (required by Embedded -# Swift), and use "CMAKE_Swift_COMPILER_WORKS" to skip the trial compilations -# which don't (yet) correctly work when cross-compiling. -set(CMAKE_Swift_COMPILER_WORKS YES) -set(CMAKE_Swift_COMPILATION_MODE_DEFAULT wholemodule) -set(CMAKE_Swift_COMPILATION_MODE wholemodule) -enable_language(Swift) - -# Don't link via the Swift driver, it doesn't understand some GNU linker -# arguments, and it's not necessary for Embedded Swift. -set_property(TARGET app PROPERTY LINKER_LANGUAGE C) - -# List of Swift and C source files to build. -target_sources(app - PRIVATE - Sources/Application/Button.swift - Sources/Application/ButtonTimes.swift - Sources/Application/LEDStrip.swift - Sources/Application/Logging.swift - Sources/Application/Main.swift - Sources/Application/QuadratureEncoder.swift - Sources/Application/Stubs.swift - - Sources/Audio/AudioAnalyzer.swift - Sources/Audio/AudioBuffer.swift - Sources/Audio/AudioBufferTransport.swift - Sources/Audio/AudioEngine.swift - Sources/Audio/AudioI2S.swift - Sources/Audio/AudioPico.swift - Sources/Audio/MAX9744.swift - Sources/Audio/Resampler.swift - Sources/Audio/Ring.swift - Sources/Audio/RingBuffer.swift - Sources/Audio/SpinLock.swift - Sources/Audio/TPA2016D2.swift - - Sources/Bluetooth/A2DP.swift - Sources/Bluetooth/AVRCP.swift - Sources/Bluetooth/HCI.swift - Sources/Bluetooth/SBC.swift - Sources/Bluetooth/SDP.swift - - Sources/PIOPrograms/I2S.pio - Sources/PIOPrograms/QuadratureEncoder.pio - Sources/PIOPrograms/WS2812.pio -) - -pico_add_extra_outputs(app) diff --git a/harmony/README.md b/harmony/README.md deleted file mode 100644 index 9e8a55f9..00000000 --- a/harmony/README.md +++ /dev/null @@ -1,113 +0,0 @@ -# Harmony - -> [!NOTE] -> This README is still under construction. - -Harmony is a Bluetooth speaker and Ferrofluidic music visualizer. - -![Harmony device](./assets/hero.jpg) - -## Table of Contents - -- [Overview](#overview) -- [Features](#features) -- [Bill of Materials](#bill-of-materials) -- [Compiling the firmware](#compiling-the-firmware) -- [Flashing and running](#flashing-and-running) -- [Monitoring UART](#monitoring-uart) -- [Hardware Setup](#hardware-setup) -- [Software Architecture](#software-architecture) - -## Overview - -Harmony combines Bluetooth audio streaming with the visual effects of a ferrofluid display reacting to the music's rhythm and bass. - -> [!WARNING] -> This project involves power electronics which can be dangerous. Take proper -> safety precautions and consult a qualified professional if unsure. - -## Features - -- Bluetooth audio streaming (using the SBC codec) -- Ferrofluid visualization synchronized with music -- Volume and playback controls -- Customizable LED lighting effects - -## Bill of Materials - -A detailed Bill of Materials (BOM) can be found in `BillOfMaterials.md`. This document lists all the necessary components for building Harmony. - -## Compiling the firmware - -The firmware for Harmony is built using CMake and requires the Raspberry Pi Pico SDK. - -1. Ensure you have the Pico SDK set up on your system. See the official Raspberry Pi Pico documentation for instructions: [https://www.raspberrypi.com/documentation/pico/getting-started/](https://www.raspberrypi.com/documentation/pico/getting-started/) - -2. Clone the swift-embedded-examples repository (if not already done): - ```bash - git clone https://github.com/swiftlang/swift-embedded-examples.git - cd harmony - ``` - -3. Set the necessary environment variables: - ```bash - export PICO_BOARD=pico_w - export PICO_SDK_PATH='' # e.g., ../pico-sdk - export PICO_EXTRAS_PATH='' # e.g., ../pico-extras - export PICO_TOOLCHAIN_PATH='' # e.g., /usr/bin - ``` - -4. Generate the build files using CMake: - ```bash - cmake -B build -G Ninja . -DCMAKE_EXPORT_COMPILE_COMMANDS=On - ``` - -5. Build the firmware: - ```bash - cmake --build build - ``` - -## Flashing and running - -To flash the compiled firmware onto the Raspberry Pi Pico, you'll need OpenOCD. - -1. Connect your Pico to your computer using a USB cable and put it into BOOTSEL mode by holding the BOOTSEL button while plugging it in. - -2. Run OpenOCD with the appropriate configuration files: - ```bash - openocd -f interface/cmsis-dap.cfg -f target/rp2040.cfg -c "adapter speed 5000" -c "program build/app.elf verify reset exit" - ``` - -## Monitoring UART - -For debugging and monitoring, you can connect to the Pico's UART using a serial terminal program like `screen`. - -1. Identify the serial port connected to your Pico. You can usually find it using `ls /dev/cu.usbmodem*` on macOS or by checking the Device Manager on Windows. - -2. Connect to the UART using `screen`: - ```bash - screen /dev/cu.usbmodem<...> 115200 - ``` - (Replace `<...>` with the correct port identifier) - -## Hardware Setup - -> [!NOTE] -> This README is still under construction. - -## Software Architecture - -> [!NOTE] -> This README is still under construction. - -The firmware is designed with a modular architecture for efficient audio processing and visualization control. - -- **Bluetooth Handlers:** Manage the Bluetooth connection and incoming audio stream using the SBC codec. -- **SBC Ring Buffer:** Stores the decoded SBC audio data for further processing. -- **Audio Decoder:** Decodes the SBC encoded audio stream into PCM (Pulse Code Modulation) format. -- **PCM Ring Buffer:** Stores the decoded PCM audio data. -- **Audio Analyzer:** Analyzes the PCM audio data to extract relevant information like amplitude and frequency. This data is used to control the ferrofluid display. -- **Audio Driver:** Sends the PCM audio data to the DAC (Digital-to-Analog Converter). -- **DAC:** Converts the digital audio signal to an analog signal. -- **Amplifier:** Amplifies the analog audio signal to drive the speaker. -- **Electromagnet Driver:** Controls the electromagnet based on the analyzed audio data, creating the ferrofluid movements. diff --git a/harmony/Sources/Application/BridgingHeader.h b/harmony/Sources/Application/BridgingHeader.h deleted file mode 100644 index 74f7f34a..00000000 --- a/harmony/Sources/Application/BridgingHeader.h +++ /dev/null @@ -1,69 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#pragma once - -// C Stdlib -#include - -// Pico SDK -#include -#include -#include - -#include -#include -#include -#include -#include - -// Bluetooth SDK -#include -#include -#include -#include - -// PIO Programs -#include "I2S.pio.h" -#include "QuadratureEncoder.pio.h" -#include "WS2812.pio.h" - -#undef ISB -#include "arm_math.h" - -// Shims -static inline pio_hw_t* _pio0(void) { return pio0; } -static inline pio_hw_t* _pio1(void) { return pio1; } -static inline int32_t _errno() { return errno; } - -static const q15_t _samples_512[512] = { - // 10000 Hz - // 0, 32419, 9435, -29673, -18071, 24413, 25176, -17086, -30149, 8311, 32568, 1166, -32228, -10546, 29159, 19033, -23619, -25907, 16079, 30587, -7177, -32676, -2332, 31997, 11644, -28608, -19971, 22796, 26605, -15052, -30986, 6034, 32742, 3494, -31725, -12728, 28021, 20883, -21943, -27269, 14006, 31346, -4883, -32767, -4652, 31413, 13795, -27398, -21769, 21062, 27899, -12943, -31666, 3726, 32751, 5805, -31061, -14845, 26741, 22627, -20155, -28493, 11862, 31946, -2565, -32692, -6949, 30670, 15876, -26049, -23457, 19222, 29052, -10767, -32185, 1400, 32593, 8085, -30240, -16886, 25325, 24257, -18265, -29573, 9658, 32384, -233, -32452, -9211, 29771, 17876, -24568, -25026, 17285, 30057, -8537, -32541, -933, 32270, 10325, -29265, -18842, 23781, 25763, -16282, -30502, 7405, 32658, 2099, -32047, -11426, 28721, 19785, -22963, -26468, 15259, 30909, -6263, -32732, -3262, 31783, 12512, -28141, -20703, 22116, 27139, -14217, -31277, 5114, 32766, 4421, -31479, -13583, 27525, 21594, -21241, -27776, 13157, 31605, -3958, -32757, -5575, 31135, 14636, -26875, -22458, 20339, 28377, -12080, -31893, 2797, 32707, 6721, -30751, -15671, 26190, 23293, -19411, -28943, 10987, 32141, -1633, -32616, -7859, 30329, 16686, -25472, -24099, 18458, 29472, -9881, -32347, 466, 32483, 8987, -29868, -17679, 24722, 24875, -17483, -29963, 8762, 32513, 700, -32309, -10103, 29369, 18651, -23941, -25619, 16484, 30416, -7632, -32638, -1866, 32094, 11207, -28833, -19598, 23129, 26330, -15466, -30831, 6492, 32721, 3030, -31839, -12296, 28260, 20521, -22287, -27008, 14427, 31207, -5344, -32762, -4190, 31543, 13370, -27651, -21418, 21418, 27651, -13370, -31543, 4190, 32762, 5344, -31207, -14427, 27008, 22287, -20521, -28260, 12296, 31839, -3030, -32721, -6492, 30831, 15466, -26330, -23129, 19598, 28833, -11207, -32094, 1866, 32638, 7632, -30416, -16484, 25619, 23941, -18651, -29369, 10103, 32309, -700, -32513, -8762, 29963, 17483, -24875, -24722, 17679, 29868, -8987, -32483, -466, 32347, 9881, -29472, -18458, 24099, 25472, -16686, -30329, 7859, 32616, 1633, -32141, -10987, 28943, 19411, -23293, -26190, 15671, 30751, -6721, -32707, -2797, 31893, 12080, -28377, -20339, 22458, 26875, -14636, -31135, 5575, 32757, 3958, -31605, -13157, 27776, 21241, -21594, -27525, 13583, 31479, -4421, -32766, -5114, 31277, 14217, -27139, -22116, 20703, 28141, -12512, -31783, 3262, 32732, 6263, -30909, -15259, 26468, 22963, -19785, -28721, 11426, 32047, -2099, -32658, -7405, 30502, 16282, -25763, -23781, 18842, 29265, -10325, -32270, 933, 32541, 8537, -30057, -17285, 25026, 24568, -17876, -29771, 9211, 32452, 233, -32384, -9658, 29573, 18265, -24257, -25325, 16886, 30240, -8085, -32593, -1400, 32185, 10767, -29052, -19222, 23457, 26049, -15876, -30670, 6949, 32692, 2565, -31946, -11862, 28493, 20155, -22627, -26741, 14845, 31061, -5805, -32751, -3726, 31666, 12943, -27899, -21062, 21769, 27398, -13795, -31413, 4652, 32767, 4883, -31346, -14006, 27269, 21943, -20883, -28021, 12728, 31725, -3494, -32742, -6034, 30986, 15052, -26605, -22796, 19971, 28608, -11644, -31997, 2332, 32676, 7177, -30587, -16079, 25907, 23619, -19033, -29159, 10546, 32228, -1166, -32568, -8311, 30149, 17086, -25176, -24413, 18071, 29673, -9435, -32419, 0, 32419, 9435, -29673, -18071, 24413, 25176, -17086, -30149, 8311, 32568, 1166, -32228, -10546, 29159, 19033, -23619, -25907, 16079, 30587, -7177, -32676, -2332, 31997, 11644, -28608, -19971, 22796, 26605, -15052, -30986, 6034, 32742, 3494, -31725, -12728, 28021, 20883, -21943, -27269, 14006, 31346, -4883, -32767, -4652, 31413, 13795, -27398, -21769, 21062, 27899, -12943, -31666, 3726, 32751, 5805, -31061, -14845, 26741, 22627, -20155, -28493, 11862, 31946, -2565, -32692, -6949, 30670, 15876, -26049, -23457 - // 100 Hz - // 0, 466, 933, 1400, 1866, 2332, 2797, 3262, 3726, 4190, 4652, 5114, 5575, 6034, 6492, 6949, 7405, 7859, 8311, 8762, 9211, 9658, 10103, 10546, 10987, 11426, 11862, 12296, 12728, 13157, 13583, 14006, 14427, 14845, 15259, 15671, 16079, 16484, 16886, 17285, 17679, 18071, 18458, 18842, 19222, 19598, 19971, 20339, 20703, 21062, 21418, 21769, 22116, 22458, 22796, 23129, 23457, 23781, 24099, 24413, 24722, 25026, 25325, 25619, 25907, 26190, 26468, 26741, 27008, 27269, 27525, 27776, 28021, 28260, 28493, 28721, 28943, 29159, 29369, 29573, 29771, 29963, 30149, 30329, 30502, 30670, 30831, 30986, 31135, 31277, 31413, 31543, 31666, 31783, 31893, 31997, 32094, 32185, 32270, 32347, 32419, 32483, 32541, 32593, 32638, 32676, 32707, 32732, 32751, 32762, 32767, 32766, 32757, 32742, 32721, 32692, 32658, 32616, 32568, 32513, 32452, 32384, 32309, 32228, 32141, 32047, 31946, 31839, 31725, 31605, 31479, 31346, 31207, 31061, 30909, 30751, 30587, 30416, 30240, 30057, 29868, 29673, 29472, 29265, 29052, 28833, 28608, 28377, 28141, 27899, 27651, 27398, 27139, 26875, 26605, 26330, 26049, 25763, 25472, 25176, 24875, 24568, 24257, 23941, 23619, 23293, 22963, 22627, 22287, 21943, 21594, 21241, 20883, 20521, 20155, 19785, 19411, 19033, 18651, 18265, 17876, 17483, 17086, 16686, 16282, 15876, 15466, 15052, 14636, 14217, 13795, 13370, 12943, 12512, 12080, 11644, 11207, 10767, 10325, 9881, 9435, 8987, 8537, 8085, 7632, 7177, 6721, 6263, 5805, 5344, 4883, 4421, 3958, 3494, 3030, 2565, 2099, 1633, 1166, 700, 233, -233, -700, -1166, -1633, -2099, -2565, -3030, -3494, -3958, -4421, -4883, -5344, -5805, -6263, -6721, -7177, -7632, -8085, -8537, -8987, -9435, -9881, -10325, -10767, -11207, -11644, -12080, -12512, -12943, -13370, -13795, -14217, -14636, -15052, -15466, -15876, -16282, -16686, -17086, -17483, -17876, -18265, -18651, -19033, -19411, -19785, -20155, -20521, -20883, -21241, -21594, -21943, -22287, -22627, -22963, -23293, -23619, -23941, -24257, -24568, -24875, -25176, -25472, -25763, -26049, -26330, -26605, -26875, -27139, -27398, -27651, -27899, -28141, -28377, -28608, -28833, -29052, -29265, -29472, -29673, -29868, -30057, -30240, -30416, -30587, -30751, -30909, -31061, -31207, -31346, -31479, -31605, -31725, -31839, -31946, -32047, -32141, -32228, -32309, -32384, -32452, -32513, -32568, -32616, -32658, -32692, -32721, -32742, -32757, -32766, -32767, -32762, -32751, -32732, -32707, -32676, -32638, -32593, -32541, -32483, -32419, -32347, -32270, -32185, -32094, -31997, -31893, -31783, -31666, -31543, -31413, -31277, -31135, -30986, -30831, -30670, -30502, -30329, -30149, -29963, -29771, -29573, -29369, -29159, -28943, -28721, -28493, -28260, -28021, -27776, -27525, -27269, -27008, -26741, -26468, -26190, -25907, -25619, -25325, -25026, -24722, -24413, -24099, -23781, -23457, -23129, -22796, -22458, -22116, -21769, -21418, -21062, -20703, -20339, -19971, -19598, -19222, -18842, -18458, -18071, -17679, -17285, -16886, -16484, -16079, -15671, -15259, -14845, -14427, -14006, -13583, -13157, -12728, -12296, -11862, -11426, -10987, -10546, -10103, -9658, -9211, -8762, -8311, -7859, -7405, -6949, -6492, -6034, -5575, -5114, -4652, -4190, -3726, -3262, -2797, -2332, -1866, -1400, -933, -466, 0, 466, 933, 1400, 1866, 2332, 2797, 3262, 3726, 4190, 4652, 5114, 5575, 6034, 6492, 6949, 7405, 7859, 8311, 8762, 9211, 9658, 10103, 10546, 10987, 11426, 11862, 12296, 12728, 13157, 13583, 14006, 14427, 14845, 15259, 15671, 16079, 16484, 16886, 17285, 17679, 18071, 18458, 18842, 19222, 19598, 19971, 20339, 20703, 21062, 21418, 21769, 22116, 22458, 22796, 23129, 23457, 23781, 24099, 24413, 24722, 25026, 25325, 25619, 25907, 26190, 26468, 26741, 27008, 27269, 27525 - // Random - // -23267, -28627, -22857, 28240, 13800, 30726, -24151, 26079, -13476, -12798, 13052, 13852, -22637, -6154, -3815, -12039, 25243, -1585, -19939, -8784, -28265, -26459, -11751, 11175, 29945, 6392, 2017, -26312, 705, 3937, 15719, 15254, 2106, -19522, -11782, 14779, 17287, -573, -4131, 1598, -17359, -2321, 29406, 10983, -1820, 10484, 2547, 21179, -8994, -2079, -27106, 10036, 24048, 20759, -22663, 30870, -23019, -6484, 10645, 28446, 5694, 29587, 2716, 28330, -31127, -24224, 11747, 4653, 25607, 2060, -13584, 18776, 3286, 4279, -23640, -19751, -29165, -26461, 1009, -26, 24934, 1737, 25904, 13741, 26638, -9855, 24739, 1151, 1288, 27717, -14507, 31321, 14853, 30335, 6779, -25100, -31174, 21443, -26019, 10443, -16230, -7792, -17010, 22850, 26999, -22520, -3965, -28776, 20422, 32717, -13509, 615, 3751, 14471, -31442, 331, -4401, -13910, -9235, -22272, -20351, -18042, -12559, -26528, -21608, -10967, -10773, 7318, 29416, 11987, -18385, 18446, -7565, -1826, 5991, -1501, -18115, 11245, -26602, 26281, -27812, 606, 10535, -24038, -9512, -28585, 17743, -23902, -5358, 14428, -6620, -11902, 29990, -1351, 229, 505, -20824, 2948, -10728, -8917, -30529, -8611, 10386, 8405, 29667, 1259, -933, 27763, 15110, -7538, 2579, -2260, 16781, 3587, 987, 10675, -12646, -26337, -15515, 10036, -10923, 19627, 23472, -19409, -25964, -15233, -12738, -17699, 21449, 12398, 31055, 3204, 10120, -5165, 28072, 3534, 8925, 8718, 12006, -14307, 3727, -2169, -9054, -32745, -27455, -2414, -30904, -27071, 29227, -1711, -32026, 16670, 4041, 11990, -6825, 19509, -10102, -5291, 14789, 13031, 27966, 3079, -30755, 18652, 8718, 17518, 27673, -21518, 26194, -7598, 8682, -30879, -26492, 25542, -683, 29625, -18786, -11302, 14478, -25560, 2884, 16250, -17512, -5658, 10514, -32180, 19268, 13426, -17484, 15865, 12636, 5169, -8869, 24014, 26874, 21372, -31006, 1717, 28024, 1712, 24846, 28640, 14211, 38, -32053, -23226, 4101, 10121, 17271, 67, 20471, -265, 17592, -17786, -14468, 836, 24620, -10300, -31533, 18124, -27177, 8895, -14010, 3583, 4616, -370, -1692, -24560, 7943, -15712, -548, 22854, 6585, -6472, -3219, -5611, -6953, 27266, 32132, -9528, 27921, -5179, 25555, -1361, 7012, 20560, -9756, 20686, -28590, -9269, 23420, -6441, -26236, -26378, -16303, -4482, -32143, 879, 28814, -15829, 13154, -32500, 10497, -15844, 27537, 12933, 24326, -8289, -25445, 5613, 3783, 19422, 13656, -28388, 10940, 23522, -8935, -10820, -23230, -6261, 8161, 16840, -23319, -14576, -20202, 9909, 14492, 17965, 830, 2347, -11266, -8371, -9564, -4490, 10044, -1236, -14600, 27197, 31869, 9030, 28833, 27173, -31152, 4385, 31150, 24565, -17190, 15066, 31896, -18756, 20622, -3244, -11415, 28206, 824, 11787, 17574, -32303, 23499, -23228, 24135, 29557, 11106, -12688, -1300, 16113, 4289, 8128, -10194, 8058, -24081, -13334, -22492, -20062, -21175, -31592, 11336, 26112, -14411, 29755, 8660, -19490, -11577, 17292, -8281, -2277, 3554, 4593, -2709, -5323, -8179, 10204, -17385, 18261, -301, 12645, -14775, -12287, -16381, 29835, -25494, 17111, 17776, 19593, 2789, 17686, -30471, -23637, -29774, -16137, 14721, -22862, 4031, -29039, -22289, 11175, 10518, -15373, 695, -23720, -24736, 14425, -9407, -25318, 2501, -5415, -21451, -20293, -19032, 27457, 28601, -11034, -9415, -8598, -30687, -26219, 31028, 9152, -20955, -30113, 31446, -23025, -14905, 384, -738, -871, 43, -5814, -6575, -12151, 13081, 14489, -3276, -24880, -27900, 5863, 7411, -21359, -26944, -9252, 15265, -12092, -8907, 17623, -13430, -3138, 23092, 10217, 13241, 1005, 11791, -12903, -12487, -13885, -8748, -7247, -12551, 1132, 16750, 29330, 9297, -22940, -2912, 7094, -3066, 20032, -13050, -26769, -32399, -23202, 13843, 18265 - // Mixed content - 0, 20065, 20774, 14478, 7238, -8053, -16118, -4051, 7534, 6075, 3660, -2261, -17285, -20472, -3071, 12656, 19351, 24507, 16764, -5807, -17284, -11343, -5570, 1128, 11683, 7992, -8598, -12980, -4950, 2096, 14516, 28344, 21538, 414, -11404, -16217, -18132, -4858, 13563, 13604, 3724, 32, -4475, -6513, 8151, 23989, 20258, 8508, -1704, -17249, -25082, -10049, 8615, 14091, 16355, 14067, -790, -9122, 1929, 12576, 13845, 15030, 7381, -13670, -23561, -13069, -737, 10830, 25231, 24491, 6096, -4544, -2850, -1845, 4676, 16574, 12215, -5964, -14129, -13027, -9898, 6065, 27202, 28380, 14823, 5084, -5222, -13918, -4550, 11428, 11365, 3816, -424, -9456, -14133, 1869, 21552, 25413, 22684, 15389, -4598, -19263, -11696, 681, 5865, 12445, 12521, -2447, -10764, -435, 10586, 17554, 26412, 21788, -1044, -16380, -15529, -11888, -1615, 16659, 20446, 7035, -458, -336, -1161, 7875, 23559, 21483, 4371, -7233, -15614, -21255, -8114, 14640, 21499, 16945, 13025, 2104, -8840, -766, 13847, 14491, 9531, 3725, -12102, -23332, -11514, 7094, 16637, 24423, 24493, 6412, -9454, -6591, -251, 3352, 11817, 11634, -5689, -16853, -11022, -2732, 8793, 26686, 29578, 11646, -3250, -9050, -14188, -8191, 9209, 13344, 2263, -4056, -7008, -10299, 1348, 22278, 26522, 16272, 6387, -8487, -23100, -16775, 1463, 8630, 9698, 10245, -523, -11784, -3252, 12037, 16701, 18293, 14505, -5708, -23916, -20524, -9316, -5, 14238, 20734, 7077, -5948, -4177, -816, 3751, 15842, 16850, -1764, -16792, -19304, -19174, -8705, 14023, 23853, 14256, 5119, -2037, -11764, -8128, 8128, 11764, 2037, -5119, -14256, -23853, -14023, 8705, 19174, 19304, 16792, 1764, -16850, -15842, -3751, 816, 4177, 5948, -7077, -20734, -14238, 5, 9316, 20524, 23916, 5708, -14505, -18293, -16701, -12037, 3252, 11784, 523, -10245, -9698, -8630, -1463, 16775, 23100, 8487, -6387, -16272, -26522, -22278, -1348, 10299, 7008, 4056, -2263, -13344, -9209, 8191, 14188, 9050, 3250, -11646, -29578, -26686, -8793, 2732, 11022, 16853, 5689, -11634, -11817, -3352, 251, 6591, 9454, -6412, -24493, -24423, -16637, -7094, 11514, 23332, 12102, -3725, -9531, -14491, -13847, 766, 8840, -2104, -13025, -16945, -21499, -14640, 8114, 21255, 15614, 7233, -4371, -21483, -23559, -7875, 1161, 336, 458, -7035, -20446, -16659, 1615, 11888, 15529, 16380, 1044, -21788, -26412, -17554, -10586, 435, 10764, 2447, -12521, -12445, -5865, -681, 11696, 19263, 4598, -15389, -22684, -25413, -21552, -1869, 14133, 9456, 424, -3816, -11365, -11428, 4550, 13918, 5222, -5084, -14823, -28380, -27202, -6065, 9898, 13027, 14129, 5964, -12215, -16574, -4676, 1845, 2850, 4544, -6096, -24491, -25231, -10830, 737, 13069, 23561, 13670, -7381, -15030, -13845, -12576, -1929, 9122, 790, -14067, -16355, -14091, -8615, 10049, 25082, 17249, 1704, -8508, -20258, -23989, -8151, 6513, 4475, -32, -3724, -13604, -13563, 4858, 18132, 16217, 11404, -414, -21538, -28344, -14516, -2096, 4950, 12980, 8598, -7992, -11683, -1128, 5570, 11343, 17284, 5807, -16764, -24507, -19351, -12656, 3071, 20472, 17285, 2261, -3660, -6075, -7534, 4051, 16118, 8053, -7238, -14478, -20774, -20065, 0, 20065, 20774, 14478, 7238, -8053, -16118, -4051, 7534, 6075, 3660, -2261, -17285, -20472, -3071, 12656, 19351, 24507, 16764, -5807, -17284, -11343, -5570, 1128, 11683, 7992, -8598, -12980, -4950, 2096, 14516, 28344, 21538, 414, -11404, -16217, -18132, -4858, 13563, 13604, 3724, 32, -4475, -6513, 8151, 23989, 20258, 8508, -1704, -17249, -25082, -10049, 8615, 14091, 16355, 14067, -790, -9122, 1929, 12576, 13845, 15030, 7381, -13670, -23561, -13069, -737, 10830, 25231, 24491, 6096 -}; - -const q15_t* samples_512(void) { - return _samples_512; -} - -static const q15_t _samples_64[64] = { - 0, 16209, 4717, -14836, -9035, 12206, 12588, -8543, -15074, 4155, 16284, 583, -16114, -5273, 14579, 9516, -11809, -12953, 8039, 15293, -3588, -16338, -1166, 15998, 5822, -14304, -9985, 11398, 13302, -7526, -15493, 3017, 16371, 1747, -15862, -6364, 14010, 10441, -10971, -13634, 7003, 15673, -2441, -16383, -2326, 15706, 6897, -13699, -10884, 10531, 13949, -6471, -15833, 1863, 16375, 2902, -15530, -7422, 13370, 11313, -10077, -14246, 5931, 15973 -}; - -const q15_t* samples_64(void) { - return _samples_64; -} - diff --git a/harmony/Sources/Application/Button.swift b/harmony/Sources/Application/Button.swift deleted file mode 100644 index 03867b54..00000000 --- a/harmony/Sources/Application/Button.swift +++ /dev/null @@ -1,29 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct Button: ~Copyable { - var pin: UInt32 - - init(pin: UInt32, onPress callback: @convention(c) (UInt32, UInt32) -> Void) { - self.pin = pin - - gpio_init(pin) - gpio_set_dir(pin, false) // input - gpio_pull_up(pin) // pull up the pin - gpio_set_irq_enabled_with_callback( - pin, UInt32(GPIO_IRQ_EDGE_FALL.rawValue), true, callback) - } - - deinit { - gpio_deinit(self.pin) - } -} - diff --git a/harmony/Sources/Application/ButtonTimes.swift b/harmony/Sources/Application/ButtonTimes.swift deleted file mode 100644 index 63d53b47..00000000 --- a/harmony/Sources/Application/ButtonTimes.swift +++ /dev/null @@ -1,42 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct ButtonTimes { - typealias Times = ( - UInt32, UInt32, UInt32, UInt32, - UInt32, UInt32, UInt32, UInt32, - UInt32, UInt32, UInt32, UInt32) - static let count = 12 - static let rawSize = MemoryLayout.size - static let reboundSize = Self.count * MemoryLayout.size - - private var times: Times = - (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - - subscript(_ index: some FixedWidthInteger) -> UInt32 { - get { - precondition(Self.rawSize == Self.reboundSize) - return withUnsafePointer(to: self.times) { - $0.withMemoryRebound(to: UInt32.self, capacity: Self.count) { - $0[Int(index)] - } - } - } - set { - precondition(Self.rawSize == Self.reboundSize) - return withUnsafeMutablePointer(to: &self.times) { - $0.withMemoryRebound(to: UInt32.self, capacity: Self.count) { - $0[Int(index)] = newValue - } - } - } - } -} diff --git a/harmony/Sources/Application/LEDStrip.swift b/harmony/Sources/Application/LEDStrip.swift deleted file mode 100644 index f8f058b5..00000000 --- a/harmony/Sources/Application/LEDStrip.swift +++ /dev/null @@ -1,92 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct LEDStrip: ~Copyable { - var dataPin: UInt32 - var ledCount: Int - - var pio: UInt32 - var pioSm: UInt32 - var pioHw: PIO - var pioOffset: UInt32 - - init( - dataPin: UInt32, - ledCount: Int, - // FIXME: change to `PIO` - pio: UInt32, - pioSm: UInt32 - ) { - self.dataPin = dataPin - self.ledCount = ledCount - self.pio = pio - self.pioSm = pioSm - self.pioHw = - switch self.pio { - case 0: _pio0() - case 1: _pio1() - default: fatalError("Invalid PIO index") - } - self.pioOffset = 0 - - pio_gpio_init(self.pioHw, self.dataPin) - - // FIXME: lower quadrature_encoder_program_init max_step_rate - pio_sm_claim(self.pioHw, self.pioSm) - self.pioOffset = withUnsafePointer(to: ws2812_program) { - UInt32(pio_add_program(self.pioHw, $0)) - } - ws2812_program_init(self.pioHw, self.pioSm, self.pioOffset, self.dataPin, 800000, false) - } - - deinit { - withUnsafePointer(to: ws2812_program) { - pio_remove_program_and_unclaim_sm($0, self.pioHw, self.pioSm, self.pioOffset) - } - - gpio_deinit(self.dataPin) - } -} - -extension LEDStrip { - // mutating func putPixel(pixelGRB: UInt32) { - // pio_sm_put_blocking(self.pioHw, self.pioSm, pixelGRB << 8) - // } - - // func urgb_u32(_ r: UInt8, _ g: UInt8, _ b: UInt8) -> UInt32 { - // (UInt32(r) << 8) | (UInt32(g) << 16) | UInt32(b) - // } - - // mutating func patternSnakes(t: UInt32) { - // for i in 0..> 1)) % 64 - // if x < 10 { - // putPixel(pixelGRB: urgb_u32(0xff, 0, 0)) - // } else if x >= 15 && x < 25 { - // putPixel(pixelGRB: urgb_u32(0, 0xff, 0)) - // } else if x >= 30 && x < 40 { - // putPixel(pixelGRB: urgb_u32(0, 0, 0xff)) - // } else { - // putPixel(pixelGRB: 0) - // } - // } - // } - - mutating func setColor(red: UInt8, green: UInt8, blue: UInt8) { - for _ in 0.. StreamingSerialMessage, - terminator: StaticString = "\n" -) { - _ = message() - SerialPrinter().write(terminator) -} - -/// An implementation of `CharacterPrinter` that calls `putchar` to write to serial. -struct SerialPrinter: CharacterPrinter { - func write(rawByte: UInt8) { - _ = putchar(CInt(rawByte)) - } - - func write(contentsOf: Self) { - // Don't need to handle nested SerialPrinter objects: they will have - // already written out to serial. - } -} - -// String interpolation objects cast to this type will be streamed -// to serial via calls to `putchar`. -typealias StreamingSerialMessage = StreamingMessage - -/// This file provides functionality for logging interpolated strings without -/// requiring construction of String types (which are not available in Embedded -/// Swift). - -/// Types that implement `Loggable` are able to be logged using the -/// `StreamingInterpolation` mechanisms. -/// -/// The `write` function should write a human-readable instance of the object to -/// the passed-in `Printer` type: -/// -/// struct MyType: Loggable { -/// func write(to printer: Printer) { -/// printer.write("A static string") -/// printer.write(42) -/// printer.write(anyLoggableItem) -/// printer.write("A more \(complex) string \(interpolation)") -/// } -/// } -protocol Loggable: ~Copyable { - func write(to: Printer) -} - -/// A type that supports printing individual characters. -/// -/// Characters can either be streamed directly out to a log (e.g. stdout), or -/// buffered any manually written out by the user. -protocol CharacterPrinter { - /// Initialize a new instance. - /// - /// Unfortunately, Swift calls this from within the compiler's generated - /// code, with a fresh object created each time string interpolation is - /// used, and no chance to have any instance variables. - init() - - /// Write a single byte to output. - func write(rawByte: UInt8) - - /// Write the contents of the given `CharacterPrinter` to this - /// `CharacterPrinter`. - /// - /// This method is required to be implemented so that implementors of the - /// `Loggable` protocol can themselves use String Interpolation. - /// - /// Implementations of `CharacterPrinter` that don't buffer anything (for - /// example, if they just forward characters directly to `stdout`) need not - /// do anything here. However, implementations of `CharacterPrinter` that - /// are attempting to buffer the text will need to append the contents of - /// the child `CharacterPrinter` into the parent `CharacterPrinter`. - func write(contentsOf: Self) -} - -// Convenience functions for writing basic objects to a CharacterPrinter. -// -// Most types should either just implement `Loggable` (preferred), or implement -// their type as an overload to `StreamingInterpolation.appendInterpolation` -// directly (for generic types or types requiring additional parameters). -extension CharacterPrinter { - /// Write the given object that implements the `Loggable` interface to the - /// printer. - func write(_ value: some Loggable) { - value.write(to: self) - } - - /// Write an integer to the printer. - func write(_ value: some FixedWidthInteger) { - value.write(to: self) - } - - /// Write the given buffer to the printer. - /// - /// This function will print the entire buffer, including NUL bytes and - /// anything following them. To print NUL-terminated strings, see the - /// overload `write(nulTerminated)`. - func write(contentsOf buffer: UnsafeBufferPointer) { - self.write(contentsOf: UnsafeRawBufferPointer(buffer)) - } - - /// Write the given buffer to the printer. - /// - /// This function will print the entire buffer, including NUL bytes and - /// anything following them. To print NUL-terminated strings, see the - /// overload `write(nulTerminated)`. - @inline(never) // avoid aggressive inlining of non-perf-sensitive code - func write(contentsOf buffer: UnsafeRawBufferPointer) { - for c in buffer { - self.write(rawByte: c) - } - } - - /// Write a NULL-terminated (C style) string to the printer. - @inline(never) // avoid aggressive inlining of non-perf-sensitive code - func write(nullTerminated value: UnsafeBufferPointer) { - for c in value { - if c == 0 { - break - } - self.write(rawByte: UInt8(c)) - } - } - - // Write the given interpolated string to this character printer. - // - // This allows implementations of `Loggable` to themselves use interpolated - // strings: - // - // ``` - // class MyClass: Loggable { - // func write(printer: P) { - // printer.write("hello, \(self.world)") - // } - // } - // ``` - @_disfavoredOverload - func write(_ value: @autoclosure () -> StreamingMessage) { - self.write(contentsOf: value().printer) - } -} - -// Loggable implementation for various types. -extension Bool: Loggable { - func write(to printer: Printer) { - if self { - printer.write("true") - } else { - printer.write("false") - } - } -} - -extension StaticString: Loggable { - func write(to printer: Printer) { - self.withUTF8Buffer { - printer.write(contentsOf: $0) - } - } -} - -extension UnsafeRawBufferPointer: Loggable { - func write(to printer: Printer) { - let base = UInt(bitPattern: self.baseAddress) - printer.write("\(hex: base), count: \(self.count)") - } -} - -extension UnsafeMutableRawBufferPointer: Loggable { - func write(to printer: Printer) { - printer.write(UnsafeRawBufferPointer(self)) - } -} - -extension CharacterPrinter { - // Write the given UInt64 to a CharacterPrinter. - // - // We use this function so that all integer sizes can reuse the same version of - // the code in the compiled binary. - @inline(never) - fileprivate func write(value: UInt64, isNegative: Bool, radix: Int) { - precondition(radix == 10 || radix == 16) - - // Special case for zero, which otherwise would have no digits printed for - // it in the algorithm below. - if value == 0 { - if radix == 16 { - self.write("0x0") - } else { - self.write("0") - } - return - } - - // Convert the given digit to its ASCII code. - func _ascii(_ digit: UInt8) -> UInt8 { - if digit < 10 { - UInt8(("0" as Unicode.Scalar).value) + digit - } else { - UInt8(("a" as Unicode.Scalar).value) + (digit - 10) - } - } - - // Render to a temporary buffer. - // - // Worst case: 64-bit type and radix 10, requires `ceil(log_10(2**64)) == 20` - // characters to render. We use another for the negative sign, and another two - // for the `0x` prefix on base 16. - withUnsafeTemporaryAllocation(byteCount: 32, alignment: 1) { buffer in - var index = buffer.count - 1 - var value = value - while value != 0 { - let (quotient, remainder) = value.quotientAndRemainder( - dividingBy: UInt64(radix)) - buffer[index] = _ascii(UInt8(truncatingIfNeeded: remainder)) - index -= 1 - value = quotient - } - if radix == 16 { - buffer[index - 1] = UInt8(("0" as Unicode.Scalar).value) - buffer[index - 0] = UInt8(("x" as Unicode.Scalar).value) - index -= 2 - } - if isNegative { - buffer[index] = UInt8(("-" as Unicode.Scalar).value) - index -= 1 - } - let start = index + 1 - let end = buffer.count - 1 - let count = end - start + 1 - self.write( - contentsOf: - UnsafeBufferPointer( - start: buffer.baseAddress?.advanced(by: start).assumingMemoryBound( - to: UInt8.self), count: count)) - } - } -} - -// Functionality to write FixedWidthInteger types to a CharacterPrinter. -extension FixedWidthInteger { - // Write a FixedWidthInteger to the given CharacterPrinter in the given radix. - func write(to printer: some CharacterPrinter, radix: Int = 10) { - precondition(radix == 10 || radix == 16) - precondition(Self.bitWidth <= 64) - - let isNegative = Self.isSigned && self < (0 as Self) - let value = self.magnitude - printer.write(value: UInt64(value), isNegative: isNegative, radix: radix) - } -} - -// Write a `StringInterpolation` to the given `CharacterPrinter` type. -// -// That is, given a type `Printer` implementing the protocol -// `CharacterPrinter`, we will convert types used in string interpolations into -// a form that can be written out to the Printer. -// -// See Swift's documentation on `StringInterpolationProtocol` for details. -struct StreamingInterpolation: StringInterpolationProtocol -{ - typealias StringLiteralType = StaticString - var printer: P = P() - - init(literalCapacity: Int, interpolationCount: Int) {} - - // Write a string literal. - mutating func appendLiteral(_ literal: StaticString) { - printer.write(literal) - } - - // Write a StaticString interpolated variable. - mutating func appendInterpolation( - _ value: StaticString - ) { - printer.write(value) - } - - // Write a basic integer type (Int16, UInt64, etc). - mutating func appendInterpolation( - _ value: some FixedWidthInteger - ) { - printer.write(value) - } -} - -extension StreamingInterpolation { - mutating func appendInterpolation(cString pointer: UnsafePointer?) { - guard var pointer else { - self.printer.write("nil") - return - } - while pointer.pointee != 0 { - self.printer.write(rawByte: pointer.pointee) - pointer = pointer.advanced(by: 1) - } - } - - mutating func appendInterpolation(cString pointer: UnsafePointer?) { - guard var pointer else { - self.printer.write("nil") - return - } - while pointer.pointee != 0 { - self.printer.write(rawByte: UInt8(pointer.pointee)) - pointer = pointer.advanced(by: 1) - } - } - - mutating func appendInterpolation(cString buffer: UnsafeBufferPointer?) - { - guard let buffer else { - self.printer.write("nil") - return - } - for byte in buffer { - guard byte != 0 else { break } - self.printer.write(rawByte: byte) - } - } - -} - -extension StreamingInterpolation { - // Write a basic integer type in hex. - // - // This can be used by writing `"the value in hex is \(hex: value)."`. - mutating func appendInterpolation( - hex value: @autoclosure () -> Word - ) { - value().write(to: printer, radix: 16) - } - - // Write an object conforming to the `Loggable` protocol. - mutating func appendInterpolation( - _ value: @autoclosure () -> some Loggable - ) { - printer.write(value()) - } - - // Write a pointer's value. - mutating func appendInterpolation(_ value: some _Pointer) { - appendInterpolation(hex: UInt(bitPattern: value)) - } - - // Write a generic `UnsafeBufferPointer` value to the stream. - mutating func appendInterpolation( - _ value: @autoclosure () -> UnsafeBufferPointer - ) { - appendInterpolation(hex: UInt(bitPattern: value().baseAddress)) - appendInterpolation(", count: ") - appendInterpolation(value().count) - } - - // Write a generic `UnsafeMutableBufferPointer` value to the stream. - mutating func appendInterpolation( - _ value: @autoclosure () -> UnsafeMutableBufferPointer - ) { - appendInterpolation(UnsafeBufferPointer(value())) - } - -} - -// Initiates a StringInterpolation. -// -// See Swift's documentation on `StringInterpolationProtocol` for details. -struct StreamingMessage: ExpressibleByStringInterpolation { - typealias StringInterpolation = StreamingInterpolation

- - init(printer: P, stringInterpolation: StreamingInterpolation

) { - self.interpolation = stringInterpolation - } - - init(stringInterpolation: StreamingInterpolation

) { - self.interpolation = stringInterpolation - } - - init(stringLiteral value: StaticString) { - self.interpolation = StreamingInterpolation( - literalCapacity: 0, interpolationCount: 0) - self.interpolation.appendLiteral(value) - } - - var printer: P { interpolation.printer } - - private var interpolation: StreamingInterpolation

-} diff --git a/harmony/Sources/Application/Main.swift b/harmony/Sources/Application/Main.swift deleted file mode 100644 index 23eb9897..00000000 --- a/harmony/Sources/Application/Main.swift +++ /dev/null @@ -1,387 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore: AlwaysUseLowerCamelCase, NeverForceUnwrap - -struct A2DPStreamEndpoint { - var a2dp_local_seid: UInt8 = 0 - var media_sbc_codec_configuration: (UInt8, UInt8, UInt8, UInt8) = (0, 0, 0, 0) -} - -var hci_event_callback_registration = btstack_packet_callback_registration_t() -var stream_endpoint = A2DPStreamEndpoint() - -// we support all configurations with bitpool 2-53 -var media_sbc_codec_capabilities: (UInt8, UInt8, UInt8, UInt8) = ( - //(AVDTP_SBC_44100 << 4) | AVDTP_SBC_STEREO, - 0xFF, - //(AVDTP_SBC_BLOCK_LENGTH_16 << 4) | (AVDTP_SBC_SUBBANDS_8 << 2) | AVDTP_SBC_ALLOCATION_METHOD_LOUDNESS, - 0xFF, - 2, 53 -) - -// FIXME: use Vector -let sdp_avdtp_sink_service_buffer = UnsafeMutableRawBufferPointer.allocate( - byteCount: 150, - alignment: MemoryLayout.alignment) -// FIXME: use Vector -let sdp_avrcp_target_service_buffer = UnsafeMutableRawBufferPointer.allocate( - byteCount: 150, - alignment: MemoryLayout.alignment) -// FIXME: use Vector -let sdp_avrcp_controller_service_buffer = - UnsafeMutableRawBufferPointer.allocate( - byteCount: 200, - alignment: MemoryLayout.alignment) -// FIXME: use Vector -let device_id_sdp_service_buffer = UnsafeMutableRawBufferPointer.allocate( - byteCount: 100, - alignment: MemoryLayout.alignment) - -// FIXME: use `Vector` -func buttonCallback(pin: UInt32, event: UInt32) { - guard event & UInt32(GPIO_IRQ_EDGE_FALL.rawValue) != 0 else { return } - Application.shared.buttonPressed(pin: pin) -} - -let BUFFER_SAMPLE_CAPACITY = 512 - - -let LED_STRIP_LED_COUNT = 20 - -let MUTE_BUTTON_PIN: UInt32 = 6 -let ROTARY_ENCODER_A_PIN : UInt32 = 7 -let ROTARY_ENCODER_B_PIN: UInt32 = 8 -let PLAY_PAUSE_BUTTON_PIN: UInt32 = 9 -let PREVIOUS_BUTTON_PIN: UInt32 = 10 -let NEXT_BUTTON_PIN: UInt32 = 11 -let LED_STRIP_PIN: UInt32 = 17 -let EM_DRIVE_PIN: UInt32 = 18 - -let WIRELESS_LED_PIN = UInt32(CYW43_WL_GPIO_LED_PIN) - -struct Application: ~Copyable { - var audioEngine = AudioEngine() - - var audioAnalyzer = AudioAnalyzer() - - let wirelessLedBlinkPeriodMs: UInt32 = 1000 - var wirelessLedBlinkTimer = btstack_timer_source_t() - var wirelessLedBlinkState = false - - let ledStripUpdatePeriodMs: UInt32 = 1000 - var ledStripUpdateTimer = btstack_timer_source_t() - var ledStrip = LEDStrip( - dataPin: LED_STRIP_PIN, - ledCount: LED_STRIP_LED_COUNT, - pio: 0, - pioSm: 1) - - let volumeKnobSamplerPeriodMs: UInt32 = 100 - var volumeKnobSamplerTimer = btstack_timer_source_t() - var volumeKnob = QuadratureEncoder( - pinA: ROTARY_ENCODER_A_PIN, - pinB: ROTARY_ENCODER_B_PIN, - pio: 1, - pioSm: 0) - - var previousPressTimes = ButtonTimes() - - var muteButton = Button( - pin: MUTE_BUTTON_PIN, - onPress: buttonCallback) - var nextButton = Button( - pin: NEXT_BUTTON_PIN, - onPress: buttonCallback) - var playPauseButton = Button( - pin: PLAY_PAUSE_BUTTON_PIN, - onPress: buttonCallback) - var previousButton = Button( - pin: PREVIOUS_BUTTON_PIN, - onPress: buttonCallback) - - mutating func run() { - stdio_init_all() - i2c_init() - - multicore_launch_core1 { - log("core1_main") - Application.shared.audioAnalyzer.run() - } - - log("Hello!") - log("sys clock running at \(clock_get_hz(clk_sys)) Hz") - log("Initializing cyw43_driver") - precondition(cyw43_arch_init() == 0, "cyw43_arch_init failed") - wirelessLedBlink(count: 2) - - gpio_init(EM_DRIVE_PIN) - gpio_set_dir(EM_DRIVE_PIN, true) - - var sdp = ServiceDiscoveryProtocol() - _setup_demo(&sdp) - - - // turn on! - log("Starting BTstack ...") - hci_power_control(HCI_POWER_ON) - wirelessLedBlink(count: 2) - log("[main] Started, starting btstack run loop") - - btstack_run_loop_set_timer_handler(&self.volumeKnobSamplerTimer) { timer in - guard let timer else { return } - Application.shared.volumeKnobSamplerHandler(&timer.pointee) - } - btstack_run_loop_set_timer(&self.volumeKnobSamplerTimer, volumeKnobSamplerPeriodMs) - btstack_run_loop_add_timer(&self.volumeKnobSamplerTimer) - - btstack_run_loop_set_timer_handler(&self.ledStripUpdateTimer) { timer in - guard let timer else { return } - Application.shared.ledStripUpdateHandler(&timer.pointee) - } - btstack_run_loop_set_timer(&self.ledStripUpdateTimer, ledStripUpdatePeriodMs) - btstack_run_loop_add_timer(&self.ledStripUpdateTimer) - - btstack_run_loop_set_timer_handler(&self.wirelessLedBlinkTimer) { timer in - guard let timer else { return } - Application.shared.wirelessLedBlinkHandler(&timer.pointee) - } - btstack_run_loop_set_timer(&self.wirelessLedBlinkTimer, wirelessLedBlinkPeriodMs) - btstack_run_loop_add_timer(&self.wirelessLedBlinkTimer) - - - btstack_run_loop_execute() // btstack_run_loop_execute never returns - _ = sdp // make sure SDP lives until the runloop exits - } -} - -// Timer handlers -extension Application { - mutating func volumeKnobSamplerHandler(_ timer: inout btstack_timer_source_t) { - let scaleFactor: Int32 = 5 - audioEngine.adjustVolume(by: Application.shared.volumeKnob.delta() * scaleFactor) - btstack_run_loop_set_timer(&timer, volumeKnobSamplerPeriodMs) - btstack_run_loop_add_timer(&timer) - } - - mutating func ledStripUpdateHandler(_ timer: inout btstack_timer_source_t) { - ledStrip.setColor( - red: .random(in: 0...255), - green: .random(in: 0...255), - blue: .random(in: 0...255)) - btstack_run_loop_set_timer(&timer, ledStripUpdatePeriodMs) - btstack_run_loop_add_timer(&timer) - } - - mutating func wirelessLedBlinkHandler(_ timer: inout btstack_timer_source_t) { - self.wirelessLedBlinkState.toggle() - cyw43_arch_gpio_put(WIRELESS_LED_PIN, self.wirelessLedBlinkState) - btstack_run_loop_set_timer(&timer, wirelessLedBlinkPeriodMs) - btstack_run_loop_add_timer(&timer) - } -} - -// Button press callbacks -extension Application { - // FIXME: use `time_us_64` - // This is a particularly large debounce time - static let buttonDebounceTimeMs = 150 - mutating func buttonPressed(pin: UInt32) { - let currentTime = to_ms_since_boot(get_absolute_time()) - guard currentTime - previousPressTimes[pin] > Self.buttonDebounceTimeMs else { - log("soft debounce \(pin)") - return - } - previousPressTimes[pin] = currentTime - - switch pin { - case MUTE_BUTTON_PIN: - self.toggleMute() - case NEXT_BUTTON_PIN: - self.nextTrack() - case PLAY_PAUSE_BUTTON_PIN: - self.playPauseTrack() - case PREVIOUS_BUTTON_PIN: - self.previousTrack() - default: - // ignore - break - } - } - - mutating func toggleMute() { - self.audioEngine.toggleMute() - } - - mutating func nextTrack() { - log("avrcp_controller_forward") - avrcp_controller_forward(avrcp_connection.avrcp_cid) - } - - mutating func playPauseTrack() { - // FIXME: this state management is almost certainly wrong - if audioEngine.running { - log("avrcp_controller_stop") - avrcp_controller_pause(avrcp_connection.avrcp_cid) - } else { - log("avrcp_controller_play") - avrcp_controller_play(avrcp_connection.avrcp_cid) - } - } - - mutating func previousTrack() { - log("avrcp_controller_backward") - avrcp_controller_backward(avrcp_connection.avrcp_cid) - } -} - -extension Application { - func wirelessLedBlink(count: UInt32) { - for _ in 0.. Int32 { - let value = quadrature_encoder_get_count(self.pioHw, self.pioSm) - self.previousValue = value - return value - } - - mutating func delta() -> Int32 { - let value = quadrature_encoder_get_count(self.pioHw, self.pioSm) - // NOTE: Thanks to two's complement arithmetic `delta`` will always be - // correct even when `value`` wraps around `Int32.max` / `Int32.min`. - let delta = value &- self.previousValue - self.previousValue = value - return delta - } -} diff --git a/harmony/Sources/Application/Stubs.swift b/harmony/Sources/Application/Stubs.swift deleted file mode 100644 index b6e8deb0..00000000 --- a/harmony/Sources/Application/Stubs.swift +++ /dev/null @@ -1,39 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// Embedded Swift currently requires posix_memalign, but the C libraries in the -// Pico SDK do not provide it. Let's implement it and forward the calls to -// aligned_alloc(3). -@_cdecl("posix_memalign") -public func posix_memalign( - memptr: UnsafeMutablePointer, - alignment: size_t, - size: size_t -) -> Int32 { - if let allocation = aligned_alloc(alignment, size) { - memptr.pointee = allocation - return 0 - } - return _errno() -} - -// FIXME: document -@_cdecl("swift_isEscapingClosureAtFileLocation") -func swift_isEscapingClosureAtFileLocation( - object: UnsafeRawPointer, - filename: UnsafePointer, - filenameLength: Int32, - line: Int32, - column: Int32, - type: UInt -) -> Bool { - false -} diff --git a/harmony/Sources/Audio/AudioAnalyzer.swift b/harmony/Sources/Audio/AudioAnalyzer.swift deleted file mode 100644 index 1939fd3f..00000000 --- a/harmony/Sources/Audio/AudioAnalyzer.swift +++ /dev/null @@ -1,94 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct AnalyzedAudioBuffer: ~Copyable { - var enableMagnet: Bool - var buffer: AudioBuffer -} - -struct AudioAnalyzer: ~Copyable { - // FIXME: add soft limit for time magnet can be enabled - - var fft_instance: arm_rfft_instance_q15 - // Used for both sample input and fft magnitude output - var dataBuffer0: UnsafeMutableBufferPointer - // Used for fft output - var dataBuffer1: UnsafeMutableBufferPointer - - init() { - let audioBufferCapacity = BUFFER_SAMPLE_CAPACITY - let fftOutputBufferCapacity = BUFFER_SAMPLE_CAPACITY * 2 // real + complex - - self.fft_instance = arm_rfft_instance_q15() - self.dataBuffer0 = .allocate(capacity: audioBufferCapacity) - self.dataBuffer1 = .allocate(capacity: fftOutputBufferCapacity) - // IMPORTANT: `bitReverseFlag` must be set. I don't understand why based on - // the documentation - arm_rfft_init_q15(&fft_instance, UInt32(audioBufferCapacity), 0, 1) - } - - deinit { - self.dataBuffer1.deallocate() - self.dataBuffer0.deallocate() - } - - mutating func run() { - while true { - guard let buffer = Application.shared.audioEngine.buffers.popFullBuffer() else { continue } - - /// Copy data from buffer to dataBuffer0 (because the fft will modify the data) - precondition(self.dataBuffer0.update(from: buffer.storage).index == self.dataBuffer0.count) - // Perform the fft using the data in dataBuffer0 and store the result in dataBuffer1 - arm_rfft_q15(&self.fft_instance, self.dataBuffer0.baseAddress, self.dataBuffer1.baseAddress) - // Calculate the magnitude of the fft output in dataBuffer1 and store the result in dataBuffer0 - arm_cmplx_mag_q15(self.dataBuffer1.baseAddress, self.dataBuffer0.baseAddress, UInt32(self.dataBuffer0.count)) - - // NOTE: This is probably wrong becasue buffer.storage is stereo data - - // Given we take an fft of audio data at 44100 Hz with a window of 512 - // samples, each output bin of the fft represents a 172 Hz range - // (44100 Hz / 2 / 512 = ~172Hz) - - // 1 Khz - let lowend = - self.dataBuffer0[00] + - self.dataBuffer0[01] + - self.dataBuffer0[02] + - self.dataBuffer0[03] + - self.dataBuffer0[04] + - self.dataBuffer0[05] + - self.dataBuffer0[06] + - self.dataBuffer0[07] + - self.dataBuffer0[08] + - self.dataBuffer0[09] + - self.dataBuffer0[10] + - self.dataBuffer0[10] + - self.dataBuffer0[11] + - self.dataBuffer0[12] + - self.dataBuffer0[13] + - self.dataBuffer0[14] + - self.dataBuffer0[15] + - self.dataBuffer0[16] + - self.dataBuffer0[17] + - self.dataBuffer0[18] + - self.dataBuffer0[19] - - - - let avg = lowend / 20 - - let analyzedBuffer = AnalyzedAudioBuffer( - enableMagnet: avg > (1 << 8), - buffer: buffer) - Application.shared.audioEngine.buffers.pushAnalyzedBuffer(analyzedBuffer) - } - } -} diff --git a/harmony/Sources/Audio/AudioBuffer.swift b/harmony/Sources/Audio/AudioBuffer.swift deleted file mode 100644 index 49431b52..00000000 --- a/harmony/Sources/Audio/AudioBuffer.swift +++ /dev/null @@ -1,28 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct AudioBuffer: ~Copyable { - // FIXME: Raw - var storage: UnsafeMutableBufferPointer - var capacity: Int { self.storage.count } - var count: Int - - init(capacity: Int) { - self.storage = .allocate(capacity: capacity) - self.storage.initialize(repeating: 0) - // FIXME: don't assume filled. - self.count = capacity - } - - deinit { - self.storage.deallocate() - } -} diff --git a/harmony/Sources/Audio/AudioBufferTransport.swift b/harmony/Sources/Audio/AudioBufferTransport.swift deleted file mode 100644 index 907637d3..00000000 --- a/harmony/Sources/Audio/AudioBufferTransport.swift +++ /dev/null @@ -1,54 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct AudioBufferTransport: ~Copyable { - var emptyBuffers: Ring - var fullBuffers: Ring - var analyzedBuffers: Ring - - init(bufferCount: Int, bufferCapacity: Int) { - // Ring buffer needs one extra slot to distinguish between empty and full. - self.emptyBuffers = Ring(capacity: bufferCount + 1) - self.fullBuffers = Ring(capacity: bufferCount + 1) - self.analyzedBuffers = Ring(capacity: bufferCount + 1) - - for _ in 0.. AudioBuffer? { - self.emptyBuffers.pop() - } - - mutating func pushFullBuffer(_ buffer: consuming AudioBuffer) { - self.fullBuffers.push(buffer) - } - - mutating func popFullBuffer() -> AudioBuffer? { - self.fullBuffers.pop() - } - - mutating func pushAnalyzedBuffer(_ buffer: consuming AnalyzedAudioBuffer) { - self.analyzedBuffers.push(buffer) - } - - mutating func popAnalyzedBuffer() -> AnalyzedAudioBuffer? { - self.analyzedBuffers.pop() - } -} diff --git a/harmony/Sources/Audio/AudioEngine.swift b/harmony/Sources/Audio/AudioEngine.swift deleted file mode 100644 index 660b2367..00000000 --- a/harmony/Sources/Audio/AudioEngine.swift +++ /dev/null @@ -1,120 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct AudioEngine: ~Copyable { - var running: Bool - var mute: Bool - var volume: UInt8 - var rawVolume: UInt8 - - var audio_pico: AudioPico - var audio_i2s: AudioI2S - var buffers: AudioBufferTransport - var amp: MAX9744 - - init() { - self.running = false - self.mute = false - self.volume = 0 - self.rawVolume = 30 - - self.audio_pico = AudioPico() - self.audio_i2s = AudioI2S( - data_pin: PICO_AUDIO_I2S_DATA_PIN, - clock_pin_base: PICO_AUDIO_I2S_CLOCK_PIN_BASE, - pio: 0, - pio_sm: 0, - // FIXME: Dont claim on each `media_processing_init`?? - dma_channel: UInt32(dma_claim_unused_channel(true))) - self.buffers = AudioBufferTransport(bufferCount: 8, bufferCapacity: BUFFER_SAMPLE_CAPACITY) - self.amp = MAX9744(i2c: i2c0_inst) - - self.set(volume: 0) - } -} - -extension AudioEngine { - mutating func `init`(_ configuration: MediaCodecConfigurationSBC) { - log(#function) - SBCDecoder.configure(mode: SBC_MODE_STANDARD) - - // setup audio playback - // FIXME: update channel count in resampler - // FIXME: update output sample-rate - - self.audio_i2s.update_pio_frequency( - UInt32(configuration.sampling_frequency)) - - self.running = false - } - - mutating func toggleMute() { - self.mute.toggle() - if self.mute { - self.amp.set(rawVolume: 0) - } else { - self.amp.set(rawVolume: rawVolume) - } - } - - mutating func set(volume: UInt8) { - guard self.volume != volume else { return } - self.volume = volume - // FIXME: - avrcp_target_volume_changed(avrcp_connection.avrcp_cid, volume >> 1) - - // Map volume (0-255) to gain (0-63) - let rawVolume = UInt8((UInt32(volume) * 63) / 255) - guard self.rawVolume != rawVolume else { return } - self.rawVolume = rawVolume - - guard !self.mute else { return } - self.amp.set(rawVolume: rawVolume) - } - - mutating func adjustVolume(by delta: Int32) { - guard delta != 0 else { return } - let volume = Int32(self.volume) + delta - let clamped = UInt8(clamping: volume) - log("Adjust volume by \(delta) to \(clamped)") - self.set(volume: clamped) - } - - mutating func start() { - guard !self.running else { return } - guard self.audio_pico.sbc_frames.count >= OPTIMAL_FRAMES_MIN else { return } - log(#function) - // start audio playback - self.audio_pico.start_stream() - self.audio_i2s.enable(true) - self.running = true - } - - mutating func pause() { - guard self.running else { return } - log(#function) - self.close() - } - - mutating func close() { - log(#function) - - // stop audio playback - self.running = false - self.audio_pico.stop_stream() - self.audio_i2s.enable(false) - - // discard pending data - self.audio_pico.decoded_audio.clear() - self.audio_pico.sbc_frame_size = 0 - self.audio_pico.sbc_frames.clear() - } -} diff --git a/harmony/Sources/Audio/AudioI2S.swift b/harmony/Sources/Audio/AudioI2S.swift deleted file mode 100644 index 52e4b96d..00000000 --- a/harmony/Sources/Audio/AudioI2S.swift +++ /dev/null @@ -1,174 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -var zero: UInt32 = 0 - -// FIXME: #define __time_critical_func(func_name) __not_in_flash_func(func_name) -// irq handler for DMA -@_cdecl("audio_i2s_dma_irq_handler") -func audio_i2s_dma_irq_handler() { - Application.shared.audioEngine.audio_i2s.handle_dma_irq() -} - -struct AudioI2S: ~Copyable { - var enabled: Bool - var freq: UInt32 - var playing_buffer: AudioBuffer? - - var pio: UInt32 - var pio_sm: UInt32 - var dma_channel: UInt32 - var pioHw: PIO - - init( - data_pin: UInt32, - clock_pin_base: UInt32, - pio: UInt32, - pio_sm: UInt32, - // FIXME: dma_channel is already claimed - dma_channel: UInt32, - ) { - self.enabled = false - self.freq = 0 - - self.pio = pio - self.pio_sm = pio_sm - self.dma_channel = dma_channel - - let gpioFunc: gpio_function_rp2040 - switch pio { - case 0: - self.pioHw = _pio0() - gpioFunc = GPIO_FUNC_PIO0 - case 1: - self.pioHw = _pio1() - gpioFunc = GPIO_FUNC_PIO1 - default: - fatalError("Invalid PIO index") - } - - gpio_set_function(data_pin, gpioFunc) - gpio_set_function(clock_pin_base, gpioFunc) - gpio_set_function(clock_pin_base + 1, gpioFunc) - - pio_sm_claim(self.pioHw, self.pio_sm) - - let offset = withUnsafePointer(to: audio_i2s_program) { - pio_add_program(self.pioHw, $0) - } - - audio_i2s_program_init( - self.pioHw, self.pio_sm, UInt32(offset), data_pin, clock_pin_base) - - __mem_fence_release() - - var dma_config = dma_channel_get_default_config(dma_channel) - - channel_config_set_dreq( - &dma_config, - UInt32(DREQ_PIO0_TX0.rawValue) + self.pio_sm) - - channel_config_set_transfer_data_size(&dma_config, i2s_dma_configure_size) - dma_channel_configure( - dma_channel, - &dma_config, - // FIXME: .advanced(by: Int(self.pio_sm)) - self.pioHw.pointer(to: \.txf), // dest - nil, // src - 0, // count - false) // trigger - - irq_add_shared_handler( - UInt32(DMA_IRQ_0.rawValue) + PICO_AUDIO_I2S_DMA_IRQ, - audio_i2s_dma_irq_handler, - UInt8(PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY)) - dma_irqn_set_channel_enabled(PICO_AUDIO_I2S_DMA_IRQ, dma_channel, true) - } - - mutating func enable(_ enable: Bool) { - guard self.enabled != enable else { return } - self.enabled = enable - - irq_set_enabled(UInt32(DMA_IRQ_0.rawValue) + PICO_AUDIO_I2S_DMA_IRQ, enable) - - if enable { - self.audio_start_dma_transfer() - } else { - // if there was a buffer in flight, it will not be freed by DMA IRQ, - // let's do it manually - self.audio_finish_dma_transfer() - gpio_put(EM_DRIVE_PIN, false) - } - - pio_sm_set_enabled(self.pioHw, self.pio_sm, enable) - } - - mutating func update_pio_frequency(_ sample_freq: UInt32?) { - guard let sample_freq = sample_freq else { return } - guard sample_freq != self.freq else { return } - - let system_clock_frequency = clock_get_hz(clk_sys) - precondition(system_clock_frequency < 0x4000_0000) - // avoid arithmetic overflow - let divider = system_clock_frequency * 4 / sample_freq - precondition(divider < 0x1000000) - pio_sm_set_clkdiv_int_frac( - self.pioHw, self.pio_sm, UInt16(divider >> 8), UInt8(divider & 0xff)) - self.freq = sample_freq - } - - mutating func handle_dma_irq() { - guard dma_irqn_get_channel_status(PICO_AUDIO_I2S_DMA_IRQ, self.dma_channel) - else { return } - dma_irqn_acknowledge_channel(PICO_AUDIO_I2S_DMA_IRQ, self.dma_channel) - - // free the buffer we just finished - self.audio_finish_dma_transfer() - self.audio_start_dma_transfer() - } - - mutating func audio_start_dma_transfer() { - precondition(self.playing_buffer == nil) - - // FIXME: support dynamic frequency shifting - - if let ab = Application.shared.audioEngine.buffers.popAnalyzedBuffer() { - gpio_put(EM_DRIVE_PIN, ab.enableMagnet) - - let ab = ab.buffer - let buf = UnsafeMutableRawBufferPointer(ab.storage) - self.playing_buffer = consume ab - - var c = dma_get_channel_config(self.dma_channel) - channel_config_set_read_increment(&c, true) - dma_channel_set_config(self.dma_channel, &c, false) - dma_channel_transfer_from_buffer_now( - self.dma_channel, - buf.baseAddress, - // FIXME: using capacity instead of ab count - UInt32(buf.count) / 4) - } else { - gpio_put(EM_DRIVE_PIN, false) - log("buffer pool low") - // just play some silence - var c = dma_get_channel_config(self.dma_channel) - channel_config_set_read_increment(&c, false) - dma_channel_set_config(self.dma_channel, &c, false) - dma_channel_transfer_from_buffer_now( - self.dma_channel, &zero, PICO_AUDIO_I2S_SILENCE_BUFFER_SAMPLE_LENGTH) - } - } - - mutating func audio_finish_dma_transfer() { - guard let playingBuffer = self.playing_buffer.take() else { return } - Application.shared.audioEngine.buffers.pushEmptyBuffer(playingBuffer) - } -} diff --git a/harmony/Sources/Audio/AudioPico.swift b/harmony/Sources/Audio/AudioPico.swift deleted file mode 100644 index ef540daf..00000000 --- a/harmony/Sources/Audio/AudioPico.swift +++ /dev/null @@ -1,181 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -extension UnsafeMutableBufferPointer where Element: ~Copyable { - func split(at index: Self.Index) -> (Self, Self) { - (self.extracting(.. - var sbc_frames: RingBuffer - var sbc_frames_in_buffer: Int { - guard sbc_frame_size > 0 else { return 0 } - return self.sbc_frames.count / self.sbc_frame_size - } - - // overflow buffer for not fully used sbc frames, with additional frames for resampling - let decoded_audio_buffer: UnsafeMutableBufferPointer - var decoded_audio: RingBuffer - - init() { - let CHANNELS_PER_FRAME = 2 - let capacity = (128 + 16) * CHANNELS_PER_FRAME - - self.fill_timer = btstack_timer_source_t() - self.resampler = Resampler(channels: CHANNELS_PER_FRAME) - - self.sbc_frame_size = 0 - self.sbc_frame_buffer = UnsafeMutableBufferPointer.allocate( - capacity: MAX_SBC_FRAME_SIZE) - self.sbc_frames = RingBuffer( - capacity: (OPTIMAL_FRAMES_MAX + ADDITIONAL_FRAMES) * MAX_SBC_FRAME_SIZE) - - self.decoded_audio_buffer = .allocate(capacity: capacity) - self.decoded_audio = RingBuffer(capacity: capacity) - } - - mutating func enqueue(sbc_frames: UnsafeMutableBufferPointer, frame_size: Int) - { - self.sbc_frame_size = frame_size - if !self.sbc_frames.write(contentsOf: sbc_frames) { - log("Error: SBC frame buffer overflow") - } - self.updateResamplingFactor() - } - - mutating func updateResamplingFactor() { - let nominal_factor: UInt32 = 0x10000 - let compensation: UInt32 = 0x00100 - - let resampling_factor = - switch self.sbc_frames_in_buffer { - case ..) { - // called from lower-layer but guaranteed to be on main thread - guard self.sbc_frame_size != 0 else { - log("Frame size is 0") - buffer.update(repeating: 0) - return - } - - // first fill from resampled audio - let samplesReadCount = self.decoded_audio.read(into: buffer) - var buffer = buffer.extracting(samplesReadCount...) - - // then start decoding sbc frames into the buffer - while buffer.count > 0, self.sbc_frames.count > self.sbc_frame_size { - // decode frame - let elementsRead = self.sbc_frames.read( - into: self.sbc_frame_buffer, count: self.sbc_frame_size) - precondition( - elementsRead == self.sbc_frame_size, "sbc frame size mismatch") - - SBCDecoder.decode_signed_16( - mode: SBC_MODE_STANDARD, - packet_status_flag: 0, - buffer: UnsafeRawBufferPointer(self.sbc_frame_buffer) - ) { samples, num_channels, sample_rate in - precondition(num_channels == 2, "must be stereo") - - // Resample audio to compensate for the amount of buffered SBC frames - let samples = self.resampler.resample( - samples: .init(samples), - usingTemporaryBuffer: self.decoded_audio_buffer) - - // Store samples in buffer first and excess in the ring buffer. - let (samples_to_copy, samples_to_store) = samples.split( - at: min(samples.count, buffer.count)) - let samplesCopiedCount = buffer.moveUpdate( - fromContentsOf: samples_to_copy) - buffer = buffer.extracting(samplesCopiedCount...) - if !self.decoded_audio.write(contentsOf: samples_to_store) { - log("ERROR: PCM ring buffer full!") - } - } - } - } - - mutating func fill_timer( - _ timer: UnsafeMutablePointer? - ) { - // refill - self.fill_buffers() - - // re-set timer - btstack_run_loop_set_timer(timer, UInt32(DRIVER_POLL_INTERVAL_MS)) - btstack_run_loop_add_timer(timer) - } - - mutating func start_stream() { - // pre-fill buffers - self.fill_buffers() - - // start timer - // FIXME: Use ctx - // NOTE: hardcoded to `Self` because the timer callback has no context - // argument which can be used to pass `self` - btstack_run_loop_set_timer_handler( - &self.fill_timer, { Application.shared.audioEngine.audio_pico.fill_timer($0) }) - btstack_run_loop_set_timer_context(&self.fill_timer, nil) - btstack_run_loop_set_timer( - &self.fill_timer, UInt32(DRIVER_POLL_INTERVAL_MS)) - btstack_run_loop_add_timer(&self.fill_timer) - } - - mutating func stop_stream() { - // stop timer - btstack_run_loop_remove_timer(&self.fill_timer) - } -} diff --git a/harmony/Sources/Audio/MAX9744.swift b/harmony/Sources/Audio/MAX9744.swift deleted file mode 100644 index 6c969508..00000000 --- a/harmony/Sources/Audio/MAX9744.swift +++ /dev/null @@ -1,105 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct MAX9744: ~Copyable { - static let i2cAddress: UInt8 = 0x4B // 7 bit address - static let absoluteVolumeControlRegisterAddress: UInt8 = 0x0 - - static let modulationControlRegisterAddress: UInt8 = 0x1 - static let filterlessModulationBitPattern: UInt8 = 0x0 - static let pwmModulationBitPattern: UInt8 = 0x1 - - static let incrementalVolumeControlRegisterAddress: UInt8 = 0x3 - static let increaseVolumeBitPattern: UInt8 = 0x4 - static let decreaseVolumeBitPattern: UInt8 = 0x5 - - var i2c: i2c_inst_t - - init(i2c: i2c_inst_t) { - self.i2c = i2c - } -} - -extension MAX9744 { - static func validAddress(_ address: UInt8) -> Bool { - switch address { - case Self.absoluteVolumeControlRegisterAddress: true - case Self.filterlessModulationBitPattern: true - case Self.incrementalVolumeControlRegisterAddress: true - default: false - } - } - - mutating func write(address: UInt8, value: UInt8) { - precondition(Self.validAddress(address)) - var data = (address << 6) | value - log("attempting to write \(hex: data)") - let size = MemoryLayout.size(ofValue: data) - let result = i2c_write_blocking( - &self.i2c, - Self.i2cAddress, - &data, - size, - false) - precondition(result == size, "I2C write failed") - } - - mutating func read(address: UInt8) -> UInt8 { - precondition(Self.validAddress(address)) - var data = address << 6 - let size = MemoryLayout.size(ofValue: data) - let readResult = i2c_read_blocking( - &self.i2c, - Self.i2cAddress, - &data, - size, - false) - precondition(readResult == size, "I2C read failed") - return data - } -} - -extension MAX9744 { - /// 6 bit value ranging from 0 (mute) to 63 (+ 9.5 dB) - mutating func set(rawVolume: UInt8) { - precondition(0 <= rawVolume && rawVolume <= 63) - self.write( - address: Self.absoluteVolumeControlRegisterAddress, - value: rawVolume) - } - - enum ModulationMode { - case filterless - case pwm - } - - mutating func set(moduluationMode: ModulationMode) { - let modulationBitPattern = switch moduluationMode { - case .filterless: Self.filterlessModulationBitPattern - case .pwm: Self.pwmModulationBitPattern - } - self.write( - address: Self.modulationControlRegisterAddress, - value: modulationBitPattern) - } - - mutating func increaseVolume() { - self.write( - address: Self.incrementalVolumeControlRegisterAddress, - value: Self.increaseVolumeBitPattern) - } - - mutating func decreaseVolume() { - self.write( - address: Self.incrementalVolumeControlRegisterAddress, - value: Self.decreaseVolumeBitPattern) - } -} diff --git a/harmony/Sources/Audio/Resampler.swift b/harmony/Sources/Audio/Resampler.swift deleted file mode 100644 index ef4cd8bb..00000000 --- a/harmony/Sources/Audio/Resampler.swift +++ /dev/null @@ -1,52 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct Resampler: ~Copyable { - var channels: Int - var context: btstack_resample_t - - init(channels: Int) { - self.channels = channels - self.context = btstack_resample_t() - btstack_resample_init(&self.context, Int32(channels)) - } - - mutating func set(channels: Int) { - self.channels = channels - btstack_resample_init(&self.context, Int32(channels)) - } - - mutating func set(factor: UInt32) { - btstack_resample_set_factor(&self.context, factor) - } - - /// Resamples the given samples using the previously set resampling factor. - /// - /// Returns a slice of the temporary buffer that contains the resampled audio. - mutating func resample( - samples: UnsafeBufferPointer, - usingTemporaryBuffer buffer: UnsafeMutableBufferPointer - ) -> UnsafeMutableBufferPointer { - precondition(samples.count.isMultiple(of: self.channels)) - - // FIXME: understand why this is not `samples.count / self.channels` - // The documentation just calls this parameter `numFrames` which implies - // the sample count should be divided by the channel count. - let inputFrameCount = samples.count - let resampledFrameCount = btstack_resample_block( - &self.context, - samples.baseAddress, - UInt32(inputFrameCount), - buffer.baseAddress) - let resampledSampleCount = Int(resampledFrameCount) * self.channels - return buffer.extracting(..: ~Copyable { - // FIMXE: Use an inline allocation like `Vector` - var storage: UnsafeMutableBufferPointer - var readerIndex: Int - var writerIndex: Int - - init(capacity: Int) { - self.storage = .allocate(capacity: capacity) - self.readerIndex = 0 - self.writerIndex = 0 - } - - deinit { - var readerIndex = self.readerIndex - while self.readerIndex != self.writerIndex { - self.storage.deinitializeElement(at: readerIndex) - readerIndex = (readerIndex + 1) % self.storage.count - } - // FIXME: why can't we use a mutating method here? - // while _ = self.pop() { } - self.storage.deallocate() - } -} - -extension Ring where Element: ~Copyable { - mutating func push(_ element: consuming Element) { - let nextWriterIndex = (self.writerIndex + 1) % self.storage.count - guard nextWriterIndex != self.readerIndex else { fatalError("Overflow") } - self.storage.initializeElement(at: self.writerIndex, to: element) - __dsb() // Make sure the element is written before updating the index - self.writerIndex = nextWriterIndex - } - - mutating func pop() -> Element? { - guard self.readerIndex != self.writerIndex else { return nil } - let element = self.storage.moveElement(from: self.readerIndex) - __dsb() // Make sure the element is read before updating the index - self.readerIndex = (self.readerIndex + 1) % self.storage.count - return element - } -} diff --git a/harmony/Sources/Audio/RingBuffer.swift b/harmony/Sources/Audio/RingBuffer.swift deleted file mode 100644 index 11a30d0e..00000000 --- a/harmony/Sources/Audio/RingBuffer.swift +++ /dev/null @@ -1,126 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// FIXME: RingBuffer -struct RingBuffer: ~Copyable { - // FIMXE: Use an inline allocation like `Vector` - var storage: UnsafeMutableBufferPointer - var count: Int - var readerIndex: Int - var writerIndex: Int - - init(capacity: Int) { - self.storage = .allocate(capacity: capacity) - self.readerIndex = 0 - self.writerIndex = 0 - self.count = 0 - } - - deinit { - self.storage.deallocate() - } -} - -extension RingBuffer { - var capacity: Int { self.storage.count } - var availableCapacity: Int { self.capacity - self.count } - var isEmpty: Bool { self.count == 0 } - var isFull: Bool { self.count == self.capacity } -} - -extension RingBuffer { - mutating func clear() { - // Forget about the contents of `storage`, this is safe because - // `Element` is `BitwiseCopyable`. - self.count = 0 - self.readerIndex = 0 - self.writerIndex = 0 - } - - mutating func read( - into buffer: UnsafeMutableBufferPointer, - count: Int? = nil - ) -> Int { - let elementsToRead = min(buffer.count, count ?? Int.max, self.count) - - // Reading 0 elements is a no-op. - guard elementsToRead > 0 else { return elementsToRead } - - // Read the initial elements from the end of the ring buffer. - let elementsUntilEnd = self.capacity - self.readerIndex - let elementsToReadFirstHalf = min(elementsUntilEnd, elementsToRead) - buffer.baseAddress!.update( - from: self.storage.baseAddress! + self.readerIndex, - count: elementsToReadFirstHalf) - self.readerIndex += elementsToReadFirstHalf - - // Update the reader index to wrap if needed. - if self.readerIndex == self.capacity { - self.readerIndex = 0 - } - - // Read the remaining elements from the beginning of the ring buffer. - let elementsToReadSecondHalf = elementsToRead - elementsToReadFirstHalf - precondition(elementsToReadSecondHalf >= 0) - (buffer.baseAddress! + elementsToReadFirstHalf).update( - from: self.storage.baseAddress! + self.readerIndex, - count: elementsToReadSecondHalf) - self.readerIndex += elementsToReadSecondHalf - - // Update bookkeeping with the new count. - self.count -= elementsToRead - - return elementsToRead - } - - mutating func write( - contentsOf buffer: UnsafeMutableBufferPointer - ) -> Bool { - self.write(contentsOf: UnsafeBufferPointer(buffer)) - } - - mutating func write( - contentsOf buffer: UnsafeBufferPointer - ) -> Bool { - let elementsToWrite = buffer.count - - // Writing 0 elements is a no-op. - guard elementsToWrite > 0 else { return true } - // Writing more than the available capacity is an error. - guard elementsToWrite <= self.availableCapacity else { return false } - - // Write the initial elements to the end of the ring buffer. - let elementsUntilEnd = self.capacity - self.writerIndex - let elementsToWriteFirstHalf = min(elementsUntilEnd, elementsToWrite) - (self.storage.baseAddress! + self.writerIndex).update( - from: buffer.baseAddress!, - count: elementsToWriteFirstHalf) - self.writerIndex += elementsToWriteFirstHalf - - // Update the writer index to wrap if needed. - if self.writerIndex == self.capacity { - self.writerIndex = 0 - } - - // Write the remaining elements to the beginning of the ring buffer. - let elementsToWriteSecondHalf = elementsToWrite - elementsToWriteFirstHalf - precondition(elementsToWriteSecondHalf >= 0) - (self.storage.baseAddress! + self.writerIndex).update( - from: buffer.baseAddress! + elementsToWriteFirstHalf, - count: elementsToWriteSecondHalf) - self.writerIndex += elementsToWriteSecondHalf - - // Update bookkeeping with the new count. - self.count += elementsToWrite - - return true - } -} diff --git a/harmony/Sources/Audio/SpinLock.swift b/harmony/Sources/Audio/SpinLock.swift deleted file mode 100644 index 8212f04f..00000000 --- a/harmony/Sources/Audio/SpinLock.swift +++ /dev/null @@ -1,38 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct SpinLock: ~Copyable { - var _lock: UnsafeMutablePointer - var value: Value - - init(index: Int, initialValue: consuming Value) { - self._lock = spin_lock_init(UInt32(index)) - self.value = initialValue - } -} - -extension SpinLock where Value: ~Copyable { - func lock() -> UInt32 { - spin_lock_blocking(self._lock) - } - - func unlock(irq_mask: UInt32) { - spin_unlock(self._lock, irq_mask) - } - - mutating func withLock( - _ body: (inout Value) throws(Error) -> Result - ) throws(Error) -> Result where Result: ~Copyable { - let irq_mask = self.lock() - defer { self.unlock(irq_mask: irq_mask) } - return try body(&self.value) - } -} diff --git a/harmony/Sources/Audio/TPA2016D2.swift b/harmony/Sources/Audio/TPA2016D2.swift deleted file mode 100644 index 59b56640..00000000 --- a/harmony/Sources/Audio/TPA2016D2.swift +++ /dev/null @@ -1,118 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -func i2c_init() { - i2c_init(&i2c0_inst, 100 * 1000) // 400kHz "Fast Mode" - gpio_set_function(UInt32(PICO_DEFAULT_I2C_SDA_PIN), GPIO_FUNC_I2C) - gpio_set_function(UInt32(PICO_DEFAULT_I2C_SCL_PIN), GPIO_FUNC_I2C) - gpio_pull_up(UInt32(PICO_DEFAULT_I2C_SDA_PIN)) - gpio_pull_up(UInt32(PICO_DEFAULT_I2C_SCL_PIN)) - - // I2C reserves some addresses for special purposes. We exclude these from the scan. - // These are any addresses of the form 000 0xxx or 111 1xxx - func reserved_addr(_ addr: UInt8) -> Bool{ - return (addr & 0x78) == 0 || (addr & 0x78) == 0x78 - } - - log("\nI2C Bus Scan") - log(" 0 1 2 3 4 5 6 7 8 9 A B C D E F") - for addr in UInt8(0) ..< (1 << 7) { - if addr.isMultiple(of: 16) { - log("\(addr >> 4) ", terminator: "") - } - - // Perform a 1-byte dummy read from the probe address. If a slave - // acknowledges this address, the function returns the number of bytes - // transferred. If the address byte is ignored, the function returns - // -1. - - // Skip over any reserved addresses. - var rxdata: UInt8 = 0 - let ret = if reserved_addr(addr) { - Int32(PICO_ERROR_GENERIC.rawValue) - } else { - i2c_read_blocking(&i2c0_inst, addr, &rxdata, 1, false) - } - - log(ret < 0 ? "." : "@", terminator: addr % 16 == 15 ? "\n" : " ") - } - log("Done.\n") -} - -struct TPA2016D2: ~Copyable { - static let address: UInt8 = 0x58 // 7 bit address - static let IC_FUNCTION_CONTROL: UInt8 = 0x1 - static let AGC_ATTACK_CONTROL: UInt8 = 0x2 - static let AGC_RELEASE_CONTROL: UInt8 = 0x3 - static let AGC_HOLD_TIME_CONTROL: UInt8 = 0x4 - static let AGC_FIXED_GAIN_CONTROL: UInt8 = 0x5 - static let AGC_CONTROL_0: UInt8 = 0x6 - static let AGC_CONTROL_1: UInt8 = 0x7 - - var i2c: i2c_inst_t - - init(i2c: i2c_inst_t) { - self.i2c = i2c - - for r in UInt8(0x1) ... 0x7 { - log("Register \(hex: r); read \(hex: self.read(address: r))") - } - - // Immediately configure the amp to our desired defaults. - // Disable AGC (Automatic Gain Control). - self.write(address: Self.AGC_CONTROL_1, value: 0x0) - // Disable Output Limiter - self.write(address: Self.AGC_CONTROL_0, value: 1 << 7) - // Set the attack time to the fastest setting (0.1067 ms per step) - self.write(address: Self.AGC_ATTACK_CONTROL, value: 1) - // Set the release time to the fastest setting (0.0137 s per step) - self.write(address: Self.AGC_RELEASE_CONTROL, value: 1) - // Disable the hold time entirely - self.write(address: Self.AGC_HOLD_TIME_CONTROL, value: 0) - } -} - -extension TPA2016D2 { - mutating func write(address: UInt8, value: UInt8) { - var combined: UInt16 = (UInt16(value) << 8) | UInt16(address) - let result = i2c_write_blocking( - &self.i2c, - Self.address, - &combined, - MemoryLayout.size(ofValue: combined), - false) - precondition(result == 2, "I2C write failed") - // log("Register \(hex: address); wrote \(hex: value) - read \(hex: self.read(address: address))") - } - - mutating func read(address: UInt8) -> UInt8 { - var data = address - let writeResult = i2c_write_blocking(&self.i2c, Self.address, &data, 1, false) - precondition(writeResult == 1, "I2C write failed") - let readResult = i2c_read_blocking(&self.i2c, Self.address, &data, 1, false) - precondition(readResult == 1, "I2C read failed") - return data - } -} - -extension TPA2016D2 { - // scale from 0 to 255 - mutating func set(gain: UInt8) { - precondition(0 <= gain && gain <= 30) - self.write(address: Self.AGC_FIXED_GAIN_CONTROL, value: gain) - } - - mutating func mute(_ mute: Bool) { - var value = self.read(address: Self.IC_FUNCTION_CONTROL) - value = mute ? value | (1 << 5) : value & ~(1 << 5) - self.write(address: Self.IC_FUNCTION_CONTROL, value: value) - } -} diff --git a/harmony/Sources/Audio/Timer.swift b/harmony/Sources/Audio/Timer.swift deleted file mode 100644 index acad420a..00000000 --- a/harmony/Sources/Audio/Timer.swift +++ /dev/null @@ -1,20 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// struct Timer: ~Copyable, ~Escapable { -// var context: UnsafePointer - -// init(context: borrowing Context) dependsOn(context) { -// withUnsafePointerToInstance(context) { context in -// self.context = context -// } -// } -// } \ No newline at end of file diff --git a/harmony/Sources/Bluetooth/A2DP.swift b/harmony/Sources/Bluetooth/A2DP.swift deleted file mode 100644 index ebb257f6..00000000 --- a/harmony/Sources/Bluetooth/A2DP.swift +++ /dev/null @@ -1,300 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// Advanced Audio Distribution Profile - -struct MediaCodecConfigurationSBC { - var reconfigure: UInt8 - var num_channels: UInt8 - var sampling_frequency: UInt16 - var block_length: UInt8 - var subbands: UInt8 - var min_bitpool_value: UInt8 - var max_bitpool_value: UInt8 - var channel_mode: btstack_sbc_channel_mode_t - var allocation_method: btstack_sbc_allocation_method_t - - init() { - self.reconfigure = 0 - self.num_channels = 0 - self.sampling_frequency = 0 - self.block_length = 0 - self.subbands = 0 - self.min_bitpool_value = 0 - self.max_bitpool_value = 0 - self.channel_mode = SBC_CHANNEL_MODE_MONO - self.allocation_method = SBC_ALLOCATION_METHOD_LOUDNESS - } - - func dump() { - log( - """ - - num_channels: \(self.num_channels) - - sampling_frequency: \(self.sampling_frequency) - - channel_mode: \(self.channel_mode.rawValue) - - block_length: \(self.block_length) - - subbands: \(self.subbands) - - allocation_method: \(self.allocation_method.rawValue) - - bitpool_value [\(self.min_bitpool_value), \(self.max_bitpool_value)] - """) - } -} - -enum StreamState { - case closed - case open - case playing - case paused -} - -struct A2DPConnection { - static var shared = Self() - - var addr: bd_addr_t = (0, 0, 0, 0, 0, 0) - var a2dp_cid: UInt16 = 0 - var a2dp_local_seid: UInt8 = 0 - var stream_state: StreamState = .closed - var sbc_configuration: MediaCodecConfigurationSBC = .init() -} - -@_cdecl("a2dp_sink_packet_handler") -func a2dp_sink_packet_handler( - packet_type: UInt8, - channel: UInt16, - packet: UnsafeMutablePointer?, - size: UInt16 -) { - guard packet_type == HCI_EVENT_PACKET else { return } - guard hci_event_packet_get_type(packet) == HCI_EVENT_A2DP_META else { return } - - let subevent = packet?[2] - switch subevent { - case UInt8(A2DP_SUBEVENT_SIGNALING_MEDIA_CODEC_OTHER_CONFIGURATION): - log("A2DP Sink : Received non SBC codec - not implemented") - - case UInt8(A2DP_SUBEVENT_SIGNALING_MEDIA_CODEC_SBC_CONFIGURATION): - log("A2DP Sink : Received SBC codec configuration") - A2DPConnection.shared.sbc_configuration.reconfigure = - a2dp_subevent_signaling_media_codec_sbc_configuration_get_reconfigure( - packet) - A2DPConnection.shared.sbc_configuration.num_channels = - a2dp_subevent_signaling_media_codec_sbc_configuration_get_num_channels( - packet) - A2DPConnection.shared.sbc_configuration.sampling_frequency = - a2dp_subevent_signaling_media_codec_sbc_configuration_get_sampling_frequency( - packet) - A2DPConnection.shared.sbc_configuration.block_length = - a2dp_subevent_signaling_media_codec_sbc_configuration_get_block_length( - packet) - A2DPConnection.shared.sbc_configuration.subbands = - a2dp_subevent_signaling_media_codec_sbc_configuration_get_subbands(packet) - A2DPConnection.shared.sbc_configuration.min_bitpool_value = - a2dp_subevent_signaling_media_codec_sbc_configuration_get_min_bitpool_value( - packet) - A2DPConnection.shared.sbc_configuration.max_bitpool_value = - a2dp_subevent_signaling_media_codec_sbc_configuration_get_max_bitpool_value( - packet) - - let allocation_method = - a2dp_subevent_signaling_media_codec_sbc_configuration_get_allocation_method( - packet) - - // Adapt Bluetooth spec definition to SBC Encoder expected input - A2DPConnection.shared.sbc_configuration.allocation_method = - (btstack_sbc_allocation_method_t)(allocation_method - 1) - - switch avdtp_channel_mode_t( - a2dp_subevent_signaling_media_codec_sbc_configuration_get_channel_mode( - packet)) - { - case AVDTP_CHANNEL_MODE_JOINT_STEREO: - A2DPConnection.shared.sbc_configuration.channel_mode = - SBC_CHANNEL_MODE_JOINT_STEREO - case AVDTP_CHANNEL_MODE_STEREO: - A2DPConnection.shared.sbc_configuration.channel_mode = - SBC_CHANNEL_MODE_STEREO - case AVDTP_CHANNEL_MODE_DUAL_CHANNEL: - A2DPConnection.shared.sbc_configuration.channel_mode = - SBC_CHANNEL_MODE_DUAL_CHANNEL - case AVDTP_CHANNEL_MODE_MONO: - A2DPConnection.shared.sbc_configuration.channel_mode = - SBC_CHANNEL_MODE_MONO - default: - fatalError() - } - A2DPConnection.shared.sbc_configuration.dump() - - case UInt8(A2DP_SUBEVENT_STREAM_ESTABLISHED): - let status = a2dp_subevent_stream_established_get_status(packet) - guard status == ERROR_CODE_SUCCESS else { - log( - "A2DP Sink : Streaming connection failed, status \(hex: status)" - ) - return - } - - a2dp_subevent_stream_established_get_bd_addr( - packet, &A2DPConnection.shared.addr) - A2DPConnection.shared.a2dp_cid = - a2dp_subevent_stream_established_get_a2dp_cid(packet) - A2DPConnection.shared.a2dp_local_seid = - a2dp_subevent_stream_established_get_local_seid(packet) - A2DPConnection.shared.stream_state = .open - - log( - "A2DP Sink : Streaming connection is established, address \(cString: bd_addr_to_str(&A2DPConnection.shared.addr)), cid \(hex: A2DPConnection.shared.a2dp_cid), local seid \(A2DPConnection.shared.a2dp_local_seid)" - ) - - #if ENABLE_AVDTP_ACCEPTOR_EXPLICIT_START_STREAM_CONFIRMATION - case UInt8(A2DP_SUBEVENT_START_STREAM_REQUESTED): - log( - "A2DP Sink : Explicit Accept to start stream, local_seid %d\n", - a2dp_subevent_start_stream_requested_get_local_seid(packet)) - a2dp_sink_start_stream_accept(a2dp_cid, a2dp_local_seid) - #endif - - case UInt8(A2DP_SUBEVENT_STREAM_STARTED): - log("A2DP Sink : Stream started") - A2DPConnection.shared.stream_state = .playing - if A2DPConnection.shared.sbc_configuration.reconfigure != 0 { - Application.shared.audioEngine.close() - } - // prepare media processing - // audio playback starts when buffer reaches minimal level - Application.shared.audioEngine.`init`(A2DPConnection.shared.sbc_configuration) - - case UInt8(A2DP_SUBEVENT_STREAM_SUSPENDED): - log("A2DP Sink : Stream paused") - A2DPConnection.shared.stream_state = .paused - Application.shared.audioEngine.pause() - - case UInt8(A2DP_SUBEVENT_STREAM_RELEASED): - log("A2DP Sink : Stream released") - A2DPConnection.shared.stream_state = .closed - Application.shared.audioEngine.close() - - case UInt8(A2DP_SUBEVENT_SIGNALING_CONNECTION_RELEASED): - log("A2DP Sink : Signaling connection released") - A2DPConnection.shared.a2dp_cid = 0 - Application.shared.audioEngine.close() - - default: - log("AVRCP Sink : Event \(hex: subevent ?? 0xff) is not parsed") - } -} - -/* @section Handle Media Data Packet - * - * @text Here the audio data, are received through the a2dp_sink_media_handler callback. - * Currently, only the SBC media codec is supported. Hence, the media data consists of the media packet header and the SBC packet. - * The SBC frame will be stored in a ring buffer for later processing (instead of decoding it to PCM right away which would require a much larger buffer). - * If the audio stream wasn't started already and there are enough SBC frames in the ring buffer, start playback. - */ - -func read_media_data_header( - _ packet: UnsafeMutablePointer?, - _ size: Int32, - _ offset: UnsafeMutablePointer, - _ media_header: UnsafeMutablePointer -) -> Bool { - guard let packet else { return false } - let media_header_len: Int32 = 12 // without crc - var pos = Int(offset.pointee) - - if size - Int32(pos) < media_header_len { - log( - "Not enough data to read media packet header, expected \(media_header_len), received \(size-Int32(pos))" - ) - return false - } - - media_header.pointee.version = packet[pos] & 0x03 - media_header.pointee.padding = UInt8(get_bit16(UInt16(packet[pos]), 2)) - media_header.pointee.extension = UInt8(get_bit16(UInt16(packet[pos]), 3)) - media_header.pointee.csrc_count = (packet[pos] >> 4) & 0x0F - pos += 1 - - media_header.pointee.marker = UInt8(get_bit16(UInt16(packet[pos]), 0)) - media_header.pointee.payload_type = (packet[pos] >> 1) & 0x7F - pos += 1 - - media_header.pointee.sequence_number = UInt16( - big_endian_read_16(packet, Int32(pos))) - pos += 2 - - media_header.pointee.timestamp = big_endian_read_32(packet, Int32(pos)) - pos += 4 - - media_header.pointee.synchronization_source = big_endian_read_32( - packet, Int32(pos)) - pos += 4 - offset.pointee = Int32(pos) - return true -} - -func read_sbc_header( - _ packet: UnsafeMutablePointer?, - _ size: Int32, - _ offset: UnsafeMutablePointer, - _ sbc_header: UnsafeMutablePointer -) -> Bool { - guard let packet else { return false } - let sbc_header_len: Int32 = 12 // without crc - var pos: Int32 = offset.pointee - - if size - pos < sbc_header_len { - log( - "Not enough data to read SBC header, expected \(sbc_header_len), received \(size-pos)" - ) - return false - } - - sbc_header.pointee.fragmentation = UInt8( - get_bit16(UInt16(packet[Int(pos)]), 7)) - sbc_header.pointee.starting_packet = UInt8( - get_bit16(UInt16(packet[Int(pos)]), 6)) - sbc_header.pointee.last_packet = UInt8(get_bit16(UInt16(packet[Int(pos)]), 5)) - sbc_header.pointee.num_frames = UInt8(packet[Int(pos)] & 0x0f) - pos += 1 - offset.pointee = pos - return true -} - -@_cdecl("a2dp_sink_media_handler") -func a2dp_sink_media_handler( - seid: UInt8, - packet: UnsafeMutablePointer?, - size: UInt16 -) { - var pos: Int32 = 0 - - var media_header = avdtp_media_packet_header_t() - guard read_media_data_header(packet, Int32(size), &pos, &media_header) else { - log("Failed to read media data header") - return - } - - var sbc_header = avdtp_sbc_codec_header_t() - guard read_sbc_header(packet, Int32(size), &pos, &sbc_header) else { - log("Failed to read SBC header") - return - } - - let packet_length = UInt32(size) - UInt32(pos) - let packet_begin = packet?.advanced(by: Int(pos)) - let sbc_frame_size = Int(packet_length / UInt32(sbc_header.num_frames)) - - let packetBuffer = UnsafeMutableBufferPointer( - start: packet_begin, count: Int(packet_length)) - Application.shared.audioEngine.audio_pico.enqueue( - sbc_frames: packetBuffer, frame_size: sbc_frame_size) - Application.shared.audioEngine.start() -} diff --git a/harmony/Sources/Bluetooth/AVRCP.swift b/harmony/Sources/Bluetooth/AVRCP.swift deleted file mode 100644 index 6f5bc44a..00000000 --- a/harmony/Sources/Bluetooth/AVRCP.swift +++ /dev/null @@ -1,286 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// Audio/Video Remote Control Profile - -struct AVRCPConnection { - var addr: bd_addr_t - var avrcp_cid: UInt16 - var playing: Bool - var notifications_supported_by_target: UInt16 -} - -var avrcp_connection = AVRCPConnection( - addr: (0, 0, 0, 0, 0, 0), - avrcp_cid: 0, - playing: false, - notifications_supported_by_target: 0) - -@_cdecl("avrcp_packet_handler") -func avrcp_packet_handler( - packet_type: UInt8, - channel: UInt16, - packet: UnsafeMutablePointer?, - size: UInt16 -) { - guard packet_type == HCI_EVENT_PACKET else { return } - guard hci_event_packet_get_type(packet) == HCI_EVENT_AVRCP_META else { - return - } - - let subevent = packet?[2] - switch subevent { - case UInt8(AVRCP_SUBEVENT_CONNECTION_ESTABLISHED): - log("AVRCP_SUBEVENT_CONNECTION_ESTABLISHED") - let local_cid = avrcp_subevent_connection_established_get_avrcp_cid(packet) - let status = avrcp_subevent_connection_established_get_status(packet) - - if status != ERROR_CODE_SUCCESS { - log("AVRCP: Connection failed, status \(hex: status)") - avrcp_connection.avrcp_cid = 0 - return - } - - avrcp_connection.avrcp_cid = local_cid - var address: bd_addr_t = (0, 0, 0, 0, 0, 0) - avrcp_subevent_connection_established_get_bd_addr(packet, &address) - log( - "AVRCP: Connected to \(cString: bd_addr_to_str(&address)), cid \(hex: avrcp_connection.avrcp_cid)" - ) - - avrcp_target_support_event( - avrcp_connection.avrcp_cid, AVRCP_NOTIFICATION_EVENT_VOLUME_CHANGED) - avrcp_target_support_event( - avrcp_connection.avrcp_cid, AVRCP_NOTIFICATION_EVENT_BATT_STATUS_CHANGED) - let battery_status = AVRCP_BATTERY_STATUS_WARNING - avrcp_target_battery_status_changed( - avrcp_connection.avrcp_cid, battery_status) - - // query supported events: - avrcp_controller_get_supported_events(avrcp_connection.avrcp_cid) - - case UInt8(AVRCP_SUBEVENT_CONNECTION_RELEASED): - log("AVRCP_SUBEVENT_CONNECTION_RELEASED") - log( - "AVRCP: Channel released: cid \(hex: avrcp_subevent_connection_released_get_avrcp_cid(packet))" - ) - avrcp_connection.avrcp_cid = 0 - avrcp_connection.notifications_supported_by_target = 0 - - default: - log("AVRCP: Event \(hex: subevent ?? 0xff) is not parsed") - } -} - -@_cdecl("avrcp_controller_packet_handler") -func avrcp_controller_packet_handler( - packet_type: UInt8, - channel: UInt16, - packet: UnsafeMutablePointer?, - size: UInt16 -) { - guard packet_type == HCI_EVENT_PACKET else { return } - guard hci_event_packet_get_type(packet) == HCI_EVENT_AVRCP_META else { - return - } - guard avrcp_connection.avrcp_cid != 0 else { return } - - let subevent = packet?[2] - switch subevent { - case UInt8(AVRCP_SUBEVENT_GET_CAPABILITY_EVENT_ID): - avrcp_connection.notifications_supported_by_target |= - (1 << avrcp_subevent_get_capability_event_id_get_event_id(packet)) - - case UInt8(AVRCP_SUBEVENT_GET_CAPABILITY_EVENT_ID_DONE): - log("AVRCP Controller: supported notifications by target:") - for event_id in UInt8( - AVRCP_NOTIFICATION_EVENT_FIRST_INDEX.rawValue).. 0 else { break } - let avrcp_subevent_value = UnsafeBufferPointer( - start: avrcp_subevent_now_playing_title_info_get_value(packet), - count: Int(count)) - log("AVRCP Controller: Title \(cString: avrcp_subevent_value)") - - case UInt8(AVRCP_SUBEVENT_NOW_PLAYING_ARTIST_INFO): - let count = avrcp_subevent_now_playing_artist_info_get_value_len(packet) - guard count > 0 else { break } - let avrcp_subevent_value = UnsafeBufferPointer( - start: avrcp_subevent_now_playing_artist_info_get_value(packet), - count: Int(count)) - log("AVRCP Controller: Artist \(cString: avrcp_subevent_value)") - - case UInt8(AVRCP_SUBEVENT_NOW_PLAYING_ALBUM_INFO): - let count = avrcp_subevent_now_playing_album_info_get_value_len(packet) - guard count > 0 else { break } - let avrcp_subevent_value = UnsafeBufferPointer( - start: avrcp_subevent_now_playing_album_info_get_value(packet), - count: Int(count)) - log("AVRCP Controller: Album \(cString: avrcp_subevent_value)") - - case UInt8(AVRCP_SUBEVENT_NOW_PLAYING_GENRE_INFO): - let count = avrcp_subevent_now_playing_genre_info_get_value_len(packet) - guard count > 0 else { break } - let avrcp_subevent_value = UnsafeBufferPointer( - start: avrcp_subevent_now_playing_genre_info_get_value(packet), - count: Int(count)) - log("AVRCP Controller: Genre \(cString: avrcp_subevent_value)") - - case UInt8(AVRCP_SUBEVENT_PLAY_STATUS): - let songLength = avrcp_subevent_play_status_get_song_length(packet) - let songPosition = avrcp_subevent_play_status_get_song_position(packet) - let playStatus = avrcp_play_status2str( - avrcp_subevent_play_status_get_play_status(packet)) - log( - "AVRCP Controller: Song length \(songLength) ms, Song position \(songPosition) ms, Play status \(cString: playStatus)" - ) - - case UInt8(AVRCP_SUBEVENT_OPERATION_COMPLETE): - let operationId = avrcp_operation2str( - avrcp_subevent_operation_complete_get_operation_id(packet)) - log("AVRCP Controller: \(cString: operationId) complete") - - case UInt8(AVRCP_SUBEVENT_OPERATION_START): - let operationId = avrcp_operation2str( - avrcp_subevent_operation_start_get_operation_id(packet)) - log("AVRCP Controller: \(cString: operationId) start") - - case UInt8(AVRCP_SUBEVENT_NOTIFICATION_EVENT_TRACK_REACHED_END): - log("AVRCP Controller: Track reached end") - - case UInt8(AVRCP_SUBEVENT_PLAYER_APPLICATION_VALUE_RESPONSE): - let commandType = avrcp_ctype2str( - avrcp_subevent_player_application_value_response_get_command_type(packet)) - log("AVRCP Controller: Set Player App Value \(cString: commandType)") - - default: - break - } -} - -@_cdecl("avrcp_target_packet_handler") -func avrcp_target_packet_handler( - packet_type: UInt8, - channel: UInt16, - packet: UnsafeMutablePointer?, - size: UInt16 -) { - guard packet_type == HCI_EVENT_PACKET else { return } - guard hci_event_packet_get_type(packet) == HCI_EVENT_AVRCP_META else { - return - } - - let subevent = packet?[2] - switch subevent { - case UInt8(AVRCP_SUBEVENT_NOTIFICATION_VOLUME_CHANGED): - let volume = avrcp_subevent_notification_volume_changed_get_absolute_volume( - packet) - log("AVRCP Target : Volume set to [\(volume) / 127]") - Application.shared.audioEngine.set(volume: volume << 1) - - case UInt8(AVRCP_SUBEVENT_OPERATION): - let operation_id = avrcp_operation_id_t( - avrcp_subevent_operation_get_operation_id(packet)) - let button_state: StaticString = - avrcp_subevent_operation_get_button_pressed(packet) > 0 - ? "PRESS" : "RELEASE" - switch operation_id { - case AVRCP_OPERATION_ID_VOLUME_UP: - log("AVRCP Target : VOLUME UP (\(button_state))") - case AVRCP_OPERATION_ID_VOLUME_DOWN: - log("AVRCP Target : VOLUME DOWN (\(button_state))") - default: - return - } - - default: - log("AVRCP Target : Event \(hex: subevent ?? 0xff) is not parsed") - } -} diff --git a/harmony/Sources/Bluetooth/HCI.swift b/harmony/Sources/Bluetooth/HCI.swift deleted file mode 100644 index e025e281..00000000 --- a/harmony/Sources/Bluetooth/HCI.swift +++ /dev/null @@ -1,30 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// Host Controller Interface - -@_cdecl("hci_packet_handler") -func hci_packet_handler( - packet_type: UInt8, - channel: UInt16, - packet: UnsafeMutablePointer?, - size: UInt16 -) { - guard packet_type == HCI_EVENT_PACKET else { return } - guard hci_event_packet_get_type(packet) == HCI_EVENT_PIN_CODE_REQUEST else { - return - } - - var address: bd_addr_t = (0, 0, 0, 0, 0, 0) - log("Pin code request - using '0000'") - hci_event_pin_code_request_get_bd_addr(packet, &address) - gap_pin_code_response(&address, "0000") -} diff --git a/harmony/Sources/Bluetooth/SBC.swift b/harmony/Sources/Bluetooth/SBC.swift deleted file mode 100644 index 2b9a3093..00000000 --- a/harmony/Sources/Bluetooth/SBC.swift +++ /dev/null @@ -1,61 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -enum SBCDecoder { - typealias Callback = ( - _ data: UnsafeMutableBufferPointer, - _ num_channels: Int32, - _ sample_rate: Int32 - ) -> Void - - static var context = btstack_sbc_decoder_bluedroid_t() - static var instance: UnsafePointer? = nil - static var callback: Callback? = nil - - static func configure(mode: btstack_sbc_mode_t) { - self.instance = btstack_sbc_decoder_bluedroid_init_instance(&context) - - func decode_callback( - _ data: UnsafeMutablePointer?, - _ num_samples: Int32, - _ num_channels: Int32, - _ sample_rate: Int32, - _ context: UnsafeMutableRawPointer? - ) { - let data = UnsafeMutableBufferPointer( - start: data, count: Int(num_samples)) - Self.callback?(data, num_channels, sample_rate) - } - - instance?.pointee.configure(&context, mode, decode_callback, nil) - } - - static func decode_signed_16( - mode: btstack_sbc_mode_t, - packet_status_flag: UInt8, - buffer: UnsafeRawBufferPointer, - callback: Callback - ) { - guard let instance = Self.instance else { - preconditionFailure("Must call configure prior to decode_signed_16") - } - - return withoutActuallyEscaping(callback) { - Self.callback = $0 - instance.pointee.decode_signed_16( - &Self.context, - packet_status_flag, - buffer.baseAddress, - UInt16(buffer.count)) - Self.callback = nil - } - } -} diff --git a/harmony/Sources/Bluetooth/SDP.swift b/harmony/Sources/Bluetooth/SDP.swift deleted file mode 100644 index d7d37fac..00000000 --- a/harmony/Sources/Bluetooth/SDP.swift +++ /dev/null @@ -1,50 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// Service Discovery Protocol - -struct ServiceDiscoveryProtocol: ~Copyable { - typealias ServiceRecord = UnsafePointer - typealias ServiceRecordHandle = UInt32 - - init() { - sdp_init() - } - - deinit { - sdp_deinit() - } - - mutating func registerService(record: ServiceRecord) { - precondition(sdp_register_service(record) == 0) - } - - mutating func registerService(record: UnsafeMutableRawBufferPointer) { - precondition(de_get_len(record.baseAddress) <= record.count) - precondition(sdp_register_service(record.baseAddress) == 0) - } - - mutating func unregisterService(handle: ServiceRecordHandle) { - sdp_unregister_service(handle) - } - - mutating func getServiceRecordHandle(for record: ServiceRecord) -> ServiceRecordHandle { - sdp_get_service_record_handle(record) - } - - mutating func makeServiceRecordHandle() -> ServiceRecordHandle { - sdp_create_service_record_handle() - } - - mutating func getServiceRecord(for handle: ServiceRecordHandle) -> ServiceRecord? { - ServiceRecord(sdp_get_record_for_handle(handle)) - } -} diff --git a/harmony/Sources/PIOPrograms/I2S.pio b/harmony/Sources/PIOPrograms/I2S.pio deleted file mode 100644 index 7b9ab6ec..00000000 --- a/harmony/Sources/PIOPrograms/I2S.pio +++ /dev/null @@ -1,64 +0,0 @@ -; -; Copyright (c) 2020 Raspberry Pi (Trading) Ltd. -; -; SPDX-License-Identifier: BSD-3-Clause -; - -; Transmit a mono or stereo I2S audio stream as stereo -; This is 16 bits per sample; can be altered by modifying the "set" params, -; or made programmable by replacing "set x" with "mov x, y" and using Y as a config register. -; -; Autopull must be enabled, with threshold set to 32. -; Since I2S is MSB-first, shift direction should be to left. -; Hence the format of the FIFO word is: -; -; | 31 : 16 | 15 : 0 | -; | sample ws=0 | sample ws=1 | -; -; Data is output at 1 bit per clock. Use clock divider to adjust frequency. -; Fractional divider will probably be needed to get correct bit clock period, -; but for common syslck freqs this should still give a constant word select period. -; -; One output pin is used for the data output. -; Two side-set pins are used. Bit 0 is clock, bit 1 is word select. - -; Send 16 bit words to the PIO for mono, 32 bit words for stereo - -.program audio_i2s -.side_set 2 - - ; /--- LRCLK - ; |/-- BCLK -bitloop1: ; || - out pins, 1 side 0b10 - jmp x-- bitloop1 side 0b11 - out pins, 1 side 0b00 - set x, 14 side 0b01 - -bitloop0: - out pins, 1 side 0b00 - jmp x-- bitloop0 side 0b01 - out pins, 1 side 0b10 -public entry_point: - set x, 14 side 0b11 - -% c-sdk { - -static inline void audio_i2s_program_init(PIO pio, uint sm, uint offset, uint data_pin, uint clock_pin_base) { - pio_sm_config sm_config = audio_i2s_program_get_default_config(offset); - - sm_config_set_out_pins(&sm_config, data_pin, 1); - sm_config_set_sideset_pins(&sm_config, clock_pin_base); - sm_config_set_out_shift(&sm_config, false, true, 32); - sm_config_set_fifo_join(&sm_config, PIO_FIFO_JOIN_TX); - - pio_sm_init(pio, sm, offset, &sm_config); - - uint pin_mask = (1u << data_pin) | (3u << clock_pin_base); - pio_sm_set_pindirs_with_mask(pio, sm, pin_mask, pin_mask); - pio_sm_set_pins(pio, sm, 0); // clear pins - - pio_sm_exec(pio, sm, pio_encode_jmp(offset + audio_i2s_offset_entry_point)); -} - -%} diff --git a/harmony/Sources/PIOPrograms/QuadratureEncoder.pio b/harmony/Sources/PIOPrograms/QuadratureEncoder.pio deleted file mode 100644 index 37ed3948..00000000 --- a/harmony/Sources/PIOPrograms/QuadratureEncoder.pio +++ /dev/null @@ -1,148 +0,0 @@ - -// FROM: https://github.com/raspberrypi/pico-examples/blob/master/pio/quadrature_encoder/quadrature_encoder.pio - -; -; Copyright (c) 2023 Raspberry Pi (Trading) Ltd. -; -; SPDX-License-Identifier: BSD-3-Clause -; -.pio_version 0 // only requires PIO version 0 - -.program quadrature_encoder - -; the code must be loaded at address 0, because it uses computed jumps -.origin 0 - - -; the code works by running a loop that continuously shifts the 2 phase pins into -; ISR and looks at the lower 4 bits to do a computed jump to an instruction that -; does the proper "do nothing" | "increment" | "decrement" action for that pin -; state change (or no change) - -; ISR holds the last state of the 2 pins during most of the code. The Y register -; keeps the current encoder count and is incremented / decremented according to -; the steps sampled - -; the program keeps trying to write the current count to the RX FIFO without -; blocking. To read the current count, the user code must drain the FIFO first -; and wait for a fresh sample (takes ~4 SM cycles on average). The worst case -; sampling loop takes 10 cycles, so this program is able to read step rates up -; to sysclk / 10 (e.g., sysclk 125MHz, max step rate = 12.5 Msteps/sec) - -; 00 state - JMP update ; read 00 - JMP decrement ; read 01 - JMP increment ; read 10 - JMP update ; read 11 - -; 01 state - JMP increment ; read 00 - JMP update ; read 01 - JMP update ; read 10 - JMP decrement ; read 11 - -; 10 state - JMP decrement ; read 00 - JMP update ; read 01 - JMP update ; read 10 - JMP increment ; read 11 - -; to reduce code size, the last 2 states are implemented in place and become the -; target for the other jumps - -; 11 state - JMP update ; read 00 - JMP increment ; read 01 -decrement: - ; note: the target of this instruction must be the next address, so that - ; the effect of the instruction does not depend on the value of Y. The - ; same is true for the "JMP X--" below. Basically "JMP Y--, " - ; is just a pure "decrement Y" instruction, with no other side effects - JMP Y--, update ; read 10 - - ; this is where the main loop starts -.wrap_target -update: - MOV ISR, Y ; read 11 - PUSH noblock - -sample_pins: - ; we shift into ISR the last state of the 2 input pins (now in OSR) and - ; the new state of the 2 pins, thus producing the 4 bit target for the - ; computed jump into the correct action for this state. Both the PUSH - ; above and the OUT below zero out the other bits in ISR - OUT ISR, 2 - IN PINS, 2 - - ; save the state in the OSR, so that we can use ISR for other purposes - MOV OSR, ISR - ; jump to the correct state machine action - MOV PC, ISR - - ; the PIO does not have a increment instruction, so to do that we do a - ; negate, decrement, negate sequence -increment: - MOV Y, ~Y - JMP Y--, increment_cont -increment_cont: - MOV Y, ~Y -.wrap ; the .wrap here avoids one jump instruction and saves a cycle too - - - -% c-sdk { - -#include "hardware/clocks.h" -#include "hardware/gpio.h" - -// max_step_rate is used to lower the clock of the state machine to save power -// if the application doesn't require a very high sampling rate. Passing zero -// will set the clock to the maximum - -static inline void quadrature_encoder_program_init(PIO pio, uint sm, uint pin, int max_step_rate) -{ - pio_sm_set_consecutive_pindirs(pio, sm, pin, 2, false); - pio_gpio_init(pio, pin); - pio_gpio_init(pio, pin + 1); - - gpio_pull_up(pin); - gpio_pull_up(pin + 1); - - pio_sm_config c = quadrature_encoder_program_get_default_config(0); - - sm_config_set_in_pins(&c, pin); // for WAIT, IN - sm_config_set_jmp_pin(&c, pin); // for JMP - // shift to left, autopull disabled - sm_config_set_in_shift(&c, false, false, 32); - // don't join FIFO's - sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_NONE); - - // passing "0" as the sample frequency, - if (max_step_rate == 0) { - sm_config_set_clkdiv(&c, 1.0); - } else { - // one state machine loop takes at most 10 cycles - float div = (float)clock_get_hz(clk_sys) / (10 * max_step_rate); - sm_config_set_clkdiv(&c, div); - } - - pio_sm_init(pio, sm, 0, &c); - pio_sm_set_enabled(pio, sm, true); -} - -static inline int32_t quadrature_encoder_get_count(PIO pio, uint sm) -{ - uint ret; - int n; - - // if the FIFO has N entries, we fetch them to drain the FIFO, - // plus one entry which will be guaranteed to not be stale - n = pio_sm_get_rx_fifo_level(pio, sm) + 1; - while (n > 0) { - ret = pio_sm_get_blocking(pio, sm); - n--; - } - return ret; -} - -%} \ No newline at end of file diff --git a/harmony/Sources/PIOPrograms/WS2812.pio b/harmony/Sources/PIOPrograms/WS2812.pio deleted file mode 100644 index 839ce5f2..00000000 --- a/harmony/Sources/PIOPrograms/WS2812.pio +++ /dev/null @@ -1,49 +0,0 @@ -; -; Copyright (c) 2020 Raspberry Pi (Trading) Ltd. -; -; SPDX-License-Identifier: BSD-3-Clause -; -.pio_version 0 // only requires PIO version 0 - -.program ws2812 -.side_set 1 - -; The following constants are selected for broad compatibility with WS2812, -; WS2812B, and SK6812 LEDs. Other constants may support higher bandwidths for -; specific LEDs, such as (7,10,8) for WS2812B LEDs. - -.define public T1 3 -.define public T2 3 -.define public T3 4 - -.wrap_target -bitloop: - out x, 1 side 0 [T3 - 1] ; Side-set still takes place when instruction stalls - jmp !x do_zero side 1 [T1 - 1] ; Branch on the bit we shifted out. Positive pulse -do_one: - jmp bitloop side 1 [T2 - 1] ; Continue driving high, for a long pulse -do_zero: - nop side 0 [T2 - 1] ; Or drive low, for a short pulse -.wrap - -% c-sdk { -#include "hardware/clocks.h" - -static inline void ws2812_program_init(PIO pio, uint sm, uint offset, uint pin, float freq, bool rgbw) { - - pio_gpio_init(pio, pin); - pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true); - - pio_sm_config c = ws2812_program_get_default_config(offset); - sm_config_set_sideset_pins(&c, pin); - sm_config_set_out_shift(&c, false, true, rgbw ? 32 : 24); - sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX); - - int cycles_per_bit = ws2812_T1 + ws2812_T2 + ws2812_T3; - float div = clock_get_hz(clk_sys) / (freq * cycles_per_bit); - sm_config_set_clkdiv(&c, div); - - pio_sm_init(pio, sm, offset, &c); - pio_sm_set_enabled(pio, sm, true); -} -%} diff --git a/harmony/Tests/AudioTests/RingBufferTests.swift b/harmony/Tests/AudioTests/RingBufferTests.swift deleted file mode 100644 index 70e119e9..00000000 --- a/harmony/Tests/AudioTests/RingBufferTests.swift +++ /dev/null @@ -1,177 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import XCTest - -@testable import Core - -extension RingBuffer { - mutating func write(contentsOf array: [Element]) -> Bool { - array.withUnsafeBufferPointer { - self.write(contentsOf: $0) - } - } - - mutating func read(into array: inout [Element], count: Int? = nil) -> Int { - array.withUnsafeMutableBufferPointer { buffer in - self.read(into: buffer, count: count) - } - } - - func assertState( - count: Int, - readerIndex: Int, - writerIndex: Int, - file: StaticString = #filePath, - line: UInt = #line - ) { - XCTAssertEqual( - self.availableCapacity, self.capacity - count, - "incorrect availableCapacity", file: file, line: line) - XCTAssertEqual( - self.isEmpty, (count == 0), "incorrect isEmpty", file: file, line: line) - XCTAssertEqual( - self.isFull, (count == self.capacity), "incorrect isFull", file: file, - line: line) - XCTAssertEqual(self.count, count, "incorrect count", file: file, line: line) - XCTAssertEqual( - self.readerIndex, readerIndex, "incorrect readerIndex", file: file, - line: line) - XCTAssertEqual( - self.writerIndex, writerIndex, "incorrect writerIndex", file: file, - line: line) - if self.isEmpty || self.isFull { - XCTAssertEqual(self.readerIndex, self.writerIndex, file: file, line: line) - } - } -} - -final class RingBufferTests: XCTestCase { - func testInitialization() { - let ringBuffer = RingBuffer(capacity: 10) - XCTAssertEqual(ringBuffer.capacity, 10) - ringBuffer.assertState(count: 0, readerIndex: 0, writerIndex: 0) - } - - func testCapacityAndAvailableCapacity() { - var ringBuffer = RingBuffer(capacity: 5) - ringBuffer.assertState(count: 0, readerIndex: 0, writerIndex: 0) - - XCTAssertTrue(ringBuffer.write(contentsOf: [1, 2, 3])) - ringBuffer.assertState(count: 3, readerIndex: 0, writerIndex: 3) - - XCTAssertTrue(ringBuffer.write(contentsOf: [4, 5])) - ringBuffer.assertState(count: 5, readerIndex: 0, writerIndex: 0) - } - - func testWriteAndRead() { - var ringBuffer = RingBuffer(capacity: 5) - - // Write data to the buffer - XCTAssertTrue(ringBuffer.write(contentsOf: [1, 2, 3])) - ringBuffer.assertState(count: 3, readerIndex: 0, writerIndex: 3) - - // Attempt to read from the buffer - var readBuffer = Array(repeating: 0, count: 3) - let readCount = ringBuffer.read(into: &readBuffer) - XCTAssertEqual(readCount, 3) - XCTAssertEqual(readBuffer, [1, 2, 3]) - ringBuffer.assertState(count: 0, readerIndex: 3, writerIndex: 3) - } - - func testOverwriteBehavior() { - var ringBuffer = RingBuffer(capacity: 3) - - // Fill buffer to capacity - XCTAssertTrue(ringBuffer.write(contentsOf: [1, 2, 3])) - ringBuffer.assertState(count: 3, readerIndex: 0, writerIndex: 0) - - // Attempt to overwrite when full - XCTAssertFalse(ringBuffer.write(contentsOf: [4])) - ringBuffer.assertState(count: 3, readerIndex: 0, writerIndex: 0) - - // Read and check if the buffer remains unaltered - var readBuffer = Array(repeating: 0, count: 3) - let readCount = ringBuffer.read(into: &readBuffer) - XCTAssertEqual(readCount, 3) - XCTAssertEqual(readBuffer, [1, 2, 3]) - ringBuffer.assertState(count: 0, readerIndex: 0, writerIndex: 0) - } - - func testClearBuffer() { - var ringBuffer = RingBuffer(capacity: 5) - XCTAssertTrue(ringBuffer.write(contentsOf: [1, 2, 3])) - ringBuffer.assertState(count: 3, readerIndex: 0, writerIndex: 3) - - ringBuffer.clear() - ringBuffer.assertState(count: 0, readerIndex: 0, writerIndex: 0) - } - - func testWrappingBehavior() { - var ringBuffer = RingBuffer(capacity: 5) - - // Step 1: Write some data to fill part of the buffer - XCTAssertTrue(ringBuffer.write(contentsOf: [1, 2, 3])) - ringBuffer.assertState(count: 3, readerIndex: 0, writerIndex: 3) - - // Step 2: Read some data, advancing the reader index - var readBuffer = Array(repeating: 0, count: 2) - let readCount = ringBuffer.read(into: &readBuffer) - XCTAssertEqual(readCount, 2) - XCTAssertEqual(readBuffer, [1, 2]) - ringBuffer.assertState(count: 1, readerIndex: 2, writerIndex: 3) - - // Step 3: Write more data, causing the writer index to wrap around - XCTAssertTrue(ringBuffer.write(contentsOf: [4, 5, 6])) - ringBuffer.assertState(count: 4, readerIndex: 2, writerIndex: 1) - - // Step 4: Read remaining data to verify the wrap-around behavior - readBuffer = Array(repeating: 0, count: 4) - let totalReadCount = ringBuffer.read(into: &readBuffer) - XCTAssertEqual(totalReadCount, 4) - XCTAssertEqual(readBuffer, [3, 4, 5, 6]) - ringBuffer.assertState(count: 0, readerIndex: 1, writerIndex: 1) - } - - func testWrappingWriteOverflowAndWrappingReadUnderflow() { - var ringBuffer = RingBuffer(capacity: 5) - - // Step 1: Fill the buffer almost to capacity - XCTAssertTrue(ringBuffer.write(contentsOf: [1, 2, 3])) - ringBuffer.assertState(count: 3, readerIndex: 0, writerIndex: 3) - - // Step 2: Read some data to advance the reader index - var readBuffer = Array(repeating: 0, count: 2) - let readCount = ringBuffer.read(into: &readBuffer) - XCTAssertEqual(readCount, 2) - XCTAssertEqual(readBuffer, [1, 2]) - ringBuffer.assertState(count: 1, readerIndex: 2, writerIndex: 3) - - // Step 3: Write more data to cause the writer index to wrap around - XCTAssertTrue(ringBuffer.write(contentsOf: [4, 5, 6])) - // Writer wraps around - ringBuffer.assertState(count: 4, readerIndex: 2, writerIndex: 1) - - // Step 4: Attempt a write that overflows (fails due to lack of capacity) - XCTAssertFalse(ringBuffer.write(contentsOf: [7, 8, 9])) - // State remains unchanged - ringBuffer.assertState(count: 4, readerIndex: 2, writerIndex: 1) - - // Step 5: Read more data than available to test wrapping underflow - readBuffer = Array(repeating: 0, count: 5) - let underflowReadCount = ringBuffer.read(into: &readBuffer) - XCTAssertEqual(underflowReadCount, 4) // Should only read 4 elements - // Validate read data - XCTAssertEqual(readBuffer.prefix(underflowReadCount), [3, 4, 5, 6]) - // Reader wraps around - ringBuffer.assertState(count: 0, readerIndex: 1, writerIndex: 1) - } -} diff --git a/harmony/assets/hero.jpg b/harmony/assets/hero.jpg deleted file mode 100644 index 460065f2..00000000 Binary files a/harmony/assets/hero.jpg and /dev/null differ diff --git a/harmony/include/btstack_config.h b/harmony/include/btstack_config.h deleted file mode 100644 index 1b969e1b..00000000 --- a/harmony/include/btstack_config.h +++ /dev/null @@ -1,89 +0,0 @@ -#ifndef _PICO_BTSTACK_BTSTACK_CONFIG_H -#define _PICO_BTSTACK_BTSTACK_CONFIG_H - -// BTstack features that can be enabled -#define ENABLE_LOG_INFO -#define ENABLE_LOG_ERROR -#define ENABLE_PRINTF_HEXDUMP -#define ENABLE_SCO_OVER_HCI - -#ifdef ENABLE_BLE -#define ENABLE_GATT_CLIENT_PAIRING -#define ENABLE_L2CAP_LE_CREDIT_BASED_FLOW_CONTROL_MODE -#define ENABLE_LE_CENTRAL -#define ENABLE_LE_DATA_LENGTH_EXTENSION -#define ENABLE_LE_PERIPHERAL -#define ENABLE_LE_PRIVACY_ADDRESS_RESOLUTION -#define ENABLE_LE_SECURE_CONNECTIONS -#endif - -#ifdef ENABLE_CLASSIC -#define ENABLE_L2CAP_ENHANCED_RETRANSMISSION_MODE -#define ENABLE_GOEP_L2CAP -#endif - -#if defined (ENABLE_CLASSIC) && defined(ENABLE_BLE) -#define ENABLE_CROSS_TRANSPORT_KEY_DERIVATION -#endif - -// BTstack configuration. buffers, sizes, ... -#define HCI_OUTGOING_PRE_BUFFER_SIZE 4 -#define HCI_ACL_PAYLOAD_SIZE (1691 + 4) -#define HCI_ACL_CHUNK_SIZE_ALIGNMENT 4 -#define MAX_NR_AVDTP_CONNECTIONS 1 -#define MAX_NR_AVDTP_STREAM_ENDPOINTS 1 -#define MAX_NR_AVRCP_CONNECTIONS 2 -#define MAX_NR_BNEP_CHANNELS 1 -#define MAX_NR_BNEP_SERVICES 1 -#define MAX_NR_BTSTACK_LINK_KEY_DB_MEMORY_ENTRIES 2 -#define MAX_NR_GATT_CLIENTS 1 -#define MAX_NR_HCI_CONNECTIONS 2 -#define MAX_NR_HID_HOST_CONNECTIONS 1 -#define MAX_NR_HIDS_CLIENTS 1 -#define MAX_NR_HFP_CONNECTIONS 1 -#define MAX_NR_L2CAP_CHANNELS 4 -#define MAX_NR_L2CAP_SERVICES 3 -#define MAX_NR_RFCOMM_CHANNELS 1 -#define MAX_NR_RFCOMM_MULTIPLEXERS 1 -#define MAX_NR_RFCOMM_SERVICES 1 -#define MAX_NR_SERVICE_RECORD_ITEMS 4 -#define MAX_NR_SM_LOOKUP_ENTRIES 3 -#define MAX_NR_WHITELIST_ENTRIES 16 -#define MAX_NR_LE_DEVICE_DB_ENTRIES 16 - -// Limit number of ACL/SCO Buffer to use by stack to avoid cyw43 shared bus overrun -#define MAX_NR_CONTROLLER_ACL_BUFFERS 3 -#define MAX_NR_CONTROLLER_SCO_PACKETS 3 - -// Enable and configure HCI Controller to Host Flow Control to avoid cyw43 shared bus overrun -#define ENABLE_HCI_CONTROLLER_TO_HOST_FLOW_CONTROL -#define HCI_HOST_ACL_PACKET_LEN 1024 -#define HCI_HOST_ACL_PACKET_NUM 3 -#define HCI_HOST_SCO_PACKET_LEN 120 -#define HCI_HOST_SCO_PACKET_NUM 3 - -// Link Key DB and LE Device DB using TLV on top of Flash Sector interface -#define NVM_NUM_DEVICE_DB_ENTRIES 16 -#define NVM_NUM_LINK_KEYS 16 - -// We don't give btstack a malloc, so use a fixed-size ATT DB. -#define MAX_ATT_DB_SIZE 512 - -// BTstack HAL configuration -#define HAVE_EMBEDDED_TIME_MS - -// map btstack_assert onto Pico SDK assert() -#define HAVE_ASSERT - -// Some USB dongles take longer to respond to HCI reset (e.g. BCM20702A). -#define HCI_RESET_RESEND_TIMEOUT_MS 1000 - -#define ENABLE_SOFTWARE_AES128 -#define ENABLE_MICRO_ECC_FOR_LE_SECURE_CONNECTIONS - -#define HAVE_BTSTACK_STDIN - -// To get the audio demos working even with HCI dump at 115200, this truncates long ACL packets -//#define HCI_DUMP_STDOUT_MAX_SIZE_ACL 100 - -#endif // _PICO_BTSTACK_BTSTACK_CONFIG_H diff --git a/harmony/include/lwipopts.h b/harmony/include/lwipopts.h deleted file mode 100644 index fefe1e4b..00000000 --- a/harmony/include/lwipopts.h +++ /dev/null @@ -1,24 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift.org open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// See https://swift.org/CONTRIBUTORS.txt for the list of Swift project authors -// -//===----------------------------------------------------------------------===// - -#ifndef _LWIPOPTS_H -#define _LWIPOPTS_H - -#define NO_SYS 1 -#define LWIP_SOCKET 0 -#define LWIP_NETCONN 0 - -// Watch out: Without this, lwip fails to initialize and crashes inside -// memp_init_pool due to misaligned memory access (the fallback is "1"). -#define MEM_ALIGNMENT 4 - -#endif diff --git a/nrfx-blink-sdk/BridgingHeader.h b/nrfx-blink-sdk/BridgingHeader.h deleted file mode 100644 index 8a4377ab..00000000 --- a/nrfx-blink-sdk/BridgingHeader.h +++ /dev/null @@ -1,18 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include - -#include -#include - -#define LED0_NODE DT_ALIAS(led0) -static struct gpio_dt_spec led0 = GPIO_DT_SPEC_GET(LED0_NODE, gpios); diff --git a/nrfx-blink-sdk/CMakeLists.txt b/nrfx-blink-sdk/CMakeLists.txt deleted file mode 100644 index 24ba2fcc..00000000 --- a/nrfx-blink-sdk/CMakeLists.txt +++ /dev/null @@ -1,73 +0,0 @@ -cmake_minimum_required(VERSION 3.29) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) - -# Use the armv7em-none-none-eabi target triple for Swift -set(CMAKE_Swift_COMPILER_TARGET armv7em-none-none-eabi) -# Enable "wmo" as needed by Embedded Swift -set(CMAKE_Swift_COMPILATION_MODE wholemodule) -# FIXME: Skip checking if the compiler works -set(CMAKE_Swift_COMPILER_WORKS true) - -# Create a new project called "blinky" and enable "Swift" as a supported language -project(blinky Swift) - -# Set global Swift compiler flags -add_compile_options( - # Enable Embedded Swift - "$<$:SHELL:-enable-experimental-feature Embedded>" - - # Enable function sections to enable dead code stripping on elf - "$<$:SHELL:-Xfrontend -function-sections>" - - # Use software floating point operations matching GCC - "$<$:SHELL:-Xcc -mfloat-abi=soft>" - - # Use compacted C enums matching GCC - "$<$:SHELL:-Xcc -fshort-enums>" - - # Disable PIC - "$<$:SHELL:-Xcc -fno-pic>" - - # Add Libc include paths - "$<$:SHELL:-Xcc -I -Xcc ${ZEPHYR_SDK_INSTALL_DIR}/arm-zephyr-eabi/picolibc/include>" -) - -# Add definitions from Zephyr to -Xcc flags -get_target_property(ZEPHYR_DEFINES zephyr_interface INTERFACE_COMPILE_DEFINITIONS) -if(ZEPHYR_DEFINES) - foreach(flag ${ZEPHYR_DEFINES}) - # Ignore expressions like "$" - string(FIND "${flag}" "$<" start_of_expression) - if(NOT start_of_expression EQUAL -1) - continue() - endif() - - add_compile_options("$<$:SHELL:-Xcc -D${flag}>") - endforeach() -endif() - -target_sources(app PRIVATE Stubs.c) - -# The Swift code providing "main" needs to be in an OBJECT library (instead of STATIC library) to make sure it actually gets linker. -# A STATIC library would get dropped from linking because Zephyr provides a default weak empty main definition. -add_library(app_swift OBJECT Main.swift) - -add_dependencies(app_swift syscall_list_h_target) -target_compile_options(app_swift PRIVATE - -parse-as-library - - -Osize - - -Xfrontend -disable-stack-protector - - # FIXME: add dependency on BridgingHeader.h - -import-bridging-header ${CMAKE_CURRENT_LIST_DIR}/BridgingHeader.h -) - -# Copy include paths from C target to Swift target -target_include_directories(app_swift PRIVATE - "$" -) - -# Link the Swift target into the primary target -target_link_libraries(app PRIVATE app_swift) diff --git a/nrfx-blink-sdk/Main.swift b/nrfx-blink-sdk/Main.swift deleted file mode 100644 index 84c5ffec..00000000 --- a/nrfx-blink-sdk/Main.swift +++ /dev/null @@ -1,24 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -@main -struct Main { - static func main() { - // Note: & in Swift is not the "address of" operator, but on a global variable declared in C - // it will give the correct address of the global. - gpio_pin_configure_dt( - &led0, GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOGICAL) - while true { - gpio_pin_toggle_dt(&led0) - k_msleep(100) - } - } -} diff --git a/nrfx-blink-sdk/README.md b/nrfx-blink-sdk/README.md deleted file mode 100644 index 8a8de074..00000000 --- a/nrfx-blink-sdk/README.md +++ /dev/null @@ -1,42 +0,0 @@ -# nrfx-blink-sdk - -This example demonstrates how to integrate with the Zephyr SDK via CMake and how to build a Swift firmware application on top of the SDK and the libraries from it. The example was tested on a nRF52840-DK board, but it should also work on other Zephyr-supported boards. - - - -## Requirements - -- Download and install [Zephyr](https://docs.zephyrproject.org/latest/), and make sure you are set up for development with it, e.g. by following the [Zephyr Getting Started Guide](https://docs.zephyrproject.org/latest/develop/getting_started/index.html). In particular, you will need: - - CMake, Ninja, and other build tools. - - The West build system. - - A Python virtualenv for Zephyr. - - Zephyr SDK/toolchain. - - Host flash/debug tools for the board you're using. For example, for the nRF52840-DK board you'll need the [nRF Util](https://www.nordicsemi.com/Products/Development-tools/nRF-Util). - -- Before trying to use Swift with the Zephyr SDK, make sure your environment works and can build the provided C/C++ sample projects, in particular: - - Try building and running the "simple/blink" example from Zephyr written in C. - -## Building - -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- Build the program in the Zephyr virtualenv, specify the target board type via the `-DBOARD=...` CMake setting: - -```console -$ cd nrfx-blink-sdk -$ source ~/zephyrproject/.venv/bin/activate -(.venv) cmake -B build -G Ninja -DBOARD=nrf52840dk/nrf52840 -DUSE_CCACHE=0 . -(.venv) cmake --build build -``` - -## Running - -- Connect the nRF52840-DK board over a USB cable to your Mac using the J-Link connector on the board. -- Use the `nrfutil device` command to upload the firmware and to run it: - -```console -(.venv) nrfutil device program --firmware build/zephyr/zephyr.hex -(.venv) nrfutil device fw-verify --firmware build/zephyr/zephyr.hex -(.venv) nrfutil device reset -``` - -- The green LED should now be blinking in a pattern. diff --git a/nrfx-blink-sdk/Stubs.c b/nrfx-blink-sdk/Stubs.c deleted file mode 100644 index 605bb39f..00000000 --- a/nrfx-blink-sdk/Stubs.c +++ /dev/null @@ -1,30 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include -#include - -void *aligned_alloc(size_t alignment, size_t size); - -// Embedded Swift currently requires posix_memalign, but the C libraries in the -// Zephyr SDK do not provide it. Let's implement it and forward the calls to -// aligned_alloc(3). -int -posix_memalign(void **memptr, size_t alignment, size_t size) -{ - void *p = aligned_alloc(alignment, size); - if (p) { - *memptr = p; - return 0; - } - - return errno; -} diff --git a/nrfx-blink-sdk/prj.conf b/nrfx-blink-sdk/prj.conf deleted file mode 100644 index 7a123333..00000000 --- a/nrfx-blink-sdk/prj.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_GPIO=y -CONFIG_NEWLIB_LIBC=y diff --git a/nrfx-blink-sdk/west.yml b/nrfx-blink-sdk/west.yml deleted file mode 100644 index ec668bea..00000000 --- a/nrfx-blink-sdk/west.yml +++ /dev/null @@ -1,13 +0,0 @@ -manifest: - remotes: - - name: zephyrproject-rtos - url-base: https://github.com/zephyrproject-rtos - - projects: - - name: zephyr - remote: zephyrproject-rtos - revision: v4.1.0 - import: - name-allowlist: - - cmsis # required by the ARM port - - hal_nordic # required by the custom_plank board (Nordic based) diff --git a/nuttx-riscv-blink/CMakeLists.txt b/nuttx-riscv-blink/CMakeLists.txt deleted file mode 100644 index da191f00..00000000 --- a/nuttx-riscv-blink/CMakeLists.txt +++ /dev/null @@ -1,134 +0,0 @@ -cmake_minimum_required(VERSION 3.14...3.30) - -project(blink - VERSION 1.0 - DESCRIPTION "Blink on NuttX" - LANGUAGES Swift -) - -if("${CMAKE_Swift_COMPILER_VERSION}" VERSION_LESS 6.1) - message(FATAL_ERROR "Swift 6.1 or later is required") -endif() - -if(POLICY CMP0169) - # allow to call FetchContent_Populate directly - cmake_policy(SET CMP0169 OLD) -endif() - -option(LIST_ALL_BOARDS "List all available boards" OFF) -option(ENABLE_NUTTX_TRACE "Enable NuttX trace" OFF) - -if(ENABLE_NUTTX_TRACE) - set(TRACEFLAG "--trace") -else() - set(TRACEFLAG "") -endif() - -set(FETCHCONTENT_QUIET FALSE) -include(FetchContent) -FetchContent_Declare( - apps - GIT_REPOSITORY https://github.com/apache/nuttx-apps.git - GIT_TAG nuttx-12.7.0 - SOURCE_DIR ${CMAKE_BINARY_DIR}/apps - FIND_PACKAGE_ARGS -) -FetchContent_GetProperties(apps) -if(NOT apps_POPULATED) - FetchContent_Populate(apps) -endif() - -FetchContent_Declare( - nuttx - GIT_REPOSITORY https://github.com/apache/nuttx.git - GIT_TAG nuttx-12.7.0 - SOURCE_DIR ${CMAKE_BINARY_DIR}/nuttx - FIND_PACKAGE_ARGS -) -FetchContent_GetProperties(nuttx) -if(NOT nuttx_POPULATED) - FetchContent_Populate(nuttx) -endif() - -if(CMAKE_HOST_SYSTEM_NAME STREQUAL "Windows") - set(SCRIPT_SUFFIX .bat) -else() - set(SCRIPT_SUFFIX .sh) -endif() - -if(LIST_ALL_BOARDS) - execute_process( - COMMAND ${CMAKE_COMMAND} -E chdir ${nuttx_SOURCE_DIR} - ${CMAKE_COMMAND} -E env PATH=${nuttx_SOURCE_DIR}/tools:$ENV{PATH} - ${nuttx_SOURCE_DIR}/tools/configure${SCRIPT_SUFFIX} -L - RESULT_VARIABLE result - ) - if(result) - message(FATAL_ERROR "Failed to run tools/configure") - endif() -else() - if(NOT DEFINED BOARD_CONFIG) - message(FATAL_ERROR "Please define configuration with BOARD_CONFIG") - else() - message(STATUS "BOARD_CONFIG: ${BOARD_CONFIG}") - endif() - - # Send swift-blinky example to nuttx-apps path - file(COPY ${CMAKE_SOURCE_DIR}/leds_swift DESTINATION ${apps_SOURCE_DIR}/examples) - file(COPY ${CMAKE_SOURCE_DIR}/defconfig DESTINATION ${nuttx_SOURCE_DIR}/boards/risc-v/qemu-rv/rv-virt/configs/leds_swift) - - add_custom_target(distclean - COMMAND ${CMAKE_COMMAND} -E chdir ${nuttx_SOURCE_DIR} - ${CMAKE_COMMAND} -E env PATH=${nuttx_SOURCE_DIR}/tools:$ENV{PATH} - make distclean - COMMENT "Clean NuttX" - ) - - execute_process( - COMMAND ${CMAKE_COMMAND} -E chdir ${nuttx_SOURCE_DIR} - ${CMAKE_COMMAND} -E env PATH=${nuttx_SOURCE_DIR}/tools:$ENV{PATH} - ${nuttx_SOURCE_DIR}/tools/configure${SCRIPT_SUFFIX} -l ${BOARD_CONFIG} - RESULT_VARIABLE result - ) - if(result) - message(FATAL_ERROR "Failed to run tools/configure") - endif() - - add_custom_target(copy_swift_example - COMMAND ${CMAKE_COMMAND} -E copy_directory ${CMAKE_SOURCE_DIR}/leds_swift ${apps_SOURCE_DIR}/examples/leds_swift - COMMENT "Copying leds_swift example to nuttx-apps" - ) - - add_custom_target(build_nuttx ALL - COMMAND ${CMAKE_COMMAND} -E chdir ${nuttx_SOURCE_DIR} - ${CMAKE_COMMAND} -E env PATH=${nuttx_SOURCE_DIR}/tools:$ENV{PATH} - make ${TRACEFLAG} -j ${JOB_POOLS} - DEPENDS copy_swift_example - COMMENT "Building NuttX" - ) - - add_custom_command( - TARGET build_nuttx - POST_BUILD - COMMAND ${CMAKE_COMMAND} -E copy ${nuttx_SOURCE_DIR}/nuttx ${CMAKE_BINARY_DIR}/nuttx.elf - ) - - add_custom_target(export_nuttx - COMMAND ${CMAKE_COMMAND} -E chdir ${nuttx_SOURCE_DIR} - ${CMAKE_COMMAND} -E env PATH=${nuttx_SOURCE_DIR}/tools:$ENV{PATH} - make export - COMMENT "Exporting NuttX" - ) - - add_custom_target(extract_nuttx_export - COMMAND ${CMAKE_COMMAND} -E tar xzf ${nuttx_SOURCE_DIR}/nuttx-export-12.7.0.tar.gz - WORKING_DIRECTORY ${CMAKE_BINARY_DIR} - COMMAND ${CMAKE_COMMAND} -E remove ${nuttx_SOURCE_DIR}/nuttx-export-12.7.0.tar.gz - DEPENDS export_nuttx - COMMENT "Extracting NuttX export" - ) - - add_custom_target(nuttx-libs - DEPENDS build_nuttx export_nuttx extract_nuttx_export - ) -endif() diff --git a/nuttx-riscv-blink/README.md b/nuttx-riscv-blink/README.md deleted file mode 100644 index 4a472393..00000000 --- a/nuttx-riscv-blink/README.md +++ /dev/null @@ -1,71 +0,0 @@ -# Swift 6 on NuttX RTOS using CMake - -## Description - -Run blink rv32-blink_leds (QEMU) example on NuttX RTOS. - -> [!NOTE] -> CMake is adapted to build NuttX and NuttX-apps (Makefiles) with Swift 6. - -## Requirements - -- [NuttX](https://github.com/apache/nuttx) & [NuttX-apps](https://github.com/apache/nuttx-apps) -- [kconfig-frontends](https://bitbucket.org/nuttx/tools) -- [CMake](https://cmake.org/download/) -- [QEMU](https://www.qemu.org/) -- [Swift 6](https://swift.org/download/) - Swift 6.1 or greater -- [RISC-V GNU Toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain/releases) - -## How to build - -```bash -# list all supported boards -cmake -B build -DLIST_ALL_BOARDS=ON | less -# build configuration -cmake -B build -GNinja -DBOARD_CONFIG=rv-virt:leds_swift -DENABLE_NUTTX_TRACE=[ON|OFF] -# build -cmake --build build -# clean -cmake --build build -t distclean -# export NuttX as library -cmake --build build -t nuttx-libs -``` - -- **Output** -```bash -qemu-system-riscv32 \ - -semihosting \ - -M virt,aclint=on \ - -cpu rv32 -smp 8 \ - -bios none \ - -kernel build/nuttx.elf -nographic -NuttShell (NSH) NuttX-12.7.0 -nsh> leds_swift -leds_main: led_daemon started - -led_daemon (pid# 4): Running -led_daemon: Opening /dev/userleds -led_daemon: Supported LEDs 0x7 -led_daemon: LED set 0x1 -board_userled: LED 1 set to 1 -board_userled: LED 2 set to 0 -board_userled: LED 3 set to 0 -nsh> led_daemon: LED set 0x0 -board_userled: LED 1 set to 0 -board_userled: LED 2 set to 0 -board_userled: LED 3 set to 0 -led_daemon: LED set 0x1 -board_userled: LED 1 set to 1 -board_userled: LED 2 set to 0 -board_userled: LED 3 set to 0 -led_daemon: LED set 0x0 -# [...] see output in QEMU -``` - -Quit from QEMU: `Ctrl-a x` - -## References - -- [Nuttx - Compiling with CMake](https://nuttx.apache.org/docs/latest/quickstart/compiling_cmake.html) -- [NuttX - C++ Example using CMake](https://nuttx.apache.org/docs/latest/guides/cpp_cmake.html) -- [NuttX - leds_rust](https://lupyuen.github.io/articles/rust6) diff --git a/nuttx-riscv-blink/defconfig b/nuttx-riscv-blink/defconfig deleted file mode 100644 index 5091081e..00000000 --- a/nuttx-riscv-blink/defconfig +++ /dev/null @@ -1,76 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLE_LOSMART is not set -CONFIG_16550_ADDRWIDTH=0 -CONFIG_16550_UART0=y -CONFIG_16550_UART0_BASE=0x10000000 -CONFIG_16550_UART0_CLOCK=3686400 -CONFIG_16550_UART0_IRQ=37 -CONFIG_16550_UART0_SERIAL_CONSOLE=y -CONFIG_16550_UART=y -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="rv-virt" -CONFIG_ARCH_BOARD_QEMU_RV_VIRT=y -CONFIG_ARCH_CHIP="qemu-rv" -# CONFIG_ARCH_CHIP_QEMU_RV64=y -CONFIG_ARCH_CHIP_QEMU_RV=y -CONFIG_ARCH_CHIP_QEMU_RV_ISA_A=y -CONFIG_ARCH_CHIP_QEMU_RV_ISA_C=y -CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BCH=y -CONFIG_BOARDCTL_POWEROFF=y -CONFIG_BOARD_LATE_INITIALIZE=y -CONFIG_BOARD_LOOPSPERMSEC=6366 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEVICE_TREE=y -CONFIG_DEV_ZERO=y -CONFIG_ELF=y -# CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_LEDS=y -CONFIG_EXAMPLES_LEDS_SWIFT=y -CONFIG_FS_HOSTFS=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_LIBC_ENVPATH=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LIBM=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PATH_INITIAL="/system/bin" -CONFIG_RAM_SIZE=33554432 -CONFIG_RAM_START=0x80000000 -CONFIG_READLINE_CMD_HISTORY=y -CONFIG_RISCV_SEMIHOSTING_HOSTFS=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_UART_ARCH_MMIO=y -CONFIG_STACK_COLORATION=y -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2021 -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NSH_STACKSIZE=3072 -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_USEC_PER_TICK=1000 -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/nuttx-riscv-blink/leds_swift/BridgingHeader.h b/nuttx-riscv-blink/leds_swift/BridgingHeader.h deleted file mode 100644 index 7b2ceba1..00000000 --- a/nuttx-riscv-blink/leds_swift/BridgingHeader.h +++ /dev/null @@ -1,124 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define LED_DEVPATH "/dev/userleds" - -const int LEDS_PRIORITY = CONFIG_EXAMPLES_LEDS_PRIORITY; -const int LEDS_STACKSIZE = CONFIG_EXAMPLES_LEDS_STACKSIZE; - -static bool g_led_daemon_started = false; - -static void sigterm_action(int signo, siginfo_t *siginfo, void *arg) { - if (signo == SIGTERM) { - printf("SIGTERM received\n"); - g_led_daemon_started = false; - printf("led_daemon: Terminated.\n"); - } else { - printf("\nsigterm_action: Received signo=%d siginfo=%p arg=%p\n", signo, - (void *)siginfo, arg); - } -} - -int led_daemon(int argc, char *argv[]) { - userled_set_t supported = 0; - userled_set_t ledset = 0; - bool incrementing = true; - - struct sigaction act = {.sa_sigaction = sigterm_action, - .sa_flags = SA_SIGINFO}; - - sigemptyset(&act.sa_mask); - sigaddset(&act.sa_mask, SIGTERM); - - if (sigaction(SIGTERM, &act, NULL) != 0) { - printf("Failed to install SIGTERM handler, errno=%d\n", errno); - return EXIT_FAILURE; - } - - pid_t mypid = getpid(); - g_led_daemon_started = true; - printf("\nled_daemon (pid# %d): Running\n", mypid); - - printf("led_daemon: Opening %s\n", CONFIG_EXAMPLES_LEDS_DEVPATH); - int fd = open(CONFIG_EXAMPLES_LEDS_DEVPATH, O_WRONLY); - if (fd < 0) { - printf("led_daemon: ERROR: Failed to open %s: %d\n", - CONFIG_EXAMPLES_LEDS_DEVPATH, errno); - g_led_daemon_started = false; - return EXIT_FAILURE; - } - - int ret = ioctl(fd, ULEDIOC_SUPPORTED, (unsigned long)&supported); - if (ret < 0) { - printf("led_daemon: ERROR: ioctl(ULEDIOC_SUPPORTED) failed: %d\n", errno); - close(fd); - g_led_daemon_started = false; - return EXIT_FAILURE; - } - - printf("led_daemon: Supported LEDs 0x%x\n", supported); - supported &= CONFIG_EXAMPLES_LEDS_LEDSET; - - while (g_led_daemon_started) { - userled_set_t newset = 0; - userled_set_t tmp = 0; - - if (incrementing) { - tmp = ledset; - while (newset == ledset) { - tmp++; - newset = tmp & supported; - } - - if (newset == 0) { - incrementing = false; - continue; - } - } else { - if (ledset == 0) { - incrementing = true; - continue; - } - - tmp = ledset; - while (newset == ledset) { - tmp--; - newset = tmp & supported; - } - } - - ledset = newset; - printf("led_daemon: LED set 0x%x\n", ledset); - - ret = ioctl(fd, ULEDIOC_SETALL, (unsigned long)ledset); - if (ret < 0) { - printf("led_daemon: ERROR: ioctl(ULEDIOC_SETALL) failed: %d\n", errno); - close(fd); - g_led_daemon_started = false; - return EXIT_FAILURE; - } - - usleep(500 * 1000); - } - - close(fd); - return EXIT_SUCCESS; -} \ No newline at end of file diff --git a/nuttx-riscv-blink/leds_swift/Kconfig b/nuttx-riscv-blink/leds_swift/Kconfig deleted file mode 100644 index e39ce088..00000000 --- a/nuttx-riscv-blink/leds_swift/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -config EXAMPLES_LEDS_SWIFT - tristate "\"LEDs Swift\" example" - default y - depends on USERLED - ---help--- - Enable the \"LEDs Swift\" example - -if EXAMPLES_LEDS_SWIFT - -config EXAMPLES_LEDS_SWIFT_PROGNAME - string "Program name" - default "leds_swift" - ---help--- - This is the name of the program that will be used when the NSH ELF - program is installed. - -config EXAMPLES_LEDS_SWIFT_PRIORITY - int "LEDs Swift task priority" - default 100 - -config EXAMPLES_LEDS_SWIFT_STACKSIZE - int "LEDs Swift stack size" - default DEFAULT_TASK_STACKSIZE - -endif diff --git a/nuttx-riscv-blink/leds_swift/Make.defs b/nuttx-riscv-blink/leds_swift/Make.defs deleted file mode 100644 index 9070565f..00000000 --- a/nuttx-riscv-blink/leds_swift/Make.defs +++ /dev/null @@ -1,24 +0,0 @@ -############################################################################ -# apps/examples/leds_swift/Make.defs -# -# Copyright (c) 2024 Apple Inc. and the Swift project authors. -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -ifneq ($(CONFIG_EXAMPLES_LEDS_SWIFT),) -CONFIGURED_APPS += $(APPDIR)/examples/leds_swift -endif diff --git a/nuttx-riscv-blink/leds_swift/Makefile b/nuttx-riscv-blink/leds_swift/Makefile deleted file mode 100644 index e2fc7df4..00000000 --- a/nuttx-riscv-blink/leds_swift/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################ -# apps/examples/leds_swift/Makefile -# -# Copyright (c) 2024 Apple Inc. and the Swift project authors. -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(APPDIR)/Make.defs - -# Blink in Swift Embedded Example - -MAINSRC = $(wildcard *.swift) $(wildcard *.h) - -# leds_swift built-in application info - -SWIFTFLAGS += -import-bridging-header BridgingHeader.h -I$(TOPDIR)/include -SWIFTFLAGS += -Xfrontend -function-sections -Xfrontend -disable-stack-protector -SWIFTFLAGS += -Xfrontend -enable-single-module-llvm-emission -PROGNAME = $(CONFIG_EXAMPLES_LEDS_SWIFT_PROGNAME) -PRIORITY = $(CONFIG_EXAMPLES_LEDS_SWIFT_PRIORITY) -STACKSIZE = $(CONFIG_EXAMPLES_LEDS_SWIFT_STACKSIZE) -MODULE = $(CONFIG_EXAMPLES_LEDS_SWIFT) - -include $(APPDIR)/Application.mk diff --git a/nuttx-riscv-blink/leds_swift/leds_swift.swift b/nuttx-riscv-blink/leds_swift/leds_swift.swift deleted file mode 100644 index 1cadcf47..00000000 --- a/nuttx-riscv-blink/leds_swift/leds_swift.swift +++ /dev/null @@ -1,30 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -@_cdecl("leds_swift_main") -public func cMain( - _ argc: Int32, _ argv: UnsafeMutablePointer?> -) -> Int32 { - let ret = task_create( - "led_daemon", - LEDS_PRIORITY, - LEDS_STACKSIZE, - led_daemon, - nil) - - if ret < 0 { - print("leds_main: ERROR: Failed to start led_daemon") - return ret - } - - print("leds_main: led_daemon started") - return 0 -} diff --git a/rpi-4b-blink/Makefile b/rpi-4b-blink/Makefile deleted file mode 100644 index 1ee6e512..00000000 --- a/rpi-4b-blink/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -##===----------------------------------------------------------------------===## -## -## This source file is part of the Swift open source project -## -## Copyright (c) 2025 Apple Inc. and the Swift project authors. -## Licensed under Apache License v2.0 with Runtime Library Exception -## -## See https://swift.org/LICENSE.txt for license information -## -##===----------------------------------------------------------------------===## - -# Paths -REPOROOT := $(shell git rev-parse --show-toplevel) -TOOLSROOT := $(REPOROOT)/Tools -TOOLSET := $(TOOLSROOT)/Toolsets/rpi-5-elf.json -LLVM_OBJCOPY := llvm-objcopy -SWIFT_BUILD := swift build - -# Flags -ARCH := aarch64 -TARGET := $(ARCH)-none-none-elf -SWIFT_BUILD_ARGS := \ - --configuration release \ - --triple $(TARGET) \ - --toolset $(TOOLSET) -BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) - -.PHONY: build -build: - @echo "building..." - $(SWIFT_BUILD) \ - $(SWIFT_BUILD_ARGS) \ - --verbose - - @echo "extracting binary..." - $(LLVM_OBJCOPY) \ - -O binary \ - "$(BUILDROOT)/Application" \ - "$(BUILDROOT)/Application.bin" \ - - -.PHONY: clean -clean: - @echo "cleaning..." - @swift package clean - @rm -rf .build diff --git a/rpi-4b-blink/Package.resolved b/rpi-4b-blink/Package.resolved deleted file mode 100644 index bfffc5ae..00000000 --- a/rpi-4b-blink/Package.resolved +++ /dev/null @@ -1,33 +0,0 @@ -{ - "originHash" : "d0330fea11b0fbdacbddd4f13debd9a4fe72ed5b628ad4959a93972f3572bf1f", - "pins" : [ - { - "identity" : "swift-argument-parser", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-argument-parser.git", - "state" : { - "revision" : "41982a3656a71c768319979febd796c6fd111d5c", - "version" : "1.5.0" - } - }, - { - "identity" : "swift-mmio", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-mmio.git", - "state" : { - "branch" : "main", - "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" - } - }, - { - "identity" : "swift-syntax", - "kind" : "remoteSourceControl", - "location" : "https://github.com/swiftlang/swift-syntax.git", - "state" : { - "revision" : "0687f71944021d616d34d922343dcef086855920", - "version" : "600.0.1" - } - } - ], - "version" : 3 -} diff --git a/rpi-4b-blink/Package.swift b/rpi-4b-blink/Package.swift deleted file mode 100644 index 5c4c7081..00000000 --- a/rpi-4b-blink/Package.swift +++ /dev/null @@ -1,21 +0,0 @@ -// swift-tools-version: 6.0 - -import PackageDescription - -let package = Package( - name: "rpi-4b-blink", - products: [ - .executable(name: "Application", targets: ["Application"]) - ], - dependencies: [ - .package(url: "https://github.com/apple/swift-mmio.git", branch: "main") - ], - targets: [ - .executableTarget( - name: "Application", - dependencies: [ - .product(name: "MMIO", package: "swift-mmio"), - "Support", - ]), - .target(name: "Support"), - ]) diff --git a/rpi-4b-blink/README.md b/rpi-4b-blink/README.md deleted file mode 100644 index a5ed157a..00000000 --- a/rpi-4b-blink/README.md +++ /dev/null @@ -1,21 +0,0 @@ -# rpi-4b-blink - - - -## Requirements - -- A Raspberry Pi 4B board -- An SD Card, with a Raspberry Pi OS installed (this way, we don't need to create the configuration files from scratch). You may backup `kernel8.img` and `config.txt` if you need the Linux install later, since we will change these files. - -## How to build and run this example: - -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- Build the program, then copy the kernel image to the SD card. -``` console -$ cd rpi-4b-blink -$ make -$ cp .build/release/Application.bin /Volumes/bootfs/kernel8.img -``` -- If your original OS is not 64-bit, make sure to set `arm_64bit=1` in `config.txt`. -- Place the SD card in your Raspberry Pi 4B, and connect it to power. -- After the boot sequence, the green (ACT) led will start blinking in a regular pattern. diff --git a/rpi-4b-blink/Sources/Application/Application.swift b/rpi-4b-blink/Sources/Application/Application.swift deleted file mode 100644 index 4a41320d..00000000 --- a/rpi-4b-blink/Sources/Application/Application.swift +++ /dev/null @@ -1,85 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import MMIO -import Support - -@Register(bitWidth: 32) -struct GPSET1 { - @ReadWrite(bits: 10..<11, as: Bool.self) - var set: SET -} - -@Register(bitWidth: 32) -struct GPCLR1 { - @ReadWrite(bits: 10..<11, as: Bool.self) - var clear: CLEAR -} - -@Register(bitWidth: 32) -struct GPFSEL4 { - @ReadWrite(bits: 6..<7, as: Bool.self) - var fsel42b1: FSEL42b1 - @ReadWrite(bits: 7..<8, as: Bool.self) - var fsel42b2: FSEL42b2 - @ReadWrite(bits: 8..<9, as: Bool.self) - var fsel42b3: FSEL42b3 -} - -@RegisterBlock -struct GPIO { - @RegisterBlock(offset: 0x200020) - var gpset1: Register - @RegisterBlock(offset: 0x20002c) - var gpclr1: Register - @RegisterBlock(offset: 0x200010) - var gpfsel4: Register -} - -let gpio = GPIO(unsafeAddress: 0xFE00_0000) - -func setLedOutput() { - gpio.gpfsel4.modify { - // setFunction Select 42 (fsel42) to 001 - $0.fsel42b1 = true - $0.fsel42b2 = false - $0.fsel42b3 = false - } -} - -func ledOn() { - gpio.gpset1.modify { - $0.set = true - } -} - -func ledOff() { - gpio.gpclr1.modify { - $0.clear = true - } -} - -func delay() { - for _ in 1..<1_000_000 { nop() } -} - -@main -struct Application { - static func main() { - setLedOutput() - while true { - ledOn() - delay() - ledOff() - delay() - } - } -} diff --git a/rpi-4b-blink/Sources/Support/boot.S b/rpi-4b-blink/Sources/Support/boot.S deleted file mode 100644 index 0a8f8c39..00000000 --- a/rpi-4b-blink/Sources/Support/boot.S +++ /dev/null @@ -1,41 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -.section ".text.boot" - -.global _start - -_start: - // Check processor ID is zero (executing on main core), else hang - mrs x1, mpidr_el1 - and x1, x1, #3 - cbz x1, 2f - // We're not on the main core, so hang in an infinite wait loop -1: wfe - b 1b -2: // We're on the main core! - - // Set stack to start below our code - ldr x1, =_start - mov sp, x1 - - // Clean the BSS section - ldr x1, =__bss_start // Start address - ldr w2, =__bss_size // Size of the section -3: cbz w2, 4f // Quit loop if zero - str xzr, [x1], #8 - sub w2, w2, #1 - cbnz w2, 3b // Loop if non-zero - - // Jump to Swift! -4: bl main - // Halt if Swift returns - b 1b diff --git a/rpi-4b-blink/Sources/Support/linkerscript.ld b/rpi-4b-blink/Sources/Support/linkerscript.ld deleted file mode 100644 index 8f10b405..00000000 --- a/rpi-4b-blink/Sources/Support/linkerscript.ld +++ /dev/null @@ -1,27 +0,0 @@ -SECTIONS -{ - /* Kernel load address for AArch64 */ - . = 0x80000; - .text : { KEEP(*(.text.boot)) *(.text .text.* .gnu.linkonce.t*) } - .rodata : { *(.rodata .rodata.* .gnu.linkonce.r*) } - PROVIDE(_data = .); - .data : { *(.data .data.* .gnu.linkonce.d*) } - .bss (NOLOAD) : { - . = ALIGN(16); - __bss_start = .; - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } - _end = .; - - /DISCARD/ : { - *(.comment) - *(.gnu*) - *(.note*) - *(.eh_frame*) - *(.swift_modhash) - } -} - -__bss_size = (__bss_end - __bss_start) >> 3; diff --git a/rpi-4b-blink/assets/hero.jpg b/rpi-4b-blink/assets/hero.jpg deleted file mode 100644 index 7deaf8f0..00000000 Binary files a/rpi-4b-blink/assets/hero.jpg and /dev/null differ diff --git a/rpi-5-blink/Makefile b/rpi-5-blink/Makefile deleted file mode 100644 index f07ed954..00000000 --- a/rpi-5-blink/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -##===----------------------------------------------------------------------===## -## -## This source file is part of the Swift open source project -## -## Copyright (c) 2025 Apple Inc. and the Swift project authors. -## Licensed under Apache License v2.0 with Runtime Library Exception -## -## See https://swift.org/LICENSE.txt for license information -## -##===----------------------------------------------------------------------===## - -# Paths -REPOROOT := $(shell git rev-parse --show-toplevel) -TOOLSROOT := $(REPOROOT)/Tools -TOOLSET := $(TOOLSROOT)/Toolsets/rpi-5-elf.json -LLVM_OBJCOPY := llvm-objcopy -SWIFT_BUILD := swift build - -# Flags -ARCH := aarch64 -TARGET := $(ARCH)-none-none-elf -SWIFT_BUILD_ARGS := \ - --configuration release \ - --triple $(TARGET) \ - --toolset $(TOOLSET) -BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) - -.PHONY: build -build: - @echo "building..." - $(SWIFT_BUILD) \ - $(SWIFT_BUILD_ARGS) \ - --verbose - - @echo "extracting binary..." - $(LLVM_OBJCOPY) \ - -O binary \ - "$(BUILDROOT)/Application" \ - "$(BUILDROOT)/Application.bin" - - -.PHONY: clean -clean: - @echo "cleaning..." - @swift package clean - @rm -rf .build diff --git a/rpi-5-blink/Package.resolved b/rpi-5-blink/Package.resolved deleted file mode 100644 index 4cf1835e..00000000 --- a/rpi-5-blink/Package.resolved +++ /dev/null @@ -1,33 +0,0 @@ -{ - "originHash" : "5bb00fe2bf59115297c70799769d8080cf6ce836d32f4a41d42e7c420afddec6", - "pins" : [ - { - "identity" : "swift-argument-parser", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-argument-parser.git", - "state" : { - "revision" : "41982a3656a71c768319979febd796c6fd111d5c", - "version" : "1.5.0" - } - }, - { - "identity" : "swift-mmio", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-mmio.git", - "state" : { - "branch" : "main", - "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" - } - }, - { - "identity" : "swift-syntax", - "kind" : "remoteSourceControl", - "location" : "https://github.com/swiftlang/swift-syntax.git", - "state" : { - "revision" : "0687f71944021d616d34d922343dcef086855920", - "version" : "600.0.1" - } - } - ], - "version" : 3 -} diff --git a/rpi-5-blink/Package.swift b/rpi-5-blink/Package.swift deleted file mode 100644 index 7bd48409..00000000 --- a/rpi-5-blink/Package.swift +++ /dev/null @@ -1,21 +0,0 @@ -// swift-tools-version: 6.0 - -import PackageDescription - -let package = Package( - name: "rpi-5-blink", - products: [ - .executable(name: "Application", targets: ["Application"]) - ], - dependencies: [ - .package(url: "https://github.com/apple/swift-mmio.git", branch: "main") - ], - targets: [ - .executableTarget( - name: "Application", - dependencies: [ - .product(name: "MMIO", package: "swift-mmio"), - "Support", - ]), - .target(name: "Support"), - ]) diff --git a/rpi-5-blink/README.md b/rpi-5-blink/README.md deleted file mode 100644 index 2ff683ca..00000000 --- a/rpi-5-blink/README.md +++ /dev/null @@ -1,22 +0,0 @@ -# rpi-5-blink - - - -## Requirements - -- A Raspberry Pi 5 board -- An SD Card, with a Raspberry Pi OS installed (this way, we don't need to create the configuration files from scratch). You may backup `kernel8.img` and `kernel_2712.img` if you need the Linux install later, since we will change these files. - -## How to build and run this example: - -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- Build the program, then copy the kernel image to the SD card. -``` console -$ cd rpi-5-blink -$ make -$ cp .build/release/Application.bin /Volumes/bootfs/kernel8.img # Copy kernel image to SD card -$ rm /Volumes/bootfs/kernel_2712.img # Delete this kernel image so our kernel8.img is used -$ # You can also rename our kernel8.img to kernel_2712.img, or set it to anything you want and specify "kernel=[your-img-name]" in config.txt. -``` -- Place the SD card in your Raspberry Pi 5, and connect it to power. -- After the boot sequence, the green (ACT) led will start blinking in a regular pattern. diff --git a/rpi-5-blink/Sources/Application/Application.swift b/rpi-5-blink/Sources/Application/Application.swift deleted file mode 100644 index 6173a1aa..00000000 --- a/rpi-5-blink/Sources/Application/Application.swift +++ /dev/null @@ -1,70 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import MMIO -import Support - -@Register(bitWidth: 32) -struct GIOIODIR { - @ReadWrite(bits: 9..<10, as: Bool.self) - var direction: DIRECTION -} - -@Register(bitWidth: 32) -struct GIODATA { - @ReadWrite(bits: 9..<10, as: Bool.self) - var value: VALUE -} - -@RegisterBlock -struct GPIO { - @RegisterBlock(offset: 0x00008) - var gioiodir: Register - @RegisterBlock(offset: 0x00004) - var giodata: Register -} - -let gpio = GPIO(unsafeAddress: 0x10_7d51_7c00) - -func setLedOutput() { - gpio.gioiodir.modify { - $0.direction = false // 0 is output, 1 is input - } -} - -func ledOn() { - gpio.giodata.modify { - $0.value = true // pin on - } -} - -func ledOff() { - gpio.giodata.modify { - $0.value = false // pin off - } -} - -func delay() { - for _ in 1..<1_000_000 { nop() } -} - -@main -struct Application { - static func main() { - setLedOutput() - while true { - ledOn() - delay() - ledOff() - delay() - } - } -} diff --git a/rpi-5-blink/Sources/Support/boot.S b/rpi-5-blink/Sources/Support/boot.S deleted file mode 100644 index 0a8f8c39..00000000 --- a/rpi-5-blink/Sources/Support/boot.S +++ /dev/null @@ -1,41 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -.section ".text.boot" - -.global _start - -_start: - // Check processor ID is zero (executing on main core), else hang - mrs x1, mpidr_el1 - and x1, x1, #3 - cbz x1, 2f - // We're not on the main core, so hang in an infinite wait loop -1: wfe - b 1b -2: // We're on the main core! - - // Set stack to start below our code - ldr x1, =_start - mov sp, x1 - - // Clean the BSS section - ldr x1, =__bss_start // Start address - ldr w2, =__bss_size // Size of the section -3: cbz w2, 4f // Quit loop if zero - str xzr, [x1], #8 - sub w2, w2, #1 - cbnz w2, 3b // Loop if non-zero - - // Jump to Swift! -4: bl main - // Halt if Swift returns - b 1b diff --git a/rpi-5-blink/Sources/Support/linkerscript.ld b/rpi-5-blink/Sources/Support/linkerscript.ld deleted file mode 100644 index 8f10b405..00000000 --- a/rpi-5-blink/Sources/Support/linkerscript.ld +++ /dev/null @@ -1,27 +0,0 @@ -SECTIONS -{ - /* Kernel load address for AArch64 */ - . = 0x80000; - .text : { KEEP(*(.text.boot)) *(.text .text.* .gnu.linkonce.t*) } - .rodata : { *(.rodata .rodata.* .gnu.linkonce.r*) } - PROVIDE(_data = .); - .data : { *(.data .data.* .gnu.linkonce.d*) } - .bss (NOLOAD) : { - . = ALIGN(16); - __bss_start = .; - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } - _end = .; - - /DISCARD/ : { - *(.comment) - *(.gnu*) - *(.note*) - *(.eh_frame*) - *(.swift_modhash) - } -} - -__bss_size = (__bss_end - __bss_start) >> 3; diff --git a/rpi-5-blink/assets/hero.jpg b/rpi-5-blink/assets/hero.jpg deleted file mode 100644 index 2f6b172e..00000000 Binary files a/rpi-5-blink/assets/hero.jpg and /dev/null differ diff --git a/rpi-pico-blink-sdk/BridgingHeader.h b/rpi-pico-blink-sdk/BridgingHeader.h deleted file mode 100644 index 417e466e..00000000 --- a/rpi-pico-blink-sdk/BridgingHeader.h +++ /dev/null @@ -1,14 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#pragma once - -#include "pico/stdlib.h" diff --git a/rpi-pico-blink-sdk/CMakeLists.txt b/rpi-pico-blink-sdk/CMakeLists.txt deleted file mode 100644 index 63a9a58d..00000000 --- a/rpi-pico-blink-sdk/CMakeLists.txt +++ /dev/null @@ -1,113 +0,0 @@ -cmake_minimum_required(VERSION 3.29) -include($ENV{PICO_SDK_PATH}/external/pico_sdk_import.cmake) - -set(CMAKE_Swift_COMPILATION_MODE wholemodule) -set(CMAKE_Swift_COMPILER_WORKS YES) - -project(swift-blinky) -pico_sdk_init() -enable_language(Swift) - -set(SWIFT_TARGET "armv6m-none-none-eabi") # default for rp2040 - -if(PICO_PLATFORM STREQUAL "rp2350-arm-s") - message(STATUS "PICO_PLATFORM is set to rp2350-arm-s, using armv7em") - set(SWIFT_TARGET "armv7em-none-none-eabi") - list(APPEND CLANG_ARCH_ABI_FLAGS "-Xcc -mfloat-abi=soft") -elseif(PICO_PLATFORM STREQUAL "rp2040") - message(STATUS "PICO_PLATFORM is set to RP2040, using armv6m") - list(APPEND CLANG_ARCH_ABI_FLAGS "-Xcc -mfloat-abi=soft") -elseif(PICO_PLATFORM STREQUAL "rp2350-riscv") - message(STATUS "PICO_PLATFORM is set to rp2350-riscv, using riscv32.") - set(SWIFT_TARGET "riscv32-none-none-eabi") - list(APPEND CLANG_ARCH_ABI_FLAGS "-Xcc -march=rv32imac_zicsr_zifencei_zba_zbb_zbs_zbkb -Xcc -mabi=ilp32") -endif() - -add_executable(swift-blinky - # Source files: - Main.swift -) - -set_target_properties(swift-blinky PROPERTIES LINKER_LANGUAGE CXX) - -target_link_libraries(swift-blinky - pico_stdlib hardware_uart hardware_gpio -) - -# Clear the default COMPILE_OPTIONS which include C specific compiler flags that the Swift compiler will not accept -# Instead, set those options to only apply when compiling C code. -set_target_properties(pico_standard_link PROPERTIES INTERFACE_COMPILE_OPTIONS "") -target_compile_options(pico_standard_link INTERFACE "$<$:SHELL: -ffunction-sections -fdata-sections>") - -# Gather C compile definitions from all dependencies -set_property(GLOBAL PROPERTY visited_targets "") -set_property(GLOBAL PROPERTY compilerdefs_list "") - -function(gather_compile_definitions_recursive target) - # Get the current value of visited_targets - get_property(visited_targets GLOBAL PROPERTY visited_targets) - - # make sure we don't visit the same target twice - # and that we don't visit the special generator expressions - if (${target} MATCHES "\\\$<" OR ${target} MATCHES "::@" OR ${target} IN_LIST visited_targets) - return() - endif() - - # Append the target to visited_targets - list(APPEND visited_targets ${target}) - set_property(GLOBAL PROPERTY visited_targets "${visited_targets}") - - get_target_property(target_definitions ${target} INTERFACE_COMPILE_DEFINITIONS) - if (target_definitions) - # Append the target definitions to compilerdefs_list - get_property(compilerdefs_list GLOBAL PROPERTY compilerdefs_list) - list(APPEND compilerdefs_list ${target_definitions}) - set_property(GLOBAL PROPERTY compilerdefs_list "${compilerdefs_list}") - endif() - - get_target_property(target_linked_libs ${target} INTERFACE_LINK_LIBRARIES) - if (target_linked_libs) - foreach(linked_target ${target_linked_libs}) - # Recursively gather compile definitions from dependencies - gather_compile_definitions_recursive(${linked_target}) - endforeach() - endif() -endfunction() - -gather_compile_definitions_recursive(swift-blinky) -get_property(COMPILE_DEFINITIONS GLOBAL PROPERTY compilerdefs_list) -get_property(INCLUDES GLOBAL PROPERTY includes_list) - -# Convert compiler definitions into a format that swiftc can understand -list(REMOVE_DUPLICATES COMPILE_DEFINITIONS) -list(PREPEND COMPILE_DEFINITIONS "") # adds a semicolon at the beginning -string(REPLACE "$" "$" COMPILE_DEFINITIONS "${COMPILE_DEFINITIONS}") -string(REPLACE ";" " -Xcc -D" COMPILE_DEFINITIONS "${COMPILE_DEFINITIONS}") - -# Compute -Xcc flags to set up the C and C++ header search paths for Swift (for bridging header). -set(IMPLICIT_INCLUDES) -foreach(dir ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES}) - string(CONCAT IMPLICIT_INCLUDES ${IMPLICIT_INCLUDES} "-Xcc ") - string(CONCAT IMPLICIT_INCLUDES ${IMPLICIT_INCLUDES} "-I${dir} ") -endforeach() -foreach(dir ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES}) - string(CONCAT IMPLICIT_INCLUDES ${IMPLICIT_INCLUDES} "-Xcc ") - string(CONCAT IMPLICIT_INCLUDES ${IMPLICIT_INCLUDES} "-I${dir} ") -endforeach() - -target_compile_options(swift-blinky PUBLIC - "$<$:SHELL: - -target ${SWIFT_TARGET} - -enable-experimental-feature Embedded - -parse-as-library - -module-name swift_blinky - - ${CLANG_ARCH_ABI_FLAGS} - -Xcc -fshort-enums - -Xfrontend -function-sections - -import-bridging-header ${CMAKE_CURRENT_LIST_DIR}/BridgingHeader.h - ${COMPILE_DEFINITIONS} - ${IMPLICIT_INCLUDES} - >") - -pico_add_extra_outputs(swift-blinky) diff --git a/rpi-pico-blink-sdk/Main.swift b/rpi-pico-blink-sdk/Main.swift deleted file mode 100644 index 74c0d7af..00000000 --- a/rpi-pico-blink-sdk/Main.swift +++ /dev/null @@ -1,25 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -@main -struct Main { - static func main() { - let led = UInt32(PICO_DEFAULT_LED_PIN) - gpio_init(led) - gpio_set_dir(led, true) - while true { - gpio_put(led, true) - sleep_ms(250) - gpio_put(led, false) - sleep_ms(250) - } - } -} diff --git a/rpi-pico-blink-sdk/README.md b/rpi-pico-blink-sdk/README.md deleted file mode 100644 index bd6d9e85..00000000 --- a/rpi-pico-blink-sdk/README.md +++ /dev/null @@ -1,43 +0,0 @@ -# rpi-pico-blink-sdk - -This example demonstrates how to integrate with the Pico SDK which is using CMake as its build system -- the simplest way to integrate with it is to also use CMake to build a Swift firmware application on top of the SDK and the libraries from it. - - - -## Requirements - -- A Raspberry Pi Pico (non-W) board. If you have a Pico W instead, refer to the [rpi-picow-blink-sdk](../rpi-picow-blink-sdk) sample instead. -- Follow the setup steps at https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf, in particular you'll need: - - A checkout of the [pico-sdk](https://github.com/raspberrypi/pico-sdk.git), with git submodules checked out. If you'd like to try RISC-V support for RP2350, you'll need Pico SDK 2.1.0 or later. - - A checkout of the [pico-examples](https://github.com/raspberrypi/pico-examples.git). - - CMake. - - The [Arm Embedded Toolchain](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads), or the RISC-V toolchain if you want to build for the RISC-V cores on the RP2350. -- Before trying to use Swift with the Pico SDK, make sure your environment works and can build the provided C/C++ sample projects, in particular: - - Try building and running the "blink" example from pico-examples written in C. - - -## Building - -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- Build and copy the program in the UF2 format to the Mass Storage device to trigger flashing the program into memory (after which the device will reboot and run the firmware): - -``` console -$ cd rpi-pico-blink-sdk -$ export PICO_BOARD='' # Examples: pico, pico2 -$ export PICO_PLATFORM='' # Optional; useful if you'd like to compile for RISC-V. Examples: rp2040, rp2350-arm-s, rp2350-riscv -$ export PICO_SDK_PATH='' -$ export PICO_TOOLCHAIN_PATH='' # A default `brew` install will be located at `/Applications/ArmGNUToolchain/[version]/arm-none-eabi`. This can also be a RISC-V toolchain for the RP2350. -$ cmake -B build -G Ninja . -DCMAKE_EXPORT_COMPILE_COMMANDS=On -$ cmake --build build -``` - -## Running - -- Connect the Pico board via a USB cable to your Mac, and make sure it's in the USB Mass Storage firmware upload mode (either hold the BOOTSEL button while plugging the board, or make sure your Flash memory doesn't contain any valid firmware). -- Copy the UF2 firmware to the Mass Storage device: - -```console -$ cp build/swift-blinky.uf2 /Volumes/RP2040 -``` - -- The green LED should now be blinking in a pattern. diff --git a/rpi-pico-blink/Makefile b/rpi-pico-blink/Makefile deleted file mode 100755 index 15cee44d..00000000 --- a/rpi-pico-blink/Makefile +++ /dev/null @@ -1,60 +0,0 @@ -##===----------------------------------------------------------------------===## -## -## This source file is part of the Swift open source project -## -## Copyright (c) 2025 Apple Inc. and the Swift project authors. -## Licensed under Apache License v2.0 with Runtime Library Exception -## -## See https://swift.org/LICENSE.txt for license information -## -##===----------------------------------------------------------------------===## - -# Paths -REPOROOT := $(shell git rev-parse --show-toplevel) -TOOLSROOT := $(REPOROOT)/Tools -TOOLSET := $(TOOLSROOT)/Toolsets/pico.json -MACHO2UF2 := $(TOOLSROOT)/macho2uf2.py -SWIFT_BUILD := swift build - -# Flags -PICO_FAMILY := rp2040 -ARCH := armv6m -TARGET := $(ARCH)-apple-none-macho -SWIFT_BUILD_ARGS := \ - --configuration release \ - --triple $(TARGET) \ - --toolset $(TOOLSET) -BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) - -.PHONY: build -build: - @echo "building..." - $(SWIFT_BUILD) \ - $(SWIFT_BUILD_ARGS) \ - -Xlinker -map -Xlinker $(BUILDROOT)/Application.mangled.map \ - --verbose - - @echo "demangling linker map..." - cat $(BUILDROOT)/Application.mangled.map \ - | c++filt | swift demangle > $(BUILDROOT)/Application.map - - @echo "disassembling..." - otool \ - -arch $(ARCH) -v -V -d -t \ - $(BUILDROOT)/Application \ - | c++filt | swift demangle > $(BUILDROOT)/Application.disassembly - - @echo "extracting binary..." - $(MACHO2UF2) \ - --pico-family "$(PICO_FAMILY)" \ - "$(BUILDROOT)/Application" \ - "$(BUILDROOT)/Application.uf2" \ - --base-address 0x20000000 \ - --segments '__TEXT,__DATA,__VECTORS,__RESET' - - -.PHONY: clean -clean: - @echo "cleaning..." - @swift package clean - @rm -rf .build diff --git a/rpi-pico-blink/Package.swift b/rpi-pico-blink/Package.swift deleted file mode 100644 index df681886..00000000 --- a/rpi-pico-blink/Package.swift +++ /dev/null @@ -1,15 +0,0 @@ -// swift-tools-version: 6.0 - -import PackageDescription - -let package = Package( - name: "RP2040", - products: [ - .executable(name: "Application", targets: ["Application"]) - ], - targets: [ - .executableTarget(name: "Application", dependencies: ["RP2040"]), - .target(name: "Support"), - .target(name: "RP2040", dependencies: ["Support"]), - ], - swiftLanguageModes: [.v5]) diff --git a/rpi-pico-blink/README.md b/rpi-pico-blink/README.md deleted file mode 100644 index 12ed0a5f..00000000 --- a/rpi-pico-blink/README.md +++ /dev/null @@ -1,21 +0,0 @@ -# rpi-pico-blink - - - -## Requirements - -- A Raspberry Pi Pico (non-W) board. If you have a Pico W instead, this sample code will require modifications. - -## How to build and run this example: - -- Connect the Pico board via a USB cable to your Mac, and make sure it's in the USB Mass Storage firmware upload mode (either hold the BOOTSEL button while plugging the board, or make sure your Flash memory doesn't contain any valid firmware). -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- Build and copy the program in the UF2 format to the Mass Storage device to trigger flashing the program into memory (after which the device will reboot and run the firmware): - -``` console -$ cd rpi-pico-blink -$ make -$ cp .build/Application.uf2 /Volumes/RP2040 -``` - -- The green LED should now be blinking in a pattern. diff --git a/rpi-pico-blink/Sources/Application/Application.swift b/rpi-pico-blink/Sources/Application/Application.swift deleted file mode 100644 index a27b8b76..00000000 --- a/rpi-pico-blink/Sources/Application/Application.swift +++ /dev/null @@ -1,367 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import RP2040 - -@main -struct Application { - // swift-format-ignore: NeverUseImplicitlyUnwrappedOptionals - static var board: RP2040! = nil - - static func main() { - board = RP2040() - - board.setMode(.output, pin: .d22) - board.digitalWrite(pin: .d22, true) - - let str: StaticString = "Hello Swift!" - - board.sleep(forMilliseconds: 1000) - - board.digitalWrite(pin: .d22, false) - - while true { - str.withUTF8Buffer { buffer in - for ch in buffer { - emit(ch) - } - delay(7) - } - } - } - - static func delay(_ count: Int = 1) { - board.sleep(forMilliseconds: 100 * count) - } - - static func dot() { - board.digitalWrite(pin: .d22, true) - delay() - board.digitalWrite(pin: .d22, false) - delay() - } - - static func dash() { - board.digitalWrite(pin: .d22, true) - delay(3) - board.digitalWrite(pin: .d22, false) - delay() - } - - static func letter(_ codes: () -> Void) { - codes() - delay(3) - } - - static func emit(_ ch: UInt8) { - switch ch { - case 0x41, 0x61: - letter { - dot() - dash() - } - case 0x42, 0x62: - letter { - dash() - dot() - dot() - dot() - } - case 0x43, 0x63: - letter { - dash() - dot() - dash() - dot() - } - case 0x44, 0x64: - letter { - dash() - dot() - dot() - } - case 0x45, 0x65: letter { dot() } - case 0x46, 0x66: - letter { - dot() - dot() - dash() - dot() - } - case 0x47, 0x67: - letter { - dash() - dash() - dot() - } - case 0x48, 0x68: - letter { - dot() - dot() - dot() - dot() - } - case 0x49, 0x69: - letter { - dot() - dot() - } - case 0x4A, 0x6A: - letter { - dot() - dash() - dash() - dash() - } - case 0x4B, 0x6B: - letter { - dash() - dot() - dash() - } - case 0x4C, 0x6C: - letter { - dot() - dash() - dot() - dot() - } - case 0x4D, 0x6D: - letter { - dash() - dash() - } - case 0x4E, 0x6E: - letter { - dash() - dot() - } - case 0x4F, 0x6F: - letter { - dash() - dash() - dash() - } - case 0x50, 0x70: - letter { - dot() - dash() - dash() - dot() - } - case 0x51, 0x71: - letter { - dash() - dash() - dot() - dash() - } - case 0x52, 0x72: - letter { - dot() - dash() - dot() - } - case 0x53, 0x73: - letter { - dot() - dot() - dot() - } - case 0x54, 0x74: letter { dash() } - case 0x55, 0x75: - letter { - dot() - dot() - dash() - } - case 0x56, 0x76: - letter { - dot() - dot() - dot() - dash() - } - case 0x57, 0x77: - letter { - dot() - dash() - dash() - } - case 0x58, 0x78: - letter { - dash() - dot() - dot() - dash() - } - case 0x59, 0x79: - letter { - dash() - dot() - dash() - dash() - } - case 0x5A, 0x7A: - letter { - dash() - dash() - dot() - dot() - } - case 0x31: - letter { - dot() - dash() - dash() - dash() - dash() - } - case 0x32: - letter { - dot() - dot() - dash() - dash() - dash() - } - case 0x33: - letter { - dot() - dot() - dot() - dash() - dash() - } - case 0x34: - letter { - dot() - dot() - dot() - dot() - dash() - } - case 0x35: - letter { - dot() - dot() - dot() - dot() - dot() - } - case 0x36: - letter { - dash() - dot() - dot() - dot() - dot() - } - case 0x37: - letter { - dash() - dash() - dot() - dot() - dot() - } - case 0x38: - letter { - dash() - dash() - dash() - dot() - dot() - } - case 0x39: - letter { - dash() - dash() - dash() - dash() - dot() - } - case 0x30: - letter { - dash() - dash() - dash() - dash() - dash() - } - case 0x2E: - letter { - dot() - dash() - dot() - dash() - dot() - dash() - } - case 0x2C: - letter { - dash() - dash() - dot() - dot() - dash() - dash() - } - case 0x3F: - letter { - dot() - dot() - dash() - dash() - dot() - dot() - } - case 0x21: - letter { - dash() - dot() - dash() - dot() - dash() - dash() - } - case 0x2F: - letter { - dash() - dot() - dot() - dash() - dot() - } - case 0x28: - letter { - dash() - dot() - dash() - dash() - dot() - } - case 0x29: - letter { - dash() - dot() - dash() - dash() - dot() - dash() - } - case 0x20: - delay(7) - default: - break - } - } -} diff --git a/rpi-pico-blink/Sources/RP2040/HAL/Digital.swift b/rpi-pico-blink/Sources/RP2040/HAL/Digital.swift deleted file mode 100644 index d6643c20..00000000 --- a/rpi-pico-blink/Sources/RP2040/HAL/Digital.swift +++ /dev/null @@ -1,131 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -extension RP2040 { - enum PinDirection { - case input - case output - } - - func setDirection(_ pin: some DigitalPin, _ direction: PinDirection) { - switch direction { - case .output: - hardware.sio.enableOutput(1 << pin.rawValue) - case .input: - hardware.sio.disableOutput(1 << pin.rawValue) - } - } - - func put(_ pin: some DigitalPin, _ value: Bool) { - switch value { - case true: - hardware.sio.setOutput(1 << pin.rawValue) - case false: - hardware.sio.clearOutput(1 << pin.rawValue) - } - } - - public func write( - _ byte: UInt8, - to pins: ( - some DigitalPin, some DigitalPin, some DigitalPin, some DigitalPin, - some DigitalPin, some DigitalPin, some DigitalPin, some DigitalPin - ) - ) { - var set = UInt32(0) - var clear = UInt32(0) - - if byte & (1 << 0) != 0 { - set |= 1 << pins.0.rawValue - } else { - clear |= 1 << pins.0.rawValue - } - if byte & (1 << 1) != 0 { - set |= 1 << pins.1.rawValue - } else { - clear |= 1 << pins.1.rawValue - } - if byte & (1 << 2) != 0 { - set |= 1 << pins.2.rawValue - } else { - clear |= 1 << pins.2.rawValue - } - if byte & (1 << 3) != 0 { - set |= 1 << pins.0.rawValue - } else { - clear |= 1 << pins.3.rawValue - } - if byte & (1 << 4) != 0 { - set |= 1 << pins.4.rawValue - } else { - clear |= 1 << pins.4.rawValue - } - if byte & (1 << 5) != 0 { - set |= 1 << pins.5.rawValue - } else { - clear |= 1 << pins.5.rawValue - } - if byte & (1 << 6) != 0 { - set |= 1 << pins.6.rawValue - } else { - clear |= 1 << pins.6.rawValue - } - if byte & (1 << 7) != 0 { - set |= 1 << pins.7.rawValue - } else { - clear |= 1 << pins.7.rawValue - } - hardware.sio.setOutput(set) - hardware.sio.clearOutput(clear) - } - - func setFunction( - _ pin: some DigitalPin, - _ function: RP2040Hardware.IOBank.GPIOControl.Projection.FuncSel - ) { - hardware.padsBank0.gpio[pin.rawValue].modify { - $0.outputDisable = false - $0.inputEnable = true - $0.driveStrength = .level4mA - $0.pullUpEnable = false - $0.pullDownEnable = true - $0.schmittTriggerEnable = true - $0.slewRateControl = .slow - } - hardware.ioBank0.gpioControl[pin.rawValue].modify { - $0.functionSelection = function - } - } - - func initialize(_ pin: some DigitalPin) { - setDirection(pin, .input) - put(pin, false) - setFunction(pin, .sio0) - } - - public func setMode(_ mode: PinMode, pin: some DigitalPin) { - switch mode { - case .output4mA: - initialize(pin) - hardware.padsBank0.gpio[pin.rawValue].modify { - $0.driveStrength = .level4mA - } - setDirection(pin, .output) - default: - break - } - } - - public func digitalWrite(pin: some DigitalPin, _ value: Bool) { - setFunction(pin, .sio0) - put(pin, value) - } -} diff --git a/rpi-pico-blink/Sources/RP2040/HAL/Pins.swift b/rpi-pico-blink/Sources/RP2040/HAL/Pins.swift deleted file mode 100644 index cf9afec5..00000000 --- a/rpi-pico-blink/Sources/RP2040/HAL/Pins.swift +++ /dev/null @@ -1,502 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -extension RP2040 { - public enum PinMode { - case input - case inputPullup - case inputPulldown - case output2mA - case output4mA - case output8mA - case output12mA - - public static var output: PinMode { return .output4mA } - } -} - - -public protocol RawPin { - var rawValue: UInt32 { get } -} - -public protocol DigitalPin: RawPin { } - -public protocol AnalogPin: RawPin { } - -public protocol I2CSDAPin: RawPin { } -public protocol I2CSCLPin: RawPin { } - -public protocol I2C0SDAPin: I2CSDAPin { } -public protocol I2C0SCLPin: I2CSCLPin { } - -public protocol I2C1SDAPin: I2CSDAPin { } -public protocol I2C1SCLPin: I2CSCLPin { } - -public protocol SPISCKPin: RawPin { } -public protocol SPITXPin: RawPin { } -public protocol SPIRXPin: RawPin { } -public protocol SPICSPin: RawPin { } - -public protocol SPI0SCKPin: SPISCKPin { } -public protocol SPI0TXPin: SPITXPin { } -public protocol SPI0RXPin: SPIRXPin { } -public protocol SPI0CSPin: SPICSPin { } - -public protocol SPI1SCKPin: SPISCKPin { } -public protocol SPI1TXPin: SPITXPin { } -public protocol SPI1RXPin: SPIRXPin { } -public protocol SPI1CSPin: SPICSPin { } - -public protocol UARTTXPin: RawPin { } -public protocol UARTRXPin: RawPin { } - -public protocol UART0TXPin: UARTTXPin { } -public protocol UART0RXPin: UARTRXPin { } - -public protocol UART1TXPin: UARTTXPin { } -public protocol UART1RXPin: UART0RXPin { } - -public struct PhysicalPin1: DigitalPin, SPI0RXPin, I2C0SDAPin, UART0TXPin { - public var rawValue: UInt32 { 0 } -} - -public struct PhysicalPin2: DigitalPin, SPI0CSPin, I2C0SCLPin, UART0RXPin { - public var rawValue: UInt32 { 1 } -} - -public struct PhysicalPin3 { } // GND - -public struct PhysicalPin4: DigitalPin, SPI0SCKPin, I2C1SDAPin { - public var rawValue: UInt32 { 2 } -} - -public struct PhysicalPin5: DigitalPin, SPI0TXPin, I2C1SCLPin { - public var rawValue: UInt32 { 3 } -} - -public struct PhysicalPin6: DigitalPin, SPI0RXPin, I2C0SDAPin, UART1TXPin { - public var rawValue: UInt32 { 4 } -} - -public struct PhysicalPin7: DigitalPin, SPI0CSPin, I2C0SCLPin, UART1RXPin { - public var rawValue: UInt32 { 5 } -} - -public struct PhysicalPin8 { } // GND - -public struct PhysicalPin9: DigitalPin, SPI0SCKPin, I2C1SDAPin { - public var rawValue: UInt32 { 6 } -} - -public struct PhysicalPin10: DigitalPin, SPI0TXPin, I2C1SCLPin { - public var rawValue: UInt32 { 7 } -} - -public struct PhysicalPin11: DigitalPin, SPI1RXPin, I2C0SDAPin, UART1TXPin { - public var rawValue: UInt32 { 8 } -} - -public struct PhysicalPin12: DigitalPin, SPI1CSPin, I2C0SCLPin, UART1RXPin { - public var rawValue: UInt32 { 9 } -} - -public struct PhysicalPin13 { } // GND - -public struct PhysicalPin14: DigitalPin, SPI1SCKPin, I2C1SDAPin { - public var rawValue: UInt32 { 10 } -} - -public struct PhysicalPin15: DigitalPin, SPI1TXPin, I2C1SCLPin { - public var rawValue: UInt32 { 11 } -} - -public struct PhysicalPin16: DigitalPin, SPI1RXPin, I2C0SDAPin, UART0TXPin { - public var rawValue: UInt32 { 12 } -} - -public struct PhysicalPin17: DigitalPin, SPI1CSPin, I2C0SCLPin, UART0RXPin { - public var rawValue: UInt32 { 13 } -} - -public struct PhysicalPin18 { } // GND - -public struct PhysicalPin19: DigitalPin, SPI1SCKPin, I2C1SDAPin { - public var rawValue: UInt32 { 14 } -} - -public struct PhysicalPin20: DigitalPin, SPI1TXPin, I2C1SCLPin { - public var rawValue: UInt32 { 15 } -} - -public struct PhysicalPin21: DigitalPin, SPI0RXPin, I2C0SDAPin, UART0TXPin { - public var rawValue: UInt32 { 16 } -} - -public struct PhysicalPin22: DigitalPin, SPI0CSPin, I2C0SCLPin, UART0RXPin { - public var rawValue: UInt32 { 17 } -} - -public struct PhysicalPin23 { } // GND - -public struct PhysicalPin24: DigitalPin, SPI0SCKPin, I2C1SDAPin { - public var rawValue: UInt32 { 18 } -} - -public struct PhysicalPin25: DigitalPin, SPI0TXPin, I2C1SCLPin { - public var rawValue: UInt32 { 19 } -} - -public struct PhysicalPin26: DigitalPin, I2C0SDAPin { - public var rawValue: UInt32 { 20 } -} - -public struct PhysicalPin27: DigitalPin, I2C0SCLPin { - public var rawValue: UInt32 { 21 } -} - -public struct PhysicalPin28 { } // GND - -public struct PhysicalPin29: DigitalPin { - public var rawValue: UInt32 { 25 } -} - -public struct PhysicalPin30 { } // RUN - -public struct PhysicalPin31: DigitalPin, AnalogPin, I2C1SDAPin { - public var rawValue: UInt32 { 26 } -} - -public struct PhysicalPin32: DigitalPin, AnalogPin, I2C1SCLPin { - public var rawValue: UInt32 { 27 } -} - -public struct PhysicalPin33 { } // GDN, AGND - -public struct PhysicalPin34: DigitalPin, AnalogPin { - public var rawValue: UInt32 { 28 } -} - -public struct PhysicalPin35 { } // ADC_VREF - -public struct PhysicalPin36 { } // 3V3 - -public struct PhysicalPin37 { } // 3V3_EN - -public struct PhysicalPin38 { } // GND - -public struct PhysicalPin39 { } // VSYS - -public struct PhysicalPin40 { } // VBUS - -extension DigitalPin where Self == PhysicalPin1 { public static var d0: some DigitalPin { PhysicalPin1() } } -extension DigitalPin where Self == PhysicalPin2 { public static var d1: some DigitalPin { PhysicalPin2() } } -extension DigitalPin where Self == PhysicalPin4 { public static var d2: some DigitalPin { PhysicalPin4() } } -extension DigitalPin where Self == PhysicalPin5 { public static var d3: some DigitalPin { PhysicalPin5() } } -extension DigitalPin where Self == PhysicalPin6 { public static var d4: some DigitalPin { PhysicalPin6() } } -extension DigitalPin where Self == PhysicalPin7 { public static var d5: some DigitalPin { PhysicalPin7() } } -extension DigitalPin where Self == PhysicalPin9 { public static var d6: some DigitalPin { PhysicalPin9() } } -extension DigitalPin where Self == PhysicalPin10 { public static var d7: some DigitalPin { PhysicalPin10() } } -extension DigitalPin where Self == PhysicalPin11 { public static var d8: some DigitalPin { PhysicalPin11() } } -extension DigitalPin where Self == PhysicalPin12 { public static var d9: some DigitalPin { PhysicalPin12() } } -extension DigitalPin where Self == PhysicalPin14 { public static var d10: some DigitalPin { PhysicalPin14() } } -extension DigitalPin where Self == PhysicalPin15 { public static var d11: some DigitalPin { PhysicalPin15() } } -extension DigitalPin where Self == PhysicalPin16 { public static var d12: some DigitalPin { PhysicalPin16() } } -extension DigitalPin where Self == PhysicalPin17 { public static var d13: some DigitalPin { PhysicalPin17() } } -extension DigitalPin where Self == PhysicalPin19 { public static var d14: some DigitalPin { PhysicalPin19() } } -extension DigitalPin where Self == PhysicalPin20 { public static var d15: some DigitalPin { PhysicalPin20() } } -extension DigitalPin where Self == PhysicalPin21 { public static var d16: some DigitalPin { PhysicalPin21() } } -extension DigitalPin where Self == PhysicalPin22 { public static var d17: some DigitalPin { PhysicalPin22() } } -extension DigitalPin where Self == PhysicalPin24 { public static var d18: some DigitalPin { PhysicalPin24() } } -extension DigitalPin where Self == PhysicalPin25 { public static var d19: some DigitalPin { PhysicalPin25() } } -extension DigitalPin where Self == PhysicalPin26 { public static var d20: some DigitalPin { PhysicalPin26() } } -extension DigitalPin where Self == PhysicalPin27 { public static var d21: some DigitalPin { PhysicalPin27() } } -extension DigitalPin where Self == PhysicalPin29 { public static var d22: some DigitalPin { PhysicalPin29() } } -extension DigitalPin where Self == PhysicalPin31 { public static var d26: some DigitalPin { PhysicalPin31() } } -extension DigitalPin where Self == PhysicalPin32 { public static var d27: some DigitalPin { PhysicalPin32() } } -extension DigitalPin where Self == PhysicalPin34 { public static var d28: some DigitalPin { PhysicalPin34() } } - -extension SPI0RXPin where Self == PhysicalPin1 { public static var d0: some SPI0RXPin { PhysicalPin1() } } -extension SPI0RXPin where Self == PhysicalPin6 { public static var d4: some SPI0RXPin { PhysicalPin6() } } -extension SPI0RXPin where Self == PhysicalPin21 { public static var d16: some SPI0RXPin { PhysicalPin21() } } - -extension SPI0CSPin where Self == PhysicalPin2 { public static var d0: some SPI0CSPin { PhysicalPin2() } } -extension SPI0CSPin where Self == PhysicalPin7 { public static var d5: some SPI0CSPin { PhysicalPin7() } } -extension SPI0CSPin where Self == PhysicalPin22 { public static var d17: some SPI0CSPin { PhysicalPin22() } } - -extension SPI0SCKPin where Self == PhysicalPin4 { public static var d2: some SPI0SCKPin { PhysicalPin4() } } -extension SPI0SCKPin where Self == PhysicalPin9 { public static var d6: some SPI0SCKPin { PhysicalPin9() } } -extension SPI0SCKPin where Self == PhysicalPin24 { public static var d18: some SPI0SCKPin { PhysicalPin24() } } - -extension SPI0TXPin where Self == PhysicalPin5 { public static var d2: some SPI0TXPin { PhysicalPin5() } } -extension SPI0TXPin where Self == PhysicalPin10 { public static var d7: some SPI0TXPin { PhysicalPin10() } } -extension SPI0TXPin where Self == PhysicalPin25 { public static var d19: some SPI0TXPin { PhysicalPin25() } } - -extension SPI1RXPin where Self == PhysicalPin11 { public static var d8: some SPI1RXPin { PhysicalPin11() } } -extension SPI1RXPin where Self == PhysicalPin16 { public static var d12: some SPI1RXPin { PhysicalPin16() } } - -extension SPI1CSPin where Self == PhysicalPin12 { public static var d9: some SPI1CSPin { PhysicalPin12() } } -extension SPI1CSPin where Self == PhysicalPin17 { public static var d13: some SPI1CSPin { PhysicalPin17() } } - -extension SPI1SCKPin where Self == PhysicalPin14 { public static var d10: some SPI1SCKPin { PhysicalPin14() } } -extension SPI1SCKPin where Self == PhysicalPin19 { public static var d14: some SPI1SCKPin { PhysicalPin19() } } - -extension SPI1TXPin where Self == PhysicalPin15 { public static var d11: some SPI1TXPin { PhysicalPin15() } } -extension SPI1TXPin where Self == PhysicalPin20 { public static var d15: some SPI1TXPin { PhysicalPin20() } } - -extension I2C0SDAPin where Self == PhysicalPin1 { public static var d0: some I2C0SDAPin { PhysicalPin1() } } -extension I2C0SDAPin where Self == PhysicalPin6 { public static var d4: some I2C0SDAPin { PhysicalPin6() } } -extension I2C0SDAPin where Self == PhysicalPin11 { public static var d8: some I2C0SDAPin { PhysicalPin11() } } -extension I2C0SDAPin where Self == PhysicalPin21 { public static var d16: some I2C0SDAPin { PhysicalPin21() } } -extension I2C0SDAPin where Self == PhysicalPin26 { public static var d20: some I2C0SDAPin { PhysicalPin26() } } - -extension I2C0SCLPin where Self == PhysicalPin2 { public static var d1: some I2C0SCLPin { PhysicalPin2() } } -extension I2C0SCLPin where Self == PhysicalPin7 { public static var d5: some I2C0SCLPin { PhysicalPin7() } } -extension I2C0SCLPin where Self == PhysicalPin12 { public static var d9: some I2C0SCLPin { PhysicalPin12() } } -extension I2C0SCLPin where Self == PhysicalPin22 { public static var d17: some I2C0SCLPin { PhysicalPin22() } } -extension I2C0SCLPin where Self == PhysicalPin27 { public static var d21: some I2C0SCLPin { PhysicalPin27() } } - -extension I2C1SDAPin where Self == PhysicalPin4 { public static var d2: some I2C1SDAPin { PhysicalPin4() } } -extension I2C1SDAPin where Self == PhysicalPin9 { public static var d6: some I2C1SDAPin { PhysicalPin9() } } -extension I2C1SDAPin where Self == PhysicalPin14 { public static var d10: some I2C1SDAPin { PhysicalPin14() } } -extension I2C1SDAPin where Self == PhysicalPin19 { public static var d14: some I2C1SDAPin { PhysicalPin19() } } -extension I2C1SDAPin where Self == PhysicalPin24 { public static var d18: some I2C1SDAPin { PhysicalPin24() } } -extension I2C1SDAPin where Self == PhysicalPin31 { public static var d26: some I2C1SDAPin { PhysicalPin31() } } - -extension I2C1SCLPin where Self == PhysicalPin5 { public static var d3: some I2C1SCLPin { PhysicalPin5() } } -extension I2C1SCLPin where Self == PhysicalPin10 { public static var d7: some I2C1SCLPin { PhysicalPin10() } } -extension I2C1SCLPin where Self == PhysicalPin15 { public static var d11: some I2C1SCLPin { PhysicalPin15() } } -extension I2C1SCLPin where Self == PhysicalPin20 { public static var d15: some I2C1SCLPin { PhysicalPin20() } } -extension I2C1SCLPin where Self == PhysicalPin25 { public static var d19: some I2C1SCLPin { PhysicalPin25() } } -extension I2C1SCLPin where Self == PhysicalPin32 { public static var d27: some I2C1SCLPin { PhysicalPin32() } } - -extension UART0TXPin where Self == PhysicalPin1 { public static var d0: some UART0TXPin { PhysicalPin1() } } -extension UART0TXPin where Self == PhysicalPin16 { public static var d12: some UART0TXPin { PhysicalPin16() } } -extension UART0TXPin where Self == PhysicalPin21 { public static var d16: some UART0TXPin { PhysicalPin21() } } - -extension UART0RXPin where Self == PhysicalPin2 { public static var d1: some UART0RXPin { PhysicalPin2() } } -extension UART0RXPin where Self == PhysicalPin17 { public static var d13: some UART0RXPin { PhysicalPin17() } } -extension UART0RXPin where Self == PhysicalPin22 { public static var d17: some UART0RXPin { PhysicalPin22() } } - -extension UART1TXPin where Self == PhysicalPin6 { public static var d4: some UART1TXPin { PhysicalPin6() } } -extension UART1TXPin where Self == PhysicalPin11 { public static var d8: some UART1TXPin { PhysicalPin11() } } - -extension UART1RXPin where Self == PhysicalPin7 { public static var d5: some UART1RXPin { PhysicalPin7() } } -extension UART1RXPin where Self == PhysicalPin12 { public static var d9: some UART1RXPin { PhysicalPin12() } } - -extension AnalogPin where Self == PhysicalPin31 { public static var a0: some AnalogPin { PhysicalPin31() } } -extension AnalogPin where Self == PhysicalPin32 { public static var a1: some AnalogPin { PhysicalPin32() } } -extension AnalogPin where Self == PhysicalPin34 { public static var a3: some AnalogPin { PhysicalPin34() } } - -extension RP2040 { - public struct AnyDigitalPin: DigitalPin { - public var rawValue: UInt32 - - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnyAnalogPin: AnalogPin { - public var rawValue: UInt32 - - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnyI2C0SDAPin: I2C0SDAPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnyI2C0SCLPin: I2C0SCLPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnyI2C1SDAPin: I2C1SDAPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnyI2C1SCLPin: I2C1SCLPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnySPI0SCKPin: SPI0SCKPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnySPI0TXPin: SPI0TXPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnySPI0RXPin: SPI0RXPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnySPI0CSPin: SPI0CSPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnySPI1SCKPin: SPI1SCKPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnySPI1TXPin: SPI1TXPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnySPI1RXPin: SPI1RXPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnySPI1CSPin: SPI1CSPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnyUART0TXPin: UART0TXPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnyUART0RXPin: UART0RXPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnyUART1TXPin: UART1TXPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - public struct AnyUART1RXPin: UART1RXPin { - public var rawValue: UInt32 - internal init(rawValue: UInt32) { - self.rawValue = rawValue - } - } - - - public func digital(pin: some DigitalPin) -> AnyDigitalPin { - AnyDigitalPin(rawValue: pin.rawValue) - } - - public func analog(pin: some AnalogPin) -> AnyAnalogPin { - AnyAnalogPin(rawValue: pin.rawValue) - } - - public func i2c0(sda pin: some I2C0SDAPin) -> AnyI2C0SDAPin { - AnyI2C0SDAPin(rawValue: pin.rawValue) - } - - public func i2c0(scl pin: some I2C0SCLPin) -> AnyI2C0SCLPin { - AnyI2C0SCLPin(rawValue: pin.rawValue) - } - - public func i2c1(sda pin: some I2C1SDAPin) -> AnyI2C1SDAPin { - AnyI2C1SDAPin(rawValue: pin.rawValue) - } - - public func i2c1SCL(scl pin: some I2C1SCLPin) -> AnyI2C1SCLPin { - AnyI2C1SCLPin(rawValue: pin.rawValue) - } - - public func spi0(sck pin: some SPI0SCKPin) -> AnySPI0SCKPin { - AnySPI0SCKPin(rawValue: pin.rawValue) - } - - public func spi0(tx pin: some SPI0TXPin) -> AnySPI0TXPin { - AnySPI0TXPin(rawValue: pin.rawValue) - } - - public func spi0(rx pin: some SPI0RXPin) -> AnySPI0RXPin { - AnySPI0RXPin(rawValue: pin.rawValue) - } - - public func spi0(cs pin: some SPI0CSPin) -> AnySPI0CSPin { - AnySPI0CSPin(rawValue: pin.rawValue) - } - - public func spi1(sck pin: some SPI1SCKPin) -> AnySPI1SCKPin { - AnySPI1SCKPin(rawValue: pin.rawValue) - } - - public func spi1(tx pin: some SPI1TXPin) -> AnySPI1TXPin { - AnySPI1TXPin(rawValue: pin.rawValue) - } - - public func spi1(rx pin: some SPI1RXPin) -> AnySPI1RXPin { - AnySPI1RXPin(rawValue: pin.rawValue) - } - - public func spi1(cs pin: some SPI1CSPin) -> AnySPI1CSPin { - AnySPI1CSPin(rawValue: pin.rawValue) - } - - public func uart0(tx pin: some UART0TXPin) -> AnyUART0TXPin { - AnyUART0TXPin(rawValue: pin.rawValue) - } - - public func uart0(rx pin: some UART0RXPin) -> AnyUART0RXPin { - AnyUART0RXPin(rawValue: pin.rawValue) - } - - public func uart1(tx pin: some UART1TXPin) -> AnyUART1TXPin { - AnyUART1TXPin(rawValue: pin.rawValue) - } - - public func uart1(rx pin: some UART1RXPin) -> AnyUART1RXPin { - AnyUART1RXPin(rawValue: pin.rawValue) - } -} diff --git a/rpi-pico-blink/Sources/RP2040/HAL/RP2040.swift b/rpi-pico-blink/Sources/RP2040/HAL/RP2040.swift deleted file mode 100644 index 772d6139..00000000 --- a/rpi-pico-blink/Sources/RP2040/HAL/RP2040.swift +++ /dev/null @@ -1,16 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -public struct RP2040 { - let hardware = RP2040Hardware() - - public init() {} -} diff --git a/rpi-pico-blink/Sources/RP2040/HAL/Time.swift b/rpi-pico-blink/Sources/RP2040/HAL/Time.swift deleted file mode 100644 index 7c1e5766..00000000 --- a/rpi-pico-blink/Sources/RP2040/HAL/Time.swift +++ /dev/null @@ -1,59 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import Support - -extension RP2040 { - var now: UInt64 { - var high = hardware.timer.awh - var low: UInt32 - repeat { - low = hardware.timer.awl - let nextHigh = hardware.timer.awh - if high == nextHigh { - break - } - high = nextHigh - } while true - return UInt64(high) << 32 | UInt64(low) - } - - public func sleep(forMicroseconds microseconds: UInt64) { - let start = now - let deadline = start + microseconds - - let highDeadline = UInt32(deadline >> 32) - let lowDeadline = UInt32(deadline & UInt64(UInt32.max)) - var high = hardware.timer.awh - - while high < highDeadline { - high = hardware.timer.awh - } - - while high == highDeadline && hardware.timer.awl < lowDeadline { - high = hardware.timer.awh - } - } - - public func sleep(forMilliseconds milliseconds: Int) { - for _ in 0.. 0 { - sleep(forMicroseconds: UInt64(microseconds)) - } - } -} diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/Clocks.swift b/rpi-pico-blink/Sources/RP2040/Hardware/Clocks.swift deleted file mode 100644 index 9425e645..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/Clocks.swift +++ /dev/null @@ -1,342 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -extension RP2040Hardware { - public var clocks: Clocks { - Clocks(unsafeAddress: 0x40008000) - } - - public struct Clocks { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var reference: Reference { - Reference(unsafeAddress: unsafeAddress) - } - - public struct Reference { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var control: Control { - Control(unsafeAddress: unsafeAddress + 0x0030) - } - - public struct Control { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public enum AuxiliarySource: UInt8 { - case clksrc_pll_usb = 0 - case clksrc_gpin0 = 1 - case clksrc_gpin1 = 2 - - init(decoding value: UInt32) { - self.init(rawValue: UInt8(value))! - } - - var encoded: UInt32 { - UInt32(rawValue) - } - } - - public var auxiliarySource: AuxiliarySource - - public enum Source: UInt8 { - case rosc_clksrc_ph = 0 - case clksrc_clk_ref_aux = 1 - case xosc_clksrc = 2 - - init(decoding value: UInt32) { - self.init(rawValue: UInt8(value))! - } - - var encoded: UInt32 { - UInt32(rawValue) - } - } - - public var source: Source - - init(decoding value: UInt32) { - auxiliarySource = AuxiliarySource(decoding: (value >> 5) & 0x3) - source = Source(decoding: (value >> 0) & 0x3) - } - - var encoded: UInt32 { - var value = UInt32(0) - value |= auxiliarySource.encoded << 5 - value |= source.encoded << 0 - return value - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress) - return result - } - - public func set(_ projection: Projection) { - RP2040Hardware.write(projection.encoded, to: unsafeAddress | RP2040Hardware.setAliasMask) - } - - public var value: Projection { - Projection(decoding: RP2040Hardware.read(UInt32.self, from: unsafeAddress)) - } - - public func clearSource() { - RP2040Hardware.write(UInt32(0x00000001), to: unsafeAddress | RP2040Hardware.clearAliasMask) - } - - public func clearReference() { - RP2040Hardware.write(UInt32(0x00000800), to: unsafeAddress | RP2040Hardware.clearAliasMask) - } - } - - public var divisor: Divisor { - Divisor(unsafeAddress: unsafeAddress + 0x0034) - } - - public struct Divisor { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public var integer: UInt32 - - init(decoding value: UInt32) { - integer = (value >> 8) & 0x3 - } - - var encoded: UInt32 { - var value = UInt32(0) - value |= (integer & 0x3) << 8 - return value - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress) - return result - } - - public func setRawValue(_ value: UInt32) { - RP2040Hardware.write(value, to: unsafeAddress) - } - } - - public var selected: Bool { - RP2040Hardware.read(UInt32.self, from: unsafeAddress + 0x0038) != 0 - } - } - - public var system: System { - System(unsafeAddress: unsafeAddress) - } - - public struct System { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var control: Control { - Control(unsafeAddress: unsafeAddress + 0x003c) - } - - public struct Control { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public enum AuxiliarySource: UInt8 { - case clksrc_pll_sys = 0 - case clksrc_pll_usb = 1 - case rosc_clksrc = 2 - case xosc_clksrc = 3 - case clksrc_gpin0 = 4 - case clksrc_gpin1 = 5 - - init(decoding value: UInt32) { - self.init(rawValue: UInt8(value))! - } - - var encoded: UInt32 { - UInt32(rawValue) - } - } - - public var auxiliarySource: AuxiliarySource - - public enum Source: UInt8 { - case clk_ref = 0 - case clksrc_clk_sys_aux = 1 - - init(decoding value: UInt32) { - self.init(rawValue: UInt8(value))! - } - - var encoded: UInt32 { - UInt32(rawValue) - } - } - - public var source: Source - - init(decoding value: UInt32) { - auxiliarySource = AuxiliarySource(decoding: (value >> 5) & 0x7) - source = Source(decoding: (value >> 0) & 0x3) - } - - var encoded: UInt32 { - var value = UInt32(0) - value |= auxiliarySource.encoded << 5 - value |= source.encoded << 0 - return value - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress) - return result - } - - public func set(_ projection: Projection) { - RP2040Hardware.write(projection.encoded, to: unsafeAddress | RP2040Hardware.setAliasMask) - } - - public var value: Projection { - Projection(decoding: RP2040Hardware.read(UInt32.self, from: unsafeAddress)) - } - - public func clearSource() { - RP2040Hardware.write(UInt32(0x00000001), to: unsafeAddress | RP2040Hardware.clearAliasMask) - } - } - - public var divisor: Divisor { - Divisor(unsafeAddress: unsafeAddress + 0x0040) - } - - public struct Divisor { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public var integer: UInt32 - public var fraction: UInt32 - - init(decoding value: UInt32) { - integer = (value >> 8) & 0xFFFFFF - fraction = (value >> 0) & 0xFF - } - - var encoded: UInt32 { - var value = UInt32(0) - value |= (integer & 0xFFFFFF) << 8 - value |= (fraction & 0xFF) << 0 - return value - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress) - return result - } - - public func setRawValue(_ value: UInt32) { - RP2040Hardware.write(value, to: unsafeAddress) - } - } - - public var selected: Bool { - RP2040Hardware.read(UInt32.self, from: unsafeAddress + 0x0044) != 0 - } - } - - public var resus: Resus { - Resus(unsafeAddress: unsafeAddress + 0x0038) - } - - public struct Resus { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public var clear: Bool - public var force: Bool - public var enable: Bool - public var timeout: UInt8 - - init(decoding value: UInt32) { - clear = (value >> 16) & 0x1 != 0 - force = (value >> 12) & 0x1 != 0 - enable = (value >> 8) & 0x1 != 0 - timeout = UInt8((value >> 0) & 0xFF) - } - - var encoded: UInt32 { - var value = UInt32(0) - value |= clear ? 1 << 16 : 0x0 - value |= force ? 1 << 12 : 0x0 - value |= enable ? 1 << 8 : 0x0 - value |= UInt32(timeout << 0) - return value - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress) - return result - } - } - } -} \ No newline at end of file diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/IOBank.swift b/rpi-pico-blink/Sources/RP2040/Hardware/IOBank.swift deleted file mode 100644 index 6feb7727..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/IOBank.swift +++ /dev/null @@ -1,170 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -extension RP2040Hardware { - public var ioBank0: IOBank { - IOBank(unsafeAddress: 0x40014000) - } - - public struct IOBank { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct GPIOControlList { - let unsafeAddress: UInt - let startOffset: UInt - let stride: UInt - let count: Int - init(unsafeAddress: UInt, startOffset: UInt, stride: UInt, count: Int) { - self.unsafeAddress = unsafeAddress - self.startOffset = startOffset - self.stride = stride - self.count = count - } - - public subscript(index: UInt32) -> GPIOControl { - precondition(index < count) - let addr = unsafeAddress + UInt(index) * stride + startOffset - return GPIOControl(unsafeAddress: addr) - } - } - - public var gpioControl: GPIOControlList { - GPIOControlList(unsafeAddress: unsafeAddress, startOffset: 0x0004, stride: 0x8, count: 30) - } - - public struct GPIOControl { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public enum IRQ: UInt32 { - case normal = 0 - case invert = 1 - case low = 2 - case high = 3 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x30000000) >> 28)! - } - - var encoded: UInt32 { - (self.rawValue << 28) & 0x30000000 - } - } - - public enum Input: UInt32 { - case normal = 0 - case inverted = 1 - case low = 2 - case high = 3 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x30000) >> 16)! - } - - var encoded: UInt32 { - (self.rawValue << 16) & 0x30000 - } - } - - public enum OutputEnable: UInt32 { - case normal = 0 - case inverted = 1 - case disabled = 2 - case enabled = 3 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x3000) >> 12)! - } - - var encoded: UInt32 { - (self.rawValue << 12) & 0x3000 - } - } - - public enum Output: UInt32 { - case normal = 0 - case inverted = 1 - case low = 2 - case high = 3 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x300) >> 8)! - } - - var encoded: UInt32 { - (self.rawValue << 8) & 0x300 - } - } - - public enum FuncSel: UInt32 { - case jtagTCK = 0 - case spiRx = 1 - case uart0Tx = 2 - case i20SDA = 3 - case pwmA0 = 4 - case sio0 = 5 - case pio0 = 6 - case pio1 = 7 - case usbMuxingOvercurrentDetect = 9 - case null = 31 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x1F) >> 0)! - } - - var encoded: UInt32 { - (self.rawValue << 0) & 0x1F - } - } - - public var irq: IRQ - public var input: Input - public var outputEnable: OutputEnable - public var output: Output - public var functionSelection: FuncSel - - init(decoding value: UInt32) { - irq = IRQ(decoding: value) - input = Input(decoding: value) - outputEnable = OutputEnable(decoding: value) - output = Output(decoding: value) - functionSelection = FuncSel(decoding: value) - } - - var encoded: UInt32 { - irq.encoded | - input.encoded | - outputEnable.encoded | - output.encoded | - functionSelection.encoded - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress) - return result - } - } - } -} diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/PLL.swift b/rpi-pico-blink/Sources/RP2040/Hardware/PLL.swift deleted file mode 100644 index 1b5ba639..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/PLL.swift +++ /dev/null @@ -1,87 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -extension RP2040Hardware { - public var pllSystem: PLL { - PLL(unsafeAddress: 0x40028000) - } - - public var pllUSB: PLL { - PLL(unsafeAddress: 0xe0000000) - } - - public struct PLL { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var status: Status { - Status(unsafeAddress: unsafeAddress + 0x0000) - } - - public struct Status { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public let locked: Bool - public var bypass: Bool - public var referenceDivide: UInt8 - - init(decoding value: UInt32) { - locked = (value >> 31) & 0x1 != 0 - bypass = (value >> 8) & 0x1 != 0 - referenceDivide = UInt8((value >> 0) & 0x3F) - } - - var encoded: UInt32 { - var value = UInt32(0) - value |= locked ? 1 << 31 : 0x0 - value |= bypass ? 1 << 8 : 0x0 - value |= UInt32(referenceDivide & 0x3F) << 0 - return value - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress | RP2040Hardware.setAliasMask) - return result - } - - public var value: Projection { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - return Projection(decoding: value) - } - } - - public var power: Power { - Power(unsafeAddress: unsafeAddress + 0x0004) - } - - public struct Power { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - } - } -} diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/PPB.swift b/rpi-pico-blink/Sources/RP2040/Hardware/PPB.swift deleted file mode 100644 index 0e69e986..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/PPB.swift +++ /dev/null @@ -1,71 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -extension RP2040Hardware { - public var ppb: PPB { - PPB(unsafeAddress: 0xe0000000) - } - - public struct PPB { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var cpuID: CPUID { - CPUID(unsafeAddress: unsafeAddress + 0xed00) - } - - public struct CPUID { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - } - - public var icsr: ICSR { - ICSR(unsafeAddress: unsafeAddress + 0xed04) - } - - public struct ICSR { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - } - - public var vtor: VTOR { - VTOR(unsafeAddress: unsafeAddress + 0xed08) - } - - public struct VTOR { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var tableOffset: UInt32 { - get { - RP2040Hardware.read(UInt32.self, from: unsafeAddress) - } - nonmutating set { - RP2040Hardware.write(newValue & 0xffffff00, to: unsafeAddress) - } - } - } - } -} \ No newline at end of file diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/PadsBank.swift b/rpi-pico-blink/Sources/RP2040/Hardware/PadsBank.swift deleted file mode 100644 index 74943258..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/PadsBank.swift +++ /dev/null @@ -1,307 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -extension RP2040Hardware { - public var padsBank0: PadsBank { - PadsBank(unsafeAddress: 0x4001c000) - } - - public struct PadsBank { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var voltageSelect: VoltageSelect { - VoltageSelect(unsafeAddress: unsafeAddress + 0x0000) - } - - public struct VoltageSelect { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public enum Value: UInt8 { - case voltage3_3 = 0 - case voltage1_8 = 1 - - init(decoding value: UInt32) { - self.init(rawValue: UInt8(value & (1 << 0)))! - } - - var encoded: UInt32 { - UInt32(self.rawValue) - } - } - - public var value: Value { - get { - Value(decoding: RP2040Hardware.read(UInt32.self, from: unsafeAddress)) - } - set { - RP2040Hardware.write(newValue.encoded, to: unsafeAddress) - } - } - } - - public struct GPIOList { - let unsafeAddress: UInt - let startOffset: UInt - let stride: UInt - let count: Int - init(unsafeAddress: UInt, startOffset: UInt, stride: UInt, count: Int) { - self.unsafeAddress = unsafeAddress - self.startOffset = startOffset - self.stride = stride - self.count = count - } - - public subscript(index: UInt32) -> GPIO { - precondition(index < count) - let addr = unsafeAddress + UInt(index) * stride + startOffset - return GPIO(unsafeAddress: addr) - } - } - - public var gpio: GPIOList { - GPIOList(unsafeAddress: unsafeAddress, startOffset: 0x4, stride: 0x4, count: 30) - } - - public struct GPIO { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public enum DriveStrength: UInt32 { - case level2mA = 0 - case level4mA = 1 - case level8mA = 2 - case level12mA = 3 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x30) >> 4)! - } - - var encoded: UInt32 { - (self.rawValue << 4) & 0x30 - } - } - public enum SlewRateControl: UInt32 { - case slow = 0 - case fast = 1 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x1) >> 0)! - } - - var encoded: UInt32 { - (self.rawValue << 0) & 0x1 - } - } - public var outputDisable: Bool - public var inputEnable: Bool - public var driveStrength: DriveStrength - public var pullUpEnable: Bool - public var pullDownEnable: Bool - public var schmittTriggerEnable: Bool - public var slewRateControl: SlewRateControl - - init(decoding value: UInt32) { - outputDisable = value & (1 << 7) != 0 - inputEnable = value & (1 << 6) != 0 - driveStrength = DriveStrength(decoding: value) - pullUpEnable = value & (1 << 3) != 0 - pullDownEnable = value & (1 << 2) != 0 - schmittTriggerEnable = value & (1 << 1) != 0 - slewRateControl = SlewRateControl(decoding: value) - } - - var encoded: UInt32 { - (outputDisable ? 1 << 7 : 0x0) | - (inputEnable ? 1 << 6 : 0x0) | - driveStrength.encoded | - (pullUpEnable ? 1 << 3 : 0x0) | - (pullDownEnable ? 1 << 2 : 0x0) | - (schmittTriggerEnable ? 1 << 1 : 0x0) | - slewRateControl.encoded - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress) - return result - } - } - - public var swclk: SWCLK { - SWCLK(unsafeAddress: unsafeAddress + 0x000000da) - } - - public struct SWCLK { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public enum DriveStrength: UInt32 { - case level2mA = 0 - case level4mA = 1 - case level8mA = 2 - case level12mA = 3 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x30) >> 4)! - } - - var encoded: UInt32 { - (self.rawValue << 4) & 0x30 - } - } - public enum SlewRateControl: UInt32 { - case slow = 0 - case fast = 1 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x1) >> 0)! - } - - var encoded: UInt32 { - (self.rawValue << 0) & 0x1 - } - } - public var outputDisable: Bool - public var inputEnable: Bool - public var driveStrength: DriveStrength - public var pullUpEnable: Bool - public var pullDownEnable: Bool - public var schmittTriggerEnable: Bool - public var slewRateControl: SlewRateControl - - init(decoding value: UInt32) { - outputDisable = value & (1 << 7) != 0 - inputEnable = value & (1 << 6) != 0 - driveStrength = DriveStrength(decoding: value) - pullUpEnable = value & (1 << 3) != 0 - pullDownEnable = value & (1 << 2) != 0 - schmittTriggerEnable = value & (1 << 1) != 0 - slewRateControl = SlewRateControl(decoding: value) - } - - var encoded: UInt32 { - (outputDisable ? 1 << 7 : 0x0) | - (inputEnable ? 1 << 6 : 0x0) | - driveStrength.encoded | - (pullUpEnable ? 1 << 3 : 0x0) | - (pullDownEnable ? 1 << 2 : 0x0) | - (schmittTriggerEnable ? 1 << 1 : 0x0) | - slewRateControl.encoded - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress) - return result - } - } - - public var swd: SWD { - SWD(unsafeAddress: unsafeAddress + 0x000000da) - } - - public struct SWD { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public enum DriveStrength: UInt32 { - case level2mA = 0 - case level4mA = 1 - case level8mA = 2 - case level12mA = 3 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x30) >> 4)! - } - - var encoded: UInt32 { - (self.rawValue << 4) & 0x30 - } - } - public enum SlewRateControl: UInt32 { - case slow = 0 - case fast = 1 - - init(decoding value: UInt32) { - self.init(rawValue: (value & 0x1) >> 0)! - } - - var encoded: UInt32 { - (self.rawValue << 0) & 0x1 - } - } - public var outputDisable: Bool - public var inputEnable: Bool - public var driveStrength: DriveStrength - public var pullUpEnable: Bool - public var pullDownEnable: Bool - public var schmittTriggerEnable: Bool - public var slewRateControl: SlewRateControl - - init(decoding value: UInt32) { - outputDisable = value & (1 << 7) != 0 - inputEnable = value & (1 << 6) != 0 - driveStrength = DriveStrength(decoding: value) - pullUpEnable = value & (1 << 3) != 0 - pullDownEnable = value & (1 << 2) != 0 - schmittTriggerEnable = value & (1 << 1) != 0 - slewRateControl = SlewRateControl(decoding: value) - } - - var encoded: UInt32 { - (outputDisable ? 1 << 7 : 0x0) | - (inputEnable ? 1 << 6 : 0x0) | - driveStrength.encoded | - (pullUpEnable ? 1 << 3 : 0x0) | - (pullDownEnable ? 1 << 2 : 0x0) | - (schmittTriggerEnable ? 1 << 1 : 0x0) | - slewRateControl.encoded - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress | RP2040Hardware.setAliasMask) - return result - } - } - } -} \ No newline at end of file diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/RP2040Hardware.swift b/rpi-pico-blink/Sources/RP2040/Hardware/RP2040Hardware.swift deleted file mode 100644 index fc7061ba..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/RP2040Hardware.swift +++ /dev/null @@ -1,229 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import Support - -public struct RP2040Hardware { - static var readWriteAliasMask: UInt { 0 << 12 } - static var xorAliasMask: UInt { 1 << 12 } - static var setAliasMask: UInt { 2 << 12 } - static var clearAliasMask: UInt { 3 << 12 } - - static var initialized = false - - public static var systemClockHz = UInt32(0) - public static var referenceClockHz = UInt32(0) - - public init() { - if !RP2040Hardware.initialized { - RP2040Hardware.initialized = true - resets.reset.set([ - .uart1, - .uart0, - .timer, - .tbman, - .sysinfo, - .spi1, - .spi0, - .rtc, - .pwm, - .pio1, - .pio0, - .pads_bank0, - .jtag, - .io_bank0, - .i2c1, - .i2c0, - .dma, - .busctrl, - .adc, - ]) - var value = Resets.ResetValue.all - value.remove([ - .adc, - .rtc, - .spi0, - .spi1, - .uart0, - .uart1, - .usbctrl, - ]) - resets.reset.clear(value) - - while !resets.resetDone.value.contains(value) {} - - initializeClocks() - - resets.reset.clear(.all) - padsBank0.gpio[26].modify { $0.inputEnable = false } - padsBank0.gpio[27].modify { $0.inputEnable = false } - padsBank0.gpio[28].modify { $0.inputEnable = false } - padsBank0.gpio[29].modify { $0.inputEnable = false } - } - - func initialize( - _ pll: PLL, vcoFrequency: UInt32, postDivisor1: UInt32, - postDivisor2: UInt32 - ) { - let referenceFrequency = UInt32(12000 * 1000) - - let fbdiv = vcoFrequency / referenceFrequency - - let pdiv = postDivisor1 << 16 | postDivisor2 << 12 - - let resetTarget: Resets.ResetValue = - pll.unsafeAddress == pllUSB.unsafeAddress ? .pll_usb : .pll_sys - resets.reset.set(resetTarget) - resets.reset.clear(resetTarget) - while !resets.resetDone.value.contains(resetTarget) {} - } - - func initializeClocks() { - let xoscKHz = UInt16(12000) - let usbClockKHz = UInt16(48000) - let systemClockKHz = UInt32(125000) - // this is technically hardware dependent (e.g. the adafruit feather has - // 64 here) - let multiplier = UInt16(1) - let freq1KHz = UInt16(1000) - - watchdog.tick.modify { - $0.cycles = xoscKHz / freq1KHz - $0.enabled = true - } - - clocks.resus.modify { - $0.clear = false - $0.force = false - $0.enable = false - $0.timeout = 0 - } - - while !xosc.status.value.stable {} - - clocks.system.control.clearSource() - while !clocks.system.selected {} - - clocks.reference.control.clearSource() - while !clocks.reference.selected {} - - initialize( - pllSystem, vcoFrequency: 1500 * 1000 * 1000, postDivisor1: 6, - postDivisor2: 2) - initialize( - pllUSB, vcoFrequency: 1200 * 1000 * 1000, postDivisor1: 5, - postDivisor2: 5) - - RP2040Hardware.referenceClockHz = clocks.reference.configure( - UInt32(xoscKHz) * UInt32(freq1KHz), UInt32(xoscKHz) * UInt32(freq1KHz)) - RP2040Hardware.systemClockHz = clocks.system.configure( - systemClockKHz * UInt32(freq1KHz), systemClockKHz * UInt32(freq1KHz)) - } - } - - static func read( - _ type: Bool.Type, from unsafeAddress: UInt, offset: UInt = 0, - bitMask: UInt32 = 0x0000_0001 - ) -> Bool { - read(UInt8.self, from: unsafeAddress, offset: offset, bitMask: bitMask) != 0 - } - - static func write(_ newValue: Bool, to unsafeAddress: UInt, offset: UInt = 0) - { - write(newValue ? UInt8(0x1) : UInt8(0x0), to: unsafeAddress, offset: offset) - } - - static func read( - _ type: UInt8.Type, from unsafeAddress: UInt, offset: UInt = 0, - bitMask: UInt32 = 0x0000_00FF - ) -> UInt8 { - // swift-format-ignore: NeverForceUnwrap - UInt8( - volatile_load_uint32_t( - UnsafeMutablePointer(bitPattern: unsafeAddress + offset)!) - & bitMask) - } - - static func write( - _ newValue: UInt8, to unsafeAddress: UInt, offset: UInt = 0, - bitMask: UInt32 = 0x0000_00FF - ) { - // swift-format-ignore: NeverForceUnwrap - volatile_store_uint32_t( - UnsafeMutablePointer(bitPattern: unsafeAddress + offset)!, - UInt32(newValue) & bitMask) - } - - static func read( - _ type: UInt16.Type, from unsafeAddress: UInt, offset: UInt = 0, - bitMask: UInt32 = 0x0000_FFFF - ) -> UInt16 { - // swift-format-ignore: NeverForceUnwrap - UInt16( - volatile_load_uint32_t( - UnsafeMutablePointer(bitPattern: unsafeAddress + offset)!) - & bitMask) - } - - static func write( - _ newValue: UInt16, to unsafeAddress: UInt, offset: UInt = 0 - ) { - // swift-format-ignore: NeverForceUnwrap - volatile_store_uint32_t( - UnsafeMutablePointer(bitPattern: unsafeAddress + offset)!, - UInt32(newValue)) - } - - static func read( - _ type: UInt32.Type, from unsafeAddress: UInt, offset: UInt = 0 - ) -> UInt32 { - // swift-format-ignore: NeverForceUnwrap - volatile_load_uint32_t( - UnsafeMutablePointer(bitPattern: unsafeAddress + offset)!) - } - - static func write( - _ newValue: UInt32, to unsafeAddress: UInt, offset: UInt = 0 - ) { - // swift-format-ignore: NeverForceUnwrap - volatile_store_uint32_t( - UnsafeMutablePointer(bitPattern: unsafeAddress + offset)!, - newValue) - } -} - -extension RP2040Hardware.Clocks.Reference { - func configure(_ sourceFrequency: UInt32, _ frequency: UInt32) -> UInt32 { - precondition(sourceFrequency >= frequency) - let div = UInt32((UInt64(sourceFrequency) << 8) / UInt64(frequency)) - control.clearReference() - control.modify { - $0.source = .xosc_clksrc - } - divisor.setRawValue(div) - return UInt32((UInt64(sourceFrequency) << 8) / UInt64(div)) - } -} - -extension RP2040Hardware.Clocks.System { - func configure(_ sourceFrequency: UInt32, _ frequency: UInt32) -> UInt32 { - precondition(sourceFrequency >= frequency) - let div = UInt32((UInt64(sourceFrequency) << 8) / UInt64(frequency)) - control.clearSource() - while !selected {} - control.modify { - $0.source = .clksrc_clk_sys_aux - $0.auxiliarySource = .xosc_clksrc - } - divisor.setRawValue(div) - return UInt32((UInt64(sourceFrequency) << 8) / UInt64(div)) - } -} diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/Resets.swift b/rpi-pico-blink/Sources/RP2040/Hardware/Resets.swift deleted file mode 100644 index 9e36d666..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/Resets.swift +++ /dev/null @@ -1,142 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -extension RP2040Hardware { - public var resets: Resets { - Resets(unsafeAddress: 0x4000c000) - } - - public struct Resets { - public struct ResetValue: OptionSet { - public var rawValue: UInt32 - - public init(rawValue: UInt32) { - self.rawValue = rawValue - } - - public init() { - self.init(rawValue: 0x0) - } - - public static var usbctrl: ResetValue { ResetValue(rawValue: 0x01000000) } - public static var uart1: ResetValue { ResetValue(rawValue: 0x00800000) } - public static var uart0: ResetValue { ResetValue(rawValue: 0x00400000) } - public static var timer: ResetValue { ResetValue(rawValue: 0x00200000) } - public static var tbman: ResetValue { ResetValue(rawValue: 0x00100000) } - public static var sysinfo: ResetValue { ResetValue(rawValue: 0x00080000) } - public static var syscfg: ResetValue { ResetValue(rawValue: 0x00040000) } - public static var spi1: ResetValue { ResetValue(rawValue: 0x00020000) } - public static var spi0: ResetValue { ResetValue(rawValue: 0x00010000) } - public static var rtc: ResetValue { ResetValue(rawValue: 0x00008000) } - public static var pwm: ResetValue { ResetValue(rawValue: 0x00004000) } - public static var pll_usb: ResetValue { ResetValue(rawValue: 0x00002000) } - public static var pll_sys: ResetValue { ResetValue(rawValue: 0x00001000) } - public static var pio1: ResetValue { ResetValue(rawValue: 0x00000800) } - public static var pio0: ResetValue { ResetValue(rawValue: 0x00000400) } - public static var pads_qspi: ResetValue { ResetValue(rawValue: 0x00000200) } - public static var pads_bank0: ResetValue { ResetValue(rawValue: 0x00000100) } - public static var jtag: ResetValue { ResetValue(rawValue: 0x00000080) } - public static var io_qspi: ResetValue { ResetValue(rawValue: 0x00000040) } - public static var io_bank0: ResetValue { ResetValue(rawValue: 0x00000020) } - public static var i2c1: ResetValue { ResetValue(rawValue: 0x00000010) } - public static var i2c0: ResetValue { ResetValue(rawValue: 0x00000008) } - public static var dma: ResetValue { ResetValue(rawValue: 0x00000004) } - public static var busctrl: ResetValue { ResetValue(rawValue: 0x00000002) } - public static var adc: ResetValue { ResetValue(rawValue: 0x00000001) } - - public static var all: ResetValue { - return [ - .usbctrl, - .uart1, - .uart0, - .timer, - .tbman, - .sysinfo, - .syscfg, - .spi1, - .spi0, - .rtc, - .pwm, - .pll_usb, - .pll_sys, - .pio1, - .pio0, - .pads_qspi, - .pads_bank0, - .jtag, - .io_qspi, - .io_bank0, - .i2c1, - .i2c0, - .dma, - .busctrl, - .adc - ] - } - } - - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var reset: Reset { - Reset(unsafeAddress: unsafeAddress + 0x0000) - } - - public var watchdogSelect: WatchdogSelect { - WatchdogSelect(unsafeAddress: unsafeAddress + 0x0004) - } - - public var resetDone: ResetDone { - ResetDone(unsafeAddress: unsafeAddress + 0x0008) - } - - public struct Reset { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public func set(_ value: ResetValue) { - RP2040Hardware.write(value.rawValue, to: unsafeAddress | RP2040Hardware.setAliasMask) - } - - public func clear(_ value: ResetValue) { - RP2040Hardware.write(value.rawValue, to: unsafeAddress | RP2040Hardware.clearAliasMask) - } - } - - public struct WatchdogSelect { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - } - - public struct ResetDone { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var value: ResetValue { - ResetValue(rawValue: RP2040Hardware.read(UInt32.self, from: unsafeAddress)) - } - } - } -} \ No newline at end of file diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/SIO.swift b/rpi-pico-blink/Sources/RP2040/Hardware/SIO.swift deleted file mode 100644 index a2ac0a00..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/SIO.swift +++ /dev/null @@ -1,42 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -extension RP2040Hardware { - public var sio: SIO { - SIO(unsafeAddress: 0xd0000000) - } - - public struct SIO { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public func setOutput(_ bits: UInt32) { - RP2040Hardware.write(bits & 0x3FFFFFFF, to: unsafeAddress, offset: 0x0014) - } - - public func clearOutput(_ bits: UInt32) { - RP2040Hardware.write(bits & 0x3FFFFFFF, to: unsafeAddress, offset: 0x0018) - } - - public func enableOutput(_ bits: UInt32) { - RP2040Hardware.write(bits & 0x3FFFFFFF, to: unsafeAddress, offset: 0x0024) - } - - public func disableOutput(_ bits: UInt32) { - RP2040Hardware.write(bits & 0x3FFFFFFF, to: unsafeAddress, offset: 0x0028) - } - } -} \ No newline at end of file diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/Timer.swift b/rpi-pico-blink/Sources/RP2040/Hardware/Timer.swift deleted file mode 100644 index 7ce6d2b6..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/Timer.swift +++ /dev/null @@ -1,34 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -extension RP2040Hardware { - public var timer: Timer { - Timer(unsafeAddress: 0x40054000) - } - - public struct Timer { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var awh: UInt32 { - RP2040Hardware.read(UInt32.self, from: unsafeAddress, offset: 0x0024) - } - - public var awl: UInt32 { - RP2040Hardware.read(UInt32.self, from: unsafeAddress, offset: 0x0028) - } - } -} \ No newline at end of file diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/Watchdog.swift b/rpi-pico-blink/Sources/RP2040/Hardware/Watchdog.swift deleted file mode 100644 index 567fa750..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/Watchdog.swift +++ /dev/null @@ -1,67 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -extension RP2040Hardware { - public var watchdog: Watchdog { - Watchdog(unsafeAddress: 0x40058000) - } - - public struct Watchdog { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var tick: Tick { - Tick(unsafeAddress: unsafeAddress + 0x002c) - } - - public struct Tick { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public var count: UInt16 - public var running: Bool - public var enabled: Bool - public var cycles: UInt16 - - init(decoding value: UInt32) { - count = UInt16((value & 0xFF800) >> 11) - running = value & (1 << 10) != 0 - enabled = value & (1 << 9) != 0 - cycles = UInt16((value & 0x1FF) >> 0) - } - - var encoded: UInt32 { - UInt32(count & 0x1FF) << 11 | - (running ? 1 << 10 : 0x0) | - (enabled ? 1 << 9 : 0x0) | - UInt32(cycles & 0x1FF) << 0 - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress) - return result - } - } - } -} \ No newline at end of file diff --git a/rpi-pico-blink/Sources/RP2040/Hardware/XOSC.swift b/rpi-pico-blink/Sources/RP2040/Hardware/XOSC.swift deleted file mode 100644 index 495cc6ae..00000000 --- a/rpi-pico-blink/Sources/RP2040/Hardware/XOSC.swift +++ /dev/null @@ -1,206 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -import Support - -extension RP2040Hardware { - public var xosc: XOSC { - XOSC(unsafeAddress: 0x40024000) - } - - public struct XOSC { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public var control: Control { - Control(unsafeAddress: unsafeAddress + 0x0000) - } - - public struct Control { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public enum Enable: UInt32 { - case enabled = 4011 - case disabled = 3358 - - init?(decoding value: UInt32) { - self.init(rawValue: value) - } - - var encoded: UInt32 { - self.rawValue - } - } - - public var enable: Enable? - - public enum FrequencyRange: UInt32 { - case oneToFifteenMHz = 0xaa0 - case reserved1 = 0xaa1 - case reserved2 = 0xaa2 - case reserved3 = 0xaa3 - case unknown = 0xfa5 // somehow this is a value? - - init(decoding value: UInt32) { - self.init(rawValue: value)! - } - - var encoded: UInt32 { - self.rawValue - } - } - - public var frequencyRange: FrequencyRange - - init(decoding value: UInt32) { - enable = Enable(decoding: (value >> 12) & 0xFFF) - frequencyRange = FrequencyRange(decoding: (value >> 0) & 0xFFF) - } - - var encoded: UInt32 { - var value = UInt32(0) - if let enable { - value |= enable.encoded << 12 - } - value |= frequencyRange.encoded << 0 - return value - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress) - return result - } - - public func set(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress | RP2040Hardware.setAliasMask) - return result - } - } - - public var status: Status { - Status(unsafeAddress: unsafeAddress + 0x0004) - } - - public struct Status { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public let stable: Bool - public var clearBadWrite: Bool - public let enabled: Bool - - public enum FrequencyRange: UInt32 { - case oneToFifteenMHz = 0 - case reserved1 = 1 - case reserved2 = 2 - case reserved3 = 3 - - init(decoding value: UInt32) { - self.init(rawValue: value)! - } - - var encoded: UInt32 { - self.rawValue - } - } - - public let frequencyRange: FrequencyRange - - init(decoding value: UInt32) { - stable = (value >> 31) & 0x1 != 0 - clearBadWrite = (value >> 24) & 0x1 != 0 - enabled = (value >> 12) & 0x1 != 0 - frequencyRange = FrequencyRange(decoding: (value >> 0) & 0x3) - } - - var encoded: UInt32 { - var value = UInt32(0) - value |= stable ? 1 << 31 : 0x0 - value |= clearBadWrite ? 1 << 24 : 0x0 - value |= enabled ? 1 << 12 : 0x0 - value |= frequencyRange.rawValue << 0 - return value - } - } - - public var value: Projection { - Projection(decoding: RP2040Hardware.read(UInt32.self, from: unsafeAddress)) - } - } - - public var dormant: UInt32 { - get { - RP2040Hardware.read(UInt32.self, from: unsafeAddress, offset: 0x0008) - } - set { - RP2040Hardware.write(newValue, to: unsafeAddress, offset: 0x0008) - } - } - - public var startup: Startup { - Startup(unsafeAddress: unsafeAddress + 0x000c) - } - - public struct Startup { - let unsafeAddress: UInt - - init(unsafeAddress: UInt) { - self.unsafeAddress = unsafeAddress - } - - public struct Projection { - public var x4: Bool - public var delay: UInt16 - - init(decoding value: UInt32) { - x4 = (value >> 20) & 0x1 != 0 - delay = UInt16((value >> 0) & 0x3FFF) - } - - var encoded: UInt32 { - var value = UInt32(0) - value |= x4 ? 1 << 20 : 0x0 - value |= UInt32(delay) << 0 - return value - } - } - - public func modify(_ apply: (inout Projection) -> T) -> T { - let value = RP2040Hardware.read(UInt32.self, from: unsafeAddress) - var projection = Projection(decoding: value) - let result = apply(&projection) - RP2040Hardware.write(projection.encoded, to: unsafeAddress | RP2040Hardware.setAliasMask) - return result - } - } - } -} \ No newline at end of file diff --git a/rpi-pico-blink/Sources/Support/Support.c b/rpi-pico-blink/Sources/Support/Support.c deleted file mode 100644 index 0ca75471..00000000 --- a/rpi-pico-blink/Sources/Support/Support.c +++ /dev/null @@ -1,41 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include -#include -#include - -#include "Support.h" - -extern int main(int argc, char *argv[]); - -void reset(void) { - int exit_code = main(0, NULL); - __builtin_trap(); -} - -void interrupt(void) { - while (1) {} -} - -__attribute((section("__DATA,stack"), aligned(32))) -char stack[0x800]; - -__attribute((used)) __attribute((section("__VECTORS,vectors"))) -void *vector_table[48] = { - (void *)(&stack[sizeof(stack)]), // initial SP - reset, // Reset - - interrupt, // NMI - interrupt, // HardFault - - 0 // NULL for all the other handlers -}; diff --git a/rpi-pico-blink/Sources/Support/crt0.S b/rpi-pico-blink/Sources/Support/crt0.S deleted file mode 100644 index 08456306..00000000 --- a/rpi-pico-blink/Sources/Support/crt0.S +++ /dev/null @@ -1,31 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - - .syntax unified - .thumb - .section __RESET,reset - .thumb_func - .global _entry_point - -_entry_point: - // Set VTOR (offset 0xed08 in Cortex-M0+ registers) to point to the vector table - ldr r0, =_vector_table - ldr r1, =(0xe0000000 + 0x0000ed08) - str r0, [r1] - - // Load the first two entries of the vector table, (1) r1 = initial SP, (2) r2 = reset function - ldmia r0!, {r1, r2} - - // Set stack pointer - msr msp, r1 - - // Transfer to reset function - bx r2 diff --git a/rpi-pico-blink/Sources/Support/include/Support.h b/rpi-pico-blink/Sources/Support/include/Support.h deleted file mode 100644 index 4b5e60ae..00000000 --- a/rpi-pico-blink/Sources/Support/include/Support.h +++ /dev/null @@ -1,44 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#pragma once - -#include - -#define VOLATILE_LOAD(type) \ - __attribute__((always_inline)) \ - static type volatile_load_##type(const volatile type * _Nonnull pointer) { return *pointer; } - -VOLATILE_LOAD(uint8_t); -VOLATILE_LOAD(uint16_t); -VOLATILE_LOAD(uint32_t); -VOLATILE_LOAD(uint64_t); - -#define VOLATILE_STORE(type) \ - __attribute__((always_inline)) \ - static void volatile_store_##type(volatile type * _Nonnull pointer, type value) { *pointer = value; } - -VOLATILE_STORE(uint8_t); -VOLATILE_STORE(uint16_t); -VOLATILE_STORE(uint32_t); -VOLATILE_STORE(uint64_t); - -static inline void busyWait(uint32_t cycles) { - asm( - "1: subs %0, #3\n" - "bcs 1b\n" - : "+l" (cycles) : : "memory" - ); -} - -static inline void nop(void) { - asm volatile("nop"); -} diff --git a/rpi-pico2-neopixel/.sourcekit-lsp/config.json b/rpi-pico2-neopixel/.sourcekit-lsp/config.json deleted file mode 100644 index 30e471b6..00000000 --- a/rpi-pico2-neopixel/.sourcekit-lsp/config.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "swiftPM": { - "configuration": "release" - } -} \ No newline at end of file diff --git a/rpi-pico2-neopixel/Makefile b/rpi-pico2-neopixel/Makefile deleted file mode 100644 index 448b28ce..00000000 --- a/rpi-pico2-neopixel/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -##===----------------------------------------------------------------------===## -## -## This source file is part of the Swift open source project -## -## Copyright (c) 2024 Apple Inc. and the Swift project authors. -## Licensed under Apache License v2.0 with Runtime Library Exception -## -## See https://swift.org/LICENSE.txt for license information -## -##===----------------------------------------------------------------------===## - -# Determine file paths -REPOROOT := $(shell git rev-parse --show-toplevel) -TOOLSROOT := $(REPOROOT)/Tools -TOOLSET := $(TOOLSROOT)/Toolsets/pico2.json -MACHO2UF2 := $(TOOLSROOT)/macho2uf2.py -SWIFT_BUILD := swift build - -# Setup tools and build flags -ARCH := armv7em -TARGET := $(ARCH)-apple-none-macho -SWIFT_BUILD_ARGS := \ - --configuration release \ - --triple $(TARGET) \ - --toolset $(TOOLSET) -BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) - -.PHONY: build -build: - @echo "building..." - $(SWIFT_BUILD) \ - $(SWIFT_BUILD_ARGS) \ - -Xlinker -map -Xlinker $(BUILDROOT)/Application.mangled.map \ - --verbose - - @echo "demangling linker map..." - cat $(BUILDROOT)/Application.mangled.map \ - | c++filt | swift demangle > $(BUILDROOT)/Application.map - - @echo "disassembling..." - otool \ - -arch $(ARCH) -v -V -d -t \ - $(BUILDROOT)/Application \ - | c++filt | swift demangle > $(BUILDROOT)/Application.disassembly - - @echo "extracting binary..." - $(MACHO2UF2) \ - $(BUILDROOT)/Application \ - $(BUILDROOT)/Application.uf2 \ - --pico-family rp2350 \ - --base-address 0x20000000 \ - --segments '__TEXT,__DATA,__VECTORS,__RESET' - -.PHONY: clean -clean: - @echo "cleaning..." - @swift package clean - @rm -rf .build diff --git a/rpi-pico2-neopixel/Package.resolved b/rpi-pico2-neopixel/Package.resolved deleted file mode 100644 index f76fcd9b..00000000 --- a/rpi-pico2-neopixel/Package.resolved +++ /dev/null @@ -1,33 +0,0 @@ -{ - "originHash" : "b2e24bf273e42b2971d4fabcbfa10a408d2817cd829c0ce45e1fc8e2e0aac421", - "pins" : [ - { - "identity" : "swift-argument-parser", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-argument-parser.git", - "state" : { - "revision" : "41982a3656a71c768319979febd796c6fd111d5c", - "version" : "1.5.0" - } - }, - { - "identity" : "swift-mmio", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-mmio.git", - "state" : { - "branch" : "main", - "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" - } - }, - { - "identity" : "swift-syntax", - "kind" : "remoteSourceControl", - "location" : "https://github.com/swiftlang/swift-syntax.git", - "state" : { - "revision" : "0687f71944021d616d34d922343dcef086855920", - "version" : "600.0.1" - } - } - ], - "version" : 3 -} diff --git a/rpi-pico2-neopixel/Package.swift b/rpi-pico2-neopixel/Package.swift deleted file mode 100644 index f06e7e6f..00000000 --- a/rpi-pico2-neopixel/Package.swift +++ /dev/null @@ -1,27 +0,0 @@ -// swift-tools-version: 6.0 - -import PackageDescription - -let package = Package( - name: "rpi-pico2-neopixel", - products: [ - .executable(name: "Application", targets: ["Application"]) - ], - dependencies: [ - .package(url: "https://github.com/apple/swift-mmio.git", branch: "main") - ], - targets: [ - .executableTarget( - name: "Application", - dependencies: ["RP2350", "Support"]), - .target( - name: "RP2350", - dependencies: [ - .product(name: "MMIO", package: "swift-mmio") - ], - plugins: [ - .plugin(name: "SVD2SwiftPlugin", package: "swift-mmio") - ]), - .target(name: "Support"), - ], - swiftLanguageModes: [.v5]) diff --git a/rpi-pico2-neopixel/README.md b/rpi-pico2-neopixel/README.md deleted file mode 100644 index f6225a76..00000000 --- a/rpi-pico2-neopixel/README.md +++ /dev/null @@ -1,43 +0,0 @@ -# rpi-pico2-neopixel - -An example project demonstrating how to drive a Neopixel RGB LED from an RP2350. - -![A SparkFun Pro Micro - RP2350 with its RGB LED glowing Red](assets/images/example.jpg) - -## Requirements - -- An RP2350 board, such as the "SparkFun Pro Micro - RP2350". - -## Configuring - -This example uses the hard coded constant `LED_PIN` in `Application.swift` to select the GPIO pin used to drive the attached Neopixel RGB LED. If you are using the "SparkFun Pro Micro - RP2350" no configuration is necessary, if you are using a different board you will need to adjust this constant to the pin used to drive your LED. - -Example diff: - -```diff -diff --git a/rpi-pico2-neopixel/Sources/Application/Application.swift b/rpi-pico2-neopixel/Sources/Application/Application.swift -index f6867b5..a2291db 100644 ---- a/rpi-pico2-neopixel/Sources/Application/Application.swift -+++ b/rpi-pico2-neopixel/Sources/Application/Application.swift -@@ -11,7 +11,7 @@ - - import RP2350 - --let LED_PIN: UInt32 = 25 -+let LED_PIN: UInt32 = 18 - - /// Configures GPIO pin as a front-end to PIO0. - func configure_output_pin() { -``` - -## How to build and run this example: - -- Connect the Pico2 board via a USB cable to your Mac, and make sure it's in the USB Mass Storage firmware upload mode (either hold the BOOTSEL button while plugging the board, or make sure your Flash memory doesn't contain any valid firmware). -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- Build and copy the program in the UF2 format to the Mass Storage device to trigger flashing the program into memory (after which the device will reboot and run the firmware): -``` console -$ cd rpi-pico2-neopixel -$ make -$ cp .build/release/Application.uf2 /Volumes/RP2350 -``` -- The RGB LED should be animating through the color wheel. diff --git a/rpi-pico2-neopixel/Sources/Application/Application.swift b/rpi-pico2-neopixel/Sources/Application/Application.swift deleted file mode 100644 index e19b197a..00000000 --- a/rpi-pico2-neopixel/Sources/Application/Application.swift +++ /dev/null @@ -1,171 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import RP2350 - -// swift-format-ignore: AlwaysUseLowerCamelCase -let LED_PIN: UInt32 = 25 - -/// Configures GPIO pin 25 as a front-end to PIO0. -func configureOutputPin() { - // Configure GPIO general properties - pads_bank0.gpio[LED_PIN].modify { rw in - rw.raw.od = 0 // Enable output - rw.raw.ie = 0 // Disable input - rw.raw.pue = 1 // Disable pull up - rw.raw.pde = 1 // Enable pull down - rw.raw.schmitt = 1 // Enable schmitt trigger - rw.raw.slewfast = 0 // Use slow slew rate - } - - // Configure GPIO function selection to use PIO0 - io_bank0.gpio[LED_PIN].gpio_ctrl.modify { rw in - rw.raw.funcsel = 0x6 // Forward output from pio0 to this pin - } - - // Remove pad isolation now that the correct peripheral is driving the pad - pads_bank0.gpio[LED_PIN].modify { rw in - rw.raw.iso = 0 // Disable isolation - } -} - -/// Configures PIO0 SM0 with a small program that drives WS2812 leds. -/// -/// This is not a general method to load PIO programs like is provided in the -/// pico-sdk. We assume no other programs are loaded into the state machine, as -/// a result we don't need to track program offsets and associated complexity. -/// -/// Additionally, this method doesn't reset any state in the PIO or state -/// machines. A more complete implementation will want to use `sm_reset` and -/// `clkdiv_restart` to clear any persisted state. -func configurePio() { - // Load the assembled program directly into the PIO's instruction memory. - withUnsafeBytes(of: WS2812.pioInstructions) { pointer in - let pioInstructions = pointer.assumingMemoryBound(to: UInt16.self) - for (index, pio_instr) in pioInstructions.enumerated() { - pio0.instr_mem[index].write { w in - w.raw.instr_mem0 = UInt32(pio_instr) - } - } - - // Configure the PIO program wrap boundaries. - pio0.sm[0].sm_execctrl.modify { r, w in - w.raw.wrap_bottom = 1 // Continue at 1 - w.raw.wrap_top = UInt32(pioInstructions.count - 1) // Wrap after last. - } - } - - // Setup the clock diver. - // - // From section 8.3.1. Ring Oscillator (ROSC) Overview - // > The Ring Oscillator (ROSC) ... provides the clock to the cores during - // > boot, ... the ROSC runs at a nominal 11MHz. - // - // Given the 11MHz input clock, the desired output frequency of 800KHz, and - // that each pio program cycle takes 10 cpu cycles. We can derive an - // approximate clock division factor. - // - // (11MHz) / (800KHz * 10) = 1.375 - // - // Mapping this to the integer register values: - // - // int: floor(1.375) = 1 - // frac: floor(0.375 * 255) = 95 - pio0.sm[0].sm_clkdiv.write { rw in - rw.raw.int = 1 - rw.raw.frac = 95 - } - - // Setup how the PIO state machine data pipeline. - // - // Use auto pull data from the txfifo into the OSR (output state register) - // every 24 bits. If no data is in the txfifo, the state machine will stall. - // Additional bond the RX TX fifos into one larger TX fifo so we can buffer - // more pixel data. - pio0.sm[0].sm_shiftctrl.modify { rw in - rw.raw.autopull = 1 // Enable autopull - rw.raw.pull_thresh = 24 // 24 bit pull threshold - rw.raw.out_shiftdir = 0 // Left shift from OSR - rw.raw.fjoin_tx = 1 // Join RX TX fifos - } - - // Setup the PIO state machine to output to the correct gpio pins. - pio0.sm[0].sm_pinctrl.modify { rw in - rw.raw.set_base = LED_PIN - rw.raw.set_count = 1 - rw.raw.sideset_base = LED_PIN - rw.raw.sideset_count = 1 - } - - // Start the state machine, it should immediately stall waiting for data in - // the txfifo. - pio0.ctrl.modify { _, w in - w.raw.sm_enable = 1 << 0 // Enable state machine 0 - } -} - -/// Writes an HSV8Pixel to the PIO TX fifo. -func pioWritePixel(_ hsv: HSV8Pixel) { - let rgb = RGB8Pixel(hsv) - - // Pixels need to be G R B 0 left to right. - let ws2812Value: UInt32 = - UInt32(rgb.green) << 24 | UInt32(rgb.red) << 16 | UInt32(rgb.blue) << 8 - - func txFifoFull() -> Bool { - pio0.fstat.read().raw.txfull & 0x1 != 0 - } - - // Wait for the TX fifo to have space before writing to it. - while txFifoFull() {} - - // Write the pixel value to TX fifo. - pio0.txf[0].write { w in - w.raw.txf0 = ws2812Value - } -} - -@main -struct Application { - static func main() { - // Take peripherals out of reset - resets.reset.modify { rw in - rw.raw.pio0 = 0 - rw.raw.pads_bank0 = 0 - rw.raw.io_bank0 = 0 - } - - var done = false - while !done { - let resetDone = resets.reset_done.read().raw - done = - resetDone.pio0 == 1 && resetDone.pads_bank0 == 1 - && resetDone.io_bank0 == 1 - } - - configureOutputPin() - configurePio() - - // Infinitely loop, cycling through colors. - var color = HSV8Pixel(hue: 0, saturation: .max, value: 64) - var x: UInt32 = 0 - while true { - // This is a poor excuse for writing pixel data at some frequency. Really - // this program should setup the system clocks at a chosen frequency and - // use the timer peripheral to sleep for N ms. - if x.isMultiple(of: 1 << 12) { - pioWritePixel(color) - color.hue &+= 1 - } - x &+= 1 - } - } -} diff --git a/rpi-pico2-neopixel/Sources/Application/HSV8Pixel.swift b/rpi-pico2-neopixel/Sources/Application/HSV8Pixel.swift deleted file mode 100644 index e13190e4..00000000 --- a/rpi-pico2-neopixel/Sources/Application/HSV8Pixel.swift +++ /dev/null @@ -1,16 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct HSV8Pixel { - var hue: UInt8 - var saturation: UInt8 - var value: UInt8 -} diff --git a/rpi-pico2-neopixel/Sources/Application/RGB8Pixel.swift b/rpi-pico2-neopixel/Sources/Application/RGB8Pixel.swift deleted file mode 100644 index e7c36b94..00000000 --- a/rpi-pico2-neopixel/Sources/Application/RGB8Pixel.swift +++ /dev/null @@ -1,75 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct RGB8Pixel { - var red: UInt8 - var green: UInt8 - var blue: UInt8 -} - -extension RGB8Pixel { - init(_ pixel: HSV8Pixel) { - // Fast path: gray scale. - guard pixel.saturation != 0 else { - self.red = pixel.value - self.green = pixel.value - self.blue = pixel.value - return - } - - // Slow path: compute each color component. - var hue = Float32(pixel.hue) / Float32(UInt8.max) - let saturation = Float32(pixel.saturation) / Float32(UInt8.max) - let value = Float32(pixel.value) / Float32(UInt8.max) - - let clampedHue = max(0, min(1 - .ulpOfOne, hue)) - let scaledHue = clampedHue * 6 - let sector = UInt8(scaledHue) - hue = scaledHue - Float32(sector) - - let fractionalChannel1 = value * (1.0 - (saturation * (1.0 - 0.0))) - let fractionalChannel2 = value * (1.0 - (saturation * (hue - 0.0))) - let fractionalChannel3 = value * (1.0 - (saturation * (1.0 - hue))) - - let channel1 = UInt8(fractionalChannel1 * Float32(UInt8.max)) - let channel2 = UInt8(fractionalChannel2 * Float32(UInt8.max)) - let channel3 = UInt8(fractionalChannel3 * Float32(UInt8.max)) - - switch sector { - case 0: - self.red = pixel.value - self.green = channel3 - self.blue = channel1 - case 1: - self.red = channel2 - self.green = pixel.value - self.blue = channel1 - case 2: - self.red = channel1 - self.green = pixel.value - self.blue = channel3 - case 3: - self.red = channel1 - self.green = channel2 - self.blue = pixel.value - case 4: - self.red = channel3 - self.green = channel1 - self.blue = pixel.value - case 5: - self.red = pixel.value - self.green = channel1 - self.blue = channel2 - default: - fatalError("Unreachable") - } - } -} diff --git a/rpi-pico2-neopixel/Sources/Application/WS2812.swift b/rpi-pico2-neopixel/Sources/Application/WS2812.swift deleted file mode 100644 index 7d1e86bc..00000000 --- a/rpi-pico2-neopixel/Sources/Application/WS2812.swift +++ /dev/null @@ -1,23 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -enum WS2812 { - // Precompiled PIO program using pioasm - static let pioInstructions: (UInt16, UInt16, UInt16, UInt16, UInt16) = ( - 0xe081, // 0: set pindirs, 1 side 0 - // .wrap_target - 0x6321, // 1: out x, 1 side 0 [3] - 0x1224, // 2: jmp !x, 4 side 1 [2] - 0x1201, // 3: jmp 1 side 1 [2] - 0xa242 // 4: nop side 0 [2] - // .wrap - ) -} diff --git a/rpi-pico2-neopixel/Sources/RP2350/Empty.swift b/rpi-pico2-neopixel/Sources/RP2350/Empty.swift deleted file mode 100644 index 934a795a..00000000 --- a/rpi-pico2-neopixel/Sources/RP2350/Empty.swift +++ /dev/null @@ -1,13 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// This file is intentionally left empty for SwiftPM to recognize the target as -// a Swift source module. diff --git a/rpi-pico2-neopixel/Sources/RP2350/rp235x.patched.svd b/rpi-pico2-neopixel/Sources/RP2350/rp235x.patched.svd deleted file mode 120000 index 3bb01c54..00000000 --- a/rpi-pico2-neopixel/Sources/RP2350/rp235x.patched.svd +++ /dev/null @@ -1 +0,0 @@ -../../../Tools/SVDs/rp235x.patched.svd \ No newline at end of file diff --git a/rpi-pico2-neopixel/Sources/RP2350/svd2swift.json b/rpi-pico2-neopixel/Sources/RP2350/svd2swift.json deleted file mode 100644 index c4dd705d..00000000 --- a/rpi-pico2-neopixel/Sources/RP2350/svd2swift.json +++ /dev/null @@ -1,9 +0,0 @@ -{ - "peripherals": [ - "PADS_BANK0", - "PIO0", - "IO_BANK0", - "RESETS" - ], - "access-level": "public" -} diff --git a/rpi-pico2-neopixel/Sources/Support/Support.c b/rpi-pico2-neopixel/Sources/Support/Support.c deleted file mode 100644 index 8cd3077e..00000000 --- a/rpi-pico2-neopixel/Sources/Support/Support.c +++ /dev/null @@ -1,72 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include -#include - -extern int main(int argc, char *argv[]); - -void enableFPU(void) { - uint32_t* cpacr = (uint32_t*)0xE000ED88; - // Read CPACR. - // Set bits 20-23 to enable CP10 and CP11 coprocessors. - // Write back the modified value to the CPACR. - *cpacr |= 0xF << 20; - // Wait for the coprocessors to become active. - asm volatile("dsb"); - asm volatile("isb"); -} - -void reset(void) { - enableFPU(); - int exit_code = main(0, NULL); - __builtin_trap(); -} - -void interrupt(void) { - while (1) {} -} - -__attribute((section("__DATA,stack"), aligned(32))) -char stack[0x1600]; - -__attribute((used)) __attribute((section("__VECTORS,vectors"))) -void *vector_table[73] = { - (void *)(&stack[sizeof(stack) - 4]), // initial SP - reset, // Reset - - interrupt, // NMI - interrupt, // HardFault - - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - interrupt, interrupt, interrupt, interrupt, - - // Minimal image per RP2350 datasheet - (void*)0xffffded3, // PICOBIN_BLOCK_MARKER_START - (void*)0x10210142, // item: PICOBIN_BLOCK_ITEM_1BS_IMAGE_TYPE - (void*)0x000001ff, // item: PICOBIN_BLOCK_ITEM_2BS_LAST - (void*)0x00000000, // link to self / "this is the last block" - (void*)0xab123579, // PICOBIN_BLOCK_MARKER_END -}; diff --git a/rpi-pico2-neopixel/Sources/Support/crt0.S b/rpi-pico2-neopixel/Sources/Support/crt0.S deleted file mode 100644 index f87c3eca..00000000 --- a/rpi-pico2-neopixel/Sources/Support/crt0.S +++ /dev/null @@ -1,31 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - - .syntax unified - .thumb - .section __RESET,reset - .thumb_func - .global _entry_point - -_entry_point: - // Set VTOR (offset 0xed08 in Cortex-M33F registers) to point to the vector table - ldr r0, =_vector_table - ldr r1, =(0xe0000000 + 0x0000ed08) - str r0, [r1] - - // Load the first two entries of the vector table, (1) r1 = initial SP, (2) r2 = reset function - ldmia r0!, {r1, r2} - - // Set stack pointer - msr msp, r1 - - // Transfer to reset function - bx r2 diff --git a/rpi-pico2-neopixel/Sources/Support/include/Support.h b/rpi-pico2-neopixel/Sources/Support/include/Support.h deleted file mode 100644 index 158cce06..00000000 --- a/rpi-pico2-neopixel/Sources/Support/include/Support.h +++ /dev/null @@ -1,12 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#pragma once diff --git a/rpi-pico2-neopixel/assets/images/example.jpg b/rpi-pico2-neopixel/assets/images/example.jpg deleted file mode 100644 index bbee6276..00000000 Binary files a/rpi-pico2-neopixel/assets/images/example.jpg and /dev/null differ diff --git a/rpi-picow-blink-sdk/BridgingHeader.h b/rpi-picow-blink-sdk/BridgingHeader.h deleted file mode 100644 index 69a2fec8..00000000 --- a/rpi-picow-blink-sdk/BridgingHeader.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#pragma once - -#include "pico/stdlib.h" -#include "pico/cyw43_arch.h" diff --git a/rpi-picow-blink-sdk/CMakeLists.txt b/rpi-picow-blink-sdk/CMakeLists.txt deleted file mode 100644 index 41cb7fcd..00000000 --- a/rpi-picow-blink-sdk/CMakeLists.txt +++ /dev/null @@ -1,97 +0,0 @@ -cmake_minimum_required(VERSION 3.29) -include($ENV{PICO_SDK_PATH}/external/pico_sdk_import.cmake) - -set(CMAKE_Swift_COMPILATION_MODE wholemodule) -set(CMAKE_Swift_COMPILER_WORKS YES) - -project(swift-blinky) -pico_sdk_init() -enable_language(Swift) - -add_executable(swift-blinky - # Source files: - Main.swift -) - -set_target_properties(swift-blinky PROPERTIES LINKER_LANGUAGE CXX) - -target_link_libraries(swift-blinky - pico_stdlib hardware_uart hardware_gpio pico_lwip_arch pico_cyw43_arch_none -) - -# Clear the default COMPILE_OPTIONS which include C specific compiler flags that the Swift compiler will not accept -# Instead, set those options to only apply when compiling C code. -set_target_properties(pico_standard_link PROPERTIES INTERFACE_COMPILE_OPTIONS "") -target_compile_options(pico_standard_link INTERFACE "$<$:SHELL: -ffunction-sections -fdata-sections>") - -# Gather C compile definitions from all dependencies -set_property(GLOBAL PROPERTY visited_targets "") -set_property(GLOBAL PROPERTY compilerdefs_list "") - -function(gather_compile_definitions_recursive target) - # Get the current value of visited_targets - get_property(visited_targets GLOBAL PROPERTY visited_targets) - - # make sure we don't visit the same target twice - # and that we don't visit the special generator expressions - if (${target} MATCHES "\\\$<" OR ${target} MATCHES "::@" OR ${target} IN_LIST visited_targets) - return() - endif() - - # Append the target to visited_targets - list(APPEND visited_targets ${target}) - set_property(GLOBAL PROPERTY visited_targets "${visited_targets}") - - get_target_property(target_definitions ${target} INTERFACE_COMPILE_DEFINITIONS) - if (target_definitions) - # Append the target definitions to compilerdefs_list - get_property(compilerdefs_list GLOBAL PROPERTY compilerdefs_list) - list(APPEND compilerdefs_list ${target_definitions}) - set_property(GLOBAL PROPERTY compilerdefs_list "${compilerdefs_list}") - endif() - - get_target_property(target_linked_libs ${target} INTERFACE_LINK_LIBRARIES) - if (target_linked_libs) - foreach(linked_target ${target_linked_libs}) - # Recursively gather compile definitions from dependencies - gather_compile_definitions_recursive(${linked_target}) - endforeach() - endif() -endfunction() - -gather_compile_definitions_recursive(swift-blinky) -get_property(COMPILE_DEFINITIONS GLOBAL PROPERTY compilerdefs_list) -get_property(INCLUDES GLOBAL PROPERTY includes_list) - -# Convert compiler definitions into a format that swiftc can understand -list(REMOVE_DUPLICATES COMPILE_DEFINITIONS) -list(PREPEND COMPILE_DEFINITIONS "") # adds a semicolon at the beginning -string(REPLACE "$" "$" COMPILE_DEFINITIONS "${COMPILE_DEFINITIONS}") -string(REPLACE ";" " -Xcc -D" COMPILE_DEFINITIONS "${COMPILE_DEFINITIONS}") - -# Compute -Xcc flags to set up the C and C++ header search paths for Swift (for bridging header). -set(IMPLICIT_INCLUDES) -foreach(dir ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES}) - string(CONCAT IMPLICIT_INCLUDES ${IMPLICIT_INCLUDES} "-Xcc ") - string(CONCAT IMPLICIT_INCLUDES ${IMPLICIT_INCLUDES} "-I${dir} ") -endforeach() -foreach(dir ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES}) - string(CONCAT IMPLICIT_INCLUDES ${IMPLICIT_INCLUDES} "-Xcc ") - string(CONCAT IMPLICIT_INCLUDES ${IMPLICIT_INCLUDES} "-I${dir} ") -endforeach() - -target_compile_options(swift-blinky PUBLIC - "$<$:SHELL: - -target armv6m-none-none-eabi - -enable-experimental-feature Embedded - -parse-as-library - -module-name swift_blinky - - -Xcc -fshort-enums - -Xfrontend -function-sections - -import-bridging-header ${CMAKE_CURRENT_LIST_DIR}/BridgingHeader.h - ${COMPILE_DEFINITIONS} - ${IMPLICIT_INCLUDES} - >") - -pico_add_extra_outputs(swift-blinky) diff --git a/rpi-picow-blink-sdk/Main.swift b/rpi-picow-blink-sdk/Main.swift deleted file mode 100644 index a60f13d3..00000000 --- a/rpi-picow-blink-sdk/Main.swift +++ /dev/null @@ -1,46 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -@main -struct Main { - static func main() { - let led = UInt32(CYW43_WL_GPIO_LED_PIN) - if cyw43_arch_init() != 0 { - print("Wi-Fi init failed") - return - } - let dot = { - cyw43_arch_gpio_put(led, true) - sleep_ms(250) - cyw43_arch_gpio_put(led, false) - sleep_ms(250) - } - let dash = { - cyw43_arch_gpio_put(led, true) - sleep_ms(500) - cyw43_arch_gpio_put(led, false) - sleep_ms(250) - } - while true { - dot() - dot() - dot() - - dash() - dash() - dash() - - dot() - dot() - dot() - } - } -} diff --git a/rpi-picow-blink-sdk/README.md b/rpi-picow-blink-sdk/README.md deleted file mode 100644 index 1b88c093..00000000 --- a/rpi-picow-blink-sdk/README.md +++ /dev/null @@ -1,41 +0,0 @@ -# rpi-picow-blink-sdk - -This example demonstrates how to integrate with the Pico SDK which is using CMake as its build system -- the simplest way to integrate with it is to also use CMake to build a Swift firmware application on top of the SDK and the libraries from it. - - - -## Requirements - -- A Raspberry Pi Pico W / Pico 2W board. If you have a Pico (non-W) instead, refer to the [rpi-pico-blink-sdk](../rpi-pico-blink-sdk) sample instead. -- Follow the setup steps at https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf, in particular you'll need: - - A checkout of the [pico-sdk](https://github.com/raspberrypi/pico-sdk.git), with git submodules checked out. - - A checkout of the [pico-examples](https://github.com/raspberrypi/pico-examples.git). - - CMake. - - The [Arm Embedded Toolchain](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads). -- Before trying to use Swift with the Pico SDK, make sure your environment works and can build the provided C/C++ sample projects, in particular: - - Try building and running the "blink" example from pico-examples written in C. - - -## Building - -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- Build and copy the program in the UF2 format to the Mass Storage device to trigger flashing the program into memory (after which the device will reboot and run the firmware): -``` console -$ cd rpi-picow-blink-sdk -$ export PICO_BOARD=pico_w # or pico2_w -$ export PICO_SDK_PATH='' -$ export PICO_TOOLCHAIN_PATH='' -$ cmake -B build -G Ninja . -DCMAKE_EXPORT_COMPILE_COMMANDS=On -$ cmake --build build -``` - -## Running - -- Connect the Pico W board via a USB cable to your Mac, and make sure it's in the USB Mass Storage firmware upload mode (either hold the BOOTSEL button while plugging the board, or make sure your Flash memory doesn't contain any valid firmware). -- Copy the UF2 firmware to the Mass Storage device: - -```console -$ cp build/swift-blinky.uf2 /Volumes/RP2040 # or /Volumes/RP2350 for Pico 2W -``` - -- The green LED should now be blinking in a pattern. diff --git a/rpi-picow-blink-sdk/include/lwipopts.h b/rpi-picow-blink-sdk/include/lwipopts.h deleted file mode 100644 index 94b02c4d..00000000 --- a/rpi-picow-blink-sdk/include/lwipopts.h +++ /dev/null @@ -1,18 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift.org open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// See https://swift.org/CONTRIBUTORS.txt for the list of Swift project authors -// -//===----------------------------------------------------------------------===// - -// Generally you would define your own explicit list of lwIP options -// (see https://www.nongnu.org/lwip/2_1_x/group__lwip__opts.html) - -#ifndef _LWIPOPTS_H -#define _LWIPOPTS_H -#endif diff --git a/stm32-blink/Board.swift b/stm32-blink/Board.swift deleted file mode 100644 index 130932e2..00000000 --- a/stm32-blink/Board.swift +++ /dev/null @@ -1,115 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#if STM32F746G_DISCOVERY - -typealias Board = STM32F746Board -enum STM32F746Board { - static func initialize() { - // (1) AHB1ENR[lecConfig.0] = 1 ... enable clock - setRegisterBit( - baseAddress: RCC.BaseAddress, offset: RCC.Offsets.AHB1ENR, - bit: RCC.AHB1ENRBit(for: ledConfig.0), - value: 1) - // (2) MODER[1] = 1 ... set mode to output - setRegisterTwoBitField( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.MODER, - bitsStartingAt: 2 * ledConfig.1, value: 1) - // (3) OTYPER[1] = 0 ... output type is push-pull - setRegisterBit( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.OTYPER, - bit: ledConfig.1, - value: 0) - // (4) OSPEEDR[1] = 2 ... speed is high - setRegisterTwoBitField( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.OSPEEDR, - bitsStartingAt: 2 * ledConfig.1, value: 2) - // (5) PUPDR[1] = 2 ... set pull to down - setRegisterTwoBitField( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.PUPDR, - bitsStartingAt: 2 * ledConfig.1, value: 2) - - ledOff() - } - - static func ledOn() { - // ODR[1] = 1 - setRegisterBit( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.ODR, bit: 1, - value: 1) - } - - static func ledOff() { - // ODR[1] = 0 - setRegisterBit( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.ODR, bit: 1, - value: 0) - } - - static func delay(milliseconds: Int) { - for _ in 0..<10_000 * milliseconds { - nop() - } - } -} - -#elseif NUCLEO_F103RB - -typealias Board = STM32F1Board -enum STM32F1Board { - static func initialize() { - // (1) APB2ENR[ledConfig.0] = 1 ... enable clock - setRegisterBit( - baseAddress: RCC.BaseAddress, offset: RCC.Offsets.APB2ENR, - bit: RCC.APB2ENRBit(for: ledConfig.0), - value: 1) - // (2) CRL.MODE[ledConfig.1] = 0b11 ... set mode to output, high speed - setRegisterTwoBitField( - baseAddress: GPIO.GPIOBaseAddress(for: ledConfig.0), - offset: GPIO.Offsets.CRL, - bitsStartingAt: 4 * ledConfig.1, value: 3) - // (3) CRL.CNF[ledConfig.1] = 0b00 ... general purpose, push-pull - setRegisterTwoBitField( - baseAddress: GPIO.GPIOBaseAddress(for: ledConfig.0), - offset: GPIO.Offsets.CRL, - bitsStartingAt: 4 * ledConfig.1 + 2, value: 0) - - ledOff() - } - - static func ledOn() { - // ODR[ledConfig.1] = 1 - setRegisterBit( - baseAddress: GPIO.GPIOBaseAddress(for: ledConfig.0), - offset: GPIO.Offsets.ODR, bit: ledConfig.1, - value: 1) - } - - static func ledOff() { - // ODR[ledConfig.1] = 0 - setRegisterBit( - baseAddress: GPIO.GPIOBaseAddress(for: ledConfig.0), - offset: GPIO.Offsets.ODR, bit: ledConfig.1, - value: 0) - } - - static func delay(milliseconds: Int) { - for _ in 0..<10_000 * milliseconds { - nop() - } - } -} - -#else - -#error("Unknown board") - -#endif diff --git a/stm32-blink/BridgingHeader.h b/stm32-blink/BridgingHeader.h deleted file mode 100644 index 6b807332..00000000 --- a/stm32-blink/BridgingHeader.h +++ /dev/null @@ -1,16 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#pragma once - -static inline __attribute((always_inline)) void nop() { - asm volatile("nop"); -} diff --git a/stm32-blink/Main.swift b/stm32-blink/Main.swift deleted file mode 100644 index 43d23858..00000000 --- a/stm32-blink/Main.swift +++ /dev/null @@ -1,42 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#if STM32F746G_DISCOVERY - -// I1 pin aka "Arduino D13" pin on STM32F746 Discovery Board -// https://www.st.com/resource/en/schematic_pack/mb1191-f746ngh6-c01_schematic.pdf -let ledConfig: (GPIOBank, GPIOPin) = (.i, 1) - -#elseif NUCLEO_F103RB - -// A5 pin aka "Arduino D13" pin on Nucleo-64 boards -// https://www.st.com/resource/en/user_manual/um1724-stm32-nucleo64-boards-mb1136-stmicroelectronics.pdf -let ledConfig: (GPIOBank, GPIOPin) = (.a, 5) - -#else - -#error("Unknown board") - -#endif - -@main -struct Main { - static func main() { - Board.initialize() - - while true { - Board.ledOn() - Board.delay(milliseconds: 100) - Board.ledOff() - Board.delay(milliseconds: 300) - } - } -} diff --git a/stm32-blink/README.md b/stm32-blink/README.md deleted file mode 100644 index 12797e03..00000000 --- a/stm32-blink/README.md +++ /dev/null @@ -1,56 +0,0 @@ -# stm32-blink - -This example shows a simple baremetal firmware for an STM32 board that blinks an LED repeatedly. The example does not use any vendor SDKs or external toolchains, the entire firmware is only built from code in this example directory. - - - -## Requirements - -- Connect the STM32F746G-DISCO board via the ST-LINK USB port to your Mac. -- Download and install a [recent nightly Swift toolchain](https://swift.org/download). Use the "Development Snapshot" from "main". -- Install the [`stlink`](https://github.com/stlink-org/stlink) command line tools, e.g. via `brew install stlink`. - -## Building and running the firmware as Mach-O on macOS - -- Build and upload the program to flash memory of the microcontroller: -```console -$ cd stm32-blink -$ export STM_BOARD=STM32F746G_DISCOVERY # or NUCLEO_F103RB -$ ./build-macho.sh -$ st-flash --reset write .build/blink.bin 0x08000000 -``` -- The green LED next to the RESET button should now be blinking in a pattern. - -## Building and running the firmware as ELF (on either macOS or Linux) - -- Build and upload the program to flash memory of the microcontroller: -```console -$ cd stm32-blink -$ export STM_BOARD=STM32F746G_DISCOVERY # or NUCLEO_F103RB -$ ./build-elf.sh -$ st-flash --format ihex --reset write .build/blink.hex -``` -- The green LED next to the RESET button should now be blinking in a pattern. - -## Binary size - -The resulting size of the compiled and linked binary is very small (which shouldn't be surprising given that this toy example only blinks an LED), and demonstrates how the Embedded Swift compilation mode doesn't include unnecessary code or data in the resulting program: - -```console -$ size -m .build/blink -Segment __TEXT: 656 - Section __text: 142 - total 142 -Segment __VECTORS: 456 - Section __text: 456 - total 456 -Segment __LINKEDIT: 188 -total 1300 -``` - -The binary contains only 142 bytes of code! Additionally, the vector table needed by the CPU is actually dominating the size of the final firmware. Note that the `__LINKEDIT` segment is discarded when forming the final `.bin` file, which is 1168 bytes in size: - -```console -$ cat .build/blink.bin | wc -c - 1168 -``` diff --git a/stm32-blink/Registers.swift b/stm32-blink/Registers.swift deleted file mode 100644 index ccbf13fb..00000000 --- a/stm32-blink/Registers.swift +++ /dev/null @@ -1,178 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -import _Volatile - -#if STM32F746G_DISCOVERY - -// Register definitions for STM32F746NG MCU -// https://www.st.com/resource/en/reference_manual/rm0385-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -enum GPIOBank: Int { - case a, b, c, d, e, f, g, h, i, j, k -} -typealias GPIOPin = Int - -enum RCC { - static let BaseAddress = UnsafeMutablePointer(bitPattern: 0x40023800 as UInt)! - enum Offsets { - static let AHB1ENR = 0x30 - } - enum Bits { - static let AHB1ENR_GPIOAEN = 0 - static let AHB1ENR_GPIOBEN = 1 - static let AHB1ENR_GPIOCEN = 2 - static let AHB1ENR_GPIODEN = 3 - static let AHB1ENR_GPIOEEN = 4 - static let AHB1ENR_GPIOFEN = 5 - static let AHB1ENR_GPIOGEN = 6 - static let AHB1ENR_GPIOHEN = 7 - static let AHB1ENR_GPIOIEN = 8 - static let AHB1ENR_GPIOJEN = 9 - static let AHB1ENR_GPIOKEN = 10 - } - - static func AHB1ENRBit(for bank: GPIOBank) -> Int { - return switch bank { - case .a: Bits.AHB1ENR_GPIOAEN - case .b: Bits.AHB1ENR_GPIOBEN - case .c: Bits.AHB1ENR_GPIOCEN - case .d: Bits.AHB1ENR_GPIODEN - case .e: Bits.AHB1ENR_GPIOEEN - case .f: Bits.AHB1ENR_GPIOFEN - case .g: Bits.AHB1ENR_GPIOGEN - case .h: Bits.AHB1ENR_GPIOHEN - case .i: Bits.AHB1ENR_GPIOIEN - case .j: Bits.AHB1ENR_GPIOJEN - case .k: Bits.AHB1ENR_GPIOKEN - } - } -} - -enum GPIO { - static let GPIOa_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40020000 as UInt)! - static let GPIOb_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40020400 as UInt)! - static let GPIOc_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40020800 as UInt)! - static let GPIOd_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40020c00 as UInt)! - static let GPIOe_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40021000 as UInt)! - static let GPIOf_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40021400 as UInt)! - static let GPIOg_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40021800 as UInt)! - static let GPIOh_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40021c00 as UInt)! - static let GPIOi_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40022000 as UInt)! - static let GPIOj_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40022400 as UInt)! - static let GPIOk_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40022800 as UInt)! - - enum Offsets { - static let MODER = 0x0 - static let OTYPER = 0x4 - static let OSPEEDR = 0x8 - static let PUPDR = 0xc - static let IDR = 0x10 - static let ODR = 0x14 - } -} - -#elseif NUCLEO_F103RB - -// Register definitions for STM32F103RB MCU -// https://www.st.com/resource/en/reference_manual/rm0008-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -enum GPIOBank: Int { - case a, b, c, d, e, f, g -} -typealias GPIOPin = Int - -enum RCC { - static let BaseAddress = UnsafeMutablePointer(bitPattern: 0x40021000 as UInt)! - enum Offsets { - static let APB2ENR = 0x18 - } - enum Bits { - static let APB2ENR_IOPAEN = 2 - static let APB2ENR_IOPBEN = 3 - static let APB2ENR_IOPCEN = 4 - static let APB2ENR_IOPDEN = 5 - static let APB2ENR_IOPEEN = 6 - static let APB2ENR_IOPFEN = 7 - static let APB2ENR_IOPGEN = 8 - } - - static func APB2ENRBit(for bank: GPIOBank) -> Int { - return switch bank { - case .a: Bits.APB2ENR_IOPAEN - case .b: Bits.APB2ENR_IOPBEN - case .c: Bits.APB2ENR_IOPCEN - case .d: Bits.APB2ENR_IOPDEN - case .e: Bits.APB2ENR_IOPEEN - case .f: Bits.APB2ENR_IOPFEN - case .g: Bits.APB2ENR_IOPGEN - } - } -} - -enum GPIO { - static let GPIOa_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40010800 as UInt)! - static let GPIOb_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40010c00 as UInt)! - static let GPIOc_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40011000 as UInt)! - static let GPIOd_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40011400 as UInt)! - static let GPIOe_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40011800 as UInt)! - static let GPIOf_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40011c00 as UInt)! - static let GPIOg_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40012000 as UInt)! - - static func GPIOBaseAddress(for bank: GPIOBank) -> UnsafeMutablePointer { - return switch bank { - case .a: GPIOa_BaseAddress - case .b: GPIOb_BaseAddress - case .c: GPIOc_BaseAddress - case .d: GPIOd_BaseAddress - case .e: GPIOe_BaseAddress - case .f: GPIOf_BaseAddress - case .g: GPIOg_BaseAddress - } - } - - enum Offsets { - static let CRL = 0x0 - static let CRH = 0x4 - static let IDR = 0x8 - static let ODR = 0xc - } -} - -#else - -#error("Unknown board") - -#endif - -func setRegisterBit(baseAddress: UnsafeMutablePointer, offset: Int, bit: Int, value: Int) { - precondition(offset % 4 == 0) - precondition(bit >= 0 && bit < 32) - precondition(value >= 0 && value < 2) - let p = baseAddress.advanced(by: offset / 4) - let m = VolatileMappedRegister(unsafeBitPattern: UInt(bitPattern: p)) - let previousValue: UInt32 = m.load() - let newValue: UInt32 = previousValue & ~(1 << UInt32(bit)) | (UInt32(value) << UInt32(bit)) - m.store(newValue) -} - -func setRegisterTwoBitField(baseAddress: UnsafeMutablePointer, offset: Int, bitsStartingAt: Int, value: Int) { - precondition(offset % 4 == 0) - precondition(bitsStartingAt >= 0 && bitsStartingAt < 31) - precondition(value >= 0 && value < 4) - let p = baseAddress.advanced(by: offset / 4) - let m = VolatileMappedRegister(unsafeBitPattern: UInt(bitPattern: p)) - let previousValue: UInt32 = m.load() - let newValue: UInt32 = previousValue & ~(0b11 << UInt32(bitsStartingAt)) | (UInt32(value) << UInt32(bitsStartingAt)) - m.store(newValue) -} diff --git a/stm32-blink/Startup.c b/stm32-blink/Startup.c deleted file mode 100644 index 9237afb1..00000000 --- a/stm32-blink/Startup.c +++ /dev/null @@ -1,44 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include -#include - -extern int main(int argc, char *argv[]); - -void reset(void) { - main(0, NULL); -} - -void interrupt(void) { - while (1) {} -} - -__attribute((used)) -#if defined(__ELF__) -__attribute((section(".vectors"))) -#elif defined(__MACH__) -__attribute((section("__VECTORS,__text"))) -#else -#error Unknown file format -#endif -void *vector_table[114] = { - (void *)0x20001ffc, // initial SP, assume we have 8 KB of SRAM - reset, // Reset - - interrupt, // NMI - interrupt, // HardFault - interrupt, // MemManage - interrupt, // BusFault - interrupt, // UsageFault - - 0 // NULL for all the other handlers -}; diff --git a/stm32-blink/build-elf.sh b/stm32-blink/build-elf.sh deleted file mode 100755 index afd9413e..00000000 --- a/stm32-blink/build-elf.sh +++ /dev/null @@ -1,52 +0,0 @@ -#!/bin/bash - -set -vex - -# Determine file paths -REPOROOT=$(realpath -- "$(dirname "${BASH_SOURCE[0]}")")/.. -TOOLSROOT="$REPOROOT/Tools" -SRCROOT="$REPOROOT/stm32-blink" -BUILDROOT="$SRCROOT/.build" - -# Clean the build directory -rm -r "$BUILDROOT" || true - -# Setup tools and build flags -TARGET=armv7em-none-none-eabi - -if [[ ! "$STM_BOARD" ]] ; then - echo "STM_BOARD must be set to STM32F746G_DISCOVERY or NUCLEO_F103RB" - exit 1 -fi - -SWIFT_EXEC=${SWIFT_EXEC:-$(which swiftc)} -SWIFT_FLAGS="-target $TARGET -Osize" -SWIFT_FLAGS+=" -import-bridging-header $SRCROOT/BridgingHeader.h -wmo -enable-experimental-feature Embedded" -SWIFT_FLAGS+=" -Xfrontend -function-sections -D${STM_BOARD}" - -CLANG_EXEC=${CLANG_EXEC:-$(which clang)} -CLANG_FLAGS="-target $TARGET -Oz" - -LD_EXEC=${LD_EXEC:-$CLANG_EXEC} -LD_FLAGS="-target $TARGET -fuse-ld=lld -nostdlib -static -Wl,-e,vector_table -Wl,--gc-sections -Wl,-T,$SRCROOT/elf-linkerscript.ld" - -# Create build directory -mkdir -p "$BUILDROOT" - -# Build Swift sources -# shellcheck disable=SC2086 # intentional splitting -"$SWIFT_EXEC" $SWIFT_FLAGS -c $SRCROOT/*.swift -o "$BUILDROOT/blink.o" - -# Build C sources -# shellcheck disable=SC2086 # intentional splitting -"$CLANG_EXEC" $CLANG_FLAGS -c "$SRCROOT/Startup.c" -o "$BUILDROOT/Startup.o" - -# Link objects into executable -# shellcheck disable=SC2086 # intentional splitting -"$LD_EXEC" $LD_FLAGS "$BUILDROOT/blink.o" "$BUILDROOT/Startup.o" -o "$BUILDROOT/blink.elf" - -# Convert to Intel HEX for flashing -"$TOOLSROOT"/elf2hex.py "$BUILDROOT/blink.elf" "$BUILDROOT/blink.hex" - -# Echo final binary path -ls -al "$BUILDROOT/blink.hex" diff --git a/stm32-blink/build-macho.sh b/stm32-blink/build-macho.sh deleted file mode 100755 index 7e9fa3d4..00000000 --- a/stm32-blink/build-macho.sh +++ /dev/null @@ -1,56 +0,0 @@ -#!/bin/bash - -set -vex - -# Determine file paths -REPOROOT=$(git rev-parse --show-toplevel) -TOOLSROOT="$REPOROOT/Tools" -SRCROOT="$REPOROOT/stm32-blink" -BUILDROOT="$SRCROOT/.build" - -# Clean the build directory -rm -r "$BUILDROOT" || true - -# Setup tools and build flags -TARGET=armv7em-apple-none-macho - -if [[ ! "$STM_BOARD" ]] ; then - echo "STM_BOARD must be set to STM32F746G_DISCOVERY or NUCLEO_F103RB" - exit 1 -fi - -SWIFT_EXEC=${SWIFT_EXEC:-$(xcrun -f swiftc)} -SWIFT_FLAGS="-target $TARGET -Osize" -SWIFT_FLAGS+=" -import-bridging-header $SRCROOT/BridgingHeader.h -wmo -enable-experimental-feature Embedded" -SWIFT_FLAGS+=" -Xcc -ffreestanding" -SWIFT_FLAGS+=" -D${STM_BOARD}" - -CLANG_EXEC=${CLANG_EXEC:-$(xcrun -f clang)} -CLANG_FLAGS="-target $TARGET -Oz" - -LD_EXEC=${LD_EXEC:-$CLANG_EXEC} -LD_FLAGS="-target $TARGET -nostdlib -static -Wl,-e,_reset -dead_strip -Wl,-no_zero_fill_sections -Wl,-segalign,4 -Wl,-segaddr,__VECTORS,0x08000000 -Wl,-seg1addr,0x08000200 -Wl,-pagezero_size,0" - -PYTHON_EXEC=${PYTHON_EXEC:-$(xcrun -f python3)} -MACHO2BIN="$TOOLSROOT/macho2bin.py" - -# Create build directory -mkdir -p "$BUILDROOT" - -# Build Swift sources -# shellcheck disable=SC2086 # intentional splitting -"$SWIFT_EXEC" $SWIFT_FLAGS -c "$SRCROOT/"*.swift -o "$BUILDROOT/blink.o" - -# Build C sources -# shellcheck disable=SC2086 # intentional splitting -"$CLANG_EXEC" $CLANG_FLAGS -c "$SRCROOT/Startup.c" -o "$BUILDROOT/Startup.o" - -# Link objects into executable -# shellcheck disable=SC2086 # intentional splitting -"$LD_EXEC" $LD_FLAGS "$BUILDROOT/blink.o" "$BUILDROOT/Startup.o" -o "$BUILDROOT/blink" - -# Extract sections from executable into flashable binary -"$PYTHON_EXEC" "$MACHO2BIN" "$BUILDROOT/blink" "$BUILDROOT/blink.bin" --base-address 0x08000000 --segments '__TEXT,__DATA,__VECTORS' - -# Echo final binary path -ls -al "$BUILDROOT/blink.bin" diff --git a/stm32-blink/elf-linkerscript.ld b/stm32-blink/elf-linkerscript.ld deleted file mode 100644 index 98d5f00a..00000000 --- a/stm32-blink/elf-linkerscript.ld +++ /dev/null @@ -1,13 +0,0 @@ -MEMORY -{ - flash : ORIGIN = 0x08000000, LENGTH = 32K - sram : ORIGIN = 0x20000000, LENGTH = 8K -} - -SECTIONS -{ - .text : { *(.vectors*) ; *(.text*) } > flash - .bss : { *(.bss*) } > sram - .data : { *(.data*) } > sram - /DISCARD/ : { *(.swift_modhash*) } -} diff --git a/stm32-lcd-logo/Makefile b/stm32-lcd-logo/Makefile deleted file mode 100644 index ae097811..00000000 --- a/stm32-lcd-logo/Makefile +++ /dev/null @@ -1,57 +0,0 @@ -##===----------------------------------------------------------------------===## -## -## This source file is part of the Swift open source project -## -## Copyright (c) 2023 Apple Inc. and the Swift project authors. -## Licensed under Apache License v2.0 with Runtime Library Exception -## -## See https://swift.org/LICENSE.txt for license information -## -##===----------------------------------------------------------------------===## - -# Paths -REPOROOT := $(shell git rev-parse --show-toplevel) -TOOLSROOT := $(REPOROOT)/Tools -TOOLSET := $(TOOLSROOT)/Toolsets/stm32f74x-lcd.json -MACHO2BIN := $(TOOLSROOT)/macho2bin.py -SWIFT_BUILD := swift build - -# Flags -ARCH := armv7em -TARGET := $(ARCH)-apple-none-macho -SWIFT_BUILD_ARGS := \ - --configuration release \ - --triple $(TARGET) \ - --toolset $(TOOLSET) -BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) - -.PHONY: build -build: - @echo "building..." - $(SWIFT_BUILD) \ - $(SWIFT_BUILD_ARGS) \ - -Xlinker -map -Xlinker $(BUILDROOT)/Application.mangled.map \ - --verbose - - @echo "demangling linker map..." - cat $(BUILDROOT)/Application.mangled.map \ - | c++filt | swift demangle > $(BUILDROOT)/Application.map - - @echo "disassembling..." - otool \ - -arch $(ARCH) -v -V -d -t \ - $(BUILDROOT)/Application \ - | c++filt | swift demangle > $(BUILDROOT)/Application.disassembly - - @echo "extracting binary..." - $(MACHO2BIN) \ - $(BUILDROOT)/Application \ - $(BUILDROOT)/Application.bin \ - --base-address 0x00200000 \ - --segments '__TEXT,__DATA,__VECTORS' - -.PHONY: clean -clean: - @echo "cleaning..." - @swift package clean - @rm -rf .build diff --git a/stm32-lcd-logo/Package.resolved b/stm32-lcd-logo/Package.resolved deleted file mode 100644 index f36366ea..00000000 --- a/stm32-lcd-logo/Package.resolved +++ /dev/null @@ -1,33 +0,0 @@ -{ - "originHash" : "0259de139c240d30a60426d7d7f2d119ccc92fffcb5377eccefe0c9a21e3ef9c", - "pins" : [ - { - "identity" : "swift-argument-parser", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-argument-parser.git", - "state" : { - "revision" : "41982a3656a71c768319979febd796c6fd111d5c", - "version" : "1.5.0" - } - }, - { - "identity" : "swift-mmio", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-mmio", - "state" : { - "branch" : "main", - "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" - } - }, - { - "identity" : "swift-syntax", - "kind" : "remoteSourceControl", - "location" : "https://github.com/swiftlang/swift-syntax.git", - "state" : { - "revision" : "0687f71944021d616d34d922343dcef086855920", - "version" : "600.0.1" - } - } - ], - "version" : 3 -} diff --git a/stm32-lcd-logo/Package.swift b/stm32-lcd-logo/Package.swift deleted file mode 100644 index 29041b56..00000000 --- a/stm32-lcd-logo/Package.swift +++ /dev/null @@ -1,38 +0,0 @@ -// swift-tools-version: 6.0 - -import PackageDescription - -let package = Package( - name: "stm32-lcd-logo", - products: [ - .executable(name: "Application", targets: ["Application"]) - ], - dependencies: [ - .package(url: "https://github.com/apple/swift-mmio", branch: "main") - ], - targets: [ - .executableTarget( - name: "Application", - dependencies: ["STM32F7X6", "Support"], - swiftSettings: [ - .enableExperimentalFeature("InlineArrayTypeSugar"), - .enableExperimentalFeature("SymbolLinkageMarkers"), - ]), - // SVD2Swift \ - // --input Sources/STM32F7X6/stm32f7x6.patched.svd \ - // --output Sources/STM32F7X6 \ - // --access-level public \ - // --indentation-width 2 \ - // --peripherals FLASH GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG GPIOH GPIOI GPIOJ GPIOK LTDC RCC - .target( - name: "STM32F7X6", - dependencies: [ - .product(name: "MMIO", package: "swift-mmio") - ], - plugins: [ - // Plugin disabled because SwiftPM is slow. - // .plugin(name: "SVD2SwiftPlugin", package: "swift-mmio") - ]), - .target(name: "Support"), - ], - swiftLanguageModes: [.v5]) diff --git a/stm32-lcd-logo/README.md b/stm32-lcd-logo/README.md deleted file mode 100644 index 764f5998..00000000 --- a/stm32-lcd-logo/README.md +++ /dev/null @@ -1,34 +0,0 @@ -# stm32-lcd-logo - - - -## How to build and run this example: - -- Connect the STM32F746G-DISCO board via the ST-LINK USB port to your Mac. -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- Install the `stlink` (https://github.com/stlink-org/stlink) command line tools, e.g. via `brew install stlink`. -- Build and upload the program to flash memory of the STM: -```console -$ cd stm32-lcd-logo -$ make -$ st-flash --reset write .build/lcd-logo.bin 0x08000000 -``` -- The LCD display on the board should now be showing a bouncing animating Swift logo on a fading background, and the user LED on should be blinking. - -Resulting size of the compiled and linked binary follows (3.5 kB of code + 10 kB of pixel data): -```console -$ size -m .build/lcd-logo -Segment __TEXT: 14376 - Section __text: 3604 - Section __const: 10000 - total 13604 -Segment __DATA: 8 - Section __nl_symbol_ptr: 4 - Section __data: 4 - total 8 -Segment __VECTORS: 456 - Section __text: 456 - total 456 -Segment __LINKEDIT: 1056 -total 15896 -``` diff --git a/stm32-lcd-logo/Sources/Application/Application.swift b/stm32-lcd-logo/Sources/Application/Application.swift deleted file mode 100644 index d6ab1f67..00000000 --- a/stm32-lcd-logo/Sources/Application/Application.swift +++ /dev/null @@ -1,80 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import STM32F7X6 -import Support - -@main -struct Application { - static let logoSize = Size( - width: LTDC.Constants.layerWidth, - height: LTDC.Constants.layerHeight) - static let displaySize = Size( - width: LTDC.Constants.displayWidth, - height: LTDC.Constants.displayHeight) - static let maxLogoPosition = Point( - x: Self.displaySize.width - Self.logoSize.width, - y: Self.displaySize.height - Self.logoSize.height) - - static func main() { - // FIXME: remove sleep hack for some bug in clock configuration - Self.delay(milliseconds: 1) - configureFlash() - initializeLTCD() - ltdc.configure() - - var logoPosition = Point(x: 100, y: 100) - var logoDelta = Point(x: 1, y: 1) - var backgroundGray: UInt8 = .min - var backgroundDelta: Int8 = -1 - - while true { - Self.delay(milliseconds: 10) - - if logoPosition.x <= 0 || logoPosition.x >= maxLogoPosition.x { - logoDelta.x *= -1 - } - if logoPosition.y <= 0 || logoPosition.y >= maxLogoPosition.y { - logoDelta.y *= -1 - } - logoPosition = logoPosition.offset(by: logoDelta) - ltdc.set(layer: 1, position: logoPosition) - - if backgroundGray == .min || backgroundGray == .max { - backgroundDelta *= -1 - } - backgroundGray = UInt8(Int16(backgroundGray) + Int16(backgroundDelta)) - ltdc.set(backgroundColor: .gray(backgroundGray)) - } - } - - static func delay(milliseconds: Int) { - for _ in 0..<100_000 * milliseconds { - nop() - } - } - - static func configureFlash() { - flash.acr.modify { $0.latency = .WS5 } - } - - static func initializeLTCD() { - rcc.cfgr.write { $0.raw.storage = 0 } - rcc.cr.modify { r, w in - w.hsion = .On - w.csson = .Off - w.raw.hseon = 1 - w.raw.pllon = 0 - w.raw.hsebyp = 0 - } - while rcc.cr.read().raw.hserdy == 0 {} - } -} diff --git a/stm32-lcd-logo/Sources/Application/Geometry/Color.swift b/stm32-lcd-logo/Sources/Application/Geometry/Color.swift deleted file mode 100644 index c553d8f2..00000000 --- a/stm32-lcd-logo/Sources/Application/Geometry/Color.swift +++ /dev/null @@ -1,18 +0,0 @@ -// -// Color.swift -// stm32-lcd-logo -// -// Created by Rauhul Varma on 3/12/25. -// - -struct Color { - var red: UInt8 - var green: UInt8 - var blue: UInt8 -} - -extension Color { - static func gray(_ value: UInt8) -> Color { - Color(red: value, green: value, blue: value) - } -} diff --git a/stm32-lcd-logo/Sources/Application/Geometry/Point.swift b/stm32-lcd-logo/Sources/Application/Geometry/Point.swift deleted file mode 100644 index 7f3a9944..00000000 --- a/stm32-lcd-logo/Sources/Application/Geometry/Point.swift +++ /dev/null @@ -1,15 +0,0 @@ -// -// Point.swift -// stm32-lcd-logo -// -// Created by Rauhul Varma on 3/12/25. -// - -struct Point { - var x: Int - var y: Int - - func offset(by: Point) -> Point { - Point(x: x + by.x, y: y + by.y) - } -} diff --git a/stm32-lcd-logo/Sources/Application/Geometry/Size.swift b/stm32-lcd-logo/Sources/Application/Geometry/Size.swift deleted file mode 100644 index 30688054..00000000 --- a/stm32-lcd-logo/Sources/Application/Geometry/Size.swift +++ /dev/null @@ -1,11 +0,0 @@ -// -// Size.swift -// stm32-lcd-logo -// -// Created by Rauhul Varma on 3/12/25. -// - -struct Size { - var width: Int - var height: Int -} diff --git a/stm32-lcd-logo/Sources/Application/HAL/GPIOA+Helpers.swift b/stm32-lcd-logo/Sources/Application/HAL/GPIOA+Helpers.swift deleted file mode 100644 index c6e978e1..00000000 --- a/stm32-lcd-logo/Sources/Application/HAL/GPIOA+Helpers.swift +++ /dev/null @@ -1,124 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import STM32F7X6 - -extension GPIOA { - public enum Port: Int { - case a, b, c, d, e, f, g, h, i, j, k - } - - enum Mode: UInt32 { - case input = 0x0 - case output = 0x1 - case alternateFunction = 0x2 - case analog = 0x3 - } - - enum OutputType: UInt32 { - case pushPull = 0x0 - case openDrain = 0x1 - } - - enum OutputSpeed: UInt32 { - case low = 0x0 - case medium = 0x1 - case high = 0x2 - case max = 0x3 - } - - enum Pull: UInt32 { - case `none` = 0x0 - case up = 0x1 - case down = 0x2 - } - - struct Configuration { - var mode: Mode - var outputType: OutputType - var outputSpeed: OutputSpeed - var pull: Pull - var alternateFunction: UInt32 - } - - func configure(pin: Int, as configuration: Configuration) { - self.moder.modify { rw in - rw.raw.storage.set( - value: configuration.mode.rawValue, - mask: 0b11, - offset: pin * 2) - } - - // Comprised of 16 x 1 bit fields. - self.otyper.modify { rw in - rw.raw.storage.set( - value: configuration.outputType.rawValue, - mask: 0b1, - offset: pin) - } - - // Comprised of 16 x 2 bit fields. - self.ospeedr.modify { rw in - rw.raw.storage.set( - value: configuration.outputSpeed.rawValue, - mask: 0b11, - offset: pin * 2) - } - - // Comprised of 16 x 2 bit fields. - self.pupdr.modify { rw in - rw.raw.storage.set( - value: configuration.pull.rawValue, - mask: 0b11, - offset: pin * 2) - } - - // Comprised of 16 x 4 bit fields, split across 2 registers. - if pin < 8 { - self.afrl.modify { rw in - rw.raw.storage.set( - value: configuration.alternateFunction, - mask: 0b1111, - offset: pin * 4) - } - } else { - self.afrh.modify { rw in - rw.raw.storage.set( - value: configuration.alternateFunction, - mask: 0b1111, - offset: (pin - 8) * 4) - } - } - } - - func set(pin: Int, to value: Bool) { - // Lower 16 bits are set, upper 16 bits are reset. - if value { - self.bsrr.write { $0.raw.storage = 1 << pin } - } else { - self.bsrr.write { $0.raw.storage = 1 << (pin + 16) } - } - } -} - -extension UInt32 { - fileprivate func get(mask: Self, offset: UInt8) -> Self { - let mask = mask &<< offset - return (self & mask) &>> offset - } - - fileprivate mutating func set(value: Self, mask: Self, offset: Int) { - let mask = mask &<< offset - let oldValue: UInt32 = self & ~mask - let newValue: UInt32 = (value &<< offset) & mask - self = oldValue | newValue - } -} diff --git a/stm32-lcd-logo/Sources/Application/HAL/LTDC+Helpers.swift b/stm32-lcd-logo/Sources/Application/HAL/LTDC+Helpers.swift deleted file mode 100644 index 22c400bd..00000000 --- a/stm32-lcd-logo/Sources/Application/HAL/LTDC+Helpers.swift +++ /dev/null @@ -1,654 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import STM32F7X6 -import Support - -extension LTDC { - enum Constants { - static let hsync = 30 - static let vsync = 10 - static let hbp = 13 - static let hfp = 32 - static let vbp = 2 - static let vfp = 2 - - static let pixelSize = 4 - - static let displayWidth = 480 - static let displayHeight = 272 - - static let layerWidth = 50 - static let layerHeight = 50 - } - - func configure() { - rcc.pllcfgr.write { - $0.raw.pllm = 25 - $0.raw.plln = 432 - $0.pllsrc = .HSE - } - - rcc.cr.modify { $1.raw.pllon = 1 } - while rcc.cr.read().raw.pllrdy != 1 {} - - // FIXME: use named fields - rcc.cfgr.modify { - $0.raw.storage &= 0b11 - $0.raw.storage |= 0b10 - } - while rcc.cfgr.read().raw.storage & 0b1100 != 0b1000 {} - - rcc.pllsaicfgr.modify { - $0.raw.pllsain = 192 - $0.raw.pllsair = 5 - } - rcc.dckcfgr1.modify { $0.pllsaidivr = .Div4 } - - rcc.cr.modify { $1.raw.pllsaion = 1 } - while rcc.cr.read().raw.pllsairdy != 1 {} - - rcc.enableGPIOPortClock(.a) - rcc.enableGPIOPortClock(.b) - rcc.enableGPIOPortClock(.c) - rcc.enableGPIOPortClock(.d) - rcc.enableGPIOPortClock(.e) - rcc.enableGPIOPortClock(.f) - rcc.enableGPIOPortClock(.g) - rcc.enableGPIOPortClock(.h) - rcc.enableGPIOPortClock(.i) - rcc.enableGPIOPortClock(.j) - rcc.enableGPIOPortClock(.k) - - let pinConfiguration = GPIOA.Configuration( - mode: .alternateFunction, - outputType: .pushPull, - outputSpeed: .high, - pull: .none, - alternateFunction: 14) - - let clkPin = 14 - let dePin = 7 - let hsyncPin = 10 - let vsyncPin = 9 - - gpioi.configure(pin: clkPin, as: pinConfiguration) - gpiok.configure(pin: dePin, as: pinConfiguration) - gpioi.configure(pin: hsyncPin, as: pinConfiguration) - gpioi.configure(pin: vsyncPin, as: pinConfiguration) - - let r0Pin = 15 - let r1Pin = 0 - let r2Pin = 1 - let r3Pin = 2 - let r4Pin = 3 - let r5Pin = 4 - let r6Pin = 5 - let r7Pin = 6 - - gpioi.configure(pin: r0Pin, as: pinConfiguration) - gpioj.configure(pin: r1Pin, as: pinConfiguration) - gpioj.configure(pin: r2Pin, as: pinConfiguration) - gpioj.configure(pin: r3Pin, as: pinConfiguration) - gpioj.configure(pin: r4Pin, as: pinConfiguration) - gpioj.configure(pin: r5Pin, as: pinConfiguration) - gpioj.configure(pin: r6Pin, as: pinConfiguration) - gpioj.configure(pin: r7Pin, as: pinConfiguration) - - let g0Pin = 7 - let g1Pin = 8 - let g2Pin = 9 - let g3Pin = 10 - let g4Pin = 11 - let g5Pin = 0 - let g6Pin = 1 - let g7Pin = 2 - - gpioj.configure(pin: g0Pin, as: pinConfiguration) - gpioj.configure(pin: g1Pin, as: pinConfiguration) - gpioj.configure(pin: g2Pin, as: pinConfiguration) - gpioj.configure(pin: g3Pin, as: pinConfiguration) - gpioj.configure(pin: g4Pin, as: pinConfiguration) - gpiok.configure(pin: g5Pin, as: pinConfiguration) - gpiok.configure(pin: g6Pin, as: pinConfiguration) - gpiok.configure(pin: g7Pin, as: pinConfiguration) - - let b0Pin = 4 - let b1Pin = 13 - let b2Pin = 14 - let b3Pin = 15 - let b4Pin = 12 - let b5Pin = 4 - let b6Pin = 5 - let b7Pin = 6 - - gpioe.configure(pin: b0Pin, as: pinConfiguration) - gpioj.configure(pin: b1Pin, as: pinConfiguration) - gpioj.configure(pin: b2Pin, as: pinConfiguration) - gpioj.configure(pin: b3Pin, as: pinConfiguration) - gpiog.configure(pin: b4Pin, as: pinConfiguration) - gpiok.configure(pin: b5Pin, as: pinConfiguration) - gpiok.configure(pin: b6Pin, as: pinConfiguration) - gpiok.configure(pin: b7Pin, as: pinConfiguration) - - let lcdPinConfiguration = GPIOA.Configuration( - mode: .output, - outputType: .pushPull, - outputSpeed: .low, - pull: .down, - alternateFunction: 0) - - let backlightPin = 3 - let lcdDispPin = 12 - - gpiok.configure(pin: backlightPin, as: lcdPinConfiguration) - gpioi.configure(pin: lcdDispPin, as: lcdPinConfiguration) - - gpioi.set(pin: lcdDispPin, to: true) - gpiok.set(pin: backlightPin, to: true) - - rcc.apb2enr.modify { $0.raw.ltdcen = 1 } - - self.sscr.modify { $0.raw.vsh = UInt32(Constants.vsync - 1) } - self.sscr.modify { $0.raw.hsw = UInt32(Constants.hsync - 1) } - self.bpcr.modify { - $0.raw.ahbp = UInt32(Constants.hsync + Constants.hbp - 1) - } - self.bpcr.modify { - $0.raw.avbp = UInt32(Constants.vsync + Constants.vbp - 1) - } - self.awcr.modify { - $0.raw.aah = UInt32( - Constants.displayHeight + Constants.vsync + Constants.vbp - 1) - } - self.awcr.modify { - $0.raw.aaw = UInt32( - Constants.displayWidth + Constants.hsync + Constants.hbp - 1) - } - self.twcr.modify { - $0.raw.totalw = UInt32( - Constants.displayWidth + Constants.hsync + Constants.hbp + Constants.hfp - - 1) - } - self.twcr.modify { - $0.raw.totalh = UInt32( - Constants.displayHeight + Constants.vsync + Constants.vbp - + Constants.vfp - 1) - } - - self.layer[1].pfcr.modify { $0.raw.storage = 0 } // Format ARGB8888 - - // FIXME: Escaping a pointer like this is very unsafe. - // We get away with it because `pixelData` is a global let. - pixelData.span.withUnsafeBytes { buffer in - // swift-format-ignore: NeverForceUnwrap - let data = UInt32(UInt(bitPattern: buffer.baseAddress!)) - self.layer[1].cfbar.modify { $0.raw.storage = data } - } - self.layer[1].cacr.modify { $0.raw.consta = 255 } - self.layer[1].bfcr.modify { $0.raw.bf1 = 5 } - self.layer[1].bfcr.modify { $0.raw.bf2 = 4 } - self.layer[1].cfblr.modify { - $0.raw.storage = - UInt32(UInt32(Constants.pixelSize * Constants.layerWidth) << 16) - | UInt32(Constants.pixelSize * Constants.layerWidth + 3) - } - self.layer[1].cfblnr.modify { - $0.raw.cfblnbr = UInt32(Constants.layerHeight) - } - self.layer[1].cr.modify { $0.raw.len = 1 } - - self.srcr.modify { $0.raw.vbr = 1 } // reload - - self.gcr.modify { $1.raw.ltdcen = 1 } - } - - func set(layer: Int, position point: Point) { - let i: Int = - ((Constants.layerWidth + Constants.hbp + Constants.hsync - 1 - + point.x) << 16) | (Constants.hbp + Constants.hsync + point.x) - self.layer[layer].whpcr.modify { $0.raw.storage = UInt32(i) } - let j: Int = - ((Constants.layerHeight + Constants.vsync + Constants.vbp - 1 - + point.y) << 16) | (Constants.vsync + Constants.vbp + point.y) - self.layer[layer].wvpcr.modify { $0.raw.storage = UInt32(j) } - self.srcr.modify { $0.raw.vbr = 1 } - } - - func set(backgroundColor: Color) { - self.bccr.modify { - $0.raw.bcred = UInt32(backgroundColor.red) - $0.raw.bcgreen = UInt32(backgroundColor.green) - $0.raw.bcblue = UInt32(backgroundColor.blue) - } - } -} - -@_used -let pixelData: InlineArray<_, UInt32> = [ - 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, - 0x03ff_5555, 0x3cee_5137, 0x86f0_5237, 0xbbf0_5038, 0xd6f0_5138, 0xeff0_5137, - 0xf9f0_5138, 0xfdf0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfdf0_5138, 0xf8f0_5138, 0xe6ef_5139, 0xcff0_5137, 0xb9f0_5139, 0x8bf0_5139, - 0x47f1_5339, 0x02ff_8000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, - 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, - 0x0000_0000, 0x5df1_5237, 0xe4f0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xe1f0_5038, 0x57f0_5238, 0x0000_0000, - 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, - 0x0000_0000, 0x15f3_553d, 0xb2f1_5238, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0x9df0_5137, 0x0be8_462e, 0x0000_0000, 0x0000_0000, 0x0000_0000, - 0x0000_0000, 0x0000_0000, 0x0be8_462e, 0xd4f1_5139, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xd1f0_5138, 0x0be8_462e, - 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x9df0_5137, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 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0xffff_ffff, 0xffff_ffff, 0xfff6_9586, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff9_b8ae, 0xffff_ffff, - 0xffff_ffff, 0xfffb_cbc4, 0xfff1_5e47, 0xfff0_543b, 0xfffb_cec7, 0xffff_ffff, - 0xffff_ffff, 0xfffa_c6bd, 0xfff1_5941, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff5_8a79, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfffc_ddd8, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_533a, 0xfffb_cbc4, 0xffff_ffff, 0xffff_ffff, 0xfffd_edea, 0xfff4_7d6b, - 0xfff1_5941, 0xfffc_ded9, 0xffff_ffff, 0xffff_ffff, 0xfffd_e4e0, 0xfff2_6d58, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff5_9080, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xfff3_7561, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff1_5941, 0xfffc_dcd6, 0xffff_ffff, - 0xffff_ffff, 0xffff_fefe, 0xfff8_b0a4, 0xfff2_6751, 0xfffd_eae7, 0xffff_ffff, - 0xffff_ffff, 0xfffe_f7f6, 0xfff6_9383, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff6_9b8d, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfff7_a699, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff1_614a, 0xfffd_e9e6, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfffc_e2dd, - 0xfff6_9181, 0xfffe_f3f2, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfffa_c2b9, - 0xfff1_5b44, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff9_b9af, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfffb_cfc8, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff2_6c56, 0xfffe_efed, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_fdfd, 0xfffc_e0db, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xfffd_ebe8, 0xfff4_7d6a, 0xfff0_5138, 0xfff0_5138, - 0xfffc_dcd7, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xfffe_f5f4, 0xfff0_523a, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff2_6e59, 0xfffe_f0ee, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_fefe, - 0xfff9_b7ac, 0xfff2_6c57, 0xffff_fefd, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfff1_5f48, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff3_6f5a, 0xfffe_f1ef, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_fcfb, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xfff2_6953, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff3_705b, 0xfffe_f1ef, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xfff3_725e, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff3_715d, 0xfffe_efec, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfff3_6f5a, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_543b, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff2_654f, 0xfffc_e0dc, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_fefe, - 0xfff1_573f, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff5_8c7c, 0xfff5_8675, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff1_5a42, 0xfffb_cec7, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xfffd_ece9, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5239, - 0xfffb_d0c9, 0xfffb_cdc6, 0xfff2_6a54, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_533a, 0xfff9_b7ad, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfffb_cfc8, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff1_614a, 0xfffe_efed, 0xffff_fafa, 0xfff8_b1a6, - 0xfff2_6953, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff2_654f, 0xfffd_e5e1, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfffe_f5f3, - 0xfff2_654f, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff3_705c, - 0xfffe_f2f0, 0xffff_ffff, 0xffff_fefe, 0xfffb_d0c9, 0xfff6_9889, 0xfff2_6650, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_523a, 0xfff4_7e6c, 0xfff9_bcb3, 0xffff_fafa, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xfffb_d2cb, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff3_715d, 0xfffe_f2f0, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xfffd_ebe8, 0xfffb_cec7, 0xfff9_b5aa, 0xfff8_aa9d, - 0xfff7_a396, 0xfff8_ab9f, 0xfff9_b8ae, 0xfffb_d5cf, 0xfffe_f6f5, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfff4_8473, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff3_725d, - 0xfffe_efec, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xfffc_d7d2, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff1_614a, 0xfffb_d0c9, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xfff2_6852, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfdf0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_523a, - 0xfff7_a598, 0xffff_fdfd, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xfff6_9b8d, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfdf0_5138, 0xf8f0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff3_6e5a, 0xfffa_c9c1, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xfffd_ece9, 0xfffa_c8c0, 0xfff9_beb5, 0xfffb_d3cc, 0xffff_fafa, - 0xffff_ffff, 0xffff_ffff, 0xfff9_bcb3, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xf8f0_5138, 0xe6ef_5139, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff3_7763, 0xfffb_d2cb, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xfffa_c9c1, 0xfff4_7f6c, 0xfff0_5239, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff1_624c, 0xfffa_c6bd, 0xffff_ffff, 0xfffb_d0c9, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xe6ef_5139, - 0xcff0_5137, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff2_6c57, - 0xfff8_aea2, 0xfffd_e5e1, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, 0xffff_ffff, - 0xfffd_ebe8, 0xfff8_aa9d, 0xfff2_6953, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5239, 0xfffa_c3ba, - 0xfffb_d1cb, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xcff0_5137, 0xb9f0_5139, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff2_654f, 0xfff5_8d7d, - 0xfff8_a99d, 0xfffa_c0b7, 0xfffa_cac3, 0xfffb_cfc8, 0xfff9_bdb4, 0xfff8_a99d, - 0xfff6_9585, 0xfff3_7966, 0xfff0_5239, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff1_5d45, 0xfff7_9d8f, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xb9f0_5139, 0x8bf0_5139, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0x8bf0_5139, - 0x47f1_5339, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0x47f1_5339, 0x02ff_8000, 0xe1f0_5038, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xe1f0_5038, 0x02ff_8000, 0x0000_0000, 0x57f0_5238, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0x57f0_5238, 0x0000_0000, - 0x0000_0000, 0x0000_0000, 0x9df0_5137, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0x9df0_5137, - 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0be8_462e, 0xd1f0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xd1f0_5138, 0x0be8_462e, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, - 0x0000_0000, 0x0be8_462e, 0x9df0_5137, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0x9df0_5137, 0x0be8_462e, 0x0000_0000, 0x0000_0000, 0x0000_0000, - 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x57f0_5238, - 0xe1f0_5038, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xe1f0_5038, 0x57f0_5238, 0x0000_0000, 0x0000_0000, 0x0000_0000, - 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, - 0x0000_0000, 0x0000_0000, 0x02ff_8000, 0x47f1_5339, 0x8cf0_5038, 0xb9f0_5139, - 0xd0f0_5138, 0xe6ef_5139, 0xf8f0_5138, 0xfdf0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, 0xfff0_5138, - 0xfff0_5138, 0xfff0_5138, 0xfdf0_5138, 0xf8f0_5138, 0xe6ef_5139, 0xd0f0_5138, - 0xb9f0_5139, 0x8cf0_5038, 0x47f1_5339, 0x02ff_8000, 0x0000_0000, 0x0000_0000, - 0x0000_0000, 0x0000_0000, 0x0000_0000, 0x0000_0000, -] diff --git a/stm32-lcd-logo/Sources/Application/HAL/RCC+Helpers.swift b/stm32-lcd-logo/Sources/Application/HAL/RCC+Helpers.swift deleted file mode 100644 index e7eb20c3..00000000 --- a/stm32-lcd-logo/Sources/Application/HAL/RCC+Helpers.swift +++ /dev/null @@ -1,66 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import STM32F7X6 - -extension RCC { - func enableGPIOPortClock(_ port: GPIOA.Port) { - switch port { - case .a: self.ahb1enr.modify { $0.raw.gpioaen = 1 } - case .b: self.ahb1enr.modify { $0.raw.gpioben = 1 } - case .c: self.ahb1enr.modify { $0.raw.gpiocen = 1 } - case .d: self.ahb1enr.modify { $0.raw.gpioden = 1 } - case .e: self.ahb1enr.modify { $0.raw.gpioeen = 1 } - case .f: self.ahb1enr.modify { $0.raw.gpiofen = 1 } - case .g: self.ahb1enr.modify { $0.raw.gpiogen = 1 } - case .h: self.ahb1enr.modify { $0.raw.gpiohen = 1 } - case .i: self.ahb1enr.modify { $0.raw.gpioien = 1 } - case .j: self.ahb1enr.modify { $0.raw.gpiojen = 1 } - case .k: self.ahb1enr.modify { $0.raw.gpioken = 1 } - } - } - - func enableUARTClock(_ uartNum: UInt8) { - switch uartNum { - case 1: self.apb2enr.modify { $0.raw.usart1en = 1 } - case 2: self.apb1enr.modify { $0.raw.usart2en = 1 } - case 3: self.apb1enr.modify { $0.raw.usart3en = 1 } - case 4: self.apb1enr.modify { $0.raw.uart4en = 1 } - case 5: self.apb1enr.modify { $0.raw.uart5en = 1 } - case 6: self.apb2enr.modify { $0.raw.usart6en = 1 } - case 7: self.apb1enr.modify { $0.raw.uart7en = 1 } - case 8: self.apb1enr.modify { $0.raw.uart8en = 1 } - default: fatalError("Invalid UART number") - } - } - - func enableI2CClock(_ i2cNum: UInt8) { - switch i2cNum { - case 1: self.apb1enr.modify { $0.raw.i2c1en = 1 } - case 2: self.apb1enr.modify { $0.raw.i2c2en = 1 } - case 3: self.apb1enr.modify { $0.raw.i2c3en = 1 } - case 4: self.apb1enr.modify { $0.raw.i2c4en = 1 } - default: fatalError("Invalid I2C number") - } - } - - func enableSPIClock(_ spiNum: UInt8) { - switch spiNum { - case 1: self.apb2enr.modify { $0.raw.spi1en = 1 } - case 2: self.apb1enr.modify { $0.raw.spi2en = 1 } - case 3: self.apb1enr.modify { $0.raw.spi3en = 1 } - case 4: self.apb2enr.modify { $0.raw.spi4en = 1 } - case 5: self.apb2enr.modify { $0.raw.spi5en = 1 } - case 6: self.apb2enr.modify { $0.raw.spi6en = 1 } - default: fatalError("Invalid SPI number") - } - } -} diff --git a/stm32-lcd-logo/Sources/STM32F7X6/Device.swift b/stm32-lcd-logo/Sources/STM32F7X6/Device.swift deleted file mode 100644 index 3166a664..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/Device.swift +++ /dev/null @@ -1,45 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// FLASH -public let flash = FLASH(unsafeAddress: 0x40023c00) - -/// General-purpose I/Os -public let gpioa = GPIOA(unsafeAddress: 0x40020000) - -/// General-purpose I/Os -public let gpiob = GPIOB(unsafeAddress: 0x40020400) - -/// General-purpose I/Os -public let gpioc = GPIOC(unsafeAddress: 0x40020800) - -/// General-purpose I/Os -public let gpiod = GPIOD(unsafeAddress: 0x40020c00) - -/// General-purpose I/Os -public let gpioe = GPIOE(unsafeAddress: 0x40021000) - -/// General-purpose I/Os -public let gpiof = GPIOF(unsafeAddress: 0x40021400) - -/// General-purpose I/Os -public let gpiog = GPIOG(unsafeAddress: 0x40021800) - -/// General-purpose I/Os -public let gpioh = GPIOH(unsafeAddress: 0x40021c00) - -/// General-purpose I/Os -public let gpioi = GPIOI(unsafeAddress: 0x40022000) - -/// General-purpose I/Os -public let gpioj = GPIOJ(unsafeAddress: 0x40022400) - -/// General-purpose I/Os -public let gpiok = GPIOK(unsafeAddress: 0x40022800) - -/// LCD-TFT Controller -public let ltdc = LTDC(unsafeAddress: 0x40016800) - -/// Reset and clock control -public let rcc = RCC(unsafeAddress: 0x40023800) diff --git a/stm32-lcd-logo/Sources/STM32F7X6/Empty.swift b/stm32-lcd-logo/Sources/STM32F7X6/Empty.swift deleted file mode 100644 index 934a795a..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/Empty.swift +++ /dev/null @@ -1,13 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// This file is intentionally left empty for SwiftPM to recognize the target as -// a Swift source module. diff --git a/stm32-lcd-logo/Sources/STM32F7X6/FLASH.swift b/stm32-lcd-logo/Sources/STM32F7X6/FLASH.swift deleted file mode 100644 index 1903ed94..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/FLASH.swift +++ /dev/null @@ -1,469 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// FLASH -@RegisterBlock -public struct FLASH { - /// Flash access control register - @RegisterBlock(offset: 0x0) - public var acr: Register - - /// Flash key register - @RegisterBlock(offset: 0x4) - public var keyr: Register - - /// Flash option key register - @RegisterBlock(offset: 0x8) - public var optkeyr: Register - - /// Status register - @RegisterBlock(offset: 0xc) - public var sr: Register - - /// Control register - @RegisterBlock(offset: 0x10) - public var cr: Register - - /// Flash option control register - @RegisterBlock(offset: 0x14) - public var optcr: Register - - /// Flash option control register 1 - @RegisterBlock(offset: 0x18) - public var optcr1: Register -} - -extension FLASH { - /// Flash access control register - @Register(bitWidth: 32) - public struct ACR { - /// Latency - @ReadWrite(bits: 0..<4, as: LATENCYValues.self) - public var latency: LATENCY - - /// Prefetch enable - @ReadWrite(bits: 8..<9, as: PRFTENValues.self) - public var prften: PRFTEN - - /// ART Accelerator Enable - @ReadWrite(bits: 9..<10, as: ARTENValues.self) - public var arten: ARTEN - - /// ART Accelerator reset - @ReadWrite(bits: 11..<12, as: ARTRSTValues.self) - public var artrst: ARTRST - } - - /// Flash key register - @Register(bitWidth: 32) - public struct KEYR { - /// FPEC key - @WriteOnly(bits: 0..<32) - public var key: KEY - } - - /// Flash option key register - @Register(bitWidth: 32) - public struct OPTKEYR { - /// Option byte key - @WriteOnly(bits: 0..<32) - public var optkeyr_field: OPTKEYR_FIELD - } - - /// Status register - @Register(bitWidth: 32) - public struct SR { - /// End of operation - @ReadWrite(bits: 0..<1) - public var eop: EOP - - /// Operation error - @ReadWrite(bits: 1..<2) - public var operr: OPERR - - /// Write protection error - @ReadWrite(bits: 4..<5) - public var wrperr: WRPERR - - /// Programming alignment error - @ReadWrite(bits: 5..<6) - public var pgaerr: PGAERR - - /// Programming parallelism error - @ReadWrite(bits: 6..<7) - public var pgperr: PGPERR - - /// Programming sequence error - @ReadWrite(bits: 7..<8) - public var erserr: ERSERR - - /// Busy - @ReadOnly(bits: 16..<17) - public var bsy: BSY - } - - /// Control register - @Register(bitWidth: 32) - public struct CR { - /// Programming - @ReadWrite(bits: 0..<1, as: PGValues.self) - public var pg: PG - - /// Sector Erase - @ReadWrite(bits: 1..<2, as: SERValues.self) - public var ser: SER - - /// Mass Erase of sectors 0 to 11 - @ReadWrite(bits: 2..<3, as: MERValues.self) - public var mer: MER - - /// Sector number - @ReadWrite(bits: 3..<7) - public var snb: SNB - - /// Program size - @ReadWrite(bits: 8..<10, as: PSIZEValues.self) - public var psize: PSIZE - - /// Start - @ReadWrite(bits: 16..<17, as: STRTValues.self) - public var strt: STRT - - /// End of operation interrupt enable - @ReadWrite(bits: 24..<25, as: EOPIEValues.self) - public var eopie: EOPIE - - /// Error interrupt enable - @ReadWrite(bits: 25..<26, as: ERRIEValues.self) - public var errie: ERRIE - - /// Lock - @ReadWrite(bits: 31..<32, as: LOCKValues.self) - public var lock: LOCK - } - - /// Flash option control register - @Register(bitWidth: 32) - public struct OPTCR { - /// Option lock - @ReadWrite(bits: 0..<1) - public var optlock: OPTLOCK - - /// Option start - @ReadWrite(bits: 1..<2) - public var optstrt: OPTSTRT - - /// BOR reset Level - @ReadWrite(bits: 2..<4) - public var bor_lev: BOR_LEV - - /// User option bytes - @ReadWrite(bits: 4..<5) - public var wwdg_sw: WWDG_SW - - /// User option bytes - @ReadWrite(bits: 5..<6) - public var iwdg_sw: IWDG_SW - - /// User option bytes - @ReadWrite(bits: 6..<7) - public var nrst_stop: nRST_STOP - - /// User option bytes - @ReadWrite(bits: 7..<8) - public var nrst_stdby: nRST_STDBY - - /// Read protect - @ReadWrite(bits: 8..<16) - public var rdp: RDP - - /// Not write protect - @ReadWrite(bits: 16..<24) - public var nwrp: nWRP - - /// Independent watchdog counter freeze in standby mode - @ReadWrite(bits: 30..<31) - public var iwdg_stdby: IWDG_STDBY - - /// Independent watchdog counter freeze in Stop mode - @ReadWrite(bits: 31..<32) - public var iwdg_stop: IWDG_STOP - } - - /// Flash option control register 1 - @Register(bitWidth: 32) - public struct OPTCR1 { - /// Boot base address when Boot pin =0 - @ReadWrite(bits: 0..<16) - public var boot_add0: BOOT_ADD0 - - /// Boot base address when Boot pin =1 - @ReadWrite(bits: 16..<32) - public var boot_add1: BOOT_ADD1 - } -} - -extension FLASH.ACR { - public struct LATENCYValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// 0 wait states - public static let WS0 = Self(rawValue: 0x0) - - /// 1 wait states - public static let WS1 = Self(rawValue: 0x1) - - /// 2 wait states - public static let WS2 = Self(rawValue: 0x2) - - /// 3 wait states - public static let WS3 = Self(rawValue: 0x3) - - /// 4 wait states - public static let WS4 = Self(rawValue: 0x4) - - /// 5 wait states - public static let WS5 = Self(rawValue: 0x5) - - /// 6 wait states - public static let WS6 = Self(rawValue: 0x6) - - /// 7 wait states - public static let WS7 = Self(rawValue: 0x7) - - /// 8 wait states - public static let WS8 = Self(rawValue: 0x8) - - /// 9 wait states - public static let WS9 = Self(rawValue: 0x9) - - /// 10 wait states - public static let WS10 = Self(rawValue: 0xa) - - /// 11 wait states - public static let WS11 = Self(rawValue: 0xb) - - /// 12 wait states - public static let WS12 = Self(rawValue: 0xc) - - /// 13 wait states - public static let WS13 = Self(rawValue: 0xd) - - /// 14 wait states - public static let WS14 = Self(rawValue: 0xe) - - /// 15 wait states - public static let WS15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.ACR { - public struct PRFTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Prefetch is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Prefetch is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.ACR { - public struct ARTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// ART Accelerator is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// ART Accelerator is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.ACR { - public struct ARTRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Accelerator is not reset - public static let NotReset = Self(rawValue: 0x0) - - /// Accelerator is reset - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct PGValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Flash programming activated - public static let Program = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct SERValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Erase activated for selected sector - public static let SectorErase = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct MERValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Erase activated for all user sectors - public static let MassErase = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct PSIZEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Program x8 - public static let PSIZE8 = Self(rawValue: 0x0) - - /// Program x16 - public static let PSIZE16 = Self(rawValue: 0x1) - - /// Program x32 - public static let PSIZE32 = Self(rawValue: 0x2) - - /// Program x64 - public static let PSIZE64 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct STRTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Trigger an erase operation - public static let Start = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct EOPIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// End of operation interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// End of operation interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct ERRIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Error interrupt generation disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Error interrupt generation enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct LOCKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// FLASH_CR register is unlocked - public static let Unlocked = Self(rawValue: 0x0) - - /// FLASH_CR register is locked - public static let Locked = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOA.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOA.swift deleted file mode 100644 index a70e68c7..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOA.swift +++ /dev/null @@ -1,1075 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -@RegisterBlock -public struct GPIOA { - /// GPIO port mode register - @RegisterBlock(offset: 0x0) - public var moder: Register - - /// GPIO port output type register - @RegisterBlock(offset: 0x4) - public var otyper: Register - - /// GPIO port output speed register - @RegisterBlock(offset: 0x8) - public var ospeedr: Register - - /// GPIO port pull-up/pull-down register - @RegisterBlock(offset: 0xc) - public var pupdr: Register - - /// GPIO port input data register - @RegisterBlock(offset: 0x10) - public var idr: Register - - /// GPIO port output data register - @RegisterBlock(offset: 0x14) - public var odr: Register - - /// GPIO port bit set/reset register - @RegisterBlock(offset: 0x18) - public var bsrr: Register - - /// GPIO port configuration lock register - @RegisterBlock(offset: 0x1c) - public var lckr: Register - - /// GPIO alternate function low register - @RegisterBlock(offset: 0x20) - public var afrl: Register - - /// GPIO alternate function high register - @RegisterBlock(offset: 0x24) - public var afrh: Register - - /// GPIO port bit reset register - @RegisterBlock(offset: 0x28) - public var brr: Register -} - -extension GPIOA { - /// GPIO port mode register - @Register(bitWidth: 32) - public struct MODER { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var moder15: MODER15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var moder14: MODER14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var moder13: MODER13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var moder12: MODER12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var moder11: MODER11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var moder10: MODER10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var moder9: MODER9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var moder8: MODER8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var moder7: MODER7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var moder6: MODER6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var moder5: MODER5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var moder4: MODER4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var moder3: MODER3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var moder2: MODER2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var moder1: MODER1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: MODER0Values.self) - public var moder0: MODER0 - } - - /// GPIO port output type register - @Register(bitWidth: 32) - public struct OTYPER { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 15..<16) - public var ot15: OT15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<15) - public var ot14: OT14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 13..<14) - public var ot13: OT13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<13) - public var ot12: OT12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 11..<12) - public var ot11: OT11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<11) - public var ot10: OT10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 9..<10) - public var ot9: OT9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<9) - public var ot8: OT8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 7..<8) - public var ot7: OT7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<7) - public var ot6: OT6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 5..<6) - public var ot5: OT5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<5) - public var ot4: OT4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 3..<4) - public var ot3: OT3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<3) - public var ot2: OT2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 1..<2) - public var ot1: OT1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<1, as: OT0Values.self) - public var ot0: OT0 - } - - /// GPIO port output speed register - @Register(bitWidth: 32) - public struct OSPEEDR { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var ospeedr15: OSPEEDR15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var ospeedr14: OSPEEDR14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var ospeedr13: OSPEEDR13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var ospeedr12: OSPEEDR12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var ospeedr11: OSPEEDR11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var ospeedr10: OSPEEDR10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var ospeedr9: OSPEEDR9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var ospeedr8: OSPEEDR8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var ospeedr7: OSPEEDR7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var ospeedr6: OSPEEDR6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var ospeedr5: OSPEEDR5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var ospeedr4: OSPEEDR4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var ospeedr3: OSPEEDR3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var ospeedr2: OSPEEDR2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var ospeedr1: OSPEEDR1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) - public var ospeedr0: OSPEEDR0 - } - - /// GPIO port pull-up/pull-down register - @Register(bitWidth: 32) - public struct PUPDR { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var pupdr15: PUPDR15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var pupdr14: PUPDR14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var pupdr13: PUPDR13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var pupdr12: PUPDR12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var pupdr11: PUPDR11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var pupdr10: PUPDR10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var pupdr9: PUPDR9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var pupdr8: PUPDR8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var pupdr7: PUPDR7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var pupdr6: PUPDR6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var pupdr5: PUPDR5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var pupdr4: PUPDR4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var pupdr3: PUPDR3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var pupdr2: PUPDR2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var pupdr1: PUPDR1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) - public var pupdr0: PUPDR0 - } - - /// GPIO port input data register - @Register(bitWidth: 32) - public struct IDR { - /// Port input data (y = 0..15) - @ReadOnly(bits: 15..<16) - public var idr15: IDR15 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 14..<15) - public var idr14: IDR14 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 13..<14) - public var idr13: IDR13 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 12..<13) - public var idr12: IDR12 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 11..<12) - public var idr11: IDR11 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 10..<11) - public var idr10: IDR10 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 9..<10) - public var idr9: IDR9 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 8..<9) - public var idr8: IDR8 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 7..<8) - public var idr7: IDR7 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 6..<7) - public var idr6: IDR6 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 5..<6) - public var idr5: IDR5 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 4..<5) - public var idr4: IDR4 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 3..<4) - public var idr3: IDR3 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 2..<3) - public var idr2: IDR2 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 1..<2) - public var idr1: IDR1 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 0..<1) - public var idr0: IDR0 - } - - /// GPIO port output data register - @Register(bitWidth: 32) - public struct ODR { - /// Port output data (y = 0..15) - @ReadWrite(bits: 15..<16) - public var odr15: ODR15 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 14..<15) - public var odr14: ODR14 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 13..<14) - public var odr13: ODR13 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 12..<13) - public var odr12: ODR12 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 11..<12) - public var odr11: ODR11 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 10..<11) - public var odr10: ODR10 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 9..<10) - public var odr9: ODR9 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 8..<9) - public var odr8: ODR8 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 7..<8) - public var odr7: ODR7 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 6..<7) - public var odr6: ODR6 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 5..<6) - public var odr5: ODR5 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 4..<5) - public var odr4: ODR4 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 3..<4) - public var odr3: ODR3 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 2..<3) - public var odr2: ODR2 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 1..<2) - public var odr1: ODR1 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 0..<1, as: ODR0Values.self) - public var odr0: ODR0 - } - - /// GPIO port bit set/reset register - @Register(bitWidth: 32) - public struct BSRR { - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 31..<32) - public var br15: BR15 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 30..<31) - public var br14: BR14 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 29..<30) - public var br13: BR13 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 28..<29) - public var br12: BR12 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 27..<28) - public var br11: BR11 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 26..<27) - public var br10: BR10 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 25..<26) - public var br9: BR9 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 24..<25) - public var br8: BR8 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 23..<24) - public var br7: BR7 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 22..<23) - public var br6: BR6 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 21..<22) - public var br5: BR5 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 20..<21) - public var br4: BR4 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 19..<20) - public var br3: BR3 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 18..<19) - public var br2: BR2 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 17..<18) - public var br1: BR1 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 16..<17) - public var br0: BR0 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 15..<16) - public var bs15: BS15 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 14..<15) - public var bs14: BS14 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 13..<14) - public var bs13: BS13 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 12..<13) - public var bs12: BS12 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 11..<12) - public var bs11: BS11 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 10..<11) - public var bs10: BS10 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 9..<10) - public var bs9: BS9 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 8..<9) - public var bs8: BS8 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 7..<8) - public var bs7: BS7 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 6..<7) - public var bs6: BS6 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 5..<6) - public var bs5: BS5 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 4..<5) - public var bs4: BS4 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 3..<4) - public var bs3: BS3 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 2..<3) - public var bs2: BS2 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 1..<2) - public var bs1: BS1 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 0..<1) - public var bs0: BS0 - } - - /// GPIO port configuration lock register - @Register(bitWidth: 32) - public struct LCKR { - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 16..<17, as: LCKKValues.self) - public var lckk: LCKK - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 15..<16) - public var lck15: LCK15 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 14..<15) - public var lck14: LCK14 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 13..<14) - public var lck13: LCK13 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 12..<13) - public var lck12: LCK12 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 11..<12) - public var lck11: LCK11 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 10..<11) - public var lck10: LCK10 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 9..<10) - public var lck9: LCK9 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 8..<9) - public var lck8: LCK8 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 7..<8) - public var lck7: LCK7 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 6..<7) - public var lck6: LCK6 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 5..<6) - public var lck5: LCK5 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 4..<5) - public var lck4: LCK4 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 3..<4) - public var lck3: LCK3 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 2..<3) - public var lck2: LCK2 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 1..<2) - public var lck1: LCK1 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 0..<1, as: LCK0Values.self) - public var lck0: LCK0 - } - - /// GPIO alternate function low register - @Register(bitWidth: 32) - public struct AFRL { - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 28..<32) - public var afrl7: AFRL7 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 24..<28) - public var afrl6: AFRL6 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 20..<24) - public var afrl5: AFRL5 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 16..<20) - public var afrl4: AFRL4 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 12..<16) - public var afrl3: AFRL3 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 8..<12) - public var afrl2: AFRL2 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 4..<8) - public var afrl1: AFRL1 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 0..<4, as: AFRL0Values.self) - public var afrl0: AFRL0 - } - - /// GPIO alternate function high register - @Register(bitWidth: 32) - public struct AFRH { - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 28..<32) - public var afrh15: AFRH15 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 24..<28) - public var afrh14: AFRH14 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 20..<24) - public var afrh13: AFRH13 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 16..<20) - public var afrh12: AFRH12 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 12..<16) - public var afrh11: AFRH11 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 8..<12) - public var afrh10: AFRH10 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 4..<8) - public var afrh9: AFRH9 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 0..<4, as: AFRH8Values.self) - public var afrh8: AFRH8 - } - - /// GPIO port bit reset register - @Register(bitWidth: 32) - public struct BRR { - /// Port A Reset bit 0 - @ReadWrite(bits: 0..<1) - public var br0: BR0 - - /// Port A Reset bit 1 - @ReadWrite(bits: 1..<2) - public var br1: BR1 - - /// Port A Reset bit 2 - @ReadWrite(bits: 2..<3) - public var br2: BR2 - - /// Port A Reset bit 3 - @ReadWrite(bits: 3..<4) - public var br3: BR3 - - /// Port A Reset bit 4 - @ReadWrite(bits: 4..<5) - public var br4: BR4 - - /// Port A Reset bit 5 - @ReadWrite(bits: 5..<6) - public var br5: BR5 - - /// Port A Reset bit 6 - @ReadWrite(bits: 6..<7) - public var br6: BR6 - - /// Port A Reset bit 7 - @ReadWrite(bits: 7..<8) - public var br7: BR7 - - /// Port A Reset bit 8 - @ReadWrite(bits: 8..<9) - public var br8: BR8 - - /// Port A Reset bit 9 - @ReadWrite(bits: 9..<10) - public var br9: BR9 - - /// Port A Reset bit 10 - @ReadWrite(bits: 10..<11) - public var br10: BR10 - - /// Port A Reset bit 11 - @ReadWrite(bits: 11..<12) - public var br11: BR11 - - /// Port A Reset bit 12 - @ReadWrite(bits: 12..<13) - public var br12: BR12 - - /// Port A Reset bit 13 - @ReadWrite(bits: 13..<14) - public var br13: BR13 - - /// Port A Reset bit 14 - @ReadWrite(bits: 14..<15) - public var br14: BR14 - - /// Port A Reset bit 15 - @ReadWrite(bits: 15..<16) - public var br15: BR15 - } -} - -extension GPIOA.MODER { - public struct MODER0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Input mode (reset state) - public static let Input = Self(rawValue: 0x0) - - /// General purpose output mode - public static let Output = Self(rawValue: 0x1) - - /// Alternate function mode - public static let Alternate = Self(rawValue: 0x2) - - /// Analog mode - public static let Analog = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.OTYPER { - public struct OT0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Output push-pull (reset state) - public static let PushPull = Self(rawValue: 0x0) - - /// Output open-drain - public static let OpenDrain = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.OSPEEDR { - public struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Low speed - public static let LowSpeed = Self(rawValue: 0x0) - - /// Medium speed - public static let MediumSpeed = Self(rawValue: 0x1) - - /// High speed - public static let HighSpeed = Self(rawValue: 0x2) - - /// Very high speed - public static let VeryHighSpeed = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.PUPDR { - public struct PUPDR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// No pull-up, pull-down - public static let Floating = Self(rawValue: 0x0) - - /// Pull-up - public static let PullUp = Self(rawValue: 0x1) - - /// Pull-down - public static let PullDown = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.ODR { - public struct ODR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Set output to logic low - public static let Low = Self(rawValue: 0x0) - - /// Set output to logic high - public static let High = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.LCKR { - public struct LCKKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Port configuration lock key not active - public static let NotActive = Self(rawValue: 0x0) - - /// Port configuration lock key active - public static let Active = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.LCKR { - public struct LCK0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Port configuration not locked - public static let Unlocked = Self(rawValue: 0x0) - - /// Port configuration locked - public static let Locked = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.AFRL { - public struct AFRL0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// AF0 - public static let AF0 = Self(rawValue: 0x0) - - /// AF1 - public static let AF1 = Self(rawValue: 0x1) - - /// AF2 - public static let AF2 = Self(rawValue: 0x2) - - /// AF3 - public static let AF3 = Self(rawValue: 0x3) - - /// AF4 - public static let AF4 = Self(rawValue: 0x4) - - /// AF5 - public static let AF5 = Self(rawValue: 0x5) - - /// AF6 - public static let AF6 = Self(rawValue: 0x6) - - /// AF7 - public static let AF7 = Self(rawValue: 0x7) - - /// AF8 - public static let AF8 = Self(rawValue: 0x8) - - /// AF9 - public static let AF9 = Self(rawValue: 0x9) - - /// AF10 - public static let AF10 = Self(rawValue: 0xa) - - /// AF11 - public static let AF11 = Self(rawValue: 0xb) - - /// AF12 - public static let AF12 = Self(rawValue: 0xc) - - /// AF13 - public static let AF13 = Self(rawValue: 0xd) - - /// AF14 - public static let AF14 = Self(rawValue: 0xe) - - /// AF15 - public static let AF15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.AFRH { - public struct AFRH8Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// AF0 - public static let AF0 = Self(rawValue: 0x0) - - /// AF1 - public static let AF1 = Self(rawValue: 0x1) - - /// AF2 - public static let AF2 = Self(rawValue: 0x2) - - /// AF3 - public static let AF3 = Self(rawValue: 0x3) - - /// AF4 - public static let AF4 = Self(rawValue: 0x4) - - /// AF5 - public static let AF5 = Self(rawValue: 0x5) - - /// AF6 - public static let AF6 = Self(rawValue: 0x6) - - /// AF7 - public static let AF7 = Self(rawValue: 0x7) - - /// AF8 - public static let AF8 = Self(rawValue: 0x8) - - /// AF9 - public static let AF9 = Self(rawValue: 0x9) - - /// AF10 - public static let AF10 = Self(rawValue: 0xa) - - /// AF11 - public static let AF11 = Self(rawValue: 0xb) - - /// AF12 - public static let AF12 = Self(rawValue: 0xc) - - /// AF13 - public static let AF13 = Self(rawValue: 0xd) - - /// AF14 - public static let AF14 = Self(rawValue: 0xe) - - /// AF15 - public static let AF15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOB.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOB.swift deleted file mode 100644 index bd0a35ba..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOB.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOB = GPIOA - diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOC.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOC.swift deleted file mode 100644 index c46e6690..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOC.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOC = GPIOA - diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOD.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOD.swift deleted file mode 100644 index d51ac802..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOD.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOD = GPIOA - diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOE.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOE.swift deleted file mode 100644 index c78fa87f..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOE.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOE = GPIOA - diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOF.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOF.swift deleted file mode 100644 index f4dce7fb..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOF.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOF = GPIOA - diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOG.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOG.swift deleted file mode 100644 index 88fb4c6a..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOG.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOG = GPIOA - diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOH.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOH.swift deleted file mode 100644 index 5a558ef3..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOH.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOH = GPIOA - diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOI.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOI.swift deleted file mode 100644 index 6b2b5182..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOI.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOI = GPIOA - diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOJ.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOJ.swift deleted file mode 100644 index 98b3c09a..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOJ.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOJ = GPIOA - diff --git a/stm32-lcd-logo/Sources/STM32F7X6/GPIOK.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOK.swift deleted file mode 100644 index c1f074b8..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/GPIOK.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOK = GPIOA - diff --git a/stm32-lcd-logo/Sources/STM32F7X6/LTDC.swift b/stm32-lcd-logo/Sources/STM32F7X6/LTDC.swift deleted file mode 100644 index 7dd4bf0a..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/LTDC.swift +++ /dev/null @@ -1,847 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// LCD-TFT Controller -@RegisterBlock -public struct LTDC { - /// Synchronization Size Configuration Register - @RegisterBlock(offset: 0x8) - public var sscr: Register - - /// Back Porch Configuration Register - @RegisterBlock(offset: 0xc) - public var bpcr: Register - - /// Active Width Configuration Register - @RegisterBlock(offset: 0x10) - public var awcr: Register - - /// Total Width Configuration Register - @RegisterBlock(offset: 0x14) - public var twcr: Register - - /// Global Control Register - @RegisterBlock(offset: 0x18) - public var gcr: Register - - /// Shadow Reload Configuration Register - @RegisterBlock(offset: 0x24) - public var srcr: Register - - /// Background Color Configuration Register - @RegisterBlock(offset: 0x2c) - public var bccr: Register - - /// Interrupt Enable Register - @RegisterBlock(offset: 0x34) - public var ier: Register - - /// Interrupt Status Register - @RegisterBlock(offset: 0x38) - public var isr: Register - - /// Interrupt Clear Register - @RegisterBlock(offset: 0x3c) - public var icr: Register - - /// Line Interrupt Position Configuration Register - @RegisterBlock(offset: 0x40) - public var lipcr: Register - - /// Current Position Status Register - @RegisterBlock(offset: 0x44) - public var cpsr: Register - - /// Current Display Status Register - @RegisterBlock(offset: 0x48) - public var cdsr: Register - - /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR - @RegisterBlock(offset: 0x84, stride: 0x80, count: 2) - public var layer: RegisterArray -} - -extension LTDC { - /// Synchronization Size Configuration Register - @Register(bitWidth: 32) - public struct SSCR { - /// Horizontal Synchronization Width (in units of pixel clock period) - @ReadWrite(bits: 16..<28) - public var hsw: HSW - - /// Vertical Synchronization Height (in units of horizontal scan line) - @ReadWrite(bits: 0..<11) - public var vsh: VSH - } - - /// Back Porch Configuration Register - @Register(bitWidth: 32) - public struct BPCR { - /// Accumulated Horizontal back porch (in units of pixel clock period) - @ReadWrite(bits: 16..<28) - public var ahbp: AHBP - - /// Accumulated Vertical back porch (in units of horizontal scan line) - @ReadWrite(bits: 0..<11) - public var avbp: AVBP - } - - /// Active Width Configuration Register - @Register(bitWidth: 32) - public struct AWCR { - /// Accumulated Active Width (in units of pixel clock period) - @ReadWrite(bits: 16..<28) - public var aaw: AAW - - /// Accumulated Active Height (in units of horizontal scan line) - @ReadWrite(bits: 0..<11) - public var aah: AAH - } - - /// Total Width Configuration Register - @Register(bitWidth: 32) - public struct TWCR { - /// Total Width (in units of pixel clock period) - @ReadWrite(bits: 16..<28) - public var totalw: TOTALW - - /// Total Height (in units of horizontal scan line) - @ReadWrite(bits: 0..<11) - public var totalh: TOTALH - } - - /// Global Control Register - @Register(bitWidth: 32) - public struct GCR { - /// Horizontal Synchronization Polarity - @ReadWrite(bits: 31..<32, as: HSPOLValues.self) - public var hspol: HSPOL - - /// Vertical Synchronization Polarity - @ReadWrite(bits: 30..<31, as: VSPOLValues.self) - public var vspol: VSPOL - - /// Data Enable Polarity - @ReadWrite(bits: 29..<30, as: DEPOLValues.self) - public var depol: DEPOL - - /// Pixel Clock Polarity - @ReadWrite(bits: 28..<29, as: PCPOLValues.self) - public var pcpol: PCPOL - - /// Dither Enable - @ReadWrite(bits: 16..<17, as: DENValues.self) - public var den: DEN - - /// Dither Red Width - @ReadOnly(bits: 12..<15) - public var drw: DRW - - /// Dither Green Width - @ReadOnly(bits: 8..<11) - public var dgw: DGW - - /// Dither Blue Width - @ReadOnly(bits: 4..<7) - public var dbw: DBW - - /// LCD-TFT controller enable bit - @ReadWrite(bits: 0..<1, as: LTDCENValues.self) - public var ltdcen: LTDCEN - } - - /// Shadow Reload Configuration Register - @Register(bitWidth: 32) - public struct SRCR { - /// Vertical Blanking Reload - @ReadWrite(bits: 1..<2, as: VBRValues.self) - public var vbr: VBR - - /// Immediate Reload - @ReadWrite(bits: 0..<1, as: IMRValues.self) - public var imr: IMR - } - - /// Background Color Configuration Register - @Register(bitWidth: 32) - public struct BCCR { - /// Background color blue value - @ReadWrite(bits: 0..<8) - public var bcblue: BCBLUE - - /// Background color green value - @ReadWrite(bits: 8..<16) - public var bcgreen: BCGREEN - - /// Background color red value - @ReadWrite(bits: 16..<24) - public var bcred: BCRED - } - - /// Interrupt Enable Register - @Register(bitWidth: 32) - public struct IER { - /// Register Reload interrupt enable - @ReadWrite(bits: 3..<4, as: RRIEValues.self) - public var rrie: RRIE - - /// Transfer Error Interrupt Enable - @ReadWrite(bits: 2..<3, as: TERRIEValues.self) - public var terrie: TERRIE - - /// FIFO Underrun Interrupt Enable - @ReadWrite(bits: 1..<2, as: FUIEValues.self) - public var fuie: FUIE - - /// Line Interrupt Enable - @ReadWrite(bits: 0..<1, as: LIEValues.self) - public var lie: LIE - } - - /// Interrupt Status Register - @Register(bitWidth: 32) - public struct ISR { - /// Register Reload Interrupt Flag - @ReadOnly(bits: 3..<4) - public var rrif: RRIF - - /// Transfer Error interrupt flag - @ReadOnly(bits: 2..<3) - public var terrif: TERRIF - - /// FIFO Underrun Interrupt flag - @ReadOnly(bits: 1..<2) - public var fuif: FUIF - - /// Line Interrupt flag - @ReadOnly(bits: 0..<1) - public var lif: LIF - } - - /// Interrupt Clear Register - @Register(bitWidth: 32) - public struct ICR { - /// Clears Register Reload Interrupt Flag - @WriteOnly(bits: 3..<4) - public var crrif: CRRIF - - /// Clears the Transfer Error Interrupt Flag - @WriteOnly(bits: 2..<3) - public var cterrif: CTERRIF - - /// Clears the FIFO Underrun Interrupt flag - @WriteOnly(bits: 1..<2) - public var cfuif: CFUIF - - /// Clears the Line Interrupt Flag - @WriteOnly(bits: 0..<1) - public var clif: CLIF - } - - /// Line Interrupt Position Configuration Register - @Register(bitWidth: 32) - public struct LIPCR { - /// Line Interrupt Position - @ReadWrite(bits: 0..<11) - public var lipos: LIPOS - } - - /// Current Position Status Register - @Register(bitWidth: 32) - public struct CPSR { - /// Current X Position - @ReadOnly(bits: 16..<32) - public var cxpos: CXPOS - - /// Current Y Position - @ReadOnly(bits: 0..<16) - public var cypos: CYPOS - } - - /// Current Display Status Register - @Register(bitWidth: 32) - public struct CDSR { - /// Horizontal Synchronization display Status - @ReadOnly(bits: 3..<4) - public var hsyncs: HSYNCS - - /// Vertical Synchronization display Status - @ReadOnly(bits: 2..<3) - public var vsyncs: VSYNCS - - /// Horizontal Data Enable display Status - @ReadOnly(bits: 1..<2) - public var hdes: HDES - - /// Vertical Data Enable display Status - @ReadOnly(bits: 0..<1) - public var vdes: VDES - } - - /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR - @RegisterBlock - public struct LAYER { - /// Layerx Control Register - @RegisterBlock(offset: 0x0) - public var cr: Register - - /// Layerx Window Horizontal Position Configuration Register - @RegisterBlock(offset: 0x4) - public var whpcr: Register - - /// Layerx Window Vertical Position Configuration Register - @RegisterBlock(offset: 0x8) - public var wvpcr: Register - - /// Layerx Color Keying Configuration Register - @RegisterBlock(offset: 0xc) - public var ckcr: Register - - /// Layerx Pixel Format Configuration Register - @RegisterBlock(offset: 0x10) - public var pfcr: Register - - /// Layerx Constant Alpha Configuration Register - @RegisterBlock(offset: 0x14) - public var cacr: Register - - /// Layerx Default Color Configuration Register - @RegisterBlock(offset: 0x18) - public var dccr: Register - - /// Layerx Blending Factors Configuration Register - @RegisterBlock(offset: 0x1c) - public var bfcr: Register - - /// Layerx Color Frame Buffer Address Register - @RegisterBlock(offset: 0x28) - public var cfbar: Register - - /// Layerx Color Frame Buffer Length Register - @RegisterBlock(offset: 0x2c) - public var cfblr: Register - - /// Layerx ColorFrame Buffer Line Number Register - @RegisterBlock(offset: 0x30) - public var cfblnr: Register - - /// Layerx CLUT Write Register - @RegisterBlock(offset: 0x40) - public var clutwr: Register - } -} - -extension LTDC.LAYER { - /// Layerx Control Register - @Register(bitWidth: 32) - public struct CR { - /// Color Look-Up Table Enable - @ReadWrite(bits: 4..<5, as: CLUTENValues.self) - public var cluten: CLUTEN - - /// Color Keying Enable - @ReadWrite(bits: 1..<2, as: COLKENValues.self) - public var colken: COLKEN - - /// Layer Enable - @ReadWrite(bits: 0..<1, as: LENValues.self) - public var len: LEN - } - - /// Layerx Window Horizontal Position Configuration Register - @Register(bitWidth: 32) - public struct WHPCR { - /// Window Horizontal Stop Position - @ReadWrite(bits: 16..<28) - public var whsppos: WHSPPOS - - /// Window Horizontal Start Position - @ReadWrite(bits: 0..<12) - public var whstpos: WHSTPOS - } - - /// Layerx Window Vertical Position Configuration Register - @Register(bitWidth: 32) - public struct WVPCR { - /// Window Vertical Stop Position - @ReadWrite(bits: 16..<27) - public var wvsppos: WVSPPOS - - /// Window Vertical Start Position - @ReadWrite(bits: 0..<11) - public var wvstpos: WVSTPOS - } - - /// Layerx Color Keying Configuration Register - @Register(bitWidth: 32) - public struct CKCR { - /// Color Key Red value - @ReadWrite(bits: 16..<24) - public var ckred: CKRED - - /// Color Key Green value - @ReadWrite(bits: 8..<16) - public var ckgreen: CKGREEN - - /// Color Key Blue value - @ReadWrite(bits: 0..<8) - public var ckblue: CKBLUE - } - - /// Layerx Pixel Format Configuration Register - @Register(bitWidth: 32) - public struct PFCR { - /// Pixel Format - @ReadWrite(bits: 0..<3, as: PFValues.self) - public var pf: PF - } - - /// Layerx Constant Alpha Configuration Register - @Register(bitWidth: 32) - public struct CACR { - /// Constant Alpha - @ReadWrite(bits: 0..<8) - public var consta: CONSTA - } - - /// Layerx Default Color Configuration Register - @Register(bitWidth: 32) - public struct DCCR { - /// Default Color Alpha - @ReadWrite(bits: 24..<32) - public var dcalpha: DCALPHA - - /// Default Color Red - @ReadWrite(bits: 16..<24) - public var dcred: DCRED - - /// Default Color Green - @ReadWrite(bits: 8..<16) - public var dcgreen: DCGREEN - - /// Default Color Blue - @ReadWrite(bits: 0..<8) - public var dcblue: DCBLUE - } - - /// Layerx Blending Factors Configuration Register - @Register(bitWidth: 32) - public struct BFCR { - /// Blending Factor 1 - @ReadWrite(bits: 8..<11, as: BF1Values.self) - public var bf1: BF1 - - /// Blending Factor 2 - @ReadWrite(bits: 0..<3, as: BF2Values.self) - public var bf2: BF2 - } - - /// Layerx Color Frame Buffer Address Register - @Register(bitWidth: 32) - public struct CFBAR { - /// Color Frame Buffer Start Address - @ReadWrite(bits: 0..<32) - public var cfbadd: CFBADD - } - - /// Layerx Color Frame Buffer Length Register - @Register(bitWidth: 32) - public struct CFBLR { - /// Color Frame Buffer Pitch in bytes - @ReadWrite(bits: 16..<29) - public var cfbp: CFBP - - /// Color Frame Buffer Line Length - @ReadWrite(bits: 0..<13) - public var cfbll: CFBLL - } - - /// Layerx ColorFrame Buffer Line Number Register - @Register(bitWidth: 32) - public struct CFBLNR { - /// Frame Buffer Line Number - @ReadWrite(bits: 0..<11) - public var cfblnbr: CFBLNBR - } - - /// Layerx CLUT Write Register - @Register(bitWidth: 32) - public struct CLUTWR { - /// CLUT Address - @WriteOnly(bits: 24..<32) - public var clutadd: CLUTADD - - /// Red value - @WriteOnly(bits: 16..<24) - public var red: RED - - /// Green value - @WriteOnly(bits: 8..<16) - public var green: GREEN - - /// Blue value - @WriteOnly(bits: 0..<8) - public var blue: BLUE - } -} - -extension LTDC.GCR { - public struct HSPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Horizontal synchronization polarity is active low - public static let ActiveLow = Self(rawValue: 0x0) - - /// Horizontal synchronization polarity is active high - public static let ActiveHigh = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.GCR { - public struct VSPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Vertical synchronization polarity is active low - public static let ActiveLow = Self(rawValue: 0x0) - - /// Vertical synchronization polarity is active high - public static let ActiveHigh = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.GCR { - public struct DEPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Data enable polarity is active low - public static let ActiveLow = Self(rawValue: 0x0) - - /// Data enable polarity is active high - public static let ActiveHigh = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.GCR { - public struct PCPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Pixel clock on rising edge - public static let RisingEdge = Self(rawValue: 0x0) - - /// Pixel clock on falling edge - public static let FallingEdge = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.GCR { - public struct DENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Dither disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Dither enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.GCR { - public struct LTDCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LCD-TFT controller disabled - public static let Disabled = Self(rawValue: 0x0) - - /// LCD-TFT controller enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.SRCR { - public struct VBRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - public static let NoEffect = Self(rawValue: 0x0) - - /// The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). - public static let Reload = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.SRCR { - public struct IMRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - public static let NoEffect = Self(rawValue: 0x0) - - /// The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload - public static let Reload = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.IER { - public struct RRIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Register reload interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Register reload interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.IER { - public struct TERRIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Transfer error interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Transfer error interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.IER { - public struct FUIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// FIFO underrun interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// FIFO underrun interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.IER { - public struct LIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Line interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Line interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.CR { - public struct CLUTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Color look-up table disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Color look-up table enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.CR { - public struct COLKENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Color keying disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Color keying enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.CR { - public struct LENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Layer disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Layer enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.PFCR { - public struct PFValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// ARGB8888 - public static let ARGB8888 = Self(rawValue: 0x0) - - /// RGB888 - public static let RGB888 = Self(rawValue: 0x1) - - /// RGB565 - public static let RGB565 = Self(rawValue: 0x2) - - /// ARGB1555 - public static let ARGB1555 = Self(rawValue: 0x3) - - /// ARGB4444 - public static let ARGB4444 = Self(rawValue: 0x4) - - /// L8 (8-bit luminance) - public static let L8 = Self(rawValue: 0x5) - - /// AL44 (4-bit alpha, 4-bit luminance) - public static let AL44 = Self(rawValue: 0x6) - - /// AL88 (8-bit alpha, 8-bit luminance) - public static let AL88 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.BFCR { - public struct BF1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// BF1 = constant alpha - public static let Constant = Self(rawValue: 0x4) - - /// BF1 = pixel alpha * constant alpha - public static let Pixel = Self(rawValue: 0x6) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.BFCR { - public struct BF2Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// BF2 = 1 - constant alpha - public static let Constant = Self(rawValue: 0x5) - - /// BF2 = 1 - pixel alpha * constant alpha - public static let Pixel = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lcd-logo/Sources/STM32F7X6/RCC.swift b/stm32-lcd-logo/Sources/STM32F7X6/RCC.swift deleted file mode 100644 index 4a36aea8..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/RCC.swift +++ /dev/null @@ -1,2833 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Reset and clock control -@RegisterBlock -public struct RCC { - /// clock control register - @RegisterBlock(offset: 0x0) - public var cr: Register - - /// PLL configuration register - @RegisterBlock(offset: 0x4) - public var pllcfgr: Register - - /// clock configuration register - @RegisterBlock(offset: 0x8) - public var cfgr: Register - - /// clock interrupt register - @RegisterBlock(offset: 0xc) - public var cir: Register - - /// AHB1 peripheral reset register - @RegisterBlock(offset: 0x10) - public var ahb1rstr: Register - - /// AHB2 peripheral reset register - @RegisterBlock(offset: 0x14) - public var ahb2rstr: Register - - /// AHB3 peripheral reset register - @RegisterBlock(offset: 0x18) - public var ahb3rstr: Register - - /// APB1 peripheral reset register - @RegisterBlock(offset: 0x20) - public var apb1rstr: Register - - /// APB2 peripheral reset register - @RegisterBlock(offset: 0x24) - public var apb2rstr: Register - - /// AHB1 peripheral clock register - @RegisterBlock(offset: 0x30) - public var ahb1enr: Register - - /// AHB2 peripheral clock enable register - @RegisterBlock(offset: 0x34) - public var ahb2enr: Register - - /// AHB3 peripheral clock enable register - @RegisterBlock(offset: 0x38) - public var ahb3enr: Register - - /// APB1 peripheral clock enable register - @RegisterBlock(offset: 0x40) - public var apb1enr: Register - - /// APB2 peripheral clock enable register - @RegisterBlock(offset: 0x44) - public var apb2enr: Register - - /// AHB1 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x50) - public var ahb1lpenr: Register - - /// AHB2 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x54) - public var ahb2lpenr: Register - - /// AHB3 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x58) - public var ahb3lpenr: Register - - /// APB1 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x60) - public var apb1lpenr: Register - - /// APB2 peripheral clock enabled in low power mode register - @RegisterBlock(offset: 0x64) - public var apb2lpenr: Register - - /// Backup domain control register - @RegisterBlock(offset: 0x70) - public var bdcr: Register - - /// clock control & status register - @RegisterBlock(offset: 0x74) - public var csr: Register - - /// spread spectrum clock generation register - @RegisterBlock(offset: 0x80) - public var sscgr: Register - - /// PLLI2S configuration register - @RegisterBlock(offset: 0x84) - public var plli2scfgr: Register - - /// PLL configuration register - @RegisterBlock(offset: 0x88) - public var pllsaicfgr: Register - - /// dedicated clocks configuration register - @RegisterBlock(offset: 0x8c) - public var dckcfgr1: Register - - /// dedicated clocks configuration register - @RegisterBlock(offset: 0x90) - public var dckcfgr2: Register -} - -extension RCC { - /// clock control register - @Register(bitWidth: 32) - public struct CR { - /// PLLI2S clock ready flag - @ReadOnly(bits: 27..<28) - public var plli2srdy: PLLI2SRDY - - /// PLLI2S enable - @ReadWrite(bits: 26..<27) - public var plli2son: PLLI2SON - - /// Main PLL (PLL) clock ready flag - @ReadOnly(bits: 25..<26) - public var pllrdy: PLLRDY - - /// Main PLL (PLL) enable - @ReadWrite(bits: 24..<25) - public var pllon: PLLON - - /// Clock security system enable - @ReadWrite(bits: 19..<20, as: CSSONValues.self) - public var csson: CSSON - - /// HSE clock bypass - @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) - public var hsebyp: HSEBYP - - /// HSE clock ready flag - @ReadOnly(bits: 17..<18) - public var hserdy: HSERDY - - /// HSE clock enable - @ReadWrite(bits: 16..<17) - public var hseon: HSEON - - /// Internal high-speed clock calibration - @ReadOnly(bits: 8..<16) - public var hsical: HSICAL - - /// Internal high-speed clock trimming - @ReadWrite(bits: 3..<8) - public var hsitrim: HSITRIM - - /// Internal high-speed clock ready flag - @ReadOnly(bits: 1..<2) - public var hsirdy: HSIRDY - - /// Internal high-speed clock enable - @ReadWrite(bits: 0..<1, as: HSIONValues.self) - public var hsion: HSION - - /// PLLSAI clock ready flag - @ReadOnly(bits: 29..<30) - public var pllsairdy: PLLSAIRDY - - /// PLLSAI enable - @ReadWrite(bits: 28..<29) - public var pllsaion: PLLSAION - } - - /// PLL configuration register - @Register(bitWidth: 32) - public struct PLLCFGR { - /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) - public var pllsrc: PLLSRC - - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 0..<6) - public var pllm: PLLM - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 6..<15) - public var plln: PLLN - - /// Main PLL (PLL) division factor for main system clock - @ReadWrite(bits: 16..<18, as: PLLPValues.self) - public var pllp: PLLP - - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 24..<28) - public var pllq: PLLQ - } - - /// clock configuration register - @Register(bitWidth: 32) - public struct CFGR { - /// Microcontroller clock output 2 - @ReadWrite(bits: 30..<32, as: MCO2Values.self) - public var mco2: MCO2 - - /// MCO2 prescaler - @ReadWrite(bits: 27..<30) - public var mco2pre: MCO2PRE - - /// MCO1 prescaler - @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) - public var mco1pre: MCO1PRE - - /// I2S clock selection - @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) - public var i2ssrc: I2SSRC - - /// Microcontroller clock output 1 - @ReadWrite(bits: 21..<23, as: MCO1Values.self) - public var mco1: MCO1 - - /// HSE division factor for RTC clock - @ReadWrite(bits: 16..<21) - public var rtcpre: RTCPRE - - /// APB high-speed prescaler (APB2) - @ReadWrite(bits: 13..<16) - public var ppre2: PPRE2 - - /// APB Low speed prescaler (APB1) - @ReadWrite(bits: 10..<13, as: PPRE1Values.self) - public var ppre1: PPRE1 - - /// AHB prescaler - @ReadWrite(bits: 4..<8, as: HPREValues.self) - public var hpre: HPRE - - /// System clock switch - @Reserved(bits: 0..<2, as: SWValues.self) - public var sw: SW - - /// System clock switch status - @Reserved(bits: 2..<4) - public var sws: SWS - } - - /// clock interrupt register - @Register(bitWidth: 32) - public struct CIR { - /// Clock security system interrupt clear - @WriteOnly(bits: 23..<24) - public var cssc: CSSC - - /// PLLSAI Ready Interrupt Clear - @WriteOnly(bits: 22..<23) - public var pllsairdyc: PLLSAIRDYC - - /// PLLI2S ready interrupt clear - @WriteOnly(bits: 21..<22) - public var plli2srdyc: PLLI2SRDYC - - /// Main PLL(PLL) ready interrupt clear - @WriteOnly(bits: 20..<21) - public var pllrdyc: PLLRDYC - - /// HSE ready interrupt clear - @WriteOnly(bits: 19..<20) - public var hserdyc: HSERDYC - - /// HSI ready interrupt clear - @WriteOnly(bits: 18..<19) - public var hsirdyc: HSIRDYC - - /// LSE ready interrupt clear - @WriteOnly(bits: 17..<18) - public var lserdyc: LSERDYC - - /// LSI ready interrupt clear - @WriteOnly(bits: 16..<17) - public var lsirdyc: LSIRDYC - - /// PLLSAI Ready Interrupt Enable - @ReadWrite(bits: 14..<15) - public var pllsairdyie: PLLSAIRDYIE - - /// PLLI2S ready interrupt enable - @ReadWrite(bits: 13..<14) - public var plli2srdyie: PLLI2SRDYIE - - /// Main PLL (PLL) ready interrupt enable - @ReadWrite(bits: 12..<13) - public var pllrdyie: PLLRDYIE - - /// HSE ready interrupt enable - @ReadWrite(bits: 11..<12) - public var hserdyie: HSERDYIE - - /// HSI ready interrupt enable - @ReadWrite(bits: 10..<11) - public var hsirdyie: HSIRDYIE - - /// LSE ready interrupt enable - @ReadWrite(bits: 9..<10) - public var lserdyie: LSERDYIE - - /// LSI ready interrupt enable - @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) - public var lsirdyie: LSIRDYIE - - /// Clock security system interrupt flag - @ReadOnly(bits: 7..<8) - public var cssf: CSSF - - /// PLLSAI ready interrupt flag - @ReadOnly(bits: 6..<7) - public var pllsairdyf: PLLSAIRDYF - - /// PLLI2S ready interrupt flag - @ReadOnly(bits: 5..<6) - public var plli2srdyf: PLLI2SRDYF - - /// Main PLL (PLL) ready interrupt flag - @ReadOnly(bits: 4..<5) - public var pllrdyf: PLLRDYF - - /// HSE ready interrupt flag - @ReadOnly(bits: 3..<4) - public var hserdyf: HSERDYF - - /// HSI ready interrupt flag - @ReadOnly(bits: 2..<3) - public var hsirdyf: HSIRDYF - - /// LSE ready interrupt flag - @ReadOnly(bits: 1..<2) - public var lserdyf: LSERDYF - - /// LSI ready interrupt flag - @ReadOnly(bits: 0..<1) - public var lsirdyf: LSIRDYF - } - - /// AHB1 peripheral reset register - @Register(bitWidth: 32) - public struct AHB1RSTR { - /// USB OTG HS module reset - @ReadWrite(bits: 29..<30) - public var otghsrst: OTGHSRST - - /// Ethernet MAC reset - @ReadWrite(bits: 25..<26) - public var ethmacrst: ETHMACRST - - /// DMA2D reset - @ReadWrite(bits: 23..<24) - public var dma2drst: DMA2DRST - - /// DMA2 reset - @ReadWrite(bits: 22..<23) - public var dma2rst: DMA2RST - - /// DMA2 reset - @ReadWrite(bits: 21..<22) - public var dma1rst: DMA1RST - - /// CRC reset - @ReadWrite(bits: 12..<13) - public var crcrst: CRCRST - - /// IO port K reset - @ReadWrite(bits: 10..<11) - public var gpiokrst: GPIOKRST - - /// IO port J reset - @ReadWrite(bits: 9..<10) - public var gpiojrst: GPIOJRST - - /// IO port I reset - @ReadWrite(bits: 8..<9) - public var gpioirst: GPIOIRST - - /// IO port H reset - @ReadWrite(bits: 7..<8) - public var gpiohrst: GPIOHRST - - /// IO port G reset - @ReadWrite(bits: 6..<7) - public var gpiogrst: GPIOGRST - - /// IO port F reset - @ReadWrite(bits: 5..<6) - public var gpiofrst: GPIOFRST - - /// IO port E reset - @ReadWrite(bits: 4..<5) - public var gpioerst: GPIOERST - - /// IO port D reset - @ReadWrite(bits: 3..<4) - public var gpiodrst: GPIODRST - - /// IO port C reset - @ReadWrite(bits: 2..<3) - public var gpiocrst: GPIOCRST - - /// IO port B reset - @ReadWrite(bits: 1..<2) - public var gpiobrst: GPIOBRST - - /// IO port A reset - @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) - public var gpioarst: GPIOARST - } - - /// AHB2 peripheral reset register - @Register(bitWidth: 32) - public struct AHB2RSTR { - /// USB OTG FS module reset - @ReadWrite(bits: 7..<8) - public var otgfsrst: OTGFSRST - - /// Random number generator module reset - @ReadWrite(bits: 6..<7) - public var rngrst: RNGRST - - /// Hash module reset - @ReadWrite(bits: 5..<6) - public var hsahrst: HSAHRST - - /// Cryptographic module reset - @ReadWrite(bits: 4..<5) - public var cryprst: CRYPRST - - /// Camera interface reset - @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) - public var dcmirst: DCMIRST - } - - /// AHB3 peripheral reset register - @Register(bitWidth: 32) - public struct AHB3RSTR { - /// Flexible memory controller module reset - @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) - public var fmcrst: FMCRST - - /// Quad SPI memory controller reset - @ReadWrite(bits: 1..<2) - public var qspirst: QSPIRST - } - - /// APB1 peripheral reset register - @Register(bitWidth: 32) - public struct APB1RSTR { - /// TIM2 reset - @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) - public var tim2rst: TIM2RST - - /// TIM3 reset - @ReadWrite(bits: 1..<2) - public var tim3rst: TIM3RST - - /// TIM4 reset - @ReadWrite(bits: 2..<3) - public var tim4rst: TIM4RST - - /// TIM5 reset - @ReadWrite(bits: 3..<4) - public var tim5rst: TIM5RST - - /// TIM6 reset - @ReadWrite(bits: 4..<5) - public var tim6rst: TIM6RST - - /// TIM7 reset - @ReadWrite(bits: 5..<6) - public var tim7rst: TIM7RST - - /// TIM12 reset - @ReadWrite(bits: 6..<7) - public var tim12rst: TIM12RST - - /// TIM13 reset - @ReadWrite(bits: 7..<8) - public var tim13rst: TIM13RST - - /// TIM14 reset - @ReadWrite(bits: 8..<9) - public var tim14rst: TIM14RST - - /// Window watchdog reset - @ReadWrite(bits: 11..<12) - public var wwdgrst: WWDGRST - - /// SPI 2 reset - @ReadWrite(bits: 14..<15) - public var spi2rst: SPI2RST - - /// SPI 3 reset - @ReadWrite(bits: 15..<16) - public var spi3rst: SPI3RST - - /// USART 2 reset - @ReadWrite(bits: 17..<18) - public var usart2rst: USART2RST - - /// USART 3 reset - @ReadWrite(bits: 18..<19) - public var usart3rst: USART3RST - - /// USART 4 reset - @ReadWrite(bits: 19..<20) - public var uart4rst: UART4RST - - /// USART 5 reset - @ReadWrite(bits: 20..<21) - public var uart5rst: UART5RST - - /// I2C 1 reset - @ReadWrite(bits: 21..<22) - public var i2c1rst: I2C1RST - - /// I2C 2 reset - @ReadWrite(bits: 22..<23) - public var i2c2rst: I2C2RST - - /// I2C3 reset - @ReadWrite(bits: 23..<24) - public var i2c3rst: I2C3RST - - /// CAN1 reset - @ReadWrite(bits: 25..<26) - public var can1rst: CAN1RST - - /// CAN2 reset - @ReadWrite(bits: 26..<27) - public var can2rst: CAN2RST - - /// Power interface reset - @ReadWrite(bits: 28..<29) - public var pwrrst: PWRRST - - /// DAC reset - @ReadWrite(bits: 29..<30) - public var dacrst: DACRST - - /// UART7 reset - @ReadWrite(bits: 30..<31) - public var uart7rst: UART7RST - - /// UART8 reset - @ReadWrite(bits: 31..<32) - public var uart8rst: UART8RST - - /// SPDIF-RX reset - @ReadWrite(bits: 16..<17) - public var spdifrxrst: SPDIFRXRST - - /// HDMI-CEC reset - @ReadWrite(bits: 27..<28) - public var cecrst: CECRST - - /// Low power timer 1 reset - @ReadWrite(bits: 9..<10) - public var lptim1rst: LPTIM1RST - - /// I2C 4 reset - @ReadWrite(bits: 24..<25) - public var i2c4rst: I2C4RST - } - - /// APB2 peripheral reset register - @Register(bitWidth: 32) - public struct APB2RSTR { - /// TIM1 reset - @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) - public var tim1rst: TIM1RST - - /// TIM8 reset - @ReadWrite(bits: 1..<2) - public var tim8rst: TIM8RST - - /// USART1 reset - @ReadWrite(bits: 4..<5) - public var usart1rst: USART1RST - - /// USART6 reset - @ReadWrite(bits: 5..<6) - public var usart6rst: USART6RST - - /// ADC interface reset (common to all ADCs) - @ReadWrite(bits: 8..<9) - public var adcrst: ADCRST - - /// SPI 1 reset - @ReadWrite(bits: 12..<13) - public var spi1rst: SPI1RST - - /// SPI4 reset - @ReadWrite(bits: 13..<14) - public var spi4rst: SPI4RST - - /// System configuration controller reset - @ReadWrite(bits: 14..<15) - public var syscfgrst: SYSCFGRST - - /// TIM9 reset - @ReadWrite(bits: 16..<17) - public var tim9rst: TIM9RST - - /// TIM10 reset - @ReadWrite(bits: 17..<18) - public var tim10rst: TIM10RST - - /// TIM11 reset - @ReadWrite(bits: 18..<19) - public var tim11rst: TIM11RST - - /// SPI5 reset - @ReadWrite(bits: 20..<21) - public var spi5rst: SPI5RST - - /// SPI6 reset - @ReadWrite(bits: 21..<22) - public var spi6rst: SPI6RST - - /// SAI1 reset - @ReadWrite(bits: 22..<23) - public var sai1rst: SAI1RST - - /// LTDC reset - @ReadWrite(bits: 26..<27) - public var ltdcrst: LTDCRST - - /// SAI2 reset - @ReadWrite(bits: 23..<24) - public var sai2rst: SAI2RST - - /// SDMMC1 reset - @ReadWrite(bits: 11..<12) - public var sdmmc1rst: SDMMC1RST - } - - /// AHB1 peripheral clock register - @Register(bitWidth: 32) - public struct AHB1ENR { - /// USB OTG HSULPI clock enable - @ReadWrite(bits: 30..<31) - public var otghsulpien: OTGHSULPIEN - - /// USB OTG HS clock enable - @ReadWrite(bits: 29..<30) - public var otghsen: OTGHSEN - - /// Ethernet PTP clock enable - @ReadWrite(bits: 28..<29) - public var ethmacptpen: ETHMACPTPEN - - /// Ethernet Reception clock enable - @ReadWrite(bits: 27..<28) - public var ethmacrxen: ETHMACRXEN - - /// Ethernet Transmission clock enable - @ReadWrite(bits: 26..<27) - public var ethmactxen: ETHMACTXEN - - /// Ethernet MAC clock enable - @ReadWrite(bits: 25..<26) - public var ethmacen: ETHMACEN - - /// DMA2D clock enable - @ReadWrite(bits: 23..<24) - public var dma2den: DMA2DEN - - /// DMA2 clock enable - @ReadWrite(bits: 22..<23) - public var dma2en: DMA2EN - - /// DMA1 clock enable - @ReadWrite(bits: 21..<22) - public var dma1en: DMA1EN - - /// CCM data RAM clock enable - @ReadWrite(bits: 20..<21) - public var dtcmramen: DTCMRAMEN - - /// Backup SRAM interface clock enable - @ReadWrite(bits: 18..<19) - public var bkpsramen: BKPSRAMEN - - /// CRC clock enable - @ReadWrite(bits: 12..<13) - public var crcen: CRCEN - - /// IO port K clock enable - @ReadWrite(bits: 10..<11) - public var gpioken: GPIOKEN - - /// IO port J clock enable - @ReadWrite(bits: 9..<10) - public var gpiojen: GPIOJEN - - /// IO port I clock enable - @ReadWrite(bits: 8..<9) - public var gpioien: GPIOIEN - - /// IO port H clock enable - @ReadWrite(bits: 7..<8) - public var gpiohen: GPIOHEN - - /// IO port G clock enable - @ReadWrite(bits: 6..<7) - public var gpiogen: GPIOGEN - - /// IO port F clock enable - @ReadWrite(bits: 5..<6) - public var gpiofen: GPIOFEN - - /// IO port E clock enable - @ReadWrite(bits: 4..<5) - public var gpioeen: GPIOEEN - - /// IO port D clock enable - @ReadWrite(bits: 3..<4) - public var gpioden: GPIODEN - - /// IO port C clock enable - @ReadWrite(bits: 2..<3) - public var gpiocen: GPIOCEN - - /// IO port B clock enable - @ReadWrite(bits: 1..<2) - public var gpioben: GPIOBEN - - /// IO port A clock enable - @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) - public var gpioaen: GPIOAEN - } - - /// AHB2 peripheral clock enable register - @Register(bitWidth: 32) - public struct AHB2ENR { - /// USB OTG FS clock enable - @ReadWrite(bits: 7..<8) - public var otgfsen: OTGFSEN - - /// Random number generator clock enable - @ReadWrite(bits: 6..<7) - public var rngen: RNGEN - - /// Hash modules clock enable - @ReadWrite(bits: 5..<6) - public var hashen: HASHEN - - /// Cryptographic modules clock enable - @ReadWrite(bits: 4..<5) - public var crypen: CRYPEN - - /// Camera interface enable - @ReadWrite(bits: 0..<1, as: DCMIENValues.self) - public var dcmien: DCMIEN - } - - /// AHB3 peripheral clock enable register - @Register(bitWidth: 32) - public struct AHB3ENR { - /// Flexible memory controller module clock enable - @ReadWrite(bits: 0..<1, as: FMCENValues.self) - public var fmcen: FMCEN - - /// Quad SPI memory controller clock enable - @ReadWrite(bits: 1..<2) - public var qspien: QSPIEN - } - - /// APB1 peripheral clock enable register - @Register(bitWidth: 32) - public struct APB1ENR { - /// TIM2 clock enable - @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) - public var tim2en: TIM2EN - - /// TIM3 clock enable - @ReadWrite(bits: 1..<2) - public var tim3en: TIM3EN - - /// TIM4 clock enable - @ReadWrite(bits: 2..<3) - public var tim4en: TIM4EN - - /// TIM5 clock enable - @ReadWrite(bits: 3..<4) - public var tim5en: TIM5EN - - /// TIM6 clock enable - @ReadWrite(bits: 4..<5) - public var tim6en: TIM6EN - - /// TIM7 clock enable - @ReadWrite(bits: 5..<6) - public var tim7en: TIM7EN - - /// TIM12 clock enable - @ReadWrite(bits: 6..<7) - public var tim12en: TIM12EN - - /// TIM13 clock enable - @ReadWrite(bits: 7..<8) - public var tim13en: TIM13EN - - /// TIM14 clock enable - @ReadWrite(bits: 8..<9) - public var tim14en: TIM14EN - - /// Window watchdog clock enable - @ReadWrite(bits: 11..<12) - public var wwdgen: WWDGEN - - /// SPI2 clock enable - @ReadWrite(bits: 14..<15) - public var spi2en: SPI2EN - - /// SPI3 clock enable - @ReadWrite(bits: 15..<16) - public var spi3en: SPI3EN - - /// USART 2 clock enable - @ReadWrite(bits: 17..<18) - public var usart2en: USART2EN - - /// USART3 clock enable - @ReadWrite(bits: 18..<19) - public var usart3en: USART3EN - - /// UART4 clock enable - @ReadWrite(bits: 19..<20) - public var uart4en: UART4EN - - /// UART5 clock enable - @ReadWrite(bits: 20..<21) - public var uart5en: UART5EN - - /// I2C1 clock enable - @ReadWrite(bits: 21..<22) - public var i2c1en: I2C1EN - - /// I2C2 clock enable - @ReadWrite(bits: 22..<23) - public var i2c2en: I2C2EN - - /// I2C3 clock enable - @ReadWrite(bits: 23..<24) - public var i2c3en: I2C3EN - - /// CAN 1 clock enable - @ReadWrite(bits: 25..<26) - public var can1en: CAN1EN - - /// CAN 2 clock enable - @ReadWrite(bits: 26..<27) - public var can2en: CAN2EN - - /// Power interface clock enable - @ReadWrite(bits: 28..<29) - public var pwren: PWREN - - /// DAC interface clock enable - @ReadWrite(bits: 29..<30) - public var dacen: DACEN - - /// UART7 clock enable - @ReadWrite(bits: 30..<31) - public var uart7en: UART7EN - - /// UART8 clock enable - @ReadWrite(bits: 31..<32) - public var uart8en: UART8EN - - /// SPDIF-RX clock enable - @ReadWrite(bits: 16..<17) - public var spdifrxen: SPDIFRXEN - - /// HDMI-CEN clock enable - @ReadWrite(bits: 27..<28) - public var cecen: CECEN - - /// Low power timer 1 clock enable - @ReadWrite(bits: 9..<10) - public var lptim1en: LPTIM1EN - - /// I2C4 clock enable - @ReadWrite(bits: 24..<25) - public var i2c4en: I2C4EN - } - - /// APB2 peripheral clock enable register - @Register(bitWidth: 32) - public struct APB2ENR { - /// TIM1 clock enable - @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) - public var tim1en: TIM1EN - - /// TIM8 clock enable - @ReadWrite(bits: 1..<2) - public var tim8en: TIM8EN - - /// USART1 clock enable - @ReadWrite(bits: 4..<5) - public var usart1en: USART1EN - - /// USART6 clock enable - @ReadWrite(bits: 5..<6) - public var usart6en: USART6EN - - /// ADC1 clock enable - @ReadWrite(bits: 8..<9) - public var adc1en: ADC1EN - - /// ADC2 clock enable - @ReadWrite(bits: 9..<10) - public var adc2en: ADC2EN - - /// ADC3 clock enable - @ReadWrite(bits: 10..<11) - public var adc3en: ADC3EN - - /// SPI1 clock enable - @ReadWrite(bits: 12..<13) - public var spi1en: SPI1EN - - /// SPI4 clock enable - @ReadWrite(bits: 13..<14) - public var spi4en: SPI4EN - - /// System configuration controller clock enable - @ReadWrite(bits: 14..<15) - public var syscfgen: SYSCFGEN - - /// TIM9 clock enable - @ReadWrite(bits: 16..<17) - public var tim9en: TIM9EN - - /// TIM10 clock enable - @ReadWrite(bits: 17..<18) - public var tim10en: TIM10EN - - /// TIM11 clock enable - @ReadWrite(bits: 18..<19) - public var tim11en: TIM11EN - - /// SPI5 clock enable - @ReadWrite(bits: 20..<21) - public var spi5en: SPI5EN - - /// SPI6 clock enable - @ReadWrite(bits: 21..<22) - public var spi6en: SPI6EN - - /// SAI1 clock enable - @ReadWrite(bits: 22..<23) - public var sai1en: SAI1EN - - /// LTDC clock enable - @ReadWrite(bits: 26..<27) - public var ltdcen: LTDCEN - - /// SAI2 clock enable - @ReadWrite(bits: 23..<24) - public var sai2en: SAI2EN - - /// SDMMC1 clock enable - @ReadWrite(bits: 11..<12) - public var sdmmc1en: SDMMC1EN - } - - /// AHB1 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB1LPENR { - /// IO port A clock enable during sleep mode - @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) - public var gpioalpen: GPIOALPEN - - /// IO port B clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var gpioblpen: GPIOBLPEN - - /// IO port C clock enable during Sleep mode - @ReadWrite(bits: 2..<3) - public var gpioclpen: GPIOCLPEN - - /// IO port D clock enable during Sleep mode - @ReadWrite(bits: 3..<4) - public var gpiodlpen: GPIODLPEN - - /// IO port E clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var gpioelpen: GPIOELPEN - - /// IO port F clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var gpioflpen: GPIOFLPEN - - /// IO port G clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var gpioglpen: GPIOGLPEN - - /// IO port H clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var gpiohlpen: GPIOHLPEN - - /// IO port I clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var gpioilpen: GPIOILPEN - - /// IO port J clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var gpiojlpen: GPIOJLPEN - - /// IO port K clock enable during Sleep mode - @ReadWrite(bits: 10..<11) - public var gpioklpen: GPIOKLPEN - - /// CRC clock enable during Sleep mode - @ReadWrite(bits: 12..<13) - public var crclpen: CRCLPEN - - /// Flash interface clock enable during Sleep mode - @ReadWrite(bits: 15..<16) - public var flitflpen: FLITFLPEN - - /// SRAM 1interface clock enable during Sleep mode - @ReadWrite(bits: 16..<17) - public var sram1lpen: SRAM1LPEN - - /// SRAM 2 interface clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var sram2lpen: SRAM2LPEN - - /// Backup SRAM interface clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var bkpsramlpen: BKPSRAMLPEN - - /// SRAM 3 interface clock enable during Sleep mode - @ReadWrite(bits: 19..<20) - public var sram3lpen: SRAM3LPEN - - /// DMA1 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var dma1lpen: DMA1LPEN - - /// DMA2 clock enable during Sleep mode - @ReadWrite(bits: 22..<23) - public var dma2lpen: DMA2LPEN - - /// DMA2D clock enable during Sleep mode - @ReadWrite(bits: 23..<24) - public var dma2dlpen: DMA2DLPEN - - /// Ethernet MAC clock enable during Sleep mode - @ReadWrite(bits: 25..<26) - public var ethmaclpen: ETHMACLPEN - - /// Ethernet transmission clock enable during Sleep mode - @ReadWrite(bits: 26..<27) - public var ethmactxlpen: ETHMACTXLPEN - - /// Ethernet reception clock enable during Sleep mode - @ReadWrite(bits: 27..<28) - public var ethmacrxlpen: ETHMACRXLPEN - - /// Ethernet PTP clock enable during Sleep mode - @ReadWrite(bits: 28..<29) - public var ethmacptplpen: ETHMACPTPLPEN - - /// USB OTG HS clock enable during Sleep mode - @ReadWrite(bits: 29..<30) - public var otghslpen: OTGHSLPEN - - /// USB OTG HS ULPI clock enable during Sleep mode - @ReadWrite(bits: 30..<31) - public var otghsulpilpen: OTGHSULPILPEN - - /// AXI to AHB bridge clock enable during Sleep mode - @ReadWrite(bits: 13..<14) - public var axilpen: AXILPEN - - /// DTCM RAM interface clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var dtcmlpen: DTCMLPEN - } - - /// AHB2 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB2LPENR { - /// USB OTG FS clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var otgfslpen: OTGFSLPEN - - /// Random number generator clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var rnglpen: RNGLPEN - - /// Hash modules clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var hashlpen: HASHLPEN - - /// Cryptography modules clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var cryplpen: CRYPLPEN - - /// Camera interface enable during Sleep mode - @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) - public var dcmilpen: DCMILPEN - } - - /// AHB3 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB3LPENR { - /// Flexible memory controller module clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) - public var fmclpen: FMCLPEN - - /// Quand SPI memory controller clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var qspilpen: QSPILPEN - } - - /// APB1 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct APB1LPENR { - /// TIM2 clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) - public var tim2lpen: TIM2LPEN - - /// TIM3 clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var tim3lpen: TIM3LPEN - - /// TIM4 clock enable during Sleep mode - @ReadWrite(bits: 2..<3) - public var tim4lpen: TIM4LPEN - - /// TIM5 clock enable during Sleep mode - @ReadWrite(bits: 3..<4) - public var tim5lpen: TIM5LPEN - - /// TIM6 clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var tim6lpen: TIM6LPEN - - /// TIM7 clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var tim7lpen: TIM7LPEN - - /// TIM12 clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var tim12lpen: TIM12LPEN - - /// TIM13 clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var tim13lpen: TIM13LPEN - - /// TIM14 clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var tim14lpen: TIM14LPEN - - /// Window watchdog clock enable during Sleep mode - @ReadWrite(bits: 11..<12) - public var wwdglpen: WWDGLPEN - - /// SPI2 clock enable during Sleep mode - @ReadWrite(bits: 14..<15) - public var spi2lpen: SPI2LPEN - - /// SPI3 clock enable during Sleep mode - @ReadWrite(bits: 15..<16) - public var spi3lpen: SPI3LPEN - - /// USART2 clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var usart2lpen: USART2LPEN - - /// USART3 clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var usart3lpen: USART3LPEN - - /// UART4 clock enable during Sleep mode - @ReadWrite(bits: 19..<20) - public var uart4lpen: UART4LPEN - - /// UART5 clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var uart5lpen: UART5LPEN - - /// I2C1 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var i2c1lpen: I2C1LPEN - - /// I2C2 clock enable during Sleep mode - @ReadWrite(bits: 22..<23) - public var i2c2lpen: I2C2LPEN - - /// I2C3 clock enable during Sleep mode - @ReadWrite(bits: 23..<24) - public var i2c3lpen: I2C3LPEN - - /// CAN 1 clock enable during Sleep mode - @ReadWrite(bits: 25..<26) - public var can1lpen: CAN1LPEN - - /// CAN 2 clock enable during Sleep mode - @ReadWrite(bits: 26..<27) - public var can2lpen: CAN2LPEN - - /// Power interface clock enable during Sleep mode - @ReadWrite(bits: 28..<29) - public var pwrlpen: PWRLPEN - - /// DAC interface clock enable during Sleep mode - @ReadWrite(bits: 29..<30) - public var daclpen: DACLPEN - - /// UART7 clock enable during Sleep mode - @ReadWrite(bits: 30..<31) - public var uart7lpen: UART7LPEN - - /// UART8 clock enable during Sleep mode - @ReadWrite(bits: 31..<32) - public var uart8lpen: UART8LPEN - - /// SPDIF-RX clock enable during sleep mode - @ReadWrite(bits: 16..<17) - public var spdifrxlpen: SPDIFRXLPEN - - /// HDMI-CEN clock enable during Sleep mode - @ReadWrite(bits: 27..<28) - public var ceclpen: CECLPEN - - /// low power timer 1 clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var lptim1lpen: LPTIM1LPEN - - /// I2C4 clock enable during Sleep mode - @ReadWrite(bits: 24..<25) - public var i2c4lpen: I2C4LPEN - } - - /// APB2 peripheral clock enabled in low power mode register - @Register(bitWidth: 32) - public struct APB2LPENR { - /// TIM1 clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) - public var tim1lpen: TIM1LPEN - - /// TIM8 clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var tim8lpen: TIM8LPEN - - /// USART1 clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var usart1lpen: USART1LPEN - - /// USART6 clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var usart6lpen: USART6LPEN - - /// ADC1 clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var adc1lpen: ADC1LPEN - - /// ADC2 clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var adc2lpen: ADC2LPEN - - /// ADC 3 clock enable during Sleep mode - @ReadWrite(bits: 10..<11) - public var adc3lpen: ADC3LPEN - - /// SPI 1 clock enable during Sleep mode - @ReadWrite(bits: 12..<13) - public var spi1lpen: SPI1LPEN - - /// SPI 4 clock enable during Sleep mode - @ReadWrite(bits: 13..<14) - public var spi4lpen: SPI4LPEN - - /// System configuration controller clock enable during Sleep mode - @ReadWrite(bits: 14..<15) - public var syscfglpen: SYSCFGLPEN - - /// TIM9 clock enable during sleep mode - @ReadWrite(bits: 16..<17) - public var tim9lpen: TIM9LPEN - - /// TIM10 clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var tim10lpen: TIM10LPEN - - /// TIM11 clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var tim11lpen: TIM11LPEN - - /// SPI 5 clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var spi5lpen: SPI5LPEN - - /// SPI 6 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var spi6lpen: SPI6LPEN - - /// SAI1 clock enable during sleep mode - @ReadWrite(bits: 22..<23) - public var sai1lpen: SAI1LPEN - - /// LTDC clock enable during sleep mode - @ReadWrite(bits: 26..<27) - public var ltdclpen: LTDCLPEN - - /// SAI2 clock enable during sleep mode - @ReadWrite(bits: 23..<24) - public var sai2lpen: SAI2LPEN - - /// SDMMC1 clock enable during Sleep mode - @ReadWrite(bits: 11..<12) - public var sdmmc1lpen: SDMMC1LPEN - } - - /// Backup domain control register - @Register(bitWidth: 32) - public struct BDCR { - /// Backup domain software reset - @ReadWrite(bits: 16..<17, as: BDRSTValues.self) - public var bdrst: BDRST - - /// RTC clock enable - @ReadWrite(bits: 15..<16, as: RTCENValues.self) - public var rtcen: RTCEN - - /// External low-speed oscillator bypass - @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) - public var lsebyp: LSEBYP - - /// External low-speed oscillator ready - @ReadOnly(bits: 1..<2) - public var lserdy: LSERDY - - /// External low-speed oscillator enable - @ReadWrite(bits: 0..<1, as: LSEONValues.self) - public var lseon: LSEON - - /// LSE oscillator drive capability - @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) - public var lsedrv: LSEDRV - - /// RTC clock source selection - @Reserved(bits: 8..<10, as: RTCSELValues.self) - public var rtcsel: RTCSEL - } - - /// clock control & status register - @Register(bitWidth: 32) - public struct CSR { - /// Low-power reset flag - @ReadWrite(bits: 31..<32) - public var lpwrrstf: LPWRRSTF - - /// Window watchdog reset flag - @ReadWrite(bits: 30..<31) - public var wwdgrstf: WWDGRSTF - - /// Independent watchdog reset flag - @ReadWrite(bits: 29..<30) - public var wdgrstf: WDGRSTF - - /// Software reset flag - @ReadWrite(bits: 28..<29) - public var sftrstf: SFTRSTF - - /// POR/PDR reset flag - @ReadWrite(bits: 27..<28) - public var porrstf: PORRSTF - - /// PIN reset flag - @ReadWrite(bits: 26..<27) - public var padrstf: PADRSTF - - /// BOR reset flag - @ReadWrite(bits: 25..<26) - public var borrstf: BORRSTF - - /// Remove reset flag - @ReadWrite(bits: 24..<25) - public var rmvf: RMVF - - /// Internal low-speed oscillator ready - @ReadOnly(bits: 1..<2) - public var lsirdy: LSIRDY - - /// Internal low-speed oscillator enable - @ReadWrite(bits: 0..<1, as: LSIONValues.self) - public var lsion: LSION - } - - /// spread spectrum clock generation register - @Register(bitWidth: 32) - public struct SSCGR { - /// Spread spectrum modulation enable - @ReadWrite(bits: 31..<32, as: SSCGENValues.self) - public var sscgen: SSCGEN - - /// Spread Select - @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) - public var spreadsel: SPREADSEL - - /// Incrementation step - @ReadWrite(bits: 13..<28) - public var incstep: INCSTEP - - /// Modulation period - @ReadWrite(bits: 0..<13) - public var modper: MODPER - } - - /// PLLI2S configuration register - @Register(bitWidth: 32) - public struct PLLI2SCFGR { - /// PLLI2S division factor for I2S clocks - @ReadWrite(bits: 28..<31) - public var plli2sr: PLLI2SR - - /// PLLI2S division factor for SAI1 clock - @ReadWrite(bits: 24..<28) - public var plli2sq: PLLI2SQ - - /// PLLI2S multiplication factor for VCO - @ReadWrite(bits: 6..<15) - public var plli2sn: PLLI2SN - - /// PLLI2S division factor for SPDIFRX clock - @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) - public var plli2sp: PLLI2SP - } - - /// PLL configuration register - @Register(bitWidth: 32) - public struct PLLSAICFGR { - /// PLLSAI division factor for VCO - @ReadWrite(bits: 6..<15) - public var pllsain: PLLSAIN - - /// PLLSAI division factor for 48MHz clock - @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) - public var pllsaip: PLLSAIP - - /// PLLSAI division factor for SAI clock - @ReadWrite(bits: 24..<28) - public var pllsaiq: PLLSAIQ - - /// PLLSAI division factor for LCD clock - @ReadWrite(bits: 28..<31) - public var pllsair: PLLSAIR - } - - /// dedicated clocks configuration register - @Register(bitWidth: 32) - public struct DCKCFGR1 { - /// PLLI2S division factor for SAI1 clock - @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) - public var plli2sdivq: PLLI2SDIVQ - - /// PLLSAI division factor for SAI1 clock - @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) - public var pllsaidivq: PLLSAIDIVQ - - /// division factor for LCD_CLK - @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) - public var pllsaidivr: PLLSAIDIVR - - /// SAI1 clock source selection - @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) - public var sai1sel: SAI1SEL - - /// SAI2 clock source selection - @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) - public var sai2sel: SAI2SEL - - /// Timers clocks prescalers selection - @ReadWrite(bits: 24..<25, as: TIMPREValues.self) - public var timpre: TIMPRE - } - - /// dedicated clocks configuration register - @Register(bitWidth: 32) - public struct DCKCFGR2 { - /// USART 1 clock source selection - @ReadWrite(bits: 0..<2, as: USART1SELValues.self) - public var usart1sel: USART1SEL - - /// USART 2 clock source selection - @ReadWrite(bits: 2..<4, as: USART2SELValues.self) - public var usart2sel: USART2SEL - - /// USART 3 clock source selection - @ReadWrite(bits: 4..<6) - public var usart3sel: USART3SEL - - /// UART 4 clock source selection - @ReadWrite(bits: 6..<8) - public var uart4sel: UART4SEL - - /// UART 5 clock source selection - @ReadWrite(bits: 8..<10) - public var uart5sel: UART5SEL - - /// USART 6 clock source selection - @ReadWrite(bits: 10..<12) - public var usart6sel: USART6SEL - - /// UART 7 clock source selection - @ReadWrite(bits: 12..<14) - public var uart7sel: UART7SEL - - /// UART 8 clock source selection - @ReadWrite(bits: 14..<16) - public var uart8sel: UART8SEL - - /// I2C1 clock source selection - @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) - public var i2c1sel: I2C1SEL - - /// I2C2 clock source selection - @ReadWrite(bits: 18..<20) - public var i2c2sel: I2C2SEL - - /// I2C3 clock source selection - @ReadWrite(bits: 20..<22) - public var i2c3sel: I2C3SEL - - /// I2C4 clock source selection - @ReadWrite(bits: 22..<24) - public var i2c4sel: I2C4SEL - - /// Low power timer 1 clock source selection - @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) - public var lptim1sel: LPTIM1SEL - - /// HDMI-CEC clock source selection - @ReadWrite(bits: 26..<27, as: CECSELValues.self) - public var cecsel: CECSEL - - /// 48MHz clock source selection - @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) - public var ck48msel: CK48MSEL - - /// SDMMC clock source selection - @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) - public var sdmmc1sel: SDMMC1SEL - } -} - -extension RCC.CR { - public struct CSSONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Clock security system disabled (clock detector OFF) - public static let Off = Self(rawValue: 0x0) - - /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CR { - public struct HSEBYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// HSE crystal oscillator not bypassed - public static let NotBypassed = Self(rawValue: 0x0) - - /// HSE crystal oscillator bypassed with external clock - public static let Bypassed = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CR { - public struct HSIONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Clock Off - public static let Off = Self(rawValue: 0x0) - - /// Clock On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLCFGR { - public struct PLLSRCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// HSI clock selected as PLL and PLLI2S clock entry - public static let HSI = Self(rawValue: 0x0) - - /// HSE oscillator clock selected as PLL and PLLI2S clock entry - public static let HSE = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLCFGR { - public struct PLLPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLLP=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLLP=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLLP=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLLP=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO2Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// System clock (SYSCLK) selected - public static let SYSCLK = Self(rawValue: 0x0) - - /// PLLI2S clock selected - public static let PLLI2S = Self(rawValue: 0x1) - - /// HSE oscillator clock selected - public static let HSE = Self(rawValue: 0x2) - - /// PLL clock selected - public static let PLL = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO1PREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// No division - public static let Div1 = Self(rawValue: 0x0) - - /// Division by 2 - public static let Div2 = Self(rawValue: 0x4) - - /// Division by 3 - public static let Div3 = Self(rawValue: 0x5) - - /// Division by 4 - public static let Div4 = Self(rawValue: 0x6) - - /// Division by 5 - public static let Div5 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct I2SSRCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// PLLI2S clock used as I2S clock source - public static let PLLI2S = Self(rawValue: 0x0) - - /// External clock mapped on the I2S_CKIN pin used as I2S clock source - public static let CKIN = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// HSI clock selected - public static let HSI = Self(rawValue: 0x0) - - /// LSE oscillator selected - public static let LSE = Self(rawValue: 0x1) - - /// HSE oscillator clock selected - public static let HSE = Self(rawValue: 0x2) - - /// PLL clock selected - public static let PLL = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct PPRE1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// HCLK not divided - public static let Div1 = Self(rawValue: 0x0) - - /// HCLK divided by 2 - public static let Div2 = Self(rawValue: 0x4) - - /// HCLK divided by 4 - public static let Div4 = Self(rawValue: 0x5) - - /// HCLK divided by 8 - public static let Div8 = Self(rawValue: 0x6) - - /// HCLK divided by 16 - public static let Div16 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct HPREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// SYSCLK not divided - public static let Div1 = Self(rawValue: 0x0) - - /// SYSCLK divided by 2 - public static let Div2 = Self(rawValue: 0x8) - - /// SYSCLK divided by 4 - public static let Div4 = Self(rawValue: 0x9) - - /// SYSCLK divided by 8 - public static let Div8 = Self(rawValue: 0xa) - - /// SYSCLK divided by 16 - public static let Div16 = Self(rawValue: 0xb) - - /// SYSCLK divided by 64 - public static let Div64 = Self(rawValue: 0xc) - - /// SYSCLK divided by 128 - public static let Div128 = Self(rawValue: 0xd) - - /// SYSCLK divided by 256 - public static let Div256 = Self(rawValue: 0xe) - - /// SYSCLK divided by 512 - public static let Div512 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct SWValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// HSI selected as system clock - public static let HSI = Self(rawValue: 0x0) - - /// HSE selected as system clock - public static let HSE = Self(rawValue: 0x1) - - /// PLL selected as system clock - public static let PLL = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CIR { - public struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1RSTR { - public struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2RSTR { - public struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3RSTR { - public struct FMCRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1RSTR { - public struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2RSTR { - public struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1ENR { - public struct GPIOAENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2ENR { - public struct DCMIENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3ENR { - public struct FMCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1ENR { - public struct TIM2ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2ENR { - public struct TIM1ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1LPENR { - public struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2LPENR { - public struct DCMILPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3LPENR { - public struct FMCLPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1LPENR { - public struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2LPENR { - public struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct BDRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset not activated - public static let Disabled = Self(rawValue: 0x0) - - /// Reset the entire RTC domain - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct RTCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RTC clock disabled - public static let Disabled = Self(rawValue: 0x0) - - /// RTC clock enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEBYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE crystal oscillator not bypassed - public static let NotBypassed = Self(rawValue: 0x0) - - /// LSE crystal oscillator bypassed with external clock - public static let Bypassed = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE oscillator Off - public static let Off = Self(rawValue: 0x0) - - /// LSE oscillator On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEDRVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Low drive capacity - public static let Low = Self(rawValue: 0x0) - - /// Medium-high drive capacity - public static let MediumHigh = Self(rawValue: 0x1) - - /// Medium-low drive capacity - public static let MediumLow = Self(rawValue: 0x2) - - /// High drive capacity - public static let High = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct RTCSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// No clock - public static let NoClock = Self(rawValue: 0x0) - - /// LSE oscillator clock used as RTC clock - public static let LSE = Self(rawValue: 0x1) - - /// LSI oscillator clock used as RTC clock - public static let LSI = Self(rawValue: 0x2) - - /// HSE oscillator clock divided by a prescaler used as RTC clock - public static let HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CSR { - public struct LSIONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSI oscillator Off - public static let Off = Self(rawValue: 0x0) - - /// LSI oscillator On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.SSCGR { - public struct SSCGENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Spread spectrum modulation disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Spread spectrum modulation enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.SSCGR { - public struct SPREADSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Center spread - public static let Center = Self(rawValue: 0x0) - - /// Down spread - public static let Down = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLI2SCFGR { - public struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLL*P=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLL*P=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLL*P=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLL*P=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLSAICFGR { - public struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLL*P=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLL*P=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLL*P=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLL*P=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 5 - - /// PLLI2SDIVQ = /1 - public static let Div1 = Self(rawValue: 0x0) - - /// PLLI2SDIVQ = /2 - public static let Div2 = Self(rawValue: 0x1) - - /// PLLI2SDIVQ = /3 - public static let Div3 = Self(rawValue: 0x2) - - /// PLLI2SDIVQ = /4 - public static let Div4 = Self(rawValue: 0x3) - - /// PLLI2SDIVQ = /5 - public static let Div5 = Self(rawValue: 0x4) - - /// PLLI2SDIVQ = /6 - public static let Div6 = Self(rawValue: 0x5) - - /// PLLI2SDIVQ = /7 - public static let Div7 = Self(rawValue: 0x6) - - /// PLLI2SDIVQ = /8 - public static let Div8 = Self(rawValue: 0x7) - - /// PLLI2SDIVQ = /9 - public static let Div9 = Self(rawValue: 0x8) - - /// PLLI2SDIVQ = /10 - public static let Div10 = Self(rawValue: 0x9) - - /// PLLI2SDIVQ = /11 - public static let Div11 = Self(rawValue: 0xa) - - /// PLLI2SDIVQ = /12 - public static let Div12 = Self(rawValue: 0xb) - - /// PLLI2SDIVQ = /13 - public static let Div13 = Self(rawValue: 0xc) - - /// PLLI2SDIVQ = /14 - public static let Div14 = Self(rawValue: 0xd) - - /// PLLI2SDIVQ = /15 - public static let Div15 = Self(rawValue: 0xe) - - /// PLLI2SDIVQ = /16 - public static let Div16 = Self(rawValue: 0xf) - - /// PLLI2SDIVQ = /17 - public static let Div17 = Self(rawValue: 0x10) - - /// PLLI2SDIVQ = /18 - public static let Div18 = Self(rawValue: 0x11) - - /// PLLI2SDIVQ = /19 - public static let Div19 = Self(rawValue: 0x12) - - /// PLLI2SDIVQ = /20 - public static let Div20 = Self(rawValue: 0x13) - - /// PLLI2SDIVQ = /21 - public static let Div21 = Self(rawValue: 0x14) - - /// PLLI2SDIVQ = /22 - public static let Div22 = Self(rawValue: 0x15) - - /// PLLI2SDIVQ = /23 - public static let Div23 = Self(rawValue: 0x16) - - /// PLLI2SDIVQ = /24 - public static let Div24 = Self(rawValue: 0x17) - - /// PLLI2SDIVQ = /25 - public static let Div25 = Self(rawValue: 0x18) - - /// PLLI2SDIVQ = /26 - public static let Div26 = Self(rawValue: 0x19) - - /// PLLI2SDIVQ = /27 - public static let Div27 = Self(rawValue: 0x1a) - - /// PLLI2SDIVQ = /28 - public static let Div28 = Self(rawValue: 0x1b) - - /// PLLI2SDIVQ = /29 - public static let Div29 = Self(rawValue: 0x1c) - - /// PLLI2SDIVQ = /30 - public static let Div30 = Self(rawValue: 0x1d) - - /// PLLI2SDIVQ = /31 - public static let Div31 = Self(rawValue: 0x1e) - - /// PLLI2SDIVQ = /32 - public static let Div32 = Self(rawValue: 0x1f) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 5 - - /// PLLSAIDIVQ = /1 - public static let Div1 = Self(rawValue: 0x0) - - /// PLLSAIDIVQ = /2 - public static let Div2 = Self(rawValue: 0x1) - - /// PLLSAIDIVQ = /3 - public static let Div3 = Self(rawValue: 0x2) - - /// PLLSAIDIVQ = /4 - public static let Div4 = Self(rawValue: 0x3) - - /// PLLSAIDIVQ = /5 - public static let Div5 = Self(rawValue: 0x4) - - /// PLLSAIDIVQ = /6 - public static let Div6 = Self(rawValue: 0x5) - - /// PLLSAIDIVQ = /7 - public static let Div7 = Self(rawValue: 0x6) - - /// PLLSAIDIVQ = /8 - public static let Div8 = Self(rawValue: 0x7) - - /// PLLSAIDIVQ = /9 - public static let Div9 = Self(rawValue: 0x8) - - /// PLLSAIDIVQ = /10 - public static let Div10 = Self(rawValue: 0x9) - - /// PLLSAIDIVQ = /11 - public static let Div11 = Self(rawValue: 0xa) - - /// PLLSAIDIVQ = /12 - public static let Div12 = Self(rawValue: 0xb) - - /// PLLSAIDIVQ = /13 - public static let Div13 = Self(rawValue: 0xc) - - /// PLLSAIDIVQ = /14 - public static let Div14 = Self(rawValue: 0xd) - - /// PLLSAIDIVQ = /15 - public static let Div15 = Self(rawValue: 0xe) - - /// PLLSAIDIVQ = /16 - public static let Div16 = Self(rawValue: 0xf) - - /// PLLSAIDIVQ = /17 - public static let Div17 = Self(rawValue: 0x10) - - /// PLLSAIDIVQ = /18 - public static let Div18 = Self(rawValue: 0x11) - - /// PLLSAIDIVQ = /19 - public static let Div19 = Self(rawValue: 0x12) - - /// PLLSAIDIVQ = /20 - public static let Div20 = Self(rawValue: 0x13) - - /// PLLSAIDIVQ = /21 - public static let Div21 = Self(rawValue: 0x14) - - /// PLLSAIDIVQ = /22 - public static let Div22 = Self(rawValue: 0x15) - - /// PLLSAIDIVQ = /23 - public static let Div23 = Self(rawValue: 0x16) - - /// PLLSAIDIVQ = /24 - public static let Div24 = Self(rawValue: 0x17) - - /// PLLSAIDIVQ = /25 - public static let Div25 = Self(rawValue: 0x18) - - /// PLLSAIDIVQ = /26 - public static let Div26 = Self(rawValue: 0x19) - - /// PLLSAIDIVQ = /27 - public static let Div27 = Self(rawValue: 0x1a) - - /// PLLSAIDIVQ = /28 - public static let Div28 = Self(rawValue: 0x1b) - - /// PLLSAIDIVQ = /29 - public static let Div29 = Self(rawValue: 0x1c) - - /// PLLSAIDIVQ = /30 - public static let Div30 = Self(rawValue: 0x1d) - - /// PLLSAIDIVQ = /31 - public static let Div31 = Self(rawValue: 0x1e) - - /// PLLSAIDIVQ = /32 - public static let Div32 = Self(rawValue: 0x1f) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLLSAIDIVR = /2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLLSAIDIVR = /4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLLSAIDIVR = /8 - public static let Div8 = Self(rawValue: 0x2) - - /// PLLSAIDIVR = /16 - public static let Div16 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct SAI1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - public static let PLLSAI = Self(rawValue: 0x0) - - /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - public static let PLLI2S = Self(rawValue: 0x1) - - /// SAI1 clock frequency = Alternate function input frequency - public static let AFIF = Self(rawValue: 0x2) - - /// SAI1 clock frequency = HSI or HSE - public static let HSI_HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct SAI2SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - public static let PLLSAI = Self(rawValue: 0x0) - - /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - public static let PLLI2S = Self(rawValue: 0x1) - - /// SAI2 clock frequency = Alternate function input frequency - public static let AFIF = Self(rawValue: 0x2) - - /// SAI2 clock frequency = HSI or HSE - public static let HSI_HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct TIMPREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - public static let Mul1Or2 = Self(rawValue: 0x0) - - /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - public static let Mul1Or4 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct USART1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB2 clock (PCLK2) is selected as USART clock - public static let APB2 = Self(rawValue: 0x0) - - /// System clock is selected as USART clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock is selected as USART clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as USART clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct USART2SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB1 clock (PCLK1) is selected as USART clock - public static let APB1 = Self(rawValue: 0x0) - - /// System clock is selected as USART clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock is selected as USART clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as USART clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct I2C1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB clock selected as I2C clock - public static let APB = Self(rawValue: 0x0) - - /// System clock selected as I2C clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock selected as I2C clock - public static let HSI = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB1 clock (PCLK1) selected as LPTILM1 clock - public static let APB1 = Self(rawValue: 0x0) - - /// LSI clock is selected as LPTILM1 clock - public static let LSI = Self(rawValue: 0x1) - - /// HSI clock is selected as LPTILM1 clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as LPTILM1 clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct CECSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE clock is selected as HDMI-CEC clock - public static let LSE = Self(rawValue: 0x0) - - /// HSI divided by 488 clock is selected as HDMI-CEC clock - public static let HSI_Div488 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct CK48MSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 48MHz clock from PLL is selected - public static let PLL = Self(rawValue: 0x0) - - /// 48MHz clock from PLLSAI is selected - public static let PLLSAI = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 48 MHz clock is selected as SD clock - public static let CK48M = Self(rawValue: 0x0) - - /// System clock is selected as SD clock - public static let SYSCLK = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lcd-logo/Sources/STM32F7X6/stm32f7x6.patched.svd b/stm32-lcd-logo/Sources/STM32F7X6/stm32f7x6.patched.svd deleted file mode 120000 index a6442b50..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/stm32f7x6.patched.svd +++ /dev/null @@ -1 +0,0 @@ -../../../Tools/SVDs/stm32f7x6.patched.svd \ No newline at end of file diff --git a/stm32-lcd-logo/Sources/STM32F7X6/svd2swift.json b/stm32-lcd-logo/Sources/STM32F7X6/svd2swift.json deleted file mode 100644 index dd674df6..00000000 --- a/stm32-lcd-logo/Sources/STM32F7X6/svd2swift.json +++ /dev/null @@ -1,19 +0,0 @@ -{ - "peripherals": [ - "FLASH", - "GPIOA", - "GPIOB", - "GPIOC", - "GPIOD", - "GPIOE", - "GPIOF", - "GPIOG", - "GPIOH", - "GPIOI", - "GPIOJ", - "GPIOK", - "LTDC", - "RCC" - ], - "access-level": "public" -} diff --git a/stm32-lcd-logo/Sources/Support/Startup.c b/stm32-lcd-logo/Sources/Support/Startup.c deleted file mode 100644 index 6838bdc0..00000000 --- a/stm32-lcd-logo/Sources/Support/Startup.c +++ /dev/null @@ -1,51 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include -#include - -extern int main(int argc, char *argv[]); - -void *memset(void *b, int c, size_t len) { - for (int i = 0; i < len; i++) { - ((char *)b)[i] = c; - } - return b; -} - -void *memcpy(void *restrict dst, const void *restrict src, size_t n) { - for (int i = 0; i < n; i++) { - ((char *)dst)[i] = ((char *)src)[i]; - } - return dst; -} - -void reset(void) { - main(0, NULL); -} - -void interrupt(void) { - while (1) {} -} - -__attribute((used)) __attribute((section("__VECTORS,__text"))) -void *vector_table[114] = { - (void *)0x2000fffc, // initial SP - reset, // Reset - - interrupt, // NMI - interrupt, // HardFault - interrupt, // MemManage - interrupt, // BusFault - interrupt, // UsageFault - - 0 // NULL for all the other handlers -}; diff --git a/stm32-lcd-logo/Sources/Support/include/Support.h b/stm32-lcd-logo/Sources/Support/include/Support.h deleted file mode 100644 index 14e4a7ac..00000000 --- a/stm32-lcd-logo/Sources/Support/include/Support.h +++ /dev/null @@ -1,16 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#pragma once - -static inline void nop() { - asm volatile("nop"); -} diff --git a/stm32-lvgl/.gitignore b/stm32-lvgl/.gitignore deleted file mode 100644 index ea5f98bd..00000000 --- a/stm32-lvgl/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -lvgl -llvm-toolchain diff --git a/stm32-lvgl/.sourcekit-lsp/config.json b/stm32-lvgl/.sourcekit-lsp/config.json deleted file mode 100644 index 7f0beef5..00000000 --- a/stm32-lvgl/.sourcekit-lsp/config.json +++ /dev/null @@ -1,11 +0,0 @@ -{ - "swiftPM": { - "configuration": "release", - "triple": "armv7em-none-none-eabi", - "toolsets": ["toolset.json"], - "swiftCompilerFlags": [ - "-enable-experimental-feature", "Embedded", - "-enable-experimental-feature", "Extern" - ] - } -} diff --git a/stm32-lvgl/Makefile b/stm32-lvgl/Makefile deleted file mode 100644 index 54f59dd9..00000000 --- a/stm32-lvgl/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -##===----------------------------------------------------------------------===## -## -## This source file is part of the Swift open source project -## -## Copyright (c) 2025 Apple Inc. and the Swift project authors. -## Licensed under Apache License v2.0 with Runtime Library Exception -## -## See https://swift.org/LICENSE.txt for license information -## -##===----------------------------------------------------------------------===## - -# Paths -REPOROOT := $(shell git rev-parse --show-toplevel) -TOOLSROOT := $(REPOROOT)/Tools -TOOLSET := $(PWD)/toolset.json -ELF2HEX := $(TOOLSROOT)/elf2hex.py -SWIFT_BUILD := swift build -NM := nm -LLVM_TOOLCHAIN := $(PWD)/llvm-toolchain - -# Flags -ARCH := armv7em -TARGET := $(ARCH)-none-none-eabi -SWIFT_BUILD_ARGS := \ - --configuration release \ - --triple $(TARGET) \ - --toolset $(TOOLSET) \ - --product Application -BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) - -.PHONY: build -build: - @echo "checking dependencies..." - - if [[ ! -d $(PWD)/lvgl ]]; then echo "\n *** LVGL checkout not found, please run ./fetch-dependencies.sh\n" ; exit 1 ; fi - if [[ ! -d $(PWD)/llvm-toolchain ]]; then echo "\n *** LLVM toolchain checkout not found, please run ./fetch-dependencies.sh\n" ; exit 1 ; fi - - mkdir -p .build - - @echo "configuring LVGL..." - cmake -B .build/lvgl -G Ninja ./lvgl \ - -DCMAKE_EXPORT_COMPILE_COMMANDS=On \ - -DTOOLCHAIN_PATH=$(LLVM_TOOLCHAIN) \ - -DCMAKE_TOOLCHAIN_FILE=../clang-arm-toolchain.cmake \ - -DLV_CONF_PATH=../Sources/CLVGL/include/lv_conf.h - - @echo "building LVGL..." - cmake --build .build/lvgl - - @echo "building..." - $(SWIFT_BUILD) \ - $(SWIFT_BUILD_ARGS) \ - --verbose - - @echo "disassembling..." - $(LLVM_TOOLCHAIN)/bin/llvm-objdump --all-headers --disassemble --mcpu=cortex-m7 \ - $(BUILDROOT)/Application \ - | c++filt | swift demangle > $(BUILDROOT)/Application.disassembly - - @echo "extracting binary..." - $(ELF2HEX) \ - $(BUILDROOT)/Application $(BUILDROOT)/Application.hex --relocate - ls -al $(BUILDROOT)/Application.hex - @echo "\n *** All done, build succeeded!\n" - -flash: - @echo "flashing..." - st-flash --reset --format ihex write $(BUILDROOT)/Application.hex - -simulator: - mkdir -p .build - - @echo "configuring LVGL..." - cmake -B .build/lvgl-host -G Ninja ./lvgl \ - -DCMAKE_EXPORT_COMPILE_COMMANDS=On \ - -DLV_CONF_PATH=../Sources/CLVGL/include/lv_conf.h - - @echo "building LVGL..." - cmake --build .build/lvgl-host - - @echo "building..." - $(SWIFT_BUILD) \ - --configuration release \ - --product HostSDLApp \ - --verbose - - @echo "running..." - $(PWD)/.build/release/HostSDLApp - -.PHONY: clean -clean: - @echo "cleaning..." - @swift package clean - @rm -rf .build diff --git a/stm32-lvgl/Package.resolved b/stm32-lvgl/Package.resolved deleted file mode 100644 index 35151e54..00000000 --- a/stm32-lvgl/Package.resolved +++ /dev/null @@ -1,42 +0,0 @@ -{ - "originHash" : "27891c7454528c694f8ba4111e7214ff70b5364bdb54bce808c6e0d4b188bd81", - "pins" : [ - { - "identity" : "swift-argument-parser", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-argument-parser.git", - "state" : { - "revision" : "41982a3656a71c768319979febd796c6fd111d5c", - "version" : "1.5.0" - } - }, - { - "identity" : "swift-mmio", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-mmio", - "state" : { - "branch" : "main", - "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" - } - }, - { - "identity" : "swift-syntax", - "kind" : "remoteSourceControl", - "location" : "https://github.com/swiftlang/swift-syntax.git", - "state" : { - "revision" : "0687f71944021d616d34d922343dcef086855920", - "version" : "600.0.1" - } - }, - { - "identity" : "swiftsdl2", - "kind" : "remoteSourceControl", - "location" : "https://github.com/ctreffs/SwiftSDL2.git", - "state" : { - "revision" : "30a2886bd68e43fc19ba29b63ffe230ac0e4db7a", - "version" : "1.4.1" - } - } - ], - "version" : 3 -} diff --git a/stm32-lvgl/Package.swift b/stm32-lvgl/Package.swift deleted file mode 100644 index aa27549a..00000000 --- a/stm32-lvgl/Package.swift +++ /dev/null @@ -1,59 +0,0 @@ -// swift-tools-version: 5.10 - -import PackageDescription - -let package = Package( - name: "stm32-lvgl", - platforms: [ - .macOS(.v11) - ], - products: [ - .executable(name: "Application", targets: ["Application"]) - ], - dependencies: [ - .package(url: "https://github.com/apple/swift-mmio", branch: "main"), - .package(url: "https://github.com/ctreffs/SwiftSDL2.git", from: "1.4.0"), - ], - targets: [ - // - // FIRMWARE TARGETS - // - - .executableTarget( - name: "Application", - dependencies: [ - "Registers", - "Support", - "CLVGL", - ]), - - // SVD2Swift \ - // --input Tools/SVDs/stm32f7x6.patched.svd \ - // --output stm32-lvgl/Sources/STM32F7x6 \ - // --peripherals FLASH LTDC RCC PWR FMC SCB DBGMCU USART1 STK NVIC SYSCFG \ - // GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG GPIOH GPIOI GPIOJ GPIOK \ - // I2C1 I2C2 I2C3 I2C4 \ - // --access-level public - .target( - name: "Registers", - dependencies: [ - .product(name: "MMIO", package: "swift-mmio") - ]), - - .target(name: "Support"), - - .target(name: "CLVGL"), - - // - // HOST TARGETS - // - - .executableTarget( - name: "HostSDLApp", - dependencies: [ - .product(name: "SDL", package: "SwiftSDL2"), - "CLVGL", - ], - swiftSettings: [.enableExperimentalFeature("Extern")], - linkerSettings: [.unsafeFlags(["-L.build/lvgl-host/lib", "-llvgl", "-llvgl_demos"])]), - ]) diff --git a/stm32-lvgl/README.md b/stm32-lvgl/README.md deleted file mode 100644 index 8a4d932a..00000000 --- a/stm32-lvgl/README.md +++ /dev/null @@ -1,49 +0,0 @@ -# stm32-lvgl - - - -This sample code is demonstrating a "full" graphical firmware running on an STM32 microcontroller board, concretely the STM32F746G "Discovery" board. It shows using: - -- **ELF file format**, linking with lld, with a custom simple linker script (and thus it builds identically on both macOS and Linux hosts) -- **LLVM Embedded Toolchain for ARM** -- **LVGL** graphical/input/animation library -- The **DRAM, LCD, touch panel, GPIO pins and interrupts** on the STM32F746G -- **No other SDKs or library dependencies** -- all the startup code, including MCU, board and peripheral initialization is done in Swift source code - -Additionally, this sample code: - -- Has **LSP integration** set up via the `.sourcekit-lsp/config.json` file, confirmed to work in multiple code editors (VS Code, Sublime Text, Zed) -- Uses **SwiftPM's toolset.json** to define compiler and linker flags -- Has a host OS (macOS, Linux) **"simulator" using SDL** that can use the same "business logic" code to render the same LVGL UI. - -## How to build and run this example: - -1. Connect the STM32F746G-DISCO board via the ST-LINK USB port to your Mac. -2. Install the right Swift toolchain specified in this repo's `.swift-version` file. This is best done using `swiftly`: -```console -$ swiftly install # Run in the project's directory -``` -3. Install the `stlink` (https://github.com/stlink-org/stlink) command line tools, e.g. via `brew install stlink`. -4. Run a provided shell script that fetches the LVGL and LLVM dependencies: -```console -$ ./fetch-dependencies.sh -``` -5. Build the firmware by running make: -```console -$ make -``` -6. Flash the built firmware by running make with the following target: -```console -$ make flash -``` - -You should now see the UI animating on the board's LCD display, and the touch screen should react to inputs. - -Optionally, you can also run build and run the code in a desktop OS SDL "simulator" by: -```console -$ make simulator -``` - -## Additional information - -- The ELF linking, linker script and packaging scheme is destribed in detail [inside the linker script](Sources/Support/linkerscript.ld). diff --git a/stm32-lvgl/Sources/Application/Clocks.swift b/stm32-lvgl/Sources/Application/Clocks.swift deleted file mode 100644 index 2da683dc..00000000 --- a/stm32-lvgl/Sources/Application/Clocks.swift +++ /dev/null @@ -1,423 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import Registers -import Support - -/* - * STM32F746 clock configuration has the following constraints: - * - * Select HSE_BYPASS if an oscillator is used instead of a crystal. - * - * VCO: 100-432MHz - * PLL input: 0.95-2.1MHz (higher is less jitter, but not required) - * PLL output: 24-216MHz - * - * Maximum HCLK, APB1, APB2: - * - * Power Scale Over-drive VDD12 HCLK APB1 APB2 - * 3 Off 1.14v 144MHz 45MHz 90MHz - * 2 Off 1.26v 168MHz 45MHz 90MHz - * 2 On 1.26v 180MHz 54MHz 108MHz - * 1 Off 1.32v 180MHz 45MHz 90MHz - * 1 On 1.32v 216MHz 54MHz 108MHz - * - * Ethernet requires HCLK>=25MHz, and USB-HS requires HCLK>=30MHz. - * - * Formulas: - * - * HSE = OSC_IN (e.g 25MHz) - * PLL input = HSE / PLLM (1-2MHz, PLLM=2..63) - * VCO = PLL input * PLLN (100-432MHz, PLLN=50..432) - * PLL output = VCO / PLLP (24-216MHz, PLLP=2,4,6,8) - * HCLK = PLL output / HPRE (Power-of-2 divide by 1-512) - * APB1 = HCLK / PPRE1 (Power-of-2 divide by 1-16) - * APB2 = HCLK / PPRE2 (Power-of-2 divide by 1-16) - * USB-FS/RNG = VCO / PLLQ (48MHz, PLLQ=2..15) - * - * APB1/APB2 TIMx timers have dedicated clocks which are 2x or 4x the - * domain they live in, limited to HCLK. This is selected by the - * TIMPRE bit in RCC: - * - * TIMPRE Multiplier - * 0 2x - * 1 4x - * - * USB-FS requires exactly 48MHz, but this is unused. RNG requires - * 48MHz or lower. - */ - -// The STM32F746-DISCO board has an external 25MHz oscillator -let CPU_TARGET_FREQ = 200 - -// Values for 200 MHz target freq: -let HSE_BYPASS = true // Oscillator, not crystal -let PLL_M: UInt32 = 12 // VCO input = 2.083MHz -let PLL_N: UInt32 = 192 // VCO = 400MHz -let PLL_P: UInt32 = 2 // Divide by 2 = 200MHz -let PLL_Q: UInt32 = 9 // Divide by 9 = 44.5MHz -let HPRE: UInt32 = 1 // AHB = 200 / 1 = 200MHz -let PPRE1: UInt32 = 4 // APB1 = 200 / 4 = 50MHz -let PPRE2: UInt32 = 2 // APB2 = 200 / 2 = 100MHz -let VOLTAGE_SCALE: UInt32 = 1 // 180MHz requires voltage scale 1 (1.32v) -let OVERDRIVE = true // Over-drive required for APB clocks -let TIMER_MUL: UInt32 = 2 // Timer clocks are 2xAPB - -// External oscillator or crystal. -let HSE_VALUE: UInt32 = 25_000_000 - -// This is the built-in oscillator. It always runs at 16MHz -let HSI_CLOCK: UInt32 = 16_000_000 - -/// Represents available system clock sources -public enum SystemClock: UInt32 { - case hsi = 0 // High-Speed Internal oscillator - case hse = 1 // High-Speed External oscillator - case pll = 2 // Phase-Locked Loop - case plli2s = 3 // I2S Phase-Locked Loop - case pllsai = 4 // SAI Phase-Locked Loop -} - -public func enableSystemClock(_ clock: SystemClock, enable: Bool) { - let v: UInt32 = enable ? 1 : 0 - switch clock { - case .hsi: - rcc.cr.modify { $1.raw.hsion = v } - case .hse: - rcc.cr.modify { $1.raw.hseon = v } - case .pll: - rcc.cr.modify { $1.raw.pllon = v } - case .plli2s: - rcc.cr.modify { $1.raw.plli2son = v } - case .pllsai: - rcc.cr.modify { $1.raw.pllsaion = v } - } - - // Dummy read-back as barrier. - _ = rcc.cr.read() -} - -public func waitSystemClock(_ clock: SystemClock, enable: Bool) { - let v: UInt32 = enable ? 1 : 0 - switch clock { - case .hsi: - while rcc.cr.read().raw.hsion != v { /* busy wait */ } - case .hse: - while rcc.cr.read().raw.hseon != v { /* busy wait */ } - case .pll: - while rcc.cr.read().raw.pllon != v { /* busy wait */ } - case .plli2s: - while rcc.cr.read().raw.plli2son != v { /* busy wait */ } - case .pllsai: - while rcc.cr.read().raw.pllsaion != v { /* busy wait */ } - } -} - -public func selectSystemClock(_ clock: SystemClock) { - let sw: UInt32 - let sws: UInt32 - - switch clock { - case .hsi: - sw = 0 // RCC_CFGR_SW_HSI - sws = 0 // RCC_CFGR_SWS_HSI - case .hse: - sw = 1 // RCC_CFGR_SW_HSE - sws = 1 // RCC_CFGR_SWS_HSE - case .pll: - sw = 2 // RCC_CFGR_SW_PLL - sws = 2 // RCC_CFGR_SWS_PLL - default: - preconditionFailure("Bad clock \(clock)") - } - - if rcc.cfgr.read().raw.sw != sw { - // Switch system clock source to the new source - rcc.cfgr.modify { $0.raw.sw = sw } - - // Wait until selected - while rcc.cfgr.read().raw.sws != sws { /* busy wait */ } - } -} - -func setFlashWaitStates(_ hclk: UInt32) { - if (hclk == 0) || (hclk > 216_000_000) { - preconditionFailure("HCLK out of range") - } - - // One wait state per 30MHz (exact multiple of 30MHz uses lower number) - let flash_ws = (hclk - 1) / 30_000_000 - - // Set the flash wait states. - flash.acr.modify { $0.latency = .init(rawValue: UInt8(flash_ws)) } - - // Dummy read-back as barrier. - _ = flash.acr.read() -} - -public func setPllConfiguration(_ config: (hse: Bool, q: UInt32, p: UInt32, n: UInt32, m: UInt32)) { - // PLLQ direct mapped 2..15 - // PLLP 2->0, 4->1, 6->2, 8->3 - // PLLN direct mapped 50..432 - // PLLM direct mapped 2..63 - - // Always assert limits. - if (config.q < 2) || (config.q > 15) || (config.p < 2) || (config.p > 8) || ((config.p % 1) != 0) || (config.n < 50) - || (config.n > 432) || (config.m < 2) || (config.m > 63) - { - preconditionFailure("PllConfig") - } - - // Update PLL configuration using structured register access - rcc.pllcfgr.modify { - $0.pllsrc = config.hse ? .HSE : .HSI - $0.raw.pllq = config.q - $0.raw.pllp = (config.p / 2) - 1 - $0.raw.plln = config.n - $0.raw.pllm = config.m - } - - // Dummy barrier read - _ = rcc.pllcfgr.read() -} - -func setVoltageScale(_ scale: UInt32) { - // Select voltage scaling. This is enacted by hardware when the - // PLL is turned on. The hardware encoding is the reverse of the - // documented voltage scale numbers. - let vosCode: UInt32 - if scale == 1 { - vosCode = 3 - } else if scale == 2 { - vosCode = 2 - } else if scale == 3 { - vosCode = 1 - } else { - preconditionFailure("Voltage scale must be 1..3") - } - - pwr.cr1.modify { - $0.raw.vos = vosCode - } - - // Dummy read-back as barrier. - _ = pwr.cr1.read() -} - -func setOverdrive(_ overdrive: Bool) { - // Configure overdrive mode on or off. - if overdrive { - // See "Entering Over-drive mode" section 4.1.4 STM32F746 Ref - // manual. - pwr.cr1.modify { $0.raw.oden = 1 } - - while pwr.csr1.read().raw.odrdy == 0 { - // Wait until overdrive ready - } - - // Enable overdrive switching. This stalls core clock, but - // this delay is hidden because we are regardless still - // waiting for the PLL to lock. - pwr.cr1.modify { $0.raw.odswen = 1 } - - while pwr.csr1.read().raw.odswrdy == 0 { - // Wait until overdrive switch ready - } - } else { - // Overdrive disable, while system clock is still on HSI. - pwr.cr1.modify { - $0.raw.oden = 0 - $0.raw.odswen = 0 - } - - // Dummy read-back as barrier. - _ = pwr.cr1.read() - } -} - -func setTimerMultiplier(_ multiplier: UInt32) { - if multiplier == 2 { - rcc.dckcfgr1.modify { $0.raw.timpre = 0 } - } else if multiplier == 4 { - rcc.dckcfgr1.modify { $0.raw.timpre = 1 } - } else { - preconditionFailure("Bad TIMPRE") - } -} - -func enableCSS(_ enable: Bool) { - rcc.cr.modify { $1.csson = enable ? .On : .Off } - - // Dummy read-back as barrier. - _ = rcc.cr.read() -} - -func setOscillator(_ enable: Bool) { - rcc.cr.modify { $1.hsebyp = enable ? .Bypassed : .NotBypassed } - - // Dummy read-back as barrier. - _ = rcc.cr.read() -} - -extension UInt64 { - func divideRoundingUp(divideBy: UInt64) -> UInt64 { - return (self + divideBy - 1) / divideBy - } -} - -func log2_exact(_ val: UInt32) -> UInt32 { - guard val.nonzeroBitCount == 1 else { - preconditionFailure("Value \(val) is not a power of 2") - } - return UInt32(val.trailingZeroBitCount) -} - -extension Main { - static func setPrescalers(_ prescalers: (hpre: UInt32, ppre1: UInt32, ppre2: UInt32)) { - let log2_ahb: UInt32 = log2_exact(prescalers.hpre) - let log2_apb1: UInt32 = log2_exact(prescalers.ppre1) - let log2_apb2: UInt32 = log2_exact(prescalers.ppre2) - - let hpreCode: UInt32 - if log2_ahb <= 4 { - // 1, 2, 4, 8, 16 -> 7, 8, 9, 10, 11 - hpreCode = 7 + log2_ahb - } else { - // The code for divide-by-32 is skipped for some reason. - // 64, 128, 256, 512 -> 12, 13, 14, 15 - hpreCode = 6 + log2_ahb - } - let ppre1Code: UInt32 = 3 + log2_apb1 // 1,2,4,8,16 -> 3,4,5,6,7 - let ppre2Code: UInt32 = 3 + log2_apb2 // 1,2,4,8,16 -> 3,4,5,6,7 - - withInterruptsDisabled { - rcc.cfgr.modify { - $0.raw.hpre = hpreCode - $0.raw.ppre1 = ppre1Code - $0.raw.ppre2 = ppre2Code - } - // Dummy read + wait up to 16 AHB clocks to take effect - _ = rcc.cfgr.read() - delay(16) - } - } - - static func initClocks() { - enableSystemClock(.hsi, enable: true) - waitSystemClock(.hsi, enable: true) - selectSystemClock(.hsi) - - setPrescalers((1, 1, 1)) - - // Set dedicated timer clock multiplier to default 2x. - setTimerMultiplier(2) - - // 16MHz operation allows zero-wait-state flash. - setFlashWaitStates(HSI_CLOCK) - - // Disable Clock Security System (CSS). - enableCSS(false) - - // Disable HSE, PLL, PLLI2S, PLLSAI. - enableSystemClock(.hse, enable: false) - enableSystemClock(.pll, enable: false) - enableSystemClock(.plli2s, enable: false) - enableSystemClock(.pllsai, enable: false) - waitSystemClock(.hse, enable: false) - waitSystemClock(.pll, enable: false) - waitSystemClock(.plli2s, enable: false) - waitSystemClock(.pllsai, enable: false) - - // Set PLLCFGR (prescalers and source) to the reset default value - // for 48MHz operation. - setPllConfiguration((hse: false, q: 4, p: 2, n: 96, m: 16)) - - // Default is crystal. - setOscillator(false) - - // XXX, HW required delay for the clocks to be set right - // TODO: figure out which exact operation in the sequence requires the - // delay - delay(4) - } - - static func checkQuiesced() { - // Check that the system is running from HSI. Otherwise, the setup - // sequence will disturb active clocks. - let cfgr = rcc.cfgr.read() - if cfgr.raw.sw != 0 || cfgr.raw.sws != 0 { - preconditionFailure("Not quiesced") - } - - // Check that non-HSI clocks are quiesced, otherwise the setup - // sequence will be prevented by hardware from updating - // configuration bits. - let cr = rcc.cr.read() - if cr.raw.hseon != 0 || cr.raw.csson != 0 || cr.raw.pllon != 0 || cr.raw.plli2son != 0 || cr.raw.pllsaion != 0 { - preconditionFailure("Not quiesced") - } - } - - static func systemSetCoreClock() { - withInterruptsDisabled { - // Check the system has started up sufficiently quiesced, or the - // config sequence may disturb clocks out of spec, or the micro - // may prevent some bits from being updated. - checkQuiesced() - - // We need the PWR block enabled. - rcc.apb1enr.modify { $0.raw.pwren = 1 } - delay(32) - - // Set flash controller wait states for the target HCLK. Quiesced - // state accepts any value (it just runs slow). - let hclk = UInt64(UInt64(HSE_VALUE) * UInt64(PLL_N)).divideRoundingUp( - divideBy: UInt64(PLL_M) * UInt64(PLL_P) * UInt64(HPRE)) - if (hclk == 0) || (hclk > 216_000_000) { - preconditionFailure("HCLK out of range") - } - setFlashWaitStates(UInt32(hclk)) - - // Configure the target PLL frequency and required voltage. - setPllConfiguration((hse: true, q: PLL_Q, p: PLL_P, n: PLL_N, m: PLL_M)) - setVoltageScale(VOLTAGE_SCALE) - - // Configure, enable, and wait for the HSE clock. - setOscillator(HSE_BYPASS) - enableSystemClock(.hse, enable: true) - waitSystemClock(.hse, enable: true) - - // Enable and wait for the PLL. PLL t_LOCK<=300usec takes a - // while. Overdrive Tod_swen<=100usec is also slow, and can be - // configure concurrently. - enableSystemClock(.pll, enable: true) - setOverdrive(OVERDRIVE) - waitSystemClock(.pll, enable: true) - - // Increase CPU and peripheral dividers. This will very - // temporarily run the system slow as we are still on 16MHz - // HSI. Then finally switch to the system to PLL. - setPrescalers((HPRE, PPRE1, PPRE2)) - selectSystemClock(.pll) - - // Set dedicated timer clock multiplier 2x or 4x. - setTimerMultiplier(TIMER_MUL) - - // Enable SYSCFG clock in APB2 peripheral clock register - rcc.apb2enr.modify { $0.raw.syscfgen = 1 } - delay(32) - - // Enable I/O Compensation Cell - syscfg.cmpcr.modify { $1.raw.cmp_pd = 1 } - while syscfg.cmpcr.read().raw.ready == 0 { /* busy wait */ } - } - } -} diff --git a/stm32-lvgl/Sources/Application/Debug.swift b/stm32-lvgl/Sources/Application/Debug.swift deleted file mode 100644 index b5788c22..00000000 --- a/stm32-lvgl/Sources/Application/Debug.swift +++ /dev/null @@ -1,67 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import Registers -import Support - -extension Main { - static func initDebug() { - // Keep clocks going when we WFI - dbgmcu.cr.modify { $0.raw.dbg_standby = 1 } - } - - static func initUartOutput() { - // A9 is UART1 TX, which is relayed by ST-LINK over USB - - // Clock configuration - rcc.ahb1enr.modify { $0.raw.gpioaen = 1 } // Enable AHB clock to port A - rcc.apb2enr.modify { $0.raw.usart1en = 1 } // Enable APB clock to usart 1 - - // Configure A9 as UART1 TX - gpioa.moder.modify { $0.raw.moder9 = 0b10 } // Put Pin A9 into alternate function mode - gpioa.otyper.modify { $0.raw.ot9 = 0b0 } // Put Pin A9 into push pull - gpioa.ospeedr.modify { $0.raw.ospeedr9 = 0b00 } // Put Pin A9 into low speed - gpioa.pupdr.modify { $0.raw.pupdr9 = 0b00 } // Disable pull up/down on Pin A9 - gpioa.afrh.modify { $0.raw.afrh9 = 0b0111 } // Set alternate function usart1 on Pin A9 - - // Configure UART1, set the baud rate to 115200 (we boot at 16 MHz) - usart1.brr.modify { $0.raw.storage = 16_000_000 / 115_200 } - - usart1.cr1.modify { - $0.raw.ue = 1 // Enable USART 1 - $0.raw.te = 1 // Enable TX - } - } -} - -func waitTxBufferEmpty() { - // Spin while tx buffer not empty - while usart1.isr.read().raw.txe == 0 {} -} - -func tx(value: UInt8) { - usart1.tdr.write { $0.raw.tdr_field = UInt32(value) } -} - -@_cdecl("putchar") -public func putchar(_ value: CInt) -> CInt { - waitTxBufferEmpty() - tx(value: UInt8(value)) - waitTxBufferEmpty() - return 0 -} - -func log(_ s: String) { - let n = uptimeInMs / 1000 - var m = String(uptimeInMs % 1000) - while m.utf8.count < 3 { m = "0" + m } - print("[\(n).\(m)] " + s) -} diff --git a/stm32-lvgl/Sources/Application/I2C.swift b/stm32-lvgl/Sources/Application/I2C.swift deleted file mode 100644 index 266fc6dc..00000000 --- a/stm32-lvgl/Sources/Application/I2C.swift +++ /dev/null @@ -1,156 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import MMIO -import Registers -import Support - -struct I2C { - let i2c: I2C1 - let deviceAddress: UInt8 - - enum Interface: Int { - case i2c1 = 0 - case i2c2 - case i2c3 - case i2c4 - } - - init(interface: Interface, deviceAddress: UInt8) { - self.deviceAddress = deviceAddress - - switch interface { - case .i2c1: - self.i2c = i2c1 - rcc.apb1enr.modify { $0.raw.i2c1en = 1 } // Enable clock - case .i2c2: - self.i2c = i2c2 - rcc.apb1enr.modify { $0.raw.i2c2en = 1 } // Enable clock - case .i2c3: - self.i2c = i2c3 - rcc.apb1enr.modify { $0.raw.i2c3en = 1 } // Enable clock - case .i2c4: - self.i2c = i2c4 - rcc.apb1enr.modify { $0.raw.i2c4en = 1 } // Enable clock - } - - // Reset I2C peripheral - i2c.cr1.write { $0.raw.pe = 0 } - - // Configure I2C timing for 100KHz (based on 50MHz APB1 clock) - i2c.timingr.write { - $0.raw.presc = 0x09 // Prescaler - $0.raw.scldel = 0x04 // Data setup time - $0.raw.sdadel = 0x02 // Data hold time - $0.raw.sclh = 0x0F // SCL high period - $0.raw.scll = 0x13 // SCL low period - } - - // Enable I2C peripheral - i2c.cr1.modify { - $0.raw.pe = 1 // Enable peripheral - $0.raw.anfoff = 0 // Analog filter enabled - $0.raw.dnf = 0 // Digital filter disabled - } - } - - func write(data: [UInt8]) -> Bool { - // Wait until I2C is not busy - while i2c.isr.read().raw.busy == 1 { /* busy wait */ } - - // Set slave address - i2c.cr2.write { - $0.raw.sadd = UInt32(deviceAddress) << 1 // 7-bit address, shifted left by 1 - $0.raw.nbytes = UInt32(data.count) - $0.raw.autoend = 1 // Automatic end mode - $0.raw.start = 1 // Generate start condition - $0.raw.rd_wrn = 0 // Write transfer - } - - // Send data bytes - for byte in data { - // Wait until TXIS is set (transmit register empty) - while i2c.isr.read().raw.txis == 0 { - // Check for errors - let isr = i2c.isr.read().raw - if isr.nackf == 1 { - // NACK received - i2c.icr.write { $0.raw.nackcf = 1 } // Clear NACK flag - return false - } - } - - // Write data to TXDR - i2c.txdr.write { $0.raw.txdata = UInt32(byte) } - } - - // Wait for transfer complete - while i2c.isr.read().raw.tc == 0 && i2c.isr.read().raw.tcr == 0 && i2c.isr.read().raw.stopf == 0 { - // Check for errors - if i2c.isr.read().raw.nackf == 1 { - i2c.icr.write { $0.raw.nackcf = 1 } // Clear NACK flag - return false - } - } - - // Clear flags - let isr = i2c.isr.read().raw - i2c.icr.write { - $0.raw.stopcf = isr.stopf - $0.raw.nackcf = isr.nackf - } - - return true - } - - func read(buffer: inout [UInt8], length: Int) -> Bool { - // Wait until I2C is not busy - while i2c.isr.read().raw.busy == 1 { /* busy wait */ } - - // Set slave address and read operation - i2c.cr2.write { - $0.raw.sadd = UInt32(deviceAddress) << 1 // 7-bit address, shifted left by 1 - $0.raw.nbytes = UInt32(length) - $0.raw.autoend = 1 // Automatic end mode - $0.raw.rd_wrn = 1 // Read transfer - $0.raw.start = 1 // Generate start condition - } - - // Read data - for i in 0.. Void) { - let oldMask = primask_get() - cpsid_i() - body() - primask_set(oldMask) -} - -extension Main { - static func initInterrupts() { - // Disable then clear all RCC interrupts. - rcc.cir.modify { - $1.raw.lsirdyie = 0 - $1.raw.lserdyie = 0 - $1.raw.hsirdyie = 0 - $1.raw.hserdyie = 0 - $1.raw.pllrdyie = 0 - $1.raw.plli2srdyie = 0 - $1.raw.pllsairdyie = 0 - } - rcc.cir.modify { - $1.raw.lsirdyie = 1 - $1.raw.lserdyie = 1 - $1.raw.hsirdyie = 1 - $1.raw.hserdyie = 1 - $1.raw.pllrdyie = 1 - $1.raw.plli2srdyie = 1 - $1.raw.pllsairdyie = 1 - } - } -} - -var uptimeInMs = 0 - -extension Main { - static func initSysTick() { - stk.rvr.write { $0.raw.reload = 200_000 } // Set the reload value, ~1ms - stk.cvr.write { $0.raw.current = 0 } // Clear the current value - - // Enable the SysTick timer with processor clock - stk.csr.modify { - $0.raw.enable = 1 - $0.raw.tickint = 1 - $0.raw.clksource = 1 - } - - // Wait one tick for wrap. This eliminates ambiguity at the - // zero count. This is only possible if SysTick is - // (significantly) slower than the core clock. - while stk.cvr.read().raw.current == 0 { /* busy wait */ } - } -} - -@_cdecl("SystickTimerISR") -func SystickTimerISR() { - uptimeInMs += 1 -} - -var lcdInterruptVerticalSyncHandler: (() -> Void)? = nil - -@_cdecl("LtdcIntHandlerISR") -func LtdcIntHandlerISR() { - let sr = ltdc.isr.read() - ltdc.icr.write { $0.storage = sr.storage } - if sr.raw.rrif != 0 { - lcdInterruptVerticalSyncHandler?() - } -} diff --git a/stm32-lvgl/Sources/Application/Lcd.swift b/stm32-lvgl/Sources/Application/Lcd.swift deleted file mode 100644 index bd8b26da..00000000 --- a/stm32-lvgl/Sources/Application/Lcd.swift +++ /dev/null @@ -1,128 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import MMIO -import Registers -import Support - -enum Lcd { - static let LCD_HSYNC: UInt32 = 10 - static let LCD_VSYNC: UInt32 = 2 - static let LCD_HBP: UInt32 = 43 - static let LCD_VBP: UInt32 = 12 - static let LCD_WIDTH: UInt32 = 480 - static let LCD_HEIGHT: UInt32 = 272 - static let LCD_HFP: UInt32 = 8 - static let LCD_VFP: UInt32 = 4 - static let LCD_PIXSIZE: UInt32 = 4 - static let SDRAM_BASE: UInt32 = 0xC000_0000 - - /// Initialize the LTDC module and get the display panel running. - static func initialize() { - // Configure the PLL for the display refresh. The LTDC has its own PLL. - // This code sets the DOTCLK to 8MHz or so. - let sain: UInt32 = 192 - let saiq = rcc.pllsaicfgr.read().raw.pllsaiq - let sair: UInt32 = 4 - - rcc.pllsaicfgr.write { - $0.raw.pllsain = sain - $0.raw.pllsaiq = saiq - $0.raw.pllsair = sair - } - rcc.dckcfgr1.modify { $0.pllsaidivr = .Div8 } - rcc.cr.modify { $1.raw.pllsaion = 1 } - - // Wait for PLLSAI to be ready - while rcc.cr.read().raw.pllsairdy == 0 { /* busy wait */ } - - // Enable clock to the LCD controller - rcc.apb2enr.modify { $0.raw.ltdcen = 1 } - - // Program the timing parameters for the panel - ltdc.sscr.write { - $0.raw.hsw = LCD_HSYNC - 1 - $0.raw.vsh = LCD_VSYNC - 1 - } - ltdc.bpcr.write { - $0.raw.ahbp = LCD_HSYNC + LCD_HBP - 1 - $0.raw.avbp = LCD_VSYNC + LCD_VBP - 1 - } - ltdc.awcr.write { - $0.raw.aaw = LCD_HSYNC + LCD_HBP + LCD_WIDTH - 1 - $0.raw.aah = LCD_VSYNC + LCD_VBP + LCD_HEIGHT - 1 - } - ltdc.twcr.write { - $0.raw.totalw = LCD_HSYNC + LCD_HBP + LCD_WIDTH + LCD_HFP - 1 - $0.raw.totalh = LCD_VSYNC + LCD_VBP + LCD_HEIGHT + LCD_VFP - 1 - } - - // Set background color to black - ltdc.bccr.write { $0.raw.storage = 0 } - - // Configure layer 1 - let h_start = LCD_HSYNC + LCD_HBP + 0 - let h_stop = LCD_HSYNC + LCD_HBP + LCD_WIDTH - 1 - let v_start = LCD_VSYNC + LCD_VBP + 0 - let v_stop = LCD_VSYNC + LCD_VBP + LCD_HEIGHT - 1 - let pitch = LCD_WIDTH * LCD_PIXSIZE - let length = LCD_WIDTH * LCD_PIXSIZE + 3 - ltdc.layer[0].whpcr.write { - $0.raw.whsppos = h_stop - $0.raw.whstpos = h_start - } - ltdc.layer[0].wvpcr.write { - $0.raw.wvsppos = v_stop - $0.raw.wvstpos = v_start - } - ltdc.layer[0].pfcr.write { - $0.raw.pf = 0 // ARGB8888 - } - ltdc.layer[0].cfbar.write { - $0.raw.cfbadd = SDRAM_BASE - } - ltdc.layer[0].cfblr.write { - $0.raw.cfbp = pitch - $0.raw.cfbll = length - } - ltdc.layer[0].cfblnr.write { - $0.raw.cfblnbr = LCD_HEIGHT - } - ltdc.layer[0].cacr.write { - $0.raw.consta = 0xFF - } - ltdc.layer[0].bfcr.write { - $0.raw.bf1 = 6 - $0.raw.bf2 = 7 - } - - // Enable layer 1 - ltdc.layer[0].cr.modify { $0.raw.len = 1 } - - // Turn on the display - ltdc.srcr.modify { $0.raw.vbr = 1 } - ltdc.gcr.modify { $1.ltdcen = .Enabled } - - // Enable interrupts - ltdc.ier.modify { $0.raw.rrie = 1 } - nvic.iser2.modify { - $0.raw.setena = (1 << (88 - 64)) // LTDC_IRQn is typically 88 - } - } - - static func setFrameBuffer(_ p: UnsafeRawPointer) { - ltdc.layer[0].cfbar.write { $0.raw.cfbadd = UInt32(UInt(bitPattern: p)) } - } - - static func reloadConfiguration() { - ltdc.srcr.modify { $0.raw.vbr = 1 } - } -} diff --git a/stm32-lvgl/Sources/Application/Main.swift b/stm32-lvgl/Sources/Application/Main.swift deleted file mode 100644 index d2722dc4..00000000 --- a/stm32-lvgl/Sources/Application/Main.swift +++ /dev/null @@ -1,163 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import CLVGL -import Registers -import Support - -@main -struct Main { - static func main() { - // main is called very early in the boot process; here we are just after - // (1) reset IRQ entrypoint, (2) enabling FPU, (3) relocating data sections - // from flash to SRAM. Notably, no HW register configuration has been done - // yet (except for the FPU enablement), and no static constructors have been - // called yet. - - // We boot at 16 MHz. - initDebug() - initUartOutput() - - withInterruptsDisabled { - log("initClock()") - initClocks() - - log("initInterrupts()") - initInterrupts() - - // Reset the vector table to where it should be. - log("init VTOR") - scb.vtor.modify { $0.storage = 0x0800_0000 } - } - - log("systemSetCoreClock()") - systemSetCoreClock() - - // We are running at 200 MHz CPU frequency now. Set the UART baud rate to - // 115200 again based on the new CPU frequency. - usart1.brr.modify { $0.raw.storage = 100_000_000 / 115_200 } - - log("initGpio()") - initGpio() - log("initSdram()") - initSdram() - log("Lcd.initialize()") - Lcd.initialize() - - log("initSysTick") - initSysTick() - - log("TouchPanel.initialize()") - TouchPanel.initialize() - - // Everything is initialized now. Run application logic. - - //log("dramTest()") - //dramTest() - - log("lvglDemo()") - lvglDemo() - } - - static func dramTest() { - let dramSizeInUInt32 = dramSize / 4 - - func fillAndCheck(pattern: UInt32) { - for i in 0.. 0 { - data!.pointee.point.x = Int32(touchData.x) - data!.pointee.point.y = Int32(touchData.y) - data!.pointee.state = LV_INDEV_STATE_PRESSED - //print("pressed: \(touchData.x) \(touchData.y)") - } else { - data!.pointee.state = LV_INDEV_STATE_RELEASED - //print("released") - } - }) - - // Add UI of application logic - UIAppLogic.createUI() - - log("LVGL setup done, starting render loop") - - while true { - // If we're pending a render, wait. - while lcdInterruptVerticalSyncHandler != nil { /* busy wait */ nop() } - - lv_timer_handler() - - // Update UI of application logic - UIAppLogic.updateFrame() - } - } -} diff --git a/stm32-lvgl/Sources/Application/Pins.swift b/stm32-lvgl/Sources/Application/Pins.swift deleted file mode 100644 index b117108d..00000000 --- a/stm32-lvgl/Sources/Application/Pins.swift +++ /dev/null @@ -1,882 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import MMIO -import Registers -import Support - -/// GPIO Port enumerations -enum GPIOPort: UInt32 { - case portA = 0 - case portB, portC, portD, portE, portF, portG, portH, portI, portJ, portK -} - -/// GPIO Pin numbers -enum GPIOPinNumber: UInt32 { - case pin0 = 0 - case pin1, pin2, pin3, pin4, pin5, pin6, pin7 - case pin8, pin9, pin10, pin11, pin12, pin13, pin14, pin15 - case pin16, pin17, pin18, pin19, pin20, pin21, pin22, pin23 - case pin24, pin25, pin26, pin27, pin28, pin29, pin30, pin31 - case pin32, pin33, pin34, pin35, pin36, pin37, pin38, pin39 - case pin40, pin41 -} - -/// Alternate Function modes -enum AltFunction: UInt8 { - case altFunc0 = 0 - case altFunc1, altFunc2, altFunc3, altFunc4, altFunc5, altFunc6, altFunc7 - case altFunc8, altFunc9, altFunc10, altFunc11, altFunc12, altFunc13, altFunc14, altFunc15 -} - -/// Pull-up/Pull-down configurations -enum GPIOPull: UInt32 { - case none = 0 - case pullUp - case pullDown -} - -/// GPIO pin speed configurations -enum GPIOSpeed: UInt8 { - case low = 0 - case medium - case high - case max -} - -/// GPIO pin modes -enum GPIOMode: UInt32 { - case input = 0 - case output - case alternate - case analog - case disabled -} - -/// GPIO output modes -enum GPIOOutput: UInt32 { - case pushPull = 0 - case openDrain -} - -/// GPIO pin definition structure -struct GPIOPin { - let name: String - let port: GPIOPort - let number: GPIOPinNumber - let mode: GPIOMode - let pull: GPIOPull - let outputType: GPIOOutput - let altFunction: AltFunction - let defaultValue: Bool - let speed: GPIOSpeed - let activeLow: Bool - let inUse: Bool - let isEndOfTable: Bool -} - -/// GPIO direct output control structure -struct GPIOOutputDirect { - let setRegister: UnsafeMutablePointer - let setValue: UInt32 - let clearRegister: UnsafeMutablePointer - let clearValue: UInt32 -} - -/// GPIO direct input control structure -struct GPIOInputDirect { - let register: UnsafeMutablePointer - let mask: UInt32 -} - -/// GPIO mode control structure -struct GPIOModeDirect { - let modeRegister: UnsafeMutablePointer - let modeMask: UInt32 - let inputMode: UInt32 - let outputMode: UInt32 -} - -/// Typealias for GPIO identifier -typealias GPIO = Int - -/// Helper functions to create pin configurations -extension GPIOPin { - static func gpioOutput(name: String, port: GPIOPort, pin: GPIOPinNumber, defaultValue: Bool) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .output, - pull: .none, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: defaultValue, - speed: .low, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioOutputSpeed(name: String, port: GPIOPort, pin: GPIOPinNumber, defaultValue: Bool, speed: GPIOSpeed) - -> GPIOPin - { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .output, - pull: .none, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: defaultValue, - speed: speed, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioOutputActiveLow(name: String, port: GPIOPort, pin: GPIOPinNumber, defaultValue: Bool) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .output, - pull: .none, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: defaultValue, - speed: .low, - activeLow: true, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioOutputOpenDrain(name: String, port: GPIOPort, pin: GPIOPinNumber, defaultValue: Bool) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .output, - pull: .none, - outputType: .openDrain, - altFunction: .altFunc0, - defaultValue: defaultValue, - speed: .low, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioOutputOpenDrainActiveLow(name: String, port: GPIOPort, pin: GPIOPinNumber, defaultValue: Bool) - -> GPIOPin - { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .output, - pull: .none, - outputType: .openDrain, - altFunction: .altFunc0, - defaultValue: defaultValue, - speed: .low, - activeLow: true, - inUse: true, - isEndOfTable: false - ) - } - - static func altFunction(name: String, port: GPIOPort, pin: GPIOPinNumber, alt: AltFunction, outputType: GPIOOutput) - -> GPIOPin - { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .alternate, - pull: .none, - outputType: outputType, - altFunction: alt, - defaultValue: false, - speed: .low, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func altFunctionSpeed( - name: String, port: GPIOPort, pin: GPIOPinNumber, alt: AltFunction, outputType: GPIOOutput, speed: GPIOSpeed - ) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .alternate, - pull: .none, - outputType: outputType, - altFunction: alt, - defaultValue: false, - speed: speed, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func altFunctionSpeedPullUp( - name: String, port: GPIOPort, pin: GPIOPinNumber, alt: AltFunction, outputType: GPIOOutput, speed: GPIOSpeed - ) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .alternate, - pull: .pullUp, - outputType: outputType, - altFunction: alt, - defaultValue: false, - speed: speed, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func analog(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .analog, - pull: .none, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: false, - speed: .low, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func disabled(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .disabled, - pull: .none, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: false, - speed: .low, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioInput(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .input, - pull: .none, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: false, - speed: .low, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioInputSpeed(name: String, port: GPIOPort, pin: GPIOPinNumber, speed: GPIOSpeed) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .input, - pull: .none, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: false, - speed: speed, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioInputPullUp(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .input, - pull: .pullUp, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: false, - speed: .low, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioInputPullDown(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .input, - pull: .pullDown, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: false, - speed: .low, - activeLow: false, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioInputActiveLow(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .input, - pull: .none, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: false, - speed: .low, - activeLow: true, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioInputActiveLowPullUp(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .input, - pull: .pullUp, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: false, - speed: .low, - activeLow: true, - inUse: true, - isEndOfTable: false - ) - } - - static func gpioInputActiveLowPullDown(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { - return GPIOPin( - name: name, - port: port, - number: pin, - mode: .input, - pull: .pullDown, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: false, - speed: .low, - activeLow: true, - inUse: true, - isEndOfTable: false - ) - } - - static func endTable(name: String) -> GPIOPin { - return GPIOPin( - name: name, - port: .portA, - number: .pin0, - mode: .disabled, - pull: .none, - outputType: .pushPull, - altFunction: .altFunc0, - defaultValue: false, - speed: .low, - activeLow: false, - inUse: false, - isEndOfTable: true - ) - } -} - -/// GPIO pin identifier enum -enum GPIOPinID: Int { - case greenLED, blueButton - case uart1TX, uart1RX - case i2c1SCL, i2c1SDA, i2c3SCL, i2c3SDA - case bbI2C_SCL, bbI2C_SDA - case lcdBLCtrl, lcdINT, lcdDISP - case _sdramA0, _sdramA1, _sdramA2, _sdramA3, _sdramA4, _sdramA5, _sdramA6, _sdramA7 - case _sdramA8, _sdramA9, _sdramA10, _sdramA11 - case _sdramBA0, _sdramBA1 - case _sdramDQ0, _sdramDQ1, _sdramDQ2, _sdramDQ3, _sdramDQ4, _sdramDQ5, _sdramDQ6, _sdramDQ7 - case _sdramDQ8, _sdramDQ9, _sdramDQ10, _sdramDQ11, _sdramDQ12, _sdramDQ13, _sdramDQ14, _sdramDQ15 - case _sdramSDNE0, _sdramSDNWE, _sdramSDNRAS, _sdramSDNCAS, _sdramSDCLK, _sdramSDCKE0 - case _sdramNBL0, _sdramNBL1 - case _lcdHSYNC, _lcdVSYNC, _lcdDOTCLK, _lcdENABLE - case _lcdB0, _lcdB1, _lcdB2, _lcdB3, _lcdB4, _lcdB5, _lcdB6, _lcdB7 - case _lcdR0, _lcdR1, _lcdR2, _lcdR3, _lcdR4, _lcdR5, _lcdR6, _lcdR7 - case _lcdG0, _lcdG1, _lcdG2, _lcdG3, _lcdG4, _lcdG5, _lcdG6, _lcdG7 - case _ethTXEN, _ethTXD0, _ethTXD1, _ethRXD0, _ethRXD1, _ethRXER, _ethCRSDV - case _ethMDC, _ethMDIO, _ethREFCLK - case _ulpiCK, _ulpiSTP, _ulpiDIR, _ulpiNXT - case _ulpiD0, _ulpiD1, _ulpiD2, _ulpiD3, _ulpiD4, _ulpiD5, _ulpiD6, _ulpiD7 - case otgHSOC - case tableEnd -} - -/// Pin table definition -/// Note: This implementation uses a dictionary-based lookup which requires: -/// - Memory allocations for the dictionary storage -/// - Runtime dependencies (e.g. on getentropy for hash randomization) -/// - Additional overhead for hash table operations -/// -/// If these dependencies are unwanted, this code could be optimized to use a -/// compile-time array or a switch statement instead. -let pinTable: [GPIOPinID: GPIOPin] = [ - // The LED on the eval board - .greenLED: .gpioOutput(name: "GREEN_LED", port: .portI, pin: .pin1, defaultValue: true), - - // User button on the board - .blueButton: .gpioInput(name: "BLUE_BUTTON", port: .portI, pin: .pin11), - - // Console UART - .uart1TX: .altFunction(name: "UART1_TX", port: .portA, pin: .pin9, alt: .altFunc7, outputType: .pushPull), - .uart1RX: .altFunction(name: "UART1_RX", port: .portB, pin: .pin7, alt: .altFunc7, outputType: .pushPull), - - // I2C buses - .i2c1SCL: .altFunction(name: "I2C1_SCL", port: .portB, pin: .pin8, alt: .altFunc4, outputType: .openDrain), - .i2c1SDA: .altFunction(name: "I2C1_SDA", port: .portB, pin: .pin9, alt: .altFunc4, outputType: .openDrain), - .i2c3SCL: .altFunction(name: "I2C3_SCL", port: .portH, pin: .pin7, alt: .altFunc4, outputType: .openDrain), - .i2c3SDA: .altFunction(name: "I2C3_SDA", port: .portH, pin: .pin8, alt: .altFunc4, outputType: .openDrain), - .bbI2C_SCL: .gpioInput(name: "BBI2C_SCL", port: .portF, pin: .pin8), - .bbI2C_SDA: .gpioInput(name: "BBI2C_SDA", port: .portF, pin: .pin9), - - // LCD pins - .lcdBLCtrl: .gpioOutput(name: "LCD_BL_CTRL", port: .portK, pin: .pin3, defaultValue: true), - .lcdINT: .gpioInputPullUp(name: "LCD_INT", port: .portI, pin: .pin13), - .lcdDISP: .gpioOutput(name: "LCD_DISP", port: .portI, pin: .pin12, defaultValue: true), - - // SDRAM pins - ._sdramA0: .altFunctionSpeed( - name: "_SDRAM_A0", port: .portF, pin: .pin0, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA1: .altFunctionSpeed( - name: "_SDRAM_A1", port: .portF, pin: .pin1, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA2: .altFunctionSpeed( - name: "_SDRAM_A2", port: .portF, pin: .pin2, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA3: .altFunctionSpeed( - name: "_SDRAM_A3", port: .portF, pin: .pin3, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA4: .altFunctionSpeed( - name: "_SDRAM_A4", port: .portF, pin: .pin4, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA5: .altFunctionSpeed( - name: "_SDRAM_A5", port: .portF, pin: .pin5, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA6: .altFunctionSpeed( - name: "_SDRAM_A6", port: .portF, pin: .pin12, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA7: .altFunctionSpeed( - name: "_SDRAM_A7", port: .portF, pin: .pin13, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA8: .altFunctionSpeed( - name: "_SDRAM_A8", port: .portF, pin: .pin14, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA9: .altFunctionSpeed( - name: "_SDRAM_A9", port: .portF, pin: .pin15, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA10: .altFunctionSpeed( - name: "_SDRAM_A10", port: .portG, pin: .pin0, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramA11: .altFunctionSpeed( - name: "_SDRAM_A11", port: .portG, pin: .pin1, alt: .altFunc12, outputType: .pushPull, speed: .max), - - ._sdramBA0: .altFunctionSpeed( - name: "_SDRAM_BA0", port: .portG, pin: .pin4, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramBA1: .altFunctionSpeed( - name: "_SDRAM_BA1", port: .portG, pin: .pin5, alt: .altFunc12, outputType: .pushPull, speed: .max), - - ._sdramDQ0: .altFunctionSpeed( - name: "_SDRAM_DQ0", port: .portD, pin: .pin14, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ1: .altFunctionSpeed( - name: "_SDRAM_DQ1", port: .portD, pin: .pin15, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ2: .altFunctionSpeed( - name: "_SDRAM_DQ2", port: .portD, pin: .pin0, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ3: .altFunctionSpeed( - name: "_SDRAM_DQ3", port: .portD, pin: .pin1, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ4: .altFunctionSpeed( - name: "_SDRAM_DQ4", port: .portE, pin: .pin7, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ5: .altFunctionSpeed( - name: "_SDRAM_DQ5", port: .portE, pin: .pin8, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ6: .altFunctionSpeed( - name: "_SDRAM_DQ6", port: .portE, pin: .pin9, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ7: .altFunctionSpeed( - name: "_SDRAM_DQ7", port: .portE, pin: .pin10, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ8: .altFunctionSpeed( - name: "_SDRAM_DQ8", port: .portE, pin: .pin11, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ9: .altFunctionSpeed( - name: "_SDRAM_DQ9", port: .portE, pin: .pin12, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ10: .altFunctionSpeed( - name: "_SDRAM_DQ10", port: .portE, pin: .pin13, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ11: .altFunctionSpeed( - name: "_SDRAM_DQ11", port: .portE, pin: .pin14, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ12: .altFunctionSpeed( - name: "_SDRAM_DQ12", port: .portE, pin: .pin15, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ13: .altFunctionSpeed( - name: "_SDRAM_DQ13", port: .portD, pin: .pin8, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ14: .altFunctionSpeed( - name: "_SDRAM_DQ14", port: .portD, pin: .pin9, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramDQ15: .altFunctionSpeed( - name: "_SDRAM_DQ15", port: .portD, pin: .pin10, alt: .altFunc12, outputType: .pushPull, speed: .max), - - ._sdramSDNE0: .altFunctionSpeed( - name: "_SDRAM_SDNE0", port: .portH, pin: .pin3, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramSDNWE: .altFunctionSpeed( - name: "_SDRAM_SDNWE", port: .portH, pin: .pin5, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramSDNRAS: .altFunctionSpeed( - name: "_SDRAM_SDNRAS", port: .portF, pin: .pin11, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramSDNCAS: .altFunctionSpeed( - name: "_SDRAM_SDNCAS", port: .portG, pin: .pin15, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramSDCLK: .altFunctionSpeed( - name: "_SDRAM_SDCLK", port: .portG, pin: .pin8, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramSDCKE0: .altFunctionSpeed( - name: "_SDRAM_SDCKE0", port: .portC, pin: .pin3, alt: .altFunc12, outputType: .pushPull, speed: .max), - - ._sdramNBL0: .altFunctionSpeed( - name: "_SDRAM_NBL0", port: .portE, pin: .pin0, alt: .altFunc12, outputType: .pushPull, speed: .max), - ._sdramNBL1: .altFunctionSpeed( - name: "_SDRAM_NBL1", port: .portE, pin: .pin1, alt: .altFunc12, outputType: .pushPull, speed: .max), - - // LCD pins - ._lcdHSYNC: .altFunction(name: "_LCD_HSYNC", port: .portI, pin: .pin9, alt: .altFunc14, outputType: .pushPull), - ._lcdVSYNC: .altFunction(name: "_LCD_VSYNC", port: .portI, pin: .pin8, alt: .altFunc14, outputType: .pushPull), - ._lcdDOTCLK: .altFunction(name: "_LCD_DOTCLK", port: .portI, pin: .pin14, alt: .altFunc14, outputType: .pushPull), - ._lcdENABLE: .altFunction(name: "_LCD_ENABLE", port: .portK, pin: .pin7, alt: .altFunc14, outputType: .pushPull), - - ._lcdB0: .altFunctionSpeed( - name: "_LCD_B0", port: .portE, pin: .pin4, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdB1: .altFunctionSpeed( - name: "_LCD_B1", port: .portJ, pin: .pin13, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdB2: .altFunctionSpeed( - name: "_LCD_B2", port: .portJ, pin: .pin14, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdB3: .altFunctionSpeed( - name: "_LCD_B3", port: .portJ, pin: .pin15, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdB4: .altFunctionSpeed( - name: "_LCD_B4", port: .portG, pin: .pin12, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdB5: .altFunctionSpeed( - name: "_LCD_B5", port: .portK, pin: .pin4, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdB6: .altFunctionSpeed( - name: "_LCD_B6", port: .portK, pin: .pin5, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdB7: .altFunctionSpeed( - name: "_LCD_B7", port: .portK, pin: .pin6, alt: .altFunc14, outputType: .pushPull, speed: .max), - - ._lcdR0: .altFunctionSpeed( - name: "_LCD_R0", port: .portI, pin: .pin15, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdR1: .altFunctionSpeed( - name: "_LCD_R1", port: .portJ, pin: .pin0, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdR2: .altFunctionSpeed( - name: "_LCD_R2", port: .portJ, pin: .pin1, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdR3: .altFunctionSpeed( - name: "_LCD_R3", port: .portJ, pin: .pin2, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdR4: .altFunctionSpeed( - name: "_LCD_R4", port: .portJ, pin: .pin3, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdR5: .altFunctionSpeed( - name: "_LCD_R5", port: .portJ, pin: .pin4, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdR6: .altFunctionSpeed( - name: "_LCD_R6", port: .portJ, pin: .pin5, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdR7: .altFunctionSpeed( - name: "_LCD_R7", port: .portJ, pin: .pin6, alt: .altFunc14, outputType: .pushPull, speed: .max), - - ._lcdG0: .altFunctionSpeed( - name: "_LCD_G0", port: .portJ, pin: .pin7, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdG1: .altFunctionSpeed( - name: "_LCD_G1", port: .portJ, pin: .pin8, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdG2: .altFunctionSpeed( - name: "_LCD_G2", port: .portJ, pin: .pin9, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdG3: .altFunctionSpeed( - name: "_LCD_G3", port: .portJ, pin: .pin10, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdG4: .altFunctionSpeed( - name: "_LCD_G4", port: .portJ, pin: .pin10, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdG5: .altFunctionSpeed( - name: "_LCD_G5", port: .portK, pin: .pin0, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdG6: .altFunctionSpeed( - name: "_LCD_G6", port: .portK, pin: .pin1, alt: .altFunc14, outputType: .pushPull, speed: .max), - ._lcdG7: .altFunctionSpeed( - name: "_LCD_G7", port: .portK, pin: .pin2, alt: .altFunc14, outputType: .pushPull, speed: .max), - - // Ethernet - ._ethTXEN: .altFunctionSpeed( - name: "_ETH_TX_EN", port: .portG, pin: .pin11, alt: .altFunc11, outputType: .pushPull, speed: .max), - ._ethTXD0: .altFunctionSpeed( - name: "_ETH_TXD0", port: .portG, pin: .pin13, alt: .altFunc11, outputType: .pushPull, speed: .max), - ._ethTXD1: .altFunctionSpeed( - name: "_ETH_TXD1", port: .portG, pin: .pin14, alt: .altFunc11, outputType: .pushPull, speed: .max), - ._ethRXD0: .altFunctionSpeed( - name: "_ETH_RXD0", port: .portC, pin: .pin4, alt: .altFunc11, outputType: .pushPull, speed: .max), - ._ethRXD1: .altFunctionSpeed( - name: "_ETH_RXD1", port: .portC, pin: .pin5, alt: .altFunc11, outputType: .pushPull, speed: .max), - ._ethRXER: .altFunctionSpeed( - name: "_ETH_RXER", port: .portG, pin: .pin2, alt: .altFunc11, outputType: .pushPull, speed: .max), - ._ethCRSDV: .altFunctionSpeed( - name: "_ETH_CRS_DV", port: .portA, pin: .pin7, alt: .altFunc11, outputType: .pushPull, speed: .max), - ._ethMDC: .altFunctionSpeed( - name: "_ETH_MDC", port: .portC, pin: .pin1, alt: .altFunc11, outputType: .pushPull, speed: .max), - ._ethMDIO: .altFunctionSpeed( - name: "_ETH_MDIO", port: .portA, pin: .pin2, alt: .altFunc11, outputType: .pushPull, speed: .max), - ._ethREFCLK: .altFunctionSpeed( - name: "_ETH_REF_CLK", port: .portA, pin: .pin1, alt: .altFunc11, outputType: .pushPull, speed: .max), - - // USB HS - ._ulpiCK: .altFunctionSpeed( - name: "_ULPI_CK", port: .portA, pin: .pin5, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiSTP: .altFunctionSpeed( - name: "_ULPI_STP", port: .portC, pin: .pin0, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiDIR: .altFunctionSpeed( - name: "_ULPI_DIR", port: .portC, pin: .pin2, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiNXT: .altFunctionSpeed( - name: "_ULPI_NXT", port: .portH, pin: .pin4, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiD0: .altFunctionSpeed( - name: "_ULPI_D0", port: .portA, pin: .pin3, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiD1: .altFunctionSpeed( - name: "_ULPI_D1", port: .portB, pin: .pin0, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiD2: .altFunctionSpeed( - name: "_ULPI_D2", port: .portB, pin: .pin1, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiD3: .altFunctionSpeed( - name: "_ULPI_D3", port: .portB, pin: .pin10, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiD4: .altFunctionSpeed( - name: "_ULPI_D4", port: .portB, pin: .pin11, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiD5: .altFunctionSpeed( - name: "_ULPI_D5", port: .portB, pin: .pin12, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiD6: .altFunctionSpeed( - name: "_ULPI_D6", port: .portB, pin: .pin13, alt: .altFunc10, outputType: .pushPull, speed: .max), - ._ulpiD7: .altFunctionSpeed( - name: "_ULPI_D7", port: .portB, pin: .pin5, alt: .altFunc10, outputType: .pushPull, speed: .max), - - .otgHSOC: .gpioInput(name: "OTG_HS_OC", port: .portE, pin: .pin3), -] - -let GPIO_CHANNELS = 11 - -/// Initialize all GPIO pins -func initGpio() { - for (_, pin) in pinTable { - if pin.inUse { - gpioInitPin(pin: pin) - } - } -} - -/// Track which ports have been enabled -var gpioPortEnabled: [Bool] = Array(repeating: false, count: GPIO_CHANNELS) - -/// GPIO port base registers indexed by the port enum -let gpioPortBases: [GPIOA] = [ - gpioa, - gpiob, - gpioc, - gpiod, - gpioe, - gpiof, - gpiog, - gpioh, - gpioi, - gpioj, - gpiok, -] - -/// Map of GPIO pull values to hardware values -let gpioPullupMap: [UInt8] = [ - 0, // GPIO_PINPULL_NONE - See 7.4.4 in RM0390 - 1, // GPIO_PINPULL_UP - 2, // GPIO_PINPULL_DOWN -] - -extension Register { - func set(index: Int, value: GPIOA.PUPDR.PUPDR0Values) { - self.clear(index: index) - self.modify { $0.storage |= UInt32(value.rawValue) << (2 * index) } - } - func clear(index: Int) { - self.modify { $0.storage &= ~(0b11 << (2 * index)) } - } -} -extension Register { - func set(index: Int, value: GPIOA.MODER.MODER0Values) { - self.clear(index: index) - self.modify { $0.storage |= UInt32(value.rawValue) << (2 * index) } - } - func clear(index: Int) { - self.modify { $0.storage &= ~(0b11 << (2 * index)) } - } -} -extension Register { - func set(index: Int, value: GPIOA.OSPEEDR.OSPEEDR0Values) { - self.clear(index: index) - self.modify { $0.storage |= UInt32(value.rawValue) << (2 * index) } - } - func clear(index: Int) { - self.modify { $0.storage &= ~(0b11 << (2 * index)) } - } -} -extension Register { - func set(index: Int, value: Bool = true) { - guard value else { - self.clear(index: index) - return - } - self.modify { $0.storage |= 1 << (1 * index) } - } - func clear(index: Int) { - self.modify { $0.storage &= ~(1 << (1 * index)) } - } -} -extension Register { - func set(gpioPort index: Int) { - self.modify { $0.storage |= 1 << (1 * index) } - } - func clear(gpioPort index: Int) { - self.modify { $0.storage &= ~(1 << (1 * index)) } - } -} -extension Register { - func set(index: Int) { - self.write { $0.storage = UInt32(1) << Int(index) } - } - func clear(index: Int) { - self.write { $0.storage = UInt32(1) << (16 + Int(index)) } - } -} -extension GPIOA { - func afrSet(index: Int, value: GPIOA.AFRL.AFRL0Values) { - precondition(index >= 0 && index < 16) - let afrShift = (index % 8) * 4 - if index >= 8 { - self.afrh.modify { - $0.storage &= ~(0b1111 << afrShift) - $0.storage |= UInt32(value.rawValue) << afrShift - } - } else { - self.afrl.modify { - $0.storage &= ~(0b1111 << afrShift) - $0.storage |= UInt32(value.rawValue) << afrShift - } - } - } -} - -/// Disable a pin (effectively reset to POR-state) -private func gpioDisabled(pin: GPIOPin) { - let port = gpioPortBases[Int(pin.port.rawValue)] - let pinNumber = Int(pin.number.rawValue) - - port.moder.clear(index: pinNumber) // clear mode to INPUT - port.otyper.clear(index: pinNumber) // push-pull - - port.pupdr.clear(index: pinNumber) // set mode to no pulls - port.ospeedr.set(index: pinNumber, value: .init(rawValue: pin.speed.rawValue)) // set speed -} - -/// Disable a pin by its GPIO identifier -/// -/// - Parameter gpio: The GPIO identifier -func gpioDisabled(gpio: GPIO) { - if let pin = pinTable[GPIOPinID(rawValue: gpio) ?? .tableEnd] { - gpioDisabled(pin: pin) - } -} - -/// Enable clock for a specific GPIO port -/// -/// - Parameter port: The port number to enable -private func enableClockForPort(port: UInt32) { - // Enable each port at most once, and leave it enabled - precondition(port < UInt32(GPIO_CHANNELS)) - - withInterruptsDisabled { - - if !gpioPortEnabled[Int(port)] { - gpioPortEnabled[Int(port)] = true - - // Enable the clock for this port - rcc.ahb1enr.set(gpioPort: Int(port)) - - // Wait two peripheral clocks - delay(2) - } - - } -} - -/// Initialize a single GPIO pin from its configuration -/// -/// - Parameter pin: The pin configuration -func gpioInitPin(pin: GPIOPin) { - // Enable clocks to this port, and leave enabled at all times - enableClockForPort(port: pin.port.rawValue) - - // Handy pointers - let port = gpioPortBases[Int(pin.port.rawValue)] - let pinNumber = pin.number.rawValue - - // Default everything to the state at POR - gpioDisabled(pin: pin) - - // Set up the pin - switch pin.mode { - case .input: - // For a real input pin, set the pullup mode - port.pupdr.set(index: Int(pinNumber), value: .init(rawValue: gpioPullupMap[Int(pin.pull.rawValue)])) - - case .output: - port.moder.set(index: Int(pinNumber), value: .init(rawValue: 1)) // mode OUTPUT - - if pin.outputType == .pushPull { - port.otyper.clear(index: Int(pinNumber)) // push-pull - } else { - port.otyper.set(index: Int(pinNumber)) // open-drain - } - - // Set the default output value - if pin.defaultValue { - port.bsrr.set(index: Int(pinNumber)) - } else { - port.bsrr.clear(index: Int(pinNumber)) - } - - case .alternate: - port.moder.set(index: Int(pinNumber), value: .init(rawValue: 2)) // mode ALT FUNC - - // Set the alternate function - port.afrSet(index: Int(pinNumber), value: .init(rawValue: pin.altFunction.rawValue)) - - // push-pull or open-drain - port.otyper.set(index: Int(pinNumber), value: pin.outputType == .openDrain) - - case .analog: - port.moder.set(index: Int(pinNumber), value: .init(rawValue: 3)) // mode ANALOG - - case .disabled: - // Already handled by gpioDisabled - break - } -} diff --git a/stm32-lvgl/Sources/Application/Sdram.swift b/stm32-lvgl/Sources/Application/Sdram.swift deleted file mode 100644 index 392af049..00000000 --- a/stm32-lvgl/Sources/Application/Sdram.swift +++ /dev/null @@ -1,109 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import MMIO -import Registers -import Support - -let dramBase = UnsafeMutableRawPointer(bitPattern: 0xC000_0000 as UInt)! -let dramBaseAsUInt32 = UnsafeMutablePointer(bitPattern: 0xC000_0000 as UInt)! -let dramSize = 0x0080_0000 // 8 MB - -// SDRAM part is a MT48LC4M32B2B5 (Micron) -// Geometry (bits): 12 row, 8 col, 2 bank -// Data width: 16 bits -// Clock frequency: 133Mhz -// Refresh rate: 4K/64ms. - -// The SDRAM clock can only be generated as 1/2 or 1/3 the core clock, -// so we'll run it at 168 / 2 = 84MHz. Kinda pokey. -// CAS Latency will be 3. - -// Initialize the SDRAM controller. This is somewhat specific to -// the chip populated on the discovery board. -func initSdram() { - // Enable clock to the FMC - rcc.ahb3enr.modify { $0.fmcen = .Enabled } - - // Program memory device features into FMC_SDCRx - fmc.sdcr[0].write { - $0.rpipe = .Clocks1 // One clock cycle pipe delay - $0.sdclk = .Div2 // SDCLK is 1/2 HCLK - $0.cas = .Clocks3 // CAS latency 3 - $0.nb = .NB4 // 4 banks - $0.mwid = .Bits16 // 16 bits wide - $0.nr = .Bits12 // 12 row bits - $0.nc = .Bits8 // 8 col bits - } - - // Program memory timing into FMC_SDTRx - fmc.sdtr[0].write { - $0.raw.tmrd = 1 // 1 cycle - $0.raw.txsr = 5 // 6 cycles, 72ns - $0.raw.tras = 3 // 4 cycles, 48ns - $0.raw.trc = 5 // 6 cycles, 72ns - $0.raw.twr = 1 // 2 cycles for CAS=3 - $0.raw.trp = 1 // 2 cycles, 24ns - $0.raw.trcd = 1 // 2 cycles, 24ns - } - - while fmc.sdsr.read().raw.busy != 0 { /* busy wait */ } - - // Set mode bits to '001' and configure FMC_SDCMR to start clock - fmc.sdcmr.write { - $0.raw.mode = 1 // Clock config enable - $0.raw.nrfs = 1 // Number of refresh cycles - $0.raw.ctb1 = 1 // Chip is on 1st csel - } - - delay(1000) // Wait - - // Set mode bits to '010' and configure FMC_SDCMR to issue "precharge all" - fmc.sdcmr.write { - $0.raw.mode = 2 // Precharge All - $0.raw.nrfs = 1 // Number of refresh cycles - $0.raw.ctb1 = 1 // Chip is on 1st csel - } - - while fmc.sdsr.read().raw.busy != 0 { /* busy wait */ } - - // Set mode bits to '011' and configure FMC_SDCMR to start auto-refresh - fmc.sdcmr.write { - $0.raw.mode = 3 // Start auto-refresh - $0.raw.nrfs = 4 // Number of refresh cycles - $0.raw.ctb1 = 1 // Chip is on 1st csel - } - - while fmc.sdsr.read().raw.busy != 0 { /* busy wait */ } - - // Configure MRD field for specific device (latency) and issue "Load Mode Register" - fmc.sdcmr.write { - $0.raw.mode = 4 // Load Mode Register - $0.raw.nrfs = 1 // Number of refresh cycles - $0.raw.mrd = 0x230 // Mode value (2<<4) - $0.raw.ctb1 = 1 // Chip is on 1st csel - } - - while fmc.sdsr.read().raw.busy != 0 { /* busy wait */ } - - // Program refresh rate into FMC_SDRTR. 64ms spread out over 4K rows, so 15.625us/row - // with 12ns per cycle, that's 1302 cycles/row. Subtract 20 so 1282. - fmc.sdrtr.write { - $0.raw.count = 683 // Refresh rate - } - - while fmc.sdsr.read().raw.busy != 0 { /* busy wait */ } - - // Clear out memory. - for i in 0.. TouchData { - // Read device registers 0x00 through 0x06: - // 0x00 DEVIDE_MODE Device Mode (bits 4...6) - // 0x01 GEST_ID Gesture ID - // 0x02 TD_STATUS Number of touch points (bits 0...3) - // 0x03 TOUCH1_XH 1st Event Flag (bits 6...7), 1st Touch X Position Hi Bits (bits 0...3) - // 0x04 TOUCH1_XL 1st Touch X Position Lo Bits - // 0x05 TOUCH1_YH 1st Touch ID (bits 4...7), 1st Touch Y Position Hi Bits (bits 0...3) - // 0x06 TOUCH1_YL 1st Touch Y Position Lo Bits - - guard touchPanel.write(data: [0x00]) else { - print("Send failed") - return TouchData(numberOfTouchPoints: 0, x: 0, y: 0) - } - - var buf = [UInt8](repeating: 0, count: 7) - guard touchPanel.read(buffer: &buf, length: 7) else { - print("Read failed") - return TouchData(numberOfTouchPoints: 0, x: 0, y: 0) - } - - let x = Int(buf[3] & 0b1111) << 8 | Int(buf[4]) - let y = Int(buf[5] & 0b1111) << 8 | Int(buf[6]) - - // On STM32F746G discovery board, the x and y are swapped. - return TouchData(numberOfTouchPoints: Int(buf[2] & 0b1111), x: y, y: x) - } - -} diff --git a/stm32-lvgl/Sources/Application/UIAppLogic.swift b/stm32-lvgl/Sources/Application/UIAppLogic.swift deleted file mode 100644 index 67dbfeca..00000000 --- a/stm32-lvgl/Sources/Application/UIAppLogic.swift +++ /dev/null @@ -1,139 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import CLVGL - -// This is shared code (via a symlink) between the firmware build and the host -// SDL-based "simulator" app. No platform/firmware specific logic to stay -// portable. -enum UIAppLogic { - static var clickCount = 0 - static var button: OpaquePointer! = nil - static var buttonLabel: OpaquePointer! = nil - static var spinnerLabel: OpaquePointer! = nil - - static var frameCounter = 0 - - // Keep styles persistent for the lifetime of the application - static var style = lv_style_t() - static var labelStyle = lv_style_t() - static var gradient = lv_grad_dsc_t() - - static var widgetDemoScreen: OpaquePointer! = nil - - static func createUI() { - // Get the active screen - let screen = lv_screen_active() - - // Create a gradient background - lv_style_init(&style) - - // Create gradient colors (blue to red) - gradient.dir = LV_GRAD_DIR_VER - gradient.stops_count = 2 - gradient.stops.0.color = lv_color_make(0, 0, 0) // Black - gradient.stops.0.opa = UInt8(LV_OPA_COVER) - gradient.stops.0.frac = 0 - gradient.stops.1.color = lv_color_make(255, 0, 0) // Red - gradient.stops.1.opa = UInt8(LV_OPA_COVER) - gradient.stops.1.frac = 255 - - // Apply gradient to the style background - lv_style_set_bg_grad(&style, &gradient) - lv_style_set_bg_opa(&style, UInt8(LV_OPA_COVER)) - - // Apply the style to the screen - lv_obj_add_style(screen, &style, 0) - - // Create a button in the top right - button = lv_button_create(screen) - lv_obj_set_size(button, 120, 50) - lv_obj_align(button, LV_ALIGN_TOP_RIGHT, -10, 10) - buttonLabel = lv_label_create(button) - lv_label_set_text(buttonLabel, "Click me") - lv_obj_center(buttonLabel) - lv_obj_add_event_cb( - button, - { event in - Self.clickCount += 1 - lv_label_set_text(Self.buttonLabel, "Clicked \(Self.clickCount)") - }, LV_EVENT_CLICKED, nil) - - // Create a 'Demo' button in the bottom right - let demoButton = lv_button_create(screen) - lv_obj_set_size(demoButton, 120, 50) - lv_obj_align(demoButton, LV_ALIGN_BOTTOM_RIGHT, -10, -10) - let demoButtonLabel = lv_label_create(demoButton) - lv_label_set_text(demoButtonLabel, "Widget Demo") - lv_obj_center(demoButtonLabel) - lv_obj_add_event_cb( - demoButton, - { event in - lv_screen_load(Self.widgetDemoScreen) - }, LV_EVENT_CLICKED, nil) - - // Create a label - let label = lv_label_create(screen) - lv_label_set_text(label, "Hello LVGL!") - lv_obj_align(label, LV_ALIGN_TOP_MID, 0, 20) - - // Make the label white for better visibility - lv_style_init(&labelStyle) - lv_style_set_text_color(&labelStyle, lv_color_white()) - lv_obj_add_style(label, &labelStyle, 0) - - // Create a spinner - let spinner = lv_spinner_create(screen) - - // Set spinner size - lv_obj_set_size(spinner, 60, 60) - - // Center the spinner on screen - lv_obj_align(spinner, LV_ALIGN_CENTER, 0, 0) - - // Configure spinner animation - lv_spinner_set_anim_params(spinner, 2_000, 200) // anim time, angle - - // Create a dropdown menu - let dropdown = lv_dropdown_create(screen) - lv_dropdown_set_options(dropdown, "Option 1\nOption 2\nOption 3\nOption 4") - lv_obj_set_size(dropdown, 150, 40) - lv_obj_align(dropdown, LV_ALIGN_TOP_LEFT, 10, 10) - - // Add event handler for dropdown selection - lv_obj_add_event_cb( - dropdown, - { event in - let dropdown = lv_event_get_target_obj(event) - let selectedIndex = lv_dropdown_get_selected(dropdown) - print("Selected option \(selectedIndex)") - }, LV_EVENT_VALUE_CHANGED, nil) - - // Add a label under the spinner - spinnerLabel = lv_label_create(screen) - lv_label_set_text(spinnerLabel, "Loading...") - lv_obj_align(spinnerLabel, LV_ALIGN_BOTTOM_LEFT, 20, -20) - lv_obj_add_style(spinnerLabel, &labelStyle, 0) - - // Create a 2nd screen with the widgets demo app from LVGL, then switch back - // to the original screen. - widgetDemoScreen = lv_obj_create(nil) - lv_screen_load(widgetDemoScreen) - @_extern(c) func lv_demo_widgets() - lv_demo_widgets() - lv_screen_load(screen) - } - - static func updateFrame() { - frameCounter += 1 - lv_label_set_text(spinnerLabel, "Uptime (ms): \(uptimeInMs)\nFrames: \(frameCounter)") - } -} diff --git a/stm32-lvgl/Sources/CLVGL/include/CLVGL.h b/stm32-lvgl/Sources/CLVGL/include/CLVGL.h deleted file mode 100644 index 88980249..00000000 --- a/stm32-lvgl/Sources/CLVGL/include/CLVGL.h +++ /dev/null @@ -1,12 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include "../../../lvgl/lvgl.h" diff --git a/stm32-lvgl/Sources/CLVGL/include/lv_conf.h b/stm32-lvgl/Sources/CLVGL/include/lv_conf.h deleted file mode 100644 index ea619dcc..00000000 --- a/stm32-lvgl/Sources/CLVGL/include/lv_conf.h +++ /dev/null @@ -1,1273 +0,0 @@ -#ifndef LV_CONF_H -#define LV_CONF_H - -/*==================== - COLOR SETTINGS - *====================*/ - -/** Color depth: 1 (I1), 8 (L8), 16 (RGB565), 24 (RGB888), 32 (XRGB8888) */ -#define LV_COLOR_DEPTH 32 - -/********************* - * DEMO USAGE - *********************/ - -#define LV_USE_DEMO_WIDGETS 1 - -/*========================= - STDLIB WRAPPER SETTINGS - *=========================*/ - -/** Possible values - * - LV_STDLIB_BUILTIN: LVGL's built in implementation - * - LV_STDLIB_CLIB: Standard C functions, like malloc, strlen, etc - * - LV_STDLIB_MICROPYTHON: MicroPython implementation - * - LV_STDLIB_RTTHREAD: RT-Thread implementation - * - LV_STDLIB_CUSTOM: Implement the functions externally - */ -#define LV_USE_STDLIB_MALLOC LV_STDLIB_BUILTIN - -/** Possible values - * - LV_STDLIB_BUILTIN: LVGL's built in implementation - * - LV_STDLIB_CLIB: Standard C functions, like malloc, strlen, etc - * - LV_STDLIB_MICROPYTHON: MicroPython implementation - * - LV_STDLIB_RTTHREAD: RT-Thread implementation - * - LV_STDLIB_CUSTOM: Implement the functions externally - */ -#define LV_USE_STDLIB_STRING LV_STDLIB_BUILTIN - -/** Possible values - * - LV_STDLIB_BUILTIN: LVGL's built in implementation - * - LV_STDLIB_CLIB: Standard C functions, like malloc, strlen, etc - * - LV_STDLIB_MICROPYTHON: MicroPython implementation - * - LV_STDLIB_RTTHREAD: RT-Thread implementation - * - LV_STDLIB_CUSTOM: Implement the functions externally - */ -#define LV_USE_STDLIB_SPRINTF LV_STDLIB_BUILTIN - -#define LV_STDINT_INCLUDE -#define LV_STDDEF_INCLUDE -#define LV_STDBOOL_INCLUDE -#define LV_INTTYPES_INCLUDE -#define LV_LIMITS_INCLUDE -#define LV_STDARG_INCLUDE - -#if LV_USE_STDLIB_MALLOC == LV_STDLIB_BUILTIN - /** Size of memory available for `lv_malloc()` in bytes (>= 2kB) */ - #define LV_MEM_SIZE (96 * 1024U) /**< [bytes] */ - - /** Size of the memory expand for `lv_malloc()` in bytes */ - #define LV_MEM_POOL_EXPAND_SIZE 0 - - /** Set an address for the memory pool instead of allocating it as a normal array. Can be in external SRAM too. */ - #define LV_MEM_ADR 0 /**< 0: unused*/ - /* Instead of an address give a memory allocator that will be called to get a memory pool for LVGL. E.g. my_malloc */ - #if LV_MEM_ADR == 0 - #undef LV_MEM_POOL_INCLUDE - #undef LV_MEM_POOL_ALLOC - #endif -#endif /*LV_USE_STDLIB_MALLOC == LV_STDLIB_BUILTIN*/ - -/*==================== - HAL SETTINGS - *====================*/ - -/** Default display refresh, input device read and animation step period. */ -#define LV_DEF_REFR_PERIOD 33 /**< [ms] */ - -/** Default Dots Per Inch. Used to initialize default sizes such as widgets sized, style paddings. - * (Not so important, you can adjust it to modify default sizes and spaces.) */ -#define LV_DPI_DEF 130 /**< [px/inch] */ - -/*================= - * OPERATING SYSTEM - *=================*/ -/** Select operating system to use. Possible options: - * - LV_OS_NONE - * - LV_OS_PTHREAD - * - LV_OS_FREERTOS - * - LV_OS_CMSIS_RTOS2 - * - LV_OS_RTTHREAD - * - LV_OS_WINDOWS - * - LV_OS_MQX - * - LV_OS_SDL2 - * - LV_OS_CUSTOM */ -#define LV_USE_OS LV_OS_NONE - -#if LV_USE_OS == LV_OS_CUSTOM - #define LV_OS_CUSTOM_INCLUDE -#endif -#if LV_USE_OS == LV_OS_FREERTOS - /* - * Unblocking an RTOS task with a direct notification is 45% faster and uses less RAM - * than unblocking a task using an intermediary object such as a binary semaphore. - * RTOS task notifications can only be used when there is only one task that can be the recipient of the event. - */ - #define LV_USE_FREERTOS_TASK_NOTIFY 1 -#endif - -/*======================== - * RENDERING CONFIGURATION - *========================*/ - -/** Align stride of all layers and images to this bytes */ -#define LV_DRAW_BUF_STRIDE_ALIGN 1 - -/** Align start address of draw_buf addresses to this bytes*/ -#define LV_DRAW_BUF_ALIGN 4 - -/** Using matrix for transformations. - * Requirements: - * - `LV_USE_MATRIX = 1`. - * - Rendering engine needs to support 3x3 matrix transformations. */ -#define LV_DRAW_TRANSFORM_USE_MATRIX 0 - -/* If a widget has `style_opa < 255` (not `bg_opa`, `text_opa` etc) or not NORMAL blend mode - * it is buffered into a "simple" layer before rendering. The widget can be buffered in smaller chunks. - * "Transformed layers" (if `transform_angle/zoom` are set) use larger buffers - * and can't be drawn in chunks. */ - -/** The target buffer size for simple layer chunks. */ -#define LV_DRAW_LAYER_SIMPLE_BUF_SIZE (24 * 1024) /**< [bytes]*/ - -/* Limit the max allocated memory for simple and transformed layers. - * It should be at least `LV_DRAW_LAYER_SIMPLE_BUF_SIZE` sized but if transformed layers are also used - * it should be enough to store the largest widget too (width x height x 4 area). - * Set it to 0 to have no limit. */ -#define LV_DRAW_LAYER_MAX_MEMORY 0 /**< No limit by default [bytes]*/ - -/** Stack size of drawing thread. - * NOTE: If FreeType or ThorVG is enabled, it is recommended to set it to 32KB or more. - */ -#define LV_DRAW_THREAD_STACK_SIZE (8 * 1024) /**< [bytes]*/ - -#define LV_USE_DRAW_SW 1 -#if LV_USE_DRAW_SW == 1 - /* - * Selectively disable color format support in order to reduce code size. - * NOTE: some features use certain color formats internally, e.g. - * - gradients use RGB888 - * - bitmaps with transparency may use ARGB8888 - */ - #define LV_DRAW_SW_SUPPORT_RGB565 1 - #define LV_DRAW_SW_SUPPORT_RGB565A8 1 - #define LV_DRAW_SW_SUPPORT_RGB888 1 - #define LV_DRAW_SW_SUPPORT_XRGB8888 1 - #define LV_DRAW_SW_SUPPORT_ARGB8888 1 - #define LV_DRAW_SW_SUPPORT_L8 1 - #define LV_DRAW_SW_SUPPORT_AL88 1 - #define LV_DRAW_SW_SUPPORT_A8 1 - #define LV_DRAW_SW_SUPPORT_I1 1 - - /* The threshold of the luminance to consider a pixel as - * active in indexed color format */ - #define LV_DRAW_SW_I1_LUM_THRESHOLD 127 - - /** Set number of draw units. - * - > 1 requires operating system to be enabled in `LV_USE_OS`. - * - > 1 means multiple threads will render the screen in parallel. */ - #define LV_DRAW_SW_DRAW_UNIT_CNT 1 - - /** Use Arm-2D to accelerate software (sw) rendering. */ - #define LV_USE_DRAW_ARM2D_SYNC 0 - - /** Enable native helium assembly to be compiled. */ - #define LV_USE_NATIVE_HELIUM_ASM 0 - - /** - * - 0: Use a simple renderer capable of drawing only simple rectangles with gradient, images, text, and straight lines only. - * - 1: Use a complex renderer capable of drawing rounded corners, shadow, skew lines, and arcs too. */ - #define LV_DRAW_SW_COMPLEX 1 - - #if LV_DRAW_SW_COMPLEX == 1 - /** Allow buffering some shadow calculation. - * LV_DRAW_SW_SHADOW_CACHE_SIZE is the maximum shadow size to buffer, where shadow size is - * `shadow_width + radius`. Caching has LV_DRAW_SW_SHADOW_CACHE_SIZE^2 RAM cost. */ - #define LV_DRAW_SW_SHADOW_CACHE_SIZE 0 - - /** Set number of maximally-cached circle data. - * The circumference of 1/4 circle are saved for anti-aliasing. - * `radius * 4` bytes are used per circle (the most often used radiuses are saved). - * - 0: disables caching */ - #define LV_DRAW_SW_CIRCLE_CACHE_SIZE 4 - #endif - - #define LV_USE_DRAW_SW_ASM LV_DRAW_SW_ASM_NONE - - #if LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_CUSTOM - #define LV_DRAW_SW_ASM_CUSTOM_INCLUDE "" - #endif - - /** Enable drawing complex gradients in software: linear at an angle, radial or conical */ - #define LV_USE_DRAW_SW_COMPLEX_GRADIENTS 0 - -#endif - -/*Use TSi's aka (Think Silicon) NemaGFX */ -#define LV_USE_NEMA_GFX 0 - -#if LV_USE_NEMA_GFX - /** Select which NemaGFX HAL to use. Possible options: - * - LV_NEMA_HAL_CUSTOM - * - LV_NEMA_HAL_STM32 */ - #define LV_USE_NEMA_HAL LV_NEMA_HAL_CUSTOM - #if LV_USE_NEMA_HAL == LV_NEMA_HAL_STM32 - #define LV_NEMA_STM32_HAL_INCLUDE - #endif - - /*Enable Vector Graphics Operations. Available only if NemaVG library is present*/ - #define LV_USE_NEMA_VG 0 - #if LV_USE_NEMA_VG - /*Define application's resolution used for VG related buffer allocation */ - #define LV_NEMA_GFX_MAX_RESX 800 - #define LV_NEMA_GFX_MAX_RESY 600 - #endif -#endif - -/** Use NXP's VG-Lite GPU on iMX RTxxx platforms. */ -#define LV_USE_DRAW_VGLITE 0 - -#if LV_USE_DRAW_VGLITE - /** Enable blit quality degradation workaround recommended for screen's dimension > 352 pixels. */ - #define LV_USE_VGLITE_BLIT_SPLIT 0 - - #if LV_USE_OS - /** Use additional draw thread for VG-Lite processing. */ - #define LV_USE_VGLITE_DRAW_THREAD 1 - - #if LV_USE_VGLITE_DRAW_THREAD - /** Enable VGLite draw async. Queue multiple tasks and flash them once to the GPU. */ - #define LV_USE_VGLITE_DRAW_ASYNC 1 - #endif - #endif - - /** Enable VGLite asserts. */ - #define LV_USE_VGLITE_ASSERT 0 -#endif - -/** Use NXP's PXP on iMX RTxxx platforms. */ -#define LV_USE_PXP 0 - -#if LV_USE_PXP - /** Use PXP for drawing.*/ - #define LV_USE_DRAW_PXP 1 - - /** Use PXP to rotate display.*/ - #define LV_USE_ROTATE_PXP 0 - - #if LV_USE_DRAW_PXP && LV_USE_OS - /** Use additional draw thread for PXP processing.*/ - #define LV_USE_PXP_DRAW_THREAD 1 - #endif - - /** Enable PXP asserts. */ - #define LV_USE_PXP_ASSERT 0 -#endif - -/** Use NXP's G2D on MPU platforms. */ -#define LV_USE_DRAW_G2D 0 - -#if LV_USE_DRAW_G2D - /** Maximum number of buffers that can be stored for G2D draw unit. - * Includes the frame buffers and assets. */ - #define LV_G2D_HASH_TABLE_SIZE 50 - - #if LV_USE_OS - /** Use additional draw thread for G2D processing.*/ - #define LV_USE_G2D_DRAW_THREAD 1 - #endif - - /** Enable G2D asserts. */ - #define LV_USE_G2D_ASSERT 0 -#endif - -/** Use Renesas Dave2D on RA platforms. */ -#define LV_USE_DRAW_DAVE2D 0 - -/** Draw using cached SDL textures*/ -#define LV_USE_DRAW_SDL 0 - -/** Use VG-Lite GPU. */ -#define LV_USE_DRAW_VG_LITE 0 - -#if LV_USE_DRAW_VG_LITE - /** Enable VG-Lite custom external 'gpu_init()' function */ - #define LV_VG_LITE_USE_GPU_INIT 0 - - /** Enable VG-Lite assert. */ - #define LV_VG_LITE_USE_ASSERT 0 - - /** VG-Lite flush commit trigger threshold. GPU will try to batch these many draw tasks. */ - #define LV_VG_LITE_FLUSH_MAX_COUNT 8 - - /** Enable border to simulate shadow. - * NOTE: which usually improves performance, - * but does not guarantee the same rendering quality as the software. */ - #define LV_VG_LITE_USE_BOX_SHADOW 0 - - /** VG-Lite gradient maximum cache number. - * @note The memory usage of a single gradient image is 4K bytes. */ - #define LV_VG_LITE_GRAD_CACHE_CNT 32 - - /** VG-Lite stroke maximum cache number. */ - #define LV_VG_LITE_STROKE_CACHE_CNT 32 -#endif - -/** Accelerate blends, fills, etc. with STM32 DMA2D */ -#define LV_USE_DRAW_DMA2D 0 - -#if LV_USE_DRAW_DMA2D - #define LV_DRAW_DMA2D_HAL_INCLUDE "stm32h7xx_hal.h" - - /* if enabled, the user is required to call `lv_draw_dma2d_transfer_complete_interrupt_handler` - * upon receiving the DMA2D global interrupt - */ - #define LV_USE_DRAW_DMA2D_INTERRUPT 0 -#endif - -/** Draw using cached OpenGLES textures */ -#define LV_USE_DRAW_OPENGLES 0 - -/*======================= - * FEATURE CONFIGURATION - *=======================*/ - -/*------------- - * Logging - *-----------*/ - -/** Enable log module */ -#define LV_USE_LOG 1 -#if LV_USE_LOG - /** Set value to one of the following levels of logging detail: - * - LV_LOG_LEVEL_TRACE Log detailed information. - * - LV_LOG_LEVEL_INFO Log important events. - * - LV_LOG_LEVEL_WARN Log if something unwanted happened but didn't cause a problem. - * - LV_LOG_LEVEL_ERROR Log only critical issues, when system may fail. - * - LV_LOG_LEVEL_USER Log only custom log messages added by the user. - * - LV_LOG_LEVEL_NONE Do not log anything. */ - #define LV_LOG_LEVEL LV_LOG_LEVEL_WARN - - /** - 1: Print log with 'printf'; - * - 0: User needs to register a callback with `lv_log_register_print_cb()`. */ - #define LV_LOG_PRINTF 0 - - /** Set callback to print logs. - * E.g `my_print`. The prototype should be `void my_print(lv_log_level_t level, const char * buf)`. - * Can be overwritten by `lv_log_register_print_cb`. */ - //#define LV_LOG_PRINT_CB - - /** - 1: Enable printing timestamp; - * - 0: Disable printing timestamp. */ - #define LV_LOG_USE_TIMESTAMP 1 - - /** - 1: Print file and line number of the log; - * - 0: Do not print file and line number of the log. */ - #define LV_LOG_USE_FILE_LINE 1 - - /* Enable/disable LV_LOG_TRACE in modules that produces a huge number of logs. */ - #define LV_LOG_TRACE_MEM 1 /**< Enable/disable trace logs in memory operations. */ - #define LV_LOG_TRACE_TIMER 1 /**< Enable/disable trace logs in timer operations. */ - #define LV_LOG_TRACE_INDEV 1 /**< Enable/disable trace logs in input device operations. */ - #define LV_LOG_TRACE_DISP_REFR 1 /**< Enable/disable trace logs in display re-draw operations. */ - #define LV_LOG_TRACE_EVENT 1 /**< Enable/disable trace logs in event dispatch logic. */ - #define LV_LOG_TRACE_OBJ_CREATE 1 /**< Enable/disable trace logs in object creation (core `obj` creation plus every widget). */ - #define LV_LOG_TRACE_LAYOUT 1 /**< Enable/disable trace logs in flex- and grid-layout operations. */ - #define LV_LOG_TRACE_ANIM 1 /**< Enable/disable trace logs in animation logic. */ - #define LV_LOG_TRACE_CACHE 1 /**< Enable/disable trace logs in cache operations. */ -#endif /*LV_USE_LOG*/ - -/*------------- - * Asserts - *-----------*/ - -/* Enable assertion failures if an operation fails or invalid data is found. - * If LV_USE_LOG is enabled, an error message will be printed on failure. */ -#define LV_USE_ASSERT_NULL 1 /**< Check if the parameter is NULL. (Very fast, recommended) */ -#define LV_USE_ASSERT_MALLOC 1 /**< Checks is the memory is successfully allocated or no. (Very fast, recommended) */ -#define LV_USE_ASSERT_STYLE 0 /**< Check if the styles are properly initialized. (Very fast, recommended) */ -#define LV_USE_ASSERT_MEM_INTEGRITY 0 /**< Check the integrity of `lv_mem` after critical operations. (Slow) */ -#define LV_USE_ASSERT_OBJ 0 /**< Check the object's type and existence (e.g. not deleted). (Slow) */ - -/** Add a custom handler when assert happens e.g. to restart MCU. */ -#define LV_ASSERT_HANDLER_INCLUDE -#define LV_ASSERT_HANDLER while(1); /**< Halt by default */ - -/*------------- - * Debug - *-----------*/ - -/** 1: Draw random colored rectangles over the redrawn areas. */ -#define LV_USE_REFR_DEBUG 0 - -/** 1: Draw a red overlay for ARGB layers and a green overlay for RGB layers*/ -#define LV_USE_LAYER_DEBUG 0 - -/** 1: Adds the following behaviors for debugging: - * - Draw overlays with different colors for each draw_unit's tasks. - * - Draw index number of draw unit on white background. - * - For layers, draws index number of draw unit on black background. */ -#define LV_USE_PARALLEL_DRAW_DEBUG 0 - -/*------------- - * Others - *-----------*/ - -#define LV_ENABLE_GLOBAL_CUSTOM 0 -#if LV_ENABLE_GLOBAL_CUSTOM - /** Header to include for custom 'lv_global' function" */ - #define LV_GLOBAL_CUSTOM_INCLUDE -#endif - -/** Default cache size in bytes. - * Used by image decoders such as `lv_lodepng` to keep the decoded image in memory. - * If size is not set to 0, the decoder will fail to decode when the cache is full. - * If size is 0, the cache function is not enabled and the decoded memory will be - * released immediately after use. */ -#define LV_CACHE_DEF_SIZE 0 - -/** Default number of image header cache entries. The cache is used to store the headers of images - * The main logic is like `LV_CACHE_DEF_SIZE` but for image headers. */ -#define LV_IMAGE_HEADER_CACHE_DEF_CNT 0 - -/** Number of stops allowed per gradient. Increase this to allow more stops. - * This adds (sizeof(lv_color_t) + 1) bytes per additional stop. */ -#define LV_GRADIENT_MAX_STOPS 2 - -/** Adjust color mix functions rounding. GPUs might calculate color mix (blending) differently. - * - 0: round down, - * - 64: round up from x.75, - * - 128: round up from half, - * - 192: round up from x.25, - * - 254: round up */ -#define LV_COLOR_MIX_ROUND_OFS 0 - -/** Add 2 x 32-bit variables to each `lv_obj_t` to speed up getting style properties */ -#define LV_OBJ_STYLE_CACHE 0 - -/** Add `id` field to `lv_obj_t` */ -#define LV_USE_OBJ_ID 0 - -/** Enable support widget names*/ -#define LV_USE_OBJ_NAME 0 - -/** Automatically assign an ID when obj is created */ -#define LV_OBJ_ID_AUTO_ASSIGN LV_USE_OBJ_ID - -/** Use builtin obj ID handler functions: -* - lv_obj_assign_id: Called when a widget is created. Use a separate counter for each widget class as an ID. -* - lv_obj_id_compare: Compare the ID to decide if it matches with a requested value. -* - lv_obj_stringify_id: Return string-ified identifier, e.g. "button3". -* - lv_obj_free_id: Does nothing, as there is no memory allocation for the ID. -* When disabled these functions needs to be implemented by the user.*/ -#define LV_USE_OBJ_ID_BUILTIN 1 - -/** Use obj property set/get API. */ -#define LV_USE_OBJ_PROPERTY 0 - -/** Enable property name support. */ -#define LV_USE_OBJ_PROPERTY_NAME 1 - -/* Use VG-Lite Simulator. - * - Requires: LV_USE_THORVG_INTERNAL or LV_USE_THORVG_EXTERNAL */ -#define LV_USE_VG_LITE_THORVG 0 - -#if LV_USE_VG_LITE_THORVG - /** Enable LVGL's blend mode support */ - #define LV_VG_LITE_THORVG_LVGL_BLEND_SUPPORT 0 - - /** Enable YUV color format support */ - #define LV_VG_LITE_THORVG_YUV_SUPPORT 0 - - /** Enable Linear gradient extension support */ - #define LV_VG_LITE_THORVG_LINEAR_GRADIENT_EXT_SUPPORT 0 - - /** Enable alignment on 16 pixels */ - #define LV_VG_LITE_THORVG_16PIXELS_ALIGN 1 - - /** Buffer address alignment */ - #define LV_VG_LITE_THORVG_BUF_ADDR_ALIGN 64 - - /** Enable multi-thread render */ - #define LV_VG_LITE_THORVG_THREAD_RENDER 0 -#endif - -/* Enable the multi-touch gesture recognition feature */ -/* Gesture recognition requires the use of floats */ -#define LV_USE_GESTURE_RECOGNITION 0 - -/*===================== - * COMPILER SETTINGS - *====================*/ - -/** For big endian systems set to 1 */ -#define LV_BIG_ENDIAN_SYSTEM 0 - -/** Define a custom attribute for `lv_tick_inc` function */ -#define LV_ATTRIBUTE_TICK_INC - -/** Define a custom attribute for `lv_timer_handler` function */ -#define LV_ATTRIBUTE_TIMER_HANDLER - -/** Define a custom attribute for `lv_display_flush_ready` function */ -#define LV_ATTRIBUTE_FLUSH_READY - -/** Align VG_LITE buffers on this number of bytes. - * @note vglite_src_buf_aligned() uses this value to validate alignment of passed buffer pointers. */ -#define LV_ATTRIBUTE_MEM_ALIGN_SIZE 1 - -/** Will be added where memory needs to be aligned (with -Os data might not be aligned to boundary by default). - * E.g. __attribute__((aligned(4)))*/ -#define LV_ATTRIBUTE_MEM_ALIGN - -/** Attribute to mark large constant arrays, for example for font bitmaps */ -#define LV_ATTRIBUTE_LARGE_CONST - -/** Compiler prefix for a large array declaration in RAM */ -#define LV_ATTRIBUTE_LARGE_RAM_ARRAY - -/** Place performance critical functions into a faster memory (e.g RAM) */ -#define LV_ATTRIBUTE_FAST_MEM - -/** Export integer constant to binding. This macro is used with constants in the form of LV_ that - * should also appear on LVGL binding API such as MicroPython. */ -#define LV_EXPORT_CONST_INT(int_value) struct _silence_gcc_warning /**< The default value just prevents GCC warning */ - -/** Prefix all global extern data with this */ -#define LV_ATTRIBUTE_EXTERN_DATA - -/** Use `float` as `lv_value_precise_t` */ -#define LV_USE_FLOAT 0 - -/** Enable matrix support - * - Requires `LV_USE_FLOAT = 1` */ -#define LV_USE_MATRIX 0 - -/** Include `lvgl_private.h` in `lvgl.h` to access internal data and functions by default */ -#define LV_USE_PRIVATE_API 0 - -/*================== - * FONT USAGE - *===================*/ - -/* Montserrat fonts with ASCII range and some symbols using bpp = 4 - * https://fonts.google.com/specimen/Montserrat */ -#define LV_FONT_MONTSERRAT_8 0 -#define LV_FONT_MONTSERRAT_10 0 -#define LV_FONT_MONTSERRAT_12 0 -#define LV_FONT_MONTSERRAT_14 1 -#define LV_FONT_MONTSERRAT_16 0 -#define LV_FONT_MONTSERRAT_18 0 -#define LV_FONT_MONTSERRAT_20 0 -#define LV_FONT_MONTSERRAT_22 0 -#define LV_FONT_MONTSERRAT_24 0 -#define LV_FONT_MONTSERRAT_26 0 -#define LV_FONT_MONTSERRAT_28 0 -#define LV_FONT_MONTSERRAT_30 0 -#define LV_FONT_MONTSERRAT_32 0 -#define LV_FONT_MONTSERRAT_34 0 -#define LV_FONT_MONTSERRAT_36 0 -#define LV_FONT_MONTSERRAT_38 0 -#define LV_FONT_MONTSERRAT_40 0 -#define LV_FONT_MONTSERRAT_42 0 -#define LV_FONT_MONTSERRAT_44 0 -#define LV_FONT_MONTSERRAT_46 0 -#define LV_FONT_MONTSERRAT_48 0 - -/* Demonstrate special features */ -#define LV_FONT_MONTSERRAT_28_COMPRESSED 0 /**< bpp = 3 */ -#define LV_FONT_DEJAVU_16_PERSIAN_HEBREW 0 /**< Hebrew, Arabic, Persian letters and all their forms */ -#define LV_FONT_SIMSUN_14_CJK 0 /**< 1000 most common CJK radicals */ -#define LV_FONT_SIMSUN_16_CJK 0 /**< 1000 most common CJK radicals */ - -/** Pixel perfect monospaced fonts */ -#define LV_FONT_UNSCII_8 0 -#define LV_FONT_UNSCII_16 0 - -/** Optionally declare custom fonts here. - * - * You can use any of these fonts as the default font too and they will be available - * globally. Example: - * - * @code - * #define LV_FONT_CUSTOM_DECLARE LV_FONT_DECLARE(my_font_1) LV_FONT_DECLARE(my_font_2) - * @endcode - */ -#define LV_FONT_CUSTOM_DECLARE - -/** Always set a default font */ -#define LV_FONT_DEFAULT &lv_font_montserrat_14 - -/** Enable handling large font and/or fonts with a lot of characters. - * The limit depends on the font size, font face and bpp. - * A compiler error will be triggered if a font needs it. */ -#define LV_FONT_FMT_TXT_LARGE 0 - -/** Enables/disables support for compressed fonts. */ -#define LV_USE_FONT_COMPRESSED 0 - -/** Enable drawing placeholders when glyph dsc is not found. */ -#define LV_USE_FONT_PLACEHOLDER 1 - -/*================= - * TEXT SETTINGS - *=================*/ - -/** - * Select a character encoding for strings. - * Your IDE or editor should have the same character encoding. - * - LV_TXT_ENC_UTF8 - * - LV_TXT_ENC_ASCII - */ -#define LV_TXT_ENC LV_TXT_ENC_UTF8 - -/** While rendering text strings, break (wrap) text on these chars. */ -#define LV_TXT_BREAK_CHARS " ,.;:-_)]}" - -/** If a word is at least this long, will break wherever "prettiest". - * To disable, set to a value <= 0. */ -#define LV_TXT_LINE_BREAK_LONG_LEN 0 - -/** Minimum number of characters in a long word to put on a line before a break. - * Depends on LV_TXT_LINE_BREAK_LONG_LEN. */ -#define LV_TXT_LINE_BREAK_LONG_PRE_MIN_LEN 3 - -/** Minimum number of characters in a long word to put on a line after a break. - * Depends on LV_TXT_LINE_BREAK_LONG_LEN. */ -#define LV_TXT_LINE_BREAK_LONG_POST_MIN_LEN 3 - -/** Support bidirectional text. Allows mixing Left-to-Right and Right-to-Left text. - * The direction will be processed according to the Unicode Bidirectional Algorithm: - * https://www.w3.org/International/articles/inline-bidi-markup/uba-basics */ -#define LV_USE_BIDI 0 -#if LV_USE_BIDI - /*Set the default direction. Supported values: - *`LV_BASE_DIR_LTR` Left-to-Right - *`LV_BASE_DIR_RTL` Right-to-Left - *`LV_BASE_DIR_AUTO` detect text base direction*/ - #define LV_BIDI_BASE_DIR_DEF LV_BASE_DIR_AUTO -#endif - -/** Enable Arabic/Persian processing - * In these languages characters should be replaced with another form based on their position in the text */ -#define LV_USE_ARABIC_PERSIAN_CHARS 0 - -/*The control character to use for signaling text recoloring*/ -#define LV_TXT_COLOR_CMD "#" - -/*================== - * WIDGETS - *================*/ -/* Documentation for widgets can be found here: https://docs.lvgl.io/master/details/widgets/index.html . */ - -/** 1: Causes these widgets to be given default values at creation time. - * - lv_buttonmatrix_t: Get default maps: {"Btn1", "Btn2", "Btn3", "\n", "Btn4", "Btn5", ""}, else map not set. - * - lv_checkbox_t : String label set to "Check box", else set to empty string. - * - lv_dropdown_t : Options set to "Option 1", "Option 2", "Option 3", else no values are set. - * - lv_roller_t : Options set to "Option 1", "Option 2", "Option 3", "Option 4", "Option 5", else no values are set. - * - lv_label_t : Text set to "Text", else empty string. - * */ -#define LV_WIDGETS_HAS_DEFAULT_VALUE 1 - -#define LV_USE_ANIMIMG 1 - -#define LV_USE_ARC 1 - -#define LV_USE_BAR 1 - -#define LV_USE_BUTTON 1 - -#define LV_USE_BUTTONMATRIX 1 - -#define LV_USE_CALENDAR 1 -#if LV_USE_CALENDAR - #define LV_CALENDAR_WEEK_STARTS_MONDAY 0 - #if LV_CALENDAR_WEEK_STARTS_MONDAY - #define LV_CALENDAR_DEFAULT_DAY_NAMES {"Mo", "Tu", "We", "Th", "Fr", "Sa", "Su"} - #else - #define LV_CALENDAR_DEFAULT_DAY_NAMES {"Su", "Mo", "Tu", "We", "Th", "Fr", "Sa"} - #endif - - #define LV_CALENDAR_DEFAULT_MONTH_NAMES {"January", "February", "March", "April", "May", "June", "July", "August", "September", "October", "November", "December"} - #define LV_USE_CALENDAR_HEADER_ARROW 1 - #define LV_USE_CALENDAR_HEADER_DROPDOWN 1 - #define LV_USE_CALENDAR_CHINESE 0 -#endif /*LV_USE_CALENDAR*/ - -#define LV_USE_CANVAS 1 - -#define LV_USE_CHART 1 - -#define LV_USE_CHECKBOX 1 - -#define LV_USE_DROPDOWN 1 /**< Requires: lv_label */ - -#define LV_USE_IMAGE 1 /**< Requires: lv_label */ - -#define LV_USE_IMAGEBUTTON 1 - -#define LV_USE_KEYBOARD 1 - -#define LV_USE_LABEL 1 -#if LV_USE_LABEL - #define LV_LABEL_TEXT_SELECTION 1 /**< Enable selecting text of the label */ - #define LV_LABEL_LONG_TXT_HINT 1 /**< Store some extra info in labels to speed up drawing of very long text */ - #define LV_LABEL_WAIT_CHAR_COUNT 3 /**< The count of wait chart */ -#endif - -#define LV_USE_LED 1 - -#define LV_USE_LINE 1 - -#define LV_USE_LIST 1 - -#define LV_USE_LOTTIE 0 /**< Requires: lv_canvas, thorvg */ - -#define LV_USE_MENU 1 - -#define LV_USE_MSGBOX 1 - -#define LV_USE_ROLLER 1 /**< Requires: lv_label */ - -#define LV_USE_SCALE 1 - -#define LV_USE_SLIDER 1 /**< Requires: lv_bar */ - -#define LV_USE_SPAN 1 -#if LV_USE_SPAN - /** A line of text can contain this maximum number of span descriptors. */ - #define LV_SPAN_SNIPPET_STACK_SIZE 64 -#endif - -#define LV_USE_SPINBOX 1 - -#define LV_USE_SPINNER 1 - -#define LV_USE_SWITCH 1 - -#define LV_USE_TABLE 1 - -#define LV_USE_TABVIEW 1 - -#define LV_USE_TEXTAREA 1 /**< Requires: lv_label */ -#if LV_USE_TEXTAREA != 0 - #define LV_TEXTAREA_DEF_PWD_SHOW_TIME 1500 /**< [ms] */ -#endif - -#define LV_USE_TILEVIEW 1 - -#define LV_USE_WIN 1 - -/*================== - * THEMES - *==================*/ -/* Documentation for themes can be found here: https://docs.lvgl.io/master/details/common-widget-features/styles/style.html#themes . */ - -/** A simple, impressive and very complete theme */ -#define LV_USE_THEME_DEFAULT 1 -#if LV_USE_THEME_DEFAULT - /** 0: Light mode; 1: Dark mode */ - #define LV_THEME_DEFAULT_DARK 0 - - /** 1: Enable grow on press */ - #define LV_THEME_DEFAULT_GROW 1 - - /** Default transition time in ms. */ - #define LV_THEME_DEFAULT_TRANSITION_TIME 80 -#endif /*LV_USE_THEME_DEFAULT*/ - -/** A very simple theme that is a good starting point for a custom theme */ -#define LV_USE_THEME_SIMPLE 1 - -/** A theme designed for monochrome displays */ -#define LV_USE_THEME_MONO 1 - -/*================== - * LAYOUTS - *==================*/ -/* Documentation for layouts can be found here: https://docs.lvgl.io/master/details/common-widget-features/layouts/index.html . */ - -/** A layout similar to Flexbox in CSS. */ -#define LV_USE_FLEX 1 - -/** A layout similar to Grid in CSS. */ -#define LV_USE_GRID 1 - -/*==================== - * 3RD PARTS LIBRARIES - *====================*/ -/* Documentation for libraries can be found here: https://docs.lvgl.io/master/details/libs/index.html . */ - -/* File system interfaces for common APIs */ - -/** Setting a default driver letter allows skipping the driver prefix in filepaths. - * Documentation about how to use the below driver-identifier letters can be found at - * https://docs.lvgl.io/master/details/main-modules/fs.html#lv-fs-identifier-letters . */ -#define LV_FS_DEFAULT_DRIVER_LETTER '\0' - -/** API for fopen, fread, etc. */ -#define LV_USE_FS_STDIO 0 -#if LV_USE_FS_STDIO - #define LV_FS_STDIO_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ - #define LV_FS_STDIO_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ - #define LV_FS_STDIO_CACHE_SIZE 0 /**< >0 to cache this number of bytes in lv_fs_read() */ -#endif - -/** API for open, read, etc. */ -#define LV_USE_FS_POSIX 0 -#if LV_USE_FS_POSIX - #define LV_FS_POSIX_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ - #define LV_FS_POSIX_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ - #define LV_FS_POSIX_CACHE_SIZE 0 /**< >0 to cache this number of bytes in lv_fs_read() */ -#endif - -/** API for CreateFile, ReadFile, etc. */ -#define LV_USE_FS_WIN32 0 -#if LV_USE_FS_WIN32 - #define LV_FS_WIN32_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ - #define LV_FS_WIN32_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ - #define LV_FS_WIN32_CACHE_SIZE 0 /**< >0 to cache this number of bytes in lv_fs_read() */ -#endif - -/** API for FATFS (needs to be added separately). Uses f_open, f_read, etc. */ -#define LV_USE_FS_FATFS 0 -#if LV_USE_FS_FATFS - #define LV_FS_FATFS_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ - #define LV_FS_FATFS_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ - #define LV_FS_FATFS_CACHE_SIZE 0 /**< >0 to cache this number of bytes in lv_fs_read() */ -#endif - -/** API for memory-mapped file access. */ -#define LV_USE_FS_MEMFS 0 -#if LV_USE_FS_MEMFS - #define LV_FS_MEMFS_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ -#endif - -/** API for LittleFs. */ -#define LV_USE_FS_LITTLEFS 0 -#if LV_USE_FS_LITTLEFS - #define LV_FS_LITTLEFS_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ - #define LV_FS_LITTLEFS_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ -#endif - -/** API for Arduino LittleFs. */ -#define LV_USE_FS_ARDUINO_ESP_LITTLEFS 0 -#if LV_USE_FS_ARDUINO_ESP_LITTLEFS - #define LV_FS_ARDUINO_ESP_LITTLEFS_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ - #define LV_FS_ARDUINO_ESP_LITTLEFS_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ -#endif - -/** API for Arduino Sd. */ -#define LV_USE_FS_ARDUINO_SD 0 -#if LV_USE_FS_ARDUINO_SD - #define LV_FS_ARDUINO_SD_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ - #define LV_FS_ARDUINO_SD_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ -#endif - -/** API for UEFI */ -#define LV_USE_FS_UEFI 0 -#if LV_USE_FS_UEFI - #define LV_FS_UEFI_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ -#endif - -/** LODEPNG decoder library */ -#define LV_USE_LODEPNG 0 - -/** PNG decoder(libpng) library */ -#define LV_USE_LIBPNG 0 - -/** BMP decoder library */ -#define LV_USE_BMP 0 - -/** JPG + split JPG decoder library. - * Split JPG is a custom format optimized for embedded systems. */ -#define LV_USE_TJPGD 0 - -/** libjpeg-turbo decoder library. - * - Supports complete JPEG specifications and high-performance JPEG decoding. */ -#define LV_USE_LIBJPEG_TURBO 0 - -/** GIF decoder library */ -#define LV_USE_GIF 0 -#if LV_USE_GIF - /** GIF decoder accelerate */ - #define LV_GIF_CACHE_DECODE_DATA 0 -#endif - - -/** Decode bin images to RAM */ -#define LV_BIN_DECODER_RAM_LOAD 0 - -/** RLE decompress library */ -#define LV_USE_RLE 0 - -/** QR code library */ -#define LV_USE_QRCODE 0 - -/** Barcode code library */ -#define LV_USE_BARCODE 0 - -/** FreeType library */ -#define LV_USE_FREETYPE 0 -#if LV_USE_FREETYPE - /** Let FreeType use LVGL memory and file porting */ - #define LV_FREETYPE_USE_LVGL_PORT 0 - - /** Cache count of glyphs in FreeType, i.e. number of glyphs that can be cached. - * The higher the value, the more memory will be used. */ - #define LV_FREETYPE_CACHE_FT_GLYPH_CNT 256 -#endif - -/** Built-in TTF decoder */ -#define LV_USE_TINY_TTF 0 -#if LV_USE_TINY_TTF - /* Enable loading TTF data from files */ - #define LV_TINY_TTF_FILE_SUPPORT 0 - #define LV_TINY_TTF_CACHE_GLYPH_CNT 256 -#endif - -/** Rlottie library */ -#define LV_USE_RLOTTIE 0 - -/** Enable Vector Graphic APIs - * - Requires `LV_USE_MATRIX = 1` */ -#define LV_USE_VECTOR_GRAPHIC 0 - -/** Enable ThorVG (vector graphics library) from the src/libs folder */ -#define LV_USE_THORVG_INTERNAL 0 - -/** Enable ThorVG by assuming that its installed and linked to the project */ -#define LV_USE_THORVG_EXTERNAL 0 - -/** Use lvgl built-in LZ4 lib */ -#define LV_USE_LZ4_INTERNAL 0 - -/** Use external LZ4 library */ -#define LV_USE_LZ4_EXTERNAL 0 - -/*SVG library - * - Requires `LV_USE_VECTOR_GRAPHIC = 1` */ -#define LV_USE_SVG 0 -#define LV_USE_SVG_ANIMATION 0 -#define LV_USE_SVG_DEBUG 0 - -/** FFmpeg library for image decoding and playing videos. - * Supports all major image formats so do not enable other image decoder with it. */ -#define LV_USE_FFMPEG 0 -#if LV_USE_FFMPEG - /** Dump input information to stderr */ - #define LV_FFMPEG_DUMP_FORMAT 0 - /** Use lvgl file path in FFmpeg Player widget - * You won't be able to open URLs after enabling this feature. - * Note that FFmpeg image decoder will always use lvgl file system. */ - #define LV_FFMPEG_PLAYER_USE_LV_FS 0 -#endif - -/*================== - * OTHERS - *==================*/ -/* Documentation for several of the below items can be found here: https://docs.lvgl.io/master/details/auxiliary-modules/index.html . */ - -/** 1: Enable API to take snapshot for object */ -#define LV_USE_SNAPSHOT 0 - -/** 1: Enable system monitor component */ -#define LV_USE_SYSMON 0 -#if LV_USE_SYSMON - /** Get the idle percentage. E.g. uint32_t my_get_idle(void); */ - #define LV_SYSMON_GET_IDLE lv_os_get_idle_percent - - /** 1: Show CPU usage and FPS count. - * - Requires `LV_USE_SYSMON = 1` */ - #define LV_USE_PERF_MONITOR 0 - #if LV_USE_PERF_MONITOR - #define LV_USE_PERF_MONITOR_POS LV_ALIGN_BOTTOM_RIGHT - - /** 0: Displays performance data on the screen; 1: Prints performance data using log. */ - #define LV_USE_PERF_MONITOR_LOG_MODE 0 - #endif - - /** 1: Show used memory and memory fragmentation. - * - Requires `LV_USE_STDLIB_MALLOC = LV_STDLIB_BUILTIN` - * - Requires `LV_USE_SYSMON = 1`*/ - #define LV_USE_MEM_MONITOR 0 - #if LV_USE_MEM_MONITOR - #define LV_USE_MEM_MONITOR_POS LV_ALIGN_BOTTOM_LEFT - #endif -#endif /*LV_USE_SYSMON*/ - -/** 1: Enable runtime performance profiler */ -#define LV_USE_PROFILER 0 -#if LV_USE_PROFILER - /** 1: Enable the built-in profiler */ - #define LV_USE_PROFILER_BUILTIN 1 - #if LV_USE_PROFILER_BUILTIN - /** Default profiler trace buffer size */ - #define LV_PROFILER_BUILTIN_BUF_SIZE (16 * 1024) /**< [bytes] */ - #endif - - /** Header to include for profiler */ - #define LV_PROFILER_INCLUDE "lvgl/src/misc/lv_profiler_builtin.h" - - /** Profiler start point function */ - #define LV_PROFILER_BEGIN LV_PROFILER_BUILTIN_BEGIN - - /** Profiler end point function */ - #define LV_PROFILER_END LV_PROFILER_BUILTIN_END - - /** Profiler start point function with custom tag */ - #define LV_PROFILER_BEGIN_TAG LV_PROFILER_BUILTIN_BEGIN_TAG - - /** Profiler end point function with custom tag */ - #define LV_PROFILER_END_TAG LV_PROFILER_BUILTIN_END_TAG - - /*Enable layout profiler*/ - #define LV_PROFILER_LAYOUT 1 - - /*Enable disp refr profiler*/ - #define LV_PROFILER_REFR 1 - - /*Enable draw profiler*/ - #define LV_PROFILER_DRAW 1 - - /*Enable indev profiler*/ - #define LV_PROFILER_INDEV 1 - - /*Enable decoder profiler*/ - #define LV_PROFILER_DECODER 1 - - /*Enable font profiler*/ - #define LV_PROFILER_FONT 1 - - /*Enable fs profiler*/ - #define LV_PROFILER_FS 1 - - /*Enable style profiler*/ - #define LV_PROFILER_STYLE 0 - - /*Enable timer profiler*/ - #define LV_PROFILER_TIMER 1 - - /*Enable cache profiler*/ - #define LV_PROFILER_CACHE 1 - - /*Enable event profiler*/ - #define LV_PROFILER_EVENT 1 -#endif - -/** 1: Enable Monkey test */ -#define LV_USE_MONKEY 0 - -/** 1: Enable grid navigation */ -#define LV_USE_GRIDNAV 0 - -/** 1: Enable `lv_obj` fragment logic */ -#define LV_USE_FRAGMENT 0 - -/** 1: Support using images as font in label or span widgets */ -#define LV_USE_IMGFONT 0 - -/** 1: Enable an observer pattern implementation */ -#define LV_USE_OBSERVER 1 - -/** 1: Enable Pinyin input method - * - Requires: lv_keyboard */ -#define LV_USE_IME_PINYIN 0 -#if LV_USE_IME_PINYIN - /** 1: Use default thesaurus. - * @note If you do not use the default thesaurus, be sure to use `lv_ime_pinyin` after setting the thesaurus. */ - #define LV_IME_PINYIN_USE_DEFAULT_DICT 1 - /** Set maximum number of candidate panels that can be displayed. - * @note This needs to be adjusted according to size of screen. */ - #define LV_IME_PINYIN_CAND_TEXT_NUM 6 - - /** Use 9-key input (k9). */ - #define LV_IME_PINYIN_USE_K9_MODE 1 - #if LV_IME_PINYIN_USE_K9_MODE == 1 - #define LV_IME_PINYIN_K9_CAND_TEXT_NUM 3 - #endif /*LV_IME_PINYIN_USE_K9_MODE*/ -#endif - -/** 1: Enable file explorer. - * - Requires: lv_table */ -#define LV_USE_FILE_EXPLORER 0 -#if LV_USE_FILE_EXPLORER - /** Maximum length of path */ - #define LV_FILE_EXPLORER_PATH_MAX_LEN (128) - /** Quick access bar, 1:use, 0:do not use. - * - Requires: lv_list */ - #define LV_FILE_EXPLORER_QUICK_ACCESS 1 -#endif - -/** 1: Enable freetype font manager - * - Requires: LV_USE_FREETYPE */ -#define LV_USE_FONT_MANAGER 0 -#if LV_USE_FONT_MANAGER - -/**Font manager name max length*/ -#define LV_FONT_MANAGER_NAME_MAX_LEN 32 - -#endif - -/** Enable emulated input devices, time emulation, and screenshot compares. */ -#define LV_USE_TEST 0 -#if LV_USE_TEST - -/** Enable `lv_test_screenshot_compare`. - * Requires libpng and a few MB of extra RAM. */ -#define LV_USE_TEST_SCREENSHOT_COMPARE 0 -#endif /*LV_USE_TEST*/ - -/** Enable loading XML UIs runtime */ -#define LV_USE_XML 0 - -/*1: Enable color filter style*/ -#define LV_USE_COLOR_FILTER 0 -/*================== - * DEVICES - *==================*/ - -/** Use SDL to open window on PC and handle mouse and keyboard. */ -#define LV_USE_SDL 0 -#if LV_USE_SDL - #define LV_SDL_INCLUDE_PATH - #define LV_SDL_RENDER_MODE LV_DISPLAY_RENDER_MODE_DIRECT /**< LV_DISPLAY_RENDER_MODE_DIRECT is recommended for best performance */ - #define LV_SDL_BUF_COUNT 1 /**< 1 or 2 */ - #define LV_SDL_ACCELERATED 1 /**< 1: Use hardware acceleration*/ - #define LV_SDL_FULLSCREEN 0 /**< 1: Make the window full screen by default */ - #define LV_SDL_DIRECT_EXIT 1 /**< 1: Exit the application when all SDL windows are closed */ - #define LV_SDL_MOUSEWHEEL_MODE LV_SDL_MOUSEWHEEL_MODE_ENCODER /*LV_SDL_MOUSEWHEEL_MODE_ENCODER/CROWN*/ -#endif - -/** Use X11 to open window on Linux desktop and handle mouse and keyboard */ -#define LV_USE_X11 0 -#if LV_USE_X11 - #define LV_X11_DIRECT_EXIT 1 /**< Exit application when all X11 windows have been closed */ - #define LV_X11_DOUBLE_BUFFER 1 /**< Use double buffers for rendering */ - /* Select only 1 of the following render modes (LV_X11_RENDER_MODE_PARTIAL preferred!). */ - #define LV_X11_RENDER_MODE_PARTIAL 1 /**< Partial render mode (preferred) */ - #define LV_X11_RENDER_MODE_DIRECT 0 /**< Direct render mode */ - #define LV_X11_RENDER_MODE_FULL 0 /**< Full render mode */ -#endif - -/** Use Wayland to open a window and handle input on Linux or BSD desktops */ -#define LV_USE_WAYLAND 0 -#if LV_USE_WAYLAND - #define LV_WAYLAND_WINDOW_DECORATIONS 0 /**< Draw client side window decorations only necessary on Mutter/GNOME */ - #define LV_WAYLAND_WL_SHELL 0 /**< Use the legacy wl_shell protocol instead of the default XDG shell */ -#endif - -/** Driver for /dev/fb */ -#define LV_USE_LINUX_FBDEV 0 -#if LV_USE_LINUX_FBDEV - #define LV_LINUX_FBDEV_BSD 0 - #define LV_LINUX_FBDEV_RENDER_MODE LV_DISPLAY_RENDER_MODE_PARTIAL - #define LV_LINUX_FBDEV_BUFFER_COUNT 0 - #define LV_LINUX_FBDEV_BUFFER_SIZE 60 -#endif - -/** Use Nuttx to open window and handle touchscreen */ -#define LV_USE_NUTTX 0 - -#if LV_USE_NUTTX - #define LV_USE_NUTTX_INDEPENDENT_IMAGE_HEAP 0 - - /** Use independent image heap for default draw buffer */ - #define LV_NUTTX_DEFAULT_DRAW_BUF_USE_INDEPENDENT_IMAGE_HEAP 0 - - #define LV_USE_NUTTX_LIBUV 0 - - /** Use Nuttx custom init API to open window and handle touchscreen */ - #define LV_USE_NUTTX_CUSTOM_INIT 0 - - /** Driver for /dev/lcd */ - #define LV_USE_NUTTX_LCD 0 - #if LV_USE_NUTTX_LCD - #define LV_NUTTX_LCD_BUFFER_COUNT 0 - #define LV_NUTTX_LCD_BUFFER_SIZE 60 - #endif - - /** Driver for /dev/input */ - #define LV_USE_NUTTX_TOUCHSCREEN 0 - - /*Touchscreen cursor size in pixels(<=0: disable cursor)*/ - #define LV_NUTTX_TOUCHSCREEN_CURSOR_SIZE 0 -#endif - -/** Driver for /dev/dri/card */ -#define LV_USE_LINUX_DRM 0 - -#if LV_USE_LINUX_DRM - - /* Use the MESA GBM library to allocate DMA buffers that can be - * shared across sub-systems and libraries using the Linux DMA-BUF API. - * The GBM library aims to provide a platform independent memory management system - * it supports the major GPU vendors - This option requires linking with libgbm */ - #define LV_LINUX_DRM_GBM_BUFFERS 0 -#endif - -/** Interface for TFT_eSPI */ -#define LV_USE_TFT_ESPI 0 - -/** Driver for evdev input devices */ -#define LV_USE_EVDEV 0 - -/** Driver for libinput input devices */ -#define LV_USE_LIBINPUT 0 - -#if LV_USE_LIBINPUT - #define LV_LIBINPUT_BSD 0 - - /** Full keyboard support */ - #define LV_LIBINPUT_XKB 0 - #if LV_LIBINPUT_XKB - /** "setxkbmap -query" can help find the right values for your keyboard */ - #define LV_LIBINPUT_XKB_KEY_MAP { .rules = NULL, .model = "pc101", .layout = "us", .variant = NULL, .options = NULL } - #endif -#endif - -/* Drivers for LCD devices connected via SPI/parallel port */ -#define LV_USE_ST7735 0 -#define LV_USE_ST7789 0 -#define LV_USE_ST7796 0 -#define LV_USE_ILI9341 0 - -#if (LV_USE_ST7735 | LV_USE_ST7789 | LV_USE_ST7796 | LV_USE_ILI9341) - #define LV_USE_GENERIC_MIPI 1 -#else - #define LV_USE_GENERIC_MIPI 0 -#endif - -/** Driver for Renesas GLCD */ -#define LV_USE_RENESAS_GLCDC 0 - -/** Driver for ST LTDC */ -#define LV_USE_ST_LTDC 0 -#if LV_USE_ST_LTDC - /* Only used for partial. */ - #define LV_ST_LTDC_USE_DMA2D_FLUSH 0 -#endif - -/** LVGL Windows backend */ -#define LV_USE_WINDOWS 0 - -/** LVGL UEFI backend */ -#define LV_USE_UEFI 0 -#if LV_USE_UEFI - #define LV_USE_UEFI_INCLUDE "myefi.h" /**< Header that hides the actual framework (EDK2, gnu-efi, ...) */ - #define LV_UEFI_USE_MEMORY_SERVICES 0 /**< Use the memory functions from the boot services table */ -#endif - -/** Use OpenGL to open window on PC and handle mouse and keyboard */ -#define LV_USE_OPENGLES 0 -#if LV_USE_OPENGLES - #define LV_USE_OPENGLES_DEBUG 1 /**< Enable or disable debug for opengles */ -#endif - -/** QNX Screen display and input drivers */ -#define LV_USE_QNX 0 -#if LV_USE_QNX - #define LV_QNX_BUF_COUNT 1 /**< 1 or 2 */ -#endif - -#endif /*LV_CONF_H*/ diff --git a/stm32-lvgl/Sources/HostSDLApp/Main.swift b/stm32-lvgl/Sources/HostSDLApp/Main.swift deleted file mode 100644 index 58f2a203..00000000 --- a/stm32-lvgl/Sources/HostSDLApp/Main.swift +++ /dev/null @@ -1,127 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import CLVGL -import Foundation -import SDL - -let drawSize: (width: Int32, height: Int32) = (width: 480, height: 272) -let windowScale: Int32 = 2 - -var clickCount = 0 -var button: OpaquePointer! = nil -var buttonLabel: OpaquePointer! = nil -var uptimeInMs: Int = 0 - -var texture: OpaquePointer! = nil -var mouseEvent = SDL_Event() - -@main -struct Main { - static func main() { - lv_init() - lv_log_register_print_cb({ level, buf in print(String(cString: buf!), terminator: "") }) - lv_tick_set_cb({ UInt32(uptimeInMs) }) - - let bufSize: UInt32 = UInt32(drawSize.width * drawSize.height * 4) - let buf1 = UnsafeMutableRawPointer.allocate(byteCount: Int(bufSize), alignment: 16) - let buf2 = UnsafeMutableRawPointer.allocate(byteCount: Int(bufSize), alignment: 16) - - let disp = lv_display_create(Int32(drawSize.width), Int32(drawSize.height))! - lv_display_set_color_format(disp, LV_COLOR_FORMAT_ARGB8888) - lv_display_set_buffers(disp, buf1, buf2, bufSize, LV_DISPLAY_RENDER_MODE_FULL) - lv_display_set_flush_cb( - disp, - { disp, _, bufferToShow in - _ = SDL_UpdateTexture(texture, nil, bufferToShow, Int32(drawSize.width * 4)) - lv_display_flush_ready(disp) - }) - - let touch = lv_indev_create() - lv_indev_set_type(touch, LV_INDEV_TYPE_POINTER) - lv_indev_set_read_cb( - touch, - { indev, data in - if mouseEvent.type == SDL_MOUSEBUTTONDOWN.rawValue { - data!.pointee.point.x = Int32(mouseEvent.button.x) / windowScale - data!.pointee.point.y = Int32(mouseEvent.button.y) / windowScale - data!.pointee.state = LV_INDEV_STATE_PRESSED - } else if mouseEvent.type == SDL_MOUSEMOTION.rawValue && mouseEvent.motion.state & 0x1 != 0 { - data!.pointee.point.x = Int32(mouseEvent.motion.x) / windowScale - data!.pointee.point.y = Int32(mouseEvent.motion.y) / windowScale - data!.pointee.state = LV_INDEV_STATE_PRESSED - } else { - data!.pointee.state = LV_INDEV_STATE_RELEASED - } - }) - - UIAppLogic.createUI() - - // Initialize SDL video systems - guard SDL_Init(SDL_INIT_VIDEO) == 0 else { - fatalError("SDL could not initialize! SDL_Error: \(String(cString: SDL_GetError()))") - } - - // Create a window at the center of the screen - let window = SDL_CreateWindow( - "SDL Window", Int32(SDL_WINDOWPOS_CENTERED_MASK), - Int32(SDL_WINDOWPOS_CENTERED_MASK), drawSize.width * windowScale, drawSize.height * windowScale, - SDL_WINDOW_SHOWN.rawValue) - - // Create renderer - guard let renderer = SDL_CreateRenderer(window, -1, SDL_RENDERER_ACCELERATED.rawValue) else { - fatalError("Renderer could not be created! SDL_Error: \(String(cString: SDL_GetError()))") - } - - // Create texture - texture = SDL_CreateTexture( - renderer, SDL_PIXELFORMAT_ARGB8888.rawValue, - Int32(SDL_TEXTUREACCESS_STREAMING.rawValue), drawSize.width, drawSize.height) - guard texture != nil else { - fatalError("Texture could not be created! SDL_Error: \(String(cString: SDL_GetError()))") - } - - var event = SDL_Event() - var frameCounter = 0 - let startTime = Date() - mainLoop: while true { - uptimeInMs = Int(Date().timeIntervalSince(startTime) * 1000) - let delay = lv_timer_handler() - - // Clear renderer, copy texture to renderer, and present - SDL_RenderClear(renderer) - SDL_RenderCopy(renderer, texture, nil, nil) - SDL_RenderPresent(renderer) - - while SDL_PollEvent(&event) > 0 { - if event.type == SDL_MOUSEBUTTONDOWN.rawValue { - mouseEvent = event - } - if event.type == SDL_MOUSEBUTTONUP.rawValue { - mouseEvent = event - } - if event.type == SDL_MOUSEMOTION.rawValue { - mouseEvent = event - } - if event.type == SDL_QUIT.rawValue { - break mainLoop - } - } - - SDL_Delay(delay) - - UIAppLogic.updateFrame() - } - - SDL_DestroyWindow(window) - SDL_Quit() - } -} diff --git a/stm32-lvgl/Sources/HostSDLApp/UIAppLogic.swift b/stm32-lvgl/Sources/HostSDLApp/UIAppLogic.swift deleted file mode 120000 index a5ab2212..00000000 --- a/stm32-lvgl/Sources/HostSDLApp/UIAppLogic.swift +++ /dev/null @@ -1 +0,0 @@ -../Application/UIAppLogic.swift \ No newline at end of file diff --git a/stm32-lvgl/Sources/Registers/DBGMCU.swift b/stm32-lvgl/Sources/Registers/DBGMCU.swift deleted file mode 100644 index c1a7a0bf..00000000 --- a/stm32-lvgl/Sources/Registers/DBGMCU.swift +++ /dev/null @@ -1,153 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Debug support -@RegisterBlock -public struct DBGMCU { - /// IDCODE - @RegisterBlock(offset: 0x0) - public var idcode: Register - - /// Control Register - @RegisterBlock(offset: 0x4) - public var cr: Register - - /// Debug MCU APB1 Freeze registe - @RegisterBlock(offset: 0x8) - public var apb1_fz: Register - - /// Debug MCU APB2 Freeze registe - @RegisterBlock(offset: 0xc) - public var apb2_fz: Register -} - -extension DBGMCU { - /// IDCODE - @Register(bitWidth: 32) - public struct IDCODE { - /// DEV_ID - @ReadOnly(bits: 0..<12) - public var dev_id: DEV_ID - - /// REV_ID - @ReadOnly(bits: 16..<32) - public var rev_id: REV_ID - } - - /// Control Register - @Register(bitWidth: 32) - public struct CR { - /// DBG_SLEEP - @ReadWrite(bits: 0..<1) - public var dbg_sleep: DBG_SLEEP - - /// DBG_STOP - @ReadWrite(bits: 1..<2) - public var dbg_stop: DBG_STOP - - /// DBG_STANDBY - @ReadWrite(bits: 2..<3) - public var dbg_standby: DBG_STANDBY - - /// TRACE_IOEN - @ReadWrite(bits: 5..<6) - public var trace_ioen: TRACE_IOEN - - /// TRACE_MODE - @ReadWrite(bits: 6..<8) - public var trace_mode: TRACE_MODE - } - - /// Debug MCU APB1 Freeze registe - @Register(bitWidth: 32) - public struct APB1_FZ { - /// DBG_TIM2_STOP - @ReadWrite(bits: 0..<1) - public var dbg_tim2_stop: DBG_TIM2_STOP - - /// DBG_TIM3 _STOP - @ReadWrite(bits: 1..<2) - public var dbg_tim3_stop: DBG_TIM3_STOP - - /// DBG_TIM4_STOP - @ReadWrite(bits: 2..<3) - public var dbg_tim4_stop: DBG_TIM4_STOP - - /// DBG_TIM5_STOP - @ReadWrite(bits: 3..<4) - public var dbg_tim5_stop: DBG_TIM5_STOP - - /// DBG_TIM6_STOP - @ReadWrite(bits: 4..<5) - public var dbg_tim6_stop: DBG_TIM6_STOP - - /// DBG_TIM7_STOP - @ReadWrite(bits: 5..<6) - public var dbg_tim7_stop: DBG_TIM7_STOP - - /// DBG_TIM12_STOP - @ReadWrite(bits: 6..<7) - public var dbg_tim12_stop: DBG_TIM12_STOP - - /// DBG_TIM13_STOP - @ReadWrite(bits: 7..<8) - public var dbg_tim13_stop: DBG_TIM13_STOP - - /// DBG_TIM14_STOP - @ReadWrite(bits: 8..<9) - public var dbg_tim14_stop: DBG_TIM14_STOP - - /// DBG_WWDG_STOP - @ReadWrite(bits: 11..<12) - public var dbg_wwdg_stop: DBG_WWDG_STOP - - /// DBG_IWDEG_STOP - @ReadWrite(bits: 12..<13) - public var dbg_iwdg_stop: DBG_IWDG_STOP - - /// DBG_J2C1_SMBUS_TIMEOUT - @ReadWrite(bits: 21..<22) - public var dbg_j2c1_smbus_timeout: DBG_J2C1_SMBUS_TIMEOUT - - /// DBG_J2C2_SMBUS_TIMEOUT - @ReadWrite(bits: 22..<23) - public var dbg_j2c2_smbus_timeout: DBG_J2C2_SMBUS_TIMEOUT - - /// DBG_J2C3SMBUS_TIMEOUT - @ReadWrite(bits: 23..<24) - public var dbg_j2c3smbus_timeout: DBG_J2C3SMBUS_TIMEOUT - - /// DBG_CAN1_STOP - @ReadWrite(bits: 25..<26) - public var dbg_can1_stop: DBG_CAN1_STOP - - /// DBG_CAN2_STOP - @ReadWrite(bits: 26..<27) - public var dbg_can2_stop: DBG_CAN2_STOP - } - - /// Debug MCU APB2 Freeze registe - @Register(bitWidth: 32) - public struct APB2_FZ { - /// TIM1 counter stopped when core is halted - @ReadWrite(bits: 0..<1) - public var dbg_tim1_stop: DBG_TIM1_STOP - - /// TIM8 counter stopped when core is halted - @ReadWrite(bits: 1..<2) - public var dbg_tim8_stop: DBG_TIM8_STOP - - /// TIM9 counter stopped when core is halted - @ReadWrite(bits: 16..<17) - public var dbg_tim9_stop: DBG_TIM9_STOP - - /// TIM10 counter stopped when core is halted - @ReadWrite(bits: 17..<18) - public var dbg_tim10_stop: DBG_TIM10_STOP - - /// TIM11 counter stopped when core is halted - @ReadWrite(bits: 18..<19) - public var dbg_tim11_stop: DBG_TIM11_STOP - } -} diff --git a/stm32-lvgl/Sources/Registers/Device.swift b/stm32-lvgl/Sources/Registers/Device.swift deleted file mode 100644 index f62c96b4..00000000 --- a/stm32-lvgl/Sources/Registers/Device.swift +++ /dev/null @@ -1,81 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Debug support -public let dbgmcu = DBGMCU(unsafeAddress: 0xe0042000) - -/// FLASH -public let flash = FLASH(unsafeAddress: 0x40023c00) - -/// Flexible memory controller -public let fmc = FMC(unsafeAddress: 0xa0000000) - -/// General-purpose I/Os -public let gpioa = GPIOA(unsafeAddress: 0x40020000) - -/// General-purpose I/Os -public let gpiob = GPIOB(unsafeAddress: 0x40020400) - -/// General-purpose I/Os -public let gpioc = GPIOC(unsafeAddress: 0x40020800) - -/// General-purpose I/Os -public let gpiod = GPIOD(unsafeAddress: 0x40020c00) - -/// General-purpose I/Os -public let gpioe = GPIOE(unsafeAddress: 0x40021000) - -/// General-purpose I/Os -public let gpiof = GPIOF(unsafeAddress: 0x40021400) - -/// General-purpose I/Os -public let gpiog = GPIOG(unsafeAddress: 0x40021800) - -/// General-purpose I/Os -public let gpioh = GPIOH(unsafeAddress: 0x40021c00) - -/// General-purpose I/Os -public let gpioi = GPIOI(unsafeAddress: 0x40022000) - -/// General-purpose I/Os -public let gpioj = GPIOJ(unsafeAddress: 0x40022400) - -/// General-purpose I/Os -public let gpiok = GPIOK(unsafeAddress: 0x40022800) - -/// Inter-integrated circuit -public let i2c1 = I2C1(unsafeAddress: 0x40005400) - -/// Inter-integrated circuit -public let i2c2 = I2C2(unsafeAddress: 0x40005800) - -/// Inter-integrated circuit -public let i2c3 = I2C3(unsafeAddress: 0x40005c00) - -/// Inter-integrated circuit -public let i2c4 = I2C4(unsafeAddress: 0x40006000) - -/// LCD-TFT Controller -public let ltdc = LTDC(unsafeAddress: 0x40016800) - -/// Nested Vectored Interrupt Controller -public let nvic = NVIC(unsafeAddress: 0xe000e100) - -/// Power control -public let pwr = PWR(unsafeAddress: 0x40007000) - -/// Reset and clock control -public let rcc = RCC(unsafeAddress: 0x40023800) - -/// System control block -public let scb = SCB(unsafeAddress: 0xe000ed00) - -/// SysTick timer -public let stk = STK(unsafeAddress: 0xe000e010) - -/// System configuration controller -public let syscfg = SYSCFG(unsafeAddress: 0x40013800) - -/// Universal synchronous asynchronous receiver transmitter -public let usart1 = USART1(unsafeAddress: 0x40011000) diff --git a/stm32-lvgl/Sources/Registers/FLASH.swift b/stm32-lvgl/Sources/Registers/FLASH.swift deleted file mode 100644 index bfceb4f2..00000000 --- a/stm32-lvgl/Sources/Registers/FLASH.swift +++ /dev/null @@ -1,469 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// FLASH -@RegisterBlock -public struct FLASH { - /// Flash access control register - @RegisterBlock(offset: 0x0) - public var acr: Register - - /// Flash key register - @RegisterBlock(offset: 0x4) - public var keyr: Register - - /// Flash option key register - @RegisterBlock(offset: 0x8) - public var optkeyr: Register - - /// Status register - @RegisterBlock(offset: 0xc) - public var sr: Register - - /// Control register - @RegisterBlock(offset: 0x10) - public var cr: Register - - /// Flash option control register - @RegisterBlock(offset: 0x14) - public var optcr: Register - - /// Flash option control register 1 - @RegisterBlock(offset: 0x18) - public var optcr1: Register -} - -extension FLASH { - /// Flash access control register - @Register(bitWidth: 32) - public struct ACR { - /// Latency - @ReadWrite(bits: 0..<4, as: LATENCYValues.self) - public var latency: LATENCY - - /// Prefetch enable - @ReadWrite(bits: 8..<9, as: PRFTENValues.self) - public var prften: PRFTEN - - /// ART Accelerator Enable - @ReadWrite(bits: 9..<10, as: ARTENValues.self) - public var arten: ARTEN - - /// ART Accelerator reset - @ReadWrite(bits: 11..<12, as: ARTRSTValues.self) - public var artrst: ARTRST - } - - /// Flash key register - @Register(bitWidth: 32) - public struct KEYR { - /// FPEC key - @WriteOnly(bits: 0..<32) - public var key: KEY - } - - /// Flash option key register - @Register(bitWidth: 32) - public struct OPTKEYR { - /// Option byte key - @WriteOnly(bits: 0..<32) - public var optkeyr_field: OPTKEYR_FIELD - } - - /// Status register - @Register(bitWidth: 32) - public struct SR { - /// End of operation - @ReadWrite(bits: 0..<1) - public var eop: EOP - - /// Operation error - @ReadWrite(bits: 1..<2) - public var operr: OPERR - - /// Write protection error - @ReadWrite(bits: 4..<5) - public var wrperr: WRPERR - - /// Programming alignment error - @ReadWrite(bits: 5..<6) - public var pgaerr: PGAERR - - /// Programming parallelism error - @ReadWrite(bits: 6..<7) - public var pgperr: PGPERR - - /// Programming sequence error - @ReadWrite(bits: 7..<8) - public var erserr: ERSERR - - /// Busy - @ReadOnly(bits: 16..<17) - public var bsy: BSY - } - - /// Control register - @Register(bitWidth: 32) - public struct CR { - /// Programming - @ReadWrite(bits: 0..<1, as: PGValues.self) - public var pg: PG - - /// Sector Erase - @ReadWrite(bits: 1..<2, as: SERValues.self) - public var ser: SER - - /// Mass Erase of sectors 0 to 11 - @ReadWrite(bits: 2..<3, as: MERValues.self) - public var mer: MER - - /// Sector number - @ReadWrite(bits: 3..<7) - public var snb: SNB - - /// Program size - @ReadWrite(bits: 8..<10, as: PSIZEValues.self) - public var psize: PSIZE - - /// Start - @ReadWrite(bits: 16..<17, as: STRTValues.self) - public var strt: STRT - - /// End of operation interrupt enable - @ReadWrite(bits: 24..<25, as: EOPIEValues.self) - public var eopie: EOPIE - - /// Error interrupt enable - @ReadWrite(bits: 25..<26, as: ERRIEValues.self) - public var errie: ERRIE - - /// Lock - @ReadWrite(bits: 31..<32, as: LOCKValues.self) - public var lock: LOCK - } - - /// Flash option control register - @Register(bitWidth: 32) - public struct OPTCR { - /// Option lock - @ReadWrite(bits: 0..<1) - public var optlock: OPTLOCK - - /// Option start - @ReadWrite(bits: 1..<2) - public var optstrt: OPTSTRT - - /// BOR reset Level - @ReadWrite(bits: 2..<4) - public var bor_lev: BOR_LEV - - /// User option bytes - @ReadWrite(bits: 4..<5) - public var wwdg_sw: WWDG_SW - - /// User option bytes - @ReadWrite(bits: 5..<6) - public var iwdg_sw: IWDG_SW - - /// User option bytes - @ReadWrite(bits: 6..<7) - public var nrst_stop: nRST_STOP - - /// User option bytes - @ReadWrite(bits: 7..<8) - public var nrst_stdby: nRST_STDBY - - /// Read protect - @ReadWrite(bits: 8..<16) - public var rdp: RDP - - /// Not write protect - @ReadWrite(bits: 16..<24) - public var nwrp: nWRP - - /// Independent watchdog counter freeze in standby mode - @ReadWrite(bits: 30..<31) - public var iwdg_stdby: IWDG_STDBY - - /// Independent watchdog counter freeze in Stop mode - @ReadWrite(bits: 31..<32) - public var iwdg_stop: IWDG_STOP - } - - /// Flash option control register 1 - @Register(bitWidth: 32) - public struct OPTCR1 { - /// Boot base address when Boot pin =0 - @ReadWrite(bits: 0..<16) - public var boot_add0: BOOT_ADD0 - - /// Boot base address when Boot pin =1 - @ReadWrite(bits: 16..<32) - public var boot_add1: BOOT_ADD1 - } -} - -extension FLASH.ACR { - public struct LATENCYValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// 0 wait states - public static let WS0 = Self(rawValue: 0x0) - - /// 1 wait states - public static let WS1 = Self(rawValue: 0x1) - - /// 2 wait states - public static let WS2 = Self(rawValue: 0x2) - - /// 3 wait states - public static let WS3 = Self(rawValue: 0x3) - - /// 4 wait states - public static let WS4 = Self(rawValue: 0x4) - - /// 5 wait states - public static let WS5 = Self(rawValue: 0x5) - - /// 6 wait states - public static let WS6 = Self(rawValue: 0x6) - - /// 7 wait states - public static let WS7 = Self(rawValue: 0x7) - - /// 8 wait states - public static let WS8 = Self(rawValue: 0x8) - - /// 9 wait states - public static let WS9 = Self(rawValue: 0x9) - - /// 10 wait states - public static let WS10 = Self(rawValue: 0xa) - - /// 11 wait states - public static let WS11 = Self(rawValue: 0xb) - - /// 12 wait states - public static let WS12 = Self(rawValue: 0xc) - - /// 13 wait states - public static let WS13 = Self(rawValue: 0xd) - - /// 14 wait states - public static let WS14 = Self(rawValue: 0xe) - - /// 15 wait states - public static let WS15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.ACR { - public struct PRFTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Prefetch is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Prefetch is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.ACR { - public struct ARTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// ART Accelerator is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// ART Accelerator is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.ACR { - public struct ARTRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Accelerator is not reset - public static let NotReset = Self(rawValue: 0x0) - - /// Accelerator is reset - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct PGValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Flash programming activated - public static let Program = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct SERValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Erase activated for selected sector - public static let SectorErase = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct MERValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Erase activated for all user sectors - public static let MassErase = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct PSIZEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Program x8 - public static let PSIZE8 = Self(rawValue: 0x0) - - /// Program x16 - public static let PSIZE16 = Self(rawValue: 0x1) - - /// Program x32 - public static let PSIZE32 = Self(rawValue: 0x2) - - /// Program x64 - public static let PSIZE64 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct STRTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Trigger an erase operation - public static let Start = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct EOPIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// End of operation interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// End of operation interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct ERRIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Error interrupt generation disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Error interrupt generation enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FLASH.CR { - public struct LOCKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// FLASH_CR register is unlocked - public static let Unlocked = Self(rawValue: 0x0) - - /// FLASH_CR register is locked - public static let Locked = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lvgl/Sources/Registers/FMC.swift b/stm32-lvgl/Sources/Registers/FMC.swift deleted file mode 100644 index 6e207f21..00000000 --- a/stm32-lvgl/Sources/Registers/FMC.swift +++ /dev/null @@ -1,1611 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Flexible memory controller -@RegisterBlock -public struct FMC { - /// SRAM/NOR-Flash chip-select control register 1 - @RegisterBlock(offset: 0x0) - public var bcr1: Register - - /// SRAM/NOR-Flash chip-select timing register 1 - @RegisterBlock(offset: 0x4, stride: 0x8, count: 4) - public var btr: RegisterArray - - /// SRAM/NOR-Flash chip-select control register 2 - @RegisterBlock(offset: 0x8, stride: 0x8, count: 3) - public var bcr: RegisterArray - - /// PC Card/NAND Flash control register - @RegisterBlock(offset: 0x80) - public var pcr: Register - - /// FIFO status and interrupt register - @RegisterBlock(offset: 0x84) - public var sr: Register - - /// Common memory space timing register - @RegisterBlock(offset: 0x88) - public var pmem: Register - - /// Attribute memory space timing register - @RegisterBlock(offset: 0x8c) - public var patt: Register - - /// ECC result register - @RegisterBlock(offset: 0x94) - public var eccr: Register - - /// SRAM/NOR-Flash write timing registers 1 - @RegisterBlock(offset: 0x104, stride: 0x8, count: 4) - public var bwtr: RegisterArray - - /// SDRAM Control Register 1 - @RegisterBlock(offset: 0x140, stride: 0x4, count: 2) - public var sdcr: RegisterArray - - /// SDRAM Timing register 1 - @RegisterBlock(offset: 0x148, stride: 0x4, count: 2) - public var sdtr: RegisterArray - - /// SDRAM Command Mode register - @RegisterBlock(offset: 0x150) - public var sdcmr: Register - - /// SDRAM Refresh Timer register - @RegisterBlock(offset: 0x154) - public var sdrtr: Register - - /// SDRAM Status register - @RegisterBlock(offset: 0x158) - public var sdsr: Register -} - -extension FMC { - /// SRAM/NOR-Flash chip-select control register 1 - @Register(bitWidth: 32) - public struct BCR1 { - /// CCLKEN - @ReadWrite(bits: 20..<21, as: CCLKENValues.self) - public var cclken: CCLKEN - - /// CBURSTRW - @ReadWrite(bits: 19..<20, as: CBURSTRWValues.self) - public var cburstrw: CBURSTRW - - /// ASYNCWAIT - @ReadWrite(bits: 15..<16, as: ASYNCWAITValues.self) - public var asyncwait: ASYNCWAIT - - /// EXTMOD - @ReadWrite(bits: 14..<15, as: EXTMODValues.self) - public var extmod: EXTMOD - - /// WAITEN - @ReadWrite(bits: 13..<14, as: WAITENValues.self) - public var waiten: WAITEN - - /// WREN - @ReadWrite(bits: 12..<13, as: WRENValues.self) - public var wren: WREN - - /// WAITCFG - @ReadWrite(bits: 11..<12, as: WAITCFGValues.self) - public var waitcfg: WAITCFG - - /// WAITPOL - @ReadWrite(bits: 9..<10, as: WAITPOLValues.self) - public var waitpol: WAITPOL - - /// BURSTEN - @ReadWrite(bits: 8..<9, as: BURSTENValues.self) - public var bursten: BURSTEN - - /// FACCEN - @ReadWrite(bits: 6..<7, as: FACCENValues.self) - public var faccen: FACCEN - - /// MWID - @ReadWrite(bits: 4..<6, as: MWIDValues.self) - public var mwid: MWID - - /// MTYP - @ReadWrite(bits: 2..<4, as: MTYPValues.self) - public var mtyp: MTYP - - /// MUXEN - @ReadWrite(bits: 1..<2, as: MUXENValues.self) - public var muxen: MUXEN - - /// MBKEN - @ReadWrite(bits: 0..<1, as: MBKENValues.self) - public var mbken: MBKEN - - /// WRAPMOD - @ReadWrite(bits: 10..<11) - public var wrapmod: WRAPMOD - - /// Write FIFO disable - @ReadWrite(bits: 21..<22, as: WFDISValues.self) - public var wfdis: WFDIS - - /// CRAM page size - @ReadWrite(bits: 16..<19, as: CPSIZEValues.self) - public var cpsize: CPSIZE - } - - /// SRAM/NOR-Flash chip-select timing register 1 - @Register(bitWidth: 32) - public struct BTR { - /// ACCMOD - @ReadWrite(bits: 28..<30, as: ACCMODValues.self) - public var accmod: ACCMOD - - /// DATLAT - @ReadWrite(bits: 24..<28) - public var datlat: DATLAT - - /// CLKDIV - @ReadWrite(bits: 20..<24) - public var clkdiv: CLKDIV - - /// BUSTURN - @ReadWrite(bits: 16..<20) - public var busturn: BUSTURN - - /// DATAST - @ReadWrite(bits: 8..<16) - public var datast: DATAST - - /// ADDHLD - @ReadWrite(bits: 4..<8) - public var addhld: ADDHLD - - /// ADDSET - @ReadWrite(bits: 0..<4) - public var addset: ADDSET - } - - /// SRAM/NOR-Flash chip-select control register 2 - @Register(bitWidth: 32) - public struct BCR { - /// CBURSTRW - @ReadWrite(bits: 19..<20, as: CBURSTRWValues.self) - public var cburstrw: CBURSTRW - - /// ASYNCWAIT - @ReadWrite(bits: 15..<16, as: ASYNCWAITValues.self) - public var asyncwait: ASYNCWAIT - - /// EXTMOD - @ReadWrite(bits: 14..<15, as: EXTMODValues.self) - public var extmod: EXTMOD - - /// WAITEN - @ReadWrite(bits: 13..<14, as: WAITENValues.self) - public var waiten: WAITEN - - /// WREN - @ReadWrite(bits: 12..<13, as: WRENValues.self) - public var wren: WREN - - /// WAITCFG - @ReadWrite(bits: 11..<12, as: WAITCFGValues.self) - public var waitcfg: WAITCFG - - /// WRAPMOD - @ReadWrite(bits: 10..<11) - public var wrapmod: WRAPMOD - - /// WAITPOL - @ReadWrite(bits: 9..<10, as: WAITPOLValues.self) - public var waitpol: WAITPOL - - /// BURSTEN - @ReadWrite(bits: 8..<9, as: BURSTENValues.self) - public var bursten: BURSTEN - - /// FACCEN - @ReadWrite(bits: 6..<7, as: FACCENValues.self) - public var faccen: FACCEN - - /// MWID - @ReadWrite(bits: 4..<6, as: MWIDValues.self) - public var mwid: MWID - - /// MTYP - @ReadWrite(bits: 2..<4, as: MTYPValues.self) - public var mtyp: MTYP - - /// MUXEN - @ReadWrite(bits: 1..<2, as: MUXENValues.self) - public var muxen: MUXEN - - /// MBKEN - @ReadWrite(bits: 0..<1, as: MBKENValues.self) - public var mbken: MBKEN - - /// CRAM page size - @ReadWrite(bits: 16..<19, as: CPSIZEValues.self) - public var cpsize: CPSIZE - } - - /// PC Card/NAND Flash control register - @Register(bitWidth: 32) - public struct PCR { - /// ECCPS - @ReadWrite(bits: 17..<20, as: ECCPSValues.self) - public var eccps: ECCPS - - /// TAR - @ReadWrite(bits: 13..<17) - public var tar: TAR - - /// TCLR - @ReadWrite(bits: 9..<13) - public var tclr: TCLR - - /// ECCEN - @ReadWrite(bits: 6..<7, as: ECCENValues.self) - public var eccen: ECCEN - - /// PWID - @ReadWrite(bits: 4..<6, as: PWIDValues.self) - public var pwid: PWID - - /// PTYP - @ReadWrite(bits: 3..<4, as: PTYPValues.self) - public var ptyp: PTYP - - /// PBKEN - @ReadWrite(bits: 2..<3, as: PBKENValues.self) - public var pbken: PBKEN - - /// PWAITEN - @ReadWrite(bits: 1..<2, as: PWAITENValues.self) - public var pwaiten: PWAITEN - } - - /// FIFO status and interrupt register - @Register(bitWidth: 32) - public struct SR { - /// FEMPT - @ReadOnly(bits: 6..<7) - public var fempt: FEMPT - - /// IFEN - @ReadWrite(bits: 5..<6, as: IFENValues.self) - public var ifen: IFEN - - /// ILEN - @ReadWrite(bits: 4..<5, as: ILENValues.self) - public var ilen: ILEN - - /// IREN - @ReadWrite(bits: 3..<4, as: IRENValues.self) - public var iren: IREN - - /// IFS - @ReadWrite(bits: 2..<3, as: IFSValues.self) - public var ifs: IFS - - /// ILS - @ReadWrite(bits: 1..<2, as: ILSValues.self) - public var ils: ILS - - /// IRS - @ReadWrite(bits: 0..<1, as: IRSValues.self) - public var irs: IRS - } - - /// Common memory space timing register - @Register(bitWidth: 32) - public struct PMEM { - /// MEMHIZx - @ReadWrite(bits: 24..<32) - public var memhiz: MEMHIZ - - /// MEMHOLDx - @ReadWrite(bits: 16..<24) - public var memhold: MEMHOLD - - /// MEMWAITx - @ReadWrite(bits: 8..<16) - public var memwait: MEMWAIT - - /// MEMSETx - @ReadWrite(bits: 0..<8) - public var memset: MEMSET - } - - /// Attribute memory space timing register - @Register(bitWidth: 32) - public struct PATT { - /// ATTHIZx - @ReadWrite(bits: 24..<32) - public var atthiz: ATTHIZ - - /// ATTHOLDx - @ReadWrite(bits: 16..<24) - public var atthold: ATTHOLD - - /// ATTWAITx - @ReadWrite(bits: 8..<16) - public var attwait: ATTWAIT - - /// ATTSETx - @ReadWrite(bits: 0..<8) - public var attset: ATTSET - } - - /// ECC result register - @Register(bitWidth: 32) - public struct ECCR { - /// ECCx - @ReadOnly(bits: 0..<32) - public var ecc: ECC - } - - /// SRAM/NOR-Flash write timing registers 1 - @Register(bitWidth: 32) - public struct BWTR { - /// ACCMOD - @ReadWrite(bits: 28..<30, as: ACCMODValues.self) - public var accmod: ACCMOD - - /// DATLAT - @ReadWrite(bits: 24..<28) - public var datlat: DATLAT - - /// CLKDIV - @ReadWrite(bits: 20..<24) - public var clkdiv: CLKDIV - - /// DATAST - @ReadWrite(bits: 8..<16) - public var datast: DATAST - - /// ADDHLD - @ReadWrite(bits: 4..<8) - public var addhld: ADDHLD - - /// ADDSET - @ReadWrite(bits: 0..<4) - public var addset: ADDSET - - /// Bus turnaround phase duration - @ReadWrite(bits: 16..<20) - public var busturn: BUSTURN - } - - /// SDRAM Control Register 1 - @Register(bitWidth: 32) - public struct SDCR { - /// Number of column address bits - @ReadWrite(bits: 0..<2, as: NCValues.self) - public var nc: NC - - /// Number of row address bits - @ReadWrite(bits: 2..<4, as: NRValues.self) - public var nr: NR - - /// Memory data bus width - @ReadWrite(bits: 4..<6, as: MWIDValues.self) - public var mwid: MWID - - /// Number of internal banks - @ReadWrite(bits: 6..<7, as: NBValues.self) - public var nb: NB - - /// CAS latency - @ReadWrite(bits: 7..<9, as: CASValues.self) - public var cas: CAS - - /// Write protection - @ReadWrite(bits: 9..<10, as: WPValues.self) - public var wp: WP - - /// SDRAM clock configuration - @ReadWrite(bits: 10..<12, as: SDCLKValues.self) - public var sdclk: SDCLK - - /// Burst read - @ReadWrite(bits: 12..<13, as: RBURSTValues.self) - public var rburst: RBURST - - /// Read pipe - @ReadWrite(bits: 13..<15, as: RPIPEValues.self) - public var rpipe: RPIPE - } - - /// SDRAM Timing register 1 - @Register(bitWidth: 32) - public struct SDTR { - /// Load Mode Register to Active - @ReadWrite(bits: 0..<4) - public var tmrd: TMRD - - /// Exit self-refresh delay - @ReadWrite(bits: 4..<8) - public var txsr: TXSR - - /// Self refresh time - @ReadWrite(bits: 8..<12) - public var tras: TRAS - - /// Row cycle delay - @ReadWrite(bits: 12..<16) - public var trc: TRC - - /// Recovery delay - @ReadWrite(bits: 16..<20) - public var twr: TWR - - /// Row precharge delay - @ReadWrite(bits: 20..<24) - public var trp: TRP - - /// Row to column delay - @ReadWrite(bits: 24..<28) - public var trcd: TRCD - } - - /// SDRAM Command Mode register - @Register(bitWidth: 32) - public struct SDCMR { - /// Command mode - @WriteOnly(bits: 0..<3) - public var mode: MODE - - /// Command target bank 2 - @WriteOnly(bits: 3..<4) - public var ctb2: CTB2 - - /// Command target bank 1 - @WriteOnly(bits: 4..<5) - public var ctb1: CTB1 - - /// Number of Auto-refresh - @ReadWrite(bits: 5..<9) - public var nrfs: NRFS - - /// Mode Register definition - @ReadWrite(bits: 9..<22) - public var mrd: MRD - } - - /// SDRAM Refresh Timer register - @Register(bitWidth: 32) - public struct SDRTR { - /// Clear Refresh error flag - @WriteOnly(bits: 0..<1) - public var cre: CRE - - /// Refresh Timer Count - @ReadWrite(bits: 1..<14) - public var count: COUNT - - /// RES Interrupt Enable - @ReadWrite(bits: 14..<15, as: REIEValues.self) - public var reie: REIE - } - - /// SDRAM Status register - @Register(bitWidth: 32) - public struct SDSR { - /// Refresh error flag - @ReadOnly(bits: 0..<1) - public var re: RE - - /// Status Mode for Bank 1 - @ReadOnly(bits: 1..<3) - public var modes1: MODES1 - - /// Status Mode for Bank 2 - @ReadOnly(bits: 3..<5) - public var modes2: MODES2 - - /// Busy status - @ReadOnly(bits: 5..<6) - public var busy: BUSY - } -} - -extension FMC.BCR1 { - public struct CCLKENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set - public static let Disabled = Self(rawValue: 0x0) - - /// The FMC_CLK is only generated during the synchronous memory access (read/write transaction) - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct CBURSTRWValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Write operations are always performed in asynchronous mode - public static let Disabled = Self(rawValue: 0x0) - - /// Write operations are performed in synchronous mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct ASYNCWAITValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Wait signal not used in asynchronous mode - public static let Disabled = Self(rawValue: 0x0) - - /// Wait signal used even in asynchronous mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct EXTMODValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Values inside the FMC_BWTR are not taken into account - public static let Disabled = Self(rawValue: 0x0) - - /// Values inside the FMC_BWTR are taken into account - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct WAITENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Values inside the FMC_BWTR are taken into account - public static let Disabled = Self(rawValue: 0x0) - - /// NWAIT signal enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct WRENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Write operations disabled for the bank by the FMC - public static let Disabled = Self(rawValue: 0x0) - - /// Write operations enabled for the bank by the FMC - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct WAITCFGValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// NWAIT signal is active one data cycle before wait state - public static let BeforeWaitState = Self(rawValue: 0x0) - - /// NWAIT signal is active during wait state - public static let DuringWaitState = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct WAITPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// NWAIT active low - public static let ActiveLow = Self(rawValue: 0x0) - - /// NWAIT active high - public static let ActiveHigh = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct BURSTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Burst mode disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Burst mode enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct FACCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Corresponding NOR Flash memory access is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Corresponding NOR Flash memory access is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct MWIDValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Memory data bus width 8 bits - public static let Bits8 = Self(rawValue: 0x0) - - /// Memory data bus width 16 bits - public static let Bits16 = Self(rawValue: 0x1) - - /// Memory data bus width 32 bits - public static let Bits32 = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct MTYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SRAM memory type - public static let SRAM = Self(rawValue: 0x0) - - /// PSRAM (CRAM) memory type - public static let PSRAM = Self(rawValue: 0x1) - - /// NOR Flash/OneNAND Flash - public static let Flash = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct MUXENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Address/Data non-multiplexed - public static let Disabled = Self(rawValue: 0x0) - - /// Address/Data multiplexed on databus - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct MBKENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Corresponding memory bank is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Corresponding memory bank is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct WFDISValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Write FIFO enabled - public static let Enabled = Self(rawValue: 0x0) - - /// Write FIFO disabled - public static let Disabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR1 { - public struct CPSIZEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// No burst split when crossing page boundary - public static let NoBurstSplit = Self(rawValue: 0x0) - - /// 128 bytes CRAM page size - public static let Bytes128 = Self(rawValue: 0x1) - - /// 256 bytes CRAM page size - public static let Bytes256 = Self(rawValue: 0x2) - - /// 512 bytes CRAM page size - public static let Bytes512 = Self(rawValue: 0x3) - - /// 1024 bytes CRAM page size - public static let Bytes1024 = Self(rawValue: 0x4) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BTR { - public struct ACCMODValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Access mode A - public static let A = Self(rawValue: 0x0) - - /// Access mode B - public static let B = Self(rawValue: 0x1) - - /// Access mode C - public static let C = Self(rawValue: 0x2) - - /// Access mode D - public static let D = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct CBURSTRWValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Write operations are always performed in asynchronous mode - public static let Disabled = Self(rawValue: 0x0) - - /// Write operations are performed in synchronous mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct ASYNCWAITValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Wait signal not used in asynchronous mode - public static let Disabled = Self(rawValue: 0x0) - - /// Wait signal used even in asynchronous mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct EXTMODValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Values inside the FMC_BWTR are not taken into account - public static let Disabled = Self(rawValue: 0x0) - - /// Values inside the FMC_BWTR are taken into account - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct WAITENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Values inside the FMC_BWTR are taken into account - public static let Disabled = Self(rawValue: 0x0) - - /// NWAIT signal enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct WRENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Write operations disabled for the bank by the FMC - public static let Disabled = Self(rawValue: 0x0) - - /// Write operations enabled for the bank by the FMC - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct WAITCFGValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// NWAIT signal is active one data cycle before wait state - public static let BeforeWaitState = Self(rawValue: 0x0) - - /// NWAIT signal is active during wait state - public static let DuringWaitState = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct WAITPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// NWAIT active low - public static let ActiveLow = Self(rawValue: 0x0) - - /// NWAIT active high - public static let ActiveHigh = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct BURSTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Burst mode disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Burst mode enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct FACCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Corresponding NOR Flash memory access is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Corresponding NOR Flash memory access is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct MWIDValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Memory data bus width 8 bits - public static let Bits8 = Self(rawValue: 0x0) - - /// Memory data bus width 16 bits - public static let Bits16 = Self(rawValue: 0x1) - - /// Memory data bus width 32 bits - public static let Bits32 = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct MTYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SRAM memory type - public static let SRAM = Self(rawValue: 0x0) - - /// PSRAM (CRAM) memory type - public static let PSRAM = Self(rawValue: 0x1) - - /// NOR Flash/OneNAND Flash - public static let Flash = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct MUXENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Address/Data non-multiplexed - public static let Disabled = Self(rawValue: 0x0) - - /// Address/Data multiplexed on databus - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct MBKENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Corresponding memory bank is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Corresponding memory bank is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BCR { - public struct CPSIZEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// No burst split when crossing page boundary - public static let NoBurstSplit = Self(rawValue: 0x0) - - /// 128 bytes CRAM page size - public static let Bytes128 = Self(rawValue: 0x1) - - /// 256 bytes CRAM page size - public static let Bytes256 = Self(rawValue: 0x2) - - /// 512 bytes CRAM page size - public static let Bytes512 = Self(rawValue: 0x3) - - /// 1024 bytes CRAM page size - public static let Bytes1024 = Self(rawValue: 0x4) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.PCR { - public struct ECCPSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// ECC page size 256 bytes - public static let Bytes256 = Self(rawValue: 0x0) - - /// ECC page size 512 bytes - public static let Bytes512 = Self(rawValue: 0x1) - - /// ECC page size 1024 bytes - public static let Bytes1024 = Self(rawValue: 0x2) - - /// ECC page size 2048 bytes - public static let Bytes2048 = Self(rawValue: 0x3) - - /// ECC page size 4096 bytes - public static let Bytes4096 = Self(rawValue: 0x4) - - /// ECC page size 8192 bytes - public static let Bytes8192 = Self(rawValue: 0x5) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.PCR { - public struct ECCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// ECC logic is disabled and reset - public static let Disabled = Self(rawValue: 0x0) - - /// ECC logic is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.PCR { - public struct PWIDValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// External memory device width 8 bits - public static let Bits8 = Self(rawValue: 0x0) - - /// External memory device width 16 bits - public static let Bits16 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.PCR { - public struct PTYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// NAND Flash - public static let NANDFlash = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.PCR { - public struct PBKENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Corresponding memory bank is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Corresponding memory bank is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.PCR { - public struct PWAITENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Wait feature disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Wait feature enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SR { - public struct IFENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt falling edge detection request disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt falling edge detection request enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SR { - public struct ILENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt high-level detection request disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt high-level detection request enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SR { - public struct IRENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt rising edge detection request disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt rising edge detection request enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SR { - public struct IFSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt falling edge did not occur - public static let DidNotOccur = Self(rawValue: 0x0) - - /// Interrupt falling edge occurred - public static let Occurred = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SR { - public struct ILSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt high-level did not occur - public static let DidNotOccur = Self(rawValue: 0x0) - - /// Interrupt high-level occurred - public static let Occurred = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SR { - public struct IRSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt rising edge did not occur - public static let DidNotOccur = Self(rawValue: 0x0) - - /// Interrupt rising edge occurred - public static let Occurred = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.BWTR { - public struct ACCMODValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Access mode A - public static let A = Self(rawValue: 0x0) - - /// Access mode B - public static let B = Self(rawValue: 0x1) - - /// Access mode C - public static let C = Self(rawValue: 0x2) - - /// Access mode D - public static let D = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SDCR { - public struct NCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// 8 bits - public static let Bits8 = Self(rawValue: 0x0) - - /// 9 bits - public static let Bits9 = Self(rawValue: 0x1) - - /// 10 bits - public static let Bits10 = Self(rawValue: 0x2) - - /// 11 bits - public static let Bits11 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SDCR { - public struct NRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// 11 bits - public static let Bits11 = Self(rawValue: 0x0) - - /// 12 bits - public static let Bits12 = Self(rawValue: 0x1) - - /// 13 bits - public static let Bits13 = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SDCR { - public struct MWIDValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Memory data bus width 8 bits - public static let Bits8 = Self(rawValue: 0x0) - - /// Memory data bus width 16 bits - public static let Bits16 = Self(rawValue: 0x1) - - /// Memory data bus width 32 bits - public static let Bits32 = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SDCR { - public struct NBValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Two internal Banks - public static let NB2 = Self(rawValue: 0x0) - - /// Four internal Banks - public static let NB4 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SDCR { - public struct CASValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// 1 cycle - public static let Clocks1 = Self(rawValue: 0x1) - - /// 2 cycles - public static let Clocks2 = Self(rawValue: 0x2) - - /// 3 cycles - public static let Clocks3 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SDCR { - public struct WPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Write accesses allowed - public static let Disabled = Self(rawValue: 0x0) - - /// Write accesses ignored - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SDCR { - public struct SDCLKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SDCLK clock disabled - public static let Disabled = Self(rawValue: 0x0) - - /// SDCLK period = 2 x HCLK period - public static let Div2 = Self(rawValue: 0x2) - - /// SDCLK period = 3 x HCLK period - public static let Div3 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SDCR { - public struct RBURSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Single read requests are not managed as bursts - public static let Disabled = Self(rawValue: 0x0) - - /// Single read requests are always managed as bursts - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SDCR { - public struct RPIPEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// No clock cycle delay - public static let NoDelay = Self(rawValue: 0x0) - - /// One clock cycle delay - public static let Clocks1 = Self(rawValue: 0x1) - - /// Two clock cycles delay - public static let Clocks2 = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension FMC.SDRTR { - public struct REIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated if RE = 1 - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lvgl/Sources/Registers/GPIOA.swift b/stm32-lvgl/Sources/Registers/GPIOA.swift deleted file mode 100644 index 9513b88f..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOA.swift +++ /dev/null @@ -1,1075 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -@RegisterBlock -public struct GPIOA { - /// GPIO port mode register - @RegisterBlock(offset: 0x0) - public var moder: Register - - /// GPIO port output type register - @RegisterBlock(offset: 0x4) - public var otyper: Register - - /// GPIO port output speed register - @RegisterBlock(offset: 0x8) - public var ospeedr: Register - - /// GPIO port pull-up/pull-down register - @RegisterBlock(offset: 0xc) - public var pupdr: Register - - /// GPIO port input data register - @RegisterBlock(offset: 0x10) - public var idr: Register - - /// GPIO port output data register - @RegisterBlock(offset: 0x14) - public var odr: Register - - /// GPIO port bit set/reset register - @RegisterBlock(offset: 0x18) - public var bsrr: Register - - /// GPIO port configuration lock register - @RegisterBlock(offset: 0x1c) - public var lckr: Register - - /// GPIO alternate function low register - @RegisterBlock(offset: 0x20) - public var afrl: Register - - /// GPIO alternate function high register - @RegisterBlock(offset: 0x24) - public var afrh: Register - - /// GPIO port bit reset register - @RegisterBlock(offset: 0x28) - public var brr: Register -} - -extension GPIOA { - /// GPIO port mode register - @Register(bitWidth: 32) - public struct MODER { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var moder15: MODER15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var moder14: MODER14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var moder13: MODER13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var moder12: MODER12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var moder11: MODER11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var moder10: MODER10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var moder9: MODER9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var moder8: MODER8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var moder7: MODER7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var moder6: MODER6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var moder5: MODER5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var moder4: MODER4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var moder3: MODER3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var moder2: MODER2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var moder1: MODER1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: MODER0Values.self) - public var moder0: MODER0 - } - - /// GPIO port output type register - @Register(bitWidth: 32) - public struct OTYPER { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 15..<16) - public var ot15: OT15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<15) - public var ot14: OT14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 13..<14) - public var ot13: OT13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<13) - public var ot12: OT12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 11..<12) - public var ot11: OT11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<11) - public var ot10: OT10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 9..<10) - public var ot9: OT9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<9) - public var ot8: OT8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 7..<8) - public var ot7: OT7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<7) - public var ot6: OT6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 5..<6) - public var ot5: OT5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<5) - public var ot4: OT4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 3..<4) - public var ot3: OT3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<3) - public var ot2: OT2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 1..<2) - public var ot1: OT1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<1, as: OT0Values.self) - public var ot0: OT0 - } - - /// GPIO port output speed register - @Register(bitWidth: 32) - public struct OSPEEDR { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var ospeedr15: OSPEEDR15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var ospeedr14: OSPEEDR14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var ospeedr13: OSPEEDR13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var ospeedr12: OSPEEDR12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var ospeedr11: OSPEEDR11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var ospeedr10: OSPEEDR10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var ospeedr9: OSPEEDR9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var ospeedr8: OSPEEDR8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var ospeedr7: OSPEEDR7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var ospeedr6: OSPEEDR6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var ospeedr5: OSPEEDR5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var ospeedr4: OSPEEDR4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var ospeedr3: OSPEEDR3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var ospeedr2: OSPEEDR2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var ospeedr1: OSPEEDR1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) - public var ospeedr0: OSPEEDR0 - } - - /// GPIO port pull-up/pull-down register - @Register(bitWidth: 32) - public struct PUPDR { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var pupdr15: PUPDR15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var pupdr14: PUPDR14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var pupdr13: PUPDR13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var pupdr12: PUPDR12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var pupdr11: PUPDR11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var pupdr10: PUPDR10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var pupdr9: PUPDR9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var pupdr8: PUPDR8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var pupdr7: PUPDR7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var pupdr6: PUPDR6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var pupdr5: PUPDR5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var pupdr4: PUPDR4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var pupdr3: PUPDR3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var pupdr2: PUPDR2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var pupdr1: PUPDR1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) - public var pupdr0: PUPDR0 - } - - /// GPIO port input data register - @Register(bitWidth: 32) - public struct IDR { - /// Port input data (y = 0..15) - @ReadOnly(bits: 15..<16) - public var idr15: IDR15 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 14..<15) - public var idr14: IDR14 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 13..<14) - public var idr13: IDR13 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 12..<13) - public var idr12: IDR12 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 11..<12) - public var idr11: IDR11 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 10..<11) - public var idr10: IDR10 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 9..<10) - public var idr9: IDR9 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 8..<9) - public var idr8: IDR8 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 7..<8) - public var idr7: IDR7 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 6..<7) - public var idr6: IDR6 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 5..<6) - public var idr5: IDR5 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 4..<5) - public var idr4: IDR4 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 3..<4) - public var idr3: IDR3 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 2..<3) - public var idr2: IDR2 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 1..<2) - public var idr1: IDR1 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 0..<1) - public var idr0: IDR0 - } - - /// GPIO port output data register - @Register(bitWidth: 32) - public struct ODR { - /// Port output data (y = 0..15) - @ReadWrite(bits: 15..<16) - public var odr15: ODR15 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 14..<15) - public var odr14: ODR14 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 13..<14) - public var odr13: ODR13 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 12..<13) - public var odr12: ODR12 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 11..<12) - public var odr11: ODR11 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 10..<11) - public var odr10: ODR10 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 9..<10) - public var odr9: ODR9 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 8..<9) - public var odr8: ODR8 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 7..<8) - public var odr7: ODR7 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 6..<7) - public var odr6: ODR6 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 5..<6) - public var odr5: ODR5 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 4..<5) - public var odr4: ODR4 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 3..<4) - public var odr3: ODR3 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 2..<3) - public var odr2: ODR2 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 1..<2) - public var odr1: ODR1 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 0..<1, as: ODR0Values.self) - public var odr0: ODR0 - } - - /// GPIO port bit set/reset register - @Register(bitWidth: 32) - public struct BSRR { - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 31..<32) - public var br15: BR15 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 30..<31) - public var br14: BR14 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 29..<30) - public var br13: BR13 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 28..<29) - public var br12: BR12 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 27..<28) - public var br11: BR11 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 26..<27) - public var br10: BR10 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 25..<26) - public var br9: BR9 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 24..<25) - public var br8: BR8 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 23..<24) - public var br7: BR7 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 22..<23) - public var br6: BR6 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 21..<22) - public var br5: BR5 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 20..<21) - public var br4: BR4 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 19..<20) - public var br3: BR3 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 18..<19) - public var br2: BR2 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 17..<18) - public var br1: BR1 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 16..<17) - public var br0: BR0 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 15..<16) - public var bs15: BS15 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 14..<15) - public var bs14: BS14 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 13..<14) - public var bs13: BS13 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 12..<13) - public var bs12: BS12 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 11..<12) - public var bs11: BS11 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 10..<11) - public var bs10: BS10 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 9..<10) - public var bs9: BS9 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 8..<9) - public var bs8: BS8 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 7..<8) - public var bs7: BS7 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 6..<7) - public var bs6: BS6 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 5..<6) - public var bs5: BS5 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 4..<5) - public var bs4: BS4 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 3..<4) - public var bs3: BS3 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 2..<3) - public var bs2: BS2 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 1..<2) - public var bs1: BS1 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 0..<1) - public var bs0: BS0 - } - - /// GPIO port configuration lock register - @Register(bitWidth: 32) - public struct LCKR { - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 16..<17, as: LCKKValues.self) - public var lckk: LCKK - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 15..<16) - public var lck15: LCK15 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 14..<15) - public var lck14: LCK14 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 13..<14) - public var lck13: LCK13 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 12..<13) - public var lck12: LCK12 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 11..<12) - public var lck11: LCK11 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 10..<11) - public var lck10: LCK10 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 9..<10) - public var lck9: LCK9 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 8..<9) - public var lck8: LCK8 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 7..<8) - public var lck7: LCK7 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 6..<7) - public var lck6: LCK6 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 5..<6) - public var lck5: LCK5 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 4..<5) - public var lck4: LCK4 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 3..<4) - public var lck3: LCK3 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 2..<3) - public var lck2: LCK2 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 1..<2) - public var lck1: LCK1 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 0..<1, as: LCK0Values.self) - public var lck0: LCK0 - } - - /// GPIO alternate function low register - @Register(bitWidth: 32) - public struct AFRL { - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 28..<32) - public var afrl7: AFRL7 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 24..<28) - public var afrl6: AFRL6 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 20..<24) - public var afrl5: AFRL5 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 16..<20) - public var afrl4: AFRL4 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 12..<16) - public var afrl3: AFRL3 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 8..<12) - public var afrl2: AFRL2 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 4..<8) - public var afrl1: AFRL1 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 0..<4, as: AFRL0Values.self) - public var afrl0: AFRL0 - } - - /// GPIO alternate function high register - @Register(bitWidth: 32) - public struct AFRH { - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 28..<32) - public var afrh15: AFRH15 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 24..<28) - public var afrh14: AFRH14 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 20..<24) - public var afrh13: AFRH13 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 16..<20) - public var afrh12: AFRH12 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 12..<16) - public var afrh11: AFRH11 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 8..<12) - public var afrh10: AFRH10 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 4..<8) - public var afrh9: AFRH9 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 0..<4, as: AFRH8Values.self) - public var afrh8: AFRH8 - } - - /// GPIO port bit reset register - @Register(bitWidth: 32) - public struct BRR { - /// Port A Reset bit 0 - @ReadWrite(bits: 0..<1) - public var br0: BR0 - - /// Port A Reset bit 1 - @ReadWrite(bits: 1..<2) - public var br1: BR1 - - /// Port A Reset bit 2 - @ReadWrite(bits: 2..<3) - public var br2: BR2 - - /// Port A Reset bit 3 - @ReadWrite(bits: 3..<4) - public var br3: BR3 - - /// Port A Reset bit 4 - @ReadWrite(bits: 4..<5) - public var br4: BR4 - - /// Port A Reset bit 5 - @ReadWrite(bits: 5..<6) - public var br5: BR5 - - /// Port A Reset bit 6 - @ReadWrite(bits: 6..<7) - public var br6: BR6 - - /// Port A Reset bit 7 - @ReadWrite(bits: 7..<8) - public var br7: BR7 - - /// Port A Reset bit 8 - @ReadWrite(bits: 8..<9) - public var br8: BR8 - - /// Port A Reset bit 9 - @ReadWrite(bits: 9..<10) - public var br9: BR9 - - /// Port A Reset bit 10 - @ReadWrite(bits: 10..<11) - public var br10: BR10 - - /// Port A Reset bit 11 - @ReadWrite(bits: 11..<12) - public var br11: BR11 - - /// Port A Reset bit 12 - @ReadWrite(bits: 12..<13) - public var br12: BR12 - - /// Port A Reset bit 13 - @ReadWrite(bits: 13..<14) - public var br13: BR13 - - /// Port A Reset bit 14 - @ReadWrite(bits: 14..<15) - public var br14: BR14 - - /// Port A Reset bit 15 - @ReadWrite(bits: 15..<16) - public var br15: BR15 - } -} - -extension GPIOA.MODER { - public struct MODER0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Input mode (reset state) - public static let Input = Self(rawValue: 0x0) - - /// General purpose output mode - public static let Output = Self(rawValue: 0x1) - - /// Alternate function mode - public static let Alternate = Self(rawValue: 0x2) - - /// Analog mode - public static let Analog = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.OTYPER { - public struct OT0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Output push-pull (reset state) - public static let PushPull = Self(rawValue: 0x0) - - /// Output open-drain - public static let OpenDrain = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.OSPEEDR { - public struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Low speed - public static let LowSpeed = Self(rawValue: 0x0) - - /// Medium speed - public static let MediumSpeed = Self(rawValue: 0x1) - - /// High speed - public static let HighSpeed = Self(rawValue: 0x2) - - /// Very high speed - public static let VeryHighSpeed = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.PUPDR { - public struct PUPDR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// No pull-up, pull-down - public static let Floating = Self(rawValue: 0x0) - - /// Pull-up - public static let PullUp = Self(rawValue: 0x1) - - /// Pull-down - public static let PullDown = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.ODR { - public struct ODR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Set output to logic low - public static let Low = Self(rawValue: 0x0) - - /// Set output to logic high - public static let High = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.LCKR { - public struct LCKKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Port configuration lock key not active - public static let NotActive = Self(rawValue: 0x0) - - /// Port configuration lock key active - public static let Active = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.LCKR { - public struct LCK0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Port configuration not locked - public static let Unlocked = Self(rawValue: 0x0) - - /// Port configuration locked - public static let Locked = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.AFRL { - public struct AFRL0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// AF0 - public static let AF0 = Self(rawValue: 0x0) - - /// AF1 - public static let AF1 = Self(rawValue: 0x1) - - /// AF2 - public static let AF2 = Self(rawValue: 0x2) - - /// AF3 - public static let AF3 = Self(rawValue: 0x3) - - /// AF4 - public static let AF4 = Self(rawValue: 0x4) - - /// AF5 - public static let AF5 = Self(rawValue: 0x5) - - /// AF6 - public static let AF6 = Self(rawValue: 0x6) - - /// AF7 - public static let AF7 = Self(rawValue: 0x7) - - /// AF8 - public static let AF8 = Self(rawValue: 0x8) - - /// AF9 - public static let AF9 = Self(rawValue: 0x9) - - /// AF10 - public static let AF10 = Self(rawValue: 0xa) - - /// AF11 - public static let AF11 = Self(rawValue: 0xb) - - /// AF12 - public static let AF12 = Self(rawValue: 0xc) - - /// AF13 - public static let AF13 = Self(rawValue: 0xd) - - /// AF14 - public static let AF14 = Self(rawValue: 0xe) - - /// AF15 - public static let AF15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.AFRH { - public struct AFRH8Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// AF0 - public static let AF0 = Self(rawValue: 0x0) - - /// AF1 - public static let AF1 = Self(rawValue: 0x1) - - /// AF2 - public static let AF2 = Self(rawValue: 0x2) - - /// AF3 - public static let AF3 = Self(rawValue: 0x3) - - /// AF4 - public static let AF4 = Self(rawValue: 0x4) - - /// AF5 - public static let AF5 = Self(rawValue: 0x5) - - /// AF6 - public static let AF6 = Self(rawValue: 0x6) - - /// AF7 - public static let AF7 = Self(rawValue: 0x7) - - /// AF8 - public static let AF8 = Self(rawValue: 0x8) - - /// AF9 - public static let AF9 = Self(rawValue: 0x9) - - /// AF10 - public static let AF10 = Self(rawValue: 0xa) - - /// AF11 - public static let AF11 = Self(rawValue: 0xb) - - /// AF12 - public static let AF12 = Self(rawValue: 0xc) - - /// AF13 - public static let AF13 = Self(rawValue: 0xd) - - /// AF14 - public static let AF14 = Self(rawValue: 0xe) - - /// AF15 - public static let AF15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lvgl/Sources/Registers/GPIOB.swift b/stm32-lvgl/Sources/Registers/GPIOB.swift deleted file mode 100644 index bd0a35ba..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOB.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOB = GPIOA - diff --git a/stm32-lvgl/Sources/Registers/GPIOC.swift b/stm32-lvgl/Sources/Registers/GPIOC.swift deleted file mode 100644 index c46e6690..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOC.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOC = GPIOA - diff --git a/stm32-lvgl/Sources/Registers/GPIOD.swift b/stm32-lvgl/Sources/Registers/GPIOD.swift deleted file mode 100644 index d51ac802..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOD.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOD = GPIOA - diff --git a/stm32-lvgl/Sources/Registers/GPIOE.swift b/stm32-lvgl/Sources/Registers/GPIOE.swift deleted file mode 100644 index c78fa87f..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOE.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOE = GPIOA - diff --git a/stm32-lvgl/Sources/Registers/GPIOF.swift b/stm32-lvgl/Sources/Registers/GPIOF.swift deleted file mode 100644 index f4dce7fb..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOF.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOF = GPIOA - diff --git a/stm32-lvgl/Sources/Registers/GPIOG.swift b/stm32-lvgl/Sources/Registers/GPIOG.swift deleted file mode 100644 index 88fb4c6a..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOG.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOG = GPIOA - diff --git a/stm32-lvgl/Sources/Registers/GPIOH.swift b/stm32-lvgl/Sources/Registers/GPIOH.swift deleted file mode 100644 index 5a558ef3..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOH.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOH = GPIOA - diff --git a/stm32-lvgl/Sources/Registers/GPIOI.swift b/stm32-lvgl/Sources/Registers/GPIOI.swift deleted file mode 100644 index 6b2b5182..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOI.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOI = GPIOA - diff --git a/stm32-lvgl/Sources/Registers/GPIOJ.swift b/stm32-lvgl/Sources/Registers/GPIOJ.swift deleted file mode 100644 index 98b3c09a..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOJ.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOJ = GPIOA - diff --git a/stm32-lvgl/Sources/Registers/GPIOK.swift b/stm32-lvgl/Sources/Registers/GPIOK.swift deleted file mode 100644 index c1f074b8..00000000 --- a/stm32-lvgl/Sources/Registers/GPIOK.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOK = GPIOA - diff --git a/stm32-lvgl/Sources/Registers/I2C1.swift b/stm32-lvgl/Sources/Registers/I2C1.swift deleted file mode 100644 index c68ff9e9..00000000 --- a/stm32-lvgl/Sources/Registers/I2C1.swift +++ /dev/null @@ -1,1069 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Inter-integrated circuit -@RegisterBlock -public struct I2C1 { - /// Control register 1 - @RegisterBlock(offset: 0x0) - public var cr1: Register - - /// Control register 2 - @RegisterBlock(offset: 0x4) - public var cr2: Register - - /// Own address register 1 - @RegisterBlock(offset: 0x8) - public var oar1: Register - - /// Own address register 2 - @RegisterBlock(offset: 0xc) - public var oar2: Register - - /// Timing register - @RegisterBlock(offset: 0x10) - public var timingr: Register - - /// Status register 1 - @RegisterBlock(offset: 0x14) - public var timeoutr: Register - - /// Interrupt and Status register - @RegisterBlock(offset: 0x18) - public var isr: Register - - /// Interrupt clear register - @RegisterBlock(offset: 0x1c) - public var icr: Register - - /// PEC register - @RegisterBlock(offset: 0x20) - public var pecr: Register - - /// Receive data register - @RegisterBlock(offset: 0x24) - public var rxdr: Register - - /// Transmit data register - @RegisterBlock(offset: 0x28) - public var txdr: Register -} - -extension I2C1 { - /// Control register 1 - @Register(bitWidth: 32) - public struct CR1 { - /// Peripheral enable - @ReadWrite(bits: 0..<1, as: PEValues.self) - public var pe: PE - - /// TX Interrupt enable - @ReadWrite(bits: 1..<2, as: TXIEValues.self) - public var txie: TXIE - - /// RX Interrupt enable - @ReadWrite(bits: 2..<3, as: RXIEValues.self) - public var rxie: RXIE - - /// Address match interrupt enable (slave only) - @ReadWrite(bits: 3..<4, as: ADDRIEValues.self) - public var addrie: ADDRIE - - /// Not acknowledge received interrupt enable - @ReadWrite(bits: 4..<5, as: NACKIEValues.self) - public var nackie: NACKIE - - /// STOP detection Interrupt enable - @ReadWrite(bits: 5..<6, as: STOPIEValues.self) - public var stopie: STOPIE - - /// Transfer Complete interrupt enable - @ReadWrite(bits: 6..<7, as: TCIEValues.self) - public var tcie: TCIE - - /// Error interrupts enable - @ReadWrite(bits: 7..<8, as: ERRIEValues.self) - public var errie: ERRIE - - /// Digital noise filter - @ReadWrite(bits: 8..<12, as: DNFValues.self) - public var dnf: DNF - - /// Analog noise filter OFF - @ReadWrite(bits: 12..<13, as: ANFOFFValues.self) - public var anfoff: ANFOFF - - /// DMA transmission requests enable - @ReadWrite(bits: 14..<15, as: TXDMAENValues.self) - public var txdmaen: TXDMAEN - - /// DMA reception requests enable - @ReadWrite(bits: 15..<16, as: RXDMAENValues.self) - public var rxdmaen: RXDMAEN - - /// Slave byte control - @ReadWrite(bits: 16..<17, as: SBCValues.self) - public var sbc: SBC - - /// Clock stretching disable - @ReadWrite(bits: 17..<18, as: NOSTRETCHValues.self) - public var nostretch: NOSTRETCH - - /// Wakeup from STOP enable - @ReadWrite(bits: 18..<19, as: WUPENValues.self) - public var wupen: WUPEN - - /// General call enable - @ReadWrite(bits: 19..<20, as: GCENValues.self) - public var gcen: GCEN - - /// SMBus Host address enable - @ReadWrite(bits: 20..<21, as: SMBHENValues.self) - public var smbhen: SMBHEN - - /// SMBus Device Default address enable - @ReadWrite(bits: 21..<22, as: SMBDENValues.self) - public var smbden: SMBDEN - - /// SMBUS alert enable - @ReadWrite(bits: 22..<23, as: ALERTENValues.self) - public var alerten: ALERTEN - - /// PEC enable - @ReadWrite(bits: 23..<24, as: PECENValues.self) - public var pecen: PECEN - } - - /// Control register 2 - @Register(bitWidth: 32) - public struct CR2 { - /// Packet error checking byte - @ReadWrite(bits: 26..<27) - public var pecbyte: PECBYTE - - /// Automatic end mode (master mode) - @ReadWrite(bits: 25..<26, as: AUTOENDValues.self) - public var autoend: AUTOEND - - /// NBYTES reload mode - @ReadWrite(bits: 24..<25, as: RELOADValues.self) - public var reload: RELOAD - - /// Number of bytes - @ReadWrite(bits: 16..<24) - public var nbytes: NBYTES - - /// NACK generation (slave mode) - @ReadWrite(bits: 15..<16) - public var nack: NACK - - /// Stop generation (master mode) - @ReadWrite(bits: 14..<15) - public var stop: STOP - - /// Start generation - @ReadWrite(bits: 13..<14) - public var start: START - - /// 10-bit address header only read direction (master receiver mode) - @ReadWrite(bits: 12..<13, as: HEAD10RValues.self) - public var head10r: HEAD10R - - /// 10-bit addressing mode (master mode) - @ReadWrite(bits: 11..<12, as: ADD10Values.self) - public var add10: ADD10 - - /// Transfer direction (master mode) - @ReadWrite(bits: 10..<11, as: RD_WRNValues.self) - public var rd_wrn: RD_WRN - - /// Slave address bit (master mode) - @ReadWrite(bits: 0..<10) - public var sadd: SADD - } - - /// Own address register 1 - @Register(bitWidth: 32) - public struct OAR1 { - /// Interface address - @ReadWrite(bits: 0..<10) - public var oa1: OA1 - - /// Own Address 1 10-bit mode - @ReadWrite(bits: 10..<11, as: OA1MODEValues.self) - public var oa1mode: OA1MODE - - /// Own Address 1 enable - @ReadWrite(bits: 15..<16, as: OA1ENValues.self) - public var oa1en: OA1EN - } - - /// Own address register 2 - @Register(bitWidth: 32) - public struct OAR2 { - /// Interface address - @ReadWrite(bits: 1..<8) - public var oa2: OA2 - - /// Own Address 2 masks - @ReadWrite(bits: 8..<11, as: OA2MSKValues.self) - public var oa2msk: OA2MSK - - /// Own Address 2 enable - @ReadWrite(bits: 15..<16, as: OA2ENValues.self) - public var oa2en: OA2EN - } - - /// Timing register - @Register(bitWidth: 32) - public struct TIMINGR { - /// SCL low period (master mode) - @ReadWrite(bits: 0..<8) - public var scll: SCLL - - /// SCL high period (master mode) - @ReadWrite(bits: 8..<16) - public var sclh: SCLH - - /// Data hold time - @ReadWrite(bits: 16..<20) - public var sdadel: SDADEL - - /// Data setup time - @ReadWrite(bits: 20..<24) - public var scldel: SCLDEL - - /// Timing prescaler - @ReadWrite(bits: 28..<32) - public var presc: PRESC - } - - /// Status register 1 - @Register(bitWidth: 32) - public struct TIMEOUTR { - /// Bus timeout A - @ReadWrite(bits: 0..<12) - public var timeouta: TIMEOUTA - - /// Idle clock timeout detection - @ReadWrite(bits: 12..<13, as: TIDLEValues.self) - public var tidle: TIDLE - - /// Clock timeout enable - @ReadWrite(bits: 15..<16, as: TIMOUTENValues.self) - public var timouten: TIMOUTEN - - /// Bus timeout B - @ReadWrite(bits: 16..<28) - public var timeoutb: TIMEOUTB - - /// Extended clock timeout enable - @ReadWrite(bits: 31..<32, as: TEXTENValues.self) - public var texten: TEXTEN - } - - /// Interrupt and Status register - @Register(bitWidth: 32) - public struct ISR { - /// Address match code (Slave mode) - @ReadOnly(bits: 17..<24) - public var addcode: ADDCODE - - /// Transfer direction (Slave mode) - @ReadOnly(bits: 16..<17) - public var dir: DIR - - /// Bus busy - @ReadOnly(bits: 15..<16) - public var busy: BUSY - - /// SMBus alert - @ReadOnly(bits: 13..<14) - public var alert: ALERT - - /// Timeout or t_low detection flag - @ReadOnly(bits: 12..<13) - public var timeout: TIMEOUT - - /// PEC Error in reception - @ReadOnly(bits: 11..<12) - public var pecerr: PECERR - - /// Overrun/Underrun (slave mode) - @ReadOnly(bits: 10..<11) - public var ovr: OVR - - /// Arbitration lost - @ReadOnly(bits: 9..<10) - public var arlo: ARLO - - /// Bus error - @ReadOnly(bits: 8..<9) - public var berr: BERR - - /// Transfer Complete Reload - @ReadOnly(bits: 7..<8) - public var tcr: TCR - - /// Transfer Complete (master mode) - @ReadOnly(bits: 6..<7) - public var tc: TC - - /// Stop detection flag - @ReadOnly(bits: 5..<6) - public var stopf: STOPF - - /// Not acknowledge received flag - @ReadOnly(bits: 4..<5) - public var nackf: NACKF - - /// Address matched (slave mode) - @ReadOnly(bits: 3..<4) - public var addr: ADDR - - /// Receive data register not empty (receivers) - @ReadOnly(bits: 2..<3) - public var rxne: RXNE - - /// Transmit interrupt status (transmitters) - @ReadWrite(bits: 1..<2) - public var txis: TXIS - - /// Transmit data register empty (transmitters) - @ReadWrite(bits: 0..<1) - public var txe: TXE - } - - /// Interrupt clear register - @Register(bitWidth: 32) - public struct ICR { - /// Alert flag clear - @WriteOnly(bits: 13..<14) - public var alertcf: ALERTCF - - /// Timeout detection flag clear - @WriteOnly(bits: 12..<13) - public var timoutcf: TIMOUTCF - - /// PEC Error flag clear - @WriteOnly(bits: 11..<12) - public var peccf: PECCF - - /// Overrun/Underrun flag clear - @WriteOnly(bits: 10..<11) - public var ovrcf: OVRCF - - /// Arbitration lost flag clear - @WriteOnly(bits: 9..<10) - public var arlocf: ARLOCF - - /// Bus error flag clear - @WriteOnly(bits: 8..<9) - public var berrcf: BERRCF - - /// Stop detection flag clear - @WriteOnly(bits: 5..<6) - public var stopcf: STOPCF - - /// Not Acknowledge flag clear - @WriteOnly(bits: 4..<5) - public var nackcf: NACKCF - - /// Address Matched flag clear - @WriteOnly(bits: 3..<4) - public var addrcf: ADDRCF - } - - /// PEC register - @Register(bitWidth: 32) - public struct PECR { - /// Packet error checking register - @ReadOnly(bits: 0..<8) - public var pec: PEC - } - - /// Receive data register - @Register(bitWidth: 32) - public struct RXDR { - /// 8-bit receive data - @ReadOnly(bits: 0..<8) - public var rxdata: RXDATA - } - - /// Transmit data register - @Register(bitWidth: 32) - public struct TXDR { - /// 8-bit transmit data - @ReadWrite(bits: 0..<8) - public var txdata: TXDATA - } -} - -extension I2C1.CR1 { - public struct PEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Peripheral disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Peripheral enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct TXIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Transmit (TXIS) interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Transmit (TXIS) interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct RXIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Receive (RXNE) interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Receive (RXNE) interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct ADDRIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Address match (ADDR) interrupts disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Address match (ADDR) interrupts enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct NACKIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Not acknowledge (NACKF) received interrupts disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Not acknowledge (NACKF) received interrupts enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct STOPIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Stop detection (STOPF) interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Stop detection (STOPF) interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct TCIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Transfer Complete interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Transfer Complete interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct ERRIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Error detection interrupts disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Error detection interrupts enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct DNFValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// Digital filter disabled - public static let NoFilter = Self(rawValue: 0x0) - - /// Digital filter enabled and filtering capability up to 1 tI2CCLK - public static let Filter1 = Self(rawValue: 0x1) - - /// Digital filter enabled and filtering capability up to 2 tI2CCLK - public static let Filter2 = Self(rawValue: 0x2) - - /// Digital filter enabled and filtering capability up to 3 tI2CCLK - public static let Filter3 = Self(rawValue: 0x3) - - /// Digital filter enabled and filtering capability up to 4 tI2CCLK - public static let Filter4 = Self(rawValue: 0x4) - - /// Digital filter enabled and filtering capability up to 5 tI2CCLK - public static let Filter5 = Self(rawValue: 0x5) - - /// Digital filter enabled and filtering capability up to 6 tI2CCLK - public static let Filter6 = Self(rawValue: 0x6) - - /// Digital filter enabled and filtering capability up to 7 tI2CCLK - public static let Filter7 = Self(rawValue: 0x7) - - /// Digital filter enabled and filtering capability up to 8 tI2CCLK - public static let Filter8 = Self(rawValue: 0x8) - - /// Digital filter enabled and filtering capability up to 9 tI2CCLK - public static let Filter9 = Self(rawValue: 0x9) - - /// Digital filter enabled and filtering capability up to 10 tI2CCLK - public static let Filter10 = Self(rawValue: 0xa) - - /// Digital filter enabled and filtering capability up to 11 tI2CCLK - public static let Filter11 = Self(rawValue: 0xb) - - /// Digital filter enabled and filtering capability up to 12 tI2CCLK - public static let Filter12 = Self(rawValue: 0xc) - - /// Digital filter enabled and filtering capability up to 13 tI2CCLK - public static let Filter13 = Self(rawValue: 0xd) - - /// Digital filter enabled and filtering capability up to 14 tI2CCLK - public static let Filter14 = Self(rawValue: 0xe) - - /// Digital filter enabled and filtering capability up to 15 tI2CCLK - public static let Filter15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct ANFOFFValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Analog noise filter enabled - public static let Enabled = Self(rawValue: 0x0) - - /// Analog noise filter disabled - public static let Disabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct TXDMAENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA mode disabled for transmission - public static let Disabled = Self(rawValue: 0x0) - - /// DMA mode enabled for transmission - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct RXDMAENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA mode disabled for reception - public static let Disabled = Self(rawValue: 0x0) - - /// DMA mode enabled for reception - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct SBCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Slave byte control disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Slave byte control enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct NOSTRETCHValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Clock stretching enabled - public static let Enabled = Self(rawValue: 0x0) - - /// Clock stretching disabled - public static let Disabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct WUPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Wakeup from Stop mode disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Wakeup from Stop mode enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct GCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// General call disabled. Address 0b00000000 is NACKed - public static let Disabled = Self(rawValue: 0x0) - - /// General call enabled. Address 0b00000000 is ACKed - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct SMBHENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Host address disabled. Address 0b0001000x is NACKed - public static let Disabled = Self(rawValue: 0x0) - - /// Host address enabled. Address 0b0001000x is ACKed - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct SMBDENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Device default address disabled. Address 0b1100001x is NACKed - public static let Disabled = Self(rawValue: 0x0) - - /// Device default address enabled. Address 0b1100001x is ACKed - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct ALERTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported - public static let Disabled = Self(rawValue: 0x0) - - /// In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR1 { - public struct PECENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// PEC calculation disabled - public static let Disabled = Self(rawValue: 0x0) - - /// PEC calculation enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR2 { - public struct AUTOENDValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low - public static let Software = Self(rawValue: 0x0) - - /// Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred - public static let Automatic = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR2 { - public struct RELOADValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) - public static let Completed = Self(rawValue: 0x0) - - /// The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) - public static let NotCompleted = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR2 { - public struct HEAD10RValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The master sends the complete 10 bit slave address read sequence - public static let Complete = Self(rawValue: 0x0) - - /// The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction - public static let Partial = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR2 { - public struct ADD10Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The master operates in 7-bit addressing mode - public static let Bit7 = Self(rawValue: 0x0) - - /// The master operates in 10-bit addressing mode - public static let Bit10 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.CR2 { - public struct RD_WRNValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Master requests a write transfer - public static let Write = Self(rawValue: 0x0) - - /// Master requests a read transfer - public static let Read = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.OAR1 { - public struct OA1MODEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Own address 1 is a 7-bit address - public static let Bit7 = Self(rawValue: 0x0) - - /// Own address 1 is a 10-bit address - public static let Bit10 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.OAR1 { - public struct OA1ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Own address 1 disabled. The received slave address OA1 is NACKed - public static let Disabled = Self(rawValue: 0x0) - - /// Own address 1 enabled. The received slave address OA1 is ACKed - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.OAR2 { - public struct OA2MSKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// No mask - public static let NoMask = Self(rawValue: 0x0) - - /// OA2[1] is masked and don’t care. Only OA2[7:2] are compared - public static let Mask1 = Self(rawValue: 0x1) - - /// OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared - public static let Mask2 = Self(rawValue: 0x2) - - /// OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared - public static let Mask3 = Self(rawValue: 0x3) - - /// OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared - public static let Mask4 = Self(rawValue: 0x4) - - /// OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared - public static let Mask5 = Self(rawValue: 0x5) - - /// OA2[6:1] are masked and don’t care. Only OA2[7] is compared. - public static let Mask6 = Self(rawValue: 0x6) - - /// OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged - public static let Mask7 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.OAR2 { - public struct OA2ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Own address 2 disabled. The received slave address OA2 is NACKed - public static let Disabled = Self(rawValue: 0x0) - - /// Own address 2 enabled. The received slave address OA2 is ACKed - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.TIMEOUTR { - public struct TIDLEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// TIMEOUTA is used to detect SCL low timeout - public static let Disabled = Self(rawValue: 0x0) - - /// TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.TIMEOUTR { - public struct TIMOUTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// SCL timeout detection is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// SCL timeout detection is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension I2C1.TIMEOUTR { - public struct TEXTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Extended clock timeout detection is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Extended clock timeout detection is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lvgl/Sources/Registers/I2C2.swift b/stm32-lvgl/Sources/Registers/I2C2.swift deleted file mode 100644 index a10d2091..00000000 --- a/stm32-lvgl/Sources/Registers/I2C2.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Inter-integrated circuit -public typealias I2C2 = I2C1 - diff --git a/stm32-lvgl/Sources/Registers/I2C3.swift b/stm32-lvgl/Sources/Registers/I2C3.swift deleted file mode 100644 index e05597b2..00000000 --- a/stm32-lvgl/Sources/Registers/I2C3.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Inter-integrated circuit -public typealias I2C3 = I2C1 - diff --git a/stm32-lvgl/Sources/Registers/I2C4.swift b/stm32-lvgl/Sources/Registers/I2C4.swift deleted file mode 100644 index bbfbd90b..00000000 --- a/stm32-lvgl/Sources/Registers/I2C4.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Inter-integrated circuit -public typealias I2C4 = I2C1 - diff --git a/stm32-lvgl/Sources/Registers/LTDC.swift b/stm32-lvgl/Sources/Registers/LTDC.swift deleted file mode 100644 index d5d46141..00000000 --- a/stm32-lvgl/Sources/Registers/LTDC.swift +++ /dev/null @@ -1,847 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// LCD-TFT Controller -@RegisterBlock -public struct LTDC { - /// Synchronization Size Configuration Register - @RegisterBlock(offset: 0x8) - public var sscr: Register - - /// Back Porch Configuration Register - @RegisterBlock(offset: 0xc) - public var bpcr: Register - - /// Active Width Configuration Register - @RegisterBlock(offset: 0x10) - public var awcr: Register - - /// Total Width Configuration Register - @RegisterBlock(offset: 0x14) - public var twcr: Register - - /// Global Control Register - @RegisterBlock(offset: 0x18) - public var gcr: Register - - /// Shadow Reload Configuration Register - @RegisterBlock(offset: 0x24) - public var srcr: Register - - /// Background Color Configuration Register - @RegisterBlock(offset: 0x2c) - public var bccr: Register - - /// Interrupt Enable Register - @RegisterBlock(offset: 0x34) - public var ier: Register - - /// Interrupt Status Register - @RegisterBlock(offset: 0x38) - public var isr: Register - - /// Interrupt Clear Register - @RegisterBlock(offset: 0x3c) - public var icr: Register - - /// Line Interrupt Position Configuration Register - @RegisterBlock(offset: 0x40) - public var lipcr: Register - - /// Current Position Status Register - @RegisterBlock(offset: 0x44) - public var cpsr: Register - - /// Current Display Status Register - @RegisterBlock(offset: 0x48) - public var cdsr: Register - - /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR - @RegisterBlock(offset: 0x84, stride: 0x80, count: 2) - public var layer: RegisterArray -} - -extension LTDC { - /// Synchronization Size Configuration Register - @Register(bitWidth: 32) - public struct SSCR { - /// Horizontal Synchronization Width (in units of pixel clock period) - @ReadWrite(bits: 16..<28) - public var hsw: HSW - - /// Vertical Synchronization Height (in units of horizontal scan line) - @ReadWrite(bits: 0..<11) - public var vsh: VSH - } - - /// Back Porch Configuration Register - @Register(bitWidth: 32) - public struct BPCR { - /// Accumulated Horizontal back porch (in units of pixel clock period) - @ReadWrite(bits: 16..<28) - public var ahbp: AHBP - - /// Accumulated Vertical back porch (in units of horizontal scan line) - @ReadWrite(bits: 0..<11) - public var avbp: AVBP - } - - /// Active Width Configuration Register - @Register(bitWidth: 32) - public struct AWCR { - /// Accumulated Active Width (in units of pixel clock period) - @ReadWrite(bits: 16..<28) - public var aaw: AAW - - /// Accumulated Active Height (in units of horizontal scan line) - @ReadWrite(bits: 0..<11) - public var aah: AAH - } - - /// Total Width Configuration Register - @Register(bitWidth: 32) - public struct TWCR { - /// Total Width (in units of pixel clock period) - @ReadWrite(bits: 16..<28) - public var totalw: TOTALW - - /// Total Height (in units of horizontal scan line) - @ReadWrite(bits: 0..<11) - public var totalh: TOTALH - } - - /// Global Control Register - @Register(bitWidth: 32) - public struct GCR { - /// Horizontal Synchronization Polarity - @ReadWrite(bits: 31..<32, as: HSPOLValues.self) - public var hspol: HSPOL - - /// Vertical Synchronization Polarity - @ReadWrite(bits: 30..<31, as: VSPOLValues.self) - public var vspol: VSPOL - - /// Data Enable Polarity - @ReadWrite(bits: 29..<30, as: DEPOLValues.self) - public var depol: DEPOL - - /// Pixel Clock Polarity - @ReadWrite(bits: 28..<29, as: PCPOLValues.self) - public var pcpol: PCPOL - - /// Dither Enable - @ReadWrite(bits: 16..<17, as: DENValues.self) - public var den: DEN - - /// Dither Red Width - @ReadOnly(bits: 12..<15) - public var drw: DRW - - /// Dither Green Width - @ReadOnly(bits: 8..<11) - public var dgw: DGW - - /// Dither Blue Width - @ReadOnly(bits: 4..<7) - public var dbw: DBW - - /// LCD-TFT controller enable bit - @ReadWrite(bits: 0..<1, as: LTDCENValues.self) - public var ltdcen: LTDCEN - } - - /// Shadow Reload Configuration Register - @Register(bitWidth: 32) - public struct SRCR { - /// Vertical Blanking Reload - @ReadWrite(bits: 1..<2, as: VBRValues.self) - public var vbr: VBR - - /// Immediate Reload - @ReadWrite(bits: 0..<1, as: IMRValues.self) - public var imr: IMR - } - - /// Background Color Configuration Register - @Register(bitWidth: 32) - public struct BCCR { - /// Background color blue value - @ReadWrite(bits: 0..<8) - public var bcblue: BCBLUE - - /// Background color green value - @ReadWrite(bits: 8..<16) - public var bcgreen: BCGREEN - - /// Background color red value - @ReadWrite(bits: 16..<24) - public var bcred: BCRED - } - - /// Interrupt Enable Register - @Register(bitWidth: 32) - public struct IER { - /// Register Reload interrupt enable - @ReadWrite(bits: 3..<4, as: RRIEValues.self) - public var rrie: RRIE - - /// Transfer Error Interrupt Enable - @ReadWrite(bits: 2..<3, as: TERRIEValues.self) - public var terrie: TERRIE - - /// FIFO Underrun Interrupt Enable - @ReadWrite(bits: 1..<2, as: FUIEValues.self) - public var fuie: FUIE - - /// Line Interrupt Enable - @ReadWrite(bits: 0..<1, as: LIEValues.self) - public var lie: LIE - } - - /// Interrupt Status Register - @Register(bitWidth: 32) - public struct ISR { - /// Register Reload Interrupt Flag - @ReadOnly(bits: 3..<4) - public var rrif: RRIF - - /// Transfer Error interrupt flag - @ReadOnly(bits: 2..<3) - public var terrif: TERRIF - - /// FIFO Underrun Interrupt flag - @ReadOnly(bits: 1..<2) - public var fuif: FUIF - - /// Line Interrupt flag - @ReadOnly(bits: 0..<1) - public var lif: LIF - } - - /// Interrupt Clear Register - @Register(bitWidth: 32) - public struct ICR { - /// Clears Register Reload Interrupt Flag - @WriteOnly(bits: 3..<4) - public var crrif: CRRIF - - /// Clears the Transfer Error Interrupt Flag - @WriteOnly(bits: 2..<3) - public var cterrif: CTERRIF - - /// Clears the FIFO Underrun Interrupt flag - @WriteOnly(bits: 1..<2) - public var cfuif: CFUIF - - /// Clears the Line Interrupt Flag - @WriteOnly(bits: 0..<1) - public var clif: CLIF - } - - /// Line Interrupt Position Configuration Register - @Register(bitWidth: 32) - public struct LIPCR { - /// Line Interrupt Position - @ReadWrite(bits: 0..<11) - public var lipos: LIPOS - } - - /// Current Position Status Register - @Register(bitWidth: 32) - public struct CPSR { - /// Current X Position - @ReadOnly(bits: 16..<32) - public var cxpos: CXPOS - - /// Current Y Position - @ReadOnly(bits: 0..<16) - public var cypos: CYPOS - } - - /// Current Display Status Register - @Register(bitWidth: 32) - public struct CDSR { - /// Horizontal Synchronization display Status - @ReadOnly(bits: 3..<4) - public var hsyncs: HSYNCS - - /// Vertical Synchronization display Status - @ReadOnly(bits: 2..<3) - public var vsyncs: VSYNCS - - /// Horizontal Data Enable display Status - @ReadOnly(bits: 1..<2) - public var hdes: HDES - - /// Vertical Data Enable display Status - @ReadOnly(bits: 0..<1) - public var vdes: VDES - } - - /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR - @RegisterBlock - public struct LAYER { - /// Layerx Control Register - @RegisterBlock(offset: 0x0) - public var cr: Register - - /// Layerx Window Horizontal Position Configuration Register - @RegisterBlock(offset: 0x4) - public var whpcr: Register - - /// Layerx Window Vertical Position Configuration Register - @RegisterBlock(offset: 0x8) - public var wvpcr: Register - - /// Layerx Color Keying Configuration Register - @RegisterBlock(offset: 0xc) - public var ckcr: Register - - /// Layerx Pixel Format Configuration Register - @RegisterBlock(offset: 0x10) - public var pfcr: Register - - /// Layerx Constant Alpha Configuration Register - @RegisterBlock(offset: 0x14) - public var cacr: Register - - /// Layerx Default Color Configuration Register - @RegisterBlock(offset: 0x18) - public var dccr: Register - - /// Layerx Blending Factors Configuration Register - @RegisterBlock(offset: 0x1c) - public var bfcr: Register - - /// Layerx Color Frame Buffer Address Register - @RegisterBlock(offset: 0x28) - public var cfbar: Register - - /// Layerx Color Frame Buffer Length Register - @RegisterBlock(offset: 0x2c) - public var cfblr: Register - - /// Layerx ColorFrame Buffer Line Number Register - @RegisterBlock(offset: 0x30) - public var cfblnr: Register - - /// Layerx CLUT Write Register - @RegisterBlock(offset: 0x40) - public var clutwr: Register - } -} - -extension LTDC.LAYER { - /// Layerx Control Register - @Register(bitWidth: 32) - public struct CR { - /// Color Look-Up Table Enable - @ReadWrite(bits: 4..<5, as: CLUTENValues.self) - public var cluten: CLUTEN - - /// Color Keying Enable - @ReadWrite(bits: 1..<2, as: COLKENValues.self) - public var colken: COLKEN - - /// Layer Enable - @ReadWrite(bits: 0..<1, as: LENValues.self) - public var len: LEN - } - - /// Layerx Window Horizontal Position Configuration Register - @Register(bitWidth: 32) - public struct WHPCR { - /// Window Horizontal Stop Position - @ReadWrite(bits: 16..<28) - public var whsppos: WHSPPOS - - /// Window Horizontal Start Position - @ReadWrite(bits: 0..<12) - public var whstpos: WHSTPOS - } - - /// Layerx Window Vertical Position Configuration Register - @Register(bitWidth: 32) - public struct WVPCR { - /// Window Vertical Stop Position - @ReadWrite(bits: 16..<27) - public var wvsppos: WVSPPOS - - /// Window Vertical Start Position - @ReadWrite(bits: 0..<11) - public var wvstpos: WVSTPOS - } - - /// Layerx Color Keying Configuration Register - @Register(bitWidth: 32) - public struct CKCR { - /// Color Key Red value - @ReadWrite(bits: 16..<24) - public var ckred: CKRED - - /// Color Key Green value - @ReadWrite(bits: 8..<16) - public var ckgreen: CKGREEN - - /// Color Key Blue value - @ReadWrite(bits: 0..<8) - public var ckblue: CKBLUE - } - - /// Layerx Pixel Format Configuration Register - @Register(bitWidth: 32) - public struct PFCR { - /// Pixel Format - @ReadWrite(bits: 0..<3, as: PFValues.self) - public var pf: PF - } - - /// Layerx Constant Alpha Configuration Register - @Register(bitWidth: 32) - public struct CACR { - /// Constant Alpha - @ReadWrite(bits: 0..<8) - public var consta: CONSTA - } - - /// Layerx Default Color Configuration Register - @Register(bitWidth: 32) - public struct DCCR { - /// Default Color Alpha - @ReadWrite(bits: 24..<32) - public var dcalpha: DCALPHA - - /// Default Color Red - @ReadWrite(bits: 16..<24) - public var dcred: DCRED - - /// Default Color Green - @ReadWrite(bits: 8..<16) - public var dcgreen: DCGREEN - - /// Default Color Blue - @ReadWrite(bits: 0..<8) - public var dcblue: DCBLUE - } - - /// Layerx Blending Factors Configuration Register - @Register(bitWidth: 32) - public struct BFCR { - /// Blending Factor 1 - @ReadWrite(bits: 8..<11, as: BF1Values.self) - public var bf1: BF1 - - /// Blending Factor 2 - @ReadWrite(bits: 0..<3, as: BF2Values.self) - public var bf2: BF2 - } - - /// Layerx Color Frame Buffer Address Register - @Register(bitWidth: 32) - public struct CFBAR { - /// Color Frame Buffer Start Address - @ReadWrite(bits: 0..<32) - public var cfbadd: CFBADD - } - - /// Layerx Color Frame Buffer Length Register - @Register(bitWidth: 32) - public struct CFBLR { - /// Color Frame Buffer Pitch in bytes - @ReadWrite(bits: 16..<29) - public var cfbp: CFBP - - /// Color Frame Buffer Line Length - @ReadWrite(bits: 0..<13) - public var cfbll: CFBLL - } - - /// Layerx ColorFrame Buffer Line Number Register - @Register(bitWidth: 32) - public struct CFBLNR { - /// Frame Buffer Line Number - @ReadWrite(bits: 0..<11) - public var cfblnbr: CFBLNBR - } - - /// Layerx CLUT Write Register - @Register(bitWidth: 32) - public struct CLUTWR { - /// CLUT Address - @WriteOnly(bits: 24..<32) - public var clutadd: CLUTADD - - /// Red value - @WriteOnly(bits: 16..<24) - public var red: RED - - /// Green value - @WriteOnly(bits: 8..<16) - public var green: GREEN - - /// Blue value - @WriteOnly(bits: 0..<8) - public var blue: BLUE - } -} - -extension LTDC.GCR { - public struct HSPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Horizontal synchronization polarity is active low - public static let ActiveLow = Self(rawValue: 0x0) - - /// Horizontal synchronization polarity is active high - public static let ActiveHigh = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.GCR { - public struct VSPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Vertical synchronization polarity is active low - public static let ActiveLow = Self(rawValue: 0x0) - - /// Vertical synchronization polarity is active high - public static let ActiveHigh = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.GCR { - public struct DEPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Data enable polarity is active low - public static let ActiveLow = Self(rawValue: 0x0) - - /// Data enable polarity is active high - public static let ActiveHigh = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.GCR { - public struct PCPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Pixel clock on rising edge - public static let RisingEdge = Self(rawValue: 0x0) - - /// Pixel clock on falling edge - public static let FallingEdge = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.GCR { - public struct DENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Dither disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Dither enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.GCR { - public struct LTDCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LCD-TFT controller disabled - public static let Disabled = Self(rawValue: 0x0) - - /// LCD-TFT controller enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.SRCR { - public struct VBRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - public static let NoEffect = Self(rawValue: 0x0) - - /// The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). - public static let Reload = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.SRCR { - public struct IMRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - public static let NoEffect = Self(rawValue: 0x0) - - /// The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload - public static let Reload = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.IER { - public struct RRIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Register reload interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Register reload interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.IER { - public struct TERRIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Transfer error interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Transfer error interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.IER { - public struct FUIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// FIFO underrun interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// FIFO underrun interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.IER { - public struct LIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Line interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Line interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.CR { - public struct CLUTENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Color look-up table disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Color look-up table enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.CR { - public struct COLKENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Color keying disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Color keying enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.CR { - public struct LENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Layer disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Layer enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.PFCR { - public struct PFValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// ARGB8888 - public static let ARGB8888 = Self(rawValue: 0x0) - - /// RGB888 - public static let RGB888 = Self(rawValue: 0x1) - - /// RGB565 - public static let RGB565 = Self(rawValue: 0x2) - - /// ARGB1555 - public static let ARGB1555 = Self(rawValue: 0x3) - - /// ARGB4444 - public static let ARGB4444 = Self(rawValue: 0x4) - - /// L8 (8-bit luminance) - public static let L8 = Self(rawValue: 0x5) - - /// AL44 (4-bit alpha, 4-bit luminance) - public static let AL44 = Self(rawValue: 0x6) - - /// AL88 (8-bit alpha, 8-bit luminance) - public static let AL88 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.BFCR { - public struct BF1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// BF1 = constant alpha - public static let Constant = Self(rawValue: 0x4) - - /// BF1 = pixel alpha * constant alpha - public static let Pixel = Self(rawValue: 0x6) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension LTDC.LAYER.BFCR { - public struct BF2Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// BF2 = 1 - constant alpha - public static let Constant = Self(rawValue: 0x5) - - /// BF2 = 1 - pixel alpha * constant alpha - public static let Pixel = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lvgl/Sources/Registers/NVIC.swift b/stm32-lvgl/Sources/Registers/NVIC.swift deleted file mode 100644 index 9876eeac..00000000 --- a/stm32-lvgl/Sources/Registers/NVIC.swift +++ /dev/null @@ -1,813 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Nested Vectored Interrupt Controller -@RegisterBlock -public struct NVIC { - /// Interrupt Set-Enable Register - @RegisterBlock(offset: 0x0) - public var iser0: Register - - /// Interrupt Set-Enable Register - @RegisterBlock(offset: 0x4) - public var iser1: Register - - /// Interrupt Set-Enable Register - @RegisterBlock(offset: 0x8) - public var iser2: Register - - /// Interrupt Clear-Enable Register - @RegisterBlock(offset: 0x80) - public var icer0: Register - - /// Interrupt Clear-Enable Register - @RegisterBlock(offset: 0x84) - public var icer1: Register - - /// Interrupt Clear-Enable Register - @RegisterBlock(offset: 0x88) - public var icer2: Register - - /// Interrupt Set-Pending Register - @RegisterBlock(offset: 0x100) - public var ispr0: Register - - /// Interrupt Set-Pending Register - @RegisterBlock(offset: 0x104) - public var ispr1: Register - - /// Interrupt Set-Pending Register - @RegisterBlock(offset: 0x108) - public var ispr2: Register - - /// Interrupt Clear-Pending Register - @RegisterBlock(offset: 0x180) - public var icpr0: Register - - /// Interrupt Clear-Pending Register - @RegisterBlock(offset: 0x184) - public var icpr1: Register - - /// Interrupt Clear-Pending Register - @RegisterBlock(offset: 0x188) - public var icpr2: Register - - /// Interrupt Active Bit Register - @RegisterBlock(offset: 0x200) - public var iabr0: Register - - /// Interrupt Active Bit Register - @RegisterBlock(offset: 0x204) - public var iabr1: Register - - /// Interrupt Active Bit Register - @RegisterBlock(offset: 0x208) - public var iabr2: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x300) - public var ipr0: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x304) - public var ipr1: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x308) - public var ipr2: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x30c) - public var ipr3: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x310) - public var ipr4: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x314) - public var ipr5: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x318) - public var ipr6: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x31c) - public var ipr7: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x320) - public var ipr8: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x324) - public var ipr9: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x328) - public var ipr10: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x32c) - public var ipr11: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x330) - public var ipr12: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x334) - public var ipr13: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x338) - public var ipr14: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x33c) - public var ipr15: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x340) - public var ipr16: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x344) - public var ipr17: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x348) - public var ipr18: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x34c) - public var ipr19: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x350) - public var ipr20: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x354) - public var ipr21: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x358) - public var ipr22: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x35c) - public var ipr23: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x360) - public var ipr24: Register - - /// Interrupt Priority Register - @RegisterBlock(offset: 0x364) - public var ipr25: Register -} - -extension NVIC { - /// Interrupt Set-Enable Register - @Register(bitWidth: 32) - public struct ISER0 { - /// SETENA - @ReadWrite(bits: 0..<32) - public var setena: SETENA - } - - /// Interrupt Set-Enable Register - @Register(bitWidth: 32) - public struct ISER1 { - /// SETENA - @ReadWrite(bits: 0..<32) - public var setena: SETENA - } - - /// Interrupt Set-Enable Register - @Register(bitWidth: 32) - public struct ISER2 { - /// SETENA - @ReadWrite(bits: 0..<32) - public var setena: SETENA - } - - /// Interrupt Clear-Enable Register - @Register(bitWidth: 32) - public struct ICER0 { - /// CLRENA - @ReadWrite(bits: 0..<32) - public var clrena: CLRENA - } - - /// Interrupt Clear-Enable Register - @Register(bitWidth: 32) - public struct ICER1 { - /// CLRENA - @ReadWrite(bits: 0..<32) - public var clrena: CLRENA - } - - /// Interrupt Clear-Enable Register - @Register(bitWidth: 32) - public struct ICER2 { - /// CLRENA - @ReadWrite(bits: 0..<32) - public var clrena: CLRENA - } - - /// Interrupt Set-Pending Register - @Register(bitWidth: 32) - public struct ISPR0 { - /// SETPEND - @ReadWrite(bits: 0..<32) - public var setpend: SETPEND - } - - /// Interrupt Set-Pending Register - @Register(bitWidth: 32) - public struct ISPR1 { - /// SETPEND - @ReadWrite(bits: 0..<32) - public var setpend: SETPEND - } - - /// Interrupt Set-Pending Register - @Register(bitWidth: 32) - public struct ISPR2 { - /// SETPEND - @ReadWrite(bits: 0..<32) - public var setpend: SETPEND - } - - /// Interrupt Clear-Pending Register - @Register(bitWidth: 32) - public struct ICPR0 { - /// CLRPEND - @ReadWrite(bits: 0..<32) - public var clrpend: CLRPEND - } - - /// Interrupt Clear-Pending Register - @Register(bitWidth: 32) - public struct ICPR1 { - /// CLRPEND - @ReadWrite(bits: 0..<32) - public var clrpend: CLRPEND - } - - /// Interrupt Clear-Pending Register - @Register(bitWidth: 32) - public struct ICPR2 { - /// CLRPEND - @ReadWrite(bits: 0..<32) - public var clrpend: CLRPEND - } - - /// Interrupt Active Bit Register - @Register(bitWidth: 32) - public struct IABR0 { - /// ACTIVE - @ReadOnly(bits: 0..<32) - public var active: ACTIVE - } - - /// Interrupt Active Bit Register - @Register(bitWidth: 32) - public struct IABR1 { - /// ACTIVE - @ReadOnly(bits: 0..<32) - public var active: ACTIVE - } - - /// Interrupt Active Bit Register - @Register(bitWidth: 32) - public struct IABR2 { - /// ACTIVE - @ReadOnly(bits: 0..<32) - public var active: ACTIVE - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR0 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR1 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR2 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR3 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR4 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR5 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR6 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR7 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR8 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR9 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR10 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR11 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR12 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR13 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR14 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR15 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR16 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR17 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR18 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR19 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR20 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR21 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR22 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR23 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR24 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } - - /// Interrupt Priority Register - @Register(bitWidth: 32) - public struct IPR25 { - /// IPR_N0 - @ReadWrite(bits: 0..<8) - public var ipr_n0: IPR_N0 - - /// IPR_N1 - @ReadWrite(bits: 8..<16) - public var ipr_n1: IPR_N1 - - /// IPR_N2 - @ReadWrite(bits: 16..<24) - public var ipr_n2: IPR_N2 - - /// IPR_N3 - @ReadWrite(bits: 24..<32) - public var ipr_n3: IPR_N3 - } -} diff --git a/stm32-lvgl/Sources/Registers/PWR.swift b/stm32-lvgl/Sources/Registers/PWR.swift deleted file mode 100644 index eb8cdcae..00000000 --- a/stm32-lvgl/Sources/Registers/PWR.swift +++ /dev/null @@ -1,270 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Power control -@RegisterBlock -public struct PWR { - /// power control register - @RegisterBlock(offset: 0x0) - public var cr1: Register - - /// power control/status register - @RegisterBlock(offset: 0x4) - public var csr1: Register - - /// power control register - @RegisterBlock(offset: 0x8) - public var cr2: Register - - /// power control/status register - @RegisterBlock(offset: 0xc) - public var csr2: Register -} - -extension PWR { - /// power control register - @Register(bitWidth: 32) - public struct CR1 { - /// Low-power deep sleep - @ReadWrite(bits: 0..<1) - public var lpds: LPDS - - /// Power down deepsleep - @ReadWrite(bits: 1..<2, as: PDDSValues.self) - public var pdds: PDDS - - /// Clear standby flag - @ReadWrite(bits: 3..<4) - public var csbf: CSBF - - /// Power voltage detector enable - @ReadWrite(bits: 4..<5) - public var pvde: PVDE - - /// PVD level selection - @ReadWrite(bits: 5..<8) - public var pls: PLS - - /// Disable backup domain write protection - @ReadWrite(bits: 8..<9) - public var dbp: DBP - - /// Flash power down in Stop mode - @ReadWrite(bits: 9..<10) - public var fpds: FPDS - - /// Low-power regulator in deepsleep under-drive mode - @ReadWrite(bits: 10..<11) - public var lpuds: LPUDS - - /// Main regulator in deepsleep under-drive mode - @ReadWrite(bits: 11..<12) - public var mruds: MRUDS - - /// ADCDC1 - @ReadWrite(bits: 13..<14) - public var adcdc1: ADCDC1 - - /// Regulator voltage scaling output selection - @ReadWrite(bits: 14..<16, as: VOSValues.self) - public var vos: VOS - - /// Over-drive enable - @ReadWrite(bits: 16..<17) - public var oden: ODEN - - /// Over-drive switching enabled - @ReadWrite(bits: 17..<18) - public var odswen: ODSWEN - - /// Under-drive enable in stop mode - @ReadWrite(bits: 18..<20) - public var uden: UDEN - } - - /// power control/status register - @Register(bitWidth: 32) - public struct CSR1 { - /// Wakeup internal flag - @ReadOnly(bits: 0..<1) - public var wuif: WUIF - - /// Standby flag - @ReadOnly(bits: 1..<2) - public var sbf: SBF - - /// PVD output - @ReadOnly(bits: 2..<3) - public var pvdo: PVDO - - /// Backup regulator ready - @ReadOnly(bits: 3..<4) - public var brr: BRR - - /// Backup regulator enable - @ReadWrite(bits: 9..<10) - public var bre: BRE - - /// Regulator voltage scaling output selection ready bit - @ReadWrite(bits: 14..<15) - public var vosrdy: VOSRDY - - /// Over-drive mode ready - @ReadWrite(bits: 16..<17) - public var odrdy: ODRDY - - /// Over-drive mode switching ready - @ReadWrite(bits: 17..<18) - public var odswrdy: ODSWRDY - - /// Under-drive ready flag - @ReadWrite(bits: 18..<20) - public var udrdy: UDRDY - } - - /// power control register - @Register(bitWidth: 32) - public struct CR2 { - /// Clear Wakeup Pin flag for PA0 - @ReadOnly(bits: 0..<1) - public var cwupf1: CWUPF1 - - /// Clear Wakeup Pin flag for PA2 - @ReadOnly(bits: 1..<2) - public var cwupf2: CWUPF2 - - /// Clear Wakeup Pin flag for PC1 - @ReadOnly(bits: 2..<3) - public var cwupf3: CWUPF3 - - /// Clear Wakeup Pin flag for PC13 - @ReadOnly(bits: 3..<4) - public var cwupf4: CWUPF4 - - /// Clear Wakeup Pin flag for PI8 - @ReadOnly(bits: 4..<5) - public var cwupf5: CWUPF5 - - /// Clear Wakeup Pin flag for PI11 - @ReadOnly(bits: 5..<6) - public var cwupf6: CWUPF6 - - /// Wakeup pin polarity bit for PA0 - @ReadWrite(bits: 8..<9) - public var wupp1: WUPP1 - - /// Wakeup pin polarity bit for PA2 - @ReadWrite(bits: 9..<10) - public var wupp2: WUPP2 - - /// Wakeup pin polarity bit for PC1 - @ReadWrite(bits: 10..<11) - public var wupp3: WUPP3 - - /// Wakeup pin polarity bit for PC13 - @ReadWrite(bits: 11..<12) - public var wupp4: WUPP4 - - /// Wakeup pin polarity bit for PI8 - @ReadWrite(bits: 12..<13) - public var wupp5: WUPP5 - - /// Wakeup pin polarity bit for PI11 - @ReadWrite(bits: 13..<14) - public var wupp6: WUPP6 - } - - /// power control/status register - @Register(bitWidth: 32) - public struct CSR2 { - /// Wakeup Pin flag for PA0 - @ReadOnly(bits: 0..<1) - public var wupf1: WUPF1 - - /// Wakeup Pin flag for PA2 - @ReadOnly(bits: 1..<2) - public var wupf2: WUPF2 - - /// Wakeup Pin flag for PC1 - @ReadOnly(bits: 2..<3) - public var wupf3: WUPF3 - - /// Wakeup Pin flag for PC13 - @ReadOnly(bits: 3..<4) - public var wupf4: WUPF4 - - /// Wakeup Pin flag for PI8 - @ReadOnly(bits: 4..<5) - public var wupf5: WUPF5 - - /// Wakeup Pin flag for PI11 - @ReadOnly(bits: 5..<6) - public var wupf6: WUPF6 - - /// Enable Wakeup pin for PA0 - @ReadWrite(bits: 8..<9) - public var ewup1: EWUP1 - - /// Enable Wakeup pin for PA2 - @ReadWrite(bits: 9..<10) - public var ewup2: EWUP2 - - /// Enable Wakeup pin for PC1 - @ReadWrite(bits: 10..<11) - public var ewup3: EWUP3 - - /// Enable Wakeup pin for PC13 - @ReadWrite(bits: 11..<12) - public var ewup4: EWUP4 - - /// Enable Wakeup pin for PI8 - @ReadWrite(bits: 12..<13) - public var ewup5: EWUP5 - - /// Enable Wakeup pin for PI11 - @ReadWrite(bits: 13..<14) - public var ewup6: EWUP6 - } -} - -extension PWR.CR1 { - public struct PDDSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Enter Stop mode when the CPU enters deepsleep - public static let STOP_MODE = Self(rawValue: 0x0) - - /// Enter Standby mode when the CPU enters deepsleep - public static let STANDBY_MODE = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension PWR.CR1 { - public struct VOSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Scale 3 mode - public static let SCALE3 = Self(rawValue: 0x1) - - /// Scale 2 mode - public static let SCALE2 = Self(rawValue: 0x2) - - /// Scale 1 mode (reset value) - public static let SCALE1 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lvgl/Sources/Registers/RCC.swift b/stm32-lvgl/Sources/Registers/RCC.swift deleted file mode 100644 index 57d1fdc3..00000000 --- a/stm32-lvgl/Sources/Registers/RCC.swift +++ /dev/null @@ -1,2833 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Reset and clock control -@RegisterBlock -public struct RCC { - /// clock control register - @RegisterBlock(offset: 0x0) - public var cr: Register - - /// PLL configuration register - @RegisterBlock(offset: 0x4) - public var pllcfgr: Register - - /// clock configuration register - @RegisterBlock(offset: 0x8) - public var cfgr: Register - - /// clock interrupt register - @RegisterBlock(offset: 0xc) - public var cir: Register - - /// AHB1 peripheral reset register - @RegisterBlock(offset: 0x10) - public var ahb1rstr: Register - - /// AHB2 peripheral reset register - @RegisterBlock(offset: 0x14) - public var ahb2rstr: Register - - /// AHB3 peripheral reset register - @RegisterBlock(offset: 0x18) - public var ahb3rstr: Register - - /// APB1 peripheral reset register - @RegisterBlock(offset: 0x20) - public var apb1rstr: Register - - /// APB2 peripheral reset register - @RegisterBlock(offset: 0x24) - public var apb2rstr: Register - - /// AHB1 peripheral clock register - @RegisterBlock(offset: 0x30) - public var ahb1enr: Register - - /// AHB2 peripheral clock enable register - @RegisterBlock(offset: 0x34) - public var ahb2enr: Register - - /// AHB3 peripheral clock enable register - @RegisterBlock(offset: 0x38) - public var ahb3enr: Register - - /// APB1 peripheral clock enable register - @RegisterBlock(offset: 0x40) - public var apb1enr: Register - - /// APB2 peripheral clock enable register - @RegisterBlock(offset: 0x44) - public var apb2enr: Register - - /// AHB1 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x50) - public var ahb1lpenr: Register - - /// AHB2 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x54) - public var ahb2lpenr: Register - - /// AHB3 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x58) - public var ahb3lpenr: Register - - /// APB1 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x60) - public var apb1lpenr: Register - - /// APB2 peripheral clock enabled in low power mode register - @RegisterBlock(offset: 0x64) - public var apb2lpenr: Register - - /// Backup domain control register - @RegisterBlock(offset: 0x70) - public var bdcr: Register - - /// clock control & status register - @RegisterBlock(offset: 0x74) - public var csr: Register - - /// spread spectrum clock generation register - @RegisterBlock(offset: 0x80) - public var sscgr: Register - - /// PLLI2S configuration register - @RegisterBlock(offset: 0x84) - public var plli2scfgr: Register - - /// PLL configuration register - @RegisterBlock(offset: 0x88) - public var pllsaicfgr: Register - - /// dedicated clocks configuration register - @RegisterBlock(offset: 0x8c) - public var dckcfgr1: Register - - /// dedicated clocks configuration register - @RegisterBlock(offset: 0x90) - public var dckcfgr2: Register -} - -extension RCC { - /// clock control register - @Register(bitWidth: 32) - public struct CR { - /// PLLI2S clock ready flag - @ReadOnly(bits: 27..<28) - public var plli2srdy: PLLI2SRDY - - /// PLLI2S enable - @ReadWrite(bits: 26..<27) - public var plli2son: PLLI2SON - - /// Main PLL (PLL) clock ready flag - @ReadOnly(bits: 25..<26) - public var pllrdy: PLLRDY - - /// Main PLL (PLL) enable - @ReadWrite(bits: 24..<25) - public var pllon: PLLON - - /// Clock security system enable - @ReadWrite(bits: 19..<20, as: CSSONValues.self) - public var csson: CSSON - - /// HSE clock bypass - @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) - public var hsebyp: HSEBYP - - /// HSE clock ready flag - @ReadOnly(bits: 17..<18) - public var hserdy: HSERDY - - /// HSE clock enable - @ReadWrite(bits: 16..<17) - public var hseon: HSEON - - /// Internal high-speed clock calibration - @ReadOnly(bits: 8..<16) - public var hsical: HSICAL - - /// Internal high-speed clock trimming - @ReadWrite(bits: 3..<8) - public var hsitrim: HSITRIM - - /// Internal high-speed clock ready flag - @ReadOnly(bits: 1..<2) - public var hsirdy: HSIRDY - - /// Internal high-speed clock enable - @ReadWrite(bits: 0..<1, as: HSIONValues.self) - public var hsion: HSION - - /// PLLSAI clock ready flag - @ReadOnly(bits: 29..<30) - public var pllsairdy: PLLSAIRDY - - /// PLLSAI enable - @ReadWrite(bits: 28..<29) - public var pllsaion: PLLSAION - } - - /// PLL configuration register - @Register(bitWidth: 32) - public struct PLLCFGR { - /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) - public var pllsrc: PLLSRC - - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 0..<6) - public var pllm: PLLM - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 6..<15) - public var plln: PLLN - - /// Main PLL (PLL) division factor for main system clock - @ReadWrite(bits: 16..<18, as: PLLPValues.self) - public var pllp: PLLP - - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 24..<28) - public var pllq: PLLQ - } - - /// clock configuration register - @Register(bitWidth: 32) - public struct CFGR { - /// Microcontroller clock output 2 - @ReadWrite(bits: 30..<32, as: MCO2Values.self) - public var mco2: MCO2 - - /// MCO2 prescaler - @ReadWrite(bits: 27..<30) - public var mco2pre: MCO2PRE - - /// MCO1 prescaler - @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) - public var mco1pre: MCO1PRE - - /// I2S clock selection - @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) - public var i2ssrc: I2SSRC - - /// Microcontroller clock output 1 - @ReadWrite(bits: 21..<23, as: MCO1Values.self) - public var mco1: MCO1 - - /// HSE division factor for RTC clock - @ReadWrite(bits: 16..<21) - public var rtcpre: RTCPRE - - /// APB high-speed prescaler (APB2) - @ReadWrite(bits: 13..<16) - public var ppre2: PPRE2 - - /// APB Low speed prescaler (APB1) - @ReadWrite(bits: 10..<13, as: PPRE1Values.self) - public var ppre1: PPRE1 - - /// AHB prescaler - @ReadWrite(bits: 4..<8, as: HPREValues.self) - public var hpre: HPRE - - /// System clock switch - @Reserved(bits: 0..<2, as: SWValues.self) - public var sw: SW - - /// System clock switch status - @Reserved(bits: 2..<4) - public var sws: SWS - } - - /// clock interrupt register - @Register(bitWidth: 32) - public struct CIR { - /// Clock security system interrupt clear - @WriteOnly(bits: 23..<24) - public var cssc: CSSC - - /// PLLSAI Ready Interrupt Clear - @WriteOnly(bits: 22..<23) - public var pllsairdyc: PLLSAIRDYC - - /// PLLI2S ready interrupt clear - @WriteOnly(bits: 21..<22) - public var plli2srdyc: PLLI2SRDYC - - /// Main PLL(PLL) ready interrupt clear - @WriteOnly(bits: 20..<21) - public var pllrdyc: PLLRDYC - - /// HSE ready interrupt clear - @WriteOnly(bits: 19..<20) - public var hserdyc: HSERDYC - - /// HSI ready interrupt clear - @WriteOnly(bits: 18..<19) - public var hsirdyc: HSIRDYC - - /// LSE ready interrupt clear - @WriteOnly(bits: 17..<18) - public var lserdyc: LSERDYC - - /// LSI ready interrupt clear - @WriteOnly(bits: 16..<17) - public var lsirdyc: LSIRDYC - - /// PLLSAI Ready Interrupt Enable - @ReadWrite(bits: 14..<15) - public var pllsairdyie: PLLSAIRDYIE - - /// PLLI2S ready interrupt enable - @ReadWrite(bits: 13..<14) - public var plli2srdyie: PLLI2SRDYIE - - /// Main PLL (PLL) ready interrupt enable - @ReadWrite(bits: 12..<13) - public var pllrdyie: PLLRDYIE - - /// HSE ready interrupt enable - @ReadWrite(bits: 11..<12) - public var hserdyie: HSERDYIE - - /// HSI ready interrupt enable - @ReadWrite(bits: 10..<11) - public var hsirdyie: HSIRDYIE - - /// LSE ready interrupt enable - @ReadWrite(bits: 9..<10) - public var lserdyie: LSERDYIE - - /// LSI ready interrupt enable - @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) - public var lsirdyie: LSIRDYIE - - /// Clock security system interrupt flag - @ReadOnly(bits: 7..<8) - public var cssf: CSSF - - /// PLLSAI ready interrupt flag - @ReadOnly(bits: 6..<7) - public var pllsairdyf: PLLSAIRDYF - - /// PLLI2S ready interrupt flag - @ReadOnly(bits: 5..<6) - public var plli2srdyf: PLLI2SRDYF - - /// Main PLL (PLL) ready interrupt flag - @ReadOnly(bits: 4..<5) - public var pllrdyf: PLLRDYF - - /// HSE ready interrupt flag - @ReadOnly(bits: 3..<4) - public var hserdyf: HSERDYF - - /// HSI ready interrupt flag - @ReadOnly(bits: 2..<3) - public var hsirdyf: HSIRDYF - - /// LSE ready interrupt flag - @ReadOnly(bits: 1..<2) - public var lserdyf: LSERDYF - - /// LSI ready interrupt flag - @ReadOnly(bits: 0..<1) - public var lsirdyf: LSIRDYF - } - - /// AHB1 peripheral reset register - @Register(bitWidth: 32) - public struct AHB1RSTR { - /// USB OTG HS module reset - @ReadWrite(bits: 29..<30) - public var otghsrst: OTGHSRST - - /// Ethernet MAC reset - @ReadWrite(bits: 25..<26) - public var ethmacrst: ETHMACRST - - /// DMA2D reset - @ReadWrite(bits: 23..<24) - public var dma2drst: DMA2DRST - - /// DMA2 reset - @ReadWrite(bits: 22..<23) - public var dma2rst: DMA2RST - - /// DMA2 reset - @ReadWrite(bits: 21..<22) - public var dma1rst: DMA1RST - - /// CRC reset - @ReadWrite(bits: 12..<13) - public var crcrst: CRCRST - - /// IO port K reset - @ReadWrite(bits: 10..<11) - public var gpiokrst: GPIOKRST - - /// IO port J reset - @ReadWrite(bits: 9..<10) - public var gpiojrst: GPIOJRST - - /// IO port I reset - @ReadWrite(bits: 8..<9) - public var gpioirst: GPIOIRST - - /// IO port H reset - @ReadWrite(bits: 7..<8) - public var gpiohrst: GPIOHRST - - /// IO port G reset - @ReadWrite(bits: 6..<7) - public var gpiogrst: GPIOGRST - - /// IO port F reset - @ReadWrite(bits: 5..<6) - public var gpiofrst: GPIOFRST - - /// IO port E reset - @ReadWrite(bits: 4..<5) - public var gpioerst: GPIOERST - - /// IO port D reset - @ReadWrite(bits: 3..<4) - public var gpiodrst: GPIODRST - - /// IO port C reset - @ReadWrite(bits: 2..<3) - public var gpiocrst: GPIOCRST - - /// IO port B reset - @ReadWrite(bits: 1..<2) - public var gpiobrst: GPIOBRST - - /// IO port A reset - @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) - public var gpioarst: GPIOARST - } - - /// AHB2 peripheral reset register - @Register(bitWidth: 32) - public struct AHB2RSTR { - /// USB OTG FS module reset - @ReadWrite(bits: 7..<8) - public var otgfsrst: OTGFSRST - - /// Random number generator module reset - @ReadWrite(bits: 6..<7) - public var rngrst: RNGRST - - /// Hash module reset - @ReadWrite(bits: 5..<6) - public var hsahrst: HSAHRST - - /// Cryptographic module reset - @ReadWrite(bits: 4..<5) - public var cryprst: CRYPRST - - /// Camera interface reset - @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) - public var dcmirst: DCMIRST - } - - /// AHB3 peripheral reset register - @Register(bitWidth: 32) - public struct AHB3RSTR { - /// Flexible memory controller module reset - @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) - public var fmcrst: FMCRST - - /// Quad SPI memory controller reset - @ReadWrite(bits: 1..<2) - public var qspirst: QSPIRST - } - - /// APB1 peripheral reset register - @Register(bitWidth: 32) - public struct APB1RSTR { - /// TIM2 reset - @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) - public var tim2rst: TIM2RST - - /// TIM3 reset - @ReadWrite(bits: 1..<2) - public var tim3rst: TIM3RST - - /// TIM4 reset - @ReadWrite(bits: 2..<3) - public var tim4rst: TIM4RST - - /// TIM5 reset - @ReadWrite(bits: 3..<4) - public var tim5rst: TIM5RST - - /// TIM6 reset - @ReadWrite(bits: 4..<5) - public var tim6rst: TIM6RST - - /// TIM7 reset - @ReadWrite(bits: 5..<6) - public var tim7rst: TIM7RST - - /// TIM12 reset - @ReadWrite(bits: 6..<7) - public var tim12rst: TIM12RST - - /// TIM13 reset - @ReadWrite(bits: 7..<8) - public var tim13rst: TIM13RST - - /// TIM14 reset - @ReadWrite(bits: 8..<9) - public var tim14rst: TIM14RST - - /// Window watchdog reset - @ReadWrite(bits: 11..<12) - public var wwdgrst: WWDGRST - - /// SPI 2 reset - @ReadWrite(bits: 14..<15) - public var spi2rst: SPI2RST - - /// SPI 3 reset - @ReadWrite(bits: 15..<16) - public var spi3rst: SPI3RST - - /// USART 2 reset - @ReadWrite(bits: 17..<18) - public var usart2rst: USART2RST - - /// USART 3 reset - @ReadWrite(bits: 18..<19) - public var usart3rst: USART3RST - - /// USART 4 reset - @ReadWrite(bits: 19..<20) - public var uart4rst: UART4RST - - /// USART 5 reset - @ReadWrite(bits: 20..<21) - public var uart5rst: UART5RST - - /// I2C 1 reset - @ReadWrite(bits: 21..<22) - public var i2c1rst: I2C1RST - - /// I2C 2 reset - @ReadWrite(bits: 22..<23) - public var i2c2rst: I2C2RST - - /// I2C3 reset - @ReadWrite(bits: 23..<24) - public var i2c3rst: I2C3RST - - /// CAN1 reset - @ReadWrite(bits: 25..<26) - public var can1rst: CAN1RST - - /// CAN2 reset - @ReadWrite(bits: 26..<27) - public var can2rst: CAN2RST - - /// Power interface reset - @ReadWrite(bits: 28..<29) - public var pwrrst: PWRRST - - /// DAC reset - @ReadWrite(bits: 29..<30) - public var dacrst: DACRST - - /// UART7 reset - @ReadWrite(bits: 30..<31) - public var uart7rst: UART7RST - - /// UART8 reset - @ReadWrite(bits: 31..<32) - public var uart8rst: UART8RST - - /// SPDIF-RX reset - @ReadWrite(bits: 16..<17) - public var spdifrxrst: SPDIFRXRST - - /// HDMI-CEC reset - @ReadWrite(bits: 27..<28) - public var cecrst: CECRST - - /// Low power timer 1 reset - @ReadWrite(bits: 9..<10) - public var lptim1rst: LPTIM1RST - - /// I2C 4 reset - @ReadWrite(bits: 24..<25) - public var i2c4rst: I2C4RST - } - - /// APB2 peripheral reset register - @Register(bitWidth: 32) - public struct APB2RSTR { - /// TIM1 reset - @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) - public var tim1rst: TIM1RST - - /// TIM8 reset - @ReadWrite(bits: 1..<2) - public var tim8rst: TIM8RST - - /// USART1 reset - @ReadWrite(bits: 4..<5) - public var usart1rst: USART1RST - - /// USART6 reset - @ReadWrite(bits: 5..<6) - public var usart6rst: USART6RST - - /// ADC interface reset (common to all ADCs) - @ReadWrite(bits: 8..<9) - public var adcrst: ADCRST - - /// SPI 1 reset - @ReadWrite(bits: 12..<13) - public var spi1rst: SPI1RST - - /// SPI4 reset - @ReadWrite(bits: 13..<14) - public var spi4rst: SPI4RST - - /// System configuration controller reset - @ReadWrite(bits: 14..<15) - public var syscfgrst: SYSCFGRST - - /// TIM9 reset - @ReadWrite(bits: 16..<17) - public var tim9rst: TIM9RST - - /// TIM10 reset - @ReadWrite(bits: 17..<18) - public var tim10rst: TIM10RST - - /// TIM11 reset - @ReadWrite(bits: 18..<19) - public var tim11rst: TIM11RST - - /// SPI5 reset - @ReadWrite(bits: 20..<21) - public var spi5rst: SPI5RST - - /// SPI6 reset - @ReadWrite(bits: 21..<22) - public var spi6rst: SPI6RST - - /// SAI1 reset - @ReadWrite(bits: 22..<23) - public var sai1rst: SAI1RST - - /// LTDC reset - @ReadWrite(bits: 26..<27) - public var ltdcrst: LTDCRST - - /// SAI2 reset - @ReadWrite(bits: 23..<24) - public var sai2rst: SAI2RST - - /// SDMMC1 reset - @ReadWrite(bits: 11..<12) - public var sdmmc1rst: SDMMC1RST - } - - /// AHB1 peripheral clock register - @Register(bitWidth: 32) - public struct AHB1ENR { - /// USB OTG HSULPI clock enable - @ReadWrite(bits: 30..<31) - public var otghsulpien: OTGHSULPIEN - - /// USB OTG HS clock enable - @ReadWrite(bits: 29..<30) - public var otghsen: OTGHSEN - - /// Ethernet PTP clock enable - @ReadWrite(bits: 28..<29) - public var ethmacptpen: ETHMACPTPEN - - /// Ethernet Reception clock enable - @ReadWrite(bits: 27..<28) - public var ethmacrxen: ETHMACRXEN - - /// Ethernet Transmission clock enable - @ReadWrite(bits: 26..<27) - public var ethmactxen: ETHMACTXEN - - /// Ethernet MAC clock enable - @ReadWrite(bits: 25..<26) - public var ethmacen: ETHMACEN - - /// DMA2D clock enable - @ReadWrite(bits: 23..<24) - public var dma2den: DMA2DEN - - /// DMA2 clock enable - @ReadWrite(bits: 22..<23) - public var dma2en: DMA2EN - - /// DMA1 clock enable - @ReadWrite(bits: 21..<22) - public var dma1en: DMA1EN - - /// CCM data RAM clock enable - @ReadWrite(bits: 20..<21) - public var dtcmramen: DTCMRAMEN - - /// Backup SRAM interface clock enable - @ReadWrite(bits: 18..<19) - public var bkpsramen: BKPSRAMEN - - /// CRC clock enable - @ReadWrite(bits: 12..<13) - public var crcen: CRCEN - - /// IO port K clock enable - @ReadWrite(bits: 10..<11) - public var gpioken: GPIOKEN - - /// IO port J clock enable - @ReadWrite(bits: 9..<10) - public var gpiojen: GPIOJEN - - /// IO port I clock enable - @ReadWrite(bits: 8..<9) - public var gpioien: GPIOIEN - - /// IO port H clock enable - @ReadWrite(bits: 7..<8) - public var gpiohen: GPIOHEN - - /// IO port G clock enable - @ReadWrite(bits: 6..<7) - public var gpiogen: GPIOGEN - - /// IO port F clock enable - @ReadWrite(bits: 5..<6) - public var gpiofen: GPIOFEN - - /// IO port E clock enable - @ReadWrite(bits: 4..<5) - public var gpioeen: GPIOEEN - - /// IO port D clock enable - @ReadWrite(bits: 3..<4) - public var gpioden: GPIODEN - - /// IO port C clock enable - @ReadWrite(bits: 2..<3) - public var gpiocen: GPIOCEN - - /// IO port B clock enable - @ReadWrite(bits: 1..<2) - public var gpioben: GPIOBEN - - /// IO port A clock enable - @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) - public var gpioaen: GPIOAEN - } - - /// AHB2 peripheral clock enable register - @Register(bitWidth: 32) - public struct AHB2ENR { - /// USB OTG FS clock enable - @ReadWrite(bits: 7..<8) - public var otgfsen: OTGFSEN - - /// Random number generator clock enable - @ReadWrite(bits: 6..<7) - public var rngen: RNGEN - - /// Hash modules clock enable - @ReadWrite(bits: 5..<6) - public var hashen: HASHEN - - /// Cryptographic modules clock enable - @ReadWrite(bits: 4..<5) - public var crypen: CRYPEN - - /// Camera interface enable - @ReadWrite(bits: 0..<1, as: DCMIENValues.self) - public var dcmien: DCMIEN - } - - /// AHB3 peripheral clock enable register - @Register(bitWidth: 32) - public struct AHB3ENR { - /// Flexible memory controller module clock enable - @ReadWrite(bits: 0..<1, as: FMCENValues.self) - public var fmcen: FMCEN - - /// Quad SPI memory controller clock enable - @ReadWrite(bits: 1..<2) - public var qspien: QSPIEN - } - - /// APB1 peripheral clock enable register - @Register(bitWidth: 32) - public struct APB1ENR { - /// TIM2 clock enable - @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) - public var tim2en: TIM2EN - - /// TIM3 clock enable - @ReadWrite(bits: 1..<2) - public var tim3en: TIM3EN - - /// TIM4 clock enable - @ReadWrite(bits: 2..<3) - public var tim4en: TIM4EN - - /// TIM5 clock enable - @ReadWrite(bits: 3..<4) - public var tim5en: TIM5EN - - /// TIM6 clock enable - @ReadWrite(bits: 4..<5) - public var tim6en: TIM6EN - - /// TIM7 clock enable - @ReadWrite(bits: 5..<6) - public var tim7en: TIM7EN - - /// TIM12 clock enable - @ReadWrite(bits: 6..<7) - public var tim12en: TIM12EN - - /// TIM13 clock enable - @ReadWrite(bits: 7..<8) - public var tim13en: TIM13EN - - /// TIM14 clock enable - @ReadWrite(bits: 8..<9) - public var tim14en: TIM14EN - - /// Window watchdog clock enable - @ReadWrite(bits: 11..<12) - public var wwdgen: WWDGEN - - /// SPI2 clock enable - @ReadWrite(bits: 14..<15) - public var spi2en: SPI2EN - - /// SPI3 clock enable - @ReadWrite(bits: 15..<16) - public var spi3en: SPI3EN - - /// USART 2 clock enable - @ReadWrite(bits: 17..<18) - public var usart2en: USART2EN - - /// USART3 clock enable - @ReadWrite(bits: 18..<19) - public var usart3en: USART3EN - - /// UART4 clock enable - @ReadWrite(bits: 19..<20) - public var uart4en: UART4EN - - /// UART5 clock enable - @ReadWrite(bits: 20..<21) - public var uart5en: UART5EN - - /// I2C1 clock enable - @ReadWrite(bits: 21..<22) - public var i2c1en: I2C1EN - - /// I2C2 clock enable - @ReadWrite(bits: 22..<23) - public var i2c2en: I2C2EN - - /// I2C3 clock enable - @ReadWrite(bits: 23..<24) - public var i2c3en: I2C3EN - - /// CAN 1 clock enable - @ReadWrite(bits: 25..<26) - public var can1en: CAN1EN - - /// CAN 2 clock enable - @ReadWrite(bits: 26..<27) - public var can2en: CAN2EN - - /// Power interface clock enable - @ReadWrite(bits: 28..<29) - public var pwren: PWREN - - /// DAC interface clock enable - @ReadWrite(bits: 29..<30) - public var dacen: DACEN - - /// UART7 clock enable - @ReadWrite(bits: 30..<31) - public var uart7en: UART7EN - - /// UART8 clock enable - @ReadWrite(bits: 31..<32) - public var uart8en: UART8EN - - /// SPDIF-RX clock enable - @ReadWrite(bits: 16..<17) - public var spdifrxen: SPDIFRXEN - - /// HDMI-CEN clock enable - @ReadWrite(bits: 27..<28) - public var cecen: CECEN - - /// Low power timer 1 clock enable - @ReadWrite(bits: 9..<10) - public var lptim1en: LPTIM1EN - - /// I2C4 clock enable - @ReadWrite(bits: 24..<25) - public var i2c4en: I2C4EN - } - - /// APB2 peripheral clock enable register - @Register(bitWidth: 32) - public struct APB2ENR { - /// TIM1 clock enable - @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) - public var tim1en: TIM1EN - - /// TIM8 clock enable - @ReadWrite(bits: 1..<2) - public var tim8en: TIM8EN - - /// USART1 clock enable - @ReadWrite(bits: 4..<5) - public var usart1en: USART1EN - - /// USART6 clock enable - @ReadWrite(bits: 5..<6) - public var usart6en: USART6EN - - /// ADC1 clock enable - @ReadWrite(bits: 8..<9) - public var adc1en: ADC1EN - - /// ADC2 clock enable - @ReadWrite(bits: 9..<10) - public var adc2en: ADC2EN - - /// ADC3 clock enable - @ReadWrite(bits: 10..<11) - public var adc3en: ADC3EN - - /// SPI1 clock enable - @ReadWrite(bits: 12..<13) - public var spi1en: SPI1EN - - /// SPI4 clock enable - @ReadWrite(bits: 13..<14) - public var spi4en: SPI4EN - - /// System configuration controller clock enable - @ReadWrite(bits: 14..<15) - public var syscfgen: SYSCFGEN - - /// TIM9 clock enable - @ReadWrite(bits: 16..<17) - public var tim9en: TIM9EN - - /// TIM10 clock enable - @ReadWrite(bits: 17..<18) - public var tim10en: TIM10EN - - /// TIM11 clock enable - @ReadWrite(bits: 18..<19) - public var tim11en: TIM11EN - - /// SPI5 clock enable - @ReadWrite(bits: 20..<21) - public var spi5en: SPI5EN - - /// SPI6 clock enable - @ReadWrite(bits: 21..<22) - public var spi6en: SPI6EN - - /// SAI1 clock enable - @ReadWrite(bits: 22..<23) - public var sai1en: SAI1EN - - /// LTDC clock enable - @ReadWrite(bits: 26..<27) - public var ltdcen: LTDCEN - - /// SAI2 clock enable - @ReadWrite(bits: 23..<24) - public var sai2en: SAI2EN - - /// SDMMC1 clock enable - @ReadWrite(bits: 11..<12) - public var sdmmc1en: SDMMC1EN - } - - /// AHB1 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB1LPENR { - /// IO port A clock enable during sleep mode - @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) - public var gpioalpen: GPIOALPEN - - /// IO port B clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var gpioblpen: GPIOBLPEN - - /// IO port C clock enable during Sleep mode - @ReadWrite(bits: 2..<3) - public var gpioclpen: GPIOCLPEN - - /// IO port D clock enable during Sleep mode - @ReadWrite(bits: 3..<4) - public var gpiodlpen: GPIODLPEN - - /// IO port E clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var gpioelpen: GPIOELPEN - - /// IO port F clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var gpioflpen: GPIOFLPEN - - /// IO port G clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var gpioglpen: GPIOGLPEN - - /// IO port H clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var gpiohlpen: GPIOHLPEN - - /// IO port I clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var gpioilpen: GPIOILPEN - - /// IO port J clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var gpiojlpen: GPIOJLPEN - - /// IO port K clock enable during Sleep mode - @ReadWrite(bits: 10..<11) - public var gpioklpen: GPIOKLPEN - - /// CRC clock enable during Sleep mode - @ReadWrite(bits: 12..<13) - public var crclpen: CRCLPEN - - /// Flash interface clock enable during Sleep mode - @ReadWrite(bits: 15..<16) - public var flitflpen: FLITFLPEN - - /// SRAM 1interface clock enable during Sleep mode - @ReadWrite(bits: 16..<17) - public var sram1lpen: SRAM1LPEN - - /// SRAM 2 interface clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var sram2lpen: SRAM2LPEN - - /// Backup SRAM interface clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var bkpsramlpen: BKPSRAMLPEN - - /// SRAM 3 interface clock enable during Sleep mode - @ReadWrite(bits: 19..<20) - public var sram3lpen: SRAM3LPEN - - /// DMA1 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var dma1lpen: DMA1LPEN - - /// DMA2 clock enable during Sleep mode - @ReadWrite(bits: 22..<23) - public var dma2lpen: DMA2LPEN - - /// DMA2D clock enable during Sleep mode - @ReadWrite(bits: 23..<24) - public var dma2dlpen: DMA2DLPEN - - /// Ethernet MAC clock enable during Sleep mode - @ReadWrite(bits: 25..<26) - public var ethmaclpen: ETHMACLPEN - - /// Ethernet transmission clock enable during Sleep mode - @ReadWrite(bits: 26..<27) - public var ethmactxlpen: ETHMACTXLPEN - - /// Ethernet reception clock enable during Sleep mode - @ReadWrite(bits: 27..<28) - public var ethmacrxlpen: ETHMACRXLPEN - - /// Ethernet PTP clock enable during Sleep mode - @ReadWrite(bits: 28..<29) - public var ethmacptplpen: ETHMACPTPLPEN - - /// USB OTG HS clock enable during Sleep mode - @ReadWrite(bits: 29..<30) - public var otghslpen: OTGHSLPEN - - /// USB OTG HS ULPI clock enable during Sleep mode - @ReadWrite(bits: 30..<31) - public var otghsulpilpen: OTGHSULPILPEN - - /// AXI to AHB bridge clock enable during Sleep mode - @ReadWrite(bits: 13..<14) - public var axilpen: AXILPEN - - /// DTCM RAM interface clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var dtcmlpen: DTCMLPEN - } - - /// AHB2 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB2LPENR { - /// USB OTG FS clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var otgfslpen: OTGFSLPEN - - /// Random number generator clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var rnglpen: RNGLPEN - - /// Hash modules clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var hashlpen: HASHLPEN - - /// Cryptography modules clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var cryplpen: CRYPLPEN - - /// Camera interface enable during Sleep mode - @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) - public var dcmilpen: DCMILPEN - } - - /// AHB3 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB3LPENR { - /// Flexible memory controller module clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) - public var fmclpen: FMCLPEN - - /// Quand SPI memory controller clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var qspilpen: QSPILPEN - } - - /// APB1 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct APB1LPENR { - /// TIM2 clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) - public var tim2lpen: TIM2LPEN - - /// TIM3 clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var tim3lpen: TIM3LPEN - - /// TIM4 clock enable during Sleep mode - @ReadWrite(bits: 2..<3) - public var tim4lpen: TIM4LPEN - - /// TIM5 clock enable during Sleep mode - @ReadWrite(bits: 3..<4) - public var tim5lpen: TIM5LPEN - - /// TIM6 clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var tim6lpen: TIM6LPEN - - /// TIM7 clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var tim7lpen: TIM7LPEN - - /// TIM12 clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var tim12lpen: TIM12LPEN - - /// TIM13 clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var tim13lpen: TIM13LPEN - - /// TIM14 clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var tim14lpen: TIM14LPEN - - /// Window watchdog clock enable during Sleep mode - @ReadWrite(bits: 11..<12) - public var wwdglpen: WWDGLPEN - - /// SPI2 clock enable during Sleep mode - @ReadWrite(bits: 14..<15) - public var spi2lpen: SPI2LPEN - - /// SPI3 clock enable during Sleep mode - @ReadWrite(bits: 15..<16) - public var spi3lpen: SPI3LPEN - - /// USART2 clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var usart2lpen: USART2LPEN - - /// USART3 clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var usart3lpen: USART3LPEN - - /// UART4 clock enable during Sleep mode - @ReadWrite(bits: 19..<20) - public var uart4lpen: UART4LPEN - - /// UART5 clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var uart5lpen: UART5LPEN - - /// I2C1 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var i2c1lpen: I2C1LPEN - - /// I2C2 clock enable during Sleep mode - @ReadWrite(bits: 22..<23) - public var i2c2lpen: I2C2LPEN - - /// I2C3 clock enable during Sleep mode - @ReadWrite(bits: 23..<24) - public var i2c3lpen: I2C3LPEN - - /// CAN 1 clock enable during Sleep mode - @ReadWrite(bits: 25..<26) - public var can1lpen: CAN1LPEN - - /// CAN 2 clock enable during Sleep mode - @ReadWrite(bits: 26..<27) - public var can2lpen: CAN2LPEN - - /// Power interface clock enable during Sleep mode - @ReadWrite(bits: 28..<29) - public var pwrlpen: PWRLPEN - - /// DAC interface clock enable during Sleep mode - @ReadWrite(bits: 29..<30) - public var daclpen: DACLPEN - - /// UART7 clock enable during Sleep mode - @ReadWrite(bits: 30..<31) - public var uart7lpen: UART7LPEN - - /// UART8 clock enable during Sleep mode - @ReadWrite(bits: 31..<32) - public var uart8lpen: UART8LPEN - - /// SPDIF-RX clock enable during sleep mode - @ReadWrite(bits: 16..<17) - public var spdifrxlpen: SPDIFRXLPEN - - /// HDMI-CEN clock enable during Sleep mode - @ReadWrite(bits: 27..<28) - public var ceclpen: CECLPEN - - /// low power timer 1 clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var lptim1lpen: LPTIM1LPEN - - /// I2C4 clock enable during Sleep mode - @ReadWrite(bits: 24..<25) - public var i2c4lpen: I2C4LPEN - } - - /// APB2 peripheral clock enabled in low power mode register - @Register(bitWidth: 32) - public struct APB2LPENR { - /// TIM1 clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) - public var tim1lpen: TIM1LPEN - - /// TIM8 clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var tim8lpen: TIM8LPEN - - /// USART1 clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var usart1lpen: USART1LPEN - - /// USART6 clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var usart6lpen: USART6LPEN - - /// ADC1 clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var adc1lpen: ADC1LPEN - - /// ADC2 clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var adc2lpen: ADC2LPEN - - /// ADC 3 clock enable during Sleep mode - @ReadWrite(bits: 10..<11) - public var adc3lpen: ADC3LPEN - - /// SPI 1 clock enable during Sleep mode - @ReadWrite(bits: 12..<13) - public var spi1lpen: SPI1LPEN - - /// SPI 4 clock enable during Sleep mode - @ReadWrite(bits: 13..<14) - public var spi4lpen: SPI4LPEN - - /// System configuration controller clock enable during Sleep mode - @ReadWrite(bits: 14..<15) - public var syscfglpen: SYSCFGLPEN - - /// TIM9 clock enable during sleep mode - @ReadWrite(bits: 16..<17) - public var tim9lpen: TIM9LPEN - - /// TIM10 clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var tim10lpen: TIM10LPEN - - /// TIM11 clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var tim11lpen: TIM11LPEN - - /// SPI 5 clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var spi5lpen: SPI5LPEN - - /// SPI 6 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var spi6lpen: SPI6LPEN - - /// SAI1 clock enable during sleep mode - @ReadWrite(bits: 22..<23) - public var sai1lpen: SAI1LPEN - - /// LTDC clock enable during sleep mode - @ReadWrite(bits: 26..<27) - public var ltdclpen: LTDCLPEN - - /// SAI2 clock enable during sleep mode - @ReadWrite(bits: 23..<24) - public var sai2lpen: SAI2LPEN - - /// SDMMC1 clock enable during Sleep mode - @ReadWrite(bits: 11..<12) - public var sdmmc1lpen: SDMMC1LPEN - } - - /// Backup domain control register - @Register(bitWidth: 32) - public struct BDCR { - /// Backup domain software reset - @ReadWrite(bits: 16..<17, as: BDRSTValues.self) - public var bdrst: BDRST - - /// RTC clock enable - @ReadWrite(bits: 15..<16, as: RTCENValues.self) - public var rtcen: RTCEN - - /// External low-speed oscillator bypass - @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) - public var lsebyp: LSEBYP - - /// External low-speed oscillator ready - @ReadOnly(bits: 1..<2) - public var lserdy: LSERDY - - /// External low-speed oscillator enable - @ReadWrite(bits: 0..<1, as: LSEONValues.self) - public var lseon: LSEON - - /// LSE oscillator drive capability - @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) - public var lsedrv: LSEDRV - - /// RTC clock source selection - @Reserved(bits: 8..<10, as: RTCSELValues.self) - public var rtcsel: RTCSEL - } - - /// clock control & status register - @Register(bitWidth: 32) - public struct CSR { - /// Low-power reset flag - @ReadWrite(bits: 31..<32) - public var lpwrrstf: LPWRRSTF - - /// Window watchdog reset flag - @ReadWrite(bits: 30..<31) - public var wwdgrstf: WWDGRSTF - - /// Independent watchdog reset flag - @ReadWrite(bits: 29..<30) - public var wdgrstf: WDGRSTF - - /// Software reset flag - @ReadWrite(bits: 28..<29) - public var sftrstf: SFTRSTF - - /// POR/PDR reset flag - @ReadWrite(bits: 27..<28) - public var porrstf: PORRSTF - - /// PIN reset flag - @ReadWrite(bits: 26..<27) - public var padrstf: PADRSTF - - /// BOR reset flag - @ReadWrite(bits: 25..<26) - public var borrstf: BORRSTF - - /// Remove reset flag - @ReadWrite(bits: 24..<25) - public var rmvf: RMVF - - /// Internal low-speed oscillator ready - @ReadOnly(bits: 1..<2) - public var lsirdy: LSIRDY - - /// Internal low-speed oscillator enable - @ReadWrite(bits: 0..<1, as: LSIONValues.self) - public var lsion: LSION - } - - /// spread spectrum clock generation register - @Register(bitWidth: 32) - public struct SSCGR { - /// Spread spectrum modulation enable - @ReadWrite(bits: 31..<32, as: SSCGENValues.self) - public var sscgen: SSCGEN - - /// Spread Select - @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) - public var spreadsel: SPREADSEL - - /// Incrementation step - @ReadWrite(bits: 13..<28) - public var incstep: INCSTEP - - /// Modulation period - @ReadWrite(bits: 0..<13) - public var modper: MODPER - } - - /// PLLI2S configuration register - @Register(bitWidth: 32) - public struct PLLI2SCFGR { - /// PLLI2S division factor for I2S clocks - @ReadWrite(bits: 28..<31) - public var plli2sr: PLLI2SR - - /// PLLI2S division factor for SAI1 clock - @ReadWrite(bits: 24..<28) - public var plli2sq: PLLI2SQ - - /// PLLI2S multiplication factor for VCO - @ReadWrite(bits: 6..<15) - public var plli2sn: PLLI2SN - - /// PLLI2S division factor for SPDIFRX clock - @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) - public var plli2sp: PLLI2SP - } - - /// PLL configuration register - @Register(bitWidth: 32) - public struct PLLSAICFGR { - /// PLLSAI division factor for VCO - @ReadWrite(bits: 6..<15) - public var pllsain: PLLSAIN - - /// PLLSAI division factor for 48MHz clock - @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) - public var pllsaip: PLLSAIP - - /// PLLSAI division factor for SAI clock - @ReadWrite(bits: 24..<28) - public var pllsaiq: PLLSAIQ - - /// PLLSAI division factor for LCD clock - @ReadWrite(bits: 28..<31) - public var pllsair: PLLSAIR - } - - /// dedicated clocks configuration register - @Register(bitWidth: 32) - public struct DCKCFGR1 { - /// PLLI2S division factor for SAI1 clock - @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) - public var plli2sdivq: PLLI2SDIVQ - - /// PLLSAI division factor for SAI1 clock - @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) - public var pllsaidivq: PLLSAIDIVQ - - /// division factor for LCD_CLK - @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) - public var pllsaidivr: PLLSAIDIVR - - /// SAI1 clock source selection - @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) - public var sai1sel: SAI1SEL - - /// SAI2 clock source selection - @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) - public var sai2sel: SAI2SEL - - /// Timers clocks prescalers selection - @ReadWrite(bits: 24..<25, as: TIMPREValues.self) - public var timpre: TIMPRE - } - - /// dedicated clocks configuration register - @Register(bitWidth: 32) - public struct DCKCFGR2 { - /// USART 1 clock source selection - @ReadWrite(bits: 0..<2, as: USART1SELValues.self) - public var usart1sel: USART1SEL - - /// USART 2 clock source selection - @ReadWrite(bits: 2..<4, as: USART2SELValues.self) - public var usart2sel: USART2SEL - - /// USART 3 clock source selection - @ReadWrite(bits: 4..<6) - public var usart3sel: USART3SEL - - /// UART 4 clock source selection - @ReadWrite(bits: 6..<8) - public var uart4sel: UART4SEL - - /// UART 5 clock source selection - @ReadWrite(bits: 8..<10) - public var uart5sel: UART5SEL - - /// USART 6 clock source selection - @ReadWrite(bits: 10..<12) - public var usart6sel: USART6SEL - - /// UART 7 clock source selection - @ReadWrite(bits: 12..<14) - public var uart7sel: UART7SEL - - /// UART 8 clock source selection - @ReadWrite(bits: 14..<16) - public var uart8sel: UART8SEL - - /// I2C1 clock source selection - @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) - public var i2c1sel: I2C1SEL - - /// I2C2 clock source selection - @ReadWrite(bits: 18..<20) - public var i2c2sel: I2C2SEL - - /// I2C3 clock source selection - @ReadWrite(bits: 20..<22) - public var i2c3sel: I2C3SEL - - /// I2C4 clock source selection - @ReadWrite(bits: 22..<24) - public var i2c4sel: I2C4SEL - - /// Low power timer 1 clock source selection - @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) - public var lptim1sel: LPTIM1SEL - - /// HDMI-CEC clock source selection - @ReadWrite(bits: 26..<27, as: CECSELValues.self) - public var cecsel: CECSEL - - /// 48MHz clock source selection - @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) - public var ck48msel: CK48MSEL - - /// SDMMC clock source selection - @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) - public var sdmmc1sel: SDMMC1SEL - } -} - -extension RCC.CR { - public struct CSSONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Clock security system disabled (clock detector OFF) - public static let Off = Self(rawValue: 0x0) - - /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CR { - public struct HSEBYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// HSE crystal oscillator not bypassed - public static let NotBypassed = Self(rawValue: 0x0) - - /// HSE crystal oscillator bypassed with external clock - public static let Bypassed = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CR { - public struct HSIONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Clock Off - public static let Off = Self(rawValue: 0x0) - - /// Clock On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLCFGR { - public struct PLLSRCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// HSI clock selected as PLL and PLLI2S clock entry - public static let HSI = Self(rawValue: 0x0) - - /// HSE oscillator clock selected as PLL and PLLI2S clock entry - public static let HSE = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLCFGR { - public struct PLLPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLLP=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLLP=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLLP=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLLP=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO2Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// System clock (SYSCLK) selected - public static let SYSCLK = Self(rawValue: 0x0) - - /// PLLI2S clock selected - public static let PLLI2S = Self(rawValue: 0x1) - - /// HSE oscillator clock selected - public static let HSE = Self(rawValue: 0x2) - - /// PLL clock selected - public static let PLL = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO1PREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// No division - public static let Div1 = Self(rawValue: 0x0) - - /// Division by 2 - public static let Div2 = Self(rawValue: 0x4) - - /// Division by 3 - public static let Div3 = Self(rawValue: 0x5) - - /// Division by 4 - public static let Div4 = Self(rawValue: 0x6) - - /// Division by 5 - public static let Div5 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct I2SSRCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// PLLI2S clock used as I2S clock source - public static let PLLI2S = Self(rawValue: 0x0) - - /// External clock mapped on the I2S_CKIN pin used as I2S clock source - public static let CKIN = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// HSI clock selected - public static let HSI = Self(rawValue: 0x0) - - /// LSE oscillator selected - public static let LSE = Self(rawValue: 0x1) - - /// HSE oscillator clock selected - public static let HSE = Self(rawValue: 0x2) - - /// PLL clock selected - public static let PLL = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct PPRE1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// HCLK not divided - public static let Div1 = Self(rawValue: 0x0) - - /// HCLK divided by 2 - public static let Div2 = Self(rawValue: 0x4) - - /// HCLK divided by 4 - public static let Div4 = Self(rawValue: 0x5) - - /// HCLK divided by 8 - public static let Div8 = Self(rawValue: 0x6) - - /// HCLK divided by 16 - public static let Div16 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct HPREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// SYSCLK not divided - public static let Div1 = Self(rawValue: 0x0) - - /// SYSCLK divided by 2 - public static let Div2 = Self(rawValue: 0x8) - - /// SYSCLK divided by 4 - public static let Div4 = Self(rawValue: 0x9) - - /// SYSCLK divided by 8 - public static let Div8 = Self(rawValue: 0xa) - - /// SYSCLK divided by 16 - public static let Div16 = Self(rawValue: 0xb) - - /// SYSCLK divided by 64 - public static let Div64 = Self(rawValue: 0xc) - - /// SYSCLK divided by 128 - public static let Div128 = Self(rawValue: 0xd) - - /// SYSCLK divided by 256 - public static let Div256 = Self(rawValue: 0xe) - - /// SYSCLK divided by 512 - public static let Div512 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct SWValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// HSI selected as system clock - public static let HSI = Self(rawValue: 0x0) - - /// HSE selected as system clock - public static let HSE = Self(rawValue: 0x1) - - /// PLL selected as system clock - public static let PLL = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CIR { - public struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1RSTR { - public struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2RSTR { - public struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3RSTR { - public struct FMCRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1RSTR { - public struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2RSTR { - public struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1ENR { - public struct GPIOAENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2ENR { - public struct DCMIENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3ENR { - public struct FMCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1ENR { - public struct TIM2ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2ENR { - public struct TIM1ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1LPENR { - public struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2LPENR { - public struct DCMILPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3LPENR { - public struct FMCLPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1LPENR { - public struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2LPENR { - public struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct BDRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset not activated - public static let Disabled = Self(rawValue: 0x0) - - /// Reset the entire RTC domain - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct RTCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RTC clock disabled - public static let Disabled = Self(rawValue: 0x0) - - /// RTC clock enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEBYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE crystal oscillator not bypassed - public static let NotBypassed = Self(rawValue: 0x0) - - /// LSE crystal oscillator bypassed with external clock - public static let Bypassed = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE oscillator Off - public static let Off = Self(rawValue: 0x0) - - /// LSE oscillator On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEDRVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Low drive capacity - public static let Low = Self(rawValue: 0x0) - - /// Medium-high drive capacity - public static let MediumHigh = Self(rawValue: 0x1) - - /// Medium-low drive capacity - public static let MediumLow = Self(rawValue: 0x2) - - /// High drive capacity - public static let High = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct RTCSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// No clock - public static let NoClock = Self(rawValue: 0x0) - - /// LSE oscillator clock used as RTC clock - public static let LSE = Self(rawValue: 0x1) - - /// LSI oscillator clock used as RTC clock - public static let LSI = Self(rawValue: 0x2) - - /// HSE oscillator clock divided by a prescaler used as RTC clock - public static let HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CSR { - public struct LSIONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSI oscillator Off - public static let Off = Self(rawValue: 0x0) - - /// LSI oscillator On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.SSCGR { - public struct SSCGENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Spread spectrum modulation disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Spread spectrum modulation enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.SSCGR { - public struct SPREADSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Center spread - public static let Center = Self(rawValue: 0x0) - - /// Down spread - public static let Down = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLI2SCFGR { - public struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLL*P=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLL*P=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLL*P=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLL*P=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLSAICFGR { - public struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLL*P=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLL*P=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLL*P=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLL*P=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 5 - - /// PLLI2SDIVQ = /1 - public static let Div1 = Self(rawValue: 0x0) - - /// PLLI2SDIVQ = /2 - public static let Div2 = Self(rawValue: 0x1) - - /// PLLI2SDIVQ = /3 - public static let Div3 = Self(rawValue: 0x2) - - /// PLLI2SDIVQ = /4 - public static let Div4 = Self(rawValue: 0x3) - - /// PLLI2SDIVQ = /5 - public static let Div5 = Self(rawValue: 0x4) - - /// PLLI2SDIVQ = /6 - public static let Div6 = Self(rawValue: 0x5) - - /// PLLI2SDIVQ = /7 - public static let Div7 = Self(rawValue: 0x6) - - /// PLLI2SDIVQ = /8 - public static let Div8 = Self(rawValue: 0x7) - - /// PLLI2SDIVQ = /9 - public static let Div9 = Self(rawValue: 0x8) - - /// PLLI2SDIVQ = /10 - public static let Div10 = Self(rawValue: 0x9) - - /// PLLI2SDIVQ = /11 - public static let Div11 = Self(rawValue: 0xa) - - /// PLLI2SDIVQ = /12 - public static let Div12 = Self(rawValue: 0xb) - - /// PLLI2SDIVQ = /13 - public static let Div13 = Self(rawValue: 0xc) - - /// PLLI2SDIVQ = /14 - public static let Div14 = Self(rawValue: 0xd) - - /// PLLI2SDIVQ = /15 - public static let Div15 = Self(rawValue: 0xe) - - /// PLLI2SDIVQ = /16 - public static let Div16 = Self(rawValue: 0xf) - - /// PLLI2SDIVQ = /17 - public static let Div17 = Self(rawValue: 0x10) - - /// PLLI2SDIVQ = /18 - public static let Div18 = Self(rawValue: 0x11) - - /// PLLI2SDIVQ = /19 - public static let Div19 = Self(rawValue: 0x12) - - /// PLLI2SDIVQ = /20 - public static let Div20 = Self(rawValue: 0x13) - - /// PLLI2SDIVQ = /21 - public static let Div21 = Self(rawValue: 0x14) - - /// PLLI2SDIVQ = /22 - public static let Div22 = Self(rawValue: 0x15) - - /// PLLI2SDIVQ = /23 - public static let Div23 = Self(rawValue: 0x16) - - /// PLLI2SDIVQ = /24 - public static let Div24 = Self(rawValue: 0x17) - - /// PLLI2SDIVQ = /25 - public static let Div25 = Self(rawValue: 0x18) - - /// PLLI2SDIVQ = /26 - public static let Div26 = Self(rawValue: 0x19) - - /// PLLI2SDIVQ = /27 - public static let Div27 = Self(rawValue: 0x1a) - - /// PLLI2SDIVQ = /28 - public static let Div28 = Self(rawValue: 0x1b) - - /// PLLI2SDIVQ = /29 - public static let Div29 = Self(rawValue: 0x1c) - - /// PLLI2SDIVQ = /30 - public static let Div30 = Self(rawValue: 0x1d) - - /// PLLI2SDIVQ = /31 - public static let Div31 = Self(rawValue: 0x1e) - - /// PLLI2SDIVQ = /32 - public static let Div32 = Self(rawValue: 0x1f) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 5 - - /// PLLSAIDIVQ = /1 - public static let Div1 = Self(rawValue: 0x0) - - /// PLLSAIDIVQ = /2 - public static let Div2 = Self(rawValue: 0x1) - - /// PLLSAIDIVQ = /3 - public static let Div3 = Self(rawValue: 0x2) - - /// PLLSAIDIVQ = /4 - public static let Div4 = Self(rawValue: 0x3) - - /// PLLSAIDIVQ = /5 - public static let Div5 = Self(rawValue: 0x4) - - /// PLLSAIDIVQ = /6 - public static let Div6 = Self(rawValue: 0x5) - - /// PLLSAIDIVQ = /7 - public static let Div7 = Self(rawValue: 0x6) - - /// PLLSAIDIVQ = /8 - public static let Div8 = Self(rawValue: 0x7) - - /// PLLSAIDIVQ = /9 - public static let Div9 = Self(rawValue: 0x8) - - /// PLLSAIDIVQ = /10 - public static let Div10 = Self(rawValue: 0x9) - - /// PLLSAIDIVQ = /11 - public static let Div11 = Self(rawValue: 0xa) - - /// PLLSAIDIVQ = /12 - public static let Div12 = Self(rawValue: 0xb) - - /// PLLSAIDIVQ = /13 - public static let Div13 = Self(rawValue: 0xc) - - /// PLLSAIDIVQ = /14 - public static let Div14 = Self(rawValue: 0xd) - - /// PLLSAIDIVQ = /15 - public static let Div15 = Self(rawValue: 0xe) - - /// PLLSAIDIVQ = /16 - public static let Div16 = Self(rawValue: 0xf) - - /// PLLSAIDIVQ = /17 - public static let Div17 = Self(rawValue: 0x10) - - /// PLLSAIDIVQ = /18 - public static let Div18 = Self(rawValue: 0x11) - - /// PLLSAIDIVQ = /19 - public static let Div19 = Self(rawValue: 0x12) - - /// PLLSAIDIVQ = /20 - public static let Div20 = Self(rawValue: 0x13) - - /// PLLSAIDIVQ = /21 - public static let Div21 = Self(rawValue: 0x14) - - /// PLLSAIDIVQ = /22 - public static let Div22 = Self(rawValue: 0x15) - - /// PLLSAIDIVQ = /23 - public static let Div23 = Self(rawValue: 0x16) - - /// PLLSAIDIVQ = /24 - public static let Div24 = Self(rawValue: 0x17) - - /// PLLSAIDIVQ = /25 - public static let Div25 = Self(rawValue: 0x18) - - /// PLLSAIDIVQ = /26 - public static let Div26 = Self(rawValue: 0x19) - - /// PLLSAIDIVQ = /27 - public static let Div27 = Self(rawValue: 0x1a) - - /// PLLSAIDIVQ = /28 - public static let Div28 = Self(rawValue: 0x1b) - - /// PLLSAIDIVQ = /29 - public static let Div29 = Self(rawValue: 0x1c) - - /// PLLSAIDIVQ = /30 - public static let Div30 = Self(rawValue: 0x1d) - - /// PLLSAIDIVQ = /31 - public static let Div31 = Self(rawValue: 0x1e) - - /// PLLSAIDIVQ = /32 - public static let Div32 = Self(rawValue: 0x1f) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLLSAIDIVR = /2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLLSAIDIVR = /4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLLSAIDIVR = /8 - public static let Div8 = Self(rawValue: 0x2) - - /// PLLSAIDIVR = /16 - public static let Div16 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct SAI1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - public static let PLLSAI = Self(rawValue: 0x0) - - /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - public static let PLLI2S = Self(rawValue: 0x1) - - /// SAI1 clock frequency = Alternate function input frequency - public static let AFIF = Self(rawValue: 0x2) - - /// SAI1 clock frequency = HSI or HSE - public static let HSI_HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct SAI2SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - public static let PLLSAI = Self(rawValue: 0x0) - - /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - public static let PLLI2S = Self(rawValue: 0x1) - - /// SAI2 clock frequency = Alternate function input frequency - public static let AFIF = Self(rawValue: 0x2) - - /// SAI2 clock frequency = HSI or HSE - public static let HSI_HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct TIMPREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - public static let Mul1Or2 = Self(rawValue: 0x0) - - /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - public static let Mul1Or4 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct USART1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB2 clock (PCLK2) is selected as USART clock - public static let APB2 = Self(rawValue: 0x0) - - /// System clock is selected as USART clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock is selected as USART clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as USART clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct USART2SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB1 clock (PCLK1) is selected as USART clock - public static let APB1 = Self(rawValue: 0x0) - - /// System clock is selected as USART clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock is selected as USART clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as USART clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct I2C1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB clock selected as I2C clock - public static let APB = Self(rawValue: 0x0) - - /// System clock selected as I2C clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock selected as I2C clock - public static let HSI = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB1 clock (PCLK1) selected as LPTILM1 clock - public static let APB1 = Self(rawValue: 0x0) - - /// LSI clock is selected as LPTILM1 clock - public static let LSI = Self(rawValue: 0x1) - - /// HSI clock is selected as LPTILM1 clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as LPTILM1 clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct CECSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE clock is selected as HDMI-CEC clock - public static let LSE = Self(rawValue: 0x0) - - /// HSI divided by 488 clock is selected as HDMI-CEC clock - public static let HSI_Div488 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct CK48MSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 48MHz clock from PLL is selected - public static let PLL = Self(rawValue: 0x0) - - /// 48MHz clock from PLLSAI is selected - public static let PLLSAI = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 48 MHz clock is selected as SD clock - public static let CK48M = Self(rawValue: 0x0) - - /// System clock is selected as SD clock - public static let SYSCLK = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lvgl/Sources/Registers/SCB.swift b/stm32-lvgl/Sources/Registers/SCB.swift deleted file mode 100644 index 08a12aeb..00000000 --- a/stm32-lvgl/Sources/Registers/SCB.swift +++ /dev/null @@ -1,429 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// System control block -@RegisterBlock -public struct SCB { - /// CPUID base register - @RegisterBlock(offset: 0x0) - public var cpuid: Register - - /// Interrupt control and state register - @RegisterBlock(offset: 0x4) - public var icsr: Register - - /// Vector table offset register - @RegisterBlock(offset: 0x8) - public var vtor: Register - - /// Application interrupt and reset control register - @RegisterBlock(offset: 0xc) - public var aircr: Register - - /// System control register - @RegisterBlock(offset: 0x10) - public var scr: Register - - /// Configuration and control register - @RegisterBlock(offset: 0x14) - public var ccr: Register - - /// System handler priority registers - @RegisterBlock(offset: 0x18) - public var shpr1: Register - - /// System handler priority registers - @RegisterBlock(offset: 0x1c) - public var shpr2: Register - - /// System handler priority registers - @RegisterBlock(offset: 0x20) - public var shpr3: Register - - /// System handler control and state register - @RegisterBlock(offset: 0x24) - public var shcrs: Register - - /// Configurable fault status register - @RegisterBlock(offset: 0x28) - public var cfsr_ufsr_bfsr_mmfsr: Register - - /// Hard fault status register - @RegisterBlock(offset: 0x2c) - public var hfsr: Register - - /// Memory management fault address register - @RegisterBlock(offset: 0x34) - public var mmfar: Register - - /// Bus fault address register - @RegisterBlock(offset: 0x38) - public var bfar: Register -} - -extension SCB { - /// CPUID base register - @Register(bitWidth: 32) - public struct CPUID { - /// Revision number - @ReadOnly(bits: 0..<4) - public var revision: Revision - - /// Part number of the processor - @ReadOnly(bits: 4..<16) - public var partno: PartNo - - /// Reads as 0xF - @ReadOnly(bits: 16..<20) - public var constant: Constant - - /// Variant number - @ReadOnly(bits: 20..<24) - public var variant: Variant - - /// Implementer code - @ReadOnly(bits: 24..<32) - public var implementer: Implementer - } - - /// Interrupt control and state register - @Register(bitWidth: 32) - public struct ICSR { - /// Active vector - @ReadWrite(bits: 0..<9) - public var vectactive: VECTACTIVE - - /// Return to base level - @ReadWrite(bits: 11..<12) - public var rettobase: RETTOBASE - - /// Pending vector - @ReadWrite(bits: 12..<19) - public var vectpending: VECTPENDING - - /// Interrupt pending flag - @ReadWrite(bits: 22..<23) - public var isrpending: ISRPENDING - - /// SysTick exception clear-pending bit - @ReadWrite(bits: 25..<26) - public var pendstclr: PENDSTCLR - - /// SysTick exception set-pending bit - @ReadWrite(bits: 26..<27) - public var pendstset: PENDSTSET - - /// PendSV clear-pending bit - @ReadWrite(bits: 27..<28) - public var pendsvclr: PENDSVCLR - - /// PendSV set-pending bit - @ReadWrite(bits: 28..<29) - public var pendsvset: PENDSVSET - - /// NMI set-pending bit. - @ReadWrite(bits: 31..<32) - public var nmipendset: NMIPENDSET - } - - /// Vector table offset register - @Register(bitWidth: 32) - public struct VTOR { - /// Vector table base offset field - @ReadWrite(bits: 9..<30) - public var tbloff: TBLOFF - } - - /// Application interrupt and reset control register - @Register(bitWidth: 32) - public struct AIRCR { - /// VECTRESET - @ReadWrite(bits: 0..<1) - public var vectreset: VECTRESET - - /// VECTCLRACTIVE - @ReadWrite(bits: 1..<2) - public var vectclractive: VECTCLRACTIVE - - /// SYSRESETREQ - @ReadWrite(bits: 2..<3) - public var sysresetreq: SYSRESETREQ - - /// PRIGROUP - @ReadWrite(bits: 8..<11) - public var prigroup: PRIGROUP - - /// ENDIANESS - @ReadWrite(bits: 15..<16) - public var endianess: ENDIANESS - - /// Register key - @ReadWrite(bits: 16..<32) - public var vectkeystat: VECTKEYSTAT - } - - /// System control register - @Register(bitWidth: 32) - public struct SCR { - /// SLEEPONEXIT - @ReadWrite(bits: 1..<2) - public var sleeponexit: SLEEPONEXIT - - /// SLEEPDEEP - @ReadWrite(bits: 2..<3) - public var sleepdeep: SLEEPDEEP - - /// Send Event on Pending bit - @ReadWrite(bits: 4..<5) - public var seveonpend: SEVEONPEND - } - - /// Configuration and control register - @Register(bitWidth: 32) - public struct CCR { - /// Configures how the processor enters Thread mode - @ReadWrite(bits: 0..<1) - public var nonbasethrdena: NONBASETHRDENA - - /// USERSETMPEND - @ReadWrite(bits: 1..<2) - public var usersetmpend: USERSETMPEND - - /// UNALIGN_ TRP - @ReadWrite(bits: 3..<4) - public var unalign__trp: UNALIGN__TRP - - /// DIV_0_TRP - @ReadWrite(bits: 4..<5) - public var div_0_trp: DIV_0_TRP - - /// BFHFNMIGN - @ReadWrite(bits: 8..<9) - public var bfhfnmign: BFHFNMIGN - - /// STKALIGN - @ReadWrite(bits: 9..<10) - public var stkalign: STKALIGN - - /// DC - @ReadWrite(bits: 16..<17) - public var dc: DC - - /// IC - @ReadWrite(bits: 17..<18) - public var ic: IC - - /// BP - @ReadWrite(bits: 18..<19) - public var bp: BP - } - - /// System handler priority registers - @Register(bitWidth: 32) - public struct SHPR1 { - /// Priority of system handler 4 - @ReadWrite(bits: 0..<8) - public var pri_4: PRI_4 - - /// Priority of system handler 5 - @ReadWrite(bits: 8..<16) - public var pri_5: PRI_5 - - /// Priority of system handler 6 - @ReadWrite(bits: 16..<24) - public var pri_6: PRI_6 - } - - /// System handler priority registers - @Register(bitWidth: 32) - public struct SHPR2 { - /// Priority of system handler 11 - @ReadWrite(bits: 24..<32) - public var pri_11: PRI_11 - } - - /// System handler priority registers - @Register(bitWidth: 32) - public struct SHPR3 { - /// Priority of system handler 14 - @ReadWrite(bits: 16..<24) - public var pri_14: PRI_14 - - /// Priority of system handler 15 - @ReadWrite(bits: 24..<32) - public var pri_15: PRI_15 - } - - /// System handler control and state register - @Register(bitWidth: 32) - public struct SHCRS { - /// Memory management fault exception active bit - @ReadWrite(bits: 0..<1) - public var memfaultact: MEMFAULTACT - - /// Bus fault exception active bit - @ReadWrite(bits: 1..<2) - public var busfaultact: BUSFAULTACT - - /// Usage fault exception active bit - @ReadWrite(bits: 3..<4) - public var usgfaultact: USGFAULTACT - - /// SVC call active bit - @ReadWrite(bits: 7..<8) - public var svcallact: SVCALLACT - - /// Debug monitor active bit - @ReadWrite(bits: 8..<9) - public var monitoract: MONITORACT - - /// PendSV exception active bit - @ReadWrite(bits: 10..<11) - public var pendsvact: PENDSVACT - - /// SysTick exception active bit - @ReadWrite(bits: 11..<12) - public var systickact: SYSTICKACT - - /// Usage fault exception pending bit - @ReadWrite(bits: 12..<13) - public var usgfaultpended: USGFAULTPENDED - - /// Memory management fault exception pending bit - @ReadWrite(bits: 13..<14) - public var memfaultpended: MEMFAULTPENDED - - /// Bus fault exception pending bit - @ReadWrite(bits: 14..<15) - public var busfaultpended: BUSFAULTPENDED - - /// SVC call pending bit - @ReadWrite(bits: 15..<16) - public var svcallpended: SVCALLPENDED - - /// Memory management fault enable bit - @ReadWrite(bits: 16..<17) - public var memfaultena: MEMFAULTENA - - /// Bus fault enable bit - @ReadWrite(bits: 17..<18) - public var busfaultena: BUSFAULTENA - - /// Usage fault enable bit - @ReadWrite(bits: 18..<19) - public var usgfaultena: USGFAULTENA - } - - /// Configurable fault status register - @Register(bitWidth: 32) - public struct CFSR_UFSR_BFSR_MMFSR { - /// IACCVIOL - @ReadWrite(bits: 0..<1) - public var iaccviol: IACCVIOL - - /// DACCVIOL - @ReadWrite(bits: 1..<2) - public var daccviol: DACCVIOL - - /// MUNSTKERR - @ReadWrite(bits: 3..<4) - public var munstkerr: MUNSTKERR - - /// MSTKERR - @ReadWrite(bits: 4..<5) - public var mstkerr: MSTKERR - - /// MLSPERR - @ReadWrite(bits: 5..<6) - public var mlsperr: MLSPERR - - /// MMARVALID - @ReadWrite(bits: 7..<8) - public var mmarvalid: MMARVALID - - /// Instruction bus error - @ReadWrite(bits: 8..<9) - public var ibuserr: IBUSERR - - /// Precise data bus error - @ReadWrite(bits: 9..<10) - public var preciserr: PRECISERR - - /// Imprecise data bus error - @ReadWrite(bits: 10..<11) - public var impreciserr: IMPRECISERR - - /// Bus fault on unstacking for a return from exception - @ReadWrite(bits: 11..<12) - public var unstkerr: UNSTKERR - - /// Bus fault on stacking for exception entry - @ReadWrite(bits: 12..<13) - public var stkerr: STKERR - - /// Bus fault on floating-point lazy state preservation - @ReadWrite(bits: 13..<14) - public var lsperr: LSPERR - - /// Bus Fault Address Register (BFAR) valid flag - @ReadWrite(bits: 15..<16) - public var bfarvalid: BFARVALID - - /// Undefined instruction usage fault - @ReadWrite(bits: 16..<17) - public var undefinstr: UNDEFINSTR - - /// Invalid state usage fault - @ReadWrite(bits: 17..<18) - public var invstate: INVSTATE - - /// Invalid PC load usage fault - @ReadWrite(bits: 18..<19) - public var invpc: INVPC - - /// No coprocessor usage fault. - @ReadWrite(bits: 19..<20) - public var nocp: NOCP - - /// Unaligned access usage fault - @ReadWrite(bits: 24..<25) - public var unaligned: UNALIGNED - - /// Divide by zero usage fault - @ReadWrite(bits: 25..<26) - public var divbyzero: DIVBYZERO - } - - /// Hard fault status register - @Register(bitWidth: 32) - public struct HFSR { - /// Vector table hard fault - @ReadWrite(bits: 1..<2) - public var vecttbl: VECTTBL - - /// Forced hard fault - @ReadWrite(bits: 30..<31) - public var forced: FORCED - - /// Reserved for Debug use - @ReadWrite(bits: 31..<32) - public var debug_vt: DEBUG_VT - } - - /// Memory management fault address register - @Register(bitWidth: 32) - public struct MMFAR { - /// Memory management fault address - @ReadWrite(bits: 0..<32) - public var address: ADDRESS - } - - /// Bus fault address register - @Register(bitWidth: 32) - public struct BFAR { - /// Bus fault address - @ReadWrite(bits: 0..<32) - public var address: ADDRESS - } -} diff --git a/stm32-lvgl/Sources/Registers/STK.swift b/stm32-lvgl/Sources/Registers/STK.swift deleted file mode 100644 index e5b20c57..00000000 --- a/stm32-lvgl/Sources/Registers/STK.swift +++ /dev/null @@ -1,77 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// SysTick timer -@RegisterBlock -public struct STK { - /// SysTick control and status register - @RegisterBlock(offset: 0x0) - public var csr: Register - - /// SysTick reload value register - @RegisterBlock(offset: 0x4) - public var rvr: Register - - /// SysTick current value register - @RegisterBlock(offset: 0x8) - public var cvr: Register - - /// SysTick calibration value register - @RegisterBlock(offset: 0xc) - public var calib: Register -} - -extension STK { - /// SysTick control and status register - @Register(bitWidth: 32) - public struct CSR { - /// Counter enable - @ReadWrite(bits: 0..<1) - public var enable: ENABLE - - /// SysTick exception request enable - @ReadWrite(bits: 1..<2) - public var tickint: TICKINT - - /// Clock source selection - @ReadWrite(bits: 2..<3) - public var clksource: CLKSOURCE - - /// COUNTFLAG - @ReadWrite(bits: 16..<17) - public var countflag: COUNTFLAG - } - - /// SysTick reload value register - @Register(bitWidth: 32) - public struct RVR { - /// RELOAD value - @ReadWrite(bits: 0..<24) - public var reload: RELOAD - } - - /// SysTick current value register - @Register(bitWidth: 32) - public struct CVR { - /// Current counter value - @ReadWrite(bits: 0..<24) - public var current: CURRENT - } - - /// SysTick calibration value register - @Register(bitWidth: 32) - public struct CALIB { - /// Calibration value - @ReadWrite(bits: 0..<24) - public var tenms: TENMS - - /// SKEW flag: Indicates whether the TENMS value is exact - @ReadWrite(bits: 30..<31) - public var skew: SKEW - - /// NOREF flag. Reads as zero - @ReadWrite(bits: 31..<32) - public var noref: NOREF - } -} diff --git a/stm32-lvgl/Sources/Registers/SYSCFG.swift b/stm32-lvgl/Sources/Registers/SYSCFG.swift deleted file mode 100644 index cacf50b2..00000000 --- a/stm32-lvgl/Sources/Registers/SYSCFG.swift +++ /dev/null @@ -1,161 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// System configuration controller -@RegisterBlock -public struct SYSCFG { - /// memory remap register - @RegisterBlock(offset: 0x0) - public var memrmp: Register - - /// peripheral mode configuration register - @RegisterBlock(offset: 0x4) - public var pmc: Register - - /// external interrupt configuration register 1 - @RegisterBlock(offset: 0x8) - public var exticr1: Register - - /// external interrupt configuration register 2 - @RegisterBlock(offset: 0xc) - public var exticr2: Register - - /// external interrupt configuration register 3 - @RegisterBlock(offset: 0x10) - public var exticr3: Register - - /// external interrupt configuration register 4 - @RegisterBlock(offset: 0x14) - public var exticr4: Register - - /// Compensation cell control register - @RegisterBlock(offset: 0x20) - public var cmpcr: Register -} - -extension SYSCFG { - /// memory remap register - @Register(bitWidth: 32) - public struct MEMRMP { - /// Memory mapping selection - @ReadWrite(bits: 0..<1) - public var mem_boot: MEM_BOOT - - /// FMC memory mapping swap - @ReadWrite(bits: 10..<12) - public var swp_fmc: SWP_FMC - } - - /// peripheral mode configuration register - @Register(bitWidth: 32) - public struct PMC { - /// Ethernet PHY interface selection - @ReadWrite(bits: 23..<24) - public var mii_rmii_sel: MII_RMII_SEL - - /// ADC1DC2 - @ReadWrite(bits: 16..<17) - public var adc1dc2: ADC1DC2 - - /// ADC2DC2 - @ReadWrite(bits: 17..<18) - public var adc2dc2: ADC2DC2 - - /// ADC3DC2 - @ReadWrite(bits: 18..<19) - public var adc3dc2: ADC3DC2 - } - - /// external interrupt configuration register 1 - @Register(bitWidth: 32) - public struct EXTICR1 { - /// EXTI x configuration (x = 0 to 3) - @ReadWrite(bits: 12..<16) - public var exti3: EXTI3 - - /// EXTI x configuration (x = 0 to 3) - @ReadWrite(bits: 8..<12) - public var exti2: EXTI2 - - /// EXTI x configuration (x = 0 to 3) - @ReadWrite(bits: 4..<8) - public var exti1: EXTI1 - - /// EXTI x configuration (x = 0 to 3) - @ReadWrite(bits: 0..<4) - public var exti0: EXTI0 - } - - /// external interrupt configuration register 2 - @Register(bitWidth: 32) - public struct EXTICR2 { - /// EXTI x configuration (x = 4 to 7) - @ReadWrite(bits: 12..<16) - public var exti7: EXTI7 - - /// EXTI x configuration (x = 4 to 7) - @ReadWrite(bits: 8..<12) - public var exti6: EXTI6 - - /// EXTI x configuration (x = 4 to 7) - @ReadWrite(bits: 4..<8) - public var exti5: EXTI5 - - /// EXTI x configuration (x = 4 to 7) - @ReadWrite(bits: 0..<4) - public var exti4: EXTI4 - } - - /// external interrupt configuration register 3 - @Register(bitWidth: 32) - public struct EXTICR3 { - /// EXTI x configuration (x = 8 to 11) - @ReadWrite(bits: 12..<16) - public var exti11: EXTI11 - - /// EXTI10 - @ReadWrite(bits: 8..<12) - public var exti10: EXTI10 - - /// EXTI x configuration (x = 8 to 11) - @ReadWrite(bits: 4..<8) - public var exti9: EXTI9 - - /// EXTI x configuration (x = 8 to 11) - @ReadWrite(bits: 0..<4) - public var exti8: EXTI8 - } - - /// external interrupt configuration register 4 - @Register(bitWidth: 32) - public struct EXTICR4 { - /// EXTI x configuration (x = 12 to 15) - @ReadWrite(bits: 12..<16) - public var exti15: EXTI15 - - /// EXTI x configuration (x = 12 to 15) - @ReadWrite(bits: 8..<12) - public var exti14: EXTI14 - - /// EXTI x configuration (x = 12 to 15) - @ReadWrite(bits: 4..<8) - public var exti13: EXTI13 - - /// EXTI x configuration (x = 12 to 15) - @ReadWrite(bits: 0..<4) - public var exti12: EXTI12 - } - - /// Compensation cell control register - @Register(bitWidth: 32) - public struct CMPCR { - /// READY - @ReadOnly(bits: 8..<9) - public var ready: READY - - /// Compensation cell power-down - @ReadOnly(bits: 0..<1) - public var cmp_pd: CMP_PD - } -} diff --git a/stm32-lvgl/Sources/Registers/USART1.swift b/stm32-lvgl/Sources/Registers/USART1.swift deleted file mode 100644 index 04d26f6a..00000000 --- a/stm32-lvgl/Sources/Registers/USART1.swift +++ /dev/null @@ -1,1554 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Universal synchronous asynchronous receiver transmitter -@RegisterBlock -public struct USART1 { - /// Control register 1 - @RegisterBlock(offset: 0x0) - public var cr1: Register - - /// Control register 2 - @RegisterBlock(offset: 0x4) - public var cr2: Register - - /// Control register 3 - @RegisterBlock(offset: 0x8) - public var cr3: Register - - /// Baud rate register - @RegisterBlock(offset: 0xc) - public var brr: Register - - /// Guard time and prescaler register - @RegisterBlock(offset: 0x10) - public var gtpr: Register - - /// Receiver timeout register - @RegisterBlock(offset: 0x14) - public var rtor: Register - - /// Request register - @RegisterBlock(offset: 0x18) - public var rqr: Register - - /// Interrupt & status register - @RegisterBlock(offset: 0x1c) - public var isr: Register - - /// Interrupt flag clear register - @RegisterBlock(offset: 0x20) - public var icr: Register - - /// Receive data register - @RegisterBlock(offset: 0x24) - public var rdr: Register - - /// Transmit data register - @RegisterBlock(offset: 0x28) - public var tdr: Register -} - -extension USART1 { - /// Control register 1 - @Register(bitWidth: 32) - public struct CR1 { - /// Word length - @ReadWrite(bits: 28..<29, as: M1Values.self) - public var m1: M1 - - /// End of Block interrupt enable - @ReadWrite(bits: 27..<28, as: EOBIEValues.self) - public var eobie: EOBIE - - /// Receiver timeout interrupt enable - @ReadWrite(bits: 26..<27, as: RTOIEValues.self) - public var rtoie: RTOIE - - /// Oversampling mode - @ReadWrite(bits: 15..<16, as: OVER8Values.self) - public var over8: OVER8 - - /// Character match interrupt enable - @ReadWrite(bits: 14..<15, as: CMIEValues.self) - public var cmie: CMIE - - /// Mute mode enable - @ReadWrite(bits: 13..<14, as: MMEValues.self) - public var mme: MME - - /// Word length - @ReadWrite(bits: 12..<13, as: M0Values.self) - public var m0: M0 - - /// Receiver wakeup method - @ReadWrite(bits: 11..<12, as: WAKEValues.self) - public var wake: WAKE - - /// Parity control enable - @ReadWrite(bits: 10..<11, as: PCEValues.self) - public var pce: PCE - - /// Parity selection - @ReadWrite(bits: 9..<10, as: PSValues.self) - public var ps: PS - - /// PE interrupt enable - @ReadWrite(bits: 8..<9, as: PEIEValues.self) - public var peie: PEIE - - /// interrupt enable - @ReadWrite(bits: 7..<8, as: TXEIEValues.self) - public var txeie: TXEIE - - /// Transmission complete interrupt enable - @ReadWrite(bits: 6..<7, as: TCIEValues.self) - public var tcie: TCIE - - /// RXNE interrupt enable - @ReadWrite(bits: 5..<6, as: RXNEIEValues.self) - public var rxneie: RXNEIE - - /// IDLE interrupt enable - @ReadWrite(bits: 4..<5, as: IDLEIEValues.self) - public var idleie: IDLEIE - - /// Transmitter enable - @ReadWrite(bits: 3..<4, as: TEValues.self) - public var te: TE - - /// Receiver enable - @ReadWrite(bits: 2..<3, as: REValues.self) - public var re: RE - - /// USART enable in Stop mode - @ReadWrite(bits: 1..<2, as: UESMValues.self) - public var uesm: UESM - - /// USART enable - @ReadWrite(bits: 0..<1, as: UEValues.self) - public var ue: UE - - /// Driver Enable assertion time - @ReadWrite(bits: 21..<26) - public var deat: DEAT - - /// Driver Enable de-assertion time - @ReadWrite(bits: 16..<21) - public var dedt: DEDT - } - - /// Control register 2 - @Register(bitWidth: 32) - public struct CR2 { - /// Receiver timeout enable - @ReadWrite(bits: 23..<24, as: RTOENValues.self) - public var rtoen: RTOEN - - /// Auto baud rate enable - @ReadWrite(bits: 20..<21, as: ABRENValues.self) - public var abren: ABREN - - /// Most significant bit first - @ReadWrite(bits: 19..<20, as: MSBFIRSTValues.self) - public var msbfirst: MSBFIRST - - /// Binary data inversion - @ReadWrite(bits: 18..<19, as: DATAINVValues.self) - public var datainv: DATAINV - - /// TX pin active level inversion - @ReadWrite(bits: 17..<18, as: TXINVValues.self) - public var txinv: TXINV - - /// RX pin active level inversion - @ReadWrite(bits: 16..<17, as: RXINVValues.self) - public var rxinv: RXINV - - /// Swap TX/RX pins - @ReadWrite(bits: 15..<16, as: SWAPValues.self) - public var swap: SWAP - - /// LIN mode enable - @ReadWrite(bits: 14..<15, as: LINENValues.self) - public var linen: LINEN - - /// STOP bits - @ReadWrite(bits: 12..<14, as: STOPValues.self) - public var stop: STOP - - /// Clock enable - @ReadWrite(bits: 11..<12, as: CLKENValues.self) - public var clken: CLKEN - - /// Clock polarity - @ReadWrite(bits: 10..<11, as: CPOLValues.self) - public var cpol: CPOL - - /// Clock phase - @ReadWrite(bits: 9..<10, as: CPHAValues.self) - public var cpha: CPHA - - /// Last bit clock pulse - @ReadWrite(bits: 8..<9, as: LBCLValues.self) - public var lbcl: LBCL - - /// LIN break detection interrupt enable - @ReadWrite(bits: 6..<7, as: LBDIEValues.self) - public var lbdie: LBDIE - - /// LIN break detection length - @ReadWrite(bits: 5..<6, as: LBDLValues.self) - public var lbdl: LBDL - - /// 7-bit Address Detection/4-bit Address Detection - @ReadWrite(bits: 4..<5, as: ADDM7Values.self) - public var addm7: ADDM7 - - /// Auto baud rate mode - @ReadWrite(bits: 21..<23, as: ABRMODValues.self) - public var abrmod: ABRMOD - - /// Address of the USART node - @ReadWrite(bits: 24..<32) - public var add: ADD - } - - /// Control register 3 - @Register(bitWidth: 32) - public struct CR3 { - /// Wakeup from Stop mode interrupt enable - @ReadWrite(bits: 22..<23, as: WUFIEValues.self) - public var wufie: WUFIE - - /// Wakeup from Stop mode interrupt flag selection - @ReadWrite(bits: 20..<22, as: WUSValues.self) - public var wus: WUS - - /// Smartcard auto-retry count - @ReadWrite(bits: 17..<20) - public var scarcnt: SCARCNT - - /// Driver enable polarity selection - @ReadWrite(bits: 15..<16, as: DEPValues.self) - public var dep: DEP - - /// Driver enable mode - @ReadWrite(bits: 14..<15, as: DEMValues.self) - public var dem: DEM - - /// DMA Disable on Reception Error - @ReadWrite(bits: 13..<14, as: DDREValues.self) - public var ddre: DDRE - - /// Overrun Disable - @ReadWrite(bits: 12..<13, as: OVRDISValues.self) - public var ovrdis: OVRDIS - - /// One sample bit method enable - @ReadWrite(bits: 11..<12, as: ONEBITValues.self) - public var onebit: ONEBIT - - /// CTS interrupt enable - @ReadWrite(bits: 10..<11, as: CTSIEValues.self) - public var ctsie: CTSIE - - /// CTS enable - @ReadWrite(bits: 9..<10, as: CTSEValues.self) - public var ctse: CTSE - - /// RTS enable - @ReadWrite(bits: 8..<9, as: RTSEValues.self) - public var rtse: RTSE - - /// DMA enable transmitter - @ReadWrite(bits: 7..<8, as: DMATValues.self) - public var dmat: DMAT - - /// DMA enable receiver - @ReadWrite(bits: 6..<7, as: DMARValues.self) - public var dmar: DMAR - - /// Smartcard mode enable - @ReadWrite(bits: 5..<6, as: SCENValues.self) - public var scen: SCEN - - /// Smartcard NACK enable - @ReadWrite(bits: 4..<5, as: NACKValues.self) - public var nack: NACK - - /// Half-duplex selection - @ReadWrite(bits: 3..<4, as: HDSELValues.self) - public var hdsel: HDSEL - - /// Ir low-power - @ReadWrite(bits: 2..<3, as: IRLPValues.self) - public var irlp: IRLP - - /// Ir mode enable - @ReadWrite(bits: 1..<2, as: IRENValues.self) - public var iren: IREN - - /// Error interrupt enable - @ReadWrite(bits: 0..<1, as: EIEValues.self) - public var eie: EIE - } - - /// Baud rate register - @Register(bitWidth: 32) - public struct BRR { - /// DIV_Mantissa - @ReadWrite(bits: 0..<16) - public var brr_field: BRR_FIELD - } - - /// Guard time and prescaler register - @Register(bitWidth: 32) - public struct GTPR { - /// Guard time value - @ReadWrite(bits: 8..<16) - public var gt: GT - - /// Prescaler value - @ReadWrite(bits: 0..<8) - public var psc: PSC - } - - /// Receiver timeout register - @Register(bitWidth: 32) - public struct RTOR { - /// Block Length - @ReadWrite(bits: 24..<32) - public var blen: BLEN - - /// Receiver timeout value - @ReadWrite(bits: 0..<24) - public var rto: RTO - } - - /// Request register - @Register(bitWidth: 32) - public struct RQR { - /// Transmit data flush request - @WriteOnly(bits: 4..<5) - public var txfrq: TXFRQ - - /// Receive data flush request - @WriteOnly(bits: 3..<4) - public var rxfrq: RXFRQ - - /// Mute mode request - @WriteOnly(bits: 2..<3) - public var mmrq: MMRQ - - /// Send break request - @WriteOnly(bits: 1..<2) - public var sbkrq: SBKRQ - - /// Auto baud rate request - @WriteOnly(bits: 0..<1) - public var abrrq: ABRRQ - } - - /// Interrupt & status register - @Register(bitWidth: 32) - public struct ISR { - /// REACK - @ReadOnly(bits: 22..<23) - public var reack: REACK - - /// TEACK - @ReadOnly(bits: 21..<22) - public var teack: TEACK - - /// WUF - @ReadOnly(bits: 20..<21) - public var wuf: WUF - - /// RWU - @ReadOnly(bits: 19..<20) - public var rwu: RWU - - /// SBKF - @ReadOnly(bits: 18..<19) - public var sbkf: SBKF - - /// CMF - @ReadOnly(bits: 17..<18) - public var cmf: CMF - - /// BUSY - @ReadOnly(bits: 16..<17) - public var busy: BUSY - - /// ABRF - @ReadOnly(bits: 15..<16) - public var abrf: ABRF - - /// ABRE - @ReadOnly(bits: 14..<15) - public var abre: ABRE - - /// EOBF - @ReadOnly(bits: 12..<13) - public var eobf: EOBF - - /// RTOF - @ReadOnly(bits: 11..<12) - public var rtof: RTOF - - /// CTS - @ReadOnly(bits: 10..<11) - public var cts: CTS - - /// CTSIF - @ReadOnly(bits: 9..<10) - public var ctsif: CTSIF - - /// LBDF - @ReadOnly(bits: 8..<9) - public var lbdf: LBDF - - /// TXE - @ReadOnly(bits: 7..<8) - public var txe: TXE - - /// TC - @ReadOnly(bits: 6..<7) - public var tc: TC - - /// RXNE - @ReadOnly(bits: 5..<6) - public var rxne: RXNE - - /// IDLE - @ReadOnly(bits: 4..<5) - public var idle: IDLE - - /// ORE - @ReadOnly(bits: 3..<4) - public var ore: ORE - - /// NF - @ReadOnly(bits: 2..<3) - public var nf: NF - - /// FE - @ReadOnly(bits: 1..<2) - public var fe: FE - - /// PE - @ReadOnly(bits: 0..<1) - public var pe: PE - } - - /// Interrupt flag clear register - @Register(bitWidth: 32) - public struct ICR { - /// Wakeup from Stop mode clear flag - @WriteOnly(bits: 20..<21) - public var wucf: WUCF - - /// Character match clear flag - @WriteOnly(bits: 17..<18) - public var cmcf: CMCF - - /// End of block clear flag - @WriteOnly(bits: 12..<13) - public var eobcf: EOBCF - - /// Receiver timeout clear flag - @WriteOnly(bits: 11..<12) - public var rtocf: RTOCF - - /// CTS clear flag - @WriteOnly(bits: 9..<10) - public var ctscf: CTSCF - - /// LIN break detection clear flag - @WriteOnly(bits: 8..<9) - public var lbdcf: LBDCF - - /// Transmission complete clear flag - @WriteOnly(bits: 6..<7) - public var tccf: TCCF - - /// Idle line detected clear flag - @WriteOnly(bits: 4..<5) - public var idlecf: IDLECF - - /// Overrun error clear flag - @WriteOnly(bits: 3..<4) - public var orecf: ORECF - - /// Noise detected clear flag - @WriteOnly(bits: 2..<3) - public var ncf: NCF - - /// Framing error clear flag - @WriteOnly(bits: 1..<2) - public var fecf: FECF - - /// Parity error clear flag - @WriteOnly(bits: 0..<1) - public var pecf: PECF - } - - /// Receive data register - @Register(bitWidth: 32) - public struct RDR { - /// Receive data value - @ReadOnly(bits: 0..<9) - public var rdr_field: RDR_FIELD - } - - /// Transmit data register - @Register(bitWidth: 32) - public struct TDR { - /// Transmit data value - @ReadWrite(bits: 0..<9) - public var tdr_field: TDR_FIELD - } -} - -extension USART1.CR1 { - public struct M1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Use M0 to set the data bits - public static let M0 = Self(rawValue: 0x0) - - /// 1 start bit, 7 data bits, n stop bits - public static let Bit7 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct EOBIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// A USART interrupt is generated when the EOBF flag is set in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct RTOIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An USART interrupt is generated when the RTOF bit is set in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct OVER8Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Oversampling by 16 - public static let Oversampling16 = Self(rawValue: 0x0) - - /// Oversampling by 8 - public static let Oversampling8 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct CMIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated when the CMF bit is set in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct MMEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Receiver in active mode permanently - public static let Disabled = Self(rawValue: 0x0) - - /// Receiver can switch between mute mode and active mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct M0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 1 start bit, 8 data bits, n stop bits - public static let Bit8 = Self(rawValue: 0x0) - - /// 1 start bit, 9 data bits, n stop bits - public static let Bit9 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct WAKEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Idle line - public static let Idle = Self(rawValue: 0x0) - - /// Address mask - public static let Address = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct PCEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Parity control disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Parity control enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct PSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Even parity - public static let Even = Self(rawValue: 0x0) - - /// Odd parity - public static let Odd = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct PEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever PE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct TXEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever TXE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct TCIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever TC=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct RXNEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct IDLEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever IDLE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct TEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Transmitter is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Transmitter is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct REValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Receiver is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Receiver is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct UESMValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// USART not able to wake up the MCU from Stop mode - public static let Disabled = Self(rawValue: 0x0) - - /// USART able to wake up the MCU from Stop mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct UEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// UART is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// UART is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct RTOENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Receiver timeout feature disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Receiver timeout feature enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct ABRENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Auto baud rate detection is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Auto baud rate detection is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct MSBFIRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// data is transmitted/received with data bit 0 first, following the start bit - public static let LSB = Self(rawValue: 0x0) - - /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit - public static let MSB = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct DATAINVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Logical data from the data register are send/received in positive/direct logic - public static let Positive = Self(rawValue: 0x0) - - /// Logical data from the data register are send/received in negative/inverse logic - public static let Negative = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct TXINVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// TX pin signal works using the standard logic levels - public static let Standard = Self(rawValue: 0x0) - - /// TX pin signal values are inverted - public static let Inverted = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct RXINVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RX pin signal works using the standard logic levels - public static let Standard = Self(rawValue: 0x0) - - /// RX pin signal values are inverted - public static let Inverted = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct SWAPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// TX/RX pins are used as defined in standard pinout - public static let Standard = Self(rawValue: 0x0) - - /// The TX and RX pins functions are swapped - public static let Swapped = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LINENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LIN mode disabled - public static let Disabled = Self(rawValue: 0x0) - - /// LIN mode enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct STOPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// 1 stop bit - public static let Stop1 = Self(rawValue: 0x0) - - /// 0.5 stop bit - public static let Stop0p5 = Self(rawValue: 0x1) - - /// 2 stop bit - public static let Stop2 = Self(rawValue: 0x2) - - /// 1.5 stop bit - public static let Stop1p5 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct CLKENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// CK pin disabled - public static let Disabled = Self(rawValue: 0x0) - - /// CK pin enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct CPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Steady low value on CK pin outside transmission window - public static let Low = Self(rawValue: 0x0) - - /// Steady high value on CK pin outside transmission window - public static let High = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct CPHAValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The first clock transition is the first data capture edge - public static let First = Self(rawValue: 0x0) - - /// The second clock transition is the first data capture edge - public static let Second = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LBCLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The clock pulse of the last data bit is not output to the CK pin - public static let NotOutput = Self(rawValue: 0x0) - - /// The clock pulse of the last data bit is output to the CK pin - public static let Output = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LBDIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An interrupt is generated whenever LBDF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LBDLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 10-bit break detection - public static let Bit10 = Self(rawValue: 0x0) - - /// 11-bit break detection - public static let Bit11 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct ADDM7Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 4-bit address detection - public static let Bit4 = Self(rawValue: 0x0) - - /// 7-bit address detection - public static let Bit7 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct ABRMODValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Measurement of the start bit is used to detect the baud rate - public static let Start = Self(rawValue: 0x0) - - /// Falling edge to falling edge measurement - public static let Edge = Self(rawValue: 0x1) - - /// 0x7F frame detection - public static let Frame7F = Self(rawValue: 0x2) - - /// 0x55 frame detection - public static let Frame55 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct WUFIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An USART interrupt is generated whenever WUF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct WUSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// WUF active on address match - public static let Address = Self(rawValue: 0x0) - - /// WuF active on Start bit detection - public static let Start = Self(rawValue: 0x2) - - /// WUF active on RXNE - public static let RXNE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DEPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DE signal is active high - public static let High = Self(rawValue: 0x0) - - /// DE signal is active low - public static let Low = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DEMValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DE function is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The DE signal is output on the RTS pin - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DDREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA is not disabled in case of reception error - public static let NotDisabled = Self(rawValue: 0x0) - - /// DMA is disabled following a reception error - public static let Disabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct OVRDISValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Overrun Error Flag, ORE, is set when received data is not read before receiving new data - public static let Enabled = Self(rawValue: 0x0) - - /// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register - public static let Disabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct ONEBITValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Three sample bit method - public static let Sample3 = Self(rawValue: 0x0) - - /// One sample bit method - public static let Sample1 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct CTSIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An interrupt is generated whenever CTSIF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct CTSEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// CTS hardware flow control disabled - public static let Disabled = Self(rawValue: 0x0) - - /// CTS mode enabled, data is only transmitted when the CTS input is asserted - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct RTSEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RTS hardware flow control disabled - public static let Disabled = Self(rawValue: 0x0) - - /// RTS output enabled, data is only requested when there is space in the receive buffer - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DMATValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA mode is disabled for transmission - public static let Disabled = Self(rawValue: 0x0) - - /// DMA mode is enabled for transmission - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DMARValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA mode is disabled for reception - public static let Disabled = Self(rawValue: 0x0) - - /// DMA mode is enabled for reception - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct SCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Smartcard Mode disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Smartcard Mode enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct NACKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// NACK transmission in case of parity error is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// NACK transmission during parity error is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct HDSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Half duplex mode is not selected - public static let NotSelected = Self(rawValue: 0x0) - - /// Half duplex mode is selected - public static let Selected = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct IRLPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Normal mode - public static let Normal = Self(rawValue: 0x0) - - /// Low-power mode - public static let LowPower = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct IRENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// IrDA disabled - public static let Disabled = Self(rawValue: 0x0) - - /// IrDA enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct EIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-lvgl/Sources/Support/Startup.c b/stm32-lvgl/Sources/Support/Startup.c deleted file mode 100644 index 1c70ffae..00000000 --- a/stm32-lvgl/Sources/Support/Startup.c +++ /dev/null @@ -1,163 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include -#include - -void enable_fpu(void) { - *(volatile uint32_t *)0xE000ED88 |= (0xF << 20); // set CP10 and CP11 Full Access -} - -// Reset entrypoint. Enables FPU, relocates the data sections from FLASH to DRAM -// and jumps to main (implemented in Application/Main.swift). -// -// See linkerscript.ld for a detailed explanation. -__attribute__((naked)) __attribute__((noreturn)) void ResetISR(void) { - asm volatile("bl enable_fpu"); - asm volatile("ldr r0, =__data_start // dst"); - asm volatile("ldr r1, =__flash_data_start // src"); - asm volatile("ldr r2, =__flash_data_len // size"); - asm volatile("bl memcpy"); - asm volatile("bl main"); - - // If main returns, spin. - asm volatile("b ."); -} - -// Implemented in Application/Interrupts.swift -void SystickTimerISR(void); -void LtdcIntHandlerISR(void); - -void IntDefaultHandlerISR() { __builtin_trap(); } - -// These are provided by the linker script -extern void *__stack_start; -extern void *__stack_end; - -// Primary interrupt vector table -__attribute__((section(".vectors"))) const void *Vectors[] = { - (void *)(((uintptr_t)&__stack_end) - 4), // initial SP - ResetISR, // 1 0x04 The reset handler - IntDefaultHandlerISR, // 2 0x08 The NMI handler - IntDefaultHandlerISR, // 3 0x0C The hard fault handler - IntDefaultHandlerISR, // 4 0x10 The MPU fault handler - IntDefaultHandlerISR, // 5 0x14 The bus fault handler - IntDefaultHandlerISR, // 6 0x18 The usage fault handler - 0, // 7 0x1c Reserved - 0, // 8 0x20 Reserved - 0, // 9 0x24 Reserved - 0, // 10 0x28 Reserved - IntDefaultHandlerISR, // 11 0x2c SVCall handler - IntDefaultHandlerISR, // 12 0x30 Debug monitor handler - IntDefaultHandlerISR, // 13 0x34 Reserved - IntDefaultHandlerISR, // 14 0x38 The PendSV handler - SystickTimerISR, // 15 0x3c The SysTick handler - IntDefaultHandlerISR, // 16 0x40 - IntDefaultHandlerISR, // 17 0x44 - IntDefaultHandlerISR, // 18 0x48 - IntDefaultHandlerISR, // 19 0x4C - IntDefaultHandlerISR, // 20 0x50 - IntDefaultHandlerISR, // 21 0x54 - IntDefaultHandlerISR, // 22 0x58 - IntDefaultHandlerISR, // 23 0x5C - IntDefaultHandlerISR, // 24 0x60 - IntDefaultHandlerISR, // 25 0x64 - IntDefaultHandlerISR, // 26 0x68 - IntDefaultHandlerISR, // 27 0x6C - IntDefaultHandlerISR, // 28 0x70 - IntDefaultHandlerISR, // 29 0x74 - IntDefaultHandlerISR, // 30 0x78 - IntDefaultHandlerISR, // 31 0x7C - IntDefaultHandlerISR, // 32 0x80 - IntDefaultHandlerISR, // 33 0x84 - IntDefaultHandlerISR, // 34 0x88 - IntDefaultHandlerISR, // 35 0x8c - IntDefaultHandlerISR, // 36 0x90 - IntDefaultHandlerISR, // 37 0x94 - IntDefaultHandlerISR, // 38 0x98 - IntDefaultHandlerISR, // 39 0x9c - IntDefaultHandlerISR, // 40 0xA0 - IntDefaultHandlerISR, // 41 0xA4 - IntDefaultHandlerISR, // 42 0xA8 - IntDefaultHandlerISR, // 43 0xAC - IntDefaultHandlerISR, // 44 0xB0 - IntDefaultHandlerISR, // 45 0xB4 - IntDefaultHandlerISR, // 46 0xB8 - IntDefaultHandlerISR, // 47 0xBC - IntDefaultHandlerISR, // 48 0xC0 - IntDefaultHandlerISR, // 49 0xC4 - IntDefaultHandlerISR, // 50 0xC8 - IntDefaultHandlerISR, // 51 0xCC - IntDefaultHandlerISR, // 52 0xD0 - IntDefaultHandlerISR, // 53 0xD4 - IntDefaultHandlerISR, // 54 0xD8 - IntDefaultHandlerISR, // 55 0xDC - IntDefaultHandlerISR, // 56 0xE0 - IntDefaultHandlerISR, // 57 0xE4 - IntDefaultHandlerISR, // 58 0xE8 - IntDefaultHandlerISR, // 59 0xEC - IntDefaultHandlerISR, // 60 0xF0 - IntDefaultHandlerISR, // 61 0xF4 - IntDefaultHandlerISR, // 62 0xF8 - IntDefaultHandlerISR, // 63 0xFC - IntDefaultHandlerISR, // 64 0x100 - IntDefaultHandlerISR, // 65 0x104 - IntDefaultHandlerISR, // 66 0x108 - IntDefaultHandlerISR, // 67 0x10C - IntDefaultHandlerISR, // 68 0x110 - IntDefaultHandlerISR, // 69 0x114 - IntDefaultHandlerISR, // 70 0x118 - IntDefaultHandlerISR, // 71 0x11C - IntDefaultHandlerISR, // 72 0x120 - IntDefaultHandlerISR, // 73 0x124 - IntDefaultHandlerISR, // 74 0x128 - IntDefaultHandlerISR, // 75 0x12C - IntDefaultHandlerISR, // 76 0x130 - IntDefaultHandlerISR, // 77 0x134 - 0, // 78 0x138 - IntDefaultHandlerISR, // 79 0x13C - IntDefaultHandlerISR, // 80 0x140 - IntDefaultHandlerISR, // 81 0x144 - IntDefaultHandlerISR, // 82 0x148 - IntDefaultHandlerISR, // 83 0x14C - IntDefaultHandlerISR, // 84 0x150 - IntDefaultHandlerISR, // 85 0x154 - IntDefaultHandlerISR, // 86 0x158 - IntDefaultHandlerISR, // 87 0x15C - IntDefaultHandlerISR, // 88 0x160 - IntDefaultHandlerISR, // 89 0x164 - IntDefaultHandlerISR, // 90 0x168 - IntDefaultHandlerISR, // 91 0x16C - IntDefaultHandlerISR, // 92 0x170 - IntDefaultHandlerISR, // 93 0x174 - IntDefaultHandlerISR, // 94 0x178 - 0, // 95 0x17C - 0, // 96 0x180 - IntDefaultHandlerISR, // 97 0x184 - 0, // 98 0x188 - 0, // 99 0x18C - IntDefaultHandlerISR, // 100 0x190 - 0, // 101 0x194 - IntDefaultHandlerISR, // 102 0x198 - IntDefaultHandlerISR, // 103 0x19C - LtdcIntHandlerISR, // 104 0x1A0 - 0, // 105 0x1A4 - 0, // 106 0x1A8 - IntDefaultHandlerISR, // 107 0x1AC - IntDefaultHandlerISR, // 108 0x1B0 - IntDefaultHandlerISR, // 109 0x1B4 - IntDefaultHandlerISR, // 110 0x1B8 - IntDefaultHandlerISR, // 111 0x1BC - IntDefaultHandlerISR, // 112 0x1C0 -}; - -// ELF entrypoint, not actually called at runtime, but it's a GC root -void *_start_elf(void) { return (void *)&Vectors; } diff --git a/stm32-lvgl/Sources/Support/Stubs.c b/stm32-lvgl/Sources/Support/Stubs.c deleted file mode 100644 index c67b280a..00000000 --- a/stm32-lvgl/Sources/Support/Stubs.c +++ /dev/null @@ -1,27 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include -#include - -// This is NOT real entropy. This implementation is a stub that generates -// predictable, sequential values for testing purposes only. Do not use this -// in production code where actual cryptographic randomness is required. -int getentropy(char *buffer, size_t length) { - for (size_t i = 0; i < length; i++) { - buffer[i] = i % 256; - } - return 0; -} - -void _exit(int status) { - __builtin_trap(); -} diff --git a/stm32-lvgl/Sources/Support/include/Support.h b/stm32-lvgl/Sources/Support/include/Support.h deleted file mode 100644 index 63765c25..00000000 --- a/stm32-lvgl/Sources/Support/include/Support.h +++ /dev/null @@ -1,43 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2025 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#pragma once - -#include - -static inline void nop() { - asm volatile("nop"); -} - -static inline uint32_t primask_get(void) { - uint32_t r; - asm volatile("mrs %0, primask" : "=r" (r)); - return r; -} - -static inline void primask_set(uint32_t m) { - asm volatile("msr primask, %0" : : "r" (m)); -} - -static inline void cpsid_i(void) { - asm volatile("cpsid i"); -} - -static inline void delay(uint32_t i) { - __asm__ volatile( - " .align 2 \n" - "1: subs %0, #1\n" - " bhi 1b\n" - : "=r"(i) - : "0" (i) - : "cc" - ); -} diff --git a/stm32-lvgl/Sources/Support/linkerscript.ld b/stm32-lvgl/Sources/Support/linkerscript.ld deleted file mode 100644 index f3c07fdc..00000000 --- a/stm32-lvgl/Sources/Support/linkerscript.ld +++ /dev/null @@ -1,103 +0,0 @@ -/*===----------------------------------------------------------------------===*/ -/* */ -/* This source file is part of the Swift open source project */ -/* */ -/* Copyright (c) 2025 Apple Inc. and the Swift project authors. */ -/* Licensed under Apache License v2.0 with Runtime Library Exception */ -/* */ -/* See https://swift.org/LICENSE.txt for license information */ -/* */ -/*===----------------------------------------------------------------------===*/ - -/* - * This application uses ELF for linking, and uses the elf2hex.py post-processing tool for package the result into a - * form suitable for flashing. The entire memory layout scheme (which this linker script participates in) is: - * - * - At normal application runtime, the expected memory layout is: - * - * - 0x08000000-0x08100000 (flash) ... code + read-only globals - * - 0x20000000-0x20008000 (SRAM) ... stack - * - 0x20008000-0x20030000 (SRAM) ... read-write globals, and bss (zero initialized globals) - * - 0x20030000-0x20050000 (SRAM) ... heap - * - * - However, this layout cannot be flashed as is (because it uses the SRAM too), so a few more steps are needed. - * - * - In a linked ELF file, the memory locations of the sections match the expected runtime layout. The ELF file does not - * contain the stack and the heap, so we don't have to worry about those (there is also no expectation that the memory - * for those is zeroed out at program start). - * - * - The ELF file is given to the elf2hex.py tool, which will produce a .hex output, and we use the - * --relocate-data-segment flag to relocate the read-write globals region (0x20008000-0x20030000) into the flash - * region, concretely the region is appended at a 4-byte-aligned location after the other contents of the flash. - * - * - This is concretely achieved using the __flash_data_start+__flash_data_len and __data_start+__data_end symbols - * defined in this linker script. The elf2hex.py script finds the addresses of these symbols and performs the - * relocation of those bytes. - * - Note that after the relocation, the segments in ELF headers (PT_LOAD commands) don't match the actual physical - * layout. However, this relocation is reversed at early startup time, so that at "normal" runtime, the layout is - * as expected. See below. - * - * - The ARM core loads the initial stack pointer, and initial program counter from the vector table which is placed at - * a well-known location, concretely the very beginning of flash, 0x08000000. The linker script places the .vectors - * section as the very first section into the flash to satisfy this. See Startup.c for the concrete content of the - * vector table, and how the initial SP and PC are set up. - * - * - The initial startup code (ResetISR in Startup.c) only does one setup step (enabling the FPU) before performing the - * reverse relocation of the data segment. The runtime back-relocation is simply a memcpy from __flash_data_start back - * into __data_start (in the SRAM region). - * - * - During this and before this (e.g. when doing the FPU enablement), read-write globals cannot be used. Reading - * a read-write global won't read the correct initial value of that global. - * - That's why the ResetISR code is written as attribute((naked)) asm implementation. The implementation is also - * very simple and it's easy to see that it indeed does not touch any globals. - * - We expect that the implementation of memcpy is also not accessing any globals. This is a reasonable expectation - * on any embedded-friendly memcpy implementation. - * - * - After that, the normal runtime memory layout is matched, and the application continues to initialize itself and - * run. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* end: 0x08100000 */ - sram_stack (rw) : ORIGIN = 0x20000000, LENGTH = 32K /* end: 0x20008000 */ - sram_data (rw) : ORIGIN = 0x20008000, LENGTH = 160K /* end: 0x20030000 */ - sram_heap (rw) : ORIGIN = 0x20030000, LENGTH = 128K /* end: 0x20050000 */ -} - -SECTIONS -{ - .text : { *(.vectors*) ; *(.text*) } > flash - .rodata : { *(.rodata*) ; *(.got*) } > flash - - __flash_data_start = (. + 3) & ~ 3; /* 4-byte aligned end of text is where data is going to be placed (by elf2hex) */ - - .bss : { *(.bss*) } > sram_data - .tbss : { *(.tbss*) } > sram_data - .data : { *(.data*) } > sram_data - - __flash_data_len = . - ORIGIN(sram_data); - - /* TODO: Add a safeguard to detect when adding data to flash would overflow the flash memory */ - - /DISCARD/ : { *(.swift_modhash*) } - - /* ARM metadata sections */ - /DISCARD/ : { *(.ARM.attributes*) *(.ARM.exidx) } - - /* ELF metadata sections */ - .symtab : { *(.symtab) } - .strtab : { *(.strtab) } - .shstrtab : { *(.shstrtab) } - .debug : { *(.debug*) } - .comment : { *(.comment) } -} - -__stack_start = ORIGIN(sram_stack); -__stack_end = ORIGIN(sram_stack) + LENGTH(sram_stack); - -__data_start = ORIGIN(sram_data); -__data_end = ORIGIN(sram_data) + LENGTH(sram_data); - -__heap_start = ORIGIN(sram_heap); -__heap_end = ORIGIN(sram_heap) + LENGTH(sram_heap); diff --git a/stm32-lvgl/clang-arm-toolchain.cmake b/stm32-lvgl/clang-arm-toolchain.cmake deleted file mode 100644 index db28d2de..00000000 --- a/stm32-lvgl/clang-arm-toolchain.cmake +++ /dev/null @@ -1,21 +0,0 @@ -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_SYSTEM_PROCESSOR arm) -set(CMAKE_CROSSCOMPILING TRUE) - -# Specify the compilers -set(CMAKE_C_COMPILER "${TOOLCHAIN_PATH}/bin/clang") -set(CMAKE_CXX_COMPILER "${TOOLCHAIN_PATH}/bin/clang++") -set(CMAKE_ASM_COMPILER "${TOOLCHAIN_PATH}/bin/clang") - -# Target flags -set(CMAKE_C_FLAGS "-target arm-none-eabi -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -ffunction-sections -fdata-sections") -set(CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS} -std=c++11 -fno-exceptions -fno-rtti") -set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS}") - -# Search paths for libraries -set(CMAKE_FIND_ROOT_PATH "${TOOLCHAIN_PATH}") -set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) diff --git a/stm32-lvgl/fetch-dependencies.sh b/stm32-lvgl/fetch-dependencies.sh deleted file mode 100755 index 02e2eedc..00000000 --- a/stm32-lvgl/fetch-dependencies.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/bash - -set -vex - -### -### LLVM Embedded Toolchain for ARM -### - -VER=19.1.5 - -if [[ "$(uname -s)" == "Darwin" ]]; then - FILE=LLVM-ET-Arm-${VER}-Darwin-universal - EXT=dmg - SHA=0451e67dc9a9066c17f746c26654962fa3889d4df468db1245d1bae69438eaf5 -elif [[ "$(uname -s)" == "Linux" && "$(uname -m)" == "aarch64" ]]; then - FILE=LLVM-ET-Arm-${VER}-Linux-AArch64 - EXT=tar.xz - SHA=5e2f6b8c77464371ae2d7445114b4bdc19f56138e8aa864495181b52f57d0b85 -elif [[ "$(uname -s)" == "Linux" && "$(uname -m)" == "x86_64" ]]; then - FILE=LLVM-ET-Arm-${VER}-Linux-x86_64 - EXT=tar.xz - SHA=34ee877aadc78c5e9f067e603a1bc9745ed93ca7ae5dbfc9b4406508dc153920 -else - echo "No LLVM toolchain for this OS/arch ($(uname -s), $(uname -m))" - exit 1 -fi - -FOUND=no -SHA_MATCHES=no -if [[ -f /tmp/${FILE}.${EXT} ]]; then - FOUND=yes - if sha256 -c $SHA /tmp/${FILE}.${EXT}; then - SHA_MATCHES=yes - fi -fi - -if [[ "$FOUND" = "no" || "$SHA_MATCHES" = "no" ]]; then - curl https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-${VER}/${FILE}.${EXT} \ - -L -O --output-dir /tmp -fi - -if [[ "$EXT" = "dmg" ]]; then - hdiutil attach /tmp/${FILE}.${EXT} - ls -al /Volumes/${FILE} - rm -r ./llvm-toolchain || true - cp -a /Volumes/${FILE}/${FILE} ./llvm-toolchain - diskutil eject /Volumes/${FILE} -elif [[ "$EXT" = "tar.xz" ]]; then - rm -r ./llvm-toolchain || true - mkdir -p ./llvm-toolchain - tar -xvf /tmp/${FILE}.${EXT} -C ./llvm-toolchain --strip-components 1 -else - exit 1 -fi - - - -### -### LVGL -### - -rm -rf ./lvgl || true -git clone https://github.com/lvgl/lvgl.git --branch release/v9.2 diff --git a/stm32-lvgl/toolset.json b/stm32-lvgl/toolset.json deleted file mode 100644 index ba5ab791..00000000 --- a/stm32-lvgl/toolset.json +++ /dev/null @@ -1,44 +0,0 @@ -{ - "schemaVersion": "1.0", - "swiftCompiler": { - "extraCLIOptions": [ - "-Xfrontend", "-disable-stack-protector", - "-enable-experimental-feature", "Embedded", - "-enable-experimental-feature", "Extern", - "-Xclang-linker", "-nostdlib", - "-Xfrontend", "-function-sections", - "-Xfrontend", "-mergeable-symbols", - "-Xfrontend", "-enable-single-module-llvm-emission", - "-assert-config", "Debug", - "-Xclang-linker", "-fuse-ld=lld" - ] - }, - "cCompiler": { - "extraCLIOptions": [ - "-nostdlib", - "-ffunction-sections", - "-Illvm-toolchain/lib/clang-runtimes/arm-none-eabi/armv7m_soft_fpv4_sp_d16_exn_rtti/include", - "-mthumb", - "-Werror", - "-Wall", - "-static", - "-fno-stack-protector", - "-fno-common" - ] - }, - "linker": { - "extraCLIOptions": [ - "-nostdlib", - "-t", "-v", - "-T", "Sources/Support/linkerscript.ld", - "-Lllvm-toolchain/lib/clang-runtimes/arm-none-eabi/armv7m_soft_fpv4_sp_d16_exn_rtti/lib", - "-lc", - "-lclang_rt.builtins", - "-L.build/lvgl/lib", - "-llvgl", "-llvgl_demos", - "-static", - "-e", "_start_elf", - "--orphan-handling=error" - ] - } -} diff --git a/stm32-neopixel/Makefile b/stm32-neopixel/Makefile deleted file mode 100755 index 6b0125c0..00000000 --- a/stm32-neopixel/Makefile +++ /dev/null @@ -1,57 +0,0 @@ -##===----------------------------------------------------------------------===## -## -## This source file is part of the Swift open source project -## -## Copyright (c) 2025 Apple Inc. and the Swift project authors. -## Licensed under Apache License v2.0 with Runtime Library Exception -## -## See https://swift.org/LICENSE.txt for license information -## -##===----------------------------------------------------------------------===## - -# Paths -REPOROOT := $(shell git rev-parse --show-toplevel) -TOOLSROOT := $(REPOROOT)/Tools -TOOLSET := $(TOOLSROOT)/Toolsets/stm32f74x.json -MACHO2BIN := $(TOOLSROOT)/macho2bin.py -SWIFT_BUILD := swift build - -# Flags -ARCH := armv7em -TARGET := $(ARCH)-apple-none-macho -SWIFT_BUILD_ARGS := \ - --configuration release \ - --triple $(TARGET) \ - --toolset $(TOOLSET) -BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) - -.PHONY: build -build: - @echo "building..." - $(SWIFT_BUILD) \ - $(SWIFT_BUILD_ARGS) \ - -Xlinker -map -Xlinker $(BUILDROOT)/Application.mangled.map \ - --verbose - - @echo "demangling linker map..." - cat $(BUILDROOT)/Application.mangled.map \ - | c++filt | swift demangle > $(BUILDROOT)/Application.map - - @echo "disassembling..." - otool \ - -arch $(ARCH) -v -V -d -t \ - $(BUILDROOT)/Application \ - | c++filt | swift demangle > $(BUILDROOT)/Application.disassembly - - @echo "extracting binary..." - $(MACHO2BIN) \ - $(BUILDROOT)/Application \ - $(BUILDROOT)/Application.bin \ - --base-address 0x20010000 \ - --segments '__TEXT,__DATA,__VECTORS' - -.PHONY: clean -clean: - @echo "cleaning..." - @swift package clean - @rm -rf .build diff --git a/stm32-neopixel/Package.resolved b/stm32-neopixel/Package.resolved deleted file mode 100644 index e9d315fa..00000000 --- a/stm32-neopixel/Package.resolved +++ /dev/null @@ -1,33 +0,0 @@ -{ - "originHash" : "fec1335f7424378925c47a261a19ffe2160476fc1e6fd88c5e270ddff078da9d", - "pins" : [ - { - "identity" : "swift-argument-parser", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-argument-parser.git", - "state" : { - "revision" : "41982a3656a71c768319979febd796c6fd111d5c", - "version" : "1.5.0" - } - }, - { - "identity" : "swift-mmio", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-mmio", - "state" : { - "branch" : "main", - "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" - } - }, - { - "identity" : "swift-syntax", - "kind" : "remoteSourceControl", - "location" : "https://github.com/swiftlang/swift-syntax.git", - "state" : { - "revision" : "0687f71944021d616d34d922343dcef086855920", - "version" : "600.0.1" - } - } - ], - "version" : 3 -} diff --git a/stm32-neopixel/Package.swift b/stm32-neopixel/Package.swift deleted file mode 100644 index 972f744c..00000000 --- a/stm32-neopixel/Package.swift +++ /dev/null @@ -1,34 +0,0 @@ -// swift-tools-version: 6.0 - -import PackageDescription - -let package = Package( - name: "stm32-neopixel", - products: [ - .executable(name: "Application", targets: ["Application"]) - ], - dependencies: [ - .package(url: "https://github.com/apple/swift-mmio", branch: "main") - ], - targets: [ - .executableTarget( - name: "Application", - dependencies: ["STM32F7X6", "Support"]), - // SVD2Swift \ - // --input Sources/STM32F7X6/stm32f7x6.patched.svd \ - // --output Sources/STM32F7X6 \ - // --access-level public \ - // --indentation-width 2 \ - // --peripherals DMA1 DMA2 GPIOA GPIOB GPIOI RCC SPI1 SPI2 USART1 - .target( - name: "STM32F7X6", - dependencies: [ - .product(name: "MMIO", package: "swift-mmio") - ], - plugins: [ - // Plugin disabled because SwiftPM is slow. - // .plugin(name: "SVD2SwiftPlugin", package: "swift-mmio") - ]), - .target(name: "Support"), - ], - swiftLanguageModes: [.v5]) diff --git a/stm32-neopixel/README.md b/stm32-neopixel/README.md deleted file mode 100644 index d006b5da..00000000 --- a/stm32-neopixel/README.md +++ /dev/null @@ -1,30 +0,0 @@ -# stm32-neopixel - - - -This demo is designed to run on an STM32 microcontroller and some additional hardware, detailed below: - -1. An [STM32F746G Discovery kit](https://www.st.com/en/evaluation-tools/32f746gdiscovery.html) -2. A 3.3V to 5V level shifter such as [Texas Instrument's TXB0104](https://www.ti.com/lit/ds/symlink/txb0104.pdf) which can be found on a breakout board for easier use, such as: [SparkFun Voltage-Level Translator Breakout](https://www.sparkfun.com/products/11771) -3. A NeoPixel WS2812 or compatible LED Strip; such as: [SparkFun LED RGB Strip](https://www.sparkfun.com/products/15205) -4. A breadboard, such as: [SparkFun Translucent Breadboard](https://www.sparkfun.com/products/9567) -5. A 5V power supply - -Connect the components as shown in the schematic below: - -![schematic](./schematic.png) - -We recommend including a capacitor across the LED strip power supply. - -## How to build and run this example: - -- Connect the STM32F746G-DISCO board via the ST-LINK USB port to your Mac. -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- Install the `stlink` (https://github.com/stlink-org/stlink) command line tools, e.g. via `brew install stlink`. -- Build and upload the program to flash memory of the STM: -```console -$ cd stm32-neopixel -$ make -$ st-flash --reset write .build/release/Application.bin 0x08000000 -``` -- The LED strip should light up and slowly animate a color gradient. diff --git a/stm32-neopixel/Sources/Application/Application.swift b/stm32-neopixel/Sources/Application/Application.swift deleted file mode 100644 index 2daab9a9..00000000 --- a/stm32-neopixel/Sources/Application/Application.swift +++ /dev/null @@ -1,139 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import STM32F7X6 -import Support - -@main -public struct Application { - public static func main() { - #if arch(arm) - enableFaults() - enableFPU() - #endif - - // MARK: Clock configuration - // Disable PLL. - rcc.cr.modify { $1.raw.pllon = 0 } - - // Configure UART to always use HSI. - rcc.dckcfgr2.modify { $0.usart1sel = .HSI } - - // Configure PLL to convert the 16MHz HSI to a 12.8MHz SYSCLK. - // HSI is measured to be closer to 16.6Mhz on my device. - // The SPI bus must run at 6.4MHz which is achieved with a /2 prescalar. - // M = 10 - // N = 64 - // P = 8 - // ((16MHz / M ) * N) / P = 12.8MHz - - rcc.pllcfgr.modify { rw in - // Clear all non-reserved registers. - rw.raw.storage &= 0b1111_0000_1011_1100__1000_0000_0000_0000 - rw.raw.pllm = 10 // Set M constant - rw.raw.plln = 64 // Set N constant - rw.pllp = .Div8 // Set P constant - rw.pllsrc = .HSI // Select HSI PLL Source - } - - // Enable the PLL clock and wait for ready. - rcc.cr.modify { $1.raw.pllon = 1 } - while rcc.cr.read().raw.pllrdy != 1 {} - - // Change the SYSCLK mux to select the PLL clock and wait for ready. - rcc.cfgr.modify { rw in - rw.raw.sw = 0b10 // Select PLL clock. - rw.raw.hpre = 0 // system clock not divided - rw.raw.ppre1 = 0 // AHB clock not divided - rw.raw.ppre2 = 0 // AHB clock not divided - } - while rcc.cfgr.read().raw.sws != 0b10 {} - - // DMA - rcc.ahb1enr.modify { $0.raw.dma1en = 1 } - // GPIO - rcc.ahb1enr.modify { rw in - rw.raw.gpioaen = 1 - rw.raw.gpioben = 1 - rw.raw.gpioien = 1 - } - // SPI - rcc.apb1enr.modify { $0.raw.spi2en = 1 } - // UART - rcc.apb2enr.modify { $0.raw.usart1en = 1 } - - // MARK: Peripheral Configuration - // GPIO - SPI pin configuration - gpiob.configure( - pin: 15, - as: .init( - mode: .alternateFunction, - outputType: .pushPull, - outputSpeed: .max, - pull: .none, - alternateFunction: 5)) - gpioi.configure( - pin: 1, - as: .init( - mode: .alternateFunction, - outputType: .pushPull, - outputSpeed: .max, - pull: .none, - alternateFunction: 5)) - - // GPIO - UART pin configuration - gpioa.configure( - pin: 9, - as: .init( - mode: .alternateFunction, - outputType: .pushPull, - outputSpeed: .low, - pull: .none, - alternateFunction: 7)) - gpiob.configure( - pin: 7, - as: .init( - mode: .alternateFunction, - outputType: .pushPull, - outputSpeed: .low, - pull: .none, - alternateFunction: 7)) - - // UART configuration - usart1.brr.modify { $0.raw.brr_field = 16_000_000 / 115200 } - usart1.cr1.modify { rw in - rw.ue = .Enabled - rw.re = .Enabled - rw.te = .Enabled - } - - // MARK: Main loop - print("Hello Swift!") - var neoPixel = SPINeoPixel(dma: dma1, spi: spi2, pixelCount: 60) - while true { - neoPixel.rainbow() - neoPixel.draw() - } - } -} - -@_cdecl("Default_Handler") -public func defaultHandler() { - while true {} -} - -@_cdecl("putchar") -public func putchar(_ value: CInt) -> CInt { - while usart1.isr.read().raw.txe == 0 {} - usart1.tdr.modify { $0.raw.tdr_field = UInt32(value) } - while usart1.isr.read().raw.txe == 0 {} - return 0 -} diff --git a/stm32-neopixel/Sources/Application/GPIO.swift b/stm32-neopixel/Sources/Application/GPIO.swift deleted file mode 100644 index 8e24b427..00000000 --- a/stm32-neopixel/Sources/Application/GPIO.swift +++ /dev/null @@ -1,111 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import STM32F7X6 - -extension GPIOA { - enum Mode: UInt32 { - case input = 0x0 - case output = 0x1 - case alternateFunction = 0x2 - case analog = 0x3 - } - - enum OutputType: UInt32 { - case pushPull = 0x0 - case openDrain = 0x1 - } - - enum OutputSpeed: UInt32 { - case low = 0x0 - case medium = 0x1 - case high = 0x2 - case max = 0x3 - } - - enum Pull: UInt32 { - case `none` = 0x0 - case up = 0x1 - case down = 0x2 - } - - struct Configuration { - var mode: Mode - var outputType: OutputType - var outputSpeed: OutputSpeed - var pull: Pull - var alternateFunction: UInt32 - } - - func configure(pin: Int, as configuration: Configuration) { - self.moder.modify { rw in - rw.raw.storage.set( - value: configuration.mode.rawValue, - mask: 0b11, - offset: pin * 2) - } - - // Comprised of 16 x 1 bit fields. - self.otyper.modify { rw in - rw.raw.storage.set( - value: configuration.outputType.rawValue, - mask: 0b1, - offset: pin) - } - - // Comprised of 16 x 2 bit fields. - self.ospeedr.modify { rw in - rw.raw.storage.set( - value: configuration.outputSpeed.rawValue, - mask: 0b11, - offset: pin * 2) - } - - // Comprised of 16 x 2 bit fields. - self.pupdr.modify { rw in - rw.raw.storage.set( - value: configuration.pull.rawValue, - mask: 0b11, - offset: pin * 2) - } - - // Comprised of 16 x 4 bit fields, split across 2 registers. - if pin < 8 { - self.afrl.modify { rw in - rw.raw.storage.set( - value: configuration.alternateFunction, - mask: 0b1111, - offset: pin * 4) - } - } else { - self.afrh.modify { rw in - rw.raw.storage.set( - value: configuration.alternateFunction, - mask: 0b1111, - offset: (pin - 8) * 4) - } - } - } -} - -extension UInt32 { - fileprivate func get(mask: Self, offset: UInt8) -> Self { - let mask = mask &<< offset - return (self & mask) &>> offset - } - - fileprivate mutating func set(value: Self, mask: Self, offset: Int) { - let mask = mask &<< offset - let oldValue: UInt32 = self & ~mask - let newValue: UInt32 = (value &<< offset) & mask - self = oldValue | newValue - } -} diff --git a/stm32-neopixel/Sources/Application/Neopixel/HSV8Pixel.swift b/stm32-neopixel/Sources/Application/Neopixel/HSV8Pixel.swift deleted file mode 100644 index e13190e4..00000000 --- a/stm32-neopixel/Sources/Application/Neopixel/HSV8Pixel.swift +++ /dev/null @@ -1,16 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct HSV8Pixel { - var hue: UInt8 - var saturation: UInt8 - var value: UInt8 -} diff --git a/stm32-neopixel/Sources/Application/Neopixel/RGB8Pixel.swift b/stm32-neopixel/Sources/Application/Neopixel/RGB8Pixel.swift deleted file mode 100644 index 9188c2af..00000000 --- a/stm32-neopixel/Sources/Application/Neopixel/RGB8Pixel.swift +++ /dev/null @@ -1,118 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct RGB8Pixel { - var red: UInt8 - var green: UInt8 - var blue: UInt8 -} - -extension RGB8Pixel { - init(_ pixel: SPINeoPixelGRB64Pixel) { - self.red = .rawChannel(neoPixelChannel: pixel.red) - self.green = .rawChannel(neoPixelChannel: pixel.green) - self.blue = .rawChannel(neoPixelChannel: pixel.blue) - } -} - -extension RGB8Pixel { - @inline(never) - init(_ pixel: HSV8Pixel) { - // Fast path: gray scale. - guard pixel.saturation != 0 else { - self.red = pixel.value - self.green = pixel.value - self.blue = pixel.value - return - } - - // Slow path: compute each color component. - var hue = Float32(pixel.hue) / Float32(UInt8.max) - let saturation = Float32(pixel.saturation) / Float32(UInt8.max) - let value = Float32(pixel.value) / Float32(UInt8.max) - - let clampedHue = max(0, min(1 - .ulpOfOne, hue)) - let scaledHue = clampedHue * 6 - let sector = UInt8(scaledHue) - hue = scaledHue - Float32(sector) - - let fractionalChannel1 = value * (1.0 - (saturation * (1.0 - 0.0))) - let fractionalChannel2 = value * (1.0 - (saturation * (hue - 0.0))) - let fractionalChannel3 = value * (1.0 - (saturation * (1.0 - hue))) - - let channel1 = UInt8(fractionalChannel1 * Float32(UInt8.max)) - let channel2 = UInt8(fractionalChannel2 * Float32(UInt8.max)) - let channel3 = UInt8(fractionalChannel3 * Float32(UInt8.max)) - - switch sector { - case 0: - self.red = pixel.value - self.green = channel3 - self.blue = channel1 - case 1: - self.red = channel2 - self.green = pixel.value - self.blue = channel1 - case 2: - self.red = channel1 - self.green = pixel.value - self.blue = channel3 - case 3: - self.red = channel1 - self.green = channel2 - self.blue = pixel.value - case 4: - self.red = channel3 - self.green = channel1 - self.blue = pixel.value - case 5: - self.red = pixel.value - self.green = channel1 - self.blue = channel2 - default: - fatalError("Unreachable") - } - } -} - -extension RGB8Pixel { - static let gammaCorrection: [UInt8] = [ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, - 2, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 5, 5, 5, - 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, - 10, 10, 11, 11, 11, 12, 12, 13, 13, 13, 14, 14, 15, 15, 16, 16, - 17, 17, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22, 23, 24, 24, 25, - 25, 26, 27, 27, 28, 29, 29, 30, 31, 32, 32, 33, 34, 35, 35, 36, - 37, 38, 39, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 50, - 51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 66, 67, 68, - 69, 70, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 85, 86, 87, 89, - 90, 92, 93, 95, 96, 98, 99, 101, 102, 104, 105, 107, 109, 110, 112, 114, - 115, 117, 119, 120, 122, 124, 126, 127, 129, 131, 133, 135, 137, 138, 140, - 142, - 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 167, 169, 171, 173, - 175, - 177, 180, 182, 184, 186, 189, 191, 193, 196, 198, 200, 203, 205, 208, 210, - 213, - 215, 218, 220, 223, 225, 228, 231, 233, 236, 239, 241, 244, 247, 249, 252, - 255, - ] - - var gammaCorrected: Self { - RGB8Pixel( - red: Self.gammaCorrection[Int(self.red)], - green: Self.gammaCorrection[Int(self.green)], - blue: Self.gammaCorrection[Int(self.blue)]) - } -} - -extension RGB8Pixel: Equatable {} diff --git a/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift b/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift deleted file mode 100644 index c130ce5e..00000000 --- a/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift +++ /dev/null @@ -1,204 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import STM32F7X6 - -class PixelBuffer { - let buffer: UnsafeMutableBufferPointer - - init(count: Int) { - self.buffer = .allocate(capacity: count) - self.buffer.initialize(repeating: .reset) - } - - deinit { - self.buffer.deallocate() - } -} - -struct SPINeoPixel { - var dma: DMA1 - var spi: SPI2 - var pixels: PixelBuffer - var base: UInt8 = 0 - - init( - dma: DMA1, - spi: SPI2, - pixelCount: Int - ) { - precondition(MemoryLayout.size == 24) - precondition(MemoryLayout.stride == 24) - self.dma = dma - self.spi = spi - self.pixels = PixelBuffer(count: pixelCount) - } -} - -extension SPINeoPixel { - @inline(never) - mutating func clear() { - let rgb = RGB8Pixel(red: 0, green: 0, blue: 0) - let pixel = SPINeoPixelGRB64Pixel(rgb) - for index in self.pixels.buffer.indices { - self.pixels.buffer[index] = pixel - } - } - - @inline(never) - mutating func rainbow() { - var hsv = HSV8Pixel(hue: self.base, saturation: 255, value: 255) - for index in self.pixels.buffer.indices { - hsv.hue &+= 1 - let rgb = RGB8Pixel(hsv) - self.pixels.buffer[index] = SPINeoPixelGRB64Pixel(rgb.gammaCorrected) - } - self.base &+= 1 - } - - @inline(never) - mutating func draw() { - // swift-format-ignore: NeverForceUnwrap - let memory = UInt32(UInt(bitPattern: self.pixels.buffer.baseAddress!)) - let peripheral = UInt32(spi.dr.unsafeAddress) - let count = UInt32( - self.pixels.buffer.count * MemoryLayout.size) - - let index = 4 - self.dma.st[index].cr.modify { rw in - rw.raw.chsel = 0 // Set the DMA channel to 0 (spi tx). - rw.raw.mburst = 0b00 // Set memory to single transaction mode. - rw.pburst = .Single // Set peripheral to single transaction mode. - // ct - rw.dbm = .Disabled // Disable double buffer mode. - rw.pl = .VeryHigh // Set the stream priority to very high. - // pincos - rw.raw.msize = 0b00 // Set memory data width to 8 bit. - rw.psize = .Bits8 // Set peripheral data width to 8 bit. - rw.raw.minc = 1 // Set memory to incremented mode. - rw.pinc = .Fixed // Set peripheral to fixed (no-increment) mode. - rw.circ = .Disabled // Disable circular mode. - rw.dir = .MemoryToPeripheral // Set transfer direction. - rw.pfctrl = .DMA // Set the DMA as the flow controller. - rw.tcie = .Enabled // Enable transfer complete interrupt. - rw.htie = .Enabled // Enable half transfer interrupt. - rw.teie = .Enabled // Enable transfer error interrupt. - rw.dmeie = .Enabled // Enable direct mode error interrupt. - } - - // Set the total number of data items to the buffer size. - self.dma.st[index].ndtr.modify { $0.raw.ndt = UInt32(count) } - - // Set the destination peripheral port address to the spi data port. - self.dma.st[index].par.modify { $0.raw.pa = peripheral } - - // Set the source memory address to the buffer's base. - self.dma.st[index].m0ar.modify { $0.raw.m0a = memory } - - // Clear the second memory address as double buffering mode is disabled. - self.dma.st[index].m1ar.modify { $0.raw.m1a = 0 } - - self.dma.st[index].fcr.modify { _, w in - w.feie = .Enabled // Enable FIFO error interrupt. - w.dmdis = .Disabled // Enable direct mode (double negative). - w.fth = .Quarter // Reset FIFO threshold (no effect in direct mode). - } - - self.dma.hifcr.modify { _, w in - w.raw.ctcif4 = 1 // Clear transfer complete interrupt flag. - w.raw.chtif4 = 1 // Clear half transfer interrupt flag. - w.raw.cteif4 = 1 // Clear transfer error interrupt flag. - w.raw.cdmeif4 = 1 // Clear direct mode error interrupt flag. - w.raw.cfeif4 = 1 // Clear FIFO error interrupt flag. - } - - self.spi.cr1.modify { rw in - rw.bidimode = .Unidirectional // Set full duplex. - rw.bidioe = .OutputDisabled - rw.crcen = .Disabled // Disable hardware crc. - rw.crcnext = .TxBuffer - rw.crcl = .EightBit - rw.rxonly = .FullDuplex // Set full duplex. - // FIXME: understand this Disable software slave management and select. - rw.ssm = .Enabled - rw.ssi = .SlaveNotSelected - rw.lsbfirst = .MSBFirst // Set data MSB first. - // spe - rw.br = .Div2 // Set Baud Rate as Fpclk/2. - rw.mstr = .Master // Set Master mode. - rw.cpol = .IdleLow // Set active high logic. - // FIXME: understand this Set trailing edge logic. - rw.cpha = .SecondEdge - } - - // Write to SPI_CR2 register: - // a) Configure the DS[3:0] bits to select the data length for the transfer. - // b) Configure SSOE (Notes: 1 & 2 & 3). - // c) Set the FRF bit if the TI protocol is required (keep NSSP bit cleared - // in TI mode). - // d) Set the NSSP bit if the NSS pulse mode between two data units is - // required (keep CHPA and TI bits cleared in NSSP mode). - // e) Configure the FRXTH bit. The RXFIFO threshold must be aligned to the - // read access size for the SPIx_DR register. - // f) Initialize LDMA_TX and LDMA_RX bits if DMA is used in packed mode. - - self.spi.cr2.modify { rw in - rw.rxdmaen = .Disabled // Disable rx dma. - rw.txdmaen = .Enabled // Enable tx dma. - // FIXME: understand this Disable slave select. - // rw.ssoe = 0 - // FIXME: understand this Disable NSS pulse management. - // rw.nssp = 0 - rw.frf = .Motorola // Reset frame format (i2s). - rw.errie = .NotMasked // Enable error interrupt. - rw.rxneie = .NotMasked // Enable rx not buffer empty interrupt. - rw.txeie = .NotMasked // Enable tx buffer empty interrupt. - rw.ds = .EightBit // Set Data size to 8 bit. - rw.frxth = .Quarter // Set RXNE if FIFO <8 bits. - rw.ldma_rx = .Even // Reset dma reception length. - rw.ldma_tx = .Even // Reset dma transmission length. - } - - // Activate the stream. - self.dma.st[index].cr.modify { $0.en = .Enabled } - - // Activate the SPI peripheral - self.spi.cr1.modify { $0.spe = .Enabled } - - func wait() -> Bool { - while true { - let hisr = self.dma.hisr.read().raw - if hisr.tcif4 == 1 { return true } - if hisr.teif4 == 1 { return false } - if hisr.dmeif4 == 1 { return false } - if hisr.feif4 == 1 { return false } - } - } - - _ = wait() - - // Wait until no more data to transmit. - while self.spi.sr.read().raw.ftlvl != 0b00 {} - // Wait until the last data frame is processed. - while self.spi.sr.read().raw.bsy != 0 {} - // Disable the SPI peripheral. - self.spi.cr1.modify { $0.spe = .Disabled } - // Don't wait until the read data is received since the NeoPixel is not - // a real SPI device. This will lead to overrun errors but they can be - // safely ignored. - // while self.spi.sr.read().raw.frlvl != 0b00 { } - - // Disable any existing DMA transfer on stream 0. - self.dma.st[index].cr.modify { $0.en = .Disabled } - // Wait for the DMA stream to actually shutdown. - while self.dma.st[index].cr.read().en != .Disabled {} - } -} diff --git a/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixelBit.swift b/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixelBit.swift deleted file mode 100644 index daa239aa..00000000 --- a/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixelBit.swift +++ /dev/null @@ -1,16 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -enum SPINeoPixelBit: UInt8 { - case reset = 0b0000_0000 - case zero = 0b1100_0000 - case one = 0b1111_1000 -} diff --git a/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixelGRB64Pixel.swift b/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixelGRB64Pixel.swift deleted file mode 100644 index 5cd09488..00000000 --- a/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixelGRB64Pixel.swift +++ /dev/null @@ -1,63 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -struct SPINeoPixelGRB64Pixel { - var green: UInt64 - var red: UInt64 - var blue: UInt64 -} - -extension SPINeoPixelGRB64Pixel { - static let reset = Self(green: 0, red: 0, blue: 0) -} - -extension SPINeoPixelGRB64Pixel { - init(_ pixel: RGB8Pixel) { - self.green = .neoPixelChannel(rawChannel: pixel.green) - self.red = .neoPixelChannel(rawChannel: pixel.red) - self.blue = .neoPixelChannel(rawChannel: pixel.blue) - } -} - -extension UInt64 { - static func neoPixelChannel(rawChannel: UInt8) -> Self { - var rawChannel = rawChannel - var neoPixelChannel: Self = 0 - for _ in 0..>= 1 - neoPixelChannel <<= 8 - neoPixelChannel |= Self(bit.rawValue) - } - return neoPixelChannel - } -} - -extension UInt8 { - static func rawChannel(neoPixelChannel: UInt64) -> Self { - var neoPixelChannel = neoPixelChannel - var rawChannel: Self = 0 - for _ in 0..>= 8 - rawChannel <<= 1 - rawChannel |= UInt8(bit) - } - return rawChannel - } -} diff --git a/stm32-neopixel/Sources/STM32F7X6/DMA1.swift b/stm32-neopixel/Sources/STM32F7X6/DMA1.swift deleted file mode 100644 index a8ad2dab..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/DMA1.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// DMA controller -public typealias DMA1 = DMA2 - diff --git a/stm32-neopixel/Sources/STM32F7X6/DMA2.swift b/stm32-neopixel/Sources/STM32F7X6/DMA2.swift deleted file mode 100644 index 8b61636f..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/DMA2.swift +++ /dev/null @@ -1,893 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// DMA controller -@RegisterBlock -public struct DMA2 { - /// low interrupt status register - @RegisterBlock(offset: 0x0) - public var lisr: Register - - /// high interrupt status register - @RegisterBlock(offset: 0x4) - public var hisr: Register - - /// low interrupt flag clear register - @RegisterBlock(offset: 0x8) - public var lifcr: Register - - /// high interrupt flag clear register - @RegisterBlock(offset: 0xc) - public var hifcr: Register - - /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers - @RegisterBlock(offset: 0x10, stride: 0x18, count: 8) - public var st: RegisterArray -} - -extension DMA2 { - /// low interrupt status register - @Register(bitWidth: 32) - public struct LISR { - /// Stream x transfer complete interrupt flag (x = 3..0) - @ReadOnly(bits: 27..<28) - public var tcif3: TCIF3 - - /// Stream x half transfer interrupt flag (x=3..0) - @ReadOnly(bits: 26..<27) - public var htif3: HTIF3 - - /// Stream x transfer error interrupt flag (x=3..0) - @ReadOnly(bits: 25..<26) - public var teif3: TEIF3 - - /// Stream x direct mode error interrupt flag (x=3..0) - @ReadOnly(bits: 24..<25) - public var dmeif3: DMEIF3 - - /// Stream x FIFO error interrupt flag (x=3..0) - @ReadOnly(bits: 22..<23) - public var feif3: FEIF3 - - /// Stream x transfer complete interrupt flag (x = 3..0) - @ReadOnly(bits: 21..<22) - public var tcif2: TCIF2 - - /// Stream x half transfer interrupt flag (x=3..0) - @ReadOnly(bits: 20..<21) - public var htif2: HTIF2 - - /// Stream x transfer error interrupt flag (x=3..0) - @ReadOnly(bits: 19..<20) - public var teif2: TEIF2 - - /// Stream x direct mode error interrupt flag (x=3..0) - @ReadOnly(bits: 18..<19) - public var dmeif2: DMEIF2 - - /// Stream x FIFO error interrupt flag (x=3..0) - @ReadOnly(bits: 16..<17) - public var feif2: FEIF2 - - /// Stream x transfer complete interrupt flag (x = 3..0) - @ReadOnly(bits: 11..<12) - public var tcif1: TCIF1 - - /// Stream x half transfer interrupt flag (x=3..0) - @ReadOnly(bits: 10..<11) - public var htif1: HTIF1 - - /// Stream x transfer error interrupt flag (x=3..0) - @ReadOnly(bits: 9..<10) - public var teif1: TEIF1 - - /// Stream x direct mode error interrupt flag (x=3..0) - @ReadOnly(bits: 8..<9) - public var dmeif1: DMEIF1 - - /// Stream x FIFO error interrupt flag (x=3..0) - @ReadOnly(bits: 6..<7) - public var feif1: FEIF1 - - /// Stream x transfer complete interrupt flag (x = 3..0) - @ReadOnly(bits: 5..<6) - public var tcif0: TCIF0 - - /// Stream x half transfer interrupt flag (x=3..0) - @ReadOnly(bits: 4..<5) - public var htif0: HTIF0 - - /// Stream x transfer error interrupt flag (x=3..0) - @ReadOnly(bits: 3..<4) - public var teif0: TEIF0 - - /// Stream x direct mode error interrupt flag (x=3..0) - @ReadOnly(bits: 2..<3) - public var dmeif0: DMEIF0 - - /// Stream x FIFO error interrupt flag (x=3..0) - @ReadOnly(bits: 0..<1) - public var feif0: FEIF0 - } - - /// high interrupt status register - @Register(bitWidth: 32) - public struct HISR { - /// Stream x transfer complete interrupt flag (x=7..4) - @ReadOnly(bits: 27..<28) - public var tcif7: TCIF7 - - /// Stream x half transfer interrupt flag (x=7..4) - @ReadOnly(bits: 26..<27) - public var htif7: HTIF7 - - /// Stream x transfer error interrupt flag (x=7..4) - @ReadOnly(bits: 25..<26) - public var teif7: TEIF7 - - /// Stream x direct mode error interrupt flag (x=7..4) - @ReadOnly(bits: 24..<25) - public var dmeif7: DMEIF7 - - /// Stream x FIFO error interrupt flag (x=7..4) - @ReadOnly(bits: 22..<23) - public var feif7: FEIF7 - - /// Stream x transfer complete interrupt flag (x=7..4) - @ReadOnly(bits: 21..<22) - public var tcif6: TCIF6 - - /// Stream x half transfer interrupt flag (x=7..4) - @ReadOnly(bits: 20..<21) - public var htif6: HTIF6 - - /// Stream x transfer error interrupt flag (x=7..4) - @ReadOnly(bits: 19..<20) - public var teif6: TEIF6 - - /// Stream x direct mode error interrupt flag (x=7..4) - @ReadOnly(bits: 18..<19) - public var dmeif6: DMEIF6 - - /// Stream x FIFO error interrupt flag (x=7..4) - @ReadOnly(bits: 16..<17) - public var feif6: FEIF6 - - /// Stream x transfer complete interrupt flag (x=7..4) - @ReadOnly(bits: 11..<12) - public var tcif5: TCIF5 - - /// Stream x half transfer interrupt flag (x=7..4) - @ReadOnly(bits: 10..<11) - public var htif5: HTIF5 - - /// Stream x transfer error interrupt flag (x=7..4) - @ReadOnly(bits: 9..<10) - public var teif5: TEIF5 - - /// Stream x direct mode error interrupt flag (x=7..4) - @ReadOnly(bits: 8..<9) - public var dmeif5: DMEIF5 - - /// Stream x FIFO error interrupt flag (x=7..4) - @ReadOnly(bits: 6..<7) - public var feif5: FEIF5 - - /// Stream x transfer complete interrupt flag (x=7..4) - @ReadOnly(bits: 5..<6) - public var tcif4: TCIF4 - - /// Stream x half transfer interrupt flag (x=7..4) - @ReadOnly(bits: 4..<5) - public var htif4: HTIF4 - - /// Stream x transfer error interrupt flag (x=7..4) - @ReadOnly(bits: 3..<4) - public var teif4: TEIF4 - - /// Stream x direct mode error interrupt flag (x=7..4) - @ReadOnly(bits: 2..<3) - public var dmeif4: DMEIF4 - - /// Stream x FIFO error interrupt flag (x=7..4) - @ReadOnly(bits: 0..<1) - public var feif4: FEIF4 - } - - /// low interrupt flag clear register - @Register(bitWidth: 32) - public struct LIFCR { - /// Stream x clear transfer complete interrupt flag (x = 3..0) - @WriteOnly(bits: 27..<28) - public var ctcif3: CTCIF3 - - /// Stream x clear half transfer interrupt flag (x = 3..0) - @WriteOnly(bits: 26..<27) - public var chtif3: CHTIF3 - - /// Stream x clear transfer error interrupt flag (x = 3..0) - @WriteOnly(bits: 25..<26) - public var cteif3: CTEIF3 - - /// Stream x clear direct mode error interrupt flag (x = 3..0) - @WriteOnly(bits: 24..<25) - public var cdmeif3: CDMEIF3 - - /// Stream x clear FIFO error interrupt flag (x = 3..0) - @WriteOnly(bits: 22..<23) - public var cfeif3: CFEIF3 - - /// Stream x clear transfer complete interrupt flag (x = 3..0) - @WriteOnly(bits: 21..<22) - public var ctcif2: CTCIF2 - - /// Stream x clear half transfer interrupt flag (x = 3..0) - @WriteOnly(bits: 20..<21) - public var chtif2: CHTIF2 - - /// Stream x clear transfer error interrupt flag (x = 3..0) - @WriteOnly(bits: 19..<20) - public var cteif2: CTEIF2 - - /// Stream x clear direct mode error interrupt flag (x = 3..0) - @WriteOnly(bits: 18..<19) - public var cdmeif2: CDMEIF2 - - /// Stream x clear FIFO error interrupt flag (x = 3..0) - @WriteOnly(bits: 16..<17) - public var cfeif2: CFEIF2 - - /// Stream x clear transfer complete interrupt flag (x = 3..0) - @WriteOnly(bits: 11..<12) - public var ctcif1: CTCIF1 - - /// Stream x clear half transfer interrupt flag (x = 3..0) - @WriteOnly(bits: 10..<11) - public var chtif1: CHTIF1 - - /// Stream x clear transfer error interrupt flag (x = 3..0) - @WriteOnly(bits: 9..<10) - public var cteif1: CTEIF1 - - /// Stream x clear direct mode error interrupt flag (x = 3..0) - @WriteOnly(bits: 8..<9) - public var cdmeif1: CDMEIF1 - - /// Stream x clear FIFO error interrupt flag (x = 3..0) - @WriteOnly(bits: 6..<7) - public var cfeif1: CFEIF1 - - /// Stream x clear transfer complete interrupt flag (x = 3..0) - @WriteOnly(bits: 5..<6) - public var ctcif0: CTCIF0 - - /// Stream x clear half transfer interrupt flag (x = 3..0) - @WriteOnly(bits: 4..<5) - public var chtif0: CHTIF0 - - /// Stream x clear transfer error interrupt flag (x = 3..0) - @WriteOnly(bits: 3..<4) - public var cteif0: CTEIF0 - - /// Stream x clear direct mode error interrupt flag (x = 3..0) - @WriteOnly(bits: 2..<3) - public var cdmeif0: CDMEIF0 - - /// Stream x clear FIFO error interrupt flag (x = 3..0) - @WriteOnly(bits: 0..<1) - public var cfeif0: CFEIF0 - } - - /// high interrupt flag clear register - @Register(bitWidth: 32) - public struct HIFCR { - /// Stream x clear transfer complete interrupt flag (x = 7..4) - @WriteOnly(bits: 27..<28) - public var ctcif7: CTCIF7 - - /// Stream x clear half transfer interrupt flag (x = 7..4) - @WriteOnly(bits: 26..<27) - public var chtif7: CHTIF7 - - /// Stream x clear transfer error interrupt flag (x = 7..4) - @WriteOnly(bits: 25..<26) - public var cteif7: CTEIF7 - - /// Stream x clear direct mode error interrupt flag (x = 7..4) - @WriteOnly(bits: 24..<25) - public var cdmeif7: CDMEIF7 - - /// Stream x clear FIFO error interrupt flag (x = 7..4) - @WriteOnly(bits: 22..<23) - public var cfeif7: CFEIF7 - - /// Stream x clear transfer complete interrupt flag (x = 7..4) - @WriteOnly(bits: 21..<22) - public var ctcif6: CTCIF6 - - /// Stream x clear half transfer interrupt flag (x = 7..4) - @WriteOnly(bits: 20..<21) - public var chtif6: CHTIF6 - - /// Stream x clear transfer error interrupt flag (x = 7..4) - @WriteOnly(bits: 19..<20) - public var cteif6: CTEIF6 - - /// Stream x clear direct mode error interrupt flag (x = 7..4) - @WriteOnly(bits: 18..<19) - public var cdmeif6: CDMEIF6 - - /// Stream x clear FIFO error interrupt flag (x = 7..4) - @WriteOnly(bits: 16..<17) - public var cfeif6: CFEIF6 - - /// Stream x clear transfer complete interrupt flag (x = 7..4) - @WriteOnly(bits: 11..<12) - public var ctcif5: CTCIF5 - - /// Stream x clear half transfer interrupt flag (x = 7..4) - @WriteOnly(bits: 10..<11) - public var chtif5: CHTIF5 - - /// Stream x clear transfer error interrupt flag (x = 7..4) - @WriteOnly(bits: 9..<10) - public var cteif5: CTEIF5 - - /// Stream x clear direct mode error interrupt flag (x = 7..4) - @WriteOnly(bits: 8..<9) - public var cdmeif5: CDMEIF5 - - /// Stream x clear FIFO error interrupt flag (x = 7..4) - @WriteOnly(bits: 6..<7) - public var cfeif5: CFEIF5 - - /// Stream x clear transfer complete interrupt flag (x = 7..4) - @WriteOnly(bits: 5..<6) - public var ctcif4: CTCIF4 - - /// Stream x clear half transfer interrupt flag (x = 7..4) - @WriteOnly(bits: 4..<5) - public var chtif4: CHTIF4 - - /// Stream x clear transfer error interrupt flag (x = 7..4) - @WriteOnly(bits: 3..<4) - public var cteif4: CTEIF4 - - /// Stream x clear direct mode error interrupt flag (x = 7..4) - @WriteOnly(bits: 2..<3) - public var cdmeif4: CDMEIF4 - - /// Stream x clear FIFO error interrupt flag (x = 7..4) - @WriteOnly(bits: 0..<1) - public var cfeif4: CFEIF4 - } - - /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers - @RegisterBlock - public struct ST { - /// stream x configuration register - @RegisterBlock(offset: 0x0) - public var cr: Register - - /// stream x number of data register - @RegisterBlock(offset: 0x4) - public var ndtr: Register - - /// stream x peripheral address register - @RegisterBlock(offset: 0x8) - public var par: Register - - /// stream x memory 0 address register - @RegisterBlock(offset: 0xc) - public var m0ar: Register - - /// stream x memory 1 address register - @RegisterBlock(offset: 0x10) - public var m1ar: Register - - /// stream x FIFO control register - @RegisterBlock(offset: 0x14) - public var fcr: Register - } -} - -extension DMA2.ST { - /// stream x configuration register - @Register(bitWidth: 32) - public struct CR { - /// Channel selection - @ReadWrite(bits: 25..<28) - public var chsel: CHSEL - - /// Memory burst transfer configuration - @ReadWrite(bits: 23..<25) - public var mburst: MBURST - - /// Peripheral burst transfer configuration - @ReadWrite(bits: 21..<23, as: PBURSTValues.self) - public var pburst: PBURST - - /// Current target (only in double buffer mode) - @ReadWrite(bits: 19..<20, as: CTValues.self) - public var ct: CT - - /// Double buffer mode - @ReadWrite(bits: 18..<19, as: DBMValues.self) - public var dbm: DBM - - /// Priority level - @ReadWrite(bits: 16..<18, as: PLValues.self) - public var pl: PL - - /// Peripheral increment offset size - @ReadWrite(bits: 15..<16, as: PINCOSValues.self) - public var pincos: PINCOS - - /// Memory data size - @ReadWrite(bits: 13..<15) - public var msize: MSIZE - - /// Peripheral data size - @ReadWrite(bits: 11..<13, as: PSIZEValues.self) - public var psize: PSIZE - - /// Memory increment mode - @ReadWrite(bits: 10..<11) - public var minc: MINC - - /// Peripheral increment mode - @ReadWrite(bits: 9..<10, as: PINCValues.self) - public var pinc: PINC - - /// Circular mode - @ReadWrite(bits: 8..<9, as: CIRCValues.self) - public var circ: CIRC - - /// Data transfer direction - @ReadWrite(bits: 6..<8, as: DIRValues.self) - public var dir: DIR - - /// Peripheral flow controller - @ReadWrite(bits: 5..<6, as: PFCTRLValues.self) - public var pfctrl: PFCTRL - - /// Transfer complete interrupt enable - @ReadWrite(bits: 4..<5, as: TCIEValues.self) - public var tcie: TCIE - - /// Half transfer interrupt enable - @ReadWrite(bits: 3..<4, as: HTIEValues.self) - public var htie: HTIE - - /// Transfer error interrupt enable - @ReadWrite(bits: 2..<3, as: TEIEValues.self) - public var teie: TEIE - - /// Direct mode error interrupt enable - @ReadWrite(bits: 1..<2, as: DMEIEValues.self) - public var dmeie: DMEIE - - /// Stream enable / flag stream ready when read low - @ReadWrite(bits: 0..<1, as: ENValues.self) - public var en: EN - } - - /// stream x number of data register - @Register(bitWidth: 32) - public struct NDTR { - /// Number of data items to transfer - @ReadWrite(bits: 0..<16) - public var ndt: NDT - } - - /// stream x peripheral address register - @Register(bitWidth: 32) - public struct PAR { - /// Peripheral address - @ReadWrite(bits: 0..<32) - public var pa: PA - } - - /// stream x memory 0 address register - @Register(bitWidth: 32) - public struct M0AR { - /// Memory 0 address - @ReadWrite(bits: 0..<32) - public var m0a: M0A - } - - /// stream x memory 1 address register - @Register(bitWidth: 32) - public struct M1AR { - /// Memory 1 address (used in case of Double buffer mode) - @ReadWrite(bits: 0..<32) - public var m1a: M1A - } - - /// stream x FIFO control register - @Register(bitWidth: 32) - public struct FCR { - /// FIFO error interrupt enable - @ReadWrite(bits: 7..<8, as: FEIEValues.self) - public var feie: FEIE - - /// FIFO status - @ReadOnly(bits: 3..<6) - public var fs: FS - - /// Direct mode disable - @ReadWrite(bits: 2..<3, as: DMDISValues.self) - public var dmdis: DMDIS - - /// FIFO threshold selection - @ReadWrite(bits: 0..<2, as: FTHValues.self) - public var fth: FTH - } -} - -extension DMA2.ST.CR { - public struct PBURSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Single transfer - public static let Single = Self(rawValue: 0x0) - - /// Incremental burst of 4 beats - public static let INCR4 = Self(rawValue: 0x1) - - /// Incremental burst of 8 beats - public static let INCR8 = Self(rawValue: 0x2) - - /// Incremental burst of 16 beats - public static let INCR16 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct CTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The current target memory is Memory 0 - public static let Memory0 = Self(rawValue: 0x0) - - /// The current target memory is Memory 1 - public static let Memory1 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct DBMValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// No buffer switching at the end of transfer - public static let Disabled = Self(rawValue: 0x0) - - /// Memory target switched at the end of the DMA transfer - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct PLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Low - public static let Low = Self(rawValue: 0x0) - - /// Medium - public static let Medium = Self(rawValue: 0x1) - - /// High - public static let High = Self(rawValue: 0x2) - - /// Very high - public static let VeryHigh = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct PINCOSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The offset size for the peripheral address calculation is linked to the PSIZE - public static let PSIZE = Self(rawValue: 0x0) - - /// The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) - public static let Fixed4 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct PSIZEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Byte (8-bit) - public static let Bits8 = Self(rawValue: 0x0) - - /// Half-word (16-bit) - public static let Bits16 = Self(rawValue: 0x1) - - /// Word (32-bit) - public static let Bits32 = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct PINCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Address pointer is fixed - public static let Fixed = Self(rawValue: 0x0) - - /// Address pointer is incremented after each data transfer - public static let Incremented = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct CIRCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Circular mode disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Circular mode enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct DIRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Peripheral-to-memory - public static let PeripheralToMemory = Self(rawValue: 0x0) - - /// Memory-to-peripheral - public static let MemoryToPeripheral = Self(rawValue: 0x1) - - /// Memory-to-memory - public static let MemoryToMemory = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct PFCTRLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The DMA is the flow controller - public static let DMA = Self(rawValue: 0x0) - - /// The peripheral is the flow controller - public static let Peripheral = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct TCIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// TC interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// TC interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct HTIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// HT interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// HT interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct TEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// TE interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// TE interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct DMEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DME interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// DME interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.CR { - public struct ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Stream disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Stream enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.FCR { - public struct FEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// FE interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// FE interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.FCR { - public struct DMDISValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Direct mode is enabled - public static let Enabled = Self(rawValue: 0x0) - - /// Direct mode is disabled - public static let Disabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension DMA2.ST.FCR { - public struct FTHValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// 1/4 full FIFO - public static let Quarter = Self(rawValue: 0x0) - - /// 1/2 full FIFO - public static let Half = Self(rawValue: 0x1) - - /// 3/4 full FIFO - public static let ThreeQuarters = Self(rawValue: 0x2) - - /// Full FIFO - public static let Full = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-neopixel/Sources/STM32F7X6/Device.swift b/stm32-neopixel/Sources/STM32F7X6/Device.swift deleted file mode 100644 index 58cb586c..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/Device.swift +++ /dev/null @@ -1,30 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// DMA controller -public let dma1 = DMA1(unsafeAddress: 0x40026000) - -/// DMA controller -public let dma2 = DMA2(unsafeAddress: 0x40026400) - -/// General-purpose I/Os -public let gpioa = GPIOA(unsafeAddress: 0x40020000) - -/// General-purpose I/Os -public let gpiob = GPIOB(unsafeAddress: 0x40020400) - -/// General-purpose I/Os -public let gpioi = GPIOI(unsafeAddress: 0x40022000) - -/// Reset and clock control -public let rcc = RCC(unsafeAddress: 0x40023800) - -/// Serial peripheral interface -public let spi1 = SPI1(unsafeAddress: 0x40013000) - -/// Serial peripheral interface -public let spi2 = SPI2(unsafeAddress: 0x40003800) - -/// Universal synchronous asynchronous receiver transmitter -public let usart1 = USART1(unsafeAddress: 0x40011000) diff --git a/stm32-neopixel/Sources/STM32F7X6/Empty.swift b/stm32-neopixel/Sources/STM32F7X6/Empty.swift deleted file mode 100644 index 934a795a..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/Empty.swift +++ /dev/null @@ -1,13 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// This file is intentionally left empty for SwiftPM to recognize the target as -// a Swift source module. diff --git a/stm32-neopixel/Sources/STM32F7X6/GPIOA.swift b/stm32-neopixel/Sources/STM32F7X6/GPIOA.swift deleted file mode 100644 index a70e68c7..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/GPIOA.swift +++ /dev/null @@ -1,1075 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -@RegisterBlock -public struct GPIOA { - /// GPIO port mode register - @RegisterBlock(offset: 0x0) - public var moder: Register - - /// GPIO port output type register - @RegisterBlock(offset: 0x4) - public var otyper: Register - - /// GPIO port output speed register - @RegisterBlock(offset: 0x8) - public var ospeedr: Register - - /// GPIO port pull-up/pull-down register - @RegisterBlock(offset: 0xc) - public var pupdr: Register - - /// GPIO port input data register - @RegisterBlock(offset: 0x10) - public var idr: Register - - /// GPIO port output data register - @RegisterBlock(offset: 0x14) - public var odr: Register - - /// GPIO port bit set/reset register - @RegisterBlock(offset: 0x18) - public var bsrr: Register - - /// GPIO port configuration lock register - @RegisterBlock(offset: 0x1c) - public var lckr: Register - - /// GPIO alternate function low register - @RegisterBlock(offset: 0x20) - public var afrl: Register - - /// GPIO alternate function high register - @RegisterBlock(offset: 0x24) - public var afrh: Register - - /// GPIO port bit reset register - @RegisterBlock(offset: 0x28) - public var brr: Register -} - -extension GPIOA { - /// GPIO port mode register - @Register(bitWidth: 32) - public struct MODER { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var moder15: MODER15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var moder14: MODER14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var moder13: MODER13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var moder12: MODER12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var moder11: MODER11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var moder10: MODER10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var moder9: MODER9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var moder8: MODER8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var moder7: MODER7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var moder6: MODER6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var moder5: MODER5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var moder4: MODER4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var moder3: MODER3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var moder2: MODER2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var moder1: MODER1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: MODER0Values.self) - public var moder0: MODER0 - } - - /// GPIO port output type register - @Register(bitWidth: 32) - public struct OTYPER { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 15..<16) - public var ot15: OT15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<15) - public var ot14: OT14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 13..<14) - public var ot13: OT13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<13) - public var ot12: OT12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 11..<12) - public var ot11: OT11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<11) - public var ot10: OT10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 9..<10) - public var ot9: OT9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<9) - public var ot8: OT8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 7..<8) - public var ot7: OT7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<7) - public var ot6: OT6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 5..<6) - public var ot5: OT5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<5) - public var ot4: OT4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 3..<4) - public var ot3: OT3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<3) - public var ot2: OT2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 1..<2) - public var ot1: OT1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<1, as: OT0Values.self) - public var ot0: OT0 - } - - /// GPIO port output speed register - @Register(bitWidth: 32) - public struct OSPEEDR { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var ospeedr15: OSPEEDR15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var ospeedr14: OSPEEDR14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var ospeedr13: OSPEEDR13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var ospeedr12: OSPEEDR12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var ospeedr11: OSPEEDR11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var ospeedr10: OSPEEDR10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var ospeedr9: OSPEEDR9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var ospeedr8: OSPEEDR8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var ospeedr7: OSPEEDR7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var ospeedr6: OSPEEDR6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var ospeedr5: OSPEEDR5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var ospeedr4: OSPEEDR4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var ospeedr3: OSPEEDR3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var ospeedr2: OSPEEDR2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var ospeedr1: OSPEEDR1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) - public var ospeedr0: OSPEEDR0 - } - - /// GPIO port pull-up/pull-down register - @Register(bitWidth: 32) - public struct PUPDR { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var pupdr15: PUPDR15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var pupdr14: PUPDR14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var pupdr13: PUPDR13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var pupdr12: PUPDR12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var pupdr11: PUPDR11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var pupdr10: PUPDR10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var pupdr9: PUPDR9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var pupdr8: PUPDR8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var pupdr7: PUPDR7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var pupdr6: PUPDR6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var pupdr5: PUPDR5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var pupdr4: PUPDR4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var pupdr3: PUPDR3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var pupdr2: PUPDR2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var pupdr1: PUPDR1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) - public var pupdr0: PUPDR0 - } - - /// GPIO port input data register - @Register(bitWidth: 32) - public struct IDR { - /// Port input data (y = 0..15) - @ReadOnly(bits: 15..<16) - public var idr15: IDR15 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 14..<15) - public var idr14: IDR14 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 13..<14) - public var idr13: IDR13 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 12..<13) - public var idr12: IDR12 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 11..<12) - public var idr11: IDR11 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 10..<11) - public var idr10: IDR10 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 9..<10) - public var idr9: IDR9 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 8..<9) - public var idr8: IDR8 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 7..<8) - public var idr7: IDR7 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 6..<7) - public var idr6: IDR6 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 5..<6) - public var idr5: IDR5 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 4..<5) - public var idr4: IDR4 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 3..<4) - public var idr3: IDR3 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 2..<3) - public var idr2: IDR2 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 1..<2) - public var idr1: IDR1 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 0..<1) - public var idr0: IDR0 - } - - /// GPIO port output data register - @Register(bitWidth: 32) - public struct ODR { - /// Port output data (y = 0..15) - @ReadWrite(bits: 15..<16) - public var odr15: ODR15 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 14..<15) - public var odr14: ODR14 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 13..<14) - public var odr13: ODR13 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 12..<13) - public var odr12: ODR12 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 11..<12) - public var odr11: ODR11 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 10..<11) - public var odr10: ODR10 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 9..<10) - public var odr9: ODR9 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 8..<9) - public var odr8: ODR8 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 7..<8) - public var odr7: ODR7 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 6..<7) - public var odr6: ODR6 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 5..<6) - public var odr5: ODR5 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 4..<5) - public var odr4: ODR4 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 3..<4) - public var odr3: ODR3 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 2..<3) - public var odr2: ODR2 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 1..<2) - public var odr1: ODR1 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 0..<1, as: ODR0Values.self) - public var odr0: ODR0 - } - - /// GPIO port bit set/reset register - @Register(bitWidth: 32) - public struct BSRR { - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 31..<32) - public var br15: BR15 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 30..<31) - public var br14: BR14 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 29..<30) - public var br13: BR13 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 28..<29) - public var br12: BR12 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 27..<28) - public var br11: BR11 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 26..<27) - public var br10: BR10 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 25..<26) - public var br9: BR9 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 24..<25) - public var br8: BR8 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 23..<24) - public var br7: BR7 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 22..<23) - public var br6: BR6 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 21..<22) - public var br5: BR5 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 20..<21) - public var br4: BR4 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 19..<20) - public var br3: BR3 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 18..<19) - public var br2: BR2 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 17..<18) - public var br1: BR1 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 16..<17) - public var br0: BR0 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 15..<16) - public var bs15: BS15 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 14..<15) - public var bs14: BS14 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 13..<14) - public var bs13: BS13 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 12..<13) - public var bs12: BS12 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 11..<12) - public var bs11: BS11 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 10..<11) - public var bs10: BS10 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 9..<10) - public var bs9: BS9 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 8..<9) - public var bs8: BS8 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 7..<8) - public var bs7: BS7 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 6..<7) - public var bs6: BS6 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 5..<6) - public var bs5: BS5 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 4..<5) - public var bs4: BS4 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 3..<4) - public var bs3: BS3 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 2..<3) - public var bs2: BS2 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 1..<2) - public var bs1: BS1 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 0..<1) - public var bs0: BS0 - } - - /// GPIO port configuration lock register - @Register(bitWidth: 32) - public struct LCKR { - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 16..<17, as: LCKKValues.self) - public var lckk: LCKK - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 15..<16) - public var lck15: LCK15 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 14..<15) - public var lck14: LCK14 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 13..<14) - public var lck13: LCK13 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 12..<13) - public var lck12: LCK12 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 11..<12) - public var lck11: LCK11 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 10..<11) - public var lck10: LCK10 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 9..<10) - public var lck9: LCK9 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 8..<9) - public var lck8: LCK8 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 7..<8) - public var lck7: LCK7 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 6..<7) - public var lck6: LCK6 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 5..<6) - public var lck5: LCK5 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 4..<5) - public var lck4: LCK4 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 3..<4) - public var lck3: LCK3 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 2..<3) - public var lck2: LCK2 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 1..<2) - public var lck1: LCK1 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 0..<1, as: LCK0Values.self) - public var lck0: LCK0 - } - - /// GPIO alternate function low register - @Register(bitWidth: 32) - public struct AFRL { - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 28..<32) - public var afrl7: AFRL7 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 24..<28) - public var afrl6: AFRL6 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 20..<24) - public var afrl5: AFRL5 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 16..<20) - public var afrl4: AFRL4 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 12..<16) - public var afrl3: AFRL3 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 8..<12) - public var afrl2: AFRL2 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 4..<8) - public var afrl1: AFRL1 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 0..<4, as: AFRL0Values.self) - public var afrl0: AFRL0 - } - - /// GPIO alternate function high register - @Register(bitWidth: 32) - public struct AFRH { - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 28..<32) - public var afrh15: AFRH15 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 24..<28) - public var afrh14: AFRH14 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 20..<24) - public var afrh13: AFRH13 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 16..<20) - public var afrh12: AFRH12 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 12..<16) - public var afrh11: AFRH11 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 8..<12) - public var afrh10: AFRH10 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 4..<8) - public var afrh9: AFRH9 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 0..<4, as: AFRH8Values.self) - public var afrh8: AFRH8 - } - - /// GPIO port bit reset register - @Register(bitWidth: 32) - public struct BRR { - /// Port A Reset bit 0 - @ReadWrite(bits: 0..<1) - public var br0: BR0 - - /// Port A Reset bit 1 - @ReadWrite(bits: 1..<2) - public var br1: BR1 - - /// Port A Reset bit 2 - @ReadWrite(bits: 2..<3) - public var br2: BR2 - - /// Port A Reset bit 3 - @ReadWrite(bits: 3..<4) - public var br3: BR3 - - /// Port A Reset bit 4 - @ReadWrite(bits: 4..<5) - public var br4: BR4 - - /// Port A Reset bit 5 - @ReadWrite(bits: 5..<6) - public var br5: BR5 - - /// Port A Reset bit 6 - @ReadWrite(bits: 6..<7) - public var br6: BR6 - - /// Port A Reset bit 7 - @ReadWrite(bits: 7..<8) - public var br7: BR7 - - /// Port A Reset bit 8 - @ReadWrite(bits: 8..<9) - public var br8: BR8 - - /// Port A Reset bit 9 - @ReadWrite(bits: 9..<10) - public var br9: BR9 - - /// Port A Reset bit 10 - @ReadWrite(bits: 10..<11) - public var br10: BR10 - - /// Port A Reset bit 11 - @ReadWrite(bits: 11..<12) - public var br11: BR11 - - /// Port A Reset bit 12 - @ReadWrite(bits: 12..<13) - public var br12: BR12 - - /// Port A Reset bit 13 - @ReadWrite(bits: 13..<14) - public var br13: BR13 - - /// Port A Reset bit 14 - @ReadWrite(bits: 14..<15) - public var br14: BR14 - - /// Port A Reset bit 15 - @ReadWrite(bits: 15..<16) - public var br15: BR15 - } -} - -extension GPIOA.MODER { - public struct MODER0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Input mode (reset state) - public static let Input = Self(rawValue: 0x0) - - /// General purpose output mode - public static let Output = Self(rawValue: 0x1) - - /// Alternate function mode - public static let Alternate = Self(rawValue: 0x2) - - /// Analog mode - public static let Analog = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.OTYPER { - public struct OT0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Output push-pull (reset state) - public static let PushPull = Self(rawValue: 0x0) - - /// Output open-drain - public static let OpenDrain = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.OSPEEDR { - public struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Low speed - public static let LowSpeed = Self(rawValue: 0x0) - - /// Medium speed - public static let MediumSpeed = Self(rawValue: 0x1) - - /// High speed - public static let HighSpeed = Self(rawValue: 0x2) - - /// Very high speed - public static let VeryHighSpeed = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.PUPDR { - public struct PUPDR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// No pull-up, pull-down - public static let Floating = Self(rawValue: 0x0) - - /// Pull-up - public static let PullUp = Self(rawValue: 0x1) - - /// Pull-down - public static let PullDown = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.ODR { - public struct ODR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Set output to logic low - public static let Low = Self(rawValue: 0x0) - - /// Set output to logic high - public static let High = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.LCKR { - public struct LCKKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Port configuration lock key not active - public static let NotActive = Self(rawValue: 0x0) - - /// Port configuration lock key active - public static let Active = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.LCKR { - public struct LCK0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Port configuration not locked - public static let Unlocked = Self(rawValue: 0x0) - - /// Port configuration locked - public static let Locked = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.AFRL { - public struct AFRL0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// AF0 - public static let AF0 = Self(rawValue: 0x0) - - /// AF1 - public static let AF1 = Self(rawValue: 0x1) - - /// AF2 - public static let AF2 = Self(rawValue: 0x2) - - /// AF3 - public static let AF3 = Self(rawValue: 0x3) - - /// AF4 - public static let AF4 = Self(rawValue: 0x4) - - /// AF5 - public static let AF5 = Self(rawValue: 0x5) - - /// AF6 - public static let AF6 = Self(rawValue: 0x6) - - /// AF7 - public static let AF7 = Self(rawValue: 0x7) - - /// AF8 - public static let AF8 = Self(rawValue: 0x8) - - /// AF9 - public static let AF9 = Self(rawValue: 0x9) - - /// AF10 - public static let AF10 = Self(rawValue: 0xa) - - /// AF11 - public static let AF11 = Self(rawValue: 0xb) - - /// AF12 - public static let AF12 = Self(rawValue: 0xc) - - /// AF13 - public static let AF13 = Self(rawValue: 0xd) - - /// AF14 - public static let AF14 = Self(rawValue: 0xe) - - /// AF15 - public static let AF15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.AFRH { - public struct AFRH8Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// AF0 - public static let AF0 = Self(rawValue: 0x0) - - /// AF1 - public static let AF1 = Self(rawValue: 0x1) - - /// AF2 - public static let AF2 = Self(rawValue: 0x2) - - /// AF3 - public static let AF3 = Self(rawValue: 0x3) - - /// AF4 - public static let AF4 = Self(rawValue: 0x4) - - /// AF5 - public static let AF5 = Self(rawValue: 0x5) - - /// AF6 - public static let AF6 = Self(rawValue: 0x6) - - /// AF7 - public static let AF7 = Self(rawValue: 0x7) - - /// AF8 - public static let AF8 = Self(rawValue: 0x8) - - /// AF9 - public static let AF9 = Self(rawValue: 0x9) - - /// AF10 - public static let AF10 = Self(rawValue: 0xa) - - /// AF11 - public static let AF11 = Self(rawValue: 0xb) - - /// AF12 - public static let AF12 = Self(rawValue: 0xc) - - /// AF13 - public static let AF13 = Self(rawValue: 0xd) - - /// AF14 - public static let AF14 = Self(rawValue: 0xe) - - /// AF15 - public static let AF15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-neopixel/Sources/STM32F7X6/GPIOB.swift b/stm32-neopixel/Sources/STM32F7X6/GPIOB.swift deleted file mode 100644 index bd0a35ba..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/GPIOB.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOB = GPIOA - diff --git a/stm32-neopixel/Sources/STM32F7X6/GPIOI.swift b/stm32-neopixel/Sources/STM32F7X6/GPIOI.swift deleted file mode 100644 index 6b2b5182..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/GPIOI.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOI = GPIOA - diff --git a/stm32-neopixel/Sources/STM32F7X6/RCC.swift b/stm32-neopixel/Sources/STM32F7X6/RCC.swift deleted file mode 100644 index 4a36aea8..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/RCC.swift +++ /dev/null @@ -1,2833 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Reset and clock control -@RegisterBlock -public struct RCC { - /// clock control register - @RegisterBlock(offset: 0x0) - public var cr: Register - - /// PLL configuration register - @RegisterBlock(offset: 0x4) - public var pllcfgr: Register - - /// clock configuration register - @RegisterBlock(offset: 0x8) - public var cfgr: Register - - /// clock interrupt register - @RegisterBlock(offset: 0xc) - public var cir: Register - - /// AHB1 peripheral reset register - @RegisterBlock(offset: 0x10) - public var ahb1rstr: Register - - /// AHB2 peripheral reset register - @RegisterBlock(offset: 0x14) - public var ahb2rstr: Register - - /// AHB3 peripheral reset register - @RegisterBlock(offset: 0x18) - public var ahb3rstr: Register - - /// APB1 peripheral reset register - @RegisterBlock(offset: 0x20) - public var apb1rstr: Register - - /// APB2 peripheral reset register - @RegisterBlock(offset: 0x24) - public var apb2rstr: Register - - /// AHB1 peripheral clock register - @RegisterBlock(offset: 0x30) - public var ahb1enr: Register - - /// AHB2 peripheral clock enable register - @RegisterBlock(offset: 0x34) - public var ahb2enr: Register - - /// AHB3 peripheral clock enable register - @RegisterBlock(offset: 0x38) - public var ahb3enr: Register - - /// APB1 peripheral clock enable register - @RegisterBlock(offset: 0x40) - public var apb1enr: Register - - /// APB2 peripheral clock enable register - @RegisterBlock(offset: 0x44) - public var apb2enr: Register - - /// AHB1 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x50) - public var ahb1lpenr: Register - - /// AHB2 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x54) - public var ahb2lpenr: Register - - /// AHB3 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x58) - public var ahb3lpenr: Register - - /// APB1 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x60) - public var apb1lpenr: Register - - /// APB2 peripheral clock enabled in low power mode register - @RegisterBlock(offset: 0x64) - public var apb2lpenr: Register - - /// Backup domain control register - @RegisterBlock(offset: 0x70) - public var bdcr: Register - - /// clock control & status register - @RegisterBlock(offset: 0x74) - public var csr: Register - - /// spread spectrum clock generation register - @RegisterBlock(offset: 0x80) - public var sscgr: Register - - /// PLLI2S configuration register - @RegisterBlock(offset: 0x84) - public var plli2scfgr: Register - - /// PLL configuration register - @RegisterBlock(offset: 0x88) - public var pllsaicfgr: Register - - /// dedicated clocks configuration register - @RegisterBlock(offset: 0x8c) - public var dckcfgr1: Register - - /// dedicated clocks configuration register - @RegisterBlock(offset: 0x90) - public var dckcfgr2: Register -} - -extension RCC { - /// clock control register - @Register(bitWidth: 32) - public struct CR { - /// PLLI2S clock ready flag - @ReadOnly(bits: 27..<28) - public var plli2srdy: PLLI2SRDY - - /// PLLI2S enable - @ReadWrite(bits: 26..<27) - public var plli2son: PLLI2SON - - /// Main PLL (PLL) clock ready flag - @ReadOnly(bits: 25..<26) - public var pllrdy: PLLRDY - - /// Main PLL (PLL) enable - @ReadWrite(bits: 24..<25) - public var pllon: PLLON - - /// Clock security system enable - @ReadWrite(bits: 19..<20, as: CSSONValues.self) - public var csson: CSSON - - /// HSE clock bypass - @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) - public var hsebyp: HSEBYP - - /// HSE clock ready flag - @ReadOnly(bits: 17..<18) - public var hserdy: HSERDY - - /// HSE clock enable - @ReadWrite(bits: 16..<17) - public var hseon: HSEON - - /// Internal high-speed clock calibration - @ReadOnly(bits: 8..<16) - public var hsical: HSICAL - - /// Internal high-speed clock trimming - @ReadWrite(bits: 3..<8) - public var hsitrim: HSITRIM - - /// Internal high-speed clock ready flag - @ReadOnly(bits: 1..<2) - public var hsirdy: HSIRDY - - /// Internal high-speed clock enable - @ReadWrite(bits: 0..<1, as: HSIONValues.self) - public var hsion: HSION - - /// PLLSAI clock ready flag - @ReadOnly(bits: 29..<30) - public var pllsairdy: PLLSAIRDY - - /// PLLSAI enable - @ReadWrite(bits: 28..<29) - public var pllsaion: PLLSAION - } - - /// PLL configuration register - @Register(bitWidth: 32) - public struct PLLCFGR { - /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) - public var pllsrc: PLLSRC - - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 0..<6) - public var pllm: PLLM - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 6..<15) - public var plln: PLLN - - /// Main PLL (PLL) division factor for main system clock - @ReadWrite(bits: 16..<18, as: PLLPValues.self) - public var pllp: PLLP - - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 24..<28) - public var pllq: PLLQ - } - - /// clock configuration register - @Register(bitWidth: 32) - public struct CFGR { - /// Microcontroller clock output 2 - @ReadWrite(bits: 30..<32, as: MCO2Values.self) - public var mco2: MCO2 - - /// MCO2 prescaler - @ReadWrite(bits: 27..<30) - public var mco2pre: MCO2PRE - - /// MCO1 prescaler - @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) - public var mco1pre: MCO1PRE - - /// I2S clock selection - @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) - public var i2ssrc: I2SSRC - - /// Microcontroller clock output 1 - @ReadWrite(bits: 21..<23, as: MCO1Values.self) - public var mco1: MCO1 - - /// HSE division factor for RTC clock - @ReadWrite(bits: 16..<21) - public var rtcpre: RTCPRE - - /// APB high-speed prescaler (APB2) - @ReadWrite(bits: 13..<16) - public var ppre2: PPRE2 - - /// APB Low speed prescaler (APB1) - @ReadWrite(bits: 10..<13, as: PPRE1Values.self) - public var ppre1: PPRE1 - - /// AHB prescaler - @ReadWrite(bits: 4..<8, as: HPREValues.self) - public var hpre: HPRE - - /// System clock switch - @Reserved(bits: 0..<2, as: SWValues.self) - public var sw: SW - - /// System clock switch status - @Reserved(bits: 2..<4) - public var sws: SWS - } - - /// clock interrupt register - @Register(bitWidth: 32) - public struct CIR { - /// Clock security system interrupt clear - @WriteOnly(bits: 23..<24) - public var cssc: CSSC - - /// PLLSAI Ready Interrupt Clear - @WriteOnly(bits: 22..<23) - public var pllsairdyc: PLLSAIRDYC - - /// PLLI2S ready interrupt clear - @WriteOnly(bits: 21..<22) - public var plli2srdyc: PLLI2SRDYC - - /// Main PLL(PLL) ready interrupt clear - @WriteOnly(bits: 20..<21) - public var pllrdyc: PLLRDYC - - /// HSE ready interrupt clear - @WriteOnly(bits: 19..<20) - public var hserdyc: HSERDYC - - /// HSI ready interrupt clear - @WriteOnly(bits: 18..<19) - public var hsirdyc: HSIRDYC - - /// LSE ready interrupt clear - @WriteOnly(bits: 17..<18) - public var lserdyc: LSERDYC - - /// LSI ready interrupt clear - @WriteOnly(bits: 16..<17) - public var lsirdyc: LSIRDYC - - /// PLLSAI Ready Interrupt Enable - @ReadWrite(bits: 14..<15) - public var pllsairdyie: PLLSAIRDYIE - - /// PLLI2S ready interrupt enable - @ReadWrite(bits: 13..<14) - public var plli2srdyie: PLLI2SRDYIE - - /// Main PLL (PLL) ready interrupt enable - @ReadWrite(bits: 12..<13) - public var pllrdyie: PLLRDYIE - - /// HSE ready interrupt enable - @ReadWrite(bits: 11..<12) - public var hserdyie: HSERDYIE - - /// HSI ready interrupt enable - @ReadWrite(bits: 10..<11) - public var hsirdyie: HSIRDYIE - - /// LSE ready interrupt enable - @ReadWrite(bits: 9..<10) - public var lserdyie: LSERDYIE - - /// LSI ready interrupt enable - @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) - public var lsirdyie: LSIRDYIE - - /// Clock security system interrupt flag - @ReadOnly(bits: 7..<8) - public var cssf: CSSF - - /// PLLSAI ready interrupt flag - @ReadOnly(bits: 6..<7) - public var pllsairdyf: PLLSAIRDYF - - /// PLLI2S ready interrupt flag - @ReadOnly(bits: 5..<6) - public var plli2srdyf: PLLI2SRDYF - - /// Main PLL (PLL) ready interrupt flag - @ReadOnly(bits: 4..<5) - public var pllrdyf: PLLRDYF - - /// HSE ready interrupt flag - @ReadOnly(bits: 3..<4) - public var hserdyf: HSERDYF - - /// HSI ready interrupt flag - @ReadOnly(bits: 2..<3) - public var hsirdyf: HSIRDYF - - /// LSE ready interrupt flag - @ReadOnly(bits: 1..<2) - public var lserdyf: LSERDYF - - /// LSI ready interrupt flag - @ReadOnly(bits: 0..<1) - public var lsirdyf: LSIRDYF - } - - /// AHB1 peripheral reset register - @Register(bitWidth: 32) - public struct AHB1RSTR { - /// USB OTG HS module reset - @ReadWrite(bits: 29..<30) - public var otghsrst: OTGHSRST - - /// Ethernet MAC reset - @ReadWrite(bits: 25..<26) - public var ethmacrst: ETHMACRST - - /// DMA2D reset - @ReadWrite(bits: 23..<24) - public var dma2drst: DMA2DRST - - /// DMA2 reset - @ReadWrite(bits: 22..<23) - public var dma2rst: DMA2RST - - /// DMA2 reset - @ReadWrite(bits: 21..<22) - public var dma1rst: DMA1RST - - /// CRC reset - @ReadWrite(bits: 12..<13) - public var crcrst: CRCRST - - /// IO port K reset - @ReadWrite(bits: 10..<11) - public var gpiokrst: GPIOKRST - - /// IO port J reset - @ReadWrite(bits: 9..<10) - public var gpiojrst: GPIOJRST - - /// IO port I reset - @ReadWrite(bits: 8..<9) - public var gpioirst: GPIOIRST - - /// IO port H reset - @ReadWrite(bits: 7..<8) - public var gpiohrst: GPIOHRST - - /// IO port G reset - @ReadWrite(bits: 6..<7) - public var gpiogrst: GPIOGRST - - /// IO port F reset - @ReadWrite(bits: 5..<6) - public var gpiofrst: GPIOFRST - - /// IO port E reset - @ReadWrite(bits: 4..<5) - public var gpioerst: GPIOERST - - /// IO port D reset - @ReadWrite(bits: 3..<4) - public var gpiodrst: GPIODRST - - /// IO port C reset - @ReadWrite(bits: 2..<3) - public var gpiocrst: GPIOCRST - - /// IO port B reset - @ReadWrite(bits: 1..<2) - public var gpiobrst: GPIOBRST - - /// IO port A reset - @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) - public var gpioarst: GPIOARST - } - - /// AHB2 peripheral reset register - @Register(bitWidth: 32) - public struct AHB2RSTR { - /// USB OTG FS module reset - @ReadWrite(bits: 7..<8) - public var otgfsrst: OTGFSRST - - /// Random number generator module reset - @ReadWrite(bits: 6..<7) - public var rngrst: RNGRST - - /// Hash module reset - @ReadWrite(bits: 5..<6) - public var hsahrst: HSAHRST - - /// Cryptographic module reset - @ReadWrite(bits: 4..<5) - public var cryprst: CRYPRST - - /// Camera interface reset - @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) - public var dcmirst: DCMIRST - } - - /// AHB3 peripheral reset register - @Register(bitWidth: 32) - public struct AHB3RSTR { - /// Flexible memory controller module reset - @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) - public var fmcrst: FMCRST - - /// Quad SPI memory controller reset - @ReadWrite(bits: 1..<2) - public var qspirst: QSPIRST - } - - /// APB1 peripheral reset register - @Register(bitWidth: 32) - public struct APB1RSTR { - /// TIM2 reset - @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) - public var tim2rst: TIM2RST - - /// TIM3 reset - @ReadWrite(bits: 1..<2) - public var tim3rst: TIM3RST - - /// TIM4 reset - @ReadWrite(bits: 2..<3) - public var tim4rst: TIM4RST - - /// TIM5 reset - @ReadWrite(bits: 3..<4) - public var tim5rst: TIM5RST - - /// TIM6 reset - @ReadWrite(bits: 4..<5) - public var tim6rst: TIM6RST - - /// TIM7 reset - @ReadWrite(bits: 5..<6) - public var tim7rst: TIM7RST - - /// TIM12 reset - @ReadWrite(bits: 6..<7) - public var tim12rst: TIM12RST - - /// TIM13 reset - @ReadWrite(bits: 7..<8) - public var tim13rst: TIM13RST - - /// TIM14 reset - @ReadWrite(bits: 8..<9) - public var tim14rst: TIM14RST - - /// Window watchdog reset - @ReadWrite(bits: 11..<12) - public var wwdgrst: WWDGRST - - /// SPI 2 reset - @ReadWrite(bits: 14..<15) - public var spi2rst: SPI2RST - - /// SPI 3 reset - @ReadWrite(bits: 15..<16) - public var spi3rst: SPI3RST - - /// USART 2 reset - @ReadWrite(bits: 17..<18) - public var usart2rst: USART2RST - - /// USART 3 reset - @ReadWrite(bits: 18..<19) - public var usart3rst: USART3RST - - /// USART 4 reset - @ReadWrite(bits: 19..<20) - public var uart4rst: UART4RST - - /// USART 5 reset - @ReadWrite(bits: 20..<21) - public var uart5rst: UART5RST - - /// I2C 1 reset - @ReadWrite(bits: 21..<22) - public var i2c1rst: I2C1RST - - /// I2C 2 reset - @ReadWrite(bits: 22..<23) - public var i2c2rst: I2C2RST - - /// I2C3 reset - @ReadWrite(bits: 23..<24) - public var i2c3rst: I2C3RST - - /// CAN1 reset - @ReadWrite(bits: 25..<26) - public var can1rst: CAN1RST - - /// CAN2 reset - @ReadWrite(bits: 26..<27) - public var can2rst: CAN2RST - - /// Power interface reset - @ReadWrite(bits: 28..<29) - public var pwrrst: PWRRST - - /// DAC reset - @ReadWrite(bits: 29..<30) - public var dacrst: DACRST - - /// UART7 reset - @ReadWrite(bits: 30..<31) - public var uart7rst: UART7RST - - /// UART8 reset - @ReadWrite(bits: 31..<32) - public var uart8rst: UART8RST - - /// SPDIF-RX reset - @ReadWrite(bits: 16..<17) - public var spdifrxrst: SPDIFRXRST - - /// HDMI-CEC reset - @ReadWrite(bits: 27..<28) - public var cecrst: CECRST - - /// Low power timer 1 reset - @ReadWrite(bits: 9..<10) - public var lptim1rst: LPTIM1RST - - /// I2C 4 reset - @ReadWrite(bits: 24..<25) - public var i2c4rst: I2C4RST - } - - /// APB2 peripheral reset register - @Register(bitWidth: 32) - public struct APB2RSTR { - /// TIM1 reset - @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) - public var tim1rst: TIM1RST - - /// TIM8 reset - @ReadWrite(bits: 1..<2) - public var tim8rst: TIM8RST - - /// USART1 reset - @ReadWrite(bits: 4..<5) - public var usart1rst: USART1RST - - /// USART6 reset - @ReadWrite(bits: 5..<6) - public var usart6rst: USART6RST - - /// ADC interface reset (common to all ADCs) - @ReadWrite(bits: 8..<9) - public var adcrst: ADCRST - - /// SPI 1 reset - @ReadWrite(bits: 12..<13) - public var spi1rst: SPI1RST - - /// SPI4 reset - @ReadWrite(bits: 13..<14) - public var spi4rst: SPI4RST - - /// System configuration controller reset - @ReadWrite(bits: 14..<15) - public var syscfgrst: SYSCFGRST - - /// TIM9 reset - @ReadWrite(bits: 16..<17) - public var tim9rst: TIM9RST - - /// TIM10 reset - @ReadWrite(bits: 17..<18) - public var tim10rst: TIM10RST - - /// TIM11 reset - @ReadWrite(bits: 18..<19) - public var tim11rst: TIM11RST - - /// SPI5 reset - @ReadWrite(bits: 20..<21) - public var spi5rst: SPI5RST - - /// SPI6 reset - @ReadWrite(bits: 21..<22) - public var spi6rst: SPI6RST - - /// SAI1 reset - @ReadWrite(bits: 22..<23) - public var sai1rst: SAI1RST - - /// LTDC reset - @ReadWrite(bits: 26..<27) - public var ltdcrst: LTDCRST - - /// SAI2 reset - @ReadWrite(bits: 23..<24) - public var sai2rst: SAI2RST - - /// SDMMC1 reset - @ReadWrite(bits: 11..<12) - public var sdmmc1rst: SDMMC1RST - } - - /// AHB1 peripheral clock register - @Register(bitWidth: 32) - public struct AHB1ENR { - /// USB OTG HSULPI clock enable - @ReadWrite(bits: 30..<31) - public var otghsulpien: OTGHSULPIEN - - /// USB OTG HS clock enable - @ReadWrite(bits: 29..<30) - public var otghsen: OTGHSEN - - /// Ethernet PTP clock enable - @ReadWrite(bits: 28..<29) - public var ethmacptpen: ETHMACPTPEN - - /// Ethernet Reception clock enable - @ReadWrite(bits: 27..<28) - public var ethmacrxen: ETHMACRXEN - - /// Ethernet Transmission clock enable - @ReadWrite(bits: 26..<27) - public var ethmactxen: ETHMACTXEN - - /// Ethernet MAC clock enable - @ReadWrite(bits: 25..<26) - public var ethmacen: ETHMACEN - - /// DMA2D clock enable - @ReadWrite(bits: 23..<24) - public var dma2den: DMA2DEN - - /// DMA2 clock enable - @ReadWrite(bits: 22..<23) - public var dma2en: DMA2EN - - /// DMA1 clock enable - @ReadWrite(bits: 21..<22) - public var dma1en: DMA1EN - - /// CCM data RAM clock enable - @ReadWrite(bits: 20..<21) - public var dtcmramen: DTCMRAMEN - - /// Backup SRAM interface clock enable - @ReadWrite(bits: 18..<19) - public var bkpsramen: BKPSRAMEN - - /// CRC clock enable - @ReadWrite(bits: 12..<13) - public var crcen: CRCEN - - /// IO port K clock enable - @ReadWrite(bits: 10..<11) - public var gpioken: GPIOKEN - - /// IO port J clock enable - @ReadWrite(bits: 9..<10) - public var gpiojen: GPIOJEN - - /// IO port I clock enable - @ReadWrite(bits: 8..<9) - public var gpioien: GPIOIEN - - /// IO port H clock enable - @ReadWrite(bits: 7..<8) - public var gpiohen: GPIOHEN - - /// IO port G clock enable - @ReadWrite(bits: 6..<7) - public var gpiogen: GPIOGEN - - /// IO port F clock enable - @ReadWrite(bits: 5..<6) - public var gpiofen: GPIOFEN - - /// IO port E clock enable - @ReadWrite(bits: 4..<5) - public var gpioeen: GPIOEEN - - /// IO port D clock enable - @ReadWrite(bits: 3..<4) - public var gpioden: GPIODEN - - /// IO port C clock enable - @ReadWrite(bits: 2..<3) - public var gpiocen: GPIOCEN - - /// IO port B clock enable - @ReadWrite(bits: 1..<2) - public var gpioben: GPIOBEN - - /// IO port A clock enable - @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) - public var gpioaen: GPIOAEN - } - - /// AHB2 peripheral clock enable register - @Register(bitWidth: 32) - public struct AHB2ENR { - /// USB OTG FS clock enable - @ReadWrite(bits: 7..<8) - public var otgfsen: OTGFSEN - - /// Random number generator clock enable - @ReadWrite(bits: 6..<7) - public var rngen: RNGEN - - /// Hash modules clock enable - @ReadWrite(bits: 5..<6) - public var hashen: HASHEN - - /// Cryptographic modules clock enable - @ReadWrite(bits: 4..<5) - public var crypen: CRYPEN - - /// Camera interface enable - @ReadWrite(bits: 0..<1, as: DCMIENValues.self) - public var dcmien: DCMIEN - } - - /// AHB3 peripheral clock enable register - @Register(bitWidth: 32) - public struct AHB3ENR { - /// Flexible memory controller module clock enable - @ReadWrite(bits: 0..<1, as: FMCENValues.self) - public var fmcen: FMCEN - - /// Quad SPI memory controller clock enable - @ReadWrite(bits: 1..<2) - public var qspien: QSPIEN - } - - /// APB1 peripheral clock enable register - @Register(bitWidth: 32) - public struct APB1ENR { - /// TIM2 clock enable - @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) - public var tim2en: TIM2EN - - /// TIM3 clock enable - @ReadWrite(bits: 1..<2) - public var tim3en: TIM3EN - - /// TIM4 clock enable - @ReadWrite(bits: 2..<3) - public var tim4en: TIM4EN - - /// TIM5 clock enable - @ReadWrite(bits: 3..<4) - public var tim5en: TIM5EN - - /// TIM6 clock enable - @ReadWrite(bits: 4..<5) - public var tim6en: TIM6EN - - /// TIM7 clock enable - @ReadWrite(bits: 5..<6) - public var tim7en: TIM7EN - - /// TIM12 clock enable - @ReadWrite(bits: 6..<7) - public var tim12en: TIM12EN - - /// TIM13 clock enable - @ReadWrite(bits: 7..<8) - public var tim13en: TIM13EN - - /// TIM14 clock enable - @ReadWrite(bits: 8..<9) - public var tim14en: TIM14EN - - /// Window watchdog clock enable - @ReadWrite(bits: 11..<12) - public var wwdgen: WWDGEN - - /// SPI2 clock enable - @ReadWrite(bits: 14..<15) - public var spi2en: SPI2EN - - /// SPI3 clock enable - @ReadWrite(bits: 15..<16) - public var spi3en: SPI3EN - - /// USART 2 clock enable - @ReadWrite(bits: 17..<18) - public var usart2en: USART2EN - - /// USART3 clock enable - @ReadWrite(bits: 18..<19) - public var usart3en: USART3EN - - /// UART4 clock enable - @ReadWrite(bits: 19..<20) - public var uart4en: UART4EN - - /// UART5 clock enable - @ReadWrite(bits: 20..<21) - public var uart5en: UART5EN - - /// I2C1 clock enable - @ReadWrite(bits: 21..<22) - public var i2c1en: I2C1EN - - /// I2C2 clock enable - @ReadWrite(bits: 22..<23) - public var i2c2en: I2C2EN - - /// I2C3 clock enable - @ReadWrite(bits: 23..<24) - public var i2c3en: I2C3EN - - /// CAN 1 clock enable - @ReadWrite(bits: 25..<26) - public var can1en: CAN1EN - - /// CAN 2 clock enable - @ReadWrite(bits: 26..<27) - public var can2en: CAN2EN - - /// Power interface clock enable - @ReadWrite(bits: 28..<29) - public var pwren: PWREN - - /// DAC interface clock enable - @ReadWrite(bits: 29..<30) - public var dacen: DACEN - - /// UART7 clock enable - @ReadWrite(bits: 30..<31) - public var uart7en: UART7EN - - /// UART8 clock enable - @ReadWrite(bits: 31..<32) - public var uart8en: UART8EN - - /// SPDIF-RX clock enable - @ReadWrite(bits: 16..<17) - public var spdifrxen: SPDIFRXEN - - /// HDMI-CEN clock enable - @ReadWrite(bits: 27..<28) - public var cecen: CECEN - - /// Low power timer 1 clock enable - @ReadWrite(bits: 9..<10) - public var lptim1en: LPTIM1EN - - /// I2C4 clock enable - @ReadWrite(bits: 24..<25) - public var i2c4en: I2C4EN - } - - /// APB2 peripheral clock enable register - @Register(bitWidth: 32) - public struct APB2ENR { - /// TIM1 clock enable - @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) - public var tim1en: TIM1EN - - /// TIM8 clock enable - @ReadWrite(bits: 1..<2) - public var tim8en: TIM8EN - - /// USART1 clock enable - @ReadWrite(bits: 4..<5) - public var usart1en: USART1EN - - /// USART6 clock enable - @ReadWrite(bits: 5..<6) - public var usart6en: USART6EN - - /// ADC1 clock enable - @ReadWrite(bits: 8..<9) - public var adc1en: ADC1EN - - /// ADC2 clock enable - @ReadWrite(bits: 9..<10) - public var adc2en: ADC2EN - - /// ADC3 clock enable - @ReadWrite(bits: 10..<11) - public var adc3en: ADC3EN - - /// SPI1 clock enable - @ReadWrite(bits: 12..<13) - public var spi1en: SPI1EN - - /// SPI4 clock enable - @ReadWrite(bits: 13..<14) - public var spi4en: SPI4EN - - /// System configuration controller clock enable - @ReadWrite(bits: 14..<15) - public var syscfgen: SYSCFGEN - - /// TIM9 clock enable - @ReadWrite(bits: 16..<17) - public var tim9en: TIM9EN - - /// TIM10 clock enable - @ReadWrite(bits: 17..<18) - public var tim10en: TIM10EN - - /// TIM11 clock enable - @ReadWrite(bits: 18..<19) - public var tim11en: TIM11EN - - /// SPI5 clock enable - @ReadWrite(bits: 20..<21) - public var spi5en: SPI5EN - - /// SPI6 clock enable - @ReadWrite(bits: 21..<22) - public var spi6en: SPI6EN - - /// SAI1 clock enable - @ReadWrite(bits: 22..<23) - public var sai1en: SAI1EN - - /// LTDC clock enable - @ReadWrite(bits: 26..<27) - public var ltdcen: LTDCEN - - /// SAI2 clock enable - @ReadWrite(bits: 23..<24) - public var sai2en: SAI2EN - - /// SDMMC1 clock enable - @ReadWrite(bits: 11..<12) - public var sdmmc1en: SDMMC1EN - } - - /// AHB1 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB1LPENR { - /// IO port A clock enable during sleep mode - @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) - public var gpioalpen: GPIOALPEN - - /// IO port B clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var gpioblpen: GPIOBLPEN - - /// IO port C clock enable during Sleep mode - @ReadWrite(bits: 2..<3) - public var gpioclpen: GPIOCLPEN - - /// IO port D clock enable during Sleep mode - @ReadWrite(bits: 3..<4) - public var gpiodlpen: GPIODLPEN - - /// IO port E clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var gpioelpen: GPIOELPEN - - /// IO port F clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var gpioflpen: GPIOFLPEN - - /// IO port G clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var gpioglpen: GPIOGLPEN - - /// IO port H clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var gpiohlpen: GPIOHLPEN - - /// IO port I clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var gpioilpen: GPIOILPEN - - /// IO port J clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var gpiojlpen: GPIOJLPEN - - /// IO port K clock enable during Sleep mode - @ReadWrite(bits: 10..<11) - public var gpioklpen: GPIOKLPEN - - /// CRC clock enable during Sleep mode - @ReadWrite(bits: 12..<13) - public var crclpen: CRCLPEN - - /// Flash interface clock enable during Sleep mode - @ReadWrite(bits: 15..<16) - public var flitflpen: FLITFLPEN - - /// SRAM 1interface clock enable during Sleep mode - @ReadWrite(bits: 16..<17) - public var sram1lpen: SRAM1LPEN - - /// SRAM 2 interface clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var sram2lpen: SRAM2LPEN - - /// Backup SRAM interface clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var bkpsramlpen: BKPSRAMLPEN - - /// SRAM 3 interface clock enable during Sleep mode - @ReadWrite(bits: 19..<20) - public var sram3lpen: SRAM3LPEN - - /// DMA1 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var dma1lpen: DMA1LPEN - - /// DMA2 clock enable during Sleep mode - @ReadWrite(bits: 22..<23) - public var dma2lpen: DMA2LPEN - - /// DMA2D clock enable during Sleep mode - @ReadWrite(bits: 23..<24) - public var dma2dlpen: DMA2DLPEN - - /// Ethernet MAC clock enable during Sleep mode - @ReadWrite(bits: 25..<26) - public var ethmaclpen: ETHMACLPEN - - /// Ethernet transmission clock enable during Sleep mode - @ReadWrite(bits: 26..<27) - public var ethmactxlpen: ETHMACTXLPEN - - /// Ethernet reception clock enable during Sleep mode - @ReadWrite(bits: 27..<28) - public var ethmacrxlpen: ETHMACRXLPEN - - /// Ethernet PTP clock enable during Sleep mode - @ReadWrite(bits: 28..<29) - public var ethmacptplpen: ETHMACPTPLPEN - - /// USB OTG HS clock enable during Sleep mode - @ReadWrite(bits: 29..<30) - public var otghslpen: OTGHSLPEN - - /// USB OTG HS ULPI clock enable during Sleep mode - @ReadWrite(bits: 30..<31) - public var otghsulpilpen: OTGHSULPILPEN - - /// AXI to AHB bridge clock enable during Sleep mode - @ReadWrite(bits: 13..<14) - public var axilpen: AXILPEN - - /// DTCM RAM interface clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var dtcmlpen: DTCMLPEN - } - - /// AHB2 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB2LPENR { - /// USB OTG FS clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var otgfslpen: OTGFSLPEN - - /// Random number generator clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var rnglpen: RNGLPEN - - /// Hash modules clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var hashlpen: HASHLPEN - - /// Cryptography modules clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var cryplpen: CRYPLPEN - - /// Camera interface enable during Sleep mode - @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) - public var dcmilpen: DCMILPEN - } - - /// AHB3 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB3LPENR { - /// Flexible memory controller module clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) - public var fmclpen: FMCLPEN - - /// Quand SPI memory controller clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var qspilpen: QSPILPEN - } - - /// APB1 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct APB1LPENR { - /// TIM2 clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) - public var tim2lpen: TIM2LPEN - - /// TIM3 clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var tim3lpen: TIM3LPEN - - /// TIM4 clock enable during Sleep mode - @ReadWrite(bits: 2..<3) - public var tim4lpen: TIM4LPEN - - /// TIM5 clock enable during Sleep mode - @ReadWrite(bits: 3..<4) - public var tim5lpen: TIM5LPEN - - /// TIM6 clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var tim6lpen: TIM6LPEN - - /// TIM7 clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var tim7lpen: TIM7LPEN - - /// TIM12 clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var tim12lpen: TIM12LPEN - - /// TIM13 clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var tim13lpen: TIM13LPEN - - /// TIM14 clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var tim14lpen: TIM14LPEN - - /// Window watchdog clock enable during Sleep mode - @ReadWrite(bits: 11..<12) - public var wwdglpen: WWDGLPEN - - /// SPI2 clock enable during Sleep mode - @ReadWrite(bits: 14..<15) - public var spi2lpen: SPI2LPEN - - /// SPI3 clock enable during Sleep mode - @ReadWrite(bits: 15..<16) - public var spi3lpen: SPI3LPEN - - /// USART2 clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var usart2lpen: USART2LPEN - - /// USART3 clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var usart3lpen: USART3LPEN - - /// UART4 clock enable during Sleep mode - @ReadWrite(bits: 19..<20) - public var uart4lpen: UART4LPEN - - /// UART5 clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var uart5lpen: UART5LPEN - - /// I2C1 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var i2c1lpen: I2C1LPEN - - /// I2C2 clock enable during Sleep mode - @ReadWrite(bits: 22..<23) - public var i2c2lpen: I2C2LPEN - - /// I2C3 clock enable during Sleep mode - @ReadWrite(bits: 23..<24) - public var i2c3lpen: I2C3LPEN - - /// CAN 1 clock enable during Sleep mode - @ReadWrite(bits: 25..<26) - public var can1lpen: CAN1LPEN - - /// CAN 2 clock enable during Sleep mode - @ReadWrite(bits: 26..<27) - public var can2lpen: CAN2LPEN - - /// Power interface clock enable during Sleep mode - @ReadWrite(bits: 28..<29) - public var pwrlpen: PWRLPEN - - /// DAC interface clock enable during Sleep mode - @ReadWrite(bits: 29..<30) - public var daclpen: DACLPEN - - /// UART7 clock enable during Sleep mode - @ReadWrite(bits: 30..<31) - public var uart7lpen: UART7LPEN - - /// UART8 clock enable during Sleep mode - @ReadWrite(bits: 31..<32) - public var uart8lpen: UART8LPEN - - /// SPDIF-RX clock enable during sleep mode - @ReadWrite(bits: 16..<17) - public var spdifrxlpen: SPDIFRXLPEN - - /// HDMI-CEN clock enable during Sleep mode - @ReadWrite(bits: 27..<28) - public var ceclpen: CECLPEN - - /// low power timer 1 clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var lptim1lpen: LPTIM1LPEN - - /// I2C4 clock enable during Sleep mode - @ReadWrite(bits: 24..<25) - public var i2c4lpen: I2C4LPEN - } - - /// APB2 peripheral clock enabled in low power mode register - @Register(bitWidth: 32) - public struct APB2LPENR { - /// TIM1 clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) - public var tim1lpen: TIM1LPEN - - /// TIM8 clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var tim8lpen: TIM8LPEN - - /// USART1 clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var usart1lpen: USART1LPEN - - /// USART6 clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var usart6lpen: USART6LPEN - - /// ADC1 clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var adc1lpen: ADC1LPEN - - /// ADC2 clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var adc2lpen: ADC2LPEN - - /// ADC 3 clock enable during Sleep mode - @ReadWrite(bits: 10..<11) - public var adc3lpen: ADC3LPEN - - /// SPI 1 clock enable during Sleep mode - @ReadWrite(bits: 12..<13) - public var spi1lpen: SPI1LPEN - - /// SPI 4 clock enable during Sleep mode - @ReadWrite(bits: 13..<14) - public var spi4lpen: SPI4LPEN - - /// System configuration controller clock enable during Sleep mode - @ReadWrite(bits: 14..<15) - public var syscfglpen: SYSCFGLPEN - - /// TIM9 clock enable during sleep mode - @ReadWrite(bits: 16..<17) - public var tim9lpen: TIM9LPEN - - /// TIM10 clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var tim10lpen: TIM10LPEN - - /// TIM11 clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var tim11lpen: TIM11LPEN - - /// SPI 5 clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var spi5lpen: SPI5LPEN - - /// SPI 6 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var spi6lpen: SPI6LPEN - - /// SAI1 clock enable during sleep mode - @ReadWrite(bits: 22..<23) - public var sai1lpen: SAI1LPEN - - /// LTDC clock enable during sleep mode - @ReadWrite(bits: 26..<27) - public var ltdclpen: LTDCLPEN - - /// SAI2 clock enable during sleep mode - @ReadWrite(bits: 23..<24) - public var sai2lpen: SAI2LPEN - - /// SDMMC1 clock enable during Sleep mode - @ReadWrite(bits: 11..<12) - public var sdmmc1lpen: SDMMC1LPEN - } - - /// Backup domain control register - @Register(bitWidth: 32) - public struct BDCR { - /// Backup domain software reset - @ReadWrite(bits: 16..<17, as: BDRSTValues.self) - public var bdrst: BDRST - - /// RTC clock enable - @ReadWrite(bits: 15..<16, as: RTCENValues.self) - public var rtcen: RTCEN - - /// External low-speed oscillator bypass - @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) - public var lsebyp: LSEBYP - - /// External low-speed oscillator ready - @ReadOnly(bits: 1..<2) - public var lserdy: LSERDY - - /// External low-speed oscillator enable - @ReadWrite(bits: 0..<1, as: LSEONValues.self) - public var lseon: LSEON - - /// LSE oscillator drive capability - @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) - public var lsedrv: LSEDRV - - /// RTC clock source selection - @Reserved(bits: 8..<10, as: RTCSELValues.self) - public var rtcsel: RTCSEL - } - - /// clock control & status register - @Register(bitWidth: 32) - public struct CSR { - /// Low-power reset flag - @ReadWrite(bits: 31..<32) - public var lpwrrstf: LPWRRSTF - - /// Window watchdog reset flag - @ReadWrite(bits: 30..<31) - public var wwdgrstf: WWDGRSTF - - /// Independent watchdog reset flag - @ReadWrite(bits: 29..<30) - public var wdgrstf: WDGRSTF - - /// Software reset flag - @ReadWrite(bits: 28..<29) - public var sftrstf: SFTRSTF - - /// POR/PDR reset flag - @ReadWrite(bits: 27..<28) - public var porrstf: PORRSTF - - /// PIN reset flag - @ReadWrite(bits: 26..<27) - public var padrstf: PADRSTF - - /// BOR reset flag - @ReadWrite(bits: 25..<26) - public var borrstf: BORRSTF - - /// Remove reset flag - @ReadWrite(bits: 24..<25) - public var rmvf: RMVF - - /// Internal low-speed oscillator ready - @ReadOnly(bits: 1..<2) - public var lsirdy: LSIRDY - - /// Internal low-speed oscillator enable - @ReadWrite(bits: 0..<1, as: LSIONValues.self) - public var lsion: LSION - } - - /// spread spectrum clock generation register - @Register(bitWidth: 32) - public struct SSCGR { - /// Spread spectrum modulation enable - @ReadWrite(bits: 31..<32, as: SSCGENValues.self) - public var sscgen: SSCGEN - - /// Spread Select - @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) - public var spreadsel: SPREADSEL - - /// Incrementation step - @ReadWrite(bits: 13..<28) - public var incstep: INCSTEP - - /// Modulation period - @ReadWrite(bits: 0..<13) - public var modper: MODPER - } - - /// PLLI2S configuration register - @Register(bitWidth: 32) - public struct PLLI2SCFGR { - /// PLLI2S division factor for I2S clocks - @ReadWrite(bits: 28..<31) - public var plli2sr: PLLI2SR - - /// PLLI2S division factor for SAI1 clock - @ReadWrite(bits: 24..<28) - public var plli2sq: PLLI2SQ - - /// PLLI2S multiplication factor for VCO - @ReadWrite(bits: 6..<15) - public var plli2sn: PLLI2SN - - /// PLLI2S division factor for SPDIFRX clock - @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) - public var plli2sp: PLLI2SP - } - - /// PLL configuration register - @Register(bitWidth: 32) - public struct PLLSAICFGR { - /// PLLSAI division factor for VCO - @ReadWrite(bits: 6..<15) - public var pllsain: PLLSAIN - - /// PLLSAI division factor for 48MHz clock - @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) - public var pllsaip: PLLSAIP - - /// PLLSAI division factor for SAI clock - @ReadWrite(bits: 24..<28) - public var pllsaiq: PLLSAIQ - - /// PLLSAI division factor for LCD clock - @ReadWrite(bits: 28..<31) - public var pllsair: PLLSAIR - } - - /// dedicated clocks configuration register - @Register(bitWidth: 32) - public struct DCKCFGR1 { - /// PLLI2S division factor for SAI1 clock - @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) - public var plli2sdivq: PLLI2SDIVQ - - /// PLLSAI division factor for SAI1 clock - @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) - public var pllsaidivq: PLLSAIDIVQ - - /// division factor for LCD_CLK - @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) - public var pllsaidivr: PLLSAIDIVR - - /// SAI1 clock source selection - @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) - public var sai1sel: SAI1SEL - - /// SAI2 clock source selection - @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) - public var sai2sel: SAI2SEL - - /// Timers clocks prescalers selection - @ReadWrite(bits: 24..<25, as: TIMPREValues.self) - public var timpre: TIMPRE - } - - /// dedicated clocks configuration register - @Register(bitWidth: 32) - public struct DCKCFGR2 { - /// USART 1 clock source selection - @ReadWrite(bits: 0..<2, as: USART1SELValues.self) - public var usart1sel: USART1SEL - - /// USART 2 clock source selection - @ReadWrite(bits: 2..<4, as: USART2SELValues.self) - public var usart2sel: USART2SEL - - /// USART 3 clock source selection - @ReadWrite(bits: 4..<6) - public var usart3sel: USART3SEL - - /// UART 4 clock source selection - @ReadWrite(bits: 6..<8) - public var uart4sel: UART4SEL - - /// UART 5 clock source selection - @ReadWrite(bits: 8..<10) - public var uart5sel: UART5SEL - - /// USART 6 clock source selection - @ReadWrite(bits: 10..<12) - public var usart6sel: USART6SEL - - /// UART 7 clock source selection - @ReadWrite(bits: 12..<14) - public var uart7sel: UART7SEL - - /// UART 8 clock source selection - @ReadWrite(bits: 14..<16) - public var uart8sel: UART8SEL - - /// I2C1 clock source selection - @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) - public var i2c1sel: I2C1SEL - - /// I2C2 clock source selection - @ReadWrite(bits: 18..<20) - public var i2c2sel: I2C2SEL - - /// I2C3 clock source selection - @ReadWrite(bits: 20..<22) - public var i2c3sel: I2C3SEL - - /// I2C4 clock source selection - @ReadWrite(bits: 22..<24) - public var i2c4sel: I2C4SEL - - /// Low power timer 1 clock source selection - @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) - public var lptim1sel: LPTIM1SEL - - /// HDMI-CEC clock source selection - @ReadWrite(bits: 26..<27, as: CECSELValues.self) - public var cecsel: CECSEL - - /// 48MHz clock source selection - @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) - public var ck48msel: CK48MSEL - - /// SDMMC clock source selection - @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) - public var sdmmc1sel: SDMMC1SEL - } -} - -extension RCC.CR { - public struct CSSONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Clock security system disabled (clock detector OFF) - public static let Off = Self(rawValue: 0x0) - - /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CR { - public struct HSEBYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// HSE crystal oscillator not bypassed - public static let NotBypassed = Self(rawValue: 0x0) - - /// HSE crystal oscillator bypassed with external clock - public static let Bypassed = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CR { - public struct HSIONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Clock Off - public static let Off = Self(rawValue: 0x0) - - /// Clock On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLCFGR { - public struct PLLSRCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// HSI clock selected as PLL and PLLI2S clock entry - public static let HSI = Self(rawValue: 0x0) - - /// HSE oscillator clock selected as PLL and PLLI2S clock entry - public static let HSE = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLCFGR { - public struct PLLPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLLP=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLLP=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLLP=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLLP=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO2Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// System clock (SYSCLK) selected - public static let SYSCLK = Self(rawValue: 0x0) - - /// PLLI2S clock selected - public static let PLLI2S = Self(rawValue: 0x1) - - /// HSE oscillator clock selected - public static let HSE = Self(rawValue: 0x2) - - /// PLL clock selected - public static let PLL = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO1PREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// No division - public static let Div1 = Self(rawValue: 0x0) - - /// Division by 2 - public static let Div2 = Self(rawValue: 0x4) - - /// Division by 3 - public static let Div3 = Self(rawValue: 0x5) - - /// Division by 4 - public static let Div4 = Self(rawValue: 0x6) - - /// Division by 5 - public static let Div5 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct I2SSRCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// PLLI2S clock used as I2S clock source - public static let PLLI2S = Self(rawValue: 0x0) - - /// External clock mapped on the I2S_CKIN pin used as I2S clock source - public static let CKIN = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// HSI clock selected - public static let HSI = Self(rawValue: 0x0) - - /// LSE oscillator selected - public static let LSE = Self(rawValue: 0x1) - - /// HSE oscillator clock selected - public static let HSE = Self(rawValue: 0x2) - - /// PLL clock selected - public static let PLL = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct PPRE1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// HCLK not divided - public static let Div1 = Self(rawValue: 0x0) - - /// HCLK divided by 2 - public static let Div2 = Self(rawValue: 0x4) - - /// HCLK divided by 4 - public static let Div4 = Self(rawValue: 0x5) - - /// HCLK divided by 8 - public static let Div8 = Self(rawValue: 0x6) - - /// HCLK divided by 16 - public static let Div16 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct HPREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// SYSCLK not divided - public static let Div1 = Self(rawValue: 0x0) - - /// SYSCLK divided by 2 - public static let Div2 = Self(rawValue: 0x8) - - /// SYSCLK divided by 4 - public static let Div4 = Self(rawValue: 0x9) - - /// SYSCLK divided by 8 - public static let Div8 = Self(rawValue: 0xa) - - /// SYSCLK divided by 16 - public static let Div16 = Self(rawValue: 0xb) - - /// SYSCLK divided by 64 - public static let Div64 = Self(rawValue: 0xc) - - /// SYSCLK divided by 128 - public static let Div128 = Self(rawValue: 0xd) - - /// SYSCLK divided by 256 - public static let Div256 = Self(rawValue: 0xe) - - /// SYSCLK divided by 512 - public static let Div512 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct SWValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// HSI selected as system clock - public static let HSI = Self(rawValue: 0x0) - - /// HSE selected as system clock - public static let HSE = Self(rawValue: 0x1) - - /// PLL selected as system clock - public static let PLL = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CIR { - public struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1RSTR { - public struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2RSTR { - public struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3RSTR { - public struct FMCRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1RSTR { - public struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2RSTR { - public struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1ENR { - public struct GPIOAENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2ENR { - public struct DCMIENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3ENR { - public struct FMCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1ENR { - public struct TIM2ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2ENR { - public struct TIM1ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1LPENR { - public struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2LPENR { - public struct DCMILPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3LPENR { - public struct FMCLPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1LPENR { - public struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2LPENR { - public struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct BDRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset not activated - public static let Disabled = Self(rawValue: 0x0) - - /// Reset the entire RTC domain - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct RTCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RTC clock disabled - public static let Disabled = Self(rawValue: 0x0) - - /// RTC clock enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEBYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE crystal oscillator not bypassed - public static let NotBypassed = Self(rawValue: 0x0) - - /// LSE crystal oscillator bypassed with external clock - public static let Bypassed = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE oscillator Off - public static let Off = Self(rawValue: 0x0) - - /// LSE oscillator On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEDRVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Low drive capacity - public static let Low = Self(rawValue: 0x0) - - /// Medium-high drive capacity - public static let MediumHigh = Self(rawValue: 0x1) - - /// Medium-low drive capacity - public static let MediumLow = Self(rawValue: 0x2) - - /// High drive capacity - public static let High = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct RTCSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// No clock - public static let NoClock = Self(rawValue: 0x0) - - /// LSE oscillator clock used as RTC clock - public static let LSE = Self(rawValue: 0x1) - - /// LSI oscillator clock used as RTC clock - public static let LSI = Self(rawValue: 0x2) - - /// HSE oscillator clock divided by a prescaler used as RTC clock - public static let HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CSR { - public struct LSIONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSI oscillator Off - public static let Off = Self(rawValue: 0x0) - - /// LSI oscillator On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.SSCGR { - public struct SSCGENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Spread spectrum modulation disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Spread spectrum modulation enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.SSCGR { - public struct SPREADSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Center spread - public static let Center = Self(rawValue: 0x0) - - /// Down spread - public static let Down = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLI2SCFGR { - public struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLL*P=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLL*P=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLL*P=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLL*P=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLSAICFGR { - public struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLL*P=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLL*P=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLL*P=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLL*P=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 5 - - /// PLLI2SDIVQ = /1 - public static let Div1 = Self(rawValue: 0x0) - - /// PLLI2SDIVQ = /2 - public static let Div2 = Self(rawValue: 0x1) - - /// PLLI2SDIVQ = /3 - public static let Div3 = Self(rawValue: 0x2) - - /// PLLI2SDIVQ = /4 - public static let Div4 = Self(rawValue: 0x3) - - /// PLLI2SDIVQ = /5 - public static let Div5 = Self(rawValue: 0x4) - - /// PLLI2SDIVQ = /6 - public static let Div6 = Self(rawValue: 0x5) - - /// PLLI2SDIVQ = /7 - public static let Div7 = Self(rawValue: 0x6) - - /// PLLI2SDIVQ = /8 - public static let Div8 = Self(rawValue: 0x7) - - /// PLLI2SDIVQ = /9 - public static let Div9 = Self(rawValue: 0x8) - - /// PLLI2SDIVQ = /10 - public static let Div10 = Self(rawValue: 0x9) - - /// PLLI2SDIVQ = /11 - public static let Div11 = Self(rawValue: 0xa) - - /// PLLI2SDIVQ = /12 - public static let Div12 = Self(rawValue: 0xb) - - /// PLLI2SDIVQ = /13 - public static let Div13 = Self(rawValue: 0xc) - - /// PLLI2SDIVQ = /14 - public static let Div14 = Self(rawValue: 0xd) - - /// PLLI2SDIVQ = /15 - public static let Div15 = Self(rawValue: 0xe) - - /// PLLI2SDIVQ = /16 - public static let Div16 = Self(rawValue: 0xf) - - /// PLLI2SDIVQ = /17 - public static let Div17 = Self(rawValue: 0x10) - - /// PLLI2SDIVQ = /18 - public static let Div18 = Self(rawValue: 0x11) - - /// PLLI2SDIVQ = /19 - public static let Div19 = Self(rawValue: 0x12) - - /// PLLI2SDIVQ = /20 - public static let Div20 = Self(rawValue: 0x13) - - /// PLLI2SDIVQ = /21 - public static let Div21 = Self(rawValue: 0x14) - - /// PLLI2SDIVQ = /22 - public static let Div22 = Self(rawValue: 0x15) - - /// PLLI2SDIVQ = /23 - public static let Div23 = Self(rawValue: 0x16) - - /// PLLI2SDIVQ = /24 - public static let Div24 = Self(rawValue: 0x17) - - /// PLLI2SDIVQ = /25 - public static let Div25 = Self(rawValue: 0x18) - - /// PLLI2SDIVQ = /26 - public static let Div26 = Self(rawValue: 0x19) - - /// PLLI2SDIVQ = /27 - public static let Div27 = Self(rawValue: 0x1a) - - /// PLLI2SDIVQ = /28 - public static let Div28 = Self(rawValue: 0x1b) - - /// PLLI2SDIVQ = /29 - public static let Div29 = Self(rawValue: 0x1c) - - /// PLLI2SDIVQ = /30 - public static let Div30 = Self(rawValue: 0x1d) - - /// PLLI2SDIVQ = /31 - public static let Div31 = Self(rawValue: 0x1e) - - /// PLLI2SDIVQ = /32 - public static let Div32 = Self(rawValue: 0x1f) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 5 - - /// PLLSAIDIVQ = /1 - public static let Div1 = Self(rawValue: 0x0) - - /// PLLSAIDIVQ = /2 - public static let Div2 = Self(rawValue: 0x1) - - /// PLLSAIDIVQ = /3 - public static let Div3 = Self(rawValue: 0x2) - - /// PLLSAIDIVQ = /4 - public static let Div4 = Self(rawValue: 0x3) - - /// PLLSAIDIVQ = /5 - public static let Div5 = Self(rawValue: 0x4) - - /// PLLSAIDIVQ = /6 - public static let Div6 = Self(rawValue: 0x5) - - /// PLLSAIDIVQ = /7 - public static let Div7 = Self(rawValue: 0x6) - - /// PLLSAIDIVQ = /8 - public static let Div8 = Self(rawValue: 0x7) - - /// PLLSAIDIVQ = /9 - public static let Div9 = Self(rawValue: 0x8) - - /// PLLSAIDIVQ = /10 - public static let Div10 = Self(rawValue: 0x9) - - /// PLLSAIDIVQ = /11 - public static let Div11 = Self(rawValue: 0xa) - - /// PLLSAIDIVQ = /12 - public static let Div12 = Self(rawValue: 0xb) - - /// PLLSAIDIVQ = /13 - public static let Div13 = Self(rawValue: 0xc) - - /// PLLSAIDIVQ = /14 - public static let Div14 = Self(rawValue: 0xd) - - /// PLLSAIDIVQ = /15 - public static let Div15 = Self(rawValue: 0xe) - - /// PLLSAIDIVQ = /16 - public static let Div16 = Self(rawValue: 0xf) - - /// PLLSAIDIVQ = /17 - public static let Div17 = Self(rawValue: 0x10) - - /// PLLSAIDIVQ = /18 - public static let Div18 = Self(rawValue: 0x11) - - /// PLLSAIDIVQ = /19 - public static let Div19 = Self(rawValue: 0x12) - - /// PLLSAIDIVQ = /20 - public static let Div20 = Self(rawValue: 0x13) - - /// PLLSAIDIVQ = /21 - public static let Div21 = Self(rawValue: 0x14) - - /// PLLSAIDIVQ = /22 - public static let Div22 = Self(rawValue: 0x15) - - /// PLLSAIDIVQ = /23 - public static let Div23 = Self(rawValue: 0x16) - - /// PLLSAIDIVQ = /24 - public static let Div24 = Self(rawValue: 0x17) - - /// PLLSAIDIVQ = /25 - public static let Div25 = Self(rawValue: 0x18) - - /// PLLSAIDIVQ = /26 - public static let Div26 = Self(rawValue: 0x19) - - /// PLLSAIDIVQ = /27 - public static let Div27 = Self(rawValue: 0x1a) - - /// PLLSAIDIVQ = /28 - public static let Div28 = Self(rawValue: 0x1b) - - /// PLLSAIDIVQ = /29 - public static let Div29 = Self(rawValue: 0x1c) - - /// PLLSAIDIVQ = /30 - public static let Div30 = Self(rawValue: 0x1d) - - /// PLLSAIDIVQ = /31 - public static let Div31 = Self(rawValue: 0x1e) - - /// PLLSAIDIVQ = /32 - public static let Div32 = Self(rawValue: 0x1f) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLLSAIDIVR = /2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLLSAIDIVR = /4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLLSAIDIVR = /8 - public static let Div8 = Self(rawValue: 0x2) - - /// PLLSAIDIVR = /16 - public static let Div16 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct SAI1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - public static let PLLSAI = Self(rawValue: 0x0) - - /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - public static let PLLI2S = Self(rawValue: 0x1) - - /// SAI1 clock frequency = Alternate function input frequency - public static let AFIF = Self(rawValue: 0x2) - - /// SAI1 clock frequency = HSI or HSE - public static let HSI_HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct SAI2SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - public static let PLLSAI = Self(rawValue: 0x0) - - /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - public static let PLLI2S = Self(rawValue: 0x1) - - /// SAI2 clock frequency = Alternate function input frequency - public static let AFIF = Self(rawValue: 0x2) - - /// SAI2 clock frequency = HSI or HSE - public static let HSI_HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct TIMPREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - public static let Mul1Or2 = Self(rawValue: 0x0) - - /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - public static let Mul1Or4 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct USART1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB2 clock (PCLK2) is selected as USART clock - public static let APB2 = Self(rawValue: 0x0) - - /// System clock is selected as USART clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock is selected as USART clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as USART clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct USART2SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB1 clock (PCLK1) is selected as USART clock - public static let APB1 = Self(rawValue: 0x0) - - /// System clock is selected as USART clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock is selected as USART clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as USART clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct I2C1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB clock selected as I2C clock - public static let APB = Self(rawValue: 0x0) - - /// System clock selected as I2C clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock selected as I2C clock - public static let HSI = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB1 clock (PCLK1) selected as LPTILM1 clock - public static let APB1 = Self(rawValue: 0x0) - - /// LSI clock is selected as LPTILM1 clock - public static let LSI = Self(rawValue: 0x1) - - /// HSI clock is selected as LPTILM1 clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as LPTILM1 clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct CECSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE clock is selected as HDMI-CEC clock - public static let LSE = Self(rawValue: 0x0) - - /// HSI divided by 488 clock is selected as HDMI-CEC clock - public static let HSI_Div488 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct CK48MSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 48MHz clock from PLL is selected - public static let PLL = Self(rawValue: 0x0) - - /// 48MHz clock from PLLSAI is selected - public static let PLLSAI = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 48 MHz clock is selected as SD clock - public static let CK48M = Self(rawValue: 0x0) - - /// System clock is selected as SD clock - public static let SYSCLK = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-neopixel/Sources/STM32F7X6/SPI1.swift b/stm32-neopixel/Sources/STM32F7X6/SPI1.swift deleted file mode 100644 index c08d7a60..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/SPI1.swift +++ /dev/null @@ -1,1043 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Serial peripheral interface -@RegisterBlock -public struct SPI1 { - /// control register 1 - @RegisterBlock(offset: 0x0) - public var cr1: Register - - /// control register 2 - @RegisterBlock(offset: 0x4) - public var cr2: Register - - /// status register - @RegisterBlock(offset: 0x8) - public var sr: Register - - /// data register - @RegisterBlock(offset: 0xc) - public var dr: Register - - /// CRC polynomial register - @RegisterBlock(offset: 0x10) - public var crcpr: Register - - /// RX CRC register - @RegisterBlock(offset: 0x14) - public var rxcrcr: Register - - /// TX CRC register - @RegisterBlock(offset: 0x18) - public var txcrcr: Register - - /// I2S configuration register - @RegisterBlock(offset: 0x1c) - public var i2scfgr: Register - - /// I2S prescaler register - @RegisterBlock(offset: 0x20) - public var i2spr: Register -} - -extension SPI1 { - /// control register 1 - @Register(bitWidth: 32) - public struct CR1 { - /// Bidirectional data mode enable - @ReadWrite(bits: 15..<16, as: BIDIMODEValues.self) - public var bidimode: BIDIMODE - - /// Output enable in bidirectional mode - @ReadWrite(bits: 14..<15, as: BIDIOEValues.self) - public var bidioe: BIDIOE - - /// Hardware CRC calculation enable - @ReadWrite(bits: 13..<14, as: CRCENValues.self) - public var crcen: CRCEN - - /// CRC transfer next - @ReadWrite(bits: 12..<13, as: CRCNEXTValues.self) - public var crcnext: CRCNEXT - - /// CRC length - @ReadWrite(bits: 11..<12, as: CRCLValues.self) - public var crcl: CRCL - - /// Receive only - @ReadWrite(bits: 10..<11, as: RXONLYValues.self) - public var rxonly: RXONLY - - /// Software slave management - @ReadWrite(bits: 9..<10, as: SSMValues.self) - public var ssm: SSM - - /// Internal slave select - @ReadWrite(bits: 8..<9, as: SSIValues.self) - public var ssi: SSI - - /// Frame format - @ReadWrite(bits: 7..<8, as: LSBFIRSTValues.self) - public var lsbfirst: LSBFIRST - - /// SPI enable - @ReadWrite(bits: 6..<7, as: SPEValues.self) - public var spe: SPE - - /// Baud rate control - @ReadWrite(bits: 3..<6, as: BRValues.self) - public var br: BR - - /// Master selection - @ReadWrite(bits: 2..<3, as: MSTRValues.self) - public var mstr: MSTR - - /// Clock polarity - @ReadWrite(bits: 1..<2, as: CPOLValues.self) - public var cpol: CPOL - - /// Clock phase - @ReadWrite(bits: 0..<1, as: CPHAValues.self) - public var cpha: CPHA - } - - /// control register 2 - @Register(bitWidth: 32) - public struct CR2 { - /// Rx buffer DMA enable - @ReadWrite(bits: 0..<1, as: RXDMAENValues.self) - public var rxdmaen: RXDMAEN - - /// Tx buffer DMA enable - @ReadWrite(bits: 1..<2, as: TXDMAENValues.self) - public var txdmaen: TXDMAEN - - /// SS output enable - @ReadWrite(bits: 2..<3, as: SSOEValues.self) - public var ssoe: SSOE - - /// NSS pulse management - @ReadWrite(bits: 3..<4, as: NSSPValues.self) - public var nssp: NSSP - - /// Frame format - @ReadWrite(bits: 4..<5, as: FRFValues.self) - public var frf: FRF - - /// Error interrupt enable - @ReadWrite(bits: 5..<6, as: ERRIEValues.self) - public var errie: ERRIE - - /// RX buffer not empty interrupt enable - @ReadWrite(bits: 6..<7, as: RXNEIEValues.self) - public var rxneie: RXNEIE - - /// Tx buffer empty interrupt enable - @ReadWrite(bits: 7..<8, as: TXEIEValues.self) - public var txeie: TXEIE - - /// Data size - @ReadWrite(bits: 8..<12, as: DSValues.self) - public var ds: DS - - /// FIFO reception threshold - @ReadWrite(bits: 12..<13, as: FRXTHValues.self) - public var frxth: FRXTH - - /// Last DMA transfer for reception - @ReadWrite(bits: 13..<14, as: LDMA_RXValues.self) - public var ldma_rx: LDMA_RX - - /// Last DMA transfer for transmission - @ReadWrite(bits: 14..<15, as: LDMA_TXValues.self) - public var ldma_tx: LDMA_TX - } - - /// status register - @Register(bitWidth: 32) - public struct SR { - /// Frame format error - @ReadOnly(bits: 8..<9) - public var fre: FRE - - /// Busy flag - @ReadOnly(bits: 7..<8) - public var bsy: BSY - - /// Overrun flag - @ReadOnly(bits: 6..<7) - public var ovr: OVR - - /// Mode fault - @ReadOnly(bits: 5..<6) - public var modf: MODF - - /// CRC error flag - @ReadWrite(bits: 4..<5) - public var crcerr: CRCERR - - /// Underrun flag - @ReadOnly(bits: 3..<4) - public var udr: UDR - - /// Channel side - @ReadOnly(bits: 2..<3) - public var chside: CHSIDE - - /// Transmit buffer empty - @ReadOnly(bits: 1..<2) - public var txe: TXE - - /// Receive buffer not empty - @ReadOnly(bits: 0..<1) - public var rxne: RXNE - - /// FIFO reception level - @ReadOnly(bits: 9..<11) - public var frlvl: FRLVL - - /// FIFO Transmission Level - @ReadOnly(bits: 11..<13) - public var ftlvl: FTLVL - } - - /// data register - @Register(bitWidth: 32) - public struct DR { - /// Data register - @ReadWrite(bits: 0..<16) - public var dr_field: DR_FIELD - } - - /// CRC polynomial register - @Register(bitWidth: 32) - public struct CRCPR { - /// CRC polynomial register - @ReadWrite(bits: 0..<16) - public var crcpoly: CRCPOLY - } - - /// RX CRC register - @Register(bitWidth: 32) - public struct RXCRCR { - /// Rx CRC register - @ReadOnly(bits: 0..<16) - public var rxcrc: RxCRC - } - - /// TX CRC register - @Register(bitWidth: 32) - public struct TXCRCR { - /// Tx CRC register - @ReadOnly(bits: 0..<16) - public var txcrc: TxCRC - } - - /// I2S configuration register - @Register(bitWidth: 32) - public struct I2SCFGR { - /// I2S mode selection - @ReadWrite(bits: 11..<12, as: I2SMODValues.self) - public var i2smod: I2SMOD - - /// I2S Enable - @ReadWrite(bits: 10..<11, as: I2SEValues.self) - public var i2se: I2SE - - /// I2S configuration mode - @ReadWrite(bits: 8..<10, as: I2SCFGValues.self) - public var i2scfg: I2SCFG - - /// PCM frame synchronization - @ReadWrite(bits: 7..<8, as: PCMSYNCValues.self) - public var pcmsync: PCMSYNC - - /// I2S standard selection - @ReadWrite(bits: 4..<6, as: I2SSTDValues.self) - public var i2sstd: I2SSTD - - /// Steady state clock polarity - @ReadWrite(bits: 3..<4, as: CKPOLValues.self) - public var ckpol: CKPOL - - /// Data length to be transferred - @ReadWrite(bits: 1..<3, as: DATLENValues.self) - public var datlen: DATLEN - - /// Channel length (number of bits per audio channel) - @ReadWrite(bits: 0..<1, as: CHLENValues.self) - public var chlen: CHLEN - - /// Asynchronous start enable - @ReadWrite(bits: 12..<13) - public var astrten: ASTRTEN - } - - /// I2S prescaler register - @Register(bitWidth: 32) - public struct I2SPR { - /// Master clock output enable - @ReadWrite(bits: 9..<10, as: MCKOEValues.self) - public var mckoe: MCKOE - - /// Odd factor for the prescaler - @ReadWrite(bits: 8..<9, as: ODDValues.self) - public var odd: ODD - - /// I2S Linear prescaler - @ReadWrite(bits: 0..<8) - public var i2sdiv: I2SDIV - } -} - -extension SPI1.CR1 { - public struct BIDIMODEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 2-line unidirectional data mode selected - public static let Unidirectional = Self(rawValue: 0x0) - - /// 1-line bidirectional data mode selected - public static let Bidirectional = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct BIDIOEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Output disabled (receive-only mode) - public static let OutputDisabled = Self(rawValue: 0x0) - - /// Output enabled (transmit-only mode) - public static let OutputEnabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct CRCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// CRC calculation disabled - public static let Disabled = Self(rawValue: 0x0) - - /// CRC calculation enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct CRCNEXTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Next transmit value is from Tx buffer - public static let TxBuffer = Self(rawValue: 0x0) - - /// Next transmit value is from Tx CRC register - public static let CRC = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct CRCLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 8-bit CRC length - public static let EightBit = Self(rawValue: 0x0) - - /// 16-bit CRC length - public static let SixteenBit = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct RXONLYValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Full duplex (Transmit and receive) - public static let FullDuplex = Self(rawValue: 0x0) - - /// Output disabled (Receive-only mode) - public static let OutputDisabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct SSMValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Software slave management disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Software slave management enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct SSIValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored - public static let SlaveSelected = Self(rawValue: 0x0) - - /// 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored - public static let SlaveNotSelected = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct LSBFIRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Data is transmitted/received with the MSB first - public static let MSBFirst = Self(rawValue: 0x0) - - /// Data is transmitted/received with the LSB first - public static let LSBFirst = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct SPEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Peripheral disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Peripheral enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct BRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// f_PCLK / 2 - public static let Div2 = Self(rawValue: 0x0) - - /// f_PCLK / 4 - public static let Div4 = Self(rawValue: 0x1) - - /// f_PCLK / 8 - public static let Div8 = Self(rawValue: 0x2) - - /// f_PCLK / 16 - public static let Div16 = Self(rawValue: 0x3) - - /// f_PCLK / 32 - public static let Div32 = Self(rawValue: 0x4) - - /// f_PCLK / 64 - public static let Div64 = Self(rawValue: 0x5) - - /// f_PCLK / 128 - public static let Div128 = Self(rawValue: 0x6) - - /// f_PCLK / 256 - public static let Div256 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct MSTRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Slave configuration - public static let Slave = Self(rawValue: 0x0) - - /// Master configuration - public static let Master = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct CPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// CK to 0 when idle - public static let IdleLow = Self(rawValue: 0x0) - - /// CK to 1 when idle - public static let IdleHigh = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - public struct CPHAValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The first clock transition is the first data capture edge - public static let FirstEdge = Self(rawValue: 0x0) - - /// The second clock transition is the first data capture edge - public static let SecondEdge = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct RXDMAENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Rx buffer DMA disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Rx buffer DMA enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct TXDMAENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Tx buffer DMA disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Tx buffer DMA enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct SSOEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// SS output is disabled in master mode - public static let Disabled = Self(rawValue: 0x0) - - /// SS output is enabled in master mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct NSSPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// No NSS pulse - public static let NoPulse = Self(rawValue: 0x0) - - /// NSS pulse generated - public static let PulseGenerated = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct FRFValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// SPI Motorola mode - public static let Motorola = Self(rawValue: 0x0) - - /// SPI TI mode - public static let TI = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct ERRIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Error interrupt masked - public static let Masked = Self(rawValue: 0x0) - - /// Error interrupt not masked - public static let NotMasked = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct RXNEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RXE interrupt masked - public static let Masked = Self(rawValue: 0x0) - - /// RXE interrupt not masked - public static let NotMasked = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct TXEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// TXE interrupt masked - public static let Masked = Self(rawValue: 0x0) - - /// TXE interrupt not masked - public static let NotMasked = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct DSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// 4-bit - public static let FourBit = Self(rawValue: 0x3) - - /// 5-bit - public static let FiveBit = Self(rawValue: 0x4) - - /// 6-bit - public static let SixBit = Self(rawValue: 0x5) - - /// 7-bit - public static let SevenBit = Self(rawValue: 0x6) - - /// 8-bit - public static let EightBit = Self(rawValue: 0x7) - - /// 9-bit - public static let NineBit = Self(rawValue: 0x8) - - /// 10-bit - public static let TenBit = Self(rawValue: 0x9) - - /// 11-bit - public static let ElevenBit = Self(rawValue: 0xa) - - /// 12-bit - public static let TwelveBit = Self(rawValue: 0xb) - - /// 13-bit - public static let ThirteenBit = Self(rawValue: 0xc) - - /// 14-bit - public static let FourteenBit = Self(rawValue: 0xd) - - /// 15-bit - public static let FifteenBit = Self(rawValue: 0xe) - - /// 16-bit - public static let SixteenBit = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct FRXTHValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) - public static let Half = Self(rawValue: 0x0) - - /// RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) - public static let Quarter = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct LDMA_RXValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Number of data to transfer for receive is even - public static let Even = Self(rawValue: 0x0) - - /// Number of data to transfer for receive is odd - public static let Odd = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - public struct LDMA_TXValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Number of data to transfer for transmit is even - public static let Even = Self(rawValue: 0x0) - - /// Number of data to transfer for transmit is odd - public static let Odd = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - public struct I2SMODValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// SPI mode is selected - public static let SPIMode = Self(rawValue: 0x0) - - /// I2S mode is selected - public static let I2SMode = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - public struct I2SEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// I2S peripheral is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// I2S peripheral is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - public struct I2SCFGValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Slave - transmit - public static let SlaveTx = Self(rawValue: 0x0) - - /// Slave - receive - public static let SlaveRx = Self(rawValue: 0x1) - - /// Master - transmit - public static let MasterTx = Self(rawValue: 0x2) - - /// Master - receive - public static let MasterRx = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - public struct PCMSYNCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Short frame synchronisation - public static let Short = Self(rawValue: 0x0) - - /// Long frame synchronisation - public static let Long = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - public struct I2SSTDValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// I2S Philips standard - public static let Philips = Self(rawValue: 0x0) - - /// MSB justified standard - public static let MSB = Self(rawValue: 0x1) - - /// LSB justified standard - public static let LSB = Self(rawValue: 0x2) - - /// PCM standard - public static let PCM = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - public struct CKPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// I2S clock inactive state is low level - public static let IdleLow = Self(rawValue: 0x0) - - /// I2S clock inactive state is high level - public static let IdleHigh = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - public struct DATLENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// 16-bit data length - public static let SixteenBit = Self(rawValue: 0x0) - - /// 24-bit data length - public static let TwentyFourBit = Self(rawValue: 0x1) - - /// 32-bit data length - public static let ThirtyTwoBit = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - public struct CHLENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 16-bit wide - public static let SixteenBit = Self(rawValue: 0x0) - - /// 32-bit wide - public static let ThirtyTwoBit = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SPR { - public struct MCKOEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Master clock output is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Master clock output is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SPR { - public struct ODDValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Real divider value is I2SDIV * 2 - public static let Even = Self(rawValue: 0x0) - - /// Real divider value is (I2SDIV * 2) + 1 - public static let Odd = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-neopixel/Sources/STM32F7X6/SPI2.swift b/stm32-neopixel/Sources/STM32F7X6/SPI2.swift deleted file mode 100644 index a653238f..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/SPI2.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Serial peripheral interface -public typealias SPI2 = SPI1 - diff --git a/stm32-neopixel/Sources/STM32F7X6/USART1.swift b/stm32-neopixel/Sources/STM32F7X6/USART1.swift deleted file mode 100644 index 508d05a1..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/USART1.swift +++ /dev/null @@ -1,1554 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Universal synchronous asynchronous receiver transmitter -@RegisterBlock -public struct USART1 { - /// Control register 1 - @RegisterBlock(offset: 0x0) - public var cr1: Register - - /// Control register 2 - @RegisterBlock(offset: 0x4) - public var cr2: Register - - /// Control register 3 - @RegisterBlock(offset: 0x8) - public var cr3: Register - - /// Baud rate register - @RegisterBlock(offset: 0xc) - public var brr: Register - - /// Guard time and prescaler register - @RegisterBlock(offset: 0x10) - public var gtpr: Register - - /// Receiver timeout register - @RegisterBlock(offset: 0x14) - public var rtor: Register - - /// Request register - @RegisterBlock(offset: 0x18) - public var rqr: Register - - /// Interrupt & status register - @RegisterBlock(offset: 0x1c) - public var isr: Register - - /// Interrupt flag clear register - @RegisterBlock(offset: 0x20) - public var icr: Register - - /// Receive data register - @RegisterBlock(offset: 0x24) - public var rdr: Register - - /// Transmit data register - @RegisterBlock(offset: 0x28) - public var tdr: Register -} - -extension USART1 { - /// Control register 1 - @Register(bitWidth: 32) - public struct CR1 { - /// Word length - @ReadWrite(bits: 28..<29, as: M1Values.self) - public var m1: M1 - - /// End of Block interrupt enable - @ReadWrite(bits: 27..<28, as: EOBIEValues.self) - public var eobie: EOBIE - - /// Receiver timeout interrupt enable - @ReadWrite(bits: 26..<27, as: RTOIEValues.self) - public var rtoie: RTOIE - - /// Oversampling mode - @ReadWrite(bits: 15..<16, as: OVER8Values.self) - public var over8: OVER8 - - /// Character match interrupt enable - @ReadWrite(bits: 14..<15, as: CMIEValues.self) - public var cmie: CMIE - - /// Mute mode enable - @ReadWrite(bits: 13..<14, as: MMEValues.self) - public var mme: MME - - /// Word length - @ReadWrite(bits: 12..<13, as: M0Values.self) - public var m0: M0 - - /// Receiver wakeup method - @ReadWrite(bits: 11..<12, as: WAKEValues.self) - public var wake: WAKE - - /// Parity control enable - @ReadWrite(bits: 10..<11, as: PCEValues.self) - public var pce: PCE - - /// Parity selection - @ReadWrite(bits: 9..<10, as: PSValues.self) - public var ps: PS - - /// PE interrupt enable - @ReadWrite(bits: 8..<9, as: PEIEValues.self) - public var peie: PEIE - - /// interrupt enable - @ReadWrite(bits: 7..<8, as: TXEIEValues.self) - public var txeie: TXEIE - - /// Transmission complete interrupt enable - @ReadWrite(bits: 6..<7, as: TCIEValues.self) - public var tcie: TCIE - - /// RXNE interrupt enable - @ReadWrite(bits: 5..<6, as: RXNEIEValues.self) - public var rxneie: RXNEIE - - /// IDLE interrupt enable - @ReadWrite(bits: 4..<5, as: IDLEIEValues.self) - public var idleie: IDLEIE - - /// Transmitter enable - @ReadWrite(bits: 3..<4, as: TEValues.self) - public var te: TE - - /// Receiver enable - @ReadWrite(bits: 2..<3, as: REValues.self) - public var re: RE - - /// USART enable in Stop mode - @ReadWrite(bits: 1..<2, as: UESMValues.self) - public var uesm: UESM - - /// USART enable - @ReadWrite(bits: 0..<1, as: UEValues.self) - public var ue: UE - - /// Driver Enable assertion time - @ReadWrite(bits: 21..<26) - public var deat: DEAT - - /// Driver Enable de-assertion time - @ReadWrite(bits: 16..<21) - public var dedt: DEDT - } - - /// Control register 2 - @Register(bitWidth: 32) - public struct CR2 { - /// Receiver timeout enable - @ReadWrite(bits: 23..<24, as: RTOENValues.self) - public var rtoen: RTOEN - - /// Auto baud rate enable - @ReadWrite(bits: 20..<21, as: ABRENValues.self) - public var abren: ABREN - - /// Most significant bit first - @ReadWrite(bits: 19..<20, as: MSBFIRSTValues.self) - public var msbfirst: MSBFIRST - - /// Binary data inversion - @ReadWrite(bits: 18..<19, as: DATAINVValues.self) - public var datainv: DATAINV - - /// TX pin active level inversion - @ReadWrite(bits: 17..<18, as: TXINVValues.self) - public var txinv: TXINV - - /// RX pin active level inversion - @ReadWrite(bits: 16..<17, as: RXINVValues.self) - public var rxinv: RXINV - - /// Swap TX/RX pins - @ReadWrite(bits: 15..<16, as: SWAPValues.self) - public var swap: SWAP - - /// LIN mode enable - @ReadWrite(bits: 14..<15, as: LINENValues.self) - public var linen: LINEN - - /// STOP bits - @ReadWrite(bits: 12..<14, as: STOPValues.self) - public var stop: STOP - - /// Clock enable - @ReadWrite(bits: 11..<12, as: CLKENValues.self) - public var clken: CLKEN - - /// Clock polarity - @ReadWrite(bits: 10..<11, as: CPOLValues.self) - public var cpol: CPOL - - /// Clock phase - @ReadWrite(bits: 9..<10, as: CPHAValues.self) - public var cpha: CPHA - - /// Last bit clock pulse - @ReadWrite(bits: 8..<9, as: LBCLValues.self) - public var lbcl: LBCL - - /// LIN break detection interrupt enable - @ReadWrite(bits: 6..<7, as: LBDIEValues.self) - public var lbdie: LBDIE - - /// LIN break detection length - @ReadWrite(bits: 5..<6, as: LBDLValues.self) - public var lbdl: LBDL - - /// 7-bit Address Detection/4-bit Address Detection - @ReadWrite(bits: 4..<5, as: ADDM7Values.self) - public var addm7: ADDM7 - - /// Auto baud rate mode - @ReadWrite(bits: 21..<23, as: ABRMODValues.self) - public var abrmod: ABRMOD - - /// Address of the USART node - @ReadWrite(bits: 24..<32) - public var add: ADD - } - - /// Control register 3 - @Register(bitWidth: 32) - public struct CR3 { - /// Wakeup from Stop mode interrupt enable - @ReadWrite(bits: 22..<23, as: WUFIEValues.self) - public var wufie: WUFIE - - /// Wakeup from Stop mode interrupt flag selection - @ReadWrite(bits: 20..<22, as: WUSValues.self) - public var wus: WUS - - /// Smartcard auto-retry count - @ReadWrite(bits: 17..<20) - public var scarcnt: SCARCNT - - /// Driver enable polarity selection - @ReadWrite(bits: 15..<16, as: DEPValues.self) - public var dep: DEP - - /// Driver enable mode - @ReadWrite(bits: 14..<15, as: DEMValues.self) - public var dem: DEM - - /// DMA Disable on Reception Error - @ReadWrite(bits: 13..<14, as: DDREValues.self) - public var ddre: DDRE - - /// Overrun Disable - @ReadWrite(bits: 12..<13, as: OVRDISValues.self) - public var ovrdis: OVRDIS - - /// One sample bit method enable - @ReadWrite(bits: 11..<12, as: ONEBITValues.self) - public var onebit: ONEBIT - - /// CTS interrupt enable - @ReadWrite(bits: 10..<11, as: CTSIEValues.self) - public var ctsie: CTSIE - - /// CTS enable - @ReadWrite(bits: 9..<10, as: CTSEValues.self) - public var ctse: CTSE - - /// RTS enable - @ReadWrite(bits: 8..<9, as: RTSEValues.self) - public var rtse: RTSE - - /// DMA enable transmitter - @ReadWrite(bits: 7..<8, as: DMATValues.self) - public var dmat: DMAT - - /// DMA enable receiver - @ReadWrite(bits: 6..<7, as: DMARValues.self) - public var dmar: DMAR - - /// Smartcard mode enable - @ReadWrite(bits: 5..<6, as: SCENValues.self) - public var scen: SCEN - - /// Smartcard NACK enable - @ReadWrite(bits: 4..<5, as: NACKValues.self) - public var nack: NACK - - /// Half-duplex selection - @ReadWrite(bits: 3..<4, as: HDSELValues.self) - public var hdsel: HDSEL - - /// Ir low-power - @ReadWrite(bits: 2..<3, as: IRLPValues.self) - public var irlp: IRLP - - /// Ir mode enable - @ReadWrite(bits: 1..<2, as: IRENValues.self) - public var iren: IREN - - /// Error interrupt enable - @ReadWrite(bits: 0..<1, as: EIEValues.self) - public var eie: EIE - } - - /// Baud rate register - @Register(bitWidth: 32) - public struct BRR { - /// DIV_Mantissa - @ReadWrite(bits: 0..<16) - public var brr_field: BRR_FIELD - } - - /// Guard time and prescaler register - @Register(bitWidth: 32) - public struct GTPR { - /// Guard time value - @ReadWrite(bits: 8..<16) - public var gt: GT - - /// Prescaler value - @ReadWrite(bits: 0..<8) - public var psc: PSC - } - - /// Receiver timeout register - @Register(bitWidth: 32) - public struct RTOR { - /// Block Length - @ReadWrite(bits: 24..<32) - public var blen: BLEN - - /// Receiver timeout value - @ReadWrite(bits: 0..<24) - public var rto: RTO - } - - /// Request register - @Register(bitWidth: 32) - public struct RQR { - /// Transmit data flush request - @WriteOnly(bits: 4..<5) - public var txfrq: TXFRQ - - /// Receive data flush request - @WriteOnly(bits: 3..<4) - public var rxfrq: RXFRQ - - /// Mute mode request - @WriteOnly(bits: 2..<3) - public var mmrq: MMRQ - - /// Send break request - @WriteOnly(bits: 1..<2) - public var sbkrq: SBKRQ - - /// Auto baud rate request - @WriteOnly(bits: 0..<1) - public var abrrq: ABRRQ - } - - /// Interrupt & status register - @Register(bitWidth: 32) - public struct ISR { - /// REACK - @ReadOnly(bits: 22..<23) - public var reack: REACK - - /// TEACK - @ReadOnly(bits: 21..<22) - public var teack: TEACK - - /// WUF - @ReadOnly(bits: 20..<21) - public var wuf: WUF - - /// RWU - @ReadOnly(bits: 19..<20) - public var rwu: RWU - - /// SBKF - @ReadOnly(bits: 18..<19) - public var sbkf: SBKF - - /// CMF - @ReadOnly(bits: 17..<18) - public var cmf: CMF - - /// BUSY - @ReadOnly(bits: 16..<17) - public var busy: BUSY - - /// ABRF - @ReadOnly(bits: 15..<16) - public var abrf: ABRF - - /// ABRE - @ReadOnly(bits: 14..<15) - public var abre: ABRE - - /// EOBF - @ReadOnly(bits: 12..<13) - public var eobf: EOBF - - /// RTOF - @ReadOnly(bits: 11..<12) - public var rtof: RTOF - - /// CTS - @ReadOnly(bits: 10..<11) - public var cts: CTS - - /// CTSIF - @ReadOnly(bits: 9..<10) - public var ctsif: CTSIF - - /// LBDF - @ReadOnly(bits: 8..<9) - public var lbdf: LBDF - - /// TXE - @ReadOnly(bits: 7..<8) - public var txe: TXE - - /// TC - @ReadOnly(bits: 6..<7) - public var tc: TC - - /// RXNE - @ReadOnly(bits: 5..<6) - public var rxne: RXNE - - /// IDLE - @ReadOnly(bits: 4..<5) - public var idle: IDLE - - /// ORE - @ReadOnly(bits: 3..<4) - public var ore: ORE - - /// NF - @ReadOnly(bits: 2..<3) - public var nf: NF - - /// FE - @ReadOnly(bits: 1..<2) - public var fe: FE - - /// PE - @ReadOnly(bits: 0..<1) - public var pe: PE - } - - /// Interrupt flag clear register - @Register(bitWidth: 32) - public struct ICR { - /// Wakeup from Stop mode clear flag - @WriteOnly(bits: 20..<21) - public var wucf: WUCF - - /// Character match clear flag - @WriteOnly(bits: 17..<18) - public var cmcf: CMCF - - /// End of block clear flag - @WriteOnly(bits: 12..<13) - public var eobcf: EOBCF - - /// Receiver timeout clear flag - @WriteOnly(bits: 11..<12) - public var rtocf: RTOCF - - /// CTS clear flag - @WriteOnly(bits: 9..<10) - public var ctscf: CTSCF - - /// LIN break detection clear flag - @WriteOnly(bits: 8..<9) - public var lbdcf: LBDCF - - /// Transmission complete clear flag - @WriteOnly(bits: 6..<7) - public var tccf: TCCF - - /// Idle line detected clear flag - @WriteOnly(bits: 4..<5) - public var idlecf: IDLECF - - /// Overrun error clear flag - @WriteOnly(bits: 3..<4) - public var orecf: ORECF - - /// Noise detected clear flag - @WriteOnly(bits: 2..<3) - public var ncf: NCF - - /// Framing error clear flag - @WriteOnly(bits: 1..<2) - public var fecf: FECF - - /// Parity error clear flag - @WriteOnly(bits: 0..<1) - public var pecf: PECF - } - - /// Receive data register - @Register(bitWidth: 32) - public struct RDR { - /// Receive data value - @ReadOnly(bits: 0..<9) - public var rdr_field: RDR_FIELD - } - - /// Transmit data register - @Register(bitWidth: 32) - public struct TDR { - /// Transmit data value - @ReadWrite(bits: 0..<9) - public var tdr_field: TDR_FIELD - } -} - -extension USART1.CR1 { - public struct M1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Use M0 to set the data bits - public static let M0 = Self(rawValue: 0x0) - - /// 1 start bit, 7 data bits, n stop bits - public static let Bit7 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct EOBIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// A USART interrupt is generated when the EOBF flag is set in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct RTOIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An USART interrupt is generated when the RTOF bit is set in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct OVER8Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Oversampling by 16 - public static let Oversampling16 = Self(rawValue: 0x0) - - /// Oversampling by 8 - public static let Oversampling8 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct CMIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated when the CMF bit is set in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct MMEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Receiver in active mode permanently - public static let Disabled = Self(rawValue: 0x0) - - /// Receiver can switch between mute mode and active mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct M0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 1 start bit, 8 data bits, n stop bits - public static let Bit8 = Self(rawValue: 0x0) - - /// 1 start bit, 9 data bits, n stop bits - public static let Bit9 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct WAKEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Idle line - public static let Idle = Self(rawValue: 0x0) - - /// Address mask - public static let Address = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct PCEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Parity control disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Parity control enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct PSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Even parity - public static let Even = Self(rawValue: 0x0) - - /// Odd parity - public static let Odd = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct PEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever PE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct TXEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever TXE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct TCIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever TC=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct RXNEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct IDLEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever IDLE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct TEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Transmitter is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Transmitter is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct REValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Receiver is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Receiver is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct UESMValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// USART not able to wake up the MCU from Stop mode - public static let Disabled = Self(rawValue: 0x0) - - /// USART able to wake up the MCU from Stop mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct UEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// UART is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// UART is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct RTOENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Receiver timeout feature disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Receiver timeout feature enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct ABRENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Auto baud rate detection is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Auto baud rate detection is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct MSBFIRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// data is transmitted/received with data bit 0 first, following the start bit - public static let LSB = Self(rawValue: 0x0) - - /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit - public static let MSB = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct DATAINVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Logical data from the data register are send/received in positive/direct logic - public static let Positive = Self(rawValue: 0x0) - - /// Logical data from the data register are send/received in negative/inverse logic - public static let Negative = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct TXINVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// TX pin signal works using the standard logic levels - public static let Standard = Self(rawValue: 0x0) - - /// TX pin signal values are inverted - public static let Inverted = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct RXINVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RX pin signal works using the standard logic levels - public static let Standard = Self(rawValue: 0x0) - - /// RX pin signal values are inverted - public static let Inverted = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct SWAPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// TX/RX pins are used as defined in standard pinout - public static let Standard = Self(rawValue: 0x0) - - /// The TX and RX pins functions are swapped - public static let Swapped = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LINENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LIN mode disabled - public static let Disabled = Self(rawValue: 0x0) - - /// LIN mode enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct STOPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// 1 stop bit - public static let Stop1 = Self(rawValue: 0x0) - - /// 0.5 stop bit - public static let Stop0p5 = Self(rawValue: 0x1) - - /// 2 stop bit - public static let Stop2 = Self(rawValue: 0x2) - - /// 1.5 stop bit - public static let Stop1p5 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct CLKENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// CK pin disabled - public static let Disabled = Self(rawValue: 0x0) - - /// CK pin enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct CPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Steady low value on CK pin outside transmission window - public static let Low = Self(rawValue: 0x0) - - /// Steady high value on CK pin outside transmission window - public static let High = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct CPHAValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The first clock transition is the first data capture edge - public static let First = Self(rawValue: 0x0) - - /// The second clock transition is the first data capture edge - public static let Second = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LBCLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The clock pulse of the last data bit is not output to the CK pin - public static let NotOutput = Self(rawValue: 0x0) - - /// The clock pulse of the last data bit is output to the CK pin - public static let Output = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LBDIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An interrupt is generated whenever LBDF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LBDLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 10-bit break detection - public static let Bit10 = Self(rawValue: 0x0) - - /// 11-bit break detection - public static let Bit11 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct ADDM7Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 4-bit address detection - public static let Bit4 = Self(rawValue: 0x0) - - /// 7-bit address detection - public static let Bit7 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct ABRMODValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Measurement of the start bit is used to detect the baud rate - public static let Start = Self(rawValue: 0x0) - - /// Falling edge to falling edge measurement - public static let Edge = Self(rawValue: 0x1) - - /// 0x7F frame detection - public static let Frame7F = Self(rawValue: 0x2) - - /// 0x55 frame detection - public static let Frame55 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct WUFIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An USART interrupt is generated whenever WUF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct WUSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// WUF active on address match - public static let Address = Self(rawValue: 0x0) - - /// WuF active on Start bit detection - public static let Start = Self(rawValue: 0x2) - - /// WUF active on RXNE - public static let RXNE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DEPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DE signal is active high - public static let High = Self(rawValue: 0x0) - - /// DE signal is active low - public static let Low = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DEMValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DE function is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The DE signal is output on the RTS pin - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DDREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA is not disabled in case of reception error - public static let NotDisabled = Self(rawValue: 0x0) - - /// DMA is disabled following a reception error - public static let Disabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct OVRDISValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Overrun Error Flag, ORE, is set when received data is not read before receiving new data - public static let Enabled = Self(rawValue: 0x0) - - /// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register - public static let Disabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct ONEBITValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Three sample bit method - public static let Sample3 = Self(rawValue: 0x0) - - /// One sample bit method - public static let Sample1 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct CTSIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An interrupt is generated whenever CTSIF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct CTSEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// CTS hardware flow control disabled - public static let Disabled = Self(rawValue: 0x0) - - /// CTS mode enabled, data is only transmitted when the CTS input is asserted - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct RTSEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RTS hardware flow control disabled - public static let Disabled = Self(rawValue: 0x0) - - /// RTS output enabled, data is only requested when there is space in the receive buffer - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DMATValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA mode is disabled for transmission - public static let Disabled = Self(rawValue: 0x0) - - /// DMA mode is enabled for transmission - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DMARValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA mode is disabled for reception - public static let Disabled = Self(rawValue: 0x0) - - /// DMA mode is enabled for reception - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct SCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Smartcard Mode disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Smartcard Mode enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct NACKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// NACK transmission in case of parity error is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// NACK transmission during parity error is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct HDSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Half duplex mode is not selected - public static let NotSelected = Self(rawValue: 0x0) - - /// Half duplex mode is selected - public static let Selected = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct IRLPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Normal mode - public static let Normal = Self(rawValue: 0x0) - - /// Low-power mode - public static let LowPower = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct IRENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// IrDA disabled - public static let Disabled = Self(rawValue: 0x0) - - /// IrDA enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct EIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-neopixel/Sources/STM32F7X6/stm32f7x6.patched.svd b/stm32-neopixel/Sources/STM32F7X6/stm32f7x6.patched.svd deleted file mode 120000 index a6442b50..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/stm32f7x6.patched.svd +++ /dev/null @@ -1 +0,0 @@ -../../../Tools/SVDs/stm32f7x6.patched.svd \ No newline at end of file diff --git a/stm32-neopixel/Sources/STM32F7X6/svd2swift.json b/stm32-neopixel/Sources/STM32F7X6/svd2swift.json deleted file mode 100644 index cfe41520..00000000 --- a/stm32-neopixel/Sources/STM32F7X6/svd2swift.json +++ /dev/null @@ -1,14 +0,0 @@ -{ - "peripherals": [ - "DMA1", - "DMA2", - "GPIOA", - "GPIOB", - "GPIOI", - "RCC", - "SPI1", - "SPI2", - "USART1" - ], - "access-level": "public" -} diff --git a/stm32-neopixel/Sources/Support/Support.c b/stm32-neopixel/Sources/Support/Support.c deleted file mode 100644 index ec20d61c..00000000 --- a/stm32-neopixel/Sources/Support/Support.c +++ /dev/null @@ -1,96 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#if defined(__arm__) - -#include -#include - -#define HEAP_SIZE (2 * 1024) - -__attribute__((aligned(8))) -__attribute__((section("__DATA,__heap"))) -char heap[HEAP_SIZE] = {}; -size_t next_heap_index = 0; - -void *calloc(size_t count, size_t size) { - if (next_heap_index + count * size > HEAP_SIZE) __builtin_trap(); - void *p = &heap[next_heap_index]; - next_heap_index += count * size; - return p; -} - -int posix_memalign(void **memptr, size_t alignment, size_t size) { - *memptr = calloc(size + alignment, 1); - if (((uintptr_t)*memptr) % alignment == 0) return 0; - *(uintptr_t *)memptr += alignment - ((uintptr_t)*memptr % alignment); - return 0; -} - -void free(void *ptr) { - __builtin_trap(); - // never free -} - -void *memset(void *b, int c, size_t len) { - for (int i = 0; i < len; i++) { - ((char *)b)[i] = c; - } - return b; -} - -void *memcpy(void *restrict dst, const void *restrict src, size_t n) { - for (int i = 0; i < n; i++) { - ((char *)dst)[i] = ((char *)src)[i]; - } - return dst; -} - -void enableFaults() { - uint32_t* shcsr = (uint32_t*)0xE000ED24; - // Read SHCSR. - // Set bits 16-18 to enable Memory, Bus, and Usage faults. - // Write back the modified value to the SHCSR. - *shcsr |= 0x7 << 16; -} - -void enableFPU() { - uint32_t* cpacr = (uint32_t*)0xE000ED88; - // Read CPACR. - // Set bits 20-23 to enable CP10 and CP11 coprocessors. - // Write back the modified value to the CPACR. - *cpacr |= 0xF << 20; - // Wait for the coprocessors to become active. - asm volatile("dsb"); - asm volatile("isb"); -} - -extern void reset(void); - -void interrupt(void) { - while (1) {} -} - -__attribute((used)) __attribute((section("__VECTORS,__text"))) -void *vector_table[114] = { - (void *)0x2000fffc, // initial SP - (void *)((uintptr_t)reset - (0x20010000 - 0x08000000)), // Reset - - (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // NMI - (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // HardFault - (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // MemManage - (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // BusFault - (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // UsageFault - - 0 // NULL for all the other handlers -}; - -#endif diff --git a/stm32-neopixel/Sources/Support/include/Support.h b/stm32-neopixel/Sources/Support/include/Support.h deleted file mode 100644 index 310665b0..00000000 --- a/stm32-neopixel/Sources/Support/include/Support.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#pragma once - -void enableFaults(); -void enableFPU(); diff --git a/stm32-neopixel/Sources/Support/startup.S b/stm32-neopixel/Sources/Support/startup.S deleted file mode 100644 index 6e8c7c27..00000000 --- a/stm32-neopixel/Sources/Support/startup.S +++ /dev/null @@ -1,45 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - - .extern _memcpy - .extern _main - - .text - .thumb - .section __TEXT,__text,regular,pure_instructions - .syntax unified - -// reset handler, main entry point - .balign 4 - .global _reset - .thumb_func -_reset: - ldr r0, =0x20010000 // dst - ldr r1, =0x08000000 // src - ldr r2, =segment$start$__VECTORS - ldr r3, =segment$end$__DATA - subs r2, r3, r2 // size = segment$end$__DATA - segment$start$__TEXT - - // memcpy (r0: dst = 0x20010000, r1: src = 0x08000000, r2: size = ...) - // Relocate ourselves: copy the entire image (VECTORS, TEXT, DATA segments) - // from flash memory (non-writable) to RAM (writable), so that globals can be - // written to. - bl _memcpy - - // Cannot jump to main normally, because that would call main using a relative - // offset, which would result in a call to the pre-relocation address. - // Loading address of main into a register will give us the post-relocation - // address. - ldr r0, =_main - blx r0 - - // Loop forever if main returns. - b . diff --git a/stm32-neopixel/schematic.png b/stm32-neopixel/schematic.png deleted file mode 100644 index d385f780..00000000 Binary files a/stm32-neopixel/schematic.png and /dev/null differ diff --git a/stm32-uart-echo/Makefile b/stm32-uart-echo/Makefile deleted file mode 100755 index bf727669..00000000 --- a/stm32-uart-echo/Makefile +++ /dev/null @@ -1,57 +0,0 @@ -##===----------------------------------------------------------------------===## -## -## This source file is part of the Swift open source project -## -## Copyright (c) 2023 Apple Inc. and the Swift project authors. -## Licensed under Apache License v2.0 with Runtime Library Exception -## -## See https://swift.org/LICENSE.txt for license information -## -##===----------------------------------------------------------------------===## - -# Paths -REPOROOT := $(shell git rev-parse --show-toplevel) -TOOLSROOT := $(REPOROOT)/Tools -TOOLSET := $(TOOLSROOT)/Toolsets/stm32f74x.json -MACHO2BIN := $(TOOLSROOT)/macho2bin.py -SWIFT_BUILD := swift build - -# Flags -ARCH := armv7em -TARGET := $(ARCH)-apple-none-macho -SWIFT_BUILD_ARGS := \ - --configuration release \ - --triple $(TARGET) \ - --toolset $(TOOLSET) -BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) - -.PHONY: build -build: - @echo "building..." - $(SWIFT_BUILD) \ - $(SWIFT_BUILD_ARGS) \ - -Xlinker -map -Xlinker $(BUILDROOT)/Application.mangled.map \ - --verbose - - @echo "demangling linker map..." - cat $(BUILDROOT)/Application.mangled.map \ - | c++filt | swift demangle > $(BUILDROOT)/Application.map - - @echo "disassembling..." - otool \ - -arch $(ARCH) -v -V -d -t \ - $(BUILDROOT)/Application \ - | c++filt | swift demangle > $(BUILDROOT)/Application.disassembly - - @echo "extracting binary..." - $(MACHO2BIN) \ - $(BUILDROOT)/Application \ - $(BUILDROOT)/Application.bin \ - --base-address 0x20010000 \ - --segments '__TEXT,__DATA,__VECTORS' - -.PHONY: clean -clean: - @echo "cleaning..." - @swift package clean - @rm -rf .build diff --git a/stm32-uart-echo/Package.resolved b/stm32-uart-echo/Package.resolved deleted file mode 100644 index bfba35e0..00000000 --- a/stm32-uart-echo/Package.resolved +++ /dev/null @@ -1,33 +0,0 @@ -{ - "originHash" : "b5206e756e7be7138148bd69eca921f1525d2b038657b90a2712a76adba376d0", - "pins" : [ - { - "identity" : "swift-argument-parser", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-argument-parser.git", - "state" : { - "revision" : "41982a3656a71c768319979febd796c6fd111d5c", - "version" : "1.5.0" - } - }, - { - "identity" : "swift-mmio", - "kind" : "remoteSourceControl", - "location" : "https://github.com/apple/swift-mmio", - "state" : { - "branch" : "main", - "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" - } - }, - { - "identity" : "swift-syntax", - "kind" : "remoteSourceControl", - "location" : "https://github.com/swiftlang/swift-syntax.git", - "state" : { - "revision" : "0687f71944021d616d34d922343dcef086855920", - "version" : "600.0.1" - } - } - ], - "version" : 3 -} diff --git a/stm32-uart-echo/Package.swift b/stm32-uart-echo/Package.swift deleted file mode 100644 index e5c40c11..00000000 --- a/stm32-uart-echo/Package.swift +++ /dev/null @@ -1,34 +0,0 @@ -// swift-tools-version: 6.0 - -import PackageDescription - -let package = Package( - name: "stm32-uart-echo", - products: [ - .executable(name: "Application", targets: ["Application"]) - ], - dependencies: [ - .package(url: "https://github.com/apple/swift-mmio", branch: "main") - ], - targets: [ - .executableTarget( - name: "Application", - dependencies: ["STM32F7X6", "Support"]), - // SVD2Swift \ - // --input Sources/STM32F7X6/stm32f7x6.patched.svd \ - // --output Sources/STM32F7X6 \ - // --access-level public \ - // --indentation-width 2 \ - // --peripherals GPIOA GPIOB RCC USART1 - .target( - name: "STM32F7X6", - dependencies: [ - .product(name: "MMIO", package: "swift-mmio") - ], - plugins: [ - // Plugin disabled because SwiftPM is slow. - // .plugin(name: "SVD2SwiftPlugin", package: "swift-mmio") - ]), - .target(name: "Support"), - ], - swiftLanguageModes: [.v5]) diff --git a/stm32-uart-echo/README.md b/stm32-uart-echo/README.md deleted file mode 100644 index 811cb681..00000000 --- a/stm32-uart-echo/README.md +++ /dev/null @@ -1,20 +0,0 @@ -# stm32-uart-echo - -This demo is designed to run on an STM32 microcontroller, concretely the STM32F746G Discovery Kit, and implements a simple "echo" service over UART. - -## How to build and run this example: - -- Connect the STM32F746G-DISCO board via the ST-LINK USB port to your Mac. -- Open a separate terminal window and run a serial UART monitor program. For example, the macOS built-in `screen` program is able to do that (but there are other popular alternatives, like `minicom`). The ST-LINK device shows up as a "usbmodem" device under `/dev`. -```console -$ screen /dev/cu.usbmodem<...> 115200 -``` -- Make sure you have a recent nightly Swift toolchain that has Embedded Swift support. -- Install the `stlink` (https://github.com/stlink-org/stlink) command line tools, e.g. via `brew install stlink`. -- Build and upload the program to flash memory of the STM: -```console -$ cd stm32-uart-echo -$ make -$ st-flash --reset write .build/release/Application.bin 0x08000000 -``` -- The other terminal that runs the UART monitoring program should now be showing a "Hello Swift" message and if you type into the terminal, you will see the letter show up (as they are replied back over the UART). diff --git a/stm32-uart-echo/Sources/Application/Application.swift b/stm32-uart-echo/Sources/Application/Application.swift deleted file mode 100644 index 118c7475..00000000 --- a/stm32-uart-echo/Sources/Application/Application.swift +++ /dev/null @@ -1,117 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import STM32F7X6 -import Support - -@main -public struct Application { - public static func main() { - // MARK: Clock configuration - rcc.ahb1enr.modify { rw in - // Enable AHB clock to port A - rw.raw.gpioaen = 1 - // Enable AHB clock to port B - rw.raw.gpioben = 1 - } - // Enable APB clock to usart 1 - rcc.apb2enr.modify { $0.raw.usart1en = 1 } - - // MARK: Peripheral Configuration - // Configure A9 as UART1 TX - // Put Pin A9 into alternate function mode - gpioa.moder.modify { $0.raw.moder9 = 0b10 } - // Put Pin A9 into push pull - gpioa.otyper.modify { $0.raw.ot9 = 0b0 } - // Put Pin A9 into low speed - gpioa.ospeedr.modify { $0.raw.ospeedr9 = 0b00 } - // Disable pull up/down on Pin A9 - gpioa.pupdr.modify { $0.raw.pupdr9 = 0b00 } - // Set alternate function usart1 on Pin A9 - gpioa.afrh.modify { $0.raw.afrh9 = 0b0111 } - - // Configure B7 as UART1 RX - // Put Pin B7 into alternate function mode - gpiob.moder.modify { $0.raw.moder7 = 0b10 } - // Put Pin B7 into push pull - gpiob.otyper.modify { $0.raw.ot7 = 0b0 } - // Put Pin B7 into low speed - gpiob.ospeedr.modify { $0.raw.ospeedr7 = 0b00 } - // Disable pull up/down on Pin B7 - gpiob.pupdr.modify { $0.raw.pupdr7 = 0b00 } - // Set alternate function usart1 on Pin B7 - gpiob.afrl.modify { $0.raw.afrl7 = 0b0111 } - - // Configure UART1 - // Set the baud rate to 115200 (by computing the divisor based on the 16Mhz - // default post-reset CPU clock frequency) - usart1.brr.modify { $0.raw.storage = 16_000_000 / 115200 } - - usart1.cr1.modify { rw in - // Enable USART 1 - rw.raw.ue = 1 - // Enable RX - rw.raw.re = 1 - // Enable TX - rw.raw.te = 1 - } - - // MARK: Main Loop - print("Hello Swift!") - - while true { - waitRxBufferFull() - let byte = rx() - tx(value: byte) - waitTxBufferEmpty() - // My serial console does not cook newlines so pressing "enter" sends a - // carriage return ('\r') to the device. If we naively echo this byte back - // to the user, we will move the cursor back to the start of the line and - // overwrite previous characters. Instead, if we receive a carriage - // return, send it back followed by a newline ('\n'). - if byte == UInt8(ascii: "\r") { - tx(value: UInt8(ascii: "\n")) - waitTxBufferEmpty() - } - } - } -} - -func waitTxBufferEmpty() { - // Spin while tx buffer not empty - while usart1.isr.read().raw.txe == 0 {} -} - -func tx(value: UInt8) { - usart1.tdr.write { $0.raw.tdr_field = UInt32(value) } -} - -func waitRxBufferFull() { - // Spin while rx buffer empty - while usart1.isr.read().raw.rxne == 0 {} -} - -func rx() -> UInt8 { - UInt8(usart1.rdr.read().raw.rdr_field) -} - -@_cdecl("Default_Handler") -public func defaultHandler() { - while true {} -} - -@_cdecl("putchar") -public func putchar(_ value: CInt) -> CInt { - waitTxBufferEmpty() - tx(value: UInt8(value)) - waitTxBufferEmpty() - return 0 -} diff --git a/stm32-uart-echo/Sources/Application/GPIO.swift b/stm32-uart-echo/Sources/Application/GPIO.swift deleted file mode 100644 index 8e24b427..00000000 --- a/stm32-uart-echo/Sources/Application/GPIO.swift +++ /dev/null @@ -1,111 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -import STM32F7X6 - -extension GPIOA { - enum Mode: UInt32 { - case input = 0x0 - case output = 0x1 - case alternateFunction = 0x2 - case analog = 0x3 - } - - enum OutputType: UInt32 { - case pushPull = 0x0 - case openDrain = 0x1 - } - - enum OutputSpeed: UInt32 { - case low = 0x0 - case medium = 0x1 - case high = 0x2 - case max = 0x3 - } - - enum Pull: UInt32 { - case `none` = 0x0 - case up = 0x1 - case down = 0x2 - } - - struct Configuration { - var mode: Mode - var outputType: OutputType - var outputSpeed: OutputSpeed - var pull: Pull - var alternateFunction: UInt32 - } - - func configure(pin: Int, as configuration: Configuration) { - self.moder.modify { rw in - rw.raw.storage.set( - value: configuration.mode.rawValue, - mask: 0b11, - offset: pin * 2) - } - - // Comprised of 16 x 1 bit fields. - self.otyper.modify { rw in - rw.raw.storage.set( - value: configuration.outputType.rawValue, - mask: 0b1, - offset: pin) - } - - // Comprised of 16 x 2 bit fields. - self.ospeedr.modify { rw in - rw.raw.storage.set( - value: configuration.outputSpeed.rawValue, - mask: 0b11, - offset: pin * 2) - } - - // Comprised of 16 x 2 bit fields. - self.pupdr.modify { rw in - rw.raw.storage.set( - value: configuration.pull.rawValue, - mask: 0b11, - offset: pin * 2) - } - - // Comprised of 16 x 4 bit fields, split across 2 registers. - if pin < 8 { - self.afrl.modify { rw in - rw.raw.storage.set( - value: configuration.alternateFunction, - mask: 0b1111, - offset: pin * 4) - } - } else { - self.afrh.modify { rw in - rw.raw.storage.set( - value: configuration.alternateFunction, - mask: 0b1111, - offset: (pin - 8) * 4) - } - } - } -} - -extension UInt32 { - fileprivate func get(mask: Self, offset: UInt8) -> Self { - let mask = mask &<< offset - return (self & mask) &>> offset - } - - fileprivate mutating func set(value: Self, mask: Self, offset: Int) { - let mask = mask &<< offset - let oldValue: UInt32 = self & ~mask - let newValue: UInt32 = (value &<< offset) & mask - self = oldValue | newValue - } -} diff --git a/stm32-uart-echo/Sources/STM32F7X6/Device.swift b/stm32-uart-echo/Sources/STM32F7X6/Device.swift deleted file mode 100644 index db4a3f50..00000000 --- a/stm32-uart-echo/Sources/STM32F7X6/Device.swift +++ /dev/null @@ -1,15 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public let gpioa = GPIOA(unsafeAddress: 0x40020000) - -/// General-purpose I/Os -public let gpiob = GPIOB(unsafeAddress: 0x40020400) - -/// Reset and clock control -public let rcc = RCC(unsafeAddress: 0x40023800) - -/// Universal synchronous asynchronous receiver transmitter -public let usart1 = USART1(unsafeAddress: 0x40011000) diff --git a/stm32-uart-echo/Sources/STM32F7X6/Empty.swift b/stm32-uart-echo/Sources/STM32F7X6/Empty.swift deleted file mode 100644 index 934a795a..00000000 --- a/stm32-uart-echo/Sources/STM32F7X6/Empty.swift +++ /dev/null @@ -1,13 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// This file is intentionally left empty for SwiftPM to recognize the target as -// a Swift source module. diff --git a/stm32-uart-echo/Sources/STM32F7X6/GPIOA.swift b/stm32-uart-echo/Sources/STM32F7X6/GPIOA.swift deleted file mode 100644 index a70e68c7..00000000 --- a/stm32-uart-echo/Sources/STM32F7X6/GPIOA.swift +++ /dev/null @@ -1,1075 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -@RegisterBlock -public struct GPIOA { - /// GPIO port mode register - @RegisterBlock(offset: 0x0) - public var moder: Register - - /// GPIO port output type register - @RegisterBlock(offset: 0x4) - public var otyper: Register - - /// GPIO port output speed register - @RegisterBlock(offset: 0x8) - public var ospeedr: Register - - /// GPIO port pull-up/pull-down register - @RegisterBlock(offset: 0xc) - public var pupdr: Register - - /// GPIO port input data register - @RegisterBlock(offset: 0x10) - public var idr: Register - - /// GPIO port output data register - @RegisterBlock(offset: 0x14) - public var odr: Register - - /// GPIO port bit set/reset register - @RegisterBlock(offset: 0x18) - public var bsrr: Register - - /// GPIO port configuration lock register - @RegisterBlock(offset: 0x1c) - public var lckr: Register - - /// GPIO alternate function low register - @RegisterBlock(offset: 0x20) - public var afrl: Register - - /// GPIO alternate function high register - @RegisterBlock(offset: 0x24) - public var afrh: Register - - /// GPIO port bit reset register - @RegisterBlock(offset: 0x28) - public var brr: Register -} - -extension GPIOA { - /// GPIO port mode register - @Register(bitWidth: 32) - public struct MODER { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var moder15: MODER15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var moder14: MODER14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var moder13: MODER13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var moder12: MODER12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var moder11: MODER11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var moder10: MODER10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var moder9: MODER9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var moder8: MODER8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var moder7: MODER7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var moder6: MODER6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var moder5: MODER5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var moder4: MODER4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var moder3: MODER3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var moder2: MODER2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var moder1: MODER1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: MODER0Values.self) - public var moder0: MODER0 - } - - /// GPIO port output type register - @Register(bitWidth: 32) - public struct OTYPER { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 15..<16) - public var ot15: OT15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<15) - public var ot14: OT14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 13..<14) - public var ot13: OT13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<13) - public var ot12: OT12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 11..<12) - public var ot11: OT11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<11) - public var ot10: OT10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 9..<10) - public var ot9: OT9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<9) - public var ot8: OT8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 7..<8) - public var ot7: OT7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<7) - public var ot6: OT6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 5..<6) - public var ot5: OT5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<5) - public var ot4: OT4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 3..<4) - public var ot3: OT3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<3) - public var ot2: OT2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 1..<2) - public var ot1: OT1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<1, as: OT0Values.self) - public var ot0: OT0 - } - - /// GPIO port output speed register - @Register(bitWidth: 32) - public struct OSPEEDR { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var ospeedr15: OSPEEDR15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var ospeedr14: OSPEEDR14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var ospeedr13: OSPEEDR13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var ospeedr12: OSPEEDR12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var ospeedr11: OSPEEDR11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var ospeedr10: OSPEEDR10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var ospeedr9: OSPEEDR9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var ospeedr8: OSPEEDR8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var ospeedr7: OSPEEDR7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var ospeedr6: OSPEEDR6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var ospeedr5: OSPEEDR5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var ospeedr4: OSPEEDR4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var ospeedr3: OSPEEDR3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var ospeedr2: OSPEEDR2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var ospeedr1: OSPEEDR1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) - public var ospeedr0: OSPEEDR0 - } - - /// GPIO port pull-up/pull-down register - @Register(bitWidth: 32) - public struct PUPDR { - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 30..<32) - public var pupdr15: PUPDR15 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 28..<30) - public var pupdr14: PUPDR14 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 26..<28) - public var pupdr13: PUPDR13 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 24..<26) - public var pupdr12: PUPDR12 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 22..<24) - public var pupdr11: PUPDR11 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 20..<22) - public var pupdr10: PUPDR10 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 18..<20) - public var pupdr9: PUPDR9 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 16..<18) - public var pupdr8: PUPDR8 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 14..<16) - public var pupdr7: PUPDR7 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 12..<14) - public var pupdr6: PUPDR6 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 10..<12) - public var pupdr5: PUPDR5 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 8..<10) - public var pupdr4: PUPDR4 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 6..<8) - public var pupdr3: PUPDR3 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 4..<6) - public var pupdr2: PUPDR2 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 2..<4) - public var pupdr1: PUPDR1 - - /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) - public var pupdr0: PUPDR0 - } - - /// GPIO port input data register - @Register(bitWidth: 32) - public struct IDR { - /// Port input data (y = 0..15) - @ReadOnly(bits: 15..<16) - public var idr15: IDR15 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 14..<15) - public var idr14: IDR14 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 13..<14) - public var idr13: IDR13 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 12..<13) - public var idr12: IDR12 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 11..<12) - public var idr11: IDR11 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 10..<11) - public var idr10: IDR10 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 9..<10) - public var idr9: IDR9 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 8..<9) - public var idr8: IDR8 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 7..<8) - public var idr7: IDR7 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 6..<7) - public var idr6: IDR6 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 5..<6) - public var idr5: IDR5 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 4..<5) - public var idr4: IDR4 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 3..<4) - public var idr3: IDR3 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 2..<3) - public var idr2: IDR2 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 1..<2) - public var idr1: IDR1 - - /// Port input data (y = 0..15) - @ReadOnly(bits: 0..<1) - public var idr0: IDR0 - } - - /// GPIO port output data register - @Register(bitWidth: 32) - public struct ODR { - /// Port output data (y = 0..15) - @ReadWrite(bits: 15..<16) - public var odr15: ODR15 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 14..<15) - public var odr14: ODR14 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 13..<14) - public var odr13: ODR13 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 12..<13) - public var odr12: ODR12 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 11..<12) - public var odr11: ODR11 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 10..<11) - public var odr10: ODR10 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 9..<10) - public var odr9: ODR9 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 8..<9) - public var odr8: ODR8 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 7..<8) - public var odr7: ODR7 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 6..<7) - public var odr6: ODR6 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 5..<6) - public var odr5: ODR5 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 4..<5) - public var odr4: ODR4 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 3..<4) - public var odr3: ODR3 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 2..<3) - public var odr2: ODR2 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 1..<2) - public var odr1: ODR1 - - /// Port output data (y = 0..15) - @ReadWrite(bits: 0..<1, as: ODR0Values.self) - public var odr0: ODR0 - } - - /// GPIO port bit set/reset register - @Register(bitWidth: 32) - public struct BSRR { - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 31..<32) - public var br15: BR15 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 30..<31) - public var br14: BR14 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 29..<30) - public var br13: BR13 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 28..<29) - public var br12: BR12 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 27..<28) - public var br11: BR11 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 26..<27) - public var br10: BR10 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 25..<26) - public var br9: BR9 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 24..<25) - public var br8: BR8 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 23..<24) - public var br7: BR7 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 22..<23) - public var br6: BR6 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 21..<22) - public var br5: BR5 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 20..<21) - public var br4: BR4 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 19..<20) - public var br3: BR3 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 18..<19) - public var br2: BR2 - - /// Port x reset bit y (y = 0..15) - @WriteOnly(bits: 17..<18) - public var br1: BR1 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 16..<17) - public var br0: BR0 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 15..<16) - public var bs15: BS15 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 14..<15) - public var bs14: BS14 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 13..<14) - public var bs13: BS13 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 12..<13) - public var bs12: BS12 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 11..<12) - public var bs11: BS11 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 10..<11) - public var bs10: BS10 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 9..<10) - public var bs9: BS9 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 8..<9) - public var bs8: BS8 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 7..<8) - public var bs7: BS7 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 6..<7) - public var bs6: BS6 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 5..<6) - public var bs5: BS5 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 4..<5) - public var bs4: BS4 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 3..<4) - public var bs3: BS3 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 2..<3) - public var bs2: BS2 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 1..<2) - public var bs1: BS1 - - /// Port x set bit y (y= 0..15) - @WriteOnly(bits: 0..<1) - public var bs0: BS0 - } - - /// GPIO port configuration lock register - @Register(bitWidth: 32) - public struct LCKR { - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 16..<17, as: LCKKValues.self) - public var lckk: LCKK - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 15..<16) - public var lck15: LCK15 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 14..<15) - public var lck14: LCK14 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 13..<14) - public var lck13: LCK13 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 12..<13) - public var lck12: LCK12 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 11..<12) - public var lck11: LCK11 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 10..<11) - public var lck10: LCK10 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 9..<10) - public var lck9: LCK9 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 8..<9) - public var lck8: LCK8 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 7..<8) - public var lck7: LCK7 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 6..<7) - public var lck6: LCK6 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 5..<6) - public var lck5: LCK5 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 4..<5) - public var lck4: LCK4 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 3..<4) - public var lck3: LCK3 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 2..<3) - public var lck2: LCK2 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 1..<2) - public var lck1: LCK1 - - /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 0..<1, as: LCK0Values.self) - public var lck0: LCK0 - } - - /// GPIO alternate function low register - @Register(bitWidth: 32) - public struct AFRL { - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 28..<32) - public var afrl7: AFRL7 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 24..<28) - public var afrl6: AFRL6 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 20..<24) - public var afrl5: AFRL5 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 16..<20) - public var afrl4: AFRL4 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 12..<16) - public var afrl3: AFRL3 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 8..<12) - public var afrl2: AFRL2 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 4..<8) - public var afrl1: AFRL1 - - /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 0..<4, as: AFRL0Values.self) - public var afrl0: AFRL0 - } - - /// GPIO alternate function high register - @Register(bitWidth: 32) - public struct AFRH { - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 28..<32) - public var afrh15: AFRH15 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 24..<28) - public var afrh14: AFRH14 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 20..<24) - public var afrh13: AFRH13 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 16..<20) - public var afrh12: AFRH12 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 12..<16) - public var afrh11: AFRH11 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 8..<12) - public var afrh10: AFRH10 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 4..<8) - public var afrh9: AFRH9 - - /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 0..<4, as: AFRH8Values.self) - public var afrh8: AFRH8 - } - - /// GPIO port bit reset register - @Register(bitWidth: 32) - public struct BRR { - /// Port A Reset bit 0 - @ReadWrite(bits: 0..<1) - public var br0: BR0 - - /// Port A Reset bit 1 - @ReadWrite(bits: 1..<2) - public var br1: BR1 - - /// Port A Reset bit 2 - @ReadWrite(bits: 2..<3) - public var br2: BR2 - - /// Port A Reset bit 3 - @ReadWrite(bits: 3..<4) - public var br3: BR3 - - /// Port A Reset bit 4 - @ReadWrite(bits: 4..<5) - public var br4: BR4 - - /// Port A Reset bit 5 - @ReadWrite(bits: 5..<6) - public var br5: BR5 - - /// Port A Reset bit 6 - @ReadWrite(bits: 6..<7) - public var br6: BR6 - - /// Port A Reset bit 7 - @ReadWrite(bits: 7..<8) - public var br7: BR7 - - /// Port A Reset bit 8 - @ReadWrite(bits: 8..<9) - public var br8: BR8 - - /// Port A Reset bit 9 - @ReadWrite(bits: 9..<10) - public var br9: BR9 - - /// Port A Reset bit 10 - @ReadWrite(bits: 10..<11) - public var br10: BR10 - - /// Port A Reset bit 11 - @ReadWrite(bits: 11..<12) - public var br11: BR11 - - /// Port A Reset bit 12 - @ReadWrite(bits: 12..<13) - public var br12: BR12 - - /// Port A Reset bit 13 - @ReadWrite(bits: 13..<14) - public var br13: BR13 - - /// Port A Reset bit 14 - @ReadWrite(bits: 14..<15) - public var br14: BR14 - - /// Port A Reset bit 15 - @ReadWrite(bits: 15..<16) - public var br15: BR15 - } -} - -extension GPIOA.MODER { - public struct MODER0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Input mode (reset state) - public static let Input = Self(rawValue: 0x0) - - /// General purpose output mode - public static let Output = Self(rawValue: 0x1) - - /// Alternate function mode - public static let Alternate = Self(rawValue: 0x2) - - /// Analog mode - public static let Analog = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.OTYPER { - public struct OT0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Output push-pull (reset state) - public static let PushPull = Self(rawValue: 0x0) - - /// Output open-drain - public static let OpenDrain = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.OSPEEDR { - public struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Low speed - public static let LowSpeed = Self(rawValue: 0x0) - - /// Medium speed - public static let MediumSpeed = Self(rawValue: 0x1) - - /// High speed - public static let HighSpeed = Self(rawValue: 0x2) - - /// Very high speed - public static let VeryHighSpeed = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.PUPDR { - public struct PUPDR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// No pull-up, pull-down - public static let Floating = Self(rawValue: 0x0) - - /// Pull-up - public static let PullUp = Self(rawValue: 0x1) - - /// Pull-down - public static let PullDown = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.ODR { - public struct ODR0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Set output to logic low - public static let Low = Self(rawValue: 0x0) - - /// Set output to logic high - public static let High = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.LCKR { - public struct LCKKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Port configuration lock key not active - public static let NotActive = Self(rawValue: 0x0) - - /// Port configuration lock key active - public static let Active = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.LCKR { - public struct LCK0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Port configuration not locked - public static let Unlocked = Self(rawValue: 0x0) - - /// Port configuration locked - public static let Locked = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.AFRL { - public struct AFRL0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// AF0 - public static let AF0 = Self(rawValue: 0x0) - - /// AF1 - public static let AF1 = Self(rawValue: 0x1) - - /// AF2 - public static let AF2 = Self(rawValue: 0x2) - - /// AF3 - public static let AF3 = Self(rawValue: 0x3) - - /// AF4 - public static let AF4 = Self(rawValue: 0x4) - - /// AF5 - public static let AF5 = Self(rawValue: 0x5) - - /// AF6 - public static let AF6 = Self(rawValue: 0x6) - - /// AF7 - public static let AF7 = Self(rawValue: 0x7) - - /// AF8 - public static let AF8 = Self(rawValue: 0x8) - - /// AF9 - public static let AF9 = Self(rawValue: 0x9) - - /// AF10 - public static let AF10 = Self(rawValue: 0xa) - - /// AF11 - public static let AF11 = Self(rawValue: 0xb) - - /// AF12 - public static let AF12 = Self(rawValue: 0xc) - - /// AF13 - public static let AF13 = Self(rawValue: 0xd) - - /// AF14 - public static let AF14 = Self(rawValue: 0xe) - - /// AF15 - public static let AF15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension GPIOA.AFRH { - public struct AFRH8Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// AF0 - public static let AF0 = Self(rawValue: 0x0) - - /// AF1 - public static let AF1 = Self(rawValue: 0x1) - - /// AF2 - public static let AF2 = Self(rawValue: 0x2) - - /// AF3 - public static let AF3 = Self(rawValue: 0x3) - - /// AF4 - public static let AF4 = Self(rawValue: 0x4) - - /// AF5 - public static let AF5 = Self(rawValue: 0x5) - - /// AF6 - public static let AF6 = Self(rawValue: 0x6) - - /// AF7 - public static let AF7 = Self(rawValue: 0x7) - - /// AF8 - public static let AF8 = Self(rawValue: 0x8) - - /// AF9 - public static let AF9 = Self(rawValue: 0x9) - - /// AF10 - public static let AF10 = Self(rawValue: 0xa) - - /// AF11 - public static let AF11 = Self(rawValue: 0xb) - - /// AF12 - public static let AF12 = Self(rawValue: 0xc) - - /// AF13 - public static let AF13 = Self(rawValue: 0xd) - - /// AF14 - public static let AF14 = Self(rawValue: 0xe) - - /// AF15 - public static let AF15 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-uart-echo/Sources/STM32F7X6/GPIOB.swift b/stm32-uart-echo/Sources/STM32F7X6/GPIOB.swift deleted file mode 100644 index bd0a35ba..00000000 --- a/stm32-uart-echo/Sources/STM32F7X6/GPIOB.swift +++ /dev/null @@ -1,7 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -public typealias GPIOB = GPIOA - diff --git a/stm32-uart-echo/Sources/STM32F7X6/RCC.swift b/stm32-uart-echo/Sources/STM32F7X6/RCC.swift deleted file mode 100644 index 4a36aea8..00000000 --- a/stm32-uart-echo/Sources/STM32F7X6/RCC.swift +++ /dev/null @@ -1,2833 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Reset and clock control -@RegisterBlock -public struct RCC { - /// clock control register - @RegisterBlock(offset: 0x0) - public var cr: Register - - /// PLL configuration register - @RegisterBlock(offset: 0x4) - public var pllcfgr: Register - - /// clock configuration register - @RegisterBlock(offset: 0x8) - public var cfgr: Register - - /// clock interrupt register - @RegisterBlock(offset: 0xc) - public var cir: Register - - /// AHB1 peripheral reset register - @RegisterBlock(offset: 0x10) - public var ahb1rstr: Register - - /// AHB2 peripheral reset register - @RegisterBlock(offset: 0x14) - public var ahb2rstr: Register - - /// AHB3 peripheral reset register - @RegisterBlock(offset: 0x18) - public var ahb3rstr: Register - - /// APB1 peripheral reset register - @RegisterBlock(offset: 0x20) - public var apb1rstr: Register - - /// APB2 peripheral reset register - @RegisterBlock(offset: 0x24) - public var apb2rstr: Register - - /// AHB1 peripheral clock register - @RegisterBlock(offset: 0x30) - public var ahb1enr: Register - - /// AHB2 peripheral clock enable register - @RegisterBlock(offset: 0x34) - public var ahb2enr: Register - - /// AHB3 peripheral clock enable register - @RegisterBlock(offset: 0x38) - public var ahb3enr: Register - - /// APB1 peripheral clock enable register - @RegisterBlock(offset: 0x40) - public var apb1enr: Register - - /// APB2 peripheral clock enable register - @RegisterBlock(offset: 0x44) - public var apb2enr: Register - - /// AHB1 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x50) - public var ahb1lpenr: Register - - /// AHB2 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x54) - public var ahb2lpenr: Register - - /// AHB3 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x58) - public var ahb3lpenr: Register - - /// APB1 peripheral clock enable in low power mode register - @RegisterBlock(offset: 0x60) - public var apb1lpenr: Register - - /// APB2 peripheral clock enabled in low power mode register - @RegisterBlock(offset: 0x64) - public var apb2lpenr: Register - - /// Backup domain control register - @RegisterBlock(offset: 0x70) - public var bdcr: Register - - /// clock control & status register - @RegisterBlock(offset: 0x74) - public var csr: Register - - /// spread spectrum clock generation register - @RegisterBlock(offset: 0x80) - public var sscgr: Register - - /// PLLI2S configuration register - @RegisterBlock(offset: 0x84) - public var plli2scfgr: Register - - /// PLL configuration register - @RegisterBlock(offset: 0x88) - public var pllsaicfgr: Register - - /// dedicated clocks configuration register - @RegisterBlock(offset: 0x8c) - public var dckcfgr1: Register - - /// dedicated clocks configuration register - @RegisterBlock(offset: 0x90) - public var dckcfgr2: Register -} - -extension RCC { - /// clock control register - @Register(bitWidth: 32) - public struct CR { - /// PLLI2S clock ready flag - @ReadOnly(bits: 27..<28) - public var plli2srdy: PLLI2SRDY - - /// PLLI2S enable - @ReadWrite(bits: 26..<27) - public var plli2son: PLLI2SON - - /// Main PLL (PLL) clock ready flag - @ReadOnly(bits: 25..<26) - public var pllrdy: PLLRDY - - /// Main PLL (PLL) enable - @ReadWrite(bits: 24..<25) - public var pllon: PLLON - - /// Clock security system enable - @ReadWrite(bits: 19..<20, as: CSSONValues.self) - public var csson: CSSON - - /// HSE clock bypass - @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) - public var hsebyp: HSEBYP - - /// HSE clock ready flag - @ReadOnly(bits: 17..<18) - public var hserdy: HSERDY - - /// HSE clock enable - @ReadWrite(bits: 16..<17) - public var hseon: HSEON - - /// Internal high-speed clock calibration - @ReadOnly(bits: 8..<16) - public var hsical: HSICAL - - /// Internal high-speed clock trimming - @ReadWrite(bits: 3..<8) - public var hsitrim: HSITRIM - - /// Internal high-speed clock ready flag - @ReadOnly(bits: 1..<2) - public var hsirdy: HSIRDY - - /// Internal high-speed clock enable - @ReadWrite(bits: 0..<1, as: HSIONValues.self) - public var hsion: HSION - - /// PLLSAI clock ready flag - @ReadOnly(bits: 29..<30) - public var pllsairdy: PLLSAIRDY - - /// PLLSAI enable - @ReadWrite(bits: 28..<29) - public var pllsaion: PLLSAION - } - - /// PLL configuration register - @Register(bitWidth: 32) - public struct PLLCFGR { - /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) - public var pllsrc: PLLSRC - - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 0..<6) - public var pllm: PLLM - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 6..<15) - public var plln: PLLN - - /// Main PLL (PLL) division factor for main system clock - @ReadWrite(bits: 16..<18, as: PLLPValues.self) - public var pllp: PLLP - - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 24..<28) - public var pllq: PLLQ - } - - /// clock configuration register - @Register(bitWidth: 32) - public struct CFGR { - /// Microcontroller clock output 2 - @ReadWrite(bits: 30..<32, as: MCO2Values.self) - public var mco2: MCO2 - - /// MCO2 prescaler - @ReadWrite(bits: 27..<30) - public var mco2pre: MCO2PRE - - /// MCO1 prescaler - @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) - public var mco1pre: MCO1PRE - - /// I2S clock selection - @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) - public var i2ssrc: I2SSRC - - /// Microcontroller clock output 1 - @ReadWrite(bits: 21..<23, as: MCO1Values.self) - public var mco1: MCO1 - - /// HSE division factor for RTC clock - @ReadWrite(bits: 16..<21) - public var rtcpre: RTCPRE - - /// APB high-speed prescaler (APB2) - @ReadWrite(bits: 13..<16) - public var ppre2: PPRE2 - - /// APB Low speed prescaler (APB1) - @ReadWrite(bits: 10..<13, as: PPRE1Values.self) - public var ppre1: PPRE1 - - /// AHB prescaler - @ReadWrite(bits: 4..<8, as: HPREValues.self) - public var hpre: HPRE - - /// System clock switch - @Reserved(bits: 0..<2, as: SWValues.self) - public var sw: SW - - /// System clock switch status - @Reserved(bits: 2..<4) - public var sws: SWS - } - - /// clock interrupt register - @Register(bitWidth: 32) - public struct CIR { - /// Clock security system interrupt clear - @WriteOnly(bits: 23..<24) - public var cssc: CSSC - - /// PLLSAI Ready Interrupt Clear - @WriteOnly(bits: 22..<23) - public var pllsairdyc: PLLSAIRDYC - - /// PLLI2S ready interrupt clear - @WriteOnly(bits: 21..<22) - public var plli2srdyc: PLLI2SRDYC - - /// Main PLL(PLL) ready interrupt clear - @WriteOnly(bits: 20..<21) - public var pllrdyc: PLLRDYC - - /// HSE ready interrupt clear - @WriteOnly(bits: 19..<20) - public var hserdyc: HSERDYC - - /// HSI ready interrupt clear - @WriteOnly(bits: 18..<19) - public var hsirdyc: HSIRDYC - - /// LSE ready interrupt clear - @WriteOnly(bits: 17..<18) - public var lserdyc: LSERDYC - - /// LSI ready interrupt clear - @WriteOnly(bits: 16..<17) - public var lsirdyc: LSIRDYC - - /// PLLSAI Ready Interrupt Enable - @ReadWrite(bits: 14..<15) - public var pllsairdyie: PLLSAIRDYIE - - /// PLLI2S ready interrupt enable - @ReadWrite(bits: 13..<14) - public var plli2srdyie: PLLI2SRDYIE - - /// Main PLL (PLL) ready interrupt enable - @ReadWrite(bits: 12..<13) - public var pllrdyie: PLLRDYIE - - /// HSE ready interrupt enable - @ReadWrite(bits: 11..<12) - public var hserdyie: HSERDYIE - - /// HSI ready interrupt enable - @ReadWrite(bits: 10..<11) - public var hsirdyie: HSIRDYIE - - /// LSE ready interrupt enable - @ReadWrite(bits: 9..<10) - public var lserdyie: LSERDYIE - - /// LSI ready interrupt enable - @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) - public var lsirdyie: LSIRDYIE - - /// Clock security system interrupt flag - @ReadOnly(bits: 7..<8) - public var cssf: CSSF - - /// PLLSAI ready interrupt flag - @ReadOnly(bits: 6..<7) - public var pllsairdyf: PLLSAIRDYF - - /// PLLI2S ready interrupt flag - @ReadOnly(bits: 5..<6) - public var plli2srdyf: PLLI2SRDYF - - /// Main PLL (PLL) ready interrupt flag - @ReadOnly(bits: 4..<5) - public var pllrdyf: PLLRDYF - - /// HSE ready interrupt flag - @ReadOnly(bits: 3..<4) - public var hserdyf: HSERDYF - - /// HSI ready interrupt flag - @ReadOnly(bits: 2..<3) - public var hsirdyf: HSIRDYF - - /// LSE ready interrupt flag - @ReadOnly(bits: 1..<2) - public var lserdyf: LSERDYF - - /// LSI ready interrupt flag - @ReadOnly(bits: 0..<1) - public var lsirdyf: LSIRDYF - } - - /// AHB1 peripheral reset register - @Register(bitWidth: 32) - public struct AHB1RSTR { - /// USB OTG HS module reset - @ReadWrite(bits: 29..<30) - public var otghsrst: OTGHSRST - - /// Ethernet MAC reset - @ReadWrite(bits: 25..<26) - public var ethmacrst: ETHMACRST - - /// DMA2D reset - @ReadWrite(bits: 23..<24) - public var dma2drst: DMA2DRST - - /// DMA2 reset - @ReadWrite(bits: 22..<23) - public var dma2rst: DMA2RST - - /// DMA2 reset - @ReadWrite(bits: 21..<22) - public var dma1rst: DMA1RST - - /// CRC reset - @ReadWrite(bits: 12..<13) - public var crcrst: CRCRST - - /// IO port K reset - @ReadWrite(bits: 10..<11) - public var gpiokrst: GPIOKRST - - /// IO port J reset - @ReadWrite(bits: 9..<10) - public var gpiojrst: GPIOJRST - - /// IO port I reset - @ReadWrite(bits: 8..<9) - public var gpioirst: GPIOIRST - - /// IO port H reset - @ReadWrite(bits: 7..<8) - public var gpiohrst: GPIOHRST - - /// IO port G reset - @ReadWrite(bits: 6..<7) - public var gpiogrst: GPIOGRST - - /// IO port F reset - @ReadWrite(bits: 5..<6) - public var gpiofrst: GPIOFRST - - /// IO port E reset - @ReadWrite(bits: 4..<5) - public var gpioerst: GPIOERST - - /// IO port D reset - @ReadWrite(bits: 3..<4) - public var gpiodrst: GPIODRST - - /// IO port C reset - @ReadWrite(bits: 2..<3) - public var gpiocrst: GPIOCRST - - /// IO port B reset - @ReadWrite(bits: 1..<2) - public var gpiobrst: GPIOBRST - - /// IO port A reset - @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) - public var gpioarst: GPIOARST - } - - /// AHB2 peripheral reset register - @Register(bitWidth: 32) - public struct AHB2RSTR { - /// USB OTG FS module reset - @ReadWrite(bits: 7..<8) - public var otgfsrst: OTGFSRST - - /// Random number generator module reset - @ReadWrite(bits: 6..<7) - public var rngrst: RNGRST - - /// Hash module reset - @ReadWrite(bits: 5..<6) - public var hsahrst: HSAHRST - - /// Cryptographic module reset - @ReadWrite(bits: 4..<5) - public var cryprst: CRYPRST - - /// Camera interface reset - @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) - public var dcmirst: DCMIRST - } - - /// AHB3 peripheral reset register - @Register(bitWidth: 32) - public struct AHB3RSTR { - /// Flexible memory controller module reset - @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) - public var fmcrst: FMCRST - - /// Quad SPI memory controller reset - @ReadWrite(bits: 1..<2) - public var qspirst: QSPIRST - } - - /// APB1 peripheral reset register - @Register(bitWidth: 32) - public struct APB1RSTR { - /// TIM2 reset - @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) - public var tim2rst: TIM2RST - - /// TIM3 reset - @ReadWrite(bits: 1..<2) - public var tim3rst: TIM3RST - - /// TIM4 reset - @ReadWrite(bits: 2..<3) - public var tim4rst: TIM4RST - - /// TIM5 reset - @ReadWrite(bits: 3..<4) - public var tim5rst: TIM5RST - - /// TIM6 reset - @ReadWrite(bits: 4..<5) - public var tim6rst: TIM6RST - - /// TIM7 reset - @ReadWrite(bits: 5..<6) - public var tim7rst: TIM7RST - - /// TIM12 reset - @ReadWrite(bits: 6..<7) - public var tim12rst: TIM12RST - - /// TIM13 reset - @ReadWrite(bits: 7..<8) - public var tim13rst: TIM13RST - - /// TIM14 reset - @ReadWrite(bits: 8..<9) - public var tim14rst: TIM14RST - - /// Window watchdog reset - @ReadWrite(bits: 11..<12) - public var wwdgrst: WWDGRST - - /// SPI 2 reset - @ReadWrite(bits: 14..<15) - public var spi2rst: SPI2RST - - /// SPI 3 reset - @ReadWrite(bits: 15..<16) - public var spi3rst: SPI3RST - - /// USART 2 reset - @ReadWrite(bits: 17..<18) - public var usart2rst: USART2RST - - /// USART 3 reset - @ReadWrite(bits: 18..<19) - public var usart3rst: USART3RST - - /// USART 4 reset - @ReadWrite(bits: 19..<20) - public var uart4rst: UART4RST - - /// USART 5 reset - @ReadWrite(bits: 20..<21) - public var uart5rst: UART5RST - - /// I2C 1 reset - @ReadWrite(bits: 21..<22) - public var i2c1rst: I2C1RST - - /// I2C 2 reset - @ReadWrite(bits: 22..<23) - public var i2c2rst: I2C2RST - - /// I2C3 reset - @ReadWrite(bits: 23..<24) - public var i2c3rst: I2C3RST - - /// CAN1 reset - @ReadWrite(bits: 25..<26) - public var can1rst: CAN1RST - - /// CAN2 reset - @ReadWrite(bits: 26..<27) - public var can2rst: CAN2RST - - /// Power interface reset - @ReadWrite(bits: 28..<29) - public var pwrrst: PWRRST - - /// DAC reset - @ReadWrite(bits: 29..<30) - public var dacrst: DACRST - - /// UART7 reset - @ReadWrite(bits: 30..<31) - public var uart7rst: UART7RST - - /// UART8 reset - @ReadWrite(bits: 31..<32) - public var uart8rst: UART8RST - - /// SPDIF-RX reset - @ReadWrite(bits: 16..<17) - public var spdifrxrst: SPDIFRXRST - - /// HDMI-CEC reset - @ReadWrite(bits: 27..<28) - public var cecrst: CECRST - - /// Low power timer 1 reset - @ReadWrite(bits: 9..<10) - public var lptim1rst: LPTIM1RST - - /// I2C 4 reset - @ReadWrite(bits: 24..<25) - public var i2c4rst: I2C4RST - } - - /// APB2 peripheral reset register - @Register(bitWidth: 32) - public struct APB2RSTR { - /// TIM1 reset - @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) - public var tim1rst: TIM1RST - - /// TIM8 reset - @ReadWrite(bits: 1..<2) - public var tim8rst: TIM8RST - - /// USART1 reset - @ReadWrite(bits: 4..<5) - public var usart1rst: USART1RST - - /// USART6 reset - @ReadWrite(bits: 5..<6) - public var usart6rst: USART6RST - - /// ADC interface reset (common to all ADCs) - @ReadWrite(bits: 8..<9) - public var adcrst: ADCRST - - /// SPI 1 reset - @ReadWrite(bits: 12..<13) - public var spi1rst: SPI1RST - - /// SPI4 reset - @ReadWrite(bits: 13..<14) - public var spi4rst: SPI4RST - - /// System configuration controller reset - @ReadWrite(bits: 14..<15) - public var syscfgrst: SYSCFGRST - - /// TIM9 reset - @ReadWrite(bits: 16..<17) - public var tim9rst: TIM9RST - - /// TIM10 reset - @ReadWrite(bits: 17..<18) - public var tim10rst: TIM10RST - - /// TIM11 reset - @ReadWrite(bits: 18..<19) - public var tim11rst: TIM11RST - - /// SPI5 reset - @ReadWrite(bits: 20..<21) - public var spi5rst: SPI5RST - - /// SPI6 reset - @ReadWrite(bits: 21..<22) - public var spi6rst: SPI6RST - - /// SAI1 reset - @ReadWrite(bits: 22..<23) - public var sai1rst: SAI1RST - - /// LTDC reset - @ReadWrite(bits: 26..<27) - public var ltdcrst: LTDCRST - - /// SAI2 reset - @ReadWrite(bits: 23..<24) - public var sai2rst: SAI2RST - - /// SDMMC1 reset - @ReadWrite(bits: 11..<12) - public var sdmmc1rst: SDMMC1RST - } - - /// AHB1 peripheral clock register - @Register(bitWidth: 32) - public struct AHB1ENR { - /// USB OTG HSULPI clock enable - @ReadWrite(bits: 30..<31) - public var otghsulpien: OTGHSULPIEN - - /// USB OTG HS clock enable - @ReadWrite(bits: 29..<30) - public var otghsen: OTGHSEN - - /// Ethernet PTP clock enable - @ReadWrite(bits: 28..<29) - public var ethmacptpen: ETHMACPTPEN - - /// Ethernet Reception clock enable - @ReadWrite(bits: 27..<28) - public var ethmacrxen: ETHMACRXEN - - /// Ethernet Transmission clock enable - @ReadWrite(bits: 26..<27) - public var ethmactxen: ETHMACTXEN - - /// Ethernet MAC clock enable - @ReadWrite(bits: 25..<26) - public var ethmacen: ETHMACEN - - /// DMA2D clock enable - @ReadWrite(bits: 23..<24) - public var dma2den: DMA2DEN - - /// DMA2 clock enable - @ReadWrite(bits: 22..<23) - public var dma2en: DMA2EN - - /// DMA1 clock enable - @ReadWrite(bits: 21..<22) - public var dma1en: DMA1EN - - /// CCM data RAM clock enable - @ReadWrite(bits: 20..<21) - public var dtcmramen: DTCMRAMEN - - /// Backup SRAM interface clock enable - @ReadWrite(bits: 18..<19) - public var bkpsramen: BKPSRAMEN - - /// CRC clock enable - @ReadWrite(bits: 12..<13) - public var crcen: CRCEN - - /// IO port K clock enable - @ReadWrite(bits: 10..<11) - public var gpioken: GPIOKEN - - /// IO port J clock enable - @ReadWrite(bits: 9..<10) - public var gpiojen: GPIOJEN - - /// IO port I clock enable - @ReadWrite(bits: 8..<9) - public var gpioien: GPIOIEN - - /// IO port H clock enable - @ReadWrite(bits: 7..<8) - public var gpiohen: GPIOHEN - - /// IO port G clock enable - @ReadWrite(bits: 6..<7) - public var gpiogen: GPIOGEN - - /// IO port F clock enable - @ReadWrite(bits: 5..<6) - public var gpiofen: GPIOFEN - - /// IO port E clock enable - @ReadWrite(bits: 4..<5) - public var gpioeen: GPIOEEN - - /// IO port D clock enable - @ReadWrite(bits: 3..<4) - public var gpioden: GPIODEN - - /// IO port C clock enable - @ReadWrite(bits: 2..<3) - public var gpiocen: GPIOCEN - - /// IO port B clock enable - @ReadWrite(bits: 1..<2) - public var gpioben: GPIOBEN - - /// IO port A clock enable - @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) - public var gpioaen: GPIOAEN - } - - /// AHB2 peripheral clock enable register - @Register(bitWidth: 32) - public struct AHB2ENR { - /// USB OTG FS clock enable - @ReadWrite(bits: 7..<8) - public var otgfsen: OTGFSEN - - /// Random number generator clock enable - @ReadWrite(bits: 6..<7) - public var rngen: RNGEN - - /// Hash modules clock enable - @ReadWrite(bits: 5..<6) - public var hashen: HASHEN - - /// Cryptographic modules clock enable - @ReadWrite(bits: 4..<5) - public var crypen: CRYPEN - - /// Camera interface enable - @ReadWrite(bits: 0..<1, as: DCMIENValues.self) - public var dcmien: DCMIEN - } - - /// AHB3 peripheral clock enable register - @Register(bitWidth: 32) - public struct AHB3ENR { - /// Flexible memory controller module clock enable - @ReadWrite(bits: 0..<1, as: FMCENValues.self) - public var fmcen: FMCEN - - /// Quad SPI memory controller clock enable - @ReadWrite(bits: 1..<2) - public var qspien: QSPIEN - } - - /// APB1 peripheral clock enable register - @Register(bitWidth: 32) - public struct APB1ENR { - /// TIM2 clock enable - @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) - public var tim2en: TIM2EN - - /// TIM3 clock enable - @ReadWrite(bits: 1..<2) - public var tim3en: TIM3EN - - /// TIM4 clock enable - @ReadWrite(bits: 2..<3) - public var tim4en: TIM4EN - - /// TIM5 clock enable - @ReadWrite(bits: 3..<4) - public var tim5en: TIM5EN - - /// TIM6 clock enable - @ReadWrite(bits: 4..<5) - public var tim6en: TIM6EN - - /// TIM7 clock enable - @ReadWrite(bits: 5..<6) - public var tim7en: TIM7EN - - /// TIM12 clock enable - @ReadWrite(bits: 6..<7) - public var tim12en: TIM12EN - - /// TIM13 clock enable - @ReadWrite(bits: 7..<8) - public var tim13en: TIM13EN - - /// TIM14 clock enable - @ReadWrite(bits: 8..<9) - public var tim14en: TIM14EN - - /// Window watchdog clock enable - @ReadWrite(bits: 11..<12) - public var wwdgen: WWDGEN - - /// SPI2 clock enable - @ReadWrite(bits: 14..<15) - public var spi2en: SPI2EN - - /// SPI3 clock enable - @ReadWrite(bits: 15..<16) - public var spi3en: SPI3EN - - /// USART 2 clock enable - @ReadWrite(bits: 17..<18) - public var usart2en: USART2EN - - /// USART3 clock enable - @ReadWrite(bits: 18..<19) - public var usart3en: USART3EN - - /// UART4 clock enable - @ReadWrite(bits: 19..<20) - public var uart4en: UART4EN - - /// UART5 clock enable - @ReadWrite(bits: 20..<21) - public var uart5en: UART5EN - - /// I2C1 clock enable - @ReadWrite(bits: 21..<22) - public var i2c1en: I2C1EN - - /// I2C2 clock enable - @ReadWrite(bits: 22..<23) - public var i2c2en: I2C2EN - - /// I2C3 clock enable - @ReadWrite(bits: 23..<24) - public var i2c3en: I2C3EN - - /// CAN 1 clock enable - @ReadWrite(bits: 25..<26) - public var can1en: CAN1EN - - /// CAN 2 clock enable - @ReadWrite(bits: 26..<27) - public var can2en: CAN2EN - - /// Power interface clock enable - @ReadWrite(bits: 28..<29) - public var pwren: PWREN - - /// DAC interface clock enable - @ReadWrite(bits: 29..<30) - public var dacen: DACEN - - /// UART7 clock enable - @ReadWrite(bits: 30..<31) - public var uart7en: UART7EN - - /// UART8 clock enable - @ReadWrite(bits: 31..<32) - public var uart8en: UART8EN - - /// SPDIF-RX clock enable - @ReadWrite(bits: 16..<17) - public var spdifrxen: SPDIFRXEN - - /// HDMI-CEN clock enable - @ReadWrite(bits: 27..<28) - public var cecen: CECEN - - /// Low power timer 1 clock enable - @ReadWrite(bits: 9..<10) - public var lptim1en: LPTIM1EN - - /// I2C4 clock enable - @ReadWrite(bits: 24..<25) - public var i2c4en: I2C4EN - } - - /// APB2 peripheral clock enable register - @Register(bitWidth: 32) - public struct APB2ENR { - /// TIM1 clock enable - @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) - public var tim1en: TIM1EN - - /// TIM8 clock enable - @ReadWrite(bits: 1..<2) - public var tim8en: TIM8EN - - /// USART1 clock enable - @ReadWrite(bits: 4..<5) - public var usart1en: USART1EN - - /// USART6 clock enable - @ReadWrite(bits: 5..<6) - public var usart6en: USART6EN - - /// ADC1 clock enable - @ReadWrite(bits: 8..<9) - public var adc1en: ADC1EN - - /// ADC2 clock enable - @ReadWrite(bits: 9..<10) - public var adc2en: ADC2EN - - /// ADC3 clock enable - @ReadWrite(bits: 10..<11) - public var adc3en: ADC3EN - - /// SPI1 clock enable - @ReadWrite(bits: 12..<13) - public var spi1en: SPI1EN - - /// SPI4 clock enable - @ReadWrite(bits: 13..<14) - public var spi4en: SPI4EN - - /// System configuration controller clock enable - @ReadWrite(bits: 14..<15) - public var syscfgen: SYSCFGEN - - /// TIM9 clock enable - @ReadWrite(bits: 16..<17) - public var tim9en: TIM9EN - - /// TIM10 clock enable - @ReadWrite(bits: 17..<18) - public var tim10en: TIM10EN - - /// TIM11 clock enable - @ReadWrite(bits: 18..<19) - public var tim11en: TIM11EN - - /// SPI5 clock enable - @ReadWrite(bits: 20..<21) - public var spi5en: SPI5EN - - /// SPI6 clock enable - @ReadWrite(bits: 21..<22) - public var spi6en: SPI6EN - - /// SAI1 clock enable - @ReadWrite(bits: 22..<23) - public var sai1en: SAI1EN - - /// LTDC clock enable - @ReadWrite(bits: 26..<27) - public var ltdcen: LTDCEN - - /// SAI2 clock enable - @ReadWrite(bits: 23..<24) - public var sai2en: SAI2EN - - /// SDMMC1 clock enable - @ReadWrite(bits: 11..<12) - public var sdmmc1en: SDMMC1EN - } - - /// AHB1 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB1LPENR { - /// IO port A clock enable during sleep mode - @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) - public var gpioalpen: GPIOALPEN - - /// IO port B clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var gpioblpen: GPIOBLPEN - - /// IO port C clock enable during Sleep mode - @ReadWrite(bits: 2..<3) - public var gpioclpen: GPIOCLPEN - - /// IO port D clock enable during Sleep mode - @ReadWrite(bits: 3..<4) - public var gpiodlpen: GPIODLPEN - - /// IO port E clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var gpioelpen: GPIOELPEN - - /// IO port F clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var gpioflpen: GPIOFLPEN - - /// IO port G clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var gpioglpen: GPIOGLPEN - - /// IO port H clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var gpiohlpen: GPIOHLPEN - - /// IO port I clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var gpioilpen: GPIOILPEN - - /// IO port J clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var gpiojlpen: GPIOJLPEN - - /// IO port K clock enable during Sleep mode - @ReadWrite(bits: 10..<11) - public var gpioklpen: GPIOKLPEN - - /// CRC clock enable during Sleep mode - @ReadWrite(bits: 12..<13) - public var crclpen: CRCLPEN - - /// Flash interface clock enable during Sleep mode - @ReadWrite(bits: 15..<16) - public var flitflpen: FLITFLPEN - - /// SRAM 1interface clock enable during Sleep mode - @ReadWrite(bits: 16..<17) - public var sram1lpen: SRAM1LPEN - - /// SRAM 2 interface clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var sram2lpen: SRAM2LPEN - - /// Backup SRAM interface clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var bkpsramlpen: BKPSRAMLPEN - - /// SRAM 3 interface clock enable during Sleep mode - @ReadWrite(bits: 19..<20) - public var sram3lpen: SRAM3LPEN - - /// DMA1 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var dma1lpen: DMA1LPEN - - /// DMA2 clock enable during Sleep mode - @ReadWrite(bits: 22..<23) - public var dma2lpen: DMA2LPEN - - /// DMA2D clock enable during Sleep mode - @ReadWrite(bits: 23..<24) - public var dma2dlpen: DMA2DLPEN - - /// Ethernet MAC clock enable during Sleep mode - @ReadWrite(bits: 25..<26) - public var ethmaclpen: ETHMACLPEN - - /// Ethernet transmission clock enable during Sleep mode - @ReadWrite(bits: 26..<27) - public var ethmactxlpen: ETHMACTXLPEN - - /// Ethernet reception clock enable during Sleep mode - @ReadWrite(bits: 27..<28) - public var ethmacrxlpen: ETHMACRXLPEN - - /// Ethernet PTP clock enable during Sleep mode - @ReadWrite(bits: 28..<29) - public var ethmacptplpen: ETHMACPTPLPEN - - /// USB OTG HS clock enable during Sleep mode - @ReadWrite(bits: 29..<30) - public var otghslpen: OTGHSLPEN - - /// USB OTG HS ULPI clock enable during Sleep mode - @ReadWrite(bits: 30..<31) - public var otghsulpilpen: OTGHSULPILPEN - - /// AXI to AHB bridge clock enable during Sleep mode - @ReadWrite(bits: 13..<14) - public var axilpen: AXILPEN - - /// DTCM RAM interface clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var dtcmlpen: DTCMLPEN - } - - /// AHB2 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB2LPENR { - /// USB OTG FS clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var otgfslpen: OTGFSLPEN - - /// Random number generator clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var rnglpen: RNGLPEN - - /// Hash modules clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var hashlpen: HASHLPEN - - /// Cryptography modules clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var cryplpen: CRYPLPEN - - /// Camera interface enable during Sleep mode - @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) - public var dcmilpen: DCMILPEN - } - - /// AHB3 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct AHB3LPENR { - /// Flexible memory controller module clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) - public var fmclpen: FMCLPEN - - /// Quand SPI memory controller clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var qspilpen: QSPILPEN - } - - /// APB1 peripheral clock enable in low power mode register - @Register(bitWidth: 32) - public struct APB1LPENR { - /// TIM2 clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) - public var tim2lpen: TIM2LPEN - - /// TIM3 clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var tim3lpen: TIM3LPEN - - /// TIM4 clock enable during Sleep mode - @ReadWrite(bits: 2..<3) - public var tim4lpen: TIM4LPEN - - /// TIM5 clock enable during Sleep mode - @ReadWrite(bits: 3..<4) - public var tim5lpen: TIM5LPEN - - /// TIM6 clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var tim6lpen: TIM6LPEN - - /// TIM7 clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var tim7lpen: TIM7LPEN - - /// TIM12 clock enable during Sleep mode - @ReadWrite(bits: 6..<7) - public var tim12lpen: TIM12LPEN - - /// TIM13 clock enable during Sleep mode - @ReadWrite(bits: 7..<8) - public var tim13lpen: TIM13LPEN - - /// TIM14 clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var tim14lpen: TIM14LPEN - - /// Window watchdog clock enable during Sleep mode - @ReadWrite(bits: 11..<12) - public var wwdglpen: WWDGLPEN - - /// SPI2 clock enable during Sleep mode - @ReadWrite(bits: 14..<15) - public var spi2lpen: SPI2LPEN - - /// SPI3 clock enable during Sleep mode - @ReadWrite(bits: 15..<16) - public var spi3lpen: SPI3LPEN - - /// USART2 clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var usart2lpen: USART2LPEN - - /// USART3 clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var usart3lpen: USART3LPEN - - /// UART4 clock enable during Sleep mode - @ReadWrite(bits: 19..<20) - public var uart4lpen: UART4LPEN - - /// UART5 clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var uart5lpen: UART5LPEN - - /// I2C1 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var i2c1lpen: I2C1LPEN - - /// I2C2 clock enable during Sleep mode - @ReadWrite(bits: 22..<23) - public var i2c2lpen: I2C2LPEN - - /// I2C3 clock enable during Sleep mode - @ReadWrite(bits: 23..<24) - public var i2c3lpen: I2C3LPEN - - /// CAN 1 clock enable during Sleep mode - @ReadWrite(bits: 25..<26) - public var can1lpen: CAN1LPEN - - /// CAN 2 clock enable during Sleep mode - @ReadWrite(bits: 26..<27) - public var can2lpen: CAN2LPEN - - /// Power interface clock enable during Sleep mode - @ReadWrite(bits: 28..<29) - public var pwrlpen: PWRLPEN - - /// DAC interface clock enable during Sleep mode - @ReadWrite(bits: 29..<30) - public var daclpen: DACLPEN - - /// UART7 clock enable during Sleep mode - @ReadWrite(bits: 30..<31) - public var uart7lpen: UART7LPEN - - /// UART8 clock enable during Sleep mode - @ReadWrite(bits: 31..<32) - public var uart8lpen: UART8LPEN - - /// SPDIF-RX clock enable during sleep mode - @ReadWrite(bits: 16..<17) - public var spdifrxlpen: SPDIFRXLPEN - - /// HDMI-CEN clock enable during Sleep mode - @ReadWrite(bits: 27..<28) - public var ceclpen: CECLPEN - - /// low power timer 1 clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var lptim1lpen: LPTIM1LPEN - - /// I2C4 clock enable during Sleep mode - @ReadWrite(bits: 24..<25) - public var i2c4lpen: I2C4LPEN - } - - /// APB2 peripheral clock enabled in low power mode register - @Register(bitWidth: 32) - public struct APB2LPENR { - /// TIM1 clock enable during Sleep mode - @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) - public var tim1lpen: TIM1LPEN - - /// TIM8 clock enable during Sleep mode - @ReadWrite(bits: 1..<2) - public var tim8lpen: TIM8LPEN - - /// USART1 clock enable during Sleep mode - @ReadWrite(bits: 4..<5) - public var usart1lpen: USART1LPEN - - /// USART6 clock enable during Sleep mode - @ReadWrite(bits: 5..<6) - public var usart6lpen: USART6LPEN - - /// ADC1 clock enable during Sleep mode - @ReadWrite(bits: 8..<9) - public var adc1lpen: ADC1LPEN - - /// ADC2 clock enable during Sleep mode - @ReadWrite(bits: 9..<10) - public var adc2lpen: ADC2LPEN - - /// ADC 3 clock enable during Sleep mode - @ReadWrite(bits: 10..<11) - public var adc3lpen: ADC3LPEN - - /// SPI 1 clock enable during Sleep mode - @ReadWrite(bits: 12..<13) - public var spi1lpen: SPI1LPEN - - /// SPI 4 clock enable during Sleep mode - @ReadWrite(bits: 13..<14) - public var spi4lpen: SPI4LPEN - - /// System configuration controller clock enable during Sleep mode - @ReadWrite(bits: 14..<15) - public var syscfglpen: SYSCFGLPEN - - /// TIM9 clock enable during sleep mode - @ReadWrite(bits: 16..<17) - public var tim9lpen: TIM9LPEN - - /// TIM10 clock enable during Sleep mode - @ReadWrite(bits: 17..<18) - public var tim10lpen: TIM10LPEN - - /// TIM11 clock enable during Sleep mode - @ReadWrite(bits: 18..<19) - public var tim11lpen: TIM11LPEN - - /// SPI 5 clock enable during Sleep mode - @ReadWrite(bits: 20..<21) - public var spi5lpen: SPI5LPEN - - /// SPI 6 clock enable during Sleep mode - @ReadWrite(bits: 21..<22) - public var spi6lpen: SPI6LPEN - - /// SAI1 clock enable during sleep mode - @ReadWrite(bits: 22..<23) - public var sai1lpen: SAI1LPEN - - /// LTDC clock enable during sleep mode - @ReadWrite(bits: 26..<27) - public var ltdclpen: LTDCLPEN - - /// SAI2 clock enable during sleep mode - @ReadWrite(bits: 23..<24) - public var sai2lpen: SAI2LPEN - - /// SDMMC1 clock enable during Sleep mode - @ReadWrite(bits: 11..<12) - public var sdmmc1lpen: SDMMC1LPEN - } - - /// Backup domain control register - @Register(bitWidth: 32) - public struct BDCR { - /// Backup domain software reset - @ReadWrite(bits: 16..<17, as: BDRSTValues.self) - public var bdrst: BDRST - - /// RTC clock enable - @ReadWrite(bits: 15..<16, as: RTCENValues.self) - public var rtcen: RTCEN - - /// External low-speed oscillator bypass - @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) - public var lsebyp: LSEBYP - - /// External low-speed oscillator ready - @ReadOnly(bits: 1..<2) - public var lserdy: LSERDY - - /// External low-speed oscillator enable - @ReadWrite(bits: 0..<1, as: LSEONValues.self) - public var lseon: LSEON - - /// LSE oscillator drive capability - @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) - public var lsedrv: LSEDRV - - /// RTC clock source selection - @Reserved(bits: 8..<10, as: RTCSELValues.self) - public var rtcsel: RTCSEL - } - - /// clock control & status register - @Register(bitWidth: 32) - public struct CSR { - /// Low-power reset flag - @ReadWrite(bits: 31..<32) - public var lpwrrstf: LPWRRSTF - - /// Window watchdog reset flag - @ReadWrite(bits: 30..<31) - public var wwdgrstf: WWDGRSTF - - /// Independent watchdog reset flag - @ReadWrite(bits: 29..<30) - public var wdgrstf: WDGRSTF - - /// Software reset flag - @ReadWrite(bits: 28..<29) - public var sftrstf: SFTRSTF - - /// POR/PDR reset flag - @ReadWrite(bits: 27..<28) - public var porrstf: PORRSTF - - /// PIN reset flag - @ReadWrite(bits: 26..<27) - public var padrstf: PADRSTF - - /// BOR reset flag - @ReadWrite(bits: 25..<26) - public var borrstf: BORRSTF - - /// Remove reset flag - @ReadWrite(bits: 24..<25) - public var rmvf: RMVF - - /// Internal low-speed oscillator ready - @ReadOnly(bits: 1..<2) - public var lsirdy: LSIRDY - - /// Internal low-speed oscillator enable - @ReadWrite(bits: 0..<1, as: LSIONValues.self) - public var lsion: LSION - } - - /// spread spectrum clock generation register - @Register(bitWidth: 32) - public struct SSCGR { - /// Spread spectrum modulation enable - @ReadWrite(bits: 31..<32, as: SSCGENValues.self) - public var sscgen: SSCGEN - - /// Spread Select - @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) - public var spreadsel: SPREADSEL - - /// Incrementation step - @ReadWrite(bits: 13..<28) - public var incstep: INCSTEP - - /// Modulation period - @ReadWrite(bits: 0..<13) - public var modper: MODPER - } - - /// PLLI2S configuration register - @Register(bitWidth: 32) - public struct PLLI2SCFGR { - /// PLLI2S division factor for I2S clocks - @ReadWrite(bits: 28..<31) - public var plli2sr: PLLI2SR - - /// PLLI2S division factor for SAI1 clock - @ReadWrite(bits: 24..<28) - public var plli2sq: PLLI2SQ - - /// PLLI2S multiplication factor for VCO - @ReadWrite(bits: 6..<15) - public var plli2sn: PLLI2SN - - /// PLLI2S division factor for SPDIFRX clock - @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) - public var plli2sp: PLLI2SP - } - - /// PLL configuration register - @Register(bitWidth: 32) - public struct PLLSAICFGR { - /// PLLSAI division factor for VCO - @ReadWrite(bits: 6..<15) - public var pllsain: PLLSAIN - - /// PLLSAI division factor for 48MHz clock - @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) - public var pllsaip: PLLSAIP - - /// PLLSAI division factor for SAI clock - @ReadWrite(bits: 24..<28) - public var pllsaiq: PLLSAIQ - - /// PLLSAI division factor for LCD clock - @ReadWrite(bits: 28..<31) - public var pllsair: PLLSAIR - } - - /// dedicated clocks configuration register - @Register(bitWidth: 32) - public struct DCKCFGR1 { - /// PLLI2S division factor for SAI1 clock - @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) - public var plli2sdivq: PLLI2SDIVQ - - /// PLLSAI division factor for SAI1 clock - @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) - public var pllsaidivq: PLLSAIDIVQ - - /// division factor for LCD_CLK - @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) - public var pllsaidivr: PLLSAIDIVR - - /// SAI1 clock source selection - @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) - public var sai1sel: SAI1SEL - - /// SAI2 clock source selection - @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) - public var sai2sel: SAI2SEL - - /// Timers clocks prescalers selection - @ReadWrite(bits: 24..<25, as: TIMPREValues.self) - public var timpre: TIMPRE - } - - /// dedicated clocks configuration register - @Register(bitWidth: 32) - public struct DCKCFGR2 { - /// USART 1 clock source selection - @ReadWrite(bits: 0..<2, as: USART1SELValues.self) - public var usart1sel: USART1SEL - - /// USART 2 clock source selection - @ReadWrite(bits: 2..<4, as: USART2SELValues.self) - public var usart2sel: USART2SEL - - /// USART 3 clock source selection - @ReadWrite(bits: 4..<6) - public var usart3sel: USART3SEL - - /// UART 4 clock source selection - @ReadWrite(bits: 6..<8) - public var uart4sel: UART4SEL - - /// UART 5 clock source selection - @ReadWrite(bits: 8..<10) - public var uart5sel: UART5SEL - - /// USART 6 clock source selection - @ReadWrite(bits: 10..<12) - public var usart6sel: USART6SEL - - /// UART 7 clock source selection - @ReadWrite(bits: 12..<14) - public var uart7sel: UART7SEL - - /// UART 8 clock source selection - @ReadWrite(bits: 14..<16) - public var uart8sel: UART8SEL - - /// I2C1 clock source selection - @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) - public var i2c1sel: I2C1SEL - - /// I2C2 clock source selection - @ReadWrite(bits: 18..<20) - public var i2c2sel: I2C2SEL - - /// I2C3 clock source selection - @ReadWrite(bits: 20..<22) - public var i2c3sel: I2C3SEL - - /// I2C4 clock source selection - @ReadWrite(bits: 22..<24) - public var i2c4sel: I2C4SEL - - /// Low power timer 1 clock source selection - @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) - public var lptim1sel: LPTIM1SEL - - /// HDMI-CEC clock source selection - @ReadWrite(bits: 26..<27, as: CECSELValues.self) - public var cecsel: CECSEL - - /// 48MHz clock source selection - @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) - public var ck48msel: CK48MSEL - - /// SDMMC clock source selection - @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) - public var sdmmc1sel: SDMMC1SEL - } -} - -extension RCC.CR { - public struct CSSONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Clock security system disabled (clock detector OFF) - public static let Off = Self(rawValue: 0x0) - - /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CR { - public struct HSEBYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// HSE crystal oscillator not bypassed - public static let NotBypassed = Self(rawValue: 0x0) - - /// HSE crystal oscillator bypassed with external clock - public static let Bypassed = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CR { - public struct HSIONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Clock Off - public static let Off = Self(rawValue: 0x0) - - /// Clock On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLCFGR { - public struct PLLSRCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// HSI clock selected as PLL and PLLI2S clock entry - public static let HSI = Self(rawValue: 0x0) - - /// HSE oscillator clock selected as PLL and PLLI2S clock entry - public static let HSE = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLCFGR { - public struct PLLPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLLP=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLLP=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLLP=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLLP=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO2Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// System clock (SYSCLK) selected - public static let SYSCLK = Self(rawValue: 0x0) - - /// PLLI2S clock selected - public static let PLLI2S = Self(rawValue: 0x1) - - /// HSE oscillator clock selected - public static let HSE = Self(rawValue: 0x2) - - /// PLL clock selected - public static let PLL = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO1PREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// No division - public static let Div1 = Self(rawValue: 0x0) - - /// Division by 2 - public static let Div2 = Self(rawValue: 0x4) - - /// Division by 3 - public static let Div3 = Self(rawValue: 0x5) - - /// Division by 4 - public static let Div4 = Self(rawValue: 0x6) - - /// Division by 5 - public static let Div5 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct I2SSRCValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// PLLI2S clock used as I2S clock source - public static let PLLI2S = Self(rawValue: 0x0) - - /// External clock mapped on the I2S_CKIN pin used as I2S clock source - public static let CKIN = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct MCO1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// HSI clock selected - public static let HSI = Self(rawValue: 0x0) - - /// LSE oscillator selected - public static let LSE = Self(rawValue: 0x1) - - /// HSE oscillator clock selected - public static let HSE = Self(rawValue: 0x2) - - /// PLL clock selected - public static let PLL = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct PPRE1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 3 - - /// HCLK not divided - public static let Div1 = Self(rawValue: 0x0) - - /// HCLK divided by 2 - public static let Div2 = Self(rawValue: 0x4) - - /// HCLK divided by 4 - public static let Div4 = Self(rawValue: 0x5) - - /// HCLK divided by 8 - public static let Div8 = Self(rawValue: 0x6) - - /// HCLK divided by 16 - public static let Div16 = Self(rawValue: 0x7) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct HPREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 4 - - /// SYSCLK not divided - public static let Div1 = Self(rawValue: 0x0) - - /// SYSCLK divided by 2 - public static let Div2 = Self(rawValue: 0x8) - - /// SYSCLK divided by 4 - public static let Div4 = Self(rawValue: 0x9) - - /// SYSCLK divided by 8 - public static let Div8 = Self(rawValue: 0xa) - - /// SYSCLK divided by 16 - public static let Div16 = Self(rawValue: 0xb) - - /// SYSCLK divided by 64 - public static let Div64 = Self(rawValue: 0xc) - - /// SYSCLK divided by 128 - public static let Div128 = Self(rawValue: 0xd) - - /// SYSCLK divided by 256 - public static let Div256 = Self(rawValue: 0xe) - - /// SYSCLK divided by 512 - public static let Div512 = Self(rawValue: 0xf) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CFGR { - public struct SWValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// HSI selected as system clock - public static let HSI = Self(rawValue: 0x0) - - /// HSE selected as system clock - public static let HSE = Self(rawValue: 0x1) - - /// PLL selected as system clock - public static let PLL = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CIR { - public struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1RSTR { - public struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2RSTR { - public struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3RSTR { - public struct FMCRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1RSTR { - public struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2RSTR { - public struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset the selected module - public static let Reset = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1ENR { - public struct GPIOAENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2ENR { - public struct DCMIENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3ENR { - public struct FMCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1ENR { - public struct TIM2ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2ENR { - public struct TIM1ENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The selected clock is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The selected clock is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB1LPENR { - public struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB2LPENR { - public struct DCMILPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.AHB3LPENR { - public struct FMCLPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB1LPENR { - public struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.APB2LPENR { - public struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Selected module is disabled during Sleep mode - public static let DisabledInSleep = Self(rawValue: 0x0) - - /// Selected module is enabled during Sleep mode - public static let EnabledInSleep = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct BDRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Reset not activated - public static let Disabled = Self(rawValue: 0x0) - - /// Reset the entire RTC domain - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct RTCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RTC clock disabled - public static let Disabled = Self(rawValue: 0x0) - - /// RTC clock enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEBYPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE crystal oscillator not bypassed - public static let NotBypassed = Self(rawValue: 0x0) - - /// LSE crystal oscillator bypassed with external clock - public static let Bypassed = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE oscillator Off - public static let Off = Self(rawValue: 0x0) - - /// LSE oscillator On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct LSEDRVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Low drive capacity - public static let Low = Self(rawValue: 0x0) - - /// Medium-high drive capacity - public static let MediumHigh = Self(rawValue: 0x1) - - /// Medium-low drive capacity - public static let MediumLow = Self(rawValue: 0x2) - - /// High drive capacity - public static let High = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.BDCR { - public struct RTCSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// No clock - public static let NoClock = Self(rawValue: 0x0) - - /// LSE oscillator clock used as RTC clock - public static let LSE = Self(rawValue: 0x1) - - /// LSI oscillator clock used as RTC clock - public static let LSI = Self(rawValue: 0x2) - - /// HSE oscillator clock divided by a prescaler used as RTC clock - public static let HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.CSR { - public struct LSIONValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSI oscillator Off - public static let Off = Self(rawValue: 0x0) - - /// LSI oscillator On - public static let On = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.SSCGR { - public struct SSCGENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Spread spectrum modulation disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Spread spectrum modulation enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.SSCGR { - public struct SPREADSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Center spread - public static let Center = Self(rawValue: 0x0) - - /// Down spread - public static let Down = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLI2SCFGR { - public struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLL*P=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLL*P=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLL*P=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLL*P=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.PLLSAICFGR { - public struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLL*P=2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLL*P=4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLL*P=6 - public static let Div6 = Self(rawValue: 0x2) - - /// PLL*P=8 - public static let Div8 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 5 - - /// PLLI2SDIVQ = /1 - public static let Div1 = Self(rawValue: 0x0) - - /// PLLI2SDIVQ = /2 - public static let Div2 = Self(rawValue: 0x1) - - /// PLLI2SDIVQ = /3 - public static let Div3 = Self(rawValue: 0x2) - - /// PLLI2SDIVQ = /4 - public static let Div4 = Self(rawValue: 0x3) - - /// PLLI2SDIVQ = /5 - public static let Div5 = Self(rawValue: 0x4) - - /// PLLI2SDIVQ = /6 - public static let Div6 = Self(rawValue: 0x5) - - /// PLLI2SDIVQ = /7 - public static let Div7 = Self(rawValue: 0x6) - - /// PLLI2SDIVQ = /8 - public static let Div8 = Self(rawValue: 0x7) - - /// PLLI2SDIVQ = /9 - public static let Div9 = Self(rawValue: 0x8) - - /// PLLI2SDIVQ = /10 - public static let Div10 = Self(rawValue: 0x9) - - /// PLLI2SDIVQ = /11 - public static let Div11 = Self(rawValue: 0xa) - - /// PLLI2SDIVQ = /12 - public static let Div12 = Self(rawValue: 0xb) - - /// PLLI2SDIVQ = /13 - public static let Div13 = Self(rawValue: 0xc) - - /// PLLI2SDIVQ = /14 - public static let Div14 = Self(rawValue: 0xd) - - /// PLLI2SDIVQ = /15 - public static let Div15 = Self(rawValue: 0xe) - - /// PLLI2SDIVQ = /16 - public static let Div16 = Self(rawValue: 0xf) - - /// PLLI2SDIVQ = /17 - public static let Div17 = Self(rawValue: 0x10) - - /// PLLI2SDIVQ = /18 - public static let Div18 = Self(rawValue: 0x11) - - /// PLLI2SDIVQ = /19 - public static let Div19 = Self(rawValue: 0x12) - - /// PLLI2SDIVQ = /20 - public static let Div20 = Self(rawValue: 0x13) - - /// PLLI2SDIVQ = /21 - public static let Div21 = Self(rawValue: 0x14) - - /// PLLI2SDIVQ = /22 - public static let Div22 = Self(rawValue: 0x15) - - /// PLLI2SDIVQ = /23 - public static let Div23 = Self(rawValue: 0x16) - - /// PLLI2SDIVQ = /24 - public static let Div24 = Self(rawValue: 0x17) - - /// PLLI2SDIVQ = /25 - public static let Div25 = Self(rawValue: 0x18) - - /// PLLI2SDIVQ = /26 - public static let Div26 = Self(rawValue: 0x19) - - /// PLLI2SDIVQ = /27 - public static let Div27 = Self(rawValue: 0x1a) - - /// PLLI2SDIVQ = /28 - public static let Div28 = Self(rawValue: 0x1b) - - /// PLLI2SDIVQ = /29 - public static let Div29 = Self(rawValue: 0x1c) - - /// PLLI2SDIVQ = /30 - public static let Div30 = Self(rawValue: 0x1d) - - /// PLLI2SDIVQ = /31 - public static let Div31 = Self(rawValue: 0x1e) - - /// PLLI2SDIVQ = /32 - public static let Div32 = Self(rawValue: 0x1f) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 5 - - /// PLLSAIDIVQ = /1 - public static let Div1 = Self(rawValue: 0x0) - - /// PLLSAIDIVQ = /2 - public static let Div2 = Self(rawValue: 0x1) - - /// PLLSAIDIVQ = /3 - public static let Div3 = Self(rawValue: 0x2) - - /// PLLSAIDIVQ = /4 - public static let Div4 = Self(rawValue: 0x3) - - /// PLLSAIDIVQ = /5 - public static let Div5 = Self(rawValue: 0x4) - - /// PLLSAIDIVQ = /6 - public static let Div6 = Self(rawValue: 0x5) - - /// PLLSAIDIVQ = /7 - public static let Div7 = Self(rawValue: 0x6) - - /// PLLSAIDIVQ = /8 - public static let Div8 = Self(rawValue: 0x7) - - /// PLLSAIDIVQ = /9 - public static let Div9 = Self(rawValue: 0x8) - - /// PLLSAIDIVQ = /10 - public static let Div10 = Self(rawValue: 0x9) - - /// PLLSAIDIVQ = /11 - public static let Div11 = Self(rawValue: 0xa) - - /// PLLSAIDIVQ = /12 - public static let Div12 = Self(rawValue: 0xb) - - /// PLLSAIDIVQ = /13 - public static let Div13 = Self(rawValue: 0xc) - - /// PLLSAIDIVQ = /14 - public static let Div14 = Self(rawValue: 0xd) - - /// PLLSAIDIVQ = /15 - public static let Div15 = Self(rawValue: 0xe) - - /// PLLSAIDIVQ = /16 - public static let Div16 = Self(rawValue: 0xf) - - /// PLLSAIDIVQ = /17 - public static let Div17 = Self(rawValue: 0x10) - - /// PLLSAIDIVQ = /18 - public static let Div18 = Self(rawValue: 0x11) - - /// PLLSAIDIVQ = /19 - public static let Div19 = Self(rawValue: 0x12) - - /// PLLSAIDIVQ = /20 - public static let Div20 = Self(rawValue: 0x13) - - /// PLLSAIDIVQ = /21 - public static let Div21 = Self(rawValue: 0x14) - - /// PLLSAIDIVQ = /22 - public static let Div22 = Self(rawValue: 0x15) - - /// PLLSAIDIVQ = /23 - public static let Div23 = Self(rawValue: 0x16) - - /// PLLSAIDIVQ = /24 - public static let Div24 = Self(rawValue: 0x17) - - /// PLLSAIDIVQ = /25 - public static let Div25 = Self(rawValue: 0x18) - - /// PLLSAIDIVQ = /26 - public static let Div26 = Self(rawValue: 0x19) - - /// PLLSAIDIVQ = /27 - public static let Div27 = Self(rawValue: 0x1a) - - /// PLLSAIDIVQ = /28 - public static let Div28 = Self(rawValue: 0x1b) - - /// PLLSAIDIVQ = /29 - public static let Div29 = Self(rawValue: 0x1c) - - /// PLLSAIDIVQ = /30 - public static let Div30 = Self(rawValue: 0x1d) - - /// PLLSAIDIVQ = /31 - public static let Div31 = Self(rawValue: 0x1e) - - /// PLLSAIDIVQ = /32 - public static let Div32 = Self(rawValue: 0x1f) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// PLLSAIDIVR = /2 - public static let Div2 = Self(rawValue: 0x0) - - /// PLLSAIDIVR = /4 - public static let Div4 = Self(rawValue: 0x1) - - /// PLLSAIDIVR = /8 - public static let Div8 = Self(rawValue: 0x2) - - /// PLLSAIDIVR = /16 - public static let Div16 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct SAI1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - public static let PLLSAI = Self(rawValue: 0x0) - - /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - public static let PLLI2S = Self(rawValue: 0x1) - - /// SAI1 clock frequency = Alternate function input frequency - public static let AFIF = Self(rawValue: 0x2) - - /// SAI1 clock frequency = HSI or HSE - public static let HSI_HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct SAI2SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - public static let PLLSAI = Self(rawValue: 0x0) - - /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - public static let PLLI2S = Self(rawValue: 0x1) - - /// SAI2 clock frequency = Alternate function input frequency - public static let AFIF = Self(rawValue: 0x2) - - /// SAI2 clock frequency = HSI or HSE - public static let HSI_HSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR1 { - public struct TIMPREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - public static let Mul1Or2 = Self(rawValue: 0x0) - - /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - public static let Mul1Or4 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct USART1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB2 clock (PCLK2) is selected as USART clock - public static let APB2 = Self(rawValue: 0x0) - - /// System clock is selected as USART clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock is selected as USART clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as USART clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct USART2SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB1 clock (PCLK1) is selected as USART clock - public static let APB1 = Self(rawValue: 0x0) - - /// System clock is selected as USART clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock is selected as USART clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as USART clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct I2C1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB clock selected as I2C clock - public static let APB = Self(rawValue: 0x0) - - /// System clock selected as I2C clock - public static let SYSCLK = Self(rawValue: 0x1) - - /// HSI clock selected as I2C clock - public static let HSI = Self(rawValue: 0x2) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// APB1 clock (PCLK1) selected as LPTILM1 clock - public static let APB1 = Self(rawValue: 0x0) - - /// LSI clock is selected as LPTILM1 clock - public static let LSI = Self(rawValue: 0x1) - - /// HSI clock is selected as LPTILM1 clock - public static let HSI = Self(rawValue: 0x2) - - /// LSE clock is selected as LPTILM1 clock - public static let LSE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct CECSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LSE clock is selected as HDMI-CEC clock - public static let LSE = Self(rawValue: 0x0) - - /// HSI divided by 488 clock is selected as HDMI-CEC clock - public static let HSI_Div488 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct CK48MSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 48MHz clock from PLL is selected - public static let PLL = Self(rawValue: 0x0) - - /// 48MHz clock from PLLSAI is selected - public static let PLLSAI = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension RCC.DCKCFGR2 { - public struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 48 MHz clock is selected as SD clock - public static let CK48M = Self(rawValue: 0x0) - - /// System clock is selected as SD clock - public static let SYSCLK = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-uart-echo/Sources/STM32F7X6/USART1.swift b/stm32-uart-echo/Sources/STM32F7X6/USART1.swift deleted file mode 100644 index 508d05a1..00000000 --- a/stm32-uart-echo/Sources/STM32F7X6/USART1.swift +++ /dev/null @@ -1,1554 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Universal synchronous asynchronous receiver transmitter -@RegisterBlock -public struct USART1 { - /// Control register 1 - @RegisterBlock(offset: 0x0) - public var cr1: Register - - /// Control register 2 - @RegisterBlock(offset: 0x4) - public var cr2: Register - - /// Control register 3 - @RegisterBlock(offset: 0x8) - public var cr3: Register - - /// Baud rate register - @RegisterBlock(offset: 0xc) - public var brr: Register - - /// Guard time and prescaler register - @RegisterBlock(offset: 0x10) - public var gtpr: Register - - /// Receiver timeout register - @RegisterBlock(offset: 0x14) - public var rtor: Register - - /// Request register - @RegisterBlock(offset: 0x18) - public var rqr: Register - - /// Interrupt & status register - @RegisterBlock(offset: 0x1c) - public var isr: Register - - /// Interrupt flag clear register - @RegisterBlock(offset: 0x20) - public var icr: Register - - /// Receive data register - @RegisterBlock(offset: 0x24) - public var rdr: Register - - /// Transmit data register - @RegisterBlock(offset: 0x28) - public var tdr: Register -} - -extension USART1 { - /// Control register 1 - @Register(bitWidth: 32) - public struct CR1 { - /// Word length - @ReadWrite(bits: 28..<29, as: M1Values.self) - public var m1: M1 - - /// End of Block interrupt enable - @ReadWrite(bits: 27..<28, as: EOBIEValues.self) - public var eobie: EOBIE - - /// Receiver timeout interrupt enable - @ReadWrite(bits: 26..<27, as: RTOIEValues.self) - public var rtoie: RTOIE - - /// Oversampling mode - @ReadWrite(bits: 15..<16, as: OVER8Values.self) - public var over8: OVER8 - - /// Character match interrupt enable - @ReadWrite(bits: 14..<15, as: CMIEValues.self) - public var cmie: CMIE - - /// Mute mode enable - @ReadWrite(bits: 13..<14, as: MMEValues.self) - public var mme: MME - - /// Word length - @ReadWrite(bits: 12..<13, as: M0Values.self) - public var m0: M0 - - /// Receiver wakeup method - @ReadWrite(bits: 11..<12, as: WAKEValues.self) - public var wake: WAKE - - /// Parity control enable - @ReadWrite(bits: 10..<11, as: PCEValues.self) - public var pce: PCE - - /// Parity selection - @ReadWrite(bits: 9..<10, as: PSValues.self) - public var ps: PS - - /// PE interrupt enable - @ReadWrite(bits: 8..<9, as: PEIEValues.self) - public var peie: PEIE - - /// interrupt enable - @ReadWrite(bits: 7..<8, as: TXEIEValues.self) - public var txeie: TXEIE - - /// Transmission complete interrupt enable - @ReadWrite(bits: 6..<7, as: TCIEValues.self) - public var tcie: TCIE - - /// RXNE interrupt enable - @ReadWrite(bits: 5..<6, as: RXNEIEValues.self) - public var rxneie: RXNEIE - - /// IDLE interrupt enable - @ReadWrite(bits: 4..<5, as: IDLEIEValues.self) - public var idleie: IDLEIE - - /// Transmitter enable - @ReadWrite(bits: 3..<4, as: TEValues.self) - public var te: TE - - /// Receiver enable - @ReadWrite(bits: 2..<3, as: REValues.self) - public var re: RE - - /// USART enable in Stop mode - @ReadWrite(bits: 1..<2, as: UESMValues.self) - public var uesm: UESM - - /// USART enable - @ReadWrite(bits: 0..<1, as: UEValues.self) - public var ue: UE - - /// Driver Enable assertion time - @ReadWrite(bits: 21..<26) - public var deat: DEAT - - /// Driver Enable de-assertion time - @ReadWrite(bits: 16..<21) - public var dedt: DEDT - } - - /// Control register 2 - @Register(bitWidth: 32) - public struct CR2 { - /// Receiver timeout enable - @ReadWrite(bits: 23..<24, as: RTOENValues.self) - public var rtoen: RTOEN - - /// Auto baud rate enable - @ReadWrite(bits: 20..<21, as: ABRENValues.self) - public var abren: ABREN - - /// Most significant bit first - @ReadWrite(bits: 19..<20, as: MSBFIRSTValues.self) - public var msbfirst: MSBFIRST - - /// Binary data inversion - @ReadWrite(bits: 18..<19, as: DATAINVValues.self) - public var datainv: DATAINV - - /// TX pin active level inversion - @ReadWrite(bits: 17..<18, as: TXINVValues.self) - public var txinv: TXINV - - /// RX pin active level inversion - @ReadWrite(bits: 16..<17, as: RXINVValues.self) - public var rxinv: RXINV - - /// Swap TX/RX pins - @ReadWrite(bits: 15..<16, as: SWAPValues.self) - public var swap: SWAP - - /// LIN mode enable - @ReadWrite(bits: 14..<15, as: LINENValues.self) - public var linen: LINEN - - /// STOP bits - @ReadWrite(bits: 12..<14, as: STOPValues.self) - public var stop: STOP - - /// Clock enable - @ReadWrite(bits: 11..<12, as: CLKENValues.self) - public var clken: CLKEN - - /// Clock polarity - @ReadWrite(bits: 10..<11, as: CPOLValues.self) - public var cpol: CPOL - - /// Clock phase - @ReadWrite(bits: 9..<10, as: CPHAValues.self) - public var cpha: CPHA - - /// Last bit clock pulse - @ReadWrite(bits: 8..<9, as: LBCLValues.self) - public var lbcl: LBCL - - /// LIN break detection interrupt enable - @ReadWrite(bits: 6..<7, as: LBDIEValues.self) - public var lbdie: LBDIE - - /// LIN break detection length - @ReadWrite(bits: 5..<6, as: LBDLValues.self) - public var lbdl: LBDL - - /// 7-bit Address Detection/4-bit Address Detection - @ReadWrite(bits: 4..<5, as: ADDM7Values.self) - public var addm7: ADDM7 - - /// Auto baud rate mode - @ReadWrite(bits: 21..<23, as: ABRMODValues.self) - public var abrmod: ABRMOD - - /// Address of the USART node - @ReadWrite(bits: 24..<32) - public var add: ADD - } - - /// Control register 3 - @Register(bitWidth: 32) - public struct CR3 { - /// Wakeup from Stop mode interrupt enable - @ReadWrite(bits: 22..<23, as: WUFIEValues.self) - public var wufie: WUFIE - - /// Wakeup from Stop mode interrupt flag selection - @ReadWrite(bits: 20..<22, as: WUSValues.self) - public var wus: WUS - - /// Smartcard auto-retry count - @ReadWrite(bits: 17..<20) - public var scarcnt: SCARCNT - - /// Driver enable polarity selection - @ReadWrite(bits: 15..<16, as: DEPValues.self) - public var dep: DEP - - /// Driver enable mode - @ReadWrite(bits: 14..<15, as: DEMValues.self) - public var dem: DEM - - /// DMA Disable on Reception Error - @ReadWrite(bits: 13..<14, as: DDREValues.self) - public var ddre: DDRE - - /// Overrun Disable - @ReadWrite(bits: 12..<13, as: OVRDISValues.self) - public var ovrdis: OVRDIS - - /// One sample bit method enable - @ReadWrite(bits: 11..<12, as: ONEBITValues.self) - public var onebit: ONEBIT - - /// CTS interrupt enable - @ReadWrite(bits: 10..<11, as: CTSIEValues.self) - public var ctsie: CTSIE - - /// CTS enable - @ReadWrite(bits: 9..<10, as: CTSEValues.self) - public var ctse: CTSE - - /// RTS enable - @ReadWrite(bits: 8..<9, as: RTSEValues.self) - public var rtse: RTSE - - /// DMA enable transmitter - @ReadWrite(bits: 7..<8, as: DMATValues.self) - public var dmat: DMAT - - /// DMA enable receiver - @ReadWrite(bits: 6..<7, as: DMARValues.self) - public var dmar: DMAR - - /// Smartcard mode enable - @ReadWrite(bits: 5..<6, as: SCENValues.self) - public var scen: SCEN - - /// Smartcard NACK enable - @ReadWrite(bits: 4..<5, as: NACKValues.self) - public var nack: NACK - - /// Half-duplex selection - @ReadWrite(bits: 3..<4, as: HDSELValues.self) - public var hdsel: HDSEL - - /// Ir low-power - @ReadWrite(bits: 2..<3, as: IRLPValues.self) - public var irlp: IRLP - - /// Ir mode enable - @ReadWrite(bits: 1..<2, as: IRENValues.self) - public var iren: IREN - - /// Error interrupt enable - @ReadWrite(bits: 0..<1, as: EIEValues.self) - public var eie: EIE - } - - /// Baud rate register - @Register(bitWidth: 32) - public struct BRR { - /// DIV_Mantissa - @ReadWrite(bits: 0..<16) - public var brr_field: BRR_FIELD - } - - /// Guard time and prescaler register - @Register(bitWidth: 32) - public struct GTPR { - /// Guard time value - @ReadWrite(bits: 8..<16) - public var gt: GT - - /// Prescaler value - @ReadWrite(bits: 0..<8) - public var psc: PSC - } - - /// Receiver timeout register - @Register(bitWidth: 32) - public struct RTOR { - /// Block Length - @ReadWrite(bits: 24..<32) - public var blen: BLEN - - /// Receiver timeout value - @ReadWrite(bits: 0..<24) - public var rto: RTO - } - - /// Request register - @Register(bitWidth: 32) - public struct RQR { - /// Transmit data flush request - @WriteOnly(bits: 4..<5) - public var txfrq: TXFRQ - - /// Receive data flush request - @WriteOnly(bits: 3..<4) - public var rxfrq: RXFRQ - - /// Mute mode request - @WriteOnly(bits: 2..<3) - public var mmrq: MMRQ - - /// Send break request - @WriteOnly(bits: 1..<2) - public var sbkrq: SBKRQ - - /// Auto baud rate request - @WriteOnly(bits: 0..<1) - public var abrrq: ABRRQ - } - - /// Interrupt & status register - @Register(bitWidth: 32) - public struct ISR { - /// REACK - @ReadOnly(bits: 22..<23) - public var reack: REACK - - /// TEACK - @ReadOnly(bits: 21..<22) - public var teack: TEACK - - /// WUF - @ReadOnly(bits: 20..<21) - public var wuf: WUF - - /// RWU - @ReadOnly(bits: 19..<20) - public var rwu: RWU - - /// SBKF - @ReadOnly(bits: 18..<19) - public var sbkf: SBKF - - /// CMF - @ReadOnly(bits: 17..<18) - public var cmf: CMF - - /// BUSY - @ReadOnly(bits: 16..<17) - public var busy: BUSY - - /// ABRF - @ReadOnly(bits: 15..<16) - public var abrf: ABRF - - /// ABRE - @ReadOnly(bits: 14..<15) - public var abre: ABRE - - /// EOBF - @ReadOnly(bits: 12..<13) - public var eobf: EOBF - - /// RTOF - @ReadOnly(bits: 11..<12) - public var rtof: RTOF - - /// CTS - @ReadOnly(bits: 10..<11) - public var cts: CTS - - /// CTSIF - @ReadOnly(bits: 9..<10) - public var ctsif: CTSIF - - /// LBDF - @ReadOnly(bits: 8..<9) - public var lbdf: LBDF - - /// TXE - @ReadOnly(bits: 7..<8) - public var txe: TXE - - /// TC - @ReadOnly(bits: 6..<7) - public var tc: TC - - /// RXNE - @ReadOnly(bits: 5..<6) - public var rxne: RXNE - - /// IDLE - @ReadOnly(bits: 4..<5) - public var idle: IDLE - - /// ORE - @ReadOnly(bits: 3..<4) - public var ore: ORE - - /// NF - @ReadOnly(bits: 2..<3) - public var nf: NF - - /// FE - @ReadOnly(bits: 1..<2) - public var fe: FE - - /// PE - @ReadOnly(bits: 0..<1) - public var pe: PE - } - - /// Interrupt flag clear register - @Register(bitWidth: 32) - public struct ICR { - /// Wakeup from Stop mode clear flag - @WriteOnly(bits: 20..<21) - public var wucf: WUCF - - /// Character match clear flag - @WriteOnly(bits: 17..<18) - public var cmcf: CMCF - - /// End of block clear flag - @WriteOnly(bits: 12..<13) - public var eobcf: EOBCF - - /// Receiver timeout clear flag - @WriteOnly(bits: 11..<12) - public var rtocf: RTOCF - - /// CTS clear flag - @WriteOnly(bits: 9..<10) - public var ctscf: CTSCF - - /// LIN break detection clear flag - @WriteOnly(bits: 8..<9) - public var lbdcf: LBDCF - - /// Transmission complete clear flag - @WriteOnly(bits: 6..<7) - public var tccf: TCCF - - /// Idle line detected clear flag - @WriteOnly(bits: 4..<5) - public var idlecf: IDLECF - - /// Overrun error clear flag - @WriteOnly(bits: 3..<4) - public var orecf: ORECF - - /// Noise detected clear flag - @WriteOnly(bits: 2..<3) - public var ncf: NCF - - /// Framing error clear flag - @WriteOnly(bits: 1..<2) - public var fecf: FECF - - /// Parity error clear flag - @WriteOnly(bits: 0..<1) - public var pecf: PECF - } - - /// Receive data register - @Register(bitWidth: 32) - public struct RDR { - /// Receive data value - @ReadOnly(bits: 0..<9) - public var rdr_field: RDR_FIELD - } - - /// Transmit data register - @Register(bitWidth: 32) - public struct TDR { - /// Transmit data value - @ReadWrite(bits: 0..<9) - public var tdr_field: TDR_FIELD - } -} - -extension USART1.CR1 { - public struct M1Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Use M0 to set the data bits - public static let M0 = Self(rawValue: 0x0) - - /// 1 start bit, 7 data bits, n stop bits - public static let Bit7 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct EOBIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// A USART interrupt is generated when the EOBF flag is set in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct RTOIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An USART interrupt is generated when the RTOF bit is set in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct OVER8Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Oversampling by 16 - public static let Oversampling16 = Self(rawValue: 0x0) - - /// Oversampling by 8 - public static let Oversampling8 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct CMIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated when the CMF bit is set in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct MMEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Receiver in active mode permanently - public static let Disabled = Self(rawValue: 0x0) - - /// Receiver can switch between mute mode and active mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct M0Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 1 start bit, 8 data bits, n stop bits - public static let Bit8 = Self(rawValue: 0x0) - - /// 1 start bit, 9 data bits, n stop bits - public static let Bit9 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct WAKEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Idle line - public static let Idle = Self(rawValue: 0x0) - - /// Address mask - public static let Address = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct PCEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Parity control disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Parity control enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct PSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Even parity - public static let Even = Self(rawValue: 0x0) - - /// Odd parity - public static let Odd = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct PEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever PE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct TXEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever TXE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct TCIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever TC=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct RXNEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct IDLEIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Interrupt is generated whenever IDLE=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct TEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Transmitter is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Transmitter is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct REValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Receiver is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Receiver is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct UESMValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// USART not able to wake up the MCU from Stop mode - public static let Disabled = Self(rawValue: 0x0) - - /// USART able to wake up the MCU from Stop mode - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR1 { - public struct UEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// UART is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// UART is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct RTOENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Receiver timeout feature disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Receiver timeout feature enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct ABRENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Auto baud rate detection is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Auto baud rate detection is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct MSBFIRSTValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// data is transmitted/received with data bit 0 first, following the start bit - public static let LSB = Self(rawValue: 0x0) - - /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit - public static let MSB = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct DATAINVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Logical data from the data register are send/received in positive/direct logic - public static let Positive = Self(rawValue: 0x0) - - /// Logical data from the data register are send/received in negative/inverse logic - public static let Negative = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct TXINVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// TX pin signal works using the standard logic levels - public static let Standard = Self(rawValue: 0x0) - - /// TX pin signal values are inverted - public static let Inverted = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct RXINVValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RX pin signal works using the standard logic levels - public static let Standard = Self(rawValue: 0x0) - - /// RX pin signal values are inverted - public static let Inverted = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct SWAPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// TX/RX pins are used as defined in standard pinout - public static let Standard = Self(rawValue: 0x0) - - /// The TX and RX pins functions are swapped - public static let Swapped = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LINENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// LIN mode disabled - public static let Disabled = Self(rawValue: 0x0) - - /// LIN mode enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct STOPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// 1 stop bit - public static let Stop1 = Self(rawValue: 0x0) - - /// 0.5 stop bit - public static let Stop0p5 = Self(rawValue: 0x1) - - /// 2 stop bit - public static let Stop2 = Self(rawValue: 0x2) - - /// 1.5 stop bit - public static let Stop1p5 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct CLKENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// CK pin disabled - public static let Disabled = Self(rawValue: 0x0) - - /// CK pin enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct CPOLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Steady low value on CK pin outside transmission window - public static let Low = Self(rawValue: 0x0) - - /// Steady high value on CK pin outside transmission window - public static let High = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct CPHAValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The first clock transition is the first data capture edge - public static let First = Self(rawValue: 0x0) - - /// The second clock transition is the first data capture edge - public static let Second = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LBCLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// The clock pulse of the last data bit is not output to the CK pin - public static let NotOutput = Self(rawValue: 0x0) - - /// The clock pulse of the last data bit is output to the CK pin - public static let Output = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LBDIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An interrupt is generated whenever LBDF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct LBDLValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 10-bit break detection - public static let Bit10 = Self(rawValue: 0x0) - - /// 11-bit break detection - public static let Bit11 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct ADDM7Values: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// 4-bit address detection - public static let Bit4 = Self(rawValue: 0x0) - - /// 7-bit address detection - public static let Bit7 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR2 { - public struct ABRMODValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// Measurement of the start bit is used to detect the baud rate - public static let Start = Self(rawValue: 0x0) - - /// Falling edge to falling edge measurement - public static let Edge = Self(rawValue: 0x1) - - /// 0x7F frame detection - public static let Frame7F = Self(rawValue: 0x2) - - /// 0x55 frame detection - public static let Frame55 = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct WUFIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An USART interrupt is generated whenever WUF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct WUSValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 2 - - /// WUF active on address match - public static let Address = Self(rawValue: 0x0) - - /// WuF active on Start bit detection - public static let Start = Self(rawValue: 0x2) - - /// WUF active on RXNE - public static let RXNE = Self(rawValue: 0x3) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DEPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DE signal is active high - public static let High = Self(rawValue: 0x0) - - /// DE signal is active low - public static let Low = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DEMValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DE function is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// The DE signal is output on the RTS pin - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DDREValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA is not disabled in case of reception error - public static let NotDisabled = Self(rawValue: 0x0) - - /// DMA is disabled following a reception error - public static let Disabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct OVRDISValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Overrun Error Flag, ORE, is set when received data is not read before receiving new data - public static let Enabled = Self(rawValue: 0x0) - - /// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register - public static let Disabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct ONEBITValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Three sample bit method - public static let Sample3 = Self(rawValue: 0x0) - - /// One sample bit method - public static let Sample1 = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct CTSIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An interrupt is generated whenever CTSIF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct CTSEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// CTS hardware flow control disabled - public static let Disabled = Self(rawValue: 0x0) - - /// CTS mode enabled, data is only transmitted when the CTS input is asserted - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct RTSEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// RTS hardware flow control disabled - public static let Disabled = Self(rawValue: 0x0) - - /// RTS output enabled, data is only requested when there is space in the receive buffer - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DMATValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA mode is disabled for transmission - public static let Disabled = Self(rawValue: 0x0) - - /// DMA mode is enabled for transmission - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct DMARValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// DMA mode is disabled for reception - public static let Disabled = Self(rawValue: 0x0) - - /// DMA mode is enabled for reception - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct SCENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Smartcard Mode disabled - public static let Disabled = Self(rawValue: 0x0) - - /// Smartcard Mode enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct NACKValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// NACK transmission in case of parity error is disabled - public static let Disabled = Self(rawValue: 0x0) - - /// NACK transmission during parity error is enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct HDSELValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Half duplex mode is not selected - public static let NotSelected = Self(rawValue: 0x0) - - /// Half duplex mode is selected - public static let Selected = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct IRLPValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Normal mode - public static let Normal = Self(rawValue: 0x0) - - /// Low-power mode - public static let LowPower = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct IRENValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// IrDA disabled - public static let Disabled = Self(rawValue: 0x0) - - /// IrDA enabled - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension USART1.CR3 { - public struct EIEValues: BitFieldProjectable, RawRepresentable { - public static let bitWidth = 1 - - /// Interrupt is inhibited - public static let Disabled = Self(rawValue: 0x0) - - /// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register - public static let Enabled = Self(rawValue: 0x1) - - public var rawValue: UInt8 - - @inlinable @inline(__always) - public init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-uart-echo/Sources/STM32F7X6/stm32f7x6.patched.svd b/stm32-uart-echo/Sources/STM32F7X6/stm32f7x6.patched.svd deleted file mode 120000 index a6442b50..00000000 --- a/stm32-uart-echo/Sources/STM32F7X6/stm32f7x6.patched.svd +++ /dev/null @@ -1 +0,0 @@ -../../../Tools/SVDs/stm32f7x6.patched.svd \ No newline at end of file diff --git a/stm32-uart-echo/Sources/STM32F7X6/svd2swift.json b/stm32-uart-echo/Sources/STM32F7X6/svd2swift.json deleted file mode 100644 index a7fe0570..00000000 --- a/stm32-uart-echo/Sources/STM32F7X6/svd2swift.json +++ /dev/null @@ -1,9 +0,0 @@ -{ - "peripherals": [ - "GPIOA", - "GPIOB", - "RCC", - "USART1" - ], - "access-level": "public" -} diff --git a/stm32-uart-echo/Sources/Support/Support.c b/stm32-uart-echo/Sources/Support/Support.c deleted file mode 100644 index fc3c1a13..00000000 --- a/stm32-uart-echo/Sources/Support/Support.c +++ /dev/null @@ -1,51 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#if defined(__arm__) - -#include -#include - -void *memset(void *b, int c, size_t len) { - for (int i = 0; i < len; i++) { - ((char *)b)[i] = c; - } - return b; -} - -void *memcpy(void *restrict dst, const void *restrict src, size_t n) { - for (int i = 0; i < n; i++) { - ((char *)dst)[i] = ((char *)src)[i]; - } - return dst; -} - -extern void reset(void); - -void interrupt(void) { - while (1) {} -} - -__attribute((used)) __attribute((section("__VECTORS,__text"))) -void *vector_table[114] = { - (void *)0x2000fffc, // initial SP - (void *)((uintptr_t)reset - (0x20010000 - 0x08000000)), // Reset - - (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // NMI - (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // HardFault - (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // MemManage - (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // BusFault - (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // UsageFault - - 0 // NULL for all the other handlers -}; - -#endif diff --git a/stm32-uart-echo/Sources/Support/include/Support.h b/stm32-uart-echo/Sources/Support/include/Support.h deleted file mode 100644 index 158cce06..00000000 --- a/stm32-uart-echo/Sources/Support/include/Support.h +++ /dev/null @@ -1,12 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2024 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#pragma once diff --git a/stm32-uart-echo/Sources/Support/startup.S b/stm32-uart-echo/Sources/Support/startup.S deleted file mode 100644 index 6e8c7c27..00000000 --- a/stm32-uart-echo/Sources/Support/startup.S +++ /dev/null @@ -1,45 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - - .extern _memcpy - .extern _main - - .text - .thumb - .section __TEXT,__text,regular,pure_instructions - .syntax unified - -// reset handler, main entry point - .balign 4 - .global _reset - .thumb_func -_reset: - ldr r0, =0x20010000 // dst - ldr r1, =0x08000000 // src - ldr r2, =segment$start$__VECTORS - ldr r3, =segment$end$__DATA - subs r2, r3, r2 // size = segment$end$__DATA - segment$start$__TEXT - - // memcpy (r0: dst = 0x20010000, r1: src = 0x08000000, r2: size = ...) - // Relocate ourselves: copy the entire image (VECTORS, TEXT, DATA segments) - // from flash memory (non-writable) to RAM (writable), so that globals can be - // written to. - bl _memcpy - - // Cannot jump to main normally, because that would call main using a relative - // offset, which would result in a call to the pre-relocation address. - // Loading address of main into a register will give us the post-relocation - // address. - ldr r0, =_main - blx r0 - - // Loop forever if main returns. - b .