diff --git a/tang20k/scr1/ip/ahb_lite_uart16550/LICENSE b/tang20k/scr1/ip/ahb_lite_uart16550/LICENSE new file mode 100644 index 0000000..19e3071 --- /dev/null +++ b/tang20k/scr1/ip/ahb_lite_uart16550/LICENSE @@ -0,0 +1,504 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 2.1, February 1999 + + Copyright (C) 1991, 1999 Free Software Foundation, Inc. + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + +(This is the first released version of the Lesser GPL. It also counts + as the successor of the GNU Library Public License, version 2, hence + the version number 2.1.) + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +Licenses are intended to guarantee your freedom to share and change +free software--to make sure the software is free for all its users. + + This license, the Lesser General Public License, applies to some +specially designated software packages--typically libraries--of the +Free Software Foundation and other authors who decide to use it. You +can use it too, but we suggest you first think carefully about whether +this license or the ordinary General Public License is the better +strategy to use in any particular case, based on the explanations below. + + When we speak of free software, we are referring to freedom of use, +not price. Our General Public Licenses are designed to make sure that +you have the freedom to distribute copies of free software (and charge +for this service if you wish); that you receive source code or can get +it if you want it; that you can change the software and use pieces of +it in new free programs; and that you are informed that you can do +these things. + + To protect your rights, we need to make restrictions that forbid +distributors to deny you these rights or to ask you to surrender these +rights. These restrictions translate to certain responsibilities for +you if you distribute copies of the library or if you modify it. + + For example, if you distribute copies of the library, whether gratis +or for a fee, you must give the recipients all the rights that we gave +you. You must make sure that they, too, receive or can get the source +code. If you link other code with the library, you must provide +complete object files to the recipients, so that they can relink them +with the library after making changes to the library and recompiling +it. And you must show them these terms so they know their rights. + + We protect your rights with a two-step method: (1) we copyright the +library, and (2) we offer you this license, which gives you legal +permission to copy, distribute and/or modify the library. + + To protect each distributor, we want to make it very clear that +there is no warranty for the free library. Also, if the library is +modified by someone else and passed on, the recipients should know +that what they have is not the original version, so that the original +author's reputation will not be affected by problems that might be +introduced by others. + + Finally, software patents pose a constant threat to the existence of +any free program. We wish to make sure that a company cannot +effectively restrict the users of a free program by obtaining a +restrictive license from a patent holder. Therefore, we insist that +any patent license obtained for a version of the library must be +consistent with the full freedom of use specified in this license. + + Most GNU software, including some libraries, is covered by the +ordinary GNU General Public License. This license, the GNU Lesser +General Public License, applies to certain designated libraries, and +is quite different from the ordinary General Public License. We use +this license for certain libraries in order to permit linking those +libraries into non-free programs. + + When a program is linked with a library, whether statically or using +a shared library, the combination of the two is legally speaking a +combined work, a derivative of the original library. The ordinary +General Public License therefore permits such linking only if the +entire combination fits its criteria of freedom. The Lesser General +Public License permits more lax criteria for linking other code with +the library. + + We call this license the "Lesser" General Public License because it +does Less to protect the user's freedom than the ordinary General +Public License. It also provides other free software developers Less +of an advantage over competing non-free programs. These disadvantages +are the reason we use the ordinary General Public License for many +libraries. However, the Lesser license provides advantages in certain +special circumstances. + + For example, on rare occasions, there may be a special need to +encourage the widest possible use of a certain library, so that it becomes +a de-facto standard. To achieve this, non-free programs must be +allowed to use the library. A more frequent case is that a free +library does the same job as widely used non-free libraries. In this +case, there is little to gain by limiting the free library to free +software only, so we use the Lesser General Public License. + + In other cases, permission to use a particular library in non-free +programs enables a greater number of people to use a large body of +free software. For example, permission to use the GNU C Library in +non-free programs enables many more people to use the whole GNU +operating system, as well as its variant, the GNU/Linux operating +system. + + Although the Lesser General Public License is Less protective of the +users' freedom, it does ensure that the user of a program that is +linked with the Library has the freedom and the wherewithal to run +that program using a modified version of the Library. + + The precise terms and conditions for copying, distribution and +modification follow. Pay close attention to the difference between a +"work based on the library" and a "work that uses the library". The +former contains code derived from the library, whereas the latter must +be combined with the library in order to run. + + GNU LESSER GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License Agreement applies to any software library or other +program which contains a notice placed by the copyright holder or +other authorized party saying it may be distributed under the terms of +this Lesser General Public License (also called "this License"). +Each licensee is addressed as "you". + + A "library" means a collection of software functions and/or data +prepared so as to be conveniently linked with application programs +(which use some of those functions and data) to form executables. + + The "Library", below, refers to any such software library or work +which has been distributed under these terms. A "work based on the +Library" means either the Library or any derivative work under +copyright law: that is to say, a work containing the Library or a +portion of it, either verbatim or with modifications and/or translated +straightforwardly into another language. (Hereinafter, translation is +included without limitation in the term "modification".) + + "Source code" for a work means the preferred form of the work for +making modifications to it. For a library, complete source code means +all the source code for all modules it contains, plus any associated +interface definition files, plus the scripts used to control compilation +and installation of the library. + + Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running a program using the Library is not restricted, and output from +such a program is covered only if its contents constitute a work based +on the Library (independent of the use of the Library in a tool for +writing it). Whether that is true depends on what the Library does +and what the program that uses the Library does. + + 1. You may copy and distribute verbatim copies of the Library's +complete source code as you receive it, in any medium, provided that +you conspicuously and appropriately publish on each copy an +appropriate copyright notice and disclaimer of warranty; keep intact +all the notices that refer to this License and to the absence of any +warranty; and distribute a copy of this License along with the +Library. + + You may charge a fee for the physical act of transferring a copy, +and you may at your option offer warranty protection in exchange for a +fee. + + 2. You may modify your copy or copies of the Library or any portion +of it, thus forming a work based on the Library, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) The modified work must itself be a software library. + + b) You must cause the files modified to carry prominent notices + stating that you changed the files and the date of any change. + + c) You must cause the whole of the work to be licensed at no + charge to all third parties under the terms of this License. + + d) If a facility in the modified Library refers to a function or a + table of data to be supplied by an application program that uses + the facility, other than as an argument passed when the facility + is invoked, then you must make a good faith effort to ensure that, + in the event an application does not supply such function or + table, the facility still operates, and performs whatever part of + its purpose remains meaningful. + + (For example, a function in a library to compute square roots has + a purpose that is entirely well-defined independent of the + application. Therefore, Subsection 2d requires that any + application-supplied function or table used by this function must + be optional: if the application does not supply it, the square + root function must still compute square roots.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Library, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Library, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote +it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Library. + +In addition, mere aggregation of another work not based on the Library +with the Library (or with a work based on the Library) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may opt to apply the terms of the ordinary GNU General Public +License instead of this License to a given copy of the Library. To do +this, you must alter all the notices that refer to this License, so +that they refer to the ordinary GNU General Public License, version 2, +instead of to this License. (If a newer version than version 2 of the +ordinary GNU General Public License has appeared, then you can specify +that version instead if you wish.) Do not make any other change in +these notices. + + Once this change is made in a given copy, it is irreversible for +that copy, so the ordinary GNU General Public License applies to all +subsequent copies and derivative works made from that copy. + + This option is useful when you wish to copy part of the code of +the Library into a program that is not a library. + + 4. You may copy and distribute the Library (or a portion or +derivative of it, under Section 2) in object code or executable form +under the terms of Sections 1 and 2 above provided that you accompany +it with the complete corresponding machine-readable source code, which +must be distributed under the terms of Sections 1 and 2 above on a +medium customarily used for software interchange. + + If distribution of object code is made by offering access to copy +from a designated place, then offering equivalent access to copy the +source code from the same place satisfies the requirement to +distribute the source code, even though third parties are not +compelled to copy the source along with the object code. + + 5. A program that contains no derivative of any portion of the +Library, but is designed to work with the Library by being compiled or +linked with it, is called a "work that uses the Library". Such a +work, in isolation, is not a derivative work of the Library, and +therefore falls outside the scope of this License. + + However, linking a "work that uses the Library" with the Library +creates an executable that is a derivative of the Library (because it +contains portions of the Library), rather than a "work that uses the +library". The executable is therefore covered by this License. +Section 6 states terms for distribution of such executables. + + When a "work that uses the Library" uses material from a header file +that is part of the Library, the object code for the work may be a +derivative work of the Library even though the source code is not. +Whether this is true is especially significant if the work can be +linked without the Library, or if the work is itself a library. The +threshold for this to be true is not precisely defined by law. + + If such an object file uses only numerical parameters, data +structure layouts and accessors, and small macros and small inline +functions (ten lines or less in length), then the use of the object +file is unrestricted, regardless of whether it is legally a derivative +work. (Executables containing this object code plus portions of the +Library will still fall under Section 6.) + + Otherwise, if the work is a derivative of the Library, you may +distribute the object code for the work under the terms of Section 6. +Any executables containing that work also fall under Section 6, +whether or not they are linked directly with the Library itself. + + 6. As an exception to the Sections above, you may also combine or +link a "work that uses the Library" with the Library to produce a +work containing portions of the Library, and distribute that work +under terms of your choice, provided that the terms permit +modification of the work for the customer's own use and reverse +engineering for debugging such modifications. + + You must give prominent notice with each copy of the work that the +Library is used in it and that the Library and its use are covered by +this License. You must supply a copy of this License. If the work +during execution displays copyright notices, you must include the +copyright notice for the Library among them, as well as a reference +directing the user to the copy of this License. Also, you must do one +of these things: + + a) Accompany the work with the complete corresponding + machine-readable source code for the Library including whatever + changes were used in the work (which must be distributed under + Sections 1 and 2 above); and, if the work is an executable linked + with the Library, with the complete machine-readable "work that + uses the Library", as object code and/or source code, so that the + user can modify the Library and then relink to produce a modified + executable containing the modified Library. (It is understood + that the user who changes the contents of definitions files in the + Library will not necessarily be able to recompile the application + to use the modified definitions.) + + b) Use a suitable shared library mechanism for linking with the + Library. A suitable mechanism is one that (1) uses at run time a + copy of the library already present on the user's computer system, + rather than copying library functions into the executable, and (2) + will operate properly with a modified version of the library, if + the user installs one, as long as the modified version is + interface-compatible with the version that the work was made with. + + c) Accompany the work with a written offer, valid for at + least three years, to give the same user the materials + specified in Subsection 6a, above, for a charge no more + than the cost of performing this distribution. + + d) If distribution of the work is made by offering access to copy + from a designated place, offer equivalent access to copy the above + specified materials from the same place. + + e) Verify that the user has already received a copy of these + materials or that you have already sent this user a copy. + + For an executable, the required form of the "work that uses the +Library" must include any data and utility programs needed for +reproducing the executable from it. However, as a special exception, +the materials to be distributed need not include anything that is +normally distributed (in either source or binary form) with the major +components (compiler, kernel, and so on) of the operating system on +which the executable runs, unless that component itself accompanies +the executable. + + It may happen that this requirement contradicts the license +restrictions of other proprietary libraries that do not normally +accompany the operating system. Such a contradiction means you cannot +use both them and the Library together in an executable that you +distribute. + + 7. You may place library facilities that are a work based on the +Library side-by-side in a single library together with other library +facilities not covered by this License, and distribute such a combined +library, provided that the separate distribution of the work based on +the Library and of the other library facilities is otherwise +permitted, and provided that you do these two things: + + a) Accompany the combined library with a copy of the same work + based on the Library, uncombined with any other library + facilities. This must be distributed under the terms of the + Sections above. + + b) Give prominent notice with the combined library of the fact + that part of it is a work based on the Library, and explaining + where to find the accompanying uncombined form of the same work. + + 8. You may not copy, modify, sublicense, link with, or distribute +the Library except as expressly provided under this License. Any +attempt otherwise to copy, modify, sublicense, link with, or +distribute the Library is void, and will automatically terminate your +rights under this License. However, parties who have received copies, +or rights, from you under this License will not have their licenses +terminated so long as such parties remain in full compliance. + + 9. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Library or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Library (or any work based on the +Library), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Library or works based on it. + + 10. Each time you redistribute the Library (or any work based on the +Library), the recipient automatically receives a license from the +original licensor to copy, distribute, link with or modify the Library +subject to these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties with +this License. + + 11. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Library at all. For example, if a patent +license would not permit royalty-free redistribution of the Library by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Library. + +If any portion of this section is held invalid or unenforceable under any +particular circumstance, the balance of the section is intended to apply, +and the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 12. If the distribution and/or use of the Library is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Library under this License may add +an explicit geographical distribution limitation excluding those countries, +so that distribution is permitted only in or among countries not thus +excluded. In such case, this License incorporates the limitation as if +written in the body of this License. + + 13. The Free Software Foundation may publish revised and/or new +versions of the Lesser General Public License from time to time. +Such new versions will be similar in spirit to the present version, +but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Library +specifies a version number of this License which applies to it and +"any later version", you have the option of following the terms and +conditions either of that version or of any later version published by +the Free Software Foundation. If the Library does not specify a +license version number, you may choose any version ever published by +the Free Software Foundation. + + 14. If you wish to incorporate parts of the Library into other free +programs whose distribution conditions are incompatible with these, +write to the author to ask for permission. For software which is +copyrighted by the Free Software Foundation, write to the Free +Software Foundation; we sometimes make exceptions for this. Our +decision will be guided by the two goals of preserving the free status +of all derivatives of our free software and of promoting the sharing +and reuse of software generally. + + NO WARRANTY + + 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO +WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW. +EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR +OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY +KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE +LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME +THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + + 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN +WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY +AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU +FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR +CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE +LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING +RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A +FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF +SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Libraries + + If you develop a new library, and you want it to be of the greatest +possible use to the public, we recommend making it free software that +everyone can redistribute and change. You can do so by permitting +redistribution under these terms (or, alternatively, under the terms of the +ordinary General Public License). + + To apply these terms, attach the following notices to the library. It is +safest to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least the +"copyright" line and a pointer to where the full notice is found. + + {description} + Copyright (C) {year} {fullname} + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 + USA + +Also add information on how to contact you by electronic and paper mail. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the library, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random + Hacker. + + {signature of Ty Coon}, 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! diff --git a/tang20k/scr1/ip/ahb_lite_uart16550/src/ahb_lite_uart16550.v b/tang20k/scr1/ip/ahb_lite_uart16550/src/ahb_lite_uart16550.v new file mode 100644 index 0000000..576ef13 --- /dev/null +++ b/tang20k/scr1/ip/ahb_lite_uart16550/src/ahb_lite_uart16550.v @@ -0,0 +1,123 @@ +/* UART16550 controller for MIPSfpga+ system AHB-Lite bus + * Copyright(c) 2017 Stanislav Zhelnio + * https://github.com/zhelnio/ahb_lite_uart16550 + * + * based on https://github.com/freecores/uart16550 + * https://github.com/olofk/uart16550 + * + * these projects source code is placed in src/uart16550 + */ + +`include "uart_defines.v" + +module ahb_lite_uart16550( + //ABB-Lite side + input HCLK, + input HRESETn, + input [ 31 : 0 ] HADDR, + input [ 2 : 0 ] HBURST, + input HMASTLOCK, // ignored + input [ 3 : 0 ] HPROT, // ignored + input HSEL, + input [ 2 : 0 ] HSIZE, + input [ 1 : 0 ] HTRANS, + input [ 31 : 0 ] HWDATA, + input HWRITE, + input HREADY_IN, + output reg [ 31 : 0 ] HRDATA, + output HREADY, + output HRESP, + input SI_Endian, // ignored + + //UART side + input UART_SRX, // UART serial input signal + output UART_STX, // UART serial output signal + output UART_RTS, // UART MODEM Request To Send + input UART_CTS, // UART MODEM Clear To Send + output UART_DTR, // UART MODEM Data Terminal Ready + input UART_DSR, // UART MODEM Data Set Ready + input UART_RI, // UART MODEM Ring Indicator + input UART_DCD, // UART MODEM Data Carrier Detect + + //UART internal + output UART_BAUD, // UART baudrate output + output UART_INT // UART interrupt +); + + parameter S_INIT = 0, + S_IDLE = 1, + S_READ = 2, + S_WRITE = 3; + + reg [ 1:0 ] State, Next; + + assign HRESP = 1'b0; + assign HREADY = (State == S_IDLE); + + always @ (posedge HCLK) begin + if (~HRESETn) + State <= S_INIT; + else + State <= Next; + end + + reg [ 2:0 ] ADDR_old; + wire [ 2:0 ] ADDR = HADDR [ 4:2 ]; + wire [ 7:0 ] ReadData; + + parameter HTRANS_IDLE = 2'b0; + wire NeedAction = HTRANS != HTRANS_IDLE && (HSEL == 1'b1) && HREADY_IN; + always @ (*) begin + //State change decision + case(State) + default : Next = S_IDLE; + S_IDLE : Next = ~NeedAction ? S_IDLE : ( + HWRITE ? S_WRITE : S_READ ); + endcase + end + + always @ (posedge HCLK) begin + case(State) + S_INIT : ; + S_IDLE : if(HSEL == 1'b1) ADDR_old <= ADDR; + S_READ : HRDATA <= { 24'b0, ReadData}; + S_WRITE : ; + endcase + end + + wire [ 7:0 ] WriteData = HWDATA [ 7:0 ]; + wire [ 2:0 ] ActionAddr; + wire WriteAction; + wire ReadAction; + reg [ 10:0 ] conf; + + assign { ReadAction, WriteAction, ActionAddr } = conf; + + always @ (*) begin + //io + case(State) + default : conf = { 2'b00, 8'b0 }; + S_READ : conf = { 2'b10, ADDR_old }; + S_WRITE : conf = { 2'b01, ADDR_old }; + endcase + end + + // Registers + uart_regs regs( + .clk ( HCLK ), + .wb_rst_i ( ~HRESETn ), + .wb_addr_i ( ActionAddr ), + .wb_dat_i ( WriteData ), + .wb_dat_o ( ReadData ), + .wb_we_i ( WriteAction ), + .wb_re_i ( ReadAction ), + .modem_inputs ( { UART_CTS, UART_DSR, UART_RI, UART_DCD } ), + .stx_pad_o ( UART_STX ), + .srx_pad_i ( UART_SRX ), + .rts_pad_o ( UART_RTS ), + .dtr_pad_o ( UART_DTR ), + .int_o ( UART_INT ), + .baud_o ( UART_BAUD ) + ); + +endmodule \ No newline at end of file diff --git a/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/raminfr.v b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/raminfr.v new file mode 100644 index 0000000..090f751 --- /dev/null +++ b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/raminfr.v @@ -0,0 +1,111 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// raminfr.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Inferrable Distributed RAM for FIFOs //// +//// //// +//// Known problems (limits): //// +//// None . //// +//// //// +//// To Do: //// +//// Nothing so far. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// //// +//// Created: 2002/07/22 //// +//// Last Updated: 2002/07/22 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// + +//Following is the Verilog code for a dual-port RAM with asynchronous read. +module raminfr + (clk, we, a, dpra, di, dpo); + +parameter addr_width = 4; +parameter data_width = 8; +parameter depth = 16; + +input clk; +input we; +input [addr_width-1:0] a; +input [addr_width-1:0] dpra; +input [data_width-1:0] di; +//output [data_width-1:0] spo; +output [data_width-1:0] dpo; +reg [data_width-1:0] ram [depth-1:0]; + +wire [data_width-1:0] dpo; +wire [data_width-1:0] di; +wire [addr_width-1:0] a; +wire [addr_width-1:0] dpra; + + always @(posedge clk) begin + if (we) + ram[a] <= di; + end +// assign spo = ram[a]; + assign dpo = ram[dpra]; +endmodule + diff --git a/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_defines.v b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_defines.v new file mode 100644 index 0000000..757a8f8 --- /dev/null +++ b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_defines.v @@ -0,0 +1,233 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_defines.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Defines of the Core //// +//// //// +//// Known problems (limits): //// +//// None //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.13 2003/06/11 16:37:47 gorban +// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. +// +// Revision 1.12 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.10 2001/12/11 08:55:40 mohor +// Scratch register define added. +// +// Revision 1.9 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.8 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.7 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.6 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.5 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.4 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.3 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:11+02 jacob +// Initial revision +// +// + +// Uncomment this if you want your UART to have +// 16xBaudrate output port. +// If defined, the enable signal will be used to drive baudrate_o signal +// It's frequency is 16xbaudrate + +// Register addresses +`define UART_REG_RB 3'd0 // receiver buffer +`define UART_REG_TR 3'd0 // transmitter +`define UART_REG_IE 3'd1 // Interrupt enable +`define UART_REG_II 3'd2 // Interrupt identification +`define UART_REG_FC 3'd2 // FIFO control +`define UART_REG_LC 3'd3 // Line Control +`define UART_REG_MC 3'd4 // Modem control +`define UART_REG_LS 3'd5 // Line status +`define UART_REG_MS 3'd6 // Modem status +`define UART_REG_SR 3'd7 // Scratch register +`define UART_REG_DL1 3'd0 // Divisor latch bytes (1-2) +`define UART_REG_DL2 3'd1 + +// Interrupt Enable register bits +`define UART_IE_RDA 0 // Received Data available interrupt +`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt +`define UART_IE_RLS 2 // Receiver Line Status Interrupt +`define UART_IE_MS 3 // Modem Status Interrupt + +// Interrupt Identification register bits +`define UART_II_IP 0 // Interrupt pending when 0 +`define UART_II_II 3:1 // Interrupt identification + +// Interrupt identification values for bits 3:1 +`define UART_II_RLS 3'b011 // Receiver Line Status +`define UART_II_RDA 3'b010 // Receiver Data available +`define UART_II_TI 3'b110 // Timeout Indication +`define UART_II_THRE 3'b001 // Transmitter Holding Register empty +`define UART_II_MS 3'b000 // Modem Status + +// FIFO Control Register bits +`define UART_FC_TL 1:0 // Trigger level + +// FIFO trigger level values +`define UART_FC_1 2'b00 +`define UART_FC_4 2'b01 +`define UART_FC_8 2'b10 +`define UART_FC_14 2'b11 + +// Line Control register bits +`define UART_LC_BITS 1:0 // bits in character +`define UART_LC_SB 2 // stop bits +`define UART_LC_PE 3 // parity enable +`define UART_LC_EP 4 // even parity +`define UART_LC_SP 5 // stick parity +`define UART_LC_BC 6 // Break control +`define UART_LC_DL 7 // Divisor Latch access bit + +// Modem Control register bits +`define UART_MC_DTR 0 +`define UART_MC_RTS 1 +`define UART_MC_OUT1 2 +`define UART_MC_OUT2 3 +`define UART_MC_LB 4 // Loopback mode + +// Line Status Register bits +`define UART_LS_DR 0 // Data ready +`define UART_LS_OE 1 // Overrun Error +`define UART_LS_PE 2 // Parity Error +`define UART_LS_FE 3 // Framing Error +`define UART_LS_BI 4 // Break interrupt +`define UART_LS_TFE 5 // Transmit FIFO is empty +`define UART_LS_TE 6 // Transmitter Empty indicator +`define UART_LS_EI 7 // Error indicator + +// Modem Status Register bits +`define UART_MS_DCTS 0 // Delta signals +`define UART_MS_DDSR 1 +`define UART_MS_TERI 2 +`define UART_MS_DDCD 3 +`define UART_MS_CCTS 4 // Complement signals +`define UART_MS_CDSR 5 +`define UART_MS_CRI 6 +`define UART_MS_CDCD 7 + +// FIFO parameter defines + +`define UART_FIFO_WIDTH 8 +`define UART_FIFO_DEPTH 16 +`define UART_FIFO_POINTER_W 4 +`define UART_FIFO_COUNTER_W 5 +// receiver fifo has width 11 because it has break, parity and framing error bits +`define UART_FIFO_REC_WIDTH 11 + + +`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded +`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register) +`define FAST_TEST 1 // 64/1024 packets are sent + +`define PRESCALER_PRESET_HARD +`define PRESCALER_HIGH_PRESET 8'd0 +`define PRESCALER_LOW_PRESET 8'd15 + + + + + diff --git a/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_receiver.v b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_receiver.v new file mode 100644 index 0000000..44c2936 --- /dev/null +++ b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_receiver.v @@ -0,0 +1,475 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_receiver.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core receiver logic //// +//// //// +//// Known problems (limits): //// +//// None known //// +//// //// +//// To Do: //// +//// Thourough testing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.29 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.28 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.27 2001/12/30 20:39:13 mohor +// More than one character was stored in case of break. End of the break +// was not detected correctly. +// +// Revision 1.26 2001/12/20 13:28:27 mohor +// Missing declaration of rf_push_q fixed. +// +// Revision 1.25 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.24 2001/12/19 08:03:34 mohor +// Warnings cleared. +// +// Revision 1.23 2001/12/19 07:33:54 mohor +// Synplicity was having troubles with the comment. +// +// Revision 1.22 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.21 2001/12/13 10:31:16 mohor +// timeout irq must be set regardless of the rda irq (rda irq does not reset the +// timeout counter). +// +// Revision 1.20 2001/12/10 19:52:05 gorban +// Igor fixed break condition bugs +// +// Revision 1.19 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.18 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.17 2001/11/28 19:36:39 gorban +// Fixed: timeout and break didn't pay attention to current data format when counting time +// +// Revision 1.16 2001/11/27 22:17:09 gorban +// Fixed bug that prevented synthesis in uart_receiver.v +// +// Revision 1.15 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.14 2001/11/10 12:43:21 gorban +// Logic Synthesis bugs fixed. Some other minor changes +// +// Revision 1.13 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.12 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.11 2001/10/31 15:19:22 gorban +// Fixes to break and timeout conditions +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.6 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.5 2001/06/02 14:28:14 gorban +// Fixed receiver and transmitter. Major bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.1 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:11+02 jacob +// Initial revision +// +// + +`include "uart_defines.v" + +module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, + counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); + +input clk; +input wb_rst_i; +input [7:0] lcr; +input rf_pop; +input srx_pad_i; +input enable; +input rx_reset; +input lsr_mask; + +output [9:0] counter_t; +output [`UART_FIFO_COUNTER_W-1:0] rf_count; +output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +output rf_overrun; +output rf_error_bit; +output [3:0] rstate; +output rf_push_pulse; + +reg [3:0] rstate; +reg [3:0] rcounter16; +reg [2:0] rbit_counter; +reg [7:0] rshift; // receiver shift register +reg rparity; // received parity +reg rparity_error; +reg rframing_error; // framing error flag +reg rparity_xor; +reg [7:0] counter_b; // counts the 0 (low) signals +reg rf_push_q; + +// RX FIFO signals +reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in; +wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +wire rf_push_pulse; +reg rf_push; +wire rf_pop; +wire rf_overrun; +wire [`UART_FIFO_COUNTER_W-1:0] rf_count; +wire rf_error_bit; // an error (parity or framing) is inside the fifo +wire break_error = (counter_b == 0); + +// RX FIFO instance +uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx( + .clk( clk ), + .wb_rst_i( wb_rst_i ), + .data_in( rf_data_in ), + .data_out( rf_data_out ), + .push( rf_push_pulse ), + .pop( rf_pop ), + .overrun( rf_overrun ), + .count( rf_count ), + .error_bit( rf_error_bit ), + .fifo_reset( rx_reset ), + .reset_status(lsr_mask) +); + +wire rcounter16_eq_7 = (rcounter16 == 4'd7); +wire rcounter16_eq_0 = (rcounter16 == 4'd0); + +wire [3:0] rcounter16_minus_1 = rcounter16 - 3'd1; + +parameter sr_idle = 4'd0; +parameter sr_rec_start = 4'd1; +parameter sr_rec_bit = 4'd2; +parameter sr_rec_parity = 4'd3; +parameter sr_rec_stop = 4'd4; +parameter sr_check_parity = 4'd5; +parameter sr_rec_prepare = 4'd6; +parameter sr_end_bit = 4'd7; +parameter sr_ca_lc_parity = 4'd8; +parameter sr_wait1 = 4'd9; +parameter sr_push = 4'd10; + + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + rstate <= sr_idle; + rcounter16 <= 0; + rbit_counter <= 0; + rparity_xor <= 1'b0; + rframing_error <= 1'b0; + rparity_error <= 1'b0; + rparity <= 1'b0; + rshift <= 0; + rf_push <= 1'b0; + rf_data_in <= 0; + end + else + if (enable) + begin + case (rstate) + sr_idle : begin + rf_push <= 1'b0; + rf_data_in <= 0; + rcounter16 <= 4'b1110; + if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?) + begin + rstate <= sr_rec_start; + end + end + sr_rec_start : begin + rf_push <= 1'b0; + if (rcounter16_eq_7) // check the pulse + if (srx_pad_i==1'b1) // no start bit + rstate <= sr_idle; + else // start bit detected + rstate <= sr_rec_prepare; + rcounter16 <= rcounter16_minus_1; + end + sr_rec_prepare:begin + case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word + 2'b00 : rbit_counter <= 3'b100; + 2'b01 : rbit_counter <= 3'b101; + 2'b10 : rbit_counter <= 3'b110; + 2'b11 : rbit_counter <= 3'b111; + endcase + if (rcounter16_eq_0) + begin + rstate <= sr_rec_bit; + rcounter16 <= 4'b1110; + rshift <= 0; + end + else + rstate <= sr_rec_prepare; + rcounter16 <= rcounter16_minus_1; + end + sr_rec_bit : begin + if (rcounter16_eq_0) + rstate <= sr_end_bit; + if (rcounter16_eq_7) // read the bit + case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word + 2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]}; + 2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]}; + 2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]}; + 2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]}; + endcase + rcounter16 <= rcounter16_minus_1; + end + sr_end_bit : begin + if (rbit_counter==3'b0) // no more bits in word + if (lcr[`UART_LC_PE]) // choose state based on parity + rstate <= sr_rec_parity; + else + begin + rstate <= sr_rec_stop; + rparity_error <= 1'b0; // no parity - no error :) + end + else // else we have more bits to read + begin + rstate <= sr_rec_bit; + rbit_counter <= rbit_counter - 3'd1; + end + rcounter16 <= 4'b1110; + end + sr_rec_parity: begin + if (rcounter16_eq_7) // read the parity + begin + rparity <= srx_pad_i; + rstate <= sr_ca_lc_parity; + end + rcounter16 <= rcounter16_minus_1; + end + sr_ca_lc_parity : begin // rcounter equals 6 + rcounter16 <= rcounter16_minus_1; + rparity_xor <= ^{rshift,rparity}; // calculate parity on all incoming data + rstate <= sr_check_parity; + end + sr_check_parity: begin // rcounter equals 5 + case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) + 2'b00: rparity_error <= rparity_xor == 0; // no error if parity 1 + 2'b01: rparity_error <= ~rparity; // parity should sticked to 1 + 2'b10: rparity_error <= rparity_xor == 1; // error if parity is odd + 2'b11: rparity_error <= rparity; // parity should be sticked to 0 + endcase + rcounter16 <= rcounter16_minus_1; + rstate <= sr_wait1; + end + sr_wait1 : if (rcounter16_eq_0) + begin + rstate <= sr_rec_stop; + rcounter16 <= 4'b1110; + end + else + rcounter16 <= rcounter16_minus_1; + sr_rec_stop : begin + if (rcounter16_eq_7) // read the parity + begin + rframing_error <= !srx_pad_i; // no framing error if input is 1 (stop bit) + rstate <= sr_push; + end + rcounter16 <= rcounter16_minus_1; + end + sr_push : begin +/////////////////////////////////////// +// $display($time, ": received: %b", rf_data_in); + if(srx_pad_i | break_error) + begin + if(break_error) + rf_data_in <= {8'b0, 3'b100}; // break input (empty character) to receiver FIFO + else + rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; + rf_push <= 1'b1; + rstate <= sr_idle; + end + else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i + begin + rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; + rf_push <= 1'b1; + rcounter16 <= 4'b1110; + rstate <= sr_rec_start; + end + + end + default : rstate <= sr_idle; + endcase + end // if (enable) +end // always of receiver + +always @ (posedge clk or posedge wb_rst_i) +begin + if(wb_rst_i) + rf_push_q <= 0; + else + rf_push_q <= rf_push; +end + +assign rf_push_pulse = rf_push & ~rf_push_q; + + +// +// Break condition detection. +// Works in conjuction with the receiver state machine + +reg [9:0] toc_value; // value to be set to timeout counter + +always @(lcr) + case (lcr[3:0]) + 4'b0000 : toc_value = 447; // 7 bits + 4'b0100 : toc_value = 479; // 7.5 bits + 4'b0001, 4'b1000 : toc_value = 511; // 8 bits + 4'b1100 : toc_value = 543; // 8.5 bits + 4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits + 4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits + 4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits + 4'b1111 : toc_value = 767; // 12 bits + endcase // case(lcr[3:0]) + +wire [7:0] brc_value; // value to be set to break counter +assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + counter_b <= 8'd159; + else + if (srx_pad_i) + counter_b <= brc_value; // character time length - 1 + else + if(enable & counter_b != 8'b0) // only work on enable times break not reached. + counter_b <= counter_b - 8'd1; // decrement break counter +end // always of break condition detection + +/// +/// Timeout condition detection +reg [9:0] counter_t; // counts the timeout condition clocks + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + counter_t <= 10'd639; // 10 bits for the default 8N1 + else + if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level + counter_t <= toc_value; + else + if (enable && counter_t != 10'b0) // we don't want to underflow + counter_t <= counter_t - 10'd1; +end + +endmodule diff --git a/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_regs.v b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_regs.v new file mode 100644 index 0000000..7e7b76e --- /dev/null +++ b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_regs.v @@ -0,0 +1,877 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_regs.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Registers of the uart 16550 core //// +//// //// +//// Known problems (limits): //// +//// Inserts 1 wait state in all WISHBONE transfers //// +//// //// +//// To Do: //// +//// Nothing or verification. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: (See log for the revision history //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.41 2004/05/21 11:44:41 tadejm +// Added synchronizer flops for RX input. +// +// Revision 1.40 2003/06/11 16:37:47 gorban +// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. +// +// Revision 1.39 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.38 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.37 2001/12/27 13:24:09 mohor +// lsr[7] was not showing overrun errors. +// +// Revision 1.36 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.35 2001/12/19 08:03:34 mohor +// Warnings cleared. +// +// Revision 1.34 2001/12/19 07:33:54 mohor +// Synplicity was having troubles with the comment. +// +// Revision 1.33 2001/12/17 10:14:43 mohor +// Things related to msr register changed. After THRE IRQ occurs, and one +// character is written to the transmit fifo, the detection of the THRE bit in the +// LSR is delayed for one character time. +// +// Revision 1.32 2001/12/14 13:19:24 mohor +// MSR register fixed. +// +// Revision 1.31 2001/12/14 10:06:58 mohor +// After reset modem status register MSR should be reset. +// +// Revision 1.30 2001/12/13 10:09:13 mohor +// thre irq should be cleared only when being source of interrupt. +// +// Revision 1.29 2001/12/12 09:05:46 mohor +// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). +// +// Revision 1.28 2001/12/10 19:52:41 gorban +// Scratch register added +// +// Revision 1.27 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.26 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.25 2001/11/28 19:36:39 gorban +// Fixed: timeout and break didn't pay attention to current data format when counting time +// +// Revision 1.24 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.23 2001/11/12 21:57:29 gorban +// fixed more typo bugs +// +// Revision 1.22 2001/11/12 15:02:28 mohor +// lsr1r error fixed. +// +// Revision 1.21 2001/11/12 14:57:27 mohor +// ti_int_pnd error fixed. +// +// Revision 1.20 2001/11/12 14:50:27 mohor +// ti_int_d error fixed. +// +// Revision 1.19 2001/11/10 12:43:21 gorban +// Logic Synthesis bugs fixed. Some other minor changes +// +// Revision 1.18 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.17 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.16 2001/11/02 09:55:16 mohor +// no message +// +// Revision 1.15 2001/10/31 15:19:22 gorban +// Fixes to break and timeout conditions +// +// Revision 1.14 2001/10/29 17:00:46 gorban +// fixed parity sending and tx_fifo resets over- and underrun +// +// Revision 1.13 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.12 2001/10/19 16:21:40 gorban +// Changes data_out to be synchronous again as it should have been. +// +// Revision 1.11 2001/10/18 20:35:45 gorban +// small fix +// +// Revision 1.10 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.9 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.10 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.9 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.8 2001/05/29 20:05:04 gorban +// Fixed some bugs and synthesis problems. +// +// Revision 1.7 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.6 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.5 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:11+02 jacob +// Initial revision +// +// + +`include "uart_defines.v" + +`define UART_DL1 7:0 +`define UART_DL2 15:8 + +module uart_regs + (clk, + wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i, + + // additional signals + modem_inputs, + stx_pad_o, srx_pad_i, rts_pad_o, dtr_pad_o, int_o, baud_o +); + +input clk; +input wb_rst_i; +input [2:0] wb_addr_i; +input [7:0] wb_dat_i; +output [7:0] wb_dat_o; +input wb_we_i; +input wb_re_i; + +output stx_pad_o; +input srx_pad_i; + +input [3:0] modem_inputs; +output rts_pad_o; +output dtr_pad_o; +output int_o; +output baud_o; + +wire [3:0] modem_inputs; +reg enable; + +assign baud_o = enable; // baud_o is actually the enable signal + +wire stx_pad_o; // received from transmitter module +wire srx_pad_i; +wire srx_pad; + +reg [7:0] wb_dat_o; + +wire [2:0] wb_addr_i; +wire [7:0] wb_dat_i; + + +reg [3:0] ier; +reg [3:0] iir; +reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored +reg [4:0] mcr; +reg [7:0] lcr; +reg [7:0] msr; +reg [15:0] dl; // 32-bit divisor latch +reg [7:0] scratch; // UART scratch register +reg start_dlc; // activate dlc on writing to UART_DL1 +reg lsr_mask_d; // delay for lsr_mask condition +reg msi_reset; // reset MSR 4 lower bits indicator +//reg threi_clear; // THRE interrupt clear flag +reg [15:0] dlc; // 32-bit divisor latch counter +reg int_o; + +reg [3:0] trigger_level; // trigger level of the receiver FIFO +reg rx_reset; +reg tx_reset; + +wire dlab; // divisor latch access bit +wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits +wire loopback; // loopback bit (MCR bit 4) +wire cts, dsr, ri, dcd; // effective signals +wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback) +wire rts_pad_o, dtr_pad_o; // modem control outputs + +// LSR bits wires and regs +wire [7:0] lsr; +wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7; +reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r; +wire lsr_mask; // lsr_mask + +// +// ASSINGS +// + +assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r }; + +assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs; +assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; + +assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]} + : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; + +assign dlab = lcr[`UART_LC_DL]; +assign loopback = mcr[4]; + +// assign modem outputs +assign rts_pad_o = mcr[`UART_MC_RTS]; +assign dtr_pad_o = mcr[`UART_MC_DTR]; + +// Interrupt signals +wire rls_int; // receiver line status interrupt +wire rda_int; // receiver data available interrupt +wire ti_int; // timeout indicator interrupt +wire thre_int; // transmitter holding register empty interrupt +wire ms_int; // modem status interrupt + +// FIFO signals +reg tf_push; +reg rf_pop; +wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +wire rf_error_bit; // an error (parity or framing) is inside the fifo +wire rf_overrun; +wire rf_push_pulse; +wire [`UART_FIFO_COUNTER_W-1:0] rf_count; +wire [`UART_FIFO_COUNTER_W-1:0] tf_count; +wire [2:0] tstate; +wire [3:0] rstate; +wire [9:0] counter_t; + +wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo. +reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle) +reg [7:0] block_value; // One character length minus stop bit + +// Transmitter Instance +wire serial_out; + +uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask); + + // Synchronizing and sampling serial RX input + uart_sync_flops i_uart_sync_flops + ( + .rst_i (wb_rst_i), + .clk_i (clk), + .stage1_rst_i (1'b0), + .stage1_clk_en_i (1'b1), + .async_dat_i (srx_pad_i), + .sync_dat_o (srx_pad) + ); + defparam i_uart_sync_flops.width = 1; + defparam i_uart_sync_flops.init_value = 1'b1; + +// handle loopback +wire serial_in = loopback ? serial_out : srx_pad; +assign stx_pad_o = loopback ? 1'b1 : serial_out; + +// Receiver Instance +uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable, + counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); + + +// Asynchronous reading here because the outputs are sampled in uart_wb.v file +always @(dl or dlab or ier or iir or scratch + or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading +begin + case (wb_addr_i) + `UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3]; + `UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : {4'd0,ier}; + `UART_REG_II : wb_dat_o = {4'b1100,iir}; + `UART_REG_LC : wb_dat_o = lcr; + `UART_REG_LS : wb_dat_o = lsr; + `UART_REG_MS : wb_dat_o = msr; + `UART_REG_SR : wb_dat_o = scratch; + default: wb_dat_o = 8'b0; // ?? + endcase // case(wb_addr_i) +end // always @ (dl or dlab or ier or iir or scratch... + + +// rf_pop signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + rf_pop <= 0; + else + if (rf_pop) // restore the signal to 0 after one clock cycle + rf_pop <= 0; + else + if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab) + rf_pop <= 1; // advance read pointer +end + +wire lsr_mask_condition; +wire iir_read; +wire msr_read; +wire fifo_read; +wire fifo_write; + +assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab); +assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab); +assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab); +assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab); +assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab); + +// lsr_mask_d delayed signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + lsr_mask_d <= 0; + else // reset bits in the Line Status Register + lsr_mask_d <= lsr_mask_condition; +end + +// lsr_mask is rise detected +assign lsr_mask = lsr_mask_condition && ~lsr_mask_d; + +// msi_reset signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + msi_reset <= 1; + else + if (msi_reset) + msi_reset <= 0; + else + if (msr_read) + msi_reset <= 1; // reset bits in Modem Status Register +end + + +// +// WRITES AND RESETS // +// +// Line Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + lcr <= 8'b00000011; // 8n1 setting + else + if (wb_we_i && wb_addr_i==`UART_REG_LC) + lcr <= wb_dat_i; + +// Interrupt Enable Register or UART_DL2 +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + begin + ier <= 4'b0000; // no interrupts after reset +`ifdef PRESCALER_PRESET_HARD + dl[`UART_DL2] <= `PRESCALER_HIGH_PRESET; +`else + dl[`UART_DL2] <= 8'b0; +`endif + end + else + if (wb_we_i && wb_addr_i==`UART_REG_IE) + if (dlab) + begin + dl[`UART_DL2] <= +`ifdef PRESCALER_PRESET_HARD + dl[`UART_DL2]; +`else + wb_dat_i; +`endif + end + else + ier <= wb_dat_i[3:0]; // ier uses only 4 lsb + + +// FIFO Control Register and rx_reset, tx_reset signals +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + fcr <= 2'b11; + rx_reset <= 0; + tx_reset <= 0; + end else + if (wb_we_i && wb_addr_i==`UART_REG_FC) begin + fcr <= wb_dat_i[7:6]; + rx_reset <= wb_dat_i[1]; + tx_reset <= wb_dat_i[2]; + end else begin + rx_reset <= 0; + tx_reset <= 0; + end + +// Modem Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + mcr <= 5'b0; + else + if (wb_we_i && wb_addr_i==`UART_REG_MC) + mcr <= wb_dat_i[4:0]; + +// Scratch register +// Line Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + scratch <= 0; // 8n1 setting + else + if (wb_we_i && wb_addr_i==`UART_REG_SR) + scratch <= wb_dat_i; + +// TX_FIFO or UART_DL1 +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + begin +`ifdef PRESCALER_PRESET_HARD + dl[`UART_DL1] <= `PRESCALER_LOW_PRESET; +`else + dl[`UART_DL1] <= 8'b0; +`endif + tf_push <= 1'b0; + start_dlc <= 1'b0; + end + else + if (wb_we_i && wb_addr_i==`UART_REG_TR) + if (dlab) + begin +`ifdef PRESCALER_PRESET_HARD + dl[`UART_DL1] <= dl[`UART_DL1]; +`else + dl[`UART_DL1] <= wb_dat_i; +`endif + start_dlc <= 1'b1; // enable DL counter + tf_push <= 1'b0; + end + else + begin + tf_push <= 1'b1; + start_dlc <= 1'b0; + end // else: !if(dlab) + else + begin + start_dlc <= 1'b0; + tf_push <= 1'b0; + end // else: !if(dlab) + +// Receiver FIFO trigger level selection logic (asynchronous mux) +always @(fcr) + case (fcr[`UART_FC_TL]) + 2'b00 : trigger_level = 1; + 2'b01 : trigger_level = 4; + 2'b10 : trigger_level = 8; + 2'b11 : trigger_level = 14; + endcase // case(fcr[`UART_FC_TL]) + +// +// STATUS REGISTERS // +// + +// Modem Status Register +reg [3:0] delayed_modem_signals; +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + msr <= 0; + delayed_modem_signals[3:0] <= 0; + end + else begin + msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 : + msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]); + msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c}; + delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts}; + end +end + + +// Line Status Register + +// activation conditions +assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition +assign lsr1 = rf_overrun; // Receiver overrun error +assign lsr2 = rf_data_out[1]; // parity error bit +assign lsr3 = rf_data_out[0]; // framing error bit +assign lsr4 = rf_data_out[2]; // break error in the character +assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty +assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty +assign lsr7 = rf_error_bit | rf_overrun; + +// lsr bit0 (receiver data available) +reg lsr0_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr0_d <= 0; + else lsr0_d <= lsr0; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr0r <= 0; + else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 1'b0 : // deassert condition + lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted + +// lsr bit 1 (receiver overrun) +reg lsr1_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr1_d <= 0; + else lsr1_d <= lsr1; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr1r <= 0; + else lsr1r <= lsr_mask ? 1'b0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise + +// lsr bit 2 (parity error) +reg lsr2_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr2_d <= 0; + else lsr2_d <= lsr2; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr2r <= 0; + else lsr2r <= lsr_mask ? 1'b0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise + +// lsr bit 3 (framing error) +reg lsr3_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr3_d <= 0; + else lsr3_d <= lsr3; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr3r <= 0; + else lsr3r <= lsr_mask ? 1'b0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise + +// lsr bit 4 (break indicator) +reg lsr4_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr4_d <= 0; + else lsr4_d <= lsr4; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr4r <= 0; + else lsr4r <= lsr_mask ? 1'b0 : lsr4r || (lsr4 && ~lsr4_d); + +// lsr bit 5 (transmitter fifo is empty) +reg lsr5_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr5_d <= 1; + else lsr5_d <= lsr5; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr5r <= 1; + else lsr5r <= (fifo_write) ? 1'b0 : lsr5r || (lsr5 && ~lsr5_d); + +// lsr bit 6 (transmitter empty indicator) +reg lsr6_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr6_d <= 1; + else lsr6_d <= lsr6; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr6r <= 1; + else lsr6r <= (fifo_write) ? 1'b0 : lsr6r || (lsr6 && ~lsr6_d); + +// lsr bit 7 (error in fifo) +reg lsr7_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr7_d <= 0; + else lsr7_d <= lsr7; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr7r <= 0; + else lsr7r <= lsr_mask ? 1'b0 : lsr7r || (lsr7 && ~lsr7_d); + +// Frequency divider +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + dlc <= 0; + else + if (start_dlc | ~ (|dlc)) + dlc <= dl - 16'd1; // preset counter + else + dlc <= dlc - 16'd1; // decrement counter +end + +// Enable signal generation logic +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + enable <= 1'b0; + else + if (|dl & ~(|dlc)) // dl>0 & dlc==0 + enable <= 1'b1; + else + enable <= 1'b0; +end + +// Delaying THRE status for one character cycle after a character is written to an empty fifo. +always @(lcr) + case (lcr[3:0]) + 4'b0000 : block_value = 95; // 6 bits + 4'b0100 : block_value = 103; // 6.5 bits + 4'b0001, 4'b1000 : block_value = 111; // 7 bits + 4'b1100 : block_value = 119; // 7.5 bits + 4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits + 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits + 4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits + 4'b1111 : block_value = 175; // 11 bits + endcase // case(lcr[3:0]) + +// Counting time of one character minus stop bit +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + block_cnt <= 8'd0; + else + if(lsr5r & fifo_write) // THRE bit set & write to fifo occured + block_cnt <= block_value; + else + if (enable & block_cnt != 8'b0) // only work on enable times + block_cnt <= block_cnt - 8'd1; // decrement break counter +end // always of break condition detection + +// Generating THRE status enable signal +assign thre_set_en = ~(|block_cnt); + + +// +// INTERRUPT LOGIC +// + +assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]); +assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level}); +assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE]; +assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]); +assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count); + +reg rls_int_d; +reg thre_int_d; +reg ms_int_d; +reg ti_int_d; +reg rda_int_d; + +// delay lines +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rls_int_d <= 0; + else rls_int_d <= rls_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rda_int_d <= 0; + else rda_int_d <= rda_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) thre_int_d <= 0; + else thre_int_d <= thre_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ms_int_d <= 0; + else ms_int_d <= ms_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ti_int_d <= 0; + else ti_int_d <= ti_int; + +// rise detection signals + +wire rls_int_rise; +wire thre_int_rise; +wire ms_int_rise; +wire ti_int_rise; +wire rda_int_rise; + +assign rda_int_rise = rda_int & ~rda_int_d; +assign rls_int_rise = rls_int & ~rls_int_d; +assign thre_int_rise = thre_int & ~thre_int_d; +assign ms_int_rise = ms_int & ~ms_int_d; +assign ti_int_rise = ti_int & ~ti_int_d; + +// interrupt pending flags +reg rls_int_pnd; +reg rda_int_pnd; +reg thre_int_pnd; +reg ms_int_pnd; +reg ti_int_pnd; + +// interrupt pending flags assignments +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rls_int_pnd <= 0; + else + rls_int_pnd <= lsr_mask ? 1'b0 : // reset condition + rls_int_rise ? 1'b1 : // latch condition + rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rda_int_pnd <= 0; + else + rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 1'b0 : // reset condition + rda_int_rise ? 1'b1 : // latch condition + rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) thre_int_pnd <= 0; + else + thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 1'b0 : + thre_int_rise ? 1'b1 : + thre_int_pnd && ier[`UART_IE_THRE]; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ms_int_pnd <= 0; + else + ms_int_pnd <= msr_read ? 1'b0 : + ms_int_rise ? 1'b1 : + ms_int_pnd && ier[`UART_IE_MS]; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ti_int_pnd <= 0; + else + ti_int_pnd <= fifo_read ? 1'b0 : + ti_int_rise ? 1'b1 : + ti_int_pnd && ier[`UART_IE_RDA]; +// end of pending flags + +// INT_O logic +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + int_o <= 1'b0; + else + int_o <= + rls_int_pnd ? ~lsr_mask : + rda_int_pnd ? 1'b1 : + ti_int_pnd ? ~fifo_read : + thre_int_pnd ? !(fifo_write & iir_read) : + ms_int_pnd ? ~msr_read : + 1'd0; // if no interrupt are pending +end + + +// Interrupt Identification register +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + iir <= 1; + else + if (rls_int_pnd) // interrupt is pending + begin + iir[`UART_II_II] <= `UART_II_RLS; // set identification register to correct value + iir[`UART_II_IP] <= 1'b0; // and clear the IIR bit 0 (interrupt pending) + end else // the sequence of conditions determines priority of interrupt identification + if (rda_int) + begin + iir[`UART_II_II] <= `UART_II_RDA; + iir[`UART_II_IP] <= 1'b0; + end + else if (ti_int_pnd) + begin + iir[`UART_II_II] <= `UART_II_TI; + iir[`UART_II_IP] <= 1'b0; + end + else if (thre_int_pnd) + begin + iir[`UART_II_II] <= `UART_II_THRE; + iir[`UART_II_IP] <= 1'b0; + end + else if (ms_int_pnd) + begin + iir[`UART_II_II] <= `UART_II_MS; + iir[`UART_II_IP] <= 1'b0; + end else // no interrupt is pending + begin + iir[`UART_II_II] <= 0; + iir[`UART_II_IP] <= 1'b1; + end +end + +endmodule diff --git a/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_rfifo.v b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_rfifo.v new file mode 100644 index 0000000..59a29b9 --- /dev/null +++ b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_rfifo.v @@ -0,0 +1,316 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_rfifo.v (Modified from uart_fifo.v) //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core receiver FIFO //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2002/07/22 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2003/06/11 16:37:47 gorban +// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. +// +// Revision 1.2 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.1 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.16 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.15 2001/12/18 09:01:07 mohor +// Bug that was entered in the last update fixed (rx state machine). +// +// Revision 1.14 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.13 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.12 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.11 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/24 08:48:10 mohor +// FIFO was not cleared after the data was read bug fixed. +// +// Revision 1.7 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.3 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:48 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +`include "uart_defines.v" + +module uart_rfifo (clk, + wb_rst_i, data_in, data_out, +// Control signals + push, // push strobe, active high + pop, // pop strobe, active high +// status signals + overrun, + count, + error_bit, + fifo_reset, + reset_status + ); + + +// FIFO parameters +parameter fifo_width = `UART_FIFO_WIDTH; +parameter fifo_depth = `UART_FIFO_DEPTH; +parameter fifo_pointer_w = `UART_FIFO_POINTER_W; +parameter fifo_counter_w = `UART_FIFO_COUNTER_W; + +input clk; +input wb_rst_i; +input push; +input pop; +input [fifo_width-1:0] data_in; +input fifo_reset; +input reset_status; + +output [fifo_width-1:0] data_out; +output overrun; +output [fifo_counter_w-1:0] count; +output error_bit; + +wire [fifo_width-1:0] data_out; +wire [7:0] data8_out; +// flags FIFO +reg [2:0] fifo[fifo_depth-1:0]; + +// FIFO pointers +reg [fifo_pointer_w-1:0] top; +reg [fifo_pointer_w-1:0] bottom; + +reg [fifo_counter_w-1:0] count; +reg overrun; + +wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'h1; + +raminfr #(fifo_pointer_w,8,fifo_depth) rfifo + (.clk(clk), + .we(push), + .a(top), + .dpra(bottom), + .di(data_in[fifo_width-1:fifo_width-8]), + .dpo(data8_out) + ); + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + begin + top <= 0; + bottom <= 0; + count <= 0; + fifo[0] <= 0; + fifo[1] <= 0; + fifo[2] <= 0; + fifo[3] <= 0; + fifo[4] <= 0; + fifo[5] <= 0; + fifo[6] <= 0; + fifo[7] <= 0; + fifo[8] <= 0; + fifo[9] <= 0; + fifo[10] <= 0; + fifo[11] <= 0; + fifo[12] <= 0; + fifo[13] <= 0; + fifo[14] <= 0; + fifo[15] <= 0; + end + else + if (fifo_reset) begin + top <= 0; + bottom <= 0; + count <= 0; + fifo[0] <= 0; + fifo[1] <= 0; + fifo[2] <= 0; + fifo[3] <= 0; + fifo[4] <= 0; + fifo[5] <= 0; + fifo[6] <= 0; + fifo[7] <= 0; + fifo[8] <= 0; + fifo[9] <= 0; + fifo[10] <= 0; + fifo[11] <= 0; + fifo[12] <= 0; + fifo[13] <= 0; + fifo[14] <= 0; + fifo[15] <= 0; + end + else + begin + case ({push, pop}) + 2'b10 : if (count0) + begin + fifo[bottom] <= 0; + bottom <= bottom + 4'd1; + count <= count - 5'd1; + end + 2'b11 : begin + bottom <= bottom + 4'd1; + top <= top_plus_1; + fifo[top] <= data_in[2:0]; + end + default: ; + endcase + end +end // always + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + overrun <= 1'b0; + else + if(fifo_reset | reset_status) + overrun <= 1'b0; + else + if(push & ~pop & (count==fifo_depth)) + overrun <= 1'b1; +end // always + + +// please note though that data_out is only valid one clock after pop signal +assign data_out = {data8_out,fifo[bottom]}; + +// Additional logic for detection of error conditions (parity and framing) inside the FIFO +// for the Line Status Register bit 7 + +wire [2:0] word0 = fifo[0]; +wire [2:0] word1 = fifo[1]; +wire [2:0] word2 = fifo[2]; +wire [2:0] word3 = fifo[3]; +wire [2:0] word4 = fifo[4]; +wire [2:0] word5 = fifo[5]; +wire [2:0] word6 = fifo[6]; +wire [2:0] word7 = fifo[7]; + +wire [2:0] word8 = fifo[8]; +wire [2:0] word9 = fifo[9]; +wire [2:0] word10 = fifo[10]; +wire [2:0] word11 = fifo[11]; +wire [2:0] word12 = fifo[12]; +wire [2:0] word13 = fifo[13]; +wire [2:0] word14 = fifo[14]; +wire [2:0] word15 = fifo[15]; + +// a 1 is returned if any of the error bits in the fifo is 1 +assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] | + word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] | + word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] | + word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] ); + +endmodule diff --git a/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_sync_flops.v b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_sync_flops.v new file mode 100644 index 0000000..82a3a61 --- /dev/null +++ b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_sync_flops.v @@ -0,0 +1,117 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_sync_flops.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core receiver logic //// +//// //// +//// Known problems (limits): //// +//// None known //// +//// //// +//// To Do: //// +//// Thourough testing. //// +//// //// +//// Author(s): //// +//// - Andrej Erzen (andreje@flextronics.si) //// +//// - Tadej Markovic (tadejm@flextronics.si) //// +//// //// +//// Created: 2004/05/20 //// +//// Last Updated: 2004/05/20 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +module uart_sync_flops +( + // internal signals + rst_i, + clk_i, + stage1_rst_i, + stage1_clk_en_i, + async_dat_i, + sync_dat_o +); + +parameter width = 1; +parameter init_value = 1'b0; + +input rst_i; // reset input +input clk_i; // clock input +input stage1_rst_i; // synchronous reset for stage 1 FF +input stage1_clk_en_i; // synchronous clock enable for stage 1 FF +input [width-1:0] async_dat_i; // asynchronous data input +output [width-1:0] sync_dat_o; // synchronous data output + + +// +// Interal signal declarations +// + +reg [width-1:0] sync_dat_o; +reg [width-1:0] flop_0; + + +// first stage +always @ (posedge clk_i or posedge rst_i) +begin + if (rst_i) + flop_0 <= {width{init_value}}; + else + flop_0 <= async_dat_i; +end + +// second stage +always @ (posedge clk_i or posedge rst_i) +begin + if (rst_i) + sync_dat_o <= {width{init_value}}; + else if (stage1_rst_i) + sync_dat_o <= {width{init_value}}; + else if (stage1_clk_en_i) + sync_dat_o <= flop_0; +end + +endmodule diff --git a/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_tfifo.v b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_tfifo.v new file mode 100644 index 0000000..5b254cb --- /dev/null +++ b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_tfifo.v @@ -0,0 +1,239 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_tfifo.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core transmitter FIFO //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2002/07/22 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.16 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.15 2001/12/18 09:01:07 mohor +// Bug that was entered in the last update fixed (rx state machine). +// +// Revision 1.14 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.13 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.12 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.11 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/24 08:48:10 mohor +// FIFO was not cleared after the data was read bug fixed. +// +// Revision 1.7 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.3 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:48 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +`include "uart_defines.v" + +module uart_tfifo (clk, + wb_rst_i, data_in, data_out, +// Control signals + push, // push strobe, active high + pop, // pop strobe, active high +// status signals + overrun, + count, + fifo_reset, + reset_status + ); + + +// FIFO parameters +parameter fifo_width = `UART_FIFO_WIDTH; +parameter fifo_depth = `UART_FIFO_DEPTH; +parameter fifo_pointer_w = `UART_FIFO_POINTER_W; +parameter fifo_counter_w = `UART_FIFO_COUNTER_W; + +input clk; +input wb_rst_i; +input push; +input pop; +input [fifo_width-1:0] data_in; +input fifo_reset; +input reset_status; + +output [fifo_width-1:0] data_out; +output overrun; +output [fifo_counter_w-1:0] count; + +wire [fifo_width-1:0] data_out; + +// FIFO pointers +reg [fifo_pointer_w-1:0] top; +reg [fifo_pointer_w-1:0] bottom; + +reg [fifo_counter_w-1:0] count; +reg overrun; +wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'd1; + +raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo + (.clk(clk), + .we(push), + .a(top), + .dpra(bottom), + .di(data_in), + .dpo(data_out) + ); + + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + begin + top <= 0; + bottom <= 0; + count <= 0; + end + else + if (fifo_reset) begin + top <= 0; + bottom <= 0; + count <= 0; + end + else + begin + case ({push, pop}) + 2'b10 : if (count0) + begin + bottom <= bottom + 4'd1; + count <= count - 5'd1; + end + 2'b11 : begin + bottom <= bottom + 4'd1; + top <= top_plus_1; + end + default: ; + endcase + end +end // always + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + overrun <= 1'b0; + else + if(fifo_reset | reset_status) + overrun <= 1'b0; + else + if(push & (count==fifo_depth)) + overrun <= 1'b1; +end // always + +endmodule diff --git a/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_transmitter.v b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_transmitter.v new file mode 100644 index 0000000..4a8ba9d --- /dev/null +++ b/tang20k/scr1/ip/ahb_lite_uart16550/src/uart16550/uart_transmitter.v @@ -0,0 +1,353 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_transmitter.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core transmitter logic //// +//// //// +//// Known problems (limits): //// +//// None known //// +//// //// +//// To Do: //// +//// Thourough testing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.18 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.16 2002/01/08 11:29:40 mohor +// tf_pop was too wide. Now it is only 1 clk cycle width. +// +// Revision 1.15 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.14 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.13 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.12 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.11 2001/10/29 17:00:46 gorban +// fixed parity sending and tx_fifo resets over- and underrun +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.6 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.5 2001/06/02 14:28:14 gorban +// Fixed receiver and transmitter. Major bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.1 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +`include "uart_defines.v" + +module uart_transmitter + (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask); + +input clk; +input wb_rst_i; +input [7:0] lcr; +input tf_push; +input [7:0] wb_dat_i; +input enable; +input tx_reset; +input lsr_mask; //reset of fifo +output stx_pad_o; +output [2:0] tstate; +output [`UART_FIFO_COUNTER_W-1:0] tf_count; + +reg [2:0] tstate; +reg [4:0] counter; +reg [2:0] bit_counter; // counts the bits to be sent +reg [6:0] shift_out; // output shift register +reg stx_o_tmp; +reg parity_xor; // parity of the word +reg tf_pop; +reg bit_out; + +// TX FIFO instance +// +// Transmitter FIFO signals +wire [`UART_FIFO_WIDTH-1:0] tf_data_in; +wire [`UART_FIFO_WIDTH-1:0] tf_data_out; +wire tf_push; +wire tf_overrun; +wire [`UART_FIFO_COUNTER_W-1:0] tf_count; + +assign tf_data_in = wb_dat_i; + +uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO + .clk( clk ), + .wb_rst_i( wb_rst_i ), + .data_in( tf_data_in ), + .data_out( tf_data_out ), + .push( tf_push ), + .pop( tf_pop ), + .overrun( tf_overrun ), + .count( tf_count ), + .fifo_reset( tx_reset ), + .reset_status(lsr_mask) +); + +// TRANSMITTER FINAL STATE MACHINE + +localparam s_idle = 3'd0; +localparam s_send_start = 3'd1; +localparam s_send_byte = 3'd2; +localparam s_send_parity = 3'd3; +localparam s_send_stop = 3'd4; +localparam s_pop_byte = 3'd5; + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + tstate <= s_idle; + stx_o_tmp <= 1'b1; + counter <= 5'b0; + shift_out <= 7'b0; + bit_out <= 1'b0; + parity_xor <= 1'b0; + tf_pop <= 1'b0; + bit_counter <= 3'b0; + end + else + if (enable) + begin + case (tstate) + s_idle : if (~|tf_count) // if tf_count==0 + begin + tstate <= s_idle; + stx_o_tmp <= 1'b1; + end + else + begin + tf_pop <= 1'b0; + stx_o_tmp <= 1'b1; + tstate <= s_pop_byte; + end + s_pop_byte : begin + tf_pop <= 1'b1; + case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word + 2'b00 : begin + bit_counter <= 3'b100; + parity_xor <= ^tf_data_out[4:0]; + end + 2'b01 : begin + bit_counter <= 3'b101; + parity_xor <= ^tf_data_out[5:0]; + end + 2'b10 : begin + bit_counter <= 3'b110; + parity_xor <= ^tf_data_out[6:0]; + end + 2'b11 : begin + bit_counter <= 3'b111; + parity_xor <= ^tf_data_out[7:0]; + end + endcase + {shift_out[6:0], bit_out} <= tf_data_out; + tstate <= s_send_start; + end + s_send_start : begin + tf_pop <= 1'b0; + if (~|counter) + counter <= 5'b01111; + else + if (counter == 5'b00001) + begin + counter <= 0; + tstate <= s_send_byte; + end + else + counter <= counter - 5'd1; + stx_o_tmp <= 1'b0; + // if (SIM) begin + // tstate <= s_idle; + // $write("%c", tf_data_out); + // $fflush(32'h80000001); + // end + end + s_send_byte : begin + if (~|counter) + counter <= 5'b01111; + else + if (counter == 5'b00001) + begin + if (bit_counter > 3'b0) + begin + bit_counter <= bit_counter - 3'd1; + {shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]}; + tstate <= s_send_byte; + end + else // end of byte + if (~lcr[`UART_LC_PE]) + begin + tstate <= s_send_stop; + end + else + begin + case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) + 2'b00: bit_out <= ~parity_xor; + 2'b01: bit_out <= 1'b1; + 2'b10: bit_out <= parity_xor; + 2'b11: bit_out <= 1'b0; + endcase + tstate <= s_send_parity; + end + counter <= 0; + end + else + counter <= counter - 5'd1; + stx_o_tmp <= bit_out; // set output pin + end + s_send_parity : begin + if (~|counter) + counter <= 5'b01111; + else + if (counter == 5'b00001) + begin + counter <= 5'd0; + tstate <= s_send_stop; + end + else + counter <= counter - 5'd1; + stx_o_tmp <= bit_out; + end + s_send_stop : begin + if (~|counter) + begin + casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]}) + 3'b0??: counter <= 5'b01101; // 1 stop bit ok igor + 3'b100: counter <= 5'b10101; // 1.5 stop bit + default: counter <= 5'b11101; // 2 stop bits + endcase + end + else + if (counter == 5'b00001) + begin + counter <= 0; + tstate <= s_idle; + end + else + counter <= counter - 5'd1; + stx_o_tmp <= 1'b1; + end + + default : // should never get here + tstate <= s_idle; + endcase + end // end if enable + else + tf_pop <= 1'b0; // tf_pop must be 1 cycle width +end // transmitter logic + +assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition + +endmodule diff --git a/tang20k/scr1/ip/ahb_slave_mux/ahb_slave_mux.sv b/tang20k/scr1/ip/ahb_slave_mux/ahb_slave_mux.sv new file mode 100644 index 0000000..6d50426 --- /dev/null +++ b/tang20k/scr1/ip/ahb_slave_mux/ahb_slave_mux.sv @@ -0,0 +1,49 @@ +`include "scr1_arch_custom.svh" +module ahb_slave_mux +( + input clk, + input rst_n, + input [SLAVE_DEVISES_CNT-1:0] hsel_s, + input [1:0] htrans, + input [31:0] rdata_0, + input [31:0] rdata_1, + input [31:0] rdata_2, + input [SLAVE_DEVISES_CNT-1:0] resp, + input [SLAVE_DEVISES_CNT-1:0] readyout, + output logic [31:0] hrdata, + output logic hresp, + output logic hready +); + logic [SLAVE_DEVISES_CNT-1:0] local_hsel; + always_ff @(posedge clk)begin + if (~rst_n)begin + local_hsel <= 2'b0; + end + else if (htrans != 2'b0 && hsel_s != 3'b0) begin + local_hsel <= hsel_s; + end + + end + always @* begin + if (local_hsel[0] == 1) begin + hresp = resp[0]; + hrdata = rdata_0; + hready = readyout[0]; + end + else if (local_hsel[1] == 1) begin + hready = readyout[1]; + hrdata = rdata_1; + hresp = resp[1]; + end + else if (local_hsel[2] == 1) begin + hready = readyout[2]; + hrdata = rdata_2; + hresp = resp[2]; + end + else begin + hready = 1'b1; + hrdata = 32'b0; + hresp = 1'b0; + end + end + endmodule: ahb_slave_mux diff --git a/tang20k/scr1/ip/rom_bsram_memory/rom_bsram.sv b/tang20k/scr1/ip/rom_bsram_memory/rom_bsram.sv new file mode 100644 index 0000000..d7e1422 --- /dev/null +++ b/tang20k/scr1/ip/rom_bsram_memory/rom_bsram.sv @@ -0,0 +1,49 @@ +`include "scr1_ahb.svh" +module rom_mem +( + input clk, + input rst_n, + input [$clog2(ROM_SIZE)+1:2] imem_addr, + input [1:0] imem_trans, + input imem_hsel, + output imem_ready, + output imem_resp, + output logic [SCR1_AHB_WIDTH-1:0] imem_data, + input [$clog2(ROM_SIZE)+1:2] dmem_addr, + input [1:0] dmem_trans, + input dmem_hsel, + input dmem_hready_in, + output reg dmem_ready, + output reg dmem_resp, + output logic [SCR1_AHB_WIDTH-1:0] dmem_data +); + + (* ram_style = "block" *) logic [SCR1_AHB_WIDTH-1:0] rom_block [ROM_SIZE-1:0] /* synthesis syn_ramstyle = "block_ram" */; + + logic rom_imem_need_action; + logic rom_dmem_need_action; + assign rom_imem_need_action = (imem_trans != 2'b00) && imem_hsel; + assign rom_dmem_need_action = (dmem_trans != 2'b00) && dmem_hsel && dmem_hready_in; + assign imem_ready = 1'b1; + assign imem_resp = 1'b0; + + + always_ff @(posedge clk) begin + if (~rst_n) begin + dmem_ready <= 1'b1; + dmem_resp <= 1'b0; + end + if (rom_imem_need_action) begin + imem_data <= rom_block[imem_addr]; + end + if (rom_dmem_need_action) begin + dmem_data <= rom_block[dmem_addr]; + dmem_ready <= 1'b1; + dmem_resp <= 1'b0; + end + end + + initial begin + $readmemh("scbl.mem", rom_block); + end + endmodule: rom_mem diff --git a/tang20k/scr1/ip/rom_bsram_memory/scbl.mem b/tang20k/scr1/ip/rom_bsram_memory/scbl.mem new file mode 100644 index 0000000..c6992eb --- /dev/null +++ b/tang20k/scr1/ip/rom_bsram_memory/scbl.mem @@ -0,0 +1,1830 @@ +000022b7 +88028293 +30029073 +00000297 +22428293 +30529073 +34401073 +08000293 +30429073 +f0011197 +fdc18193 +f1402573 +08051463 +f0010297 +7cc28293 +f0010317 +7c430313 +00c0006f +0002a023 +00428293 +fe62ece3 +f0010117 +62c10113 +00010213 +f0010297 +7a028293 +f0010317 +79830313 +00020393 +0140006f +0002a503 +00a3a023 +00428293 +00438393 +fe62e8e3 +98018293 +406282b3 +007282b3 +00c0006f +0003a023 +00438393 +fe53ece3 +34011073 +00000513 +00000593 +099000ef +08000293 +3042b073 +10500073 +ffdff06f +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +6e00106f +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +02c12823 +02d12a23 +c0002673 +c02026f3 +00112223 +340115f3 +00b12423 +00312623 +00412823 +00512a23 +00612c23 +00712e23 +02812023 +02912223 +02e12c23 +02f12e23 +05012023 +05112223 +05212423 +05312623 +05412823 +05512a23 +05612c23 +05712e23 +07812023 +07912223 +07a12423 +07b12623 +07c12823 +07d12a23 +07e12c23 +07f12e23 +f0011197 +e8018193 +00010593 +00800293 +00a28663 +00b00293 +08a29663 +00010213 +670010ef +00412083 +00c12183 +01012203 +01412283 +01812303 +01c12383 +02012403 +02412483 +02c12583 +03012603 +03412683 +03812703 +03c12783 +04012803 +04412883 +04812903 +04c12983 +05012a03 +05412a83 +05812b03 +05c12b83 +06012c03 +06412c83 +06812d03 +06c12d83 +07012e03 +07412e83 +07812f03 +07c12f83 +02812503 +00812103 +30200073 +5c40106f +00000013 +00000013 +34011173 +02a12423 +02b12623 +34202573 +ea0540e3 +ebdff06f +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +d01ff06f +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +4800106f +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +eb1ff06f +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ff010113 +00812423 +00050413 +00a00513 +00112623 +720000ef +ff010737 +01470713 +00072783 +0407f793 +fe078ce3 +c01026f3 +00005737 +e1f70713 +c01027f3 +40d787b3 +fef77ce3 +000400e7 +00c12083 +00812403 +01010113 +00008067 +ff010113 +00112623 +00812423 +00050413 +03d000ef +03a00513 +6c4000ef +02000513 +6bc000ef +38d000ef +00c12083 +00a42023 +00812403 +01010113 +00008067 +ff010113 +000015b7 +00812423 +00112623 +585000ef +ff010737 +01472783 +00050413 +01470713 +0017f793 +ff0106b7 +00078a63 +0006a783 +00072783 +0017f793 +fe079ae3 +02044863 +ffff2537 +8d850513 +6a4000ef +00040513 +21d000ef +00812403 +00c12083 +ffff2537 +8fc50513 +01010113 +6840006f +ffff2537 +8c050513 +678000ef +40800533 +1f1000ef +00812403 +00c12083 +00a00513 +01010113 +60c0006f +14058e63 +fe010113 +00912a23 +01212823 +01312623 +01412423 +00112e23 +00812c23 +01512223 +00058493 +00050913 +01000a13 +05e00993 +00090513 +740000ef +03a00513 +5c8000ef +00000413 +01c0006f +008907b3 +0007c503 +00140413 +11d000ef +03440a63 +02940863 +02000513 +5a0000ef +00347793 +fc079ee3 +02000513 +590000ef +008907b3 +0007c503 +00140413 +0ed000ef +fd441ae3 +02000513 +574000ef +00048413 +07c00513 +568000ef +ff048493 +00890ab3 +0180006f +00078513 +fff40413 +550000ef +02940663 +04040463 +408a87b3 +0007c783 +02e00513 +fe078713 +0ff7f793 +fce9fce3 +fff40413 +528000ef +fc941ee3 +07c00513 +51c000ef +00a00513 +514000ef +01090913 +02040e63 +00040493 +f31ff06f +07c00513 +4fc000ef +01812403 +01c12083 +01412483 +01012903 +00c12983 +00812a03 +00412a83 +00a00513 +02010113 +4d40006f +01c12083 +01812403 +01412483 +01012903 +00c12983 +00812a03 +00412a83 +02010113 +00008067 +00008067 +08000593 +e9dff06f +ffff27b7 +fd010113 +91478793 +00f12023 +ffff27b7 +91878793 +00f12223 +ffff27b7 +91c78793 +00f12423 +ffff2537 +ffff27b7 +92078793 +92450513 +02912223 +01312e23 +00f12623 +02112623 +02812423 +03212023 +4a0000ef +301024f3 +01f4d793 +00149713 +00179793 +f13029f3 +00075463 +0017e793 +00279793 +01078793 +002787b3 +ff07a503 +ffff2437 +90440413 +468000ef +04900513 +00100913 +0100006f +00144503 +00140413 +02050263 +fbf50793 +00f917b3 +0097f7b3 +fe0784e3 +3ec000ef +00144503 +00140413 +fe0512e3 +ffff2537 +92c50513 +424000ef +00048513 +53c000ef +ffff2537 +93050513 +410000ef +00098513 +528000ef +ffff2437 +9f440513 +3fc000ef +ffff2537 +93c50513 +3f0000ef +01b00513 +768000ef +ffff24b7 +96448513 +3dc000ef +ffff2537 +96850513 +3d0000ef +01b00513 +748000ef +96448513 +3c0000ef +9f440513 +3b8000ef +ffff2537 +97450513 +3ac000ef +ffff2437 +bc840793 +0047a903 +04090e63 +bc840413 +00042483 +01040413 +00048513 +4a8000ef +02d00513 +330000ef +fff48513 +01250533 +494000ef +00900513 +31c000ef +ff842503 +484000ef +00900513 +30c000ef +ffc42503 +354000ef +00a00513 +2fc000ef +00442903 +fa0918e3 +02c12083 +02812403 +02412483 +02012903 +01c12983 +03010113 +00008067 +ff010113 +00a00513 +00112623 +2c8000ef +e25ff0ef +ffff2537 +98450513 +308000ef +00c12083 +01010113 +4f40006f +ffff2537 +ff010113 +9a050513 +00112623 +2e8000ef +00c12083 +ffff2537 +9bc50513 +01010113 +2d40006f +fe010113 +00812c23 +01312623 +ffff2437 +ffff29b7 +9f498513 +b6840413 +01212823 +01412423 +00112e23 +00912a23 +06040913 +2a0000ef +ffff2a37 +00042503 +10057793 +02079663 +00442483 +0ff57513 +02048063 +230000ef +9f8a0513 +278000ef +00048513 +270000ef +9f498513 +268000ef +01040413 +fd2414e3 +01c12083 +01812403 +01412483 +01012903 +00c12983 +00812a03 +02010113 +00008067 +f6dff06f +fc010113 +02112e23 +02912a23 +03212823 +03312623 +03412423 +03512223 +03612023 +01812c23 +01912a23 +01a12823 +01b12623 +02812c23 +01712e23 +f0040537 +00052023 +f0040637 +00062423 +f00406b7 +0006a623 +f0040737 +fff00813 +01072a23 +f00407b7 +0107a823 +f00405b7 +01a00813 +0105a223 +00100593 +00b52023 +ff010cb7 +ffff2c37 +00010d37 +118000ef +00000993 +eb5ff0ef +00000913 +cb5ff0ef +b68c0c13 +ecdff0ef +ffff2b37 +ffff2ab7 +ff010db7 +014c8c93 +fffd0d13 +00600493 +00d00a13 +03a00513 +128000ef +02000513 +120000ef +000ca783 +0017f793 +fe078ce3 +000da503 +000c0713 +00000793 +01a57533 +00072b83 +01070713 +0ffbf693 +04a68863 +00178793 +fe9796e3 +03451a63 +06090863 +00092783 +4007f793 +06078263 +00d00513 +0d0000ef +00c92703 +00892783 +00e989b3 +00098513 +000780e7 +f8dff06f +0b4000ef +a04a8513 +0fc000ef +f7dff06f +00479413 +00d00513 +200bfb93 +008c0933 +094000ef +020b9463 +00c92983 +008c07b3 +0087a783 +00098513 +000780e7 +f4dff06f +00a00513 +070000ef +f41ff06f +00492503 +0b4000ef +9fcb0513 +0ac000ef +52c000ef +00050993 +fc9ff06f +ff010737 +00072223 +ff010637 +00062823 +ff0106b7 +08300793 +00f6a623 +00f00593 +ff0107b7 +00b7a023 +00072223 +00300593 +00b6a623 +00600693 +00d7a423 +00100693 +00d7a423 +00d7a423 +00008067 +00a00793 +02f50463 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +0ff57713 +ff0107b7 +00e7a023 +00008067 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff0107b7 +00d00713 +00e7a023 +fbdff06f +00054683 +02068c63 +ff010737 +00a00593 +ff010637 +01470713 +00d00813 +00150513 +02b68063 +00072783 +0207f793 +fe078ce3 +00d62023 +00054683 +fe0692e3 +00008067 +00072783 +0207f793 +fe078ce3 +01062023 +fd5ff06f +00c55793 +00900713 +00855693 +03078613 +00f77463 +03778613 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff010737 +00f6f793 +00c72023 +00900713 +03778693 +00f76463 +03078693 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff010737 +0ff57513 +00d72023 +00455793 +00900713 +03778693 +00f76463 +03078693 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff0107b7 +00d7a023 +00f57513 +00900793 +03750693 +00a7e463 +03050693 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff0107b7 +00d7a023 +00008067 +01c55793 +00900713 +01055693 +01855613 +03078593 +00f77463 +03778593 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff010737 +00f67793 +00b72023 +00900713 +03778613 +00f76463 +03078613 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff010737 +0ff6f693 +00c72023 +0046d793 +00900713 +03778613 +00f76463 +03078613 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff010737 +00f6f793 +00c72023 +00900713 +03778693 +00f76463 +03078693 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff0107b7 +01051513 +00d7a023 +01055513 +e61ff06f +ff010113 +ff010537 +00112623 +f1dff0ef +ff010737 +ffff2637 +00900693 +a6060613 +00a00513 +ff0105b7 +01470713 +00d00813 +00160613 +0ca68463 +00072783 +0207f793 +fe078ce3 +00d5a023 +00064683 +fe0692e3 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +03000693 +ff010737 +ff0107b7 +ffff2637 +00d7a023 +a6860613 +00900693 +00a00513 +ff0105b7 +01470713 +00d00813 +00160613 +06a68e63 +00072783 +0207f793 +fe078ce3 +00d5a023 +00064683 +fe0692e3 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff010737 +ff0107b7 +00d00693 +00d7a023 +01470713 +00072783 +0207f793 +fe078ce3 +00c12083 +ff0107b7 +00a00713 +00e7a023 +01010113 +00008067 +00072783 +0207f793 +fe078ce3 +0105a023 +f2dff06f +00072783 +0207f793 +fe078ce3 +0105a023 +f79ff06f +00455793 +00900713 +03078693 +00f77463 +03778693 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff0107b7 +00d7a023 +00f57513 +00900793 +03750693 +00a7e463 +03050693 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff0107b7 +00d7a023 +00008067 +00000793 +00000693 +0c050863 +00a00713 +00800893 +00900313 +0080006f +08c37263 +02e57833 +00469693 +00078593 +00178793 +00050613 +00d866b3 +02e55533 +ff1790e3 +00900793 +04c7fc63 +06300813 +02e575b3 +02e557b3 +0ac87463 +00459593 +00100513 +02e7f7b3 +00f5e5b3 +ff010737 +ff010837 +01470713 +00f5f613 +03060613 +00072783 +0207f793 +fe078ce3 +00c82023 +0045d593 +00050663 +00000513 +fddff06f +00700593 +ff010737 +ff010837 +01470713 +fff00513 +00f6f613 +03060613 +00072783 +0207f793 +fe078ce3 +00c82023 +fff58593 +0046d693 +fea590e3 +00008067 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff0107b7 +03000713 +00e7a023 +00008067 +00000513 +f69ff06f +ff010113 +ff010637 +00010f37 +000108b7 +00812623 +00912423 +01212223 +00000513 +00000e13 +ff010837 +01460613 +fff88893 +00900313 +00700e93 +03900293 +fdff0f13 +00500f93 +07f00413 +00800393 +02000913 +00d00493 +00062783 +0017f793 +fe078ce3 +00082783 +0117f6b3 +fd068713 +06e37863 +01e7f5b3 +fbf58593 +06bff263 +08868a63 +08768863 +fc9698e3 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff010737 +ff0107b7 +00d00693 +00d7a023 +01470713 +00072783 +0207f793 +fe078ce3 +00c12403 +ff0107b7 +00a00713 +00e7a023 +00812483 +00412903 +01010113 +00008067 +f7ceece3 +00062583 +0205f593 +fe058ce3 +00d82023 +00d2f863 +01e7f7b3 +fc978793 +00f7f713 +00451513 +001e0e13 +00a70533 +f49ff06f +f40e02e3 +fffe0e13 +00455513 +00062783 +0207f793 +fe078ce3 +00782023 +00062783 +0207f793 +fe078ce3 +01282023 +00062783 +0207f793 +fe078ce3 +00782023 +f09ff06f +ff010837 +01482783 +01480813 +ff010737 +0017f793 +00078a63 +00072783 +00082783 +0017f793 +fe079ae3 +0001f537 +ff0106b7 +40150513 +00900593 +01468693 +c0102673 +c01027f3 +40c787b3 +fef5fce3 +fff50513 +00050c63 +0006a783 +0017f793 +fe0780e3 +00072783 +fb9ff06f +00008067 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff010737 +ff0107b7 +01800693 +00d7a023 +01470713 +00072783 +0207f793 +fe078ce3 +ff010737 +ff0107b7 +01800693 +00d7a023 +01470713 +00072783 +0207f793 +fe078ce3 +ff0107b7 +01800713 +00e7a023 +f35ff06f +fa010113 +05312623 +05412423 +03712e23 +ff010a37 +00001bb7 +00100793 +000109b7 +04812c23 +04912a23 +05212823 +03912a23 +03a12823 +03b12623 +04112e23 +05512223 +05612023 +03812c23 +00050d93 +00058c93 +01900493 +00000d13 +00000913 +00f12623 +04300693 +ff010437 +014a0a13 +fff98993 +021b8b93 +10069063 +000a2783 +00400a93 +00100b13 +0017f793 +00200c13 +18078e63 +00042783 +0137f7b3 +1d578a63 +0efae663 +15678063 +fd8798e3 +40000513 +000a2783 +ffe00713 +00000593 +0017f793 +01a50833 +06078263 +00042783 +0137f6b3 +08074a63 +10a75c63 +0ff6f693 +010ce663 +00ed87b3 +00d78023 +00869693 +00d5c5b3 +00800693 +00f5d793 +00159593 +40f007b3 +01059593 +0177f7b3 +0105d593 +fff68693 +00b7c5b3 +fe0690e3 +00170713 +000a2783 +0017f793 +fa0792e3 +0001f337 +40130313 +00900893 +c01026f3 +c01027f3 +40d787b3 +fef8fce3 +fff30313 +0a030e63 +000a2783 +0017f793 +fe0780e3 +00042783 +0137f6b3 +f6075ae3 +01c10793 +00e787b3 +00d78123 +00170713 +fa9ff06f +000a2783 +0207f793 +fe078ce3 +00d42023 +ef5ff06f +01800713 +eee794e3 +ff010737 +01472783 +01470713 +0017f793 +22078463 +00042783 +01800713 +0137f7b3 +ece792e3 +ff0107b7 +01478793 +0007a703 +02077713 +fe070ce3 +ff0107b7 +00600713 +00e7a023 +d5dff0ef +fff00d13 +0b80006f +08000513 +ec9ff06f +0ee51663 +00879793 +01079913 +01095913 +00170713 +f1dff06f +000a2783 +0207f793 +fe078ce3 +01500793 +00f42023 +d1dff0ef +00000693 +000a2783 +0017f793 +e60796e3 +0002f837 +ff010737 +e0180813 +00900513 +01470713 +c01025f3 +c01027f3 +40b787b3 +fef57ce3 +fff80813 +e20802e3 +00072783 +0017f793 +fe0780e3 +00042783 +0137f7b3 +e3579ae3 +180d0a63 +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff0107b7 +00600713 +00e7a023 +ca1ff0ef +05c12083 +05812403 +05412483 +05012903 +04c12983 +04812a03 +04412a83 +04012b03 +03c12b83 +03812c03 +03412c83 +02c12d83 +000d0513 +03012d03 +06010113 +00008067 +01d14703 +01c14683 +0ff7f793 +fff74713 +0ff77713 +00f96933 +08e69263 +05259a63 +00c12783 +00168713 +08e78e63 +00c12783 +0ef69c63 +ff0107b7 +0ff77713 +00e12623 +00ad8db3 +00ad0d33 +01478793 +0007a703 +02077713 +fe070ce3 +ff0107b7 +00600713 +00e7a023 +01900493 +00000693 +eddff06f +ff0107b7 +01478793 +0007a703 +02077713 +fe070ce3 +ff0107b7 +01500713 +00e7a023 +bcdff0ef +00000693 +eb1ff06f +ff010737 +01470713 +00072783 +0207f793 +fe078ce3 +ff0107b7 +01500713 +00e7a023 +ba1ff0ef +fd5ff06f +fff48493 +06905663 +ff0107b7 +01478793 +0007a703 +02077713 +fe070ce3 +ff0107b7 +00600713 +00e7a023 +00000693 +e59ff06f +0001f837 +40180813 +00900593 +c0102573 +c01027f3 +40a787b3 +fef5fce3 +fff80813 +c80806e3 +00072783 +0017f793 +da0798e3 +fddff06f +ba1ff0ef +ffe00d13 +e91ff06f +b95ff0ef +ffd00d13 +e85ff06f +fe010113 +01412423 +00050a13 +00a00513 +00112e23 +00812c23 +00912a23 +00068413 +00060493 +01212823 +01312623 +00070913 +00058993 +cc4ff0ef +00a00513 +cbcff0ef +000a0513 +d04ff0ef +ffff2537 +a9450513 +cf8ff0ef +00098513 +e10ff0ef +ffff2537 +a9c50513 +ce4ff0ef +34102573 +dfcff0ef +ffff2537 +aa050513 +cd0ff0ef +f1402573 +849ff0ef +ffff2537 +aa850513 +cbcff0ef +30002573 +dd4ff0ef +ffff2537 +ab450513 +ca8ff0ef +34302573 +dc0ff0ef +ffff2537 +abc50513 +c94ff0ef +00090513 +dacff0ef +ffff2537 +ac850513 +c80ff0ef +00040513 +d98ff0ef +00a00513 +c20ff0ef +08048463 +ffff2937 +c1890913 +00000413 +00a00993 +00300a13 +02000513 +c00ff0ef +02000513 +bf8ff0ef +03345533 +03050513 +becff0ef +03347533 +03050513 +be0ff0ef +02000513 +bd8ff0ef +00092503 +c20ff0ef +02000513 +bc8ff0ef +0004a503 +d30ff0ef +00347793 +02000513 +01479463 +00a00513 +bacff0ef +00140413 +02000793 +00490913 +00448493 +f8f41ae3 +01c12083 +01812403 +01412483 +01012903 +00c12983 +00812a03 +02010113 +00008067 +ff010113 +00112623 +342025f3 +c00026f3 +c0202773 +ffff2537 +00000613 +ad450513 +e5dff0ef +8d5fe0ef +00068713 +00060693 +00058613 +00050593 +ffff2537 +ff010113 +ad850513 +00112623 +e35ff0ef +8adfe0ef +0445a783 +ff010113 +00812423 +00112623 +00200713 +0285a503 +00058413 +04e78663 +00800713 +06e78863 +00100693 +fa800713 +02d78463 +02e42423 +341027f3 +00478793 +34179073 +00c12083 +00812403 +00000513 +01010113 +00008067 +0ff57513 +ac8ff0ef +00000713 +fd1ff06f +ff010737 +01472783 +0017f793 +00078c63 +ff0107b7 +0007a703 +01071713 +01075713 +fadff06f +fff00713 +fa5ff06f +a5dfe0ef +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +6f6d580a +206d6564 +65636572 +20657669 +6f727265 +00203a72 +6f6d580a +206d6564 +63637573 +66737365 +796c6c75 +63657220 +65766965 +00002064 +00000000 +74796220 +000a7365 +414d4549 +4c514446 +5442434e +00585650 +00003f3f +00003233 +00003436 +00383231 +3a415349 +00565220 +00005b20 +4d49205d +3a444950 +00000020 +616c500a +726f6674 +74203a6d +5f676e61 +6d697270 +325f7265 +2c6b5f30 +75706320 +206b6c63 +00000000 +007a484d +7973202c +6b6c6373 +00000020 +6f6d654d +6d207972 +0a3a7061 +00000000 +74616c50 +6d726f66 +6e6f6320 +75676966 +69746172 +0a3a6e6f +00000000 +5243530a +616f6c20 +20726564 +322e3176 +7263732d +43525f31 +00000000 +706f430a +67697279 +28207468 +32202943 +2d353130 +31323032 +6e795320 +6f636174 +202e6572 +206c6c41 +68676972 +72207374 +72657365 +2e646576 +0000000a +0000203a +6464610a +00203a72 +75202d20 +6f6e6b6e +63206e77 +616d6d6f +000a646e +646f6d78 +6c206d65 +2064616f +64646140 +00000072 +72617473 +61402074 +00726464 +706d7564 +6d656d20 +00000000 +69646f6d +6d207966 +00006d65 +74616c70 +6d726f66 +666e6920 +0000006f +71726909 +00000020 +52415509 +35363154 +00003035 +004d4354 +6d69544d +00007265 +4f494d4d +00000000 +432d6e4f +20706968 +004d4f52 +61727420 +00002070 +00204020 +61682820 +00237472 +61747320 +20737574 +00000000 +76746d20 +00206c61 +20200a29 +736e6920 +00202074 +20202020 +6c637963 +00002020 +00646142 +686e552b +6c646e61 +656c6261 +00000000 +0020207a +00206172 +00207073 +00207067 +00207074 +00203074 +00203174 +00203274 +00203073 +00203173 +00203061 +00203161 +00203261 +00203361 +00203461 +00203561 +00203661 +00203761 +00203273 +00203373 +00203473 +00203573 +00203673 +00203773 +00203873 +00203973 +00303173 +00313173 +00203374 +00203474 +00203574 +00203674 +00000231 +ffff1a18 +ffff0494 +00000000 +00000267 +ffff1a2c +ffff0400 +00000000 +00000664 +ffff1a38 +ffff068c +00000080 +0000066d +ffff1a44 +ffff0458 +00000004 +00000069 +ffff1a50 +ffff0860 +00000000 +00000120 +00000000 +ffff0948 +00000000 +f0000000 +00001000 +00000000 +ffff1a74 +f0040000 +00001000 +00000000 +ffff1a78 +ff000000 +00100000 +00000000 +ffff1a80 +ffff0000 +00008000 +00000000 +ffff1a88 +00000000 +00000000 +00000000 +00000000 +ffff1ae8 +ffff1aec +ffff1af0 +ffff1af4 +ffff1af8 +ffff1afc +ffff1b00 +ffff1b04 +ffff1b08 +ffff1b0c +ffff1b10 +ffff1b14 +ffff1b18 +ffff1b1c +ffff1b20 +ffff1b24 +ffff1b28 +ffff1b2c +ffff1b30 +ffff1b34 +ffff1b38 +ffff1b3c +ffff1b40 +ffff1b44 +ffff1b48 +ffff1b4c +ffff1b50 +ffff1b54 +ffff1b58 +ffff1b5c +ffff1b60 +ffff1b64 diff --git a/tang20k/scr1/run.tcl b/tang20k/scr1/run.tcl new file mode 100644 index 0000000..30c38cc --- /dev/null +++ b/tang20k/scr1/run.tcl @@ -0,0 +1,72 @@ +set ScriptDir [file normalize [file dirname [info script]]] +open_project tang20k_scr1.gprj +set_device GW2A-LV18PG256C8/I7 -device_version C +set_csr NA +set_option -synthesis_tool gowinsynthesis +set_option -output_base_name tang20k_scr1 +set_option -global_freq default +set_option -top_module tang20k_scr1 +set_option -include_path {"${ScriptDir}/../../../../scr1/src/includes"} +set_option -verilog_std sysv2017 +set_option -vhdl_std vhd1993 +set_option -print_all_synthesis_warning 0 +set_option -disable_io_insertion 0 +set_option -looplimit 2000 +set_option -rw_check_on_ram 0 +set_option -gen_sdf 0 +set_option -gen_io_cst 0 +set_option -vccaux 3.3 +set_option -gen_ibis 0 +set_option -gen_posp 0 +set_option -gen_text_timing_rpt 0 +set_option -gen_verilog_sim_netlist 0 +set_option -gen_vhdl_sim_netlist 0 +set_option -show_init_in_vo 0 +set_option -show_all_warn 0 +set_option -timing_driven 1 +set_option -ireg_in_iob 1 +set_option -oreg_in_iob 1 +set_option -ioreg_in_iob 1 +set_option -replicate_resources 0 +set_option -cst_warn_to_error 1 +set_option -rpt_auto_place_io_info 0 +set_option -correct_hold_violation 1 +set_option -place_option 0 +set_option -route_option 0 +set_option -clock_route_order 0 +set_option -route_maxfan 23 +set_option -use_jtag_as_gpio 0 +set_option -use_sspi_as_gpio 1 +set_option -use_mspi_as_gpio 1 +set_option -use_ready_as_gpio 1 +set_option -use_done_as_gpio 1 +set_option -use_reconfign_as_gpio 0 +set_option -use_mode_as_gpio 0 +set_option -use_i2c_as_gpio 0 +set_option -use_cpu_as_gpio 0 +set_option -power_on_reset_monitor 1 +set_option -bit_format bin +set_option -bit_crc_check 1 +set_option -bit_compress 0 +set_option -bit_encrypt 0 +set_option -bit_encrypt_key 00000000000000000000000000000000 +set_option -bit_security 1 +set_option -bit_incl_bsram_init 1 +set_option -bg_programming off +set_option -hotboot 0 +set_option -i2c_slave_addr 00 +set_option -secure_mode 0 +set_option -loading_rate default +set_option -program_done_bypass 0 +set_option -wakeup_mode 0 +set_option -user_code default +set_option -unused_pin default +set_option -multi_boot 1 +set_option -multiboot_address_width 24 +set_option -multiboot_mode normal +set_option -multiboot_spi_flash_address 00000000 +set_option -mspi_jump 0 +set_option -turn_off_bg 0 +set_option -vccx 3.3 +set_option -vcc 1.0 +run all \ No newline at end of file diff --git a/tang20k/scr1/scr1_arch_custom.svh b/tang20k/scr1/scr1_arch_custom.svh new file mode 100644 index 0000000..e89d06e --- /dev/null +++ b/tang20k/scr1/scr1_arch_custom.svh @@ -0,0 +1,43 @@ +`ifndef SCR1_ARCH_CUSTOM_SVH +`define SCR1_ARCH_CUSTOM_SVH +/// Copyright by Syntacore LLC © 2016, 2017, 2021. See LICENSE for details +/// @file +/// @brief Custom Architecture Parameters File +/// + +// Current FPGA build identificators, can be modified +`define SCR1_PTFM_SOC_ID 32'h21042600 +`define SCR1_PTFM_BLD_ID 32'h22011202 +`define SCR1_PTFM_CORE_CLK_FREQ 32'd27000000 +`define SLAVE_DEVISES_CNT 3 +`define ROM_SIZE 16384 + +//`define SCR1_TRGT_FPGA_XILINX // Uncomment if target platform is Xilinx FPGAs +//`define SCR1_TRGT_FPGA_INTEL // Uncomment if target platform is Intel FPGAs AND ---> +//`define SCR1_TRGT_FPGA_INTEL_MAX10 // ---> Uncomment if target platform is Intel MAX 10 FPGAs +//`define SCR1_TRGT_FPGA_INTEL_ARRIAV // ---> Uncomment if target platform is Intel Arria V FPGAs +`define SCR1_TRGT_FPGA_GOWIN // Uncomment if target platform is Gowin FPGAs + + + + + +// Uncomment to select recommended core architecture configurations +// Default SCR1 FPGA SDK created for RV32IMC_MAX config + +`define SCR1_CFG_RV32IMC_MAX +//`define SCR1_CFG_RV32IC_BASE +// `define SCR1_CFG_RV32EC_MIN + + + +parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_RST_VECTOR = 'hFFFF0000; // Reset vector +parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_MTVEC_BASE = 'hFFFF0300; // MTVEC BASE field reset value + +parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_MASK = 'hFFFF0000; // TCM mask and size +parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_PATTERN = 'hF0000000; // TCM address match pattern + +parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_MASK = 'hFFFFFFE0; // Timer mask (should be 0xFFFFFFE0) +parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_PATTERN = 'hF0040000; // Timer address match pattern + +`endif // SCR1_ARCH_CUSTOM_SVH diff --git a/tang20k/scr1/src/gowin_dpb/gowin_dpb.ipc b/tang20k/scr1/src/gowin_dpb/gowin_dpb.ipc new file mode 100644 index 0000000..f51d44b --- /dev/null +++ b/tang20k/scr1/src/gowin_dpb/gowin_dpb.ipc @@ -0,0 +1,22 @@ +[General] +file=gowin_dpb +ipc_version=4 +module=Gowin_DPB +target_device=gw2a18c-011 +type=ram_dpb +version=1.0 + +[Config] +Area=true +BYTE_SIZE=0 +DEPTH_A=16384 +DEPTH_B=16384 +LANG=0 +READ_A=0 +READ_B=0 +RESET_MODE=true +Speed=false +WIDTH_A=8 +WIDTH_B=8 +WRITE_A=0 +WRITE_B=0 diff --git a/tang20k/scr1/src/gowin_dpb/gowin_dpb.mod b/tang20k/scr1/src/gowin_dpb/gowin_dpb.mod new file mode 100644 index 0000000..c859dd1 --- /dev/null +++ b/tang20k/scr1/src/gowin_dpb/gowin_dpb.mod @@ -0,0 +1,24 @@ +-series GW2A +-device GW2A-18 +-device_version C +-package PBGA256 +-part_number GW2A-LV18PG256C8/I7 + + +-mod_name Gowin_DPB +-file_name gowin_dpb +-path /Users/nikitalukonenko/Desktop/FPGA/fpga-sdk-prj/tang20k/scr1/src/gowin_dpb/ +-type RAM_DP +-file_type vlg +-bram_b true +-dev_type GW2A-18C +-depth_0 16384 +-depth_1 16384 +-width_0 8 +-width_1 8 +-read_mode_0 bypass +-read_mode_1 bypass +-write_mode_0 normal +-write_mode_1 normal +-speed false +-reset_mode sync \ No newline at end of file diff --git a/tang20k/scr1/src/gowin_dpb/gowin_dpb.v b/tang20k/scr1/src/gowin_dpb/gowin_dpb.v new file mode 100644 index 0000000..a5398e4 --- /dev/null +++ b/tang20k/scr1/src/gowin_dpb/gowin_dpb.v @@ -0,0 +1,297 @@ +//Copyright (C)2014-2024 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: IP file +//Tool Version: V1.9.10.03 Education +//Part Number: GW2A-LV18PG256C8/I7 +//Device: GW2A-18 +//Device Version: C +//Created Time: Sun Apr 13 11:25:13 2025 + +module Gowin_DPB (douta, doutb, clka, ocea, cea, reseta, wrea, clkb, oceb, ceb, resetb, wreb, ada, dina, adb, dinb); + +output [7:0] douta; +output [7:0] doutb; +input clka; +input ocea; +input cea; +input reseta; +input wrea; +input clkb; +input oceb; +input ceb; +input resetb; +input wreb; +input [13:0] ada; +input [7:0] dina; +input [13:0] adb; +input [7:0] dinb; + +wire [14:0] dpb_inst_0_douta_w; +wire [14:0] dpb_inst_0_doutb_w; +wire [14:0] dpb_inst_1_douta_w; +wire [14:0] dpb_inst_1_doutb_w; +wire [14:0] dpb_inst_2_douta_w; +wire [14:0] dpb_inst_2_doutb_w; +wire [14:0] dpb_inst_3_douta_w; +wire [14:0] dpb_inst_3_doutb_w; +wire [14:0] dpb_inst_4_douta_w; +wire [14:0] dpb_inst_4_doutb_w; +wire [14:0] dpb_inst_5_douta_w; +wire [14:0] dpb_inst_5_doutb_w; +wire [14:0] dpb_inst_6_douta_w; +wire [14:0] dpb_inst_6_doutb_w; +wire [14:0] dpb_inst_7_douta_w; +wire [14:0] dpb_inst_7_doutb_w; +wire gw_gnd; + +assign gw_gnd = 1'b0; + +DPB dpb_inst_0 ( + .DOA({dpb_inst_0_douta_w[14:0],douta[0]}), + .DOB({dpb_inst_0_doutb_w[14:0],doutb[0]}), + .CLKA(clka), + .OCEA(ocea), + .CEA(cea), + .RESETA(reseta), + .WREA(wrea), + .CLKB(clkb), + .OCEB(oceb), + .CEB(ceb), + .RESETB(resetb), + .WREB(wreb), + .BLKSELA({gw_gnd,gw_gnd,gw_gnd}), + .BLKSELB({gw_gnd,gw_gnd,gw_gnd}), + .ADA(ada[13:0]), + .DIA({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dina[0]}), + .ADB(adb[13:0]), + .DIB({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dinb[0]}) +); + +defparam dpb_inst_0.READ_MODE0 = 1'b0; +defparam dpb_inst_0.READ_MODE1 = 1'b0; +defparam dpb_inst_0.WRITE_MODE0 = 2'b00; +defparam dpb_inst_0.WRITE_MODE1 = 2'b00; +defparam dpb_inst_0.BIT_WIDTH_0 = 1; +defparam dpb_inst_0.BIT_WIDTH_1 = 1; +defparam dpb_inst_0.BLK_SEL_0 = 3'b000; +defparam dpb_inst_0.BLK_SEL_1 = 3'b000; +defparam dpb_inst_0.RESET_MODE = "SYNC"; + +DPB dpb_inst_1 ( + .DOA({dpb_inst_1_douta_w[14:0],douta[1]}), + .DOB({dpb_inst_1_doutb_w[14:0],doutb[1]}), + .CLKA(clka), + .OCEA(ocea), + .CEA(cea), + .RESETA(reseta), + .WREA(wrea), + .CLKB(clkb), + .OCEB(oceb), + .CEB(ceb), + .RESETB(resetb), + .WREB(wreb), + .BLKSELA({gw_gnd,gw_gnd,gw_gnd}), + .BLKSELB({gw_gnd,gw_gnd,gw_gnd}), + .ADA(ada[13:0]), + .DIA({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dina[1]}), + .ADB(adb[13:0]), + .DIB({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dinb[1]}) +); + +defparam dpb_inst_1.READ_MODE0 = 1'b0; +defparam dpb_inst_1.READ_MODE1 = 1'b0; +defparam dpb_inst_1.WRITE_MODE0 = 2'b00; +defparam dpb_inst_1.WRITE_MODE1 = 2'b00; +defparam dpb_inst_1.BIT_WIDTH_0 = 1; +defparam dpb_inst_1.BIT_WIDTH_1 = 1; +defparam dpb_inst_1.BLK_SEL_0 = 3'b000; +defparam dpb_inst_1.BLK_SEL_1 = 3'b000; +defparam dpb_inst_1.RESET_MODE = "SYNC"; + +DPB dpb_inst_2 ( + .DOA({dpb_inst_2_douta_w[14:0],douta[2]}), + .DOB({dpb_inst_2_doutb_w[14:0],doutb[2]}), + .CLKA(clka), + .OCEA(ocea), + .CEA(cea), + .RESETA(reseta), + .WREA(wrea), + .CLKB(clkb), + .OCEB(oceb), + .CEB(ceb), + .RESETB(resetb), + .WREB(wreb), + .BLKSELA({gw_gnd,gw_gnd,gw_gnd}), + .BLKSELB({gw_gnd,gw_gnd,gw_gnd}), + .ADA(ada[13:0]), + .DIA({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dina[2]}), + .ADB(adb[13:0]), + .DIB({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dinb[2]}) +); + +defparam dpb_inst_2.READ_MODE0 = 1'b0; +defparam dpb_inst_2.READ_MODE1 = 1'b0; +defparam dpb_inst_2.WRITE_MODE0 = 2'b00; +defparam dpb_inst_2.WRITE_MODE1 = 2'b00; +defparam dpb_inst_2.BIT_WIDTH_0 = 1; +defparam dpb_inst_2.BIT_WIDTH_1 = 1; +defparam dpb_inst_2.BLK_SEL_0 = 3'b000; +defparam dpb_inst_2.BLK_SEL_1 = 3'b000; +defparam dpb_inst_2.RESET_MODE = "SYNC"; + +DPB dpb_inst_3 ( + .DOA({dpb_inst_3_douta_w[14:0],douta[3]}), + .DOB({dpb_inst_3_doutb_w[14:0],doutb[3]}), + .CLKA(clka), + .OCEA(ocea), + .CEA(cea), + .RESETA(reseta), + .WREA(wrea), + .CLKB(clkb), + .OCEB(oceb), + .CEB(ceb), + .RESETB(resetb), + .WREB(wreb), + .BLKSELA({gw_gnd,gw_gnd,gw_gnd}), + .BLKSELB({gw_gnd,gw_gnd,gw_gnd}), + .ADA(ada[13:0]), + .DIA({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dina[3]}), + .ADB(adb[13:0]), + .DIB({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dinb[3]}) +); + +defparam dpb_inst_3.READ_MODE0 = 1'b0; +defparam dpb_inst_3.READ_MODE1 = 1'b0; +defparam dpb_inst_3.WRITE_MODE0 = 2'b00; +defparam dpb_inst_3.WRITE_MODE1 = 2'b00; +defparam dpb_inst_3.BIT_WIDTH_0 = 1; +defparam dpb_inst_3.BIT_WIDTH_1 = 1; +defparam dpb_inst_3.BLK_SEL_0 = 3'b000; +defparam dpb_inst_3.BLK_SEL_1 = 3'b000; +defparam dpb_inst_3.RESET_MODE = "SYNC"; + +DPB dpb_inst_4 ( + .DOA({dpb_inst_4_douta_w[14:0],douta[4]}), + .DOB({dpb_inst_4_doutb_w[14:0],doutb[4]}), + .CLKA(clka), + .OCEA(ocea), + .CEA(cea), + .RESETA(reseta), + .WREA(wrea), + .CLKB(clkb), + .OCEB(oceb), + .CEB(ceb), + .RESETB(resetb), + .WREB(wreb), + .BLKSELA({gw_gnd,gw_gnd,gw_gnd}), + .BLKSELB({gw_gnd,gw_gnd,gw_gnd}), + .ADA(ada[13:0]), + .DIA({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dina[4]}), + .ADB(adb[13:0]), + .DIB({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dinb[4]}) +); + +defparam dpb_inst_4.READ_MODE0 = 1'b0; +defparam dpb_inst_4.READ_MODE1 = 1'b0; +defparam dpb_inst_4.WRITE_MODE0 = 2'b00; +defparam dpb_inst_4.WRITE_MODE1 = 2'b00; +defparam dpb_inst_4.BIT_WIDTH_0 = 1; +defparam dpb_inst_4.BIT_WIDTH_1 = 1; +defparam dpb_inst_4.BLK_SEL_0 = 3'b000; +defparam dpb_inst_4.BLK_SEL_1 = 3'b000; +defparam dpb_inst_4.RESET_MODE = "SYNC"; + +DPB dpb_inst_5 ( + .DOA({dpb_inst_5_douta_w[14:0],douta[5]}), + .DOB({dpb_inst_5_doutb_w[14:0],doutb[5]}), + .CLKA(clka), + .OCEA(ocea), + .CEA(cea), + .RESETA(reseta), + .WREA(wrea), + .CLKB(clkb), + .OCEB(oceb), + .CEB(ceb), + .RESETB(resetb), + .WREB(wreb), + .BLKSELA({gw_gnd,gw_gnd,gw_gnd}), + .BLKSELB({gw_gnd,gw_gnd,gw_gnd}), + .ADA(ada[13:0]), + .DIA({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dina[5]}), + .ADB(adb[13:0]), + .DIB({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dinb[5]}) +); + +defparam dpb_inst_5.READ_MODE0 = 1'b0; +defparam dpb_inst_5.READ_MODE1 = 1'b0; +defparam dpb_inst_5.WRITE_MODE0 = 2'b00; +defparam dpb_inst_5.WRITE_MODE1 = 2'b00; +defparam dpb_inst_5.BIT_WIDTH_0 = 1; +defparam dpb_inst_5.BIT_WIDTH_1 = 1; +defparam dpb_inst_5.BLK_SEL_0 = 3'b000; +defparam dpb_inst_5.BLK_SEL_1 = 3'b000; +defparam dpb_inst_5.RESET_MODE = "SYNC"; + +DPB dpb_inst_6 ( + .DOA({dpb_inst_6_douta_w[14:0],douta[6]}), + .DOB({dpb_inst_6_doutb_w[14:0],doutb[6]}), + .CLKA(clka), + .OCEA(ocea), + .CEA(cea), + .RESETA(reseta), + .WREA(wrea), + .CLKB(clkb), + .OCEB(oceb), + .CEB(ceb), + .RESETB(resetb), + .WREB(wreb), + .BLKSELA({gw_gnd,gw_gnd,gw_gnd}), + .BLKSELB({gw_gnd,gw_gnd,gw_gnd}), + .ADA(ada[13:0]), + .DIA({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dina[6]}), + .ADB(adb[13:0]), + .DIB({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dinb[6]}) +); + +defparam dpb_inst_6.READ_MODE0 = 1'b0; +defparam dpb_inst_6.READ_MODE1 = 1'b0; +defparam dpb_inst_6.WRITE_MODE0 = 2'b00; +defparam dpb_inst_6.WRITE_MODE1 = 2'b00; +defparam dpb_inst_6.BIT_WIDTH_0 = 1; +defparam dpb_inst_6.BIT_WIDTH_1 = 1; +defparam dpb_inst_6.BLK_SEL_0 = 3'b000; +defparam dpb_inst_6.BLK_SEL_1 = 3'b000; +defparam dpb_inst_6.RESET_MODE = "SYNC"; + +DPB dpb_inst_7 ( + .DOA({dpb_inst_7_douta_w[14:0],douta[7]}), + .DOB({dpb_inst_7_doutb_w[14:0],doutb[7]}), + .CLKA(clka), + .OCEA(ocea), + .CEA(cea), + .RESETA(reseta), + .WREA(wrea), + .CLKB(clkb), + .OCEB(oceb), + .CEB(ceb), + .RESETB(resetb), + .WREB(wreb), + .BLKSELA({gw_gnd,gw_gnd,gw_gnd}), + .BLKSELB({gw_gnd,gw_gnd,gw_gnd}), + .ADA(ada[13:0]), + .DIA({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dina[7]}), + .ADB(adb[13:0]), + .DIB({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,dinb[7]}) +); + +defparam dpb_inst_7.READ_MODE0 = 1'b0; +defparam dpb_inst_7.READ_MODE1 = 1'b0; +defparam dpb_inst_7.WRITE_MODE0 = 2'b00; +defparam dpb_inst_7.WRITE_MODE1 = 2'b00; +defparam dpb_inst_7.BIT_WIDTH_0 = 1; +defparam dpb_inst_7.BIT_WIDTH_1 = 1; +defparam dpb_inst_7.BLK_SEL_0 = 3'b000; +defparam dpb_inst_7.BLK_SEL_1 = 3'b000; +defparam dpb_inst_7.RESET_MODE = "SYNC"; + +endmodule //Gowin_DPB diff --git a/tang20k/scr1/tang20k_scr1.cst b/tang20k/scr1/tang20k_scr1.cst new file mode 100644 index 0000000..85de54f --- /dev/null +++ b/tang20k/scr1/tang20k_scr1.cst @@ -0,0 +1,45 @@ +//Copyright (C)2014-2024 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: Physical Constraints file +//Tool Version: V1.9.10.03 Education +//Part Number: GW2A-LV18PG256C8/I7 +//Device: GW2A-18 +//Device Version: C +//Created Time: Thu 02 20 11:06:07 2025 + +IO_LOC "UART_TX" M11; +IO_PORT "UART_TX" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "LED5" L16; +IO_PORT "LED5" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "LED4" L14; +IO_PORT "LED4" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "LED3" N14; +IO_PORT "LED3" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "LED2" N16; +IO_PORT "LED2" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "JTAG_TDO" M15; +IO_PORT "JTAG_TDO" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "UART_RX" T13; +IO_PORT "UART_RX" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; +IO_LOC "JTAG_TDI" R11; +IO_PORT "JTAG_TDI" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; +IO_LOC "JTAG_TMS" J16; +IO_PORT "JTAG_TMS" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; +IO_LOC "JTAG_TCK" P11; +IO_PORT "JTAG_TCK" IO_TYPE=LVCMOS33 PULL_MODE=DOWN BANK_VCCIO=3.3; +IO_LOC "JTAG_TRST_N" T11; +IO_PORT "JTAG_TRST_N" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; +IO_LOC "RESETn" T10; +IO_PORT "RESETn" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8; +IO_LOC "CLK" H11; +IO_PORT "CLK" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; +IO_LOC "BTN3" D7; +IO_PORT "BTN3" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; +IO_LOC "BTN2" T2; +IO_PORT "BTN2" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; +IO_LOC "BTN4" C7; +IO_PORT "BTN4" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; +IO_LOC "BTN1" T3; +IO_PORT "BTN1" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; +IO_LOC "D_OUT_T12" T12; +IO_PORT "D_OUT_T12" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; diff --git a/tang20k/scr1/tang20k_scr1.gprj b/tang20k/scr1/tang20k_scr1.gprj new file mode 100644 index 0000000..77b1322 --- /dev/null +++ b/tang20k/scr1/tang20k_scr1.gprj @@ -0,0 +1,82 @@ + + + + + 5 + gw2a18c-011 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tang20k/scr1/tang20k_scr1.gprj.user b/tang20k/scr1/tang20k_scr1.gprj.user new file mode 100644 index 0000000..701a2e5 --- /dev/null +++ b/tang20k/scr1/tang20k_scr1.gprj.user @@ -0,0 +1,27 @@ + + + + 1.0 + + + + + + + + + + + + + + + + + + + + + 000000ff00000001fd0000000200000000000001fd0000019efc0200000001fc000000240000019e0000009801000014fa000000010200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006100fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005d00fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000008300ffffff00000003000005a000000120fc0100000001fc00000000000005a0000000b200fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004c00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000b200ffffff000003a20000019e00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000d1ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001d2ffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f006300650073007301000002bfffffffff0000000000000000 + 312e30313130000000ff00000000fd00000002000000000000008300000092fc0200000001fc0000002c000000920000008c00fffffffa000000000200000002fb0000001c0044006f0063006b00650072002e00530075006d006d0061007200790100000000ffffffff0000008c00fffffffb0000001c0044006f0063006b00650072002e004e00650074006c0069007300740000000000ffffffff0000005d00ffffff00000003000002d000000199fc0100000001fc00000000000002d0000001c100fffffffa00000001010000000bfb0000001c0044006f0063006b00650072002e004d0065007300730061006700650100000000ffffffff0000006200fffffffb0000002c0044006f0063006b00650072002e0049002f004f002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004900fffffffb000000380044006f0063006b00650072002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004900fffffffb000000300044006f0063006b00650072002e00470072006f00750070002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004900fffffffb000000360044006f0063006b00650072002e005200650073006f0075007200630065002e005200650073006500720076006100740069006f006e0100000000ffffffff0000004900fffffffb000000380044006f0063006b00650072002e0043006c006f0063006b002e004e00650074002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004900fffffffb000000420044006f0063006b00650072002e00470043004c004b002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004900fffffffb000000420044006f0063006b00650072002e00480043004c004b002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004900fffffffb000000440044006f0063006b00650072002e00470043004c004b0032002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730000000000ffffffff0000004900fffffffb000000460044006f0063006b00650072002e00480043004c004b00350041002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730000000000ffffffff0000004900fffffffb0000002e0044006f0063006b00650072002e0056007200650066002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004900ffffff0000024c0000009200000004000000040000000800000008fc000000010000000200000001000000180054006f006f006c004200610072002e00460069006c00650100000000ffffffff0000000000000000 + diff --git a/tang20k/scr1/tang20k_scr1.sdc b/tang20k/scr1/tang20k_scr1.sdc new file mode 100644 index 0000000..8bea6d0 --- /dev/null +++ b/tang20k/scr1/tang20k_scr1.sdc @@ -0,0 +1,9 @@ +//Copyright (C)2014-2025 GOWIN Semiconductor Corporation. +//All rights reserved. +//File Title: Timing Constraints file +//Tool Version: V1.9.10.03 Education +//Created Time: 2025-02-19 13:51:59 +create_clock -name CLK -period 37.037 -waveform {0 18.518} [get_ports {CLK}] -add +create_clock -name JTAG_TCK -period 1000 -waveform {0 125} [get_ports {JTAG_TCK}] -add +set_input_delay -clock JTAG_TCK 6.6 -add_delay [get_ports {JTAG_TMS JTAG_TDI}] +set_output_delay -clock JTAG_TCK 3.3 -add_delay [get_ports {JTAG_TDO}] diff --git a/tang20k/scr1/tang20k_scr1.sv b/tang20k/scr1/tang20k_scr1.sv new file mode 100644 index 0000000..a1acf40 --- /dev/null +++ b/tang20k/scr1/tang20k_scr1.sv @@ -0,0 +1,389 @@ +/// Copyright by Syntacore LLC © 2016, 2017, 2021. See LICENSE for details +/// @file +/// @brief Top-level entity with SCR1 for Tang Primer 20K board +/// +`define SCR1_ARCH_CUSTOM +`include "scr1_arch_types.svh" +`include "scr1_arch_description.svh" +`include "scr1_ahb.svh" +`include "scr1_memif.svh" +`include "scr1_ipic.svh" + +//User-defined board-specific parameters accessible as memory-mapped GPIO +parameter bit [31:0] FPGA_PRIMER20K_SOC_ID = `SCR1_PTFM_SOC_ID; +parameter bit [31:0] FPGA_PRIMER20K_BLD_ID = `SCR1_PTFM_BLD_ID; +parameter bit [31:0] FPGA_TANG20K_CORE_CLK_FREQ = `SCR1_PTFM_CORE_CLK_FREQ; +parameter SLAVE_DEVISES_CNT = `SLAVE_DEVISES_CNT; +parameter ROM_SIZE = `ROM_SIZE; + +module tang20k_scr1 +( + input logic CLK, + input logic RESETn, + output logic LED0, + output logic LED1, + output logic LED2, + output logic LED3, + output logic LED4, + output logic LED5, + output logic D_OUT_T12, + input logic BTN0, + input logic BTN1, + input logic BTN2, + input logic BTN3, + input logic BTN4, + + `ifdef SCR1_DBG_EN + // input logic JTAG_SRST_N, + input logic JTAG_TRST_N, + input logic JTAG_TCK, + input logic JTAG_TMS, + input logic JTAG_TDI, + output logic JTAG_TDO, + `endif + input logic UART_RX, + output logic UART_TX +); + + + + // == == == == == == == == == == == == == == == == == == == == == == == == == == == = + // Signals / Variables declarations + // == == == == == == == == == == == == == == == == == == == == == == == == == == == = + logic pwrup_rst_n; + logic cpu_clk; + logic extn_rst_in_n; + logic extn_rst_n; + logic [1:0] extn_rst_n_sync; + logic hard_rst_n; + logic [3:0] hard_rst_n_count; + logic soc_rst_n; + logic cpu_rst_n; + `ifdef SCR1_DBG_EN + logic sys_rst_n; + + + logic dmem_ready; + logic dmem_resp; + logic dmem_hsel; + `endif // SCR1_DBG_EN + + // --- SCR1 --------------------------------------------- + logic [3:0] ahb_imem_hprot; + logic [2:0] ahb_imem_hburst; + logic [2:0] ahb_imem_hsize; + logic [1:0] ahb_imem_htrans; + logic [SCR1_AHB_WIDTH-1:0] ahb_imem_haddr; + logic ahb_imem_hready; + logic [SCR1_AHB_WIDTH-1:0] ahb_imem_hrdata; + logic ahb_imem_hresp; + // + logic [3:0] ahb_dmem_hprot; + logic [2:0] ahb_dmem_hburst; + logic [2:0] ahb_dmem_hsize; + logic [1:0] ahb_dmem_htrans; + logic [SCR1_AHB_WIDTH-1:0] ahb_dmem_haddr; + logic ahb_dmem_hwrite; + logic [SCR1_AHB_WIDTH-1:0] ahb_dmem_hwdata; + logic ahb_dmem_hready; + logic [SCR1_AHB_WIDTH-1:0] ahb_dmem_hrdata; + logic ahb_dmem_hresp; + `ifdef SCR1_IPIC_EN + logic [31:0] scr1_irq; + `else + logic scr1_irq; + `endif // SCR1_IPIC_EN + + wire [`SLAVE_DEVISES_CNT-1:0] hreadyout; + wire [`SLAVE_DEVISES_CNT-1:0] hresp; + wire [`SLAVE_DEVISES_CNT-1:0] hsel_; + wire imem_hsel; + logic [SCR1_AHB_WIDTH-1:0] hrdata_0; + logic [SCR1_AHB_WIDTH-1:0] hrdata_1; + + + `ifdef SCR1_DBG_EN + //logic jtag_srst_n; + logic jtag_trst_n; + logic jtag_tck; + logic jtag_tms; + logic jtag_tdi; + logic jtag_tdo; + logic jtag_tdo_en; + `endif // SCR1_DBG_EN + + // --- UART --------------------------------------------- + logic uart_rts_n; // <- UART + logic uart_dtr_n; // <- UART + logic uart_irq; + logic uart_hready; + logic uart_hresp; + logic uart_hsel; + + // --- Heartbeat ---------------------------------------- + logic [31:0] rtc_counter; + logic tick_2Hz; + logic heartbeat; + + logic [31:0] core_frq = FPGA_TANG20K_CORE_CLK_FREQ; + logic ahb_core_frq_sel; + + // == == == == == == == == == == == == == == == == == == == == == == == == == == == = + // Resets + // == == == == == == == == == == == == == == == == == == == == == == == == == == == = + assign extn_rst_in_n = RESETn; + assign cpu_clk = CLK; + assign pwrup_rst_n = RESETn; + + always_ff @(posedge cpu_clk, negedge pwrup_rst_n) + begin + if (~pwrup_rst_n) begin + extn_rst_n_sync <= '0; + end else begin + extn_rst_n_sync[0] <= extn_rst_in_n; + extn_rst_n_sync[1] <= extn_rst_n_sync[0]; + end + end + assign extn_rst_n = extn_rst_n_sync[1]; + + always_ff @(posedge cpu_clk, negedge pwrup_rst_n) + begin + if (~pwrup_rst_n) begin + hard_rst_n <= 1'b0; + hard_rst_n_count <= '0; + end else begin + if (hard_rst_n) begin + // hard_rst_n == 1 - de-asserted + hard_rst_n <= extn_rst_n; + hard_rst_n_count <= '0; + end else begin + // hard_rst_n == 0 - asserted + if (extn_rst_n) begin + if (hard_rst_n_count == '1) begin + // If extn_rst_n = 1 at least 16 clocks, + // de-assert hard_rst_n + hard_rst_n <= 1'b1; + end else begin + hard_rst_n_count <= hard_rst_n_count + 1'b1; + end + end else begin + // If extn_rst_n is asserted within 16-cycles window -> start + // counting from the beginning + hard_rst_n_count <= '0; + end + end + end + end + + `ifdef SCR1_DBG_EN + assign soc_rst_n = sys_rst_n; + assign cpu_rst_n = sys_rst_n; + `else + assign soc_rst_n = hard_rst_n; + assign cpu_rst_n = hard_rst_n; + `endif // SCR1_DBG_EN + + // == == == == == == == == == == == == == == == == == == == == == == == == == == == = + // Heartbeat + // == == == == == == == == == == == == == == == == == == == == == == == == == == == = + always_ff @(posedge cpu_clk, negedge hard_rst_n) + begin + if (~hard_rst_n) begin + rtc_counter <= '0; + tick_2Hz <= 1'b0; + end + else begin + if (rtc_counter == '0) begin + rtc_counter <= (FPGA_TANG20K_CORE_CLK_FREQ/2); + tick_2Hz <= 1'b1; + end + else begin + rtc_counter <= rtc_counter - 1'b1; + tick_2Hz <= 1'b0; + end + end + end + + always_ff @(posedge cpu_clk, negedge hard_rst_n) + begin + if (~hard_rst_n) begin + heartbeat <= 1'b0; + end + else begin + if (tick_2Hz) begin + heartbeat <= ~heartbeat; + end + end + end + // == == == == == == == == == == == == == == == == == == == == == == == == == == == = + // SCR1 Core's Processor Cluster + // == == == == == == == == == == == == == == == == == == == == == == == == == == == = + scr1_top_ahb + i_scr1 ( + // Common + .pwrup_rst_n (pwrup_rst_n), + .rst_n (hard_rst_n), + .cpu_rst_n (cpu_rst_n), + .test_mode (1'b0), + .test_rst_n (1'b1), + .clk (cpu_clk), + .rtc_clk (1'b0), + `ifdef SCR1_DBG_EN + .sys_rst_n_o (sys_rst_n), + .sys_rdc_qlfy_o (), + `endif // SCR1_DBG_EN + + // Fuses + .fuse_mhartid ('0), + `ifdef SCR1_DBG_EN + .fuse_idcode (`SCR1_TAP_IDCODE), + `endif // SCR1_DBG_EN + + // IRQ + `ifdef SCR1_IPIC_EN + .irq_lines (scr1_irq), + `else + .ext_irq (scr1_irq), + `endif//SCR1_IPIC_EN + .soft_irq ('0), + + // Instruction Memory Interface + .imem_hprot (ahb_imem_hprot), + .imem_hburst (ahb_imem_hburst), + .imem_hsize (ahb_imem_hsize), + .imem_htrans (ahb_imem_htrans), + .imem_hmastlock (), + .imem_haddr (ahb_imem_haddr), + .imem_hready (ahb_imem_hready), + .imem_hrdata (ahb_imem_hrdata), + .imem_hresp (ahb_imem_hresp), + // Data Memory Interface + .dmem_hprot (ahb_dmem_hprot), + .dmem_hburst (ahb_dmem_hburst), + .dmem_hsize (ahb_dmem_hsize), + .dmem_htrans (ahb_dmem_htrans), + .dmem_hmastlock (), + .dmem_haddr (ahb_dmem_haddr), + .dmem_hwrite (ahb_dmem_hwrite), + .dmem_hwdata (ahb_dmem_hwdata), + .dmem_hready (ahb_dmem_hready), + .dmem_hrdata (ahb_dmem_hrdata), + .dmem_hresp (ahb_dmem_hresp), + + `ifdef SCR1_DBG_EN + .trst_n (jtag_trst_n), + .tck (jtag_tck), + .tms (jtag_tms), + .tdi (jtag_tdi), + .tdo (jtag_tdo), + .tdo_en (jtag_tdo_en) + `endif + ); + + `ifdef SCR1_IPIC_EN + assign scr1_irq = {31'd0, uart_irq}; + `else + assign scr1_irq = uart_irq; + `endif // SCR1_IPIC_EN + + `ifdef SCR1_DBG_EN + assign jtag_trst_n = JTAG_TRST_N; + assign jtag_tck = JTAG_TCK; + assign jtag_tms = JTAG_TMS; + assign jtag_tdi = JTAG_TDI; + + assign JTAG_TDO = (jtag_tdo_en == 1'b1) ? jtag_tdo : 1'bZ;; + + assign LED2 = jtag_tck; + + `endif + + assign LED0 = ~hard_rst_n; + assign LED1 = heartbeat; + assign D_OUT_T12 = ~heartbeat; + assign LED3 = 1'b1; + assign LED4 = 1'b0; + assign LED5 = 1'b1; + + + assign ahb_core_frq_sel = ahb_dmem_haddr[31:16] == 16'b1111_1111_0000_0000; + assign uart_hsel = ahb_dmem_haddr[31:16] == 16'b1111_1111_0000_0001; //uart + assign dmem_hsel = ahb_dmem_haddr[31:16] == 16'b1111_1111_1111_1111; //rom + assign imem_hsel = ahb_imem_haddr[31:16] == 16'b1111_1111_1111_1111; + + assign hsel_ = {ahb_core_frq_sel, dmem_hsel, uart_hsel}; + assign hreadyout = {1'b1, dmem_ready, uart_hready}; + assign hresp = {1'b0, dmem_resp, uart_hresp}; + + + ahb_lite_uart16550 + i_uart( + .HCLK (cpu_clk), + .HRESETn (soc_rst_n), + .HADDR (ahb_dmem_haddr), + .HBURST (ahb_dmem_hburst), + .HMASTLOCK (1'b1), + .HPROT (ahb_dmem_hprot), + .HSEL (uart_hsel), + .HSIZE (ahb_dmem_hsize), + .HTRANS (ahb_dmem_htrans), + .HWDATA (ahb_dmem_hwdata), + .HWRITE (ahb_dmem_hwrite), + .HREADY_IN (ahb_dmem_hready), + .HRDATA (hrdata_0), + .HREADY (uart_hready), + .HRESP (uart_hresp), + .SI_Endian (1'b1), + + .UART_SRX (UART_RX), + .UART_STX (UART_TX), + .UART_RTS (uart_rts_n), + .UART_CTS (uart_rts_n), + .UART_DTR (uart_dtr_n), + .UART_DSR (uart_dtr_n), + .UART_RI ('1), + .UART_DCD ('1), + + .UART_INT (uart_irq) + ); + + rom_mem + soc_rom_mem( + .clk (cpu_clk), + .rst_n (soc_rst_n), + .dmem_hsel (dmem_hsel), + .dmem_hready_in(ahb_dmem_hready), + + .imem_addr (ahb_imem_haddr[$clog2(ROM_SIZE)+1:2]), + .imem_trans (ahb_imem_htrans), + .imem_hsel (imem_hsel), + + .imem_ready (ahb_imem_hready), + .imem_resp (ahb_imem_hresp), + .imem_data (ahb_imem_hrdata), + + .dmem_addr (ahb_dmem_haddr[$clog2(ROM_SIZE)+1:2]), + .dmem_trans (ahb_dmem_htrans), + + .dmem_ready (dmem_ready), + .dmem_resp (dmem_resp), + .dmem_data (hrdata_1) + ); + + ahb_slave_mux + soc_ahb_slave_mux( + .clk (cpu_clk), + .rst_n (soc_rst_n), + .htrans (ahb_dmem_htrans), + .hsel_s (hsel_), + .rdata_0 (hrdata_0), + .rdata_1 (hrdata_1), + .rdata_2 (core_frq), + .resp (hresp), + .readyout (hreadyout), + + .hrdata (ahb_dmem_hrdata), + .hresp (ahb_dmem_hresp), + .hready (ahb_dmem_hready) + ); + endmodule: tang20k_scr1