Merge pull request #10 from AlexandraKulyatskaya/riscv-specific-direct-access-commands

RISC-V specific direct access commands

Author: en-sc

tcl/syntacore/sc_fpga_lib.tcl

@@ -163,6 +163,60 @@ namespace eval _SC_INTERNALS {
         }
         sc_lib_print "[sc_lib_write_reg mcountinhibit [format "0x%08x" $inhibit_value]]"
     }
+
+    ## aarsize - data size: 2 (32 bits), 3 (64 bits), 4 (128 bits)
+    proc sc_lib_get_aarsize {xlen} {
+        if {$xlen == 32} {
+            return 2
+        }
+        if {$xlen == 64} {
+            return 3
+        }
+        return -code error "invalid MXL value: $xlen"
+    }
+
+    proc sc_lib_riscv_encode_abstarct_command {regno write transfer aarsize cmdtype} {
+        set cmd [expr {($regno & 0xFFFF) |
+            ($write << 16) |
+            ($transfer << 17) |
+            ($aarsize << 20) |
+            ($cmdtype << 24)}]
+        return $cmd
+    }
+
+    proc sc_lib_require_halted_and_check_csr {csr_num} {
+        sc_lib_require_halted
+        if {$csr_num > 4069 || $csr_num < 0} {
+            return -code error "$csr_num is not a valid CSR number"
+        }
+    }
+
+    variable FPGA_LIB_BUSY_DURATION 3
+
+    proc sc_lib_riscv_csr_impl {csr_num value write xlen} {
+        set aarsize [sc_lib_get_aarsize $xlen]
+        set COMMAND_ADDR 0x17
+        riscv dmi_write $COMMAND_ADDR [sc_lib_riscv_encode_abstarct_command $csr_num \
+            $write 1 $aarsize 0]
+
+        set ABSTRACTCS_ADDR 0x16
+        set abstractcs [riscv dmi_read $ABSTRACTCS_ADDR]
+        set start_time [clock seconds]
+
+        while {$abstractcs & 0x1000 != 0} {
+            if {([clock seconds] - $start_time) >= [sc_fpga_get_busy_duration]} {
+                return -code error "Busy bit set after duration time"
+            }
+            set abstractcs [riscv dmi_read $ABSTRACTCS_ADDR]
+        }
+
+        set cmderr [expr {($abstractcs & 0x700) >> 8}]
+        if {$cmderr != 0} {
+            riscv dmi_write $ABSTRACTCS_ADDR 0x700
+            return -code error "problem with abstract command execution, \
+                    error code : $cmderr"
+        }
+    }
 }
 
 proc sc_fpga_ctrl_silence {} {
@@ -301,6 +355,45 @@ proc sc_fpga_info {} {
         ] "\n"]
 }
 
+proc sc_fpga_get_busy_duration {} {
+    return ${::_SC_INTERNALS::FPGA_LIB_BUSY_DURATION}
+}
+
+proc sc_fpga_set_busy_duration {value} {
+    set ::_SC_INTERNALS::FPGA_LIB_BUSY_DURATION $value
+}
+
+proc sc_fpga_riscv_csr_read {csr_num {xlen 64}} {
+    _SC_INTERNALS::sc_lib_require_halted_and_check_csr $csr_num
+
+    _SC_INTERNALS::sc_lib_riscv_csr_impl $csr_num 0 0 $xlen
+    set DATA_0 0x04
+    set DATA_1 0x05
+    if {$xlen == 32} {
+        return [format 0x%.8x [expr {[riscv dmi_read $DATA_0]}]]
+    }
+    if {$xlen == 64} {
+        return [format 0x%.16x [expr {[riscv dmi_read $DATA_0] | [riscv dmi_read $DATA_1]<<32}]]
+    }
+    return -code error "unsupported architecture size"
+}
+
+proc sc_fpga_riscv_csr_write {csr_num value {xlen 64}} {
+    _SC_INTERNALS::sc_lib_require_halted_and_check_csr $csr_num
+
+    set DATA_0 0x04
+    set DATA_1 0x05
+    if {$xlen == 32} {
+        riscv dmi_write $DATA_0 $value
+    }
+    if {$xlen == 64} {
+        riscv dmi_write $DATA_0 [expr {$value & 0xFFFFFFFF}]
+        riscv dmi_write $DATA_1 [expr {$value >> 32}]
+    }
+
+    _SC_INTERNALS::sc_lib_riscv_csr_impl $csr_num $value 1 $xlen
+}
+
 ## @return value of a counter corresponding to the specified event
 ## @param[in] "context" object returned by sc_experimental_pmu_setup
 ## @param[in] name of PMU event