From 00f4386d536379fefe71c90803c8839f2c861336 Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Wed, 5 Mar 2025 16:31:20 +0300 Subject: [PATCH 1/2] [syntacore] tools/syntacore: add N extension registers to IDE cloack * `N` extension is removed from RISC-V priveleged spec from 1.11 (covers `sedeleg`, `sideleg`). * While I didn't find the exact spec version where `uscratchcsw`, `uscratchcswl` were removed, it seems like there are also a part of the deprecated N extension (from the simularity to `uscratch`). Change-Id: Ife9db04be0644083633a902e0b1513780c9eb0d2 Signed-off-by: Evgeniy Naydanov --- tools/syntacore/ide_cloak.tcl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/syntacore/ide_cloak.tcl b/tools/syntacore/ide_cloak.tcl index 5f3f410539..b6d7a5a13b 100755 --- a/tools/syntacore/ide_cloak.tcl +++ b/tools/syntacore/ide_cloak.tcl @@ -105,6 +105,10 @@ proc generateIdeCloak { } { vtype \ vxrm \ vxsat \ + sedeleg \ + sideleg \ + uscratchcsw \ + uscratchcswl \ ] set CSRS_TO_HIDE [generateListOfCloakedAddresses $IDE_CSRS] From 72b7cd9b0588ef6b78af73b87463b7397a9bb94c Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Wed, 5 Mar 2025 16:31:20 +0300 Subject: [PATCH 2/2] Revert "[quick fix] remove deprecated registers" This reverts commit 3d7902303a5fd2e504adc13e60ee6bf9906c310c ("[quick fix] remove deprecated registers"). The reasoning for revert is as follows: 1. This is a change to an auto-generated file. 2. To adjust existence of registers `riscv_reg_impl_gdb_regno_exist()` should be used instead. Change-Id: Ib5f569a64f453f85294de4476e5826c1c8620017 Signed-off-by: Evgeniy Naydanov --- src/target/riscv/encoding.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/target/riscv/encoding.h b/src/target/riscv/encoding.h index 5f05015ea7..3ac537c377 100644 --- a/src/target/riscv/encoding.h +++ b/src/target/riscv/encoding.h @@ -2831,6 +2831,8 @@ #define CSR_VTYPE 0xc21 #define CSR_VLENB 0xc22 #define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 @@ -2892,6 +2894,8 @@ #define CSR_UTVT 0x7 #define CSR_UNXTI 0x45 #define CSR_UINTSTATUS 0x46 +#define CSR_USCRATCHCSW 0x48 +#define CSR_USCRATCHCSWL 0x49 #define CSR_STVT 0x107 #define CSR_SNXTI 0x145 #define CSR_SINTSTATUS 0x146 @@ -4584,6 +4588,8 @@ DECLARE_CSR(vl, CSR_VL) DECLARE_CSR(vtype, CSR_VTYPE) DECLARE_CSR(vlenb, CSR_VLENB) DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sedeleg, CSR_SEDELEG) +DECLARE_CSR(sideleg, CSR_SIDELEG) DECLARE_CSR(sie, CSR_SIE) DECLARE_CSR(stvec, CSR_STVEC) DECLARE_CSR(scounteren, CSR_SCOUNTEREN) @@ -4645,6 +4651,8 @@ DECLARE_CSR(stopi, CSR_STOPI) DECLARE_CSR(utvt, CSR_UTVT) DECLARE_CSR(unxti, CSR_UNXTI) DECLARE_CSR(uintstatus, CSR_UINTSTATUS) +DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW) +DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL) DECLARE_CSR(stvt, CSR_STVT) DECLARE_CSR(snxti, CSR_SNXTI) DECLARE_CSR(sintstatus, CSR_SINTSTATUS)