mb/system76/tgl-u: darp7: Re-add CPU PCIe RTD3

Change-Id: I2df115c323a4fa50ffac191461060df9059381f7
Signed-off-by: Tim Crawford <[email protected]>

Author: crawfxrd

src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb

@@ -21,6 +21,12 @@ chip soc/intel/tigerlake
 			# PCIe PEG0 x4, Clock 0 (SSD1)
 			register "PcieClkSrcUsage[0]" = "0x40"
 			register "PcieClkSrcClkReq[0]" = "0"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
+				register "srcclk_pin" = "0" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref north_xhci on # J_TYPEC2
 			register "UsbTcPortEn" = "1"