diff --git a/coreboot b/coreboot index 05dda8aa..a91d2c7f 160000 --- a/coreboot +++ b/coreboot @@ -1 +1 @@ -Subproject commit 05dda8aa05f988f3d38720b46804c9cf2590855a +Subproject commit a91d2c7f79fc0d14b5818c47a070be670c63c3a3 diff --git a/ec b/ec index 39f1a9e2..68d90e0d 160000 --- a/ec +++ b/ec @@ -1 +1 @@ -Subproject commit 39f1a9e24f87e9c3a729692221371631d6832c42 +Subproject commit 68d90e0df6ee9231221afb13b9365b492a65a1b9 diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Fbm.bin b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Fbm.bin new file mode 100644 index 00000000..2717b57a Binary files /dev/null and b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Fbm.bin differ diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Fsp.bsf b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Fsp.bsf new file mode 100644 index 00000000..6d81a2bc --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Fsp.bsf @@ -0,0 +1,6294 @@ +/** @file + + Boot Setting File for Platform Configuration. + + Copyright (c) 2026, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + This file is automatically generated. Please do NOT modify !!! + +**/ + + + +GlobalDataDef + SKUID = 0, "DEFAULT" +EndGlobalData + + +StructDef + + Find "PTLUPD_T" + $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02 + Skip 87 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartNumber 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartMode 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartPowerGating 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartBaudRate 4 bytes $_DEFAULT_ = 115200 + $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xE0000000 + $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength 4 bytes $_DEFAULT_ = 0x10000000 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartParity 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartDataBits 1 bytes $_DEFAULT_ = 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartStopBits 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartAutoFlow 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartRxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartTxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartRtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartCtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUartDebugMmioBase 4 bytes $_DEFAULT_ = 0xFE02C000 + $gSiPkgTokenSpaceGuid_PcdLpssUartDebugPciCfgBase 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndNumber 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndMode 1 bytes $_DEFAULT_ = 0x02 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndBaudRate 4 bytes $_DEFAULT_ = 115200 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndParity 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndDataBits 1 bytes $_DEFAULT_ = 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndStopBits 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndAutoFlow 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndRxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndTxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndRtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndCtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndMmioBase 4 bytes $_DEFAULT_ = 0xFE030000 + $gSiPkgTokenSpaceGuid_PcdLpssUart2ndPciCfgBase 4 bytes $_DEFAULT_ = 0x0 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsPolarity 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsEnable 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiDefaultCsOutput 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsState 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiNumber 1 bytes $_DEFAULT_ = 0x0 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMmioBase 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiClkPinMux 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMisoPinMux 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMosiPinMux 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoI2cMmioBase 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoI2cSdaPin 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoI2cSclPin 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoI2cPadsTerm 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoI2cNumber 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_EnableSecondaryDataCache 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ProgramWriteBackCodeCache 1 bytes $_DEFAULT_ = 0x01 + + Find "PTLUPD_M" + $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02 + Skip 87 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow 1 bytes $_DEFAULT_ = 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugTxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugCtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_DciEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DciDbcMode 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_DciClkEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_KeepEarlyTrace 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MemMapOverlapCheckSupport 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxEqTap0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxEqTap1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyDqTcoComp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxCtleR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxCtleC 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize 8 bytes $_DEFAULT_ = 0x15000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen 2 bytes $_DEFAULT_ = 0x200 + $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxCtleRcmn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxCtleEq 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxCtleTailCtl 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5Dfeq 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5PdDrvStr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5SocOdt 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr000 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr001 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr010 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr011 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr020 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr021 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr030 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr031 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr100 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr101 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr110 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr111 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr120 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr121 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr130 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr131 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_RcompResistor 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_RcompTarget 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch0 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch1 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch2 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch3 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch0 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch1 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch2 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch3 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch0 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch1 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch2 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch3 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch0 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch1 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch2 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch3 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_LowerBasicMemTestSize 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EccGranularity32BEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EccCorrectionMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CaVrefHigh 1 bytes $_DEFAULT_ = 0x1D + $gPlatformFspPkgTokenSpaceGuid_CaVrefLow 1 bytes $_DEFAULT_ = 0x45 + $gPlatformFspPkgTokenSpaceGuid_CsVrefHigh 1 bytes $_DEFAULT_ = 0x1D + $gPlatformFspPkgTokenSpaceGuid_CsVrefLow 1 bytes $_DEFAULT_ = 0x45 + $gPlatformFspPkgTokenSpaceGuid_DFETap1StepSize 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DFETap2StepSize 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Vdd2Mv 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRAS 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRCDtRP 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tREFI 4 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tCL 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tCWL 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tFAW 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRFC 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRRD 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRTP 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWR 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWTR 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWTR_S 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWTR_L 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tCCD_L 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRD_S 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRD_L 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRFC4 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRFC2 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRFCpb 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tCCD_L_WR 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_EnPeriodicComp 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_LpMode4 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_LpMode 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_OpportunisticRead 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Disable2CycleBypass 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_OCSafeMode 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VrefCtlOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SmramMask 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_RmtPerTask 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TrainTrace 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjCount 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaGvWpMask 1 bytes $_DEFAULT_ = 0x0F + $gPlatformFspPkgTokenSpaceGuid_SaGvGear 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaGvFreq 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_GearRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch3 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch3 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MsHashOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VddVoltage 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_Ratio 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RXVREFPERBIT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TXDQSDCC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RXDQSDCC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ChHashOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VoltageReadout 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DQSRF 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDDQSODTT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PRETRAIN 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DUNITC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_FUNCDCCCLK 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQS 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_DCCLP5WCKDCA 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DQDQSSWZ 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DCCLP5READDCA 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQ 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SubChHashOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Ddr5AutoPrechargeEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Lp5SplitACTEnable 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_CccHalfFrequency 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DIMMNTODT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RXUNMATCHEDCAL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PPR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprTestType 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprRunOnce 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PprRunAtFastboot 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprRepairType 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprErrorInjection 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprRepairController 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairChannel 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairDimm 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairRank 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MsHashInterleaveBit 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_MsHashMask 2 bytes $_DEFAULT_ = 0x2090 + $gPlatformFspPkgTokenSpaceGuid_PprRepairRow 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairPhysicalAddrLow 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairPhysicalAddrHigh 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairBankGroup 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_LVRAUTOTRIM 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_OPTIMIZECOMP 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_WRTRETRAIN 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PHASECLKCAL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TLINECLKCAL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DCCPISERIALCAL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDDQODTT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDCTLET 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EMPHASIS 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RXDQSVOCC 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NModeSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_LpddrRttWr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RetrainOnFastFail 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_LpddrRttCa 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_WRTDIMMDFE 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DDR5ODTTIMING 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_HobBufferSize 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ECT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SOT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDMPRT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RCVET 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_JWRL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EWRTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ERDTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_UNMATCHEDWRTC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRTC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRVC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDTC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DIMMODTT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DIMMRONT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_WRDSEQT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDEQT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRTC2D 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RDTC2D 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_WRVC2D 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RDVC2D 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CMDVC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_LCT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RTL 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TAT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RMTEVENODD 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ALIASCHK 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RCVENC1D 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RMC 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EccSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DLLDCC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DLLBWSEL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Ibecc 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccParity 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MsHashEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionEnable 8 bytes $_DEFAULT_ = 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5PreEmpDn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionBase 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionMask 16 bytes $_DEFAULT_ = 0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F + $gPlatformFspPkgTokenSpaceGuid_RemapEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RankInterleave 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ChHashEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WCKPADDCCCAL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DCCPICODELUT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDVC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TXTCO 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CLKTCO 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CMDSR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DIMMODTCA 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RDVREFDC 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RMTBIT 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_REFPI 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VCCCLKFF 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DATAPILIN 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DDR5XTALK 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RetrainToWorkingChannel 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RowPressEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DBI 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IsDdr5MR7WicaSupported 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_WREQT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ChHashMask 2 bytes $_DEFAULT_ = 0x830 + $gPlatformFspPkgTokenSpaceGuid_CccPinsInterleaved 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AllowOppRefBelowWriteThrehold 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_WriteThreshold 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_McRefreshRate 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RefreshWm 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerDownMode 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SafeModeOverride 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5PreEmpUp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjAddrBase 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DdrSafeMode 4 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_McSafeMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CleanMemory 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RetryCount 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MrcPprStatus 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TsegMemoryTestStatus 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRecoveryStatusEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SafeLoadingBiosEnableState 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MrcBdatTestType 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MrcBdatEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DisableMrcRetraining 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DdrOneDpc 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_VddqVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VccIogVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VccClkVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5WckDcaWr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MarginLimitL2 2 bytes $_DEFAULT_ = 0x64 + $gPlatformFspPkgTokenSpaceGuid_ExtendedBankHashing 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DrfmBrc 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_Lp5CccConfig 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_CmdMirror 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DvfsqEnabled 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DvfscEnabled 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DCCDDR5READDCA 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PprRunWCHMATS8 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprRunRetention 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprRunXMarch 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprRunXMarchG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprRunYMarchShort 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprRunYMarchLong 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprRunMmrw 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprTestDisabled 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprEntryInfo 16 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprEntryAddress 16 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_RDTCIDLE 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PprRetryLimit 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_Use1p5ReadPostamble 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IsWckIdleExitEnabled 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Lp5SafeSpeed 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ForceInternalClkOn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DIMMRXOFFSET 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_FlexibleAnalogSettings 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ForceWRDSEQT2400 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5WckDcaRd 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5RttNT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5DfeTap1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5DfeTap2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5RttWr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5RttNomWr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5RttNomRd 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5RonUp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5RonDn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyOvrdMask 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NnFlexDramOvrdMask 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MrcPreMemRsvd 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_TxtImplemented 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PcieResizableBarSupport 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_BdatTestType 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect 2 bytes $_DEFAULT_ = 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHdaEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchHdaSdiEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClkAPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicDataPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspEnable 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaDiscBtOffEnabled 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaDiscBtOffSspLink 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspSclkPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspSfmrPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspTxdPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspRxdPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndwEnable 5 bytes $_DEFAULT_ = 0x01, 0x00, 0x00, 0x00, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchHdAudioSndwMultilaneEnable 2 bytes $_DEFAULT_ = 0x00, 0x02 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkMultilaneClkPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkMultilaneData0PinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkMultilaneData1PinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkMultilaneData2PinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkMultilaneData3PinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdAudioSndwMultilaneSndwInterface 2 bytes $_DEFAULT_ = 0x02,0x03 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_ResetWaitTimer 2 bytes $_DEFAULT_ = 0x258 + $gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaTestLowFreqLinkClkSrc 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaSubSystemIds 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwClockSourceSelect 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage 18 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq 18 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x00, 0x01 + Skip 14 bytes + $gPlatformFspPkgTokenSpaceGuid_PcieClkReqGpioMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask 4 bytes $_DEFAULT_ = 0x00FFFFFF + $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x32 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMmioBase 4 bytes $_DEFAULT_ = 0xFE02C000 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate 4 bytes $_DEFAULT_ = 115200 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits 1 bytes $_DEFAULT_ = 0x8 + $gPlatformFspPkgTokenSpaceGuid_ImguClkOutEn 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_HeciCommunication 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_HeciCommunication3 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort 2 bytes $_DEFAULT_ = 0x80 + $gPlatformFspPkgTokenSpaceGuid_I2cPostCodeEnable 1 bytes $_DEFAULT_ = 0x0 + Skip 5 bytes + $gPlatformFspPkgTokenSpaceGuid_FspmValidationPtr 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ExtendedBiosDecodeRange 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeBase 4 bytes $_DEFAULT_ = 0xF8000000 + $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeLimit 4 bytes $_DEFAULT_ = 0xF9FFFFFF + $gPlatformFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0 + $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 5 bytes + $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaOcSupport 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VfPointCount 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcessVmaxLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CorePllCurrentRefTuningOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingPllCurrentRefTuningOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IaAtomPllCurrentRefTuningOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreMinRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NegativeTemperatureReporting 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcorePowerDensityThrottle 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EcorePowerDensityThrottle 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_OcSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_UnderVoltProtection 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Lfsr0Mask 1 bytes $_DEFAULT_ = 0xB + $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Lfsr1Mask 1 bytes $_DEFAULT_ = 0xB + $gPlatformFspPkgTokenSpaceGuid_DramRfmMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TargetedRowRefreshMode 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOffset 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOffsetPrefix 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageMode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOverride 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfConfigScope 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOffset 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOffsetPrefix 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreRatioOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageMode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOverride 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreRatio 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomClusterRatio 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PvdRatioThreshold 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PvdMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FllOverclockMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SocDieSscEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreOpPointReportingEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuBclkOcFrequency 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SocBclkOcFrequency 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_DisablePerCoreMask 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GranularRatioOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Avx2VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_OcPreMemRsvd 5 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshEnable 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2800 + $gPlatformFspPkgTokenSpaceGuid_BiosGuard 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_Txt 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ResetAux 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TseEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TdxEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GenerateNewTmeKey 1 bytes $_DEFAULT_ = 0x00 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_TmeExcludeBase 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TmeExcludeSize 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TdxActmModuleAddr 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_TdxActmModuleSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TdxSeamldrSvn 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_BootMaxFrequency 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_BistOnReset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ReduceXecores 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VmxEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_FClkFrequency 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TmeEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CrashLogGprs 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_OcLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuRatio 1 bytes $_DEFAULT_ = 0x1C + $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_ActiveSmallCoreCount 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_ActiveLpAtomCoreCount 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_DfdEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PrmrrSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TsegSize 4 bytes $_DEFAULT_ = 0x00400000 + $gPlatformFspPkgTokenSpaceGuid_SmmRelocationEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PlatformAtxTelemetryUnit 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CustomPowerLimit1 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CustomPowerLimit2 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VsysMax 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ThETAIbattEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_IsysCurrentLimitL1 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_IsysCurrentL1Tau 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_IsysCurrentLimitL2 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IsysCurrentLimitL1Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IsysCurrentLimitL2Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Boost 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SkinTargetTemp 3 bytes $_DEFAULT_ = 0x0, 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_SkinTempControlEnable 3 bytes $_DEFAULT_ = 0x0, 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_SkinControlLoopGain 3 bytes $_DEFAULT_ = 0x0,0x0,0x0 + $gPlatformFspPkgTokenSpaceGuid_SkinTempOverrideEnable 3 bytes $_DEFAULT_ = 0x0, 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_SkinMinPerformanceLevel 3 bytes $_DEFAULT_ = 0x0,0x0,0x0 + $gPlatformFspPkgTokenSpaceGuid_SkinTempOverride 3 bytes $_DEFAULT_ = 0x0,0x0,0x0 + $gPlatformFspPkgTokenSpaceGuid_SkinTempControl 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_AcDcPowerState 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CustomTurboActivationRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CustomPowerLimit1Time 1 bytes $_DEFAULT_ = 0x50 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PowerLimit1 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit4 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ApplyConfigTdp 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DualTauBoost 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit2 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ResponseMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize 4 bytes $_DEFAULT_ = 0x50000 + $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_ApStartupBase 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TgaSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RfiMitigation 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysSlope 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPmax 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TdcCurrentLimit 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_AcLoadline 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_DcLoadline 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_Ps1Threshold 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_Ps2Threshold 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_Ps3Threshold 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_ImonOffset 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IccMax 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ImonSlope 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_Ps3Enable 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_Ps4Enable 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_TdcEnable 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_TdcLock 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisable 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SlowSlewRate 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PsysOffset 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_TdcMode 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_FivrSpectrumEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DlvrSpreadSpectrumPercentage 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DlvrRfiEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PcoreHysteresisWindow 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EcoreHysteresisWindow 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VccsaShutdown 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DlvrRfiFrequency 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DlvrPhaseSsc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_EnableVsysCritical 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchMantissa 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchExponent 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchMantissa 1 bytes $_DEFAULT_ = 0x0D + $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchExponent 1 bytes $_DEFAULT_ = 0x02 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_IccLimit 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableFastVmode 6 bytes $_DEFAULT_ = 0x1, 0x1, 0x1, 0x0, 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_CepEnable 6 bytes $_DEFAULT_ = 0x01, 0x00, 0x01, 0x01, 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_VsysFullScale 4 bytes $_DEFAULT_ = 0x5DC0 + $gPlatformFspPkgTokenSpaceGuid_VsysCriticalThreshold 4 bytes $_DEFAULT_ = 0x1770 + $gPlatformFspPkgTokenSpaceGuid_PsysFullScale 4 bytes $_DEFAULT_ = 0x30D40 + $gPlatformFspPkgTokenSpaceGuid_PsysCriticalThreshold 4 bytes $_DEFAULT_ = 0x1D4C0 + $gPlatformFspPkgTokenSpaceGuid_CpuPmVrRsvd 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IoeDebugEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmodeClkEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPort80Route 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GpioOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcPrivacyConsent 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTestDmiMeUmaRootSpaceCheck 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_DmaBufferSize 4 bytes $_DEFAULT_ = 0x0600000 + $gPlatformFspPkgTokenSpaceGuid_PreBootDmaMask 1 bytes $_DEFAULT_ = 0x2 + $gPlatformFspPkgTokenSpaceGuid_DmaControlGuarantee 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_VtdDisable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VtdCapabilityControl 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress 36 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_MchBar 8 bytes $_DEFAULT_ = 0xFEDC0000 + $gPlatformFspPkgTokenSpaceGuid_RegBar 8 bytes $_DEFAULT_ = 0xF0000000 + $gPlatformFspPkgTokenSpaceGuid_MmioSize 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment 2 bytes $_DEFAULT_ = 0x67 + $gPlatformFspPkgTokenSpaceGuid_ApicLocalAddress 4 bytes $_DEFAULT_ = 0xFEE00000 + $gPlatformFspPkgTokenSpaceGuid_NvmeHcPeiMmioBase 4 bytes $_DEFAULT_ = 0xB1000000 + $gPlatformFspPkgTokenSpaceGuid_NvmeHcPeiMmioLimit 4 bytes $_DEFAULT_ = 0xB2000000 + $gPlatformFspPkgTokenSpaceGuid_AhciPeiMmioBase 4 bytes $_DEFAULT_ = 0x90000000 + $gPlatformFspPkgTokenSpaceGuid_AhciPeiMmioLimit 4 bytes $_DEFAULT_ = 0x91000000 + $gPlatformFspPkgTokenSpaceGuid_EcExtraIoBase 2 bytes $_DEFAULT_ = 0x6A0 + $gPlatformFspPkgTokenSpaceGuid_SioBaseAddress 2 bytes $_DEFAULT_ = 0x0680 + $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBar 4 bytes $_DEFAULT_ = 0xA0000000 + $gPlatformFspPkgTokenSpaceGuid_SafBar 8 bytes $_DEFAULT_ = 0xFA000000 + $gPlatformFspPkgTokenSpaceGuid_EnableAbove4GBMmio 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_StreamTracerMode 4 bytes $_DEFAULT_ = 0x00 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogDevice 4 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_StreamTracerBase 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Bar 4 bytes $_DEFAULT_ = 0xA2000000 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Bar 4 bytes $_DEFAULT_ = 0xA4000000 + $gPlatformFspPkgTokenSpaceGuid_SiSkipOverrideBootModeWhenFwUpdate 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_StaticContentSizeAt4Gb 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PlatformDebugOption 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CmosTxtOffset 1 bytes $_DEFAULT_ = 0x2A + $gPlatformFspPkgTokenSpaceGuid_SiPreMemRsvd 13 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_HgSubSystemId 2 bytes $_DEFAULT_ = 0x2112 + $gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortAHpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort1Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort2Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort3Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort4Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortADdc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort1Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort2Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort3Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort4Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride 1 bytes $_DEFAULT_ = 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_LMemBar 8 bytes $_DEFAULT_ = 0xB0000000 + $gPlatformFspPkgTokenSpaceGuid_GttMmAdr 8 bytes $_DEFAULT_ = 0xAF000000 + $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MemoryBandwidthCompression 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_IGpuGsm2Size 1 bytes $_DEFAULT_ = 0xFF + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_VbtSize 4 bytes $_DEFAULT_ = 0x00000000 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_VbtPtr 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_VgaMessage 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LidStatus 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VgaInitControl 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight 2 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth 2 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LogoXPosition 2 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_VgaGraphicsMode12ImagePtr 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LogoYPosition 2 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TcssXhciEn 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_IomUsbCDpConfig 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_TcssPort0 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_TcssPort1 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_TcssPort2 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_TcssPort3 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TcssPlatConf 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IomTypeCPortPadCfg 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_TcssAuxOri 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_TcssHslOri 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_CnviDdrRfim 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg0Size 2 bytes $_DEFAULT_ = 0x0E + $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg1Size 2 bytes $_DEFAULT_ = 0x0E + $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 2 bytes $_DEFAULT_ = 0x2 + $gPlatformFspPkgTokenSpaceGuid_InternalGraphics 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_AsyncOdtDis 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_WeaklockEn 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_RxDqsDelayCompEn 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_MrcFailureOnUnsupportedDimm 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ForceSingleRank 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DynamicMemoryBoost 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryFrequency 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SrefCfgIdleTmr 2 bytes $_DEFAULT_ = 0x640 + $gPlatformFspPkgTokenSpaceGuid_MCREGOFFSET 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CAVrefCtlOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ClkPiCodeOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RcvEnOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RxDqsOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TxDqOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TxDqsOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VrefOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CntrlrMask 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ChMask 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRSG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRDG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRDR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRDD 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWRSG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWRDG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWRDR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWRDD 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWWSG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWWDG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWWDR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWWDD 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRWSG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRWDG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRWDR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRWDD 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Interpreter 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IoOdtMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerBankRefresh 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_MimicWcDisaplayInIpq 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_FakeSagv 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_DprLock 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_BoardStackUp 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PprForceRepair 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairBank 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_BoardTopology 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_SubChHashInterleaveBit 1 bytes $_DEFAULT_ = 0x03 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SubChHashMask 2 bytes $_DEFAULT_ = 0x838 + $gPlatformFspPkgTokenSpaceGuid_ForceCkdBypass 1 bytes $_DEFAULT_ = 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_DisableZq 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_ReplicateSagv 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_AdjustWckMode 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_TelemetryControl 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_SpineAndPhclkGateControl 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_SpineGatePerLpmode 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_PhclkGatePerLpmode 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_DisableSwitchDfiToMc 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SmbusPostCodeEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SmbusPostCodeAddress 1 bytes $_DEFAULT_ = 0x38 + $gPlatformFspPkgTokenSpaceGuid_SmbusPostCodeCommand 1 bytes $_DEFAULT_ = 0x20 + $gPlatformFspPkgTokenSpaceGuid_ChannelToCkdQckMapping 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PhyClockToCkdDimm 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CkdAddressTable 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SingleVdd2Rail 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_Vdd2HVoltage 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Vdd1Voltage 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Vdd2LVoltage 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VddqVoltage 2 bytes $_DEFAULT_ = 0x00 + Skip 6 bytes + $gPlatformFspPkgTokenSpaceGuid_GraphicsMode12FontPtr 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_MrcErrorKeyValueTablePtr 8 bytes $_DEFAULT_ = 0x0000000000000000 + + Find "PTLUPD_S" + $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02 + Skip 55 bytes + $gPlatformFspPkgTokenSpaceGuid_BgpdtHash 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF + $gPlatformFspPkgTokenSpaceGuid_EcProvisionEav 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF + $gPlatformFspPkgTokenSpaceGuid_EcBiosGuardCmdLock 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF + $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeHostDeviceEnabled 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchEspiHostC10ReportEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchEspiPmHAE 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchEspiHideNonFatalErrors 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchEspiNmiEnableCs1 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_CpuBistData 8 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi 8 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogEnable 1 bytes $_DEFAULT_ = 0x1 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_StreamTracerMode 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TxtEnable 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PpinSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AesEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_AvxDisable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_X2ApicEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_Eist 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TStates 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableAllThermalFunctions 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Cx 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CStatePreWake 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TimedMwait 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_ForcePrDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VrAlertDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PowerFloorPcieGenDowngrade 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_StateRatio 40 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MaxRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_BootFrequency 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableFastMsrHwpReq 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitRatio 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitNumCore 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitRatio 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitNumCore 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_RaceToHalt 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableRp 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Hwp 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoPerCorePstate 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoEppGrouping 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableDynamicEfficiencyControl 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_HwpLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PowerFloorManagement 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PowerFloorDisplayDisconnect 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemSize 1 bytes $_DEFAULT_ = 0xff + $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceBspOnly 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceTimingPacket 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounter 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_UfsEnable 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_UfsInlineEncryption 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_UfsDeviceConnected 2 bytes $_DEFAULT_ = 0x1, 0x1 + $gPlatformFspPkgTokenSpaceGuid_ITbtPcieTunnelingForUsb4 1 bytes $_DEFAULT_ = 0x01 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_ITbtForcePowerOnTimeoutInMs 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_ITbtConnectTopologyTimeoutInMs 2 bytes $_DEFAULT_ = 0x1388 + $gPlatformFspPkgTokenSpaceGuid_ITbtDmaLtr 4 bytes $_DEFAULT_ = 0xFF,0x97,0xFF,0x97 + $gPlatformFspPkgTokenSpaceGuid_Usb4CmMode 1 bytes $_DEFAULT_ = 0x01 + Skip 11 bytes + $gPlatformFspPkgTokenSpaceGuid_FspsValidationPtr 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IehMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RtcBiosInterfaceLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RtcMemoryLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_AmtEnabled 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_IaxEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPinMuxing 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartRxPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartTxPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPinMuxing 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPinMuxing 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPinMuxing 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPinMuxing 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPadTermination 12 bytes $_DEFAULT_ = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartRxPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartTxPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPadTermination 4 bytes $_DEFAULT_ = 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCsEnable 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCs0Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshSpiEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshUartEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshI2cEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshGpEnable 12 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshMsiInterrupt 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x2 + $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MctpBroadcastCycle 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CseDataResilience 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PseEomFlowEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IshI3cSdaPinMuxing 8 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshI3cSclPinMuxing 8 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshI3cSdaPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshI3cSclPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_PchIshI3cEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcUsb2PhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcV1p05PhyExtFetControlEn 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcV1p05IsExtFetControlEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur 1 bytes $_DEFAULT_ = 0xC7 + $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsOnEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcOsIdleEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchS0ixAutoDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmLatchEventsC10Exit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcLpmS0ixSubStateEnableMask 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PchPmErDebugMode 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcC10DynamicThresholdAdjustment 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PciePtm 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x2, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber 28 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B + $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm 28 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_HostL0sTxDis 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates 28 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqOverrideDefault 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMethod 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMode 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqLocalTxOverrideEn 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3NoOfPresetOrCoeff 12 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor0List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor0List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor1List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor1List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor2List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor2List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor3List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor3List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor4List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor4List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor5List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor5List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor6List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor6List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor7List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor7List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor8List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor8List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor9List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor9List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset0List 12 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset1List 12 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset2List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset3List 12 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset4List 12 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset5List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset6List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset7List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset8List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset9List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset10List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh1DpTxPreset 12 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh1UpTxPreset 12 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh2LocalTxOverridePreset 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMethod 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMode 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqLocalTxOverrideEn 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3NoOfPresetOrCoeff 12 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor0List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor0List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor1List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor1List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor2List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor2List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor3List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor3List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor4List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor4List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor5List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor5List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor6List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor6List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor7List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor7List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor8List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor8List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor9List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor9List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset0List 12 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset1List 12 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset2List 12 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset3List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset4List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset5List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset6List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset7List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset8List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset9List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset10List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh1DpTxPreset 12 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh1UpTxPreset 12 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh2LocalTxOverridePreset 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMethod 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMode 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqLocalTxOverrideEn 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3NoOfPresetOrCoeff 12 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor0List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor0List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor1List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor1List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor2List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor2List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor3List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor3List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor4List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor4List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor5List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor5List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor6List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor6List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor7List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor7List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor8List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor8List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor9List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor9List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset0List 12 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset1List 12 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset2List 12 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset3List 12 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset4List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset5List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset6List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset7List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset8List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset9List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset10List 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh1DpTxPreset 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x000 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh1UpTxPreset 12 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh2LocalTxOverridePreset 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Bypass 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh3Bypass 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh3Bypass 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh23Bypass 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh23Bypass 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh23Bypass 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3PcetTimer 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4PcetTimer 12 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5PcetTimer 12 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3TsLockTimer 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4TsLockTimer 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5TsLockTimer 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieSetSecuredRegisterLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpTestAspmOc 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLinkDownGpios 12 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieClockGating 12 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PciePowerGating 12 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieVisaClockGating 12 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieAutoPowerGating 12 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PciePhyAutoPowerGating 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieFomsCp 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqPhBypass 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency 48 bytes $_DEFAULT_ = 0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency 48 bytes $_DEFAULT_ = 0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode 28 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier 28 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode 28 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier 28 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrOverrideSpecCompliant 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_GlobalPcieAer 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieTbtPerfBoost 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiClkPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiCsPinMux 56 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiMode 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiMosiPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiMisoPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiCsPolarity 14 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiCsEnable 14 bytes $_DEFAULT_ = 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiCsMode 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiCsState 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate 28 bytes $_DEFAULT_ = 0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity 7 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits 7 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits 7 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating 7 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable 7 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRtsPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRxPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartTxPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPgDbg2 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSdaPinMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSclPinMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cMode 3 bytes $_DEFAULT_ = 0, 0, 0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSdaPinMux 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSdaPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclPinMux 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclFbPinMux 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclFbPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_VmdEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VmdGlobalMapping 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdPort 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdPortBus 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdPortDev 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdPortFunc 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + Skip 7 bytes + $gPlatformFspPkgTokenSpaceGuid_VmdVariablePtr 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBase 4 bytes $_DEFAULT_ = 0xA0000000 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Base 4 bytes $_DEFAULT_ = 0xA2000000 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Base 4 bytes $_DEFAULT_ = 0xA4000000 + $gPlatformFspPkgTokenSpaceGuid_D3HotEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TcssTbtPerfBoost 1 bytes $_DEFAULT_ = 0x0F + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_IomTypeCPortPadCfg 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuUsb3OverCurrentPin 10 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + $gPlatformFspPkgTokenSpaceGuid_D3ColdEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcCstateLimit 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_TcNotifyIgd 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TcssCpuUsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcPdEnable 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_TcssAuxOri 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_TcssHslOri 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_UsbTcPortEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VccSt 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PtmEnabled 4 bytes $_DEFAULT_ = 1, 1, 1, 1 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpLtrEnable 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideMode 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideMultiplier 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideValue 8 bytes $_DEFAULT_ = 0xC8,0x00,0xC8,0x00,0xC8,0x00,0xC8,0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideMode 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideMultiplier 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideValue 8 bytes $_DEFAULT_ = 0xC8,0x00,0xC8,0x00,0xC8,0x00,0xC8,0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpForceLtrOverride 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpLtrConfigLock 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableTcssCovTypeA 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcAssignment 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcInterruptPinMuxing 8 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcMode 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcWakeOnTouch 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcActiveLtr 8 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF + $gPlatformFspPkgTokenSpaceGuid_ThcIdleLtr 8 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF + $gPlatformFspPkgTokenSpaceGuid_TimestampTimerMode 2 bytes $_DEFAULT_ = 0x0, 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_DisplayFrameSyncPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcResetPad 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcResetPadTrigger 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcDsyncPad 2 bytes $_DEFAULT_ = 0x0, 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiConnectionSpeed 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiLimitPacketSize 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcPerformanceLimitation 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiInputReportHeaderAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiInputReportBodyAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiOutputReportAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiReadOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiWriteOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiFlags 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcResetSequencingDelay 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cDeviceAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cConnectionSpeed 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cAddressingMode 2 bytes $_DEFAULT_ = 0x0, 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cDeviceDescriptorAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cStandardModeSerialClockLineHighPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cStandardModeSerialClockLineLowPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cStandardModeSerialDataLineTransmitHoldPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cStandardModeSerialDataLineReceiveHoldPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModeSerialClockLineHighPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModeSerialClockLineLowPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModeSerialDataLineTransmitHoldPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModeSerialDataLineReceiveHoldPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cMaxSuppressedSpikesSMFMFMP 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModePlusSerialClockLineHighPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModePlusSerialClockLineLowPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModePlusSerialDataLineTransmitHoldPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModePlusSerialDataLineReceiveHoldPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cHighSpeedModePlusSerialClockLineHighPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cHighSpeedModePlusSerialClockLineLowPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cHighSpeedModePlusSerialDataLineTransmitHoldPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cHighSpeedModePlusSerialDataLineReceiveHoldPeriod 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cMaximumLengthOfSuppressedSpikesInHighSpeedMode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcWotEdgeLevel 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcWotActiveLevel 2 bytes $_DEFAULT_ = 0x1, 0x1 + $gPlatformFspPkgTokenSpaceGuid_ThcWotPinConfig 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcCustomizedSsid 4 bytes $_DEFAULT_ = 0x70,0x72,0x70,0x72 + $gPlatformFspPkgTokenSpaceGuid_ThcCustomizedSvid 4 bytes $_DEFAULT_ = 0x86,0x80,0x86,0x80 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_Usb31PortSpeed 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cMaxFrameSize 2 bytes $_DEFAULT_ = 0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cMaxFrameSizeValue 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cIntDelay 2 bytes $_DEFAULT_ = 0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cIntDelayValue 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPostMemRsvd 9 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHotEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchT0Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PchT1Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PchT2Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PchTTEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTTLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel 2 bytes $_DEFAULT_ = 0x0073 + $gPlatformFspPkgTokenSpaceGuid_PchTsnEnable 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PchTsn1MacAddressHigh 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsn1MacAddressLow 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsn2MacAddressHigh 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsn2MacAddressLow 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsn3MacAddressHigh 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsn3MacAddressLow 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsn4MacAddressHigh 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsn4MacAddressLow 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_XdciEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchXhciUaolEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 + $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchXhciDwbEnable 1 bytes $_DEFAULT_ = 0x01 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PortResetMessageEnable 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPetxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyTxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPredeemp 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPehalfbit 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 80 bytes + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_PcieFiaProgramming 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SseCommunication 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MePostMemRestrictedRsvd 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NpuEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PchLanEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchLanWOLFastSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SiSkipSsidProgramming 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SiCustomizedSvid 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_SiCustomizedSsid 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PchCanEnable 2 bytes $_DEFAULT_ = 0x01, 0x01 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_DfxSkipBiosDone 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SiPostMemRsvd 6 bytes $_DEFAULT_ = 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth 4 bytes $_DEFAULT_ = 0x00000000 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SkipFspGop 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ConfigureMedia 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_RenderStandby 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_ConfigureGT 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_RC1pGtFreqEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RC1pMediaFreqEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PavpEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_MediaStandby 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_Dev2IsGfxWorkstation 1 bytes $_DEFAULT_ = 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_VbtSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LidStatus 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MaxActiveDisplays 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_HorizontalResolution 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_VerticalResolution 4 bytes $_DEFAULT_ = 0x00000000 + Skip 56 bytes + $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute 1 bytes $_DEFAULT_ = 0x0E + $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect 1 bytes $_DEFAULT_ = 0x09 + $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect 1 bytes $_DEFAULT_ = 0x09 + $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimerEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimer1Val 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrMultiplier1Val 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrHostPartitionReset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailEnabledStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailSupportedVoltageStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailVoltage 2 bytes $_DEFAULT_ = 0x01A4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMax 1 bytes $_DEFAULT_ = 0x64 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailEnabledStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSupportedVoltageStates 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailVoltage 2 bytes $_DEFAULT_ = 0x01A4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMax 1 bytes $_DEFAULT_ = 0xC8 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxEnabledStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxVoltage 2 bytes $_DEFAULT_ = 0x01A4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMax 1 bytes $_DEFAULT_ = 0xC8 + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxLowToHighCurModeVolTranTime 1 bytes $_DEFAULT_ = 0x0C + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToHighCurModeVolTranTime 1 bytes $_DEFAULT_ = 0x036 + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToLowCurModeVolTranTime 1 bytes $_DEFAULT_ = 0x2B + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxOffToHighCurModeVolTranTime 2 bytes $_DEFAULT_ = 0x0096 + $gPlatformFspPkgTokenSpaceGuid_PchFivrDynPm 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMaximum 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMaximum 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMaximum 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailCtrlRampTmr 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailCtrlRampTmr 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PchCrid 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SvTestUnhideP2sb 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchIoApicId 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_CnviMode 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CnviWifiCore 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CnviBtCore 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CnviBtInterface 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CnviWwanCoex 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SkipBtPreInit 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_CnviRfResetPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CnviClkreqPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffloadInterface 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Device4Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SkipPamLock 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TcssLsxOe 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum 1 bytes $_DEFAULT_ = 0 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr 8 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PchHdaCodecSxWakeCapability 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaPme 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyDeglitch 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeSoundWire0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeSoundWire1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeSoundWire2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeSoundWire3 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeSoundWire4 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeDmic 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyTimeout 4 bytes $_DEFAULT_ = 0x00000064 + Skip 8 bytes + $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen 4 bytes $_DEFAULT_ = 0x00000000 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_NphyBinPtr 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_NphyBinLen 4 bytes $_DEFAULT_ = 0x00000000 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinPtr 8 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinLen 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SiSkipBiosDoneWhenFwUpdate 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcWdtTimerEn 1 bytes $_DEFAULT_ = 0x01 + +EndStruct + + +List &EN_DIS + Selection 0x1 , "Enabled" + Selection 0x0 , "Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUartDebugEnable + Selection 0 , "Disable" + Selection 1 , "Enable and Initialize" + Selection 2 , "Enable without Initializing" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUartNumber + Selection 0 , "SerialIoUart0" + Selection 1 , "SerialIoUart1" + Selection 2 , "SerialIoUart2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUartMode + Selection 0 , "SerialIoUartDisabled" + Selection 1 , "SerialIoUartPci" + Selection 2 , "SerialIoUartHidden" + Selection 3 , "SerialIoUartCom" + Selection 4 , "SerialIoUartSkipInit" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUartPowerGating + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUartParity + Selection 0 , " DefaultParity" + Selection 1 , " NoParity" + Selection 2 , " EvenParity" + Selection 3 , " OddParity" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUartStopBits + Selection 0 , " DefaultStopBits" + Selection 1 , " OneStopBit" + Selection 2 , " OneFiveStopBits" + Selection 3 , " TwoStopBits" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUartAutoFlow + Selection 0 , " Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel + Selection 0 , "Disable" + Selection 1 , "Error Only" + Selection 2 , "Error and Warnings" + Selection 3 , "Load Error Warnings and Info" + Selection 4 , "Load Error Warnings and Info & Event" + Selection 5 , "Load Error Warnings Info and Verbose" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase + Selection 0 , "0x3F8" + Selection 1 , "0x2F8" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndEnable + Selection 0 , "Disable" + Selection 1 , "Enable and Initialize" + Selection 2 , "Enable without Initializing" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndNumber + Selection 0 , "SerialIoUart0" + Selection 1 , "SerialIoUart1" + Selection 2 , "SerialIoUart2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndMode + Selection 0 , "SerialIoUartDisabled" + Selection 1 , "SerialIoUartPci" + Selection 2 , "SerialIoUartHidden" + Selection 3 , "SerialIoUartCom" + Selection 4 , "SerialIoUartSkipInit" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndParity + Selection 0 , " DefaultParity" + Selection 1 , " NoParity" + Selection 2 , " EvenParity" + Selection 3 , " OddParity" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndStopBits + Selection 0 , " DefaultStopBits" + Selection 1 , " OneStopBit" + Selection 2 , " OneFiveStopBits" + Selection 3 , " TwoStopBits" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpssUart2ndAutoFlow + Selection 0 , " Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_EnableSecondaryDataCache + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ProgramWriteBackCodeCache + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode + Selection 1 , "SerialIoUartPci" + Selection 4 , "SerialIoUartSkipInit" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DciDbcMode + Selection 0 , "Disabled" + Selection 1 , "USB2 DbC" + Selection 2 , "USB3 DbC" + Selection 3 , "Both" + Selection 4 , "No Change" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen + Selection 0x100 , "256 Bytes" + Selection 0x200 , "512 Bytes" + Selection 0x400 , "1024 Bytes" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl + Selection 0 , " No Error Injection" + Selection 1 , "Inject Correctable Error Address match" + Selection 3 , "Inject Correctable Error on insertion counter" + Selection 5 , " Inject Uncorrectable Error Address match" + Selection 7 , "Inject Uncorrectable Error on insertion counter" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_tWR + Selection 0 , "Auto" + Selection 5 , "5" + Selection 6 , "6" + Selection 7 , "7" + Selection 8 , "8" + Selection 10 , "10" + Selection 12 , "12" + Selection 14 , "14" + Selection 16 , "16" + Selection 18 , "18" + Selection 20 , "20" + Selection 24 , "24" + Selection 30 , "30" + Selection 34 , "34" + Selection 40 , "40" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_LpMode4 + Selection 0 , " Disable" + Selection 1 , "Enable" + Selection 2 , "Dynamic Threshold 2" + Selection 3 , "Dynamic Threshold 3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VrefCtlOffset + Selection 0xF4 , "-12" + Selection 0xF5 , "-11" + Selection 0xF6 , "-10" + Selection 0xF7 , "-9" + Selection 0xF8 , "-8" + Selection 0xF9 , "-7" + Selection 0xFA , "-6" + Selection 0xFB , "-5" + Selection 0xFC , "-4" + Selection 0xFD , "-3" + Selection 0xFE , "-2" + Selection 0xFF , "-1" + Selection 0 , "0" + Selection 1 , "+1" + Selection 2 , "+2" + Selection 3 , "+3" + Selection 4 , "+4" + Selection 5 , "+5" + Selection 6 , "+6" + Selection 7 , "+7" + Selection 8 , "+8" + Selection 9 , "+9" + Selection 10 , "+10" + Selection 11 , "+11" + Selection 12 , "+12" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SmramMask + Selection 0 , " Neither" + Selection 1 , "AB-SEG" + Selection 2 , "H-SEG" + Selection 3 , " Both" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit + Selection 1067 , "1067" + Selection 1333 , "1333" + Selection 1600 , "1600" + Selection 1867 , "1867" + Selection 2133 , "2133" + Selection 2400 , "2400" + Selection 2667 , "2667" + Selection 2933 , "2933" + Selection 0 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SaGv + Selection 0 , "Disabled" + Selection 1 , "Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SaGvWpMask + Selection 0x3 , "Points0_1" + Selection 0x7 , "Points0_1_2" + Selection 0xF , "AllPoints0_1_2_3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VddVoltage + Selection 0 , "Default" + Selection 1200 , "1.20 Volts" + Selection 1250 , "1.25 Volts" + Selection 1300 , "1.30 Volts" + Selection 1350 , "1.35 Volts" + Selection 1400 , "1.40 Volts" + Selection 1450 , "1.45 Volts" + Selection 1500 , "1.50 Volts" + Selection 1550 , "1.55 Volts" + Selection 1600 , "1.60 Volts" + Selection 1650 , "1.65 Volts" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_Ratio + Selection 0 , "Auto" + Selection 4 , "4" + Selection 5 , "5" + Selection 6 , "6" + Selection 7 , "7" + Selection 8 , "8" + Selection 9 , "9" + Selection 10 , "10" + Selection 11 , "11" + Selection 12 , "12" + Selection 13 , "13" + Selection 14 , "14" + Selection 15 , "15" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected + Selection 0 , "Default Profile" + Selection 1 , "Custom Profile" + Selection 2 , "XMP Profile 1" + Selection 3 , "XMP Profile 2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_FUNCDCCCLK + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQS + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQ + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_Lp5SplitACTEnable + Selection 0 , "Auto" + Selection 1 , "Disable" + Selection 2 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CccHalfFrequency + Selection 0 , " Auto" + Selection 1 , " Disable" + Selection 2 , " GroupGv0" + Selection 3 , " GroupGv1" + Selection 4 , " GroupGv2" + Selection 5 , " GroupGv3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PprRepairType + Selection 0 , "Do not Repair (Default)" + Selection 1 , "Soft Repair" + Selection 2 , "Hard Repair" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MsHashInterleaveBit + Selection 0 , "BIT6" + Selection 1 , "BIT7" + Selection 2 , "BIT8" + Selection 3 , "BIT9" + Selection 4 , "BIT10" + Selection 5 , "BIT11" + Selection 6 , "BIT12" + Selection 7 , "BIT13" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_HobBufferSize + Selection 0 , "Default" + Selection 1 , " 1 Byte" + Selection 2 , " 1 KB" + Selection 3 , " Max value" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode + Selection 0 , "Protect base on address range" + Selection 1 , " Non-protected" + Selection 2 , " All protected" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VCCCLKFF + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit + Selection 0 , "BIT6" + Selection 1 , "BIT7" + Selection 2 , "BIT8" + Selection 3 , "BIT9" + Selection 4 , "BIT10" + Selection 5 , "BIT11" + Selection 6 , "BIT12" + Selection 7 , "BIT13" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_McRefreshRate + Selection 0 , "NORMAL Refresh" + Selection 1 , "1x Refresh" + Selection 2 , "2x Refresh" + Selection 3 , "4x Refresh" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RefreshWm + Selection 0 , "Set Refresh Watermarks to Low" + Selection 1 , "Set Refresh Watermarks to High (Default)" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PowerDownMode + Selection 0x0 , "No Power Down" + Selection 0x1 , "APD" + Selection 0x6 , "PPD DLL OFF" + Selection 0xFF , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout + Selection 0 , "Enabled" + Selection 1 , "Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RetryCount + Selection 0 , " Default" + Selection 1 , "3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MrcPprStatus + Selection 0 , " PASS" + Selection 1 , " FAIL(Default)" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TsegMemoryTestStatus + Selection 0 , " PASS" + Selection 1 , " FAIL(Default)" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MrcBdatTestType + Selection 0 , "RMT per Rank" + Selection 1 , "RMT per Bit" + Selection 2 , "Margin2D" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdrOneDpc + Selection 0 , " Disabled" + Selection 1 , " Enabled on DIMM0 only" + Selection 2 , " Enabled on DIMM1 only" + Selection 3 , " Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_UserBd + Selection 0 , "Mobile/Mobile Halo" + Selection 1 , "Desktop/DT Halo" + Selection 5 , "ULT/ULX/Mobile Halo" + Selection 7 , "UP Server" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BdatTestType + Selection 0 , "RMT per Rank" + Selection 1 , "RMT per Bit" + Selection 2 , "Margin2D" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect + Selection 0 , " Both" + Selection 1 , " ClkA" + Selection 2 , " ClkB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency + Selection 4 , " 96MHz" + Selection 3 , " 48MHz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode + Selection 0 , " 2T" + Selection 2 , " 4T" + Selection 3 , " 8T" + Selection 4 , " 16T" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdAudioSndwMultilaneSndwInterface + Selection 0 , " Sndw0" + Selection 1 , " Sndw1" + Selection 2 , " Sndw2" + Selection 3 , " Sndw3" + Selection 4 , " Sndw4" + Selection 5 , " Sndw5" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating + Selection 0 , " POR" + Selection 1 , " Force Enable" + Selection 2 , " Force Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaTestLowFreqLinkClkSrc + Selection 0 , " POR (Enable)" + Selection 1 , " Enable (XTAL)" + Selection 2 , " Disable (Audio PLL)" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel + Selection 0 , "Disable" + Selection 1 , "Error Only" + Selection 2 , "Error and Warnings" + Selection 3 , "Load Error Warnings and Info" + Selection 4 , "Load Error Warnings and Info & Event" + Selection 5 , "Load Error Warnings Info and Verbose" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber + Selection 0 , "SerialIoUart0" + Selection 1 , "SerialIoUart1" + Selection 2 , "SerialIoUart2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity + Selection 0 , " DefaultParity" + Selection 1 , " NoParity" + Selection 2 , " EvenParity" + Selection 3 , " OddParity" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits + Selection 0 , " DefaultStopBits" + Selection 1 , " OneStopBit" + Selection 2 , " OneFiveStopBits" + Selection 3 , " TwoStopBits" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate + Selection 3 , "9600" + Selection 4 , "19200" + Selection 6 , "56700" + Selection 7 , "115200" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming + Selection 0 , " Disabled" + Selection 1 , " Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck + Selection 0 , "Disable" + Selection 1 , "L1" + Selection 2 , "L2" + Selection 3 , "Both" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DramRfmMode + Selection 0 , " RFM" + Selection 1 , " ARFM Level A" + Selection 2 , " ARFM Level B" + Selection 3 , " ARFM Level C" + Selection 4 , " ARFM and RFM Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TargetedRowRefreshMode + Selection 0 , " DRFM" + Selection 1 , " pTRR" + Selection 2 , " Targeted Row Refresh Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix + Selection 0 , "Positive" + Selection 1 , "Negative" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CoreVfConfigScope + Selection 0 , "All-core" + Selection 1 , "Per-core" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CoreOpPointReportingEn + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_FClkFrequency + Selection 0 , "800 MHz" + Selection 1 , " 1 GHz" + Selection 2 , " 400 MHz" + Selection 3 , " Reserved" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "No Change" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CrashLogGprs + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "Only Smm GPRs Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount + Selection 0 , "Disable all big cores" + Selection 1 , "1" + Selection 2 , "2" + Selection 3 , "3" + Selection 0xFF , "Active all big cores" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ActiveSmallCoreCount + Selection 0 , "Disable all small cores" + Selection 1 , "1" + Selection 2 , "2" + Selection 3 , "3" + Selection 0xFF , "Active all small cores" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ActiveLpAtomCoreCount + Selection 0 , "Disable all LP Atom cores" + Selection 1 , "1" + Selection 2 , "2" + Selection 0xFF , "Active all cores" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TsegSize + Selection 0x0400000 , "4MB" + Selection 0x01000000 , "16MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_AcDcPowerState + Selection 0 , "DC" + Selection 1 , "AC" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRate + Selection 0 , " Fast/2" + Selection 1 , " Fast/4" + Selection 2 , " Fast/8" + Selection 3 , " Fast/16" + Selection 0xFF , " Ignore the configuration" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_EnableFastVmode + Selection 0 , " Disable" + Selection 1 , " Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CepEnable + Selection 0 , " Disable" + Selection 1 , " Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchTestDmiMeUmaRootSpaceCheck + Selection 0 , " POR" + Selection 1 , " enable" + Selection 2 , " disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_StreamTracerMode + Selection 0 , " Disable (Default)" + Selection 524288 , " Advanced Tracing" + Selection 8192 , " Auto" + Selection 3 , " User input" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_StaticContentSizeAt4Gb + Selection 0 , " No Allocation" + Selection 0x20 , "32MB" + Selection 0x40 , "64MB" + Selection 0x80 , "128MB" + Selection 0x100 , "256MB" + Selection 0x200 , "512MB" + Selection 0x400 , "1GB" + Selection 0x800 , "2GB" + Selection 0xC00 , "3GB" + Selection 0x1000 , "4GB" + Selection 0x2000 , "8GB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PlatformDebugOption + Selection 0 , "Disabled" + Selection 2 , "Enabled Trace Active" + Selection 4 , "Enabled Trace Ready" + Selection 6 , "Enable Trace Power-Off" + Selection 7 , "Manual" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig + Selection 0 , "Disabled" + Selection 1 , "eDP" + Selection 2 , "MIPI DSI" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig + Selection 0 , "Disabled" + Selection 1 , "eDP" + Selection 2 , "MIPI DSI" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay + Selection 0 , " No Delay" + Selection 0xFFFF , " Auto Calulate T12 Delay" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay + Selection 3 , "AUTO" + Selection 0 , "IGFX" + Selection 4 , "HG" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IGpuGsm2Size + Selection 0 , "2GB" + Selection 1 , "4GB" + Selection 2 , "6GB" + Selection 3 , "8GB" + Selection 4 , "10GB" + Selection 5 , "12GB" + Selection 6 , "14GB" + Selection 7 , "16GB" + Selection 8 , "18GB" + Selection 9 , "20GB" + Selection 10 , "22GB" + Selection 11 , "24GB" + Selection 12 , "26GB" + Selection 13 , "28GB" + Selection 14 , "30GB" + Selection 15 , "32GB" + Selection 0xFF , "No Allocation" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_LidStatus + Selection 0 , " LidClosed" + Selection 1 , " LidOpen" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VgaInitControl + Selection 0 , "VGA Disable" + Selection 1 , "Mode 3 VGA" + Selection 2 , "Mode 12 VGA" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IomUsbCDpConfig + Selection 0 , "Disabled" + Selection 1 , "IOM_DP" + Selection 2 , "IOM_HDMI" + Selection 3 , " IOM_EDP" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TcssPort0 + Selection 0 , "DISABLE" + Selection 1 , "DP_ONLY" + Selection 2 , "NO_TBT" + Selection 3 , " NO_PCIE" + Selection 7 , "FULL_FUN" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TcssPort1 + Selection 0 , "DISABLE" + Selection 1 , "DP_ONLY" + Selection 2 , "NO_TBT" + Selection 3 , " NO_PCIE" + Selection 7 , "FULL_FUN" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TcssPort2 + Selection 0 , "DISABLE" + Selection 1 , "DP_ONLY" + Selection 2 , "NO_TBT" + Selection 3 , " NO_PCIE" + Selection 7 , "FULL_FUN" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TcssPort3 + Selection 0 , "DISABLE" + Selection 1 , "DP_ONLY" + Selection 2 , "NO_TBT" + Selection 3 , " NO_PCIE" + Selection 7 , "FULL_FUN" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg0Size + Selection 0x00 , "1MB" + Selection 0x03 , "8MB" + Selection 0x06 , "64MB" + Selection 0x07 , "128MB" + Selection 0x08 , "256MB" + Selection 0x09 , "512MB" + Selection 0x0A , "1GB" + Selection 0x0B , "2GB" + Selection 0x0C , "4GB" + Selection 0x0D , "8GB" + Selection 0x0E , "0MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg1Size + Selection 0x00 , "1MB" + Selection 0x03 , "8MB" + Selection 0x06 , "64MB" + Selection 0x07 , "128MB" + Selection 0x08 , "256MB" + Selection 0x09 , "512MB" + Selection 0x0A , "1GB" + Selection 0x0B , "2GB" + Selection 0x0C , "4GB" + Selection 0x0D , "8GB" + Selection 0x0E , "0MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc + Selection 0x00 , "0MB" + Selection 0x01 , "32MB" + Selection 0x02 , "64MB" + Selection 0x03 , "96MB" + Selection 0x04 , "128MB" + Selection 0xF0 , "4MB" + Selection 0xF1 , "8MB" + Selection 0xF2 , "12MB" + Selection 0xF3 , "16MB" + Selection 0xF4 , "20MB" + Selection 0xF5 , "24MB" + Selection 0xF6 , "28MB" + Selection 0xF7 , "32MB" + Selection 0xF8 , "36MB" + Selection 0xF9 , "40MB" + Selection 0xFA , "44MB" + Selection 0xFB , "48MB" + Selection 0xFC , "52MB" + Selection 0xFD , "56MB" + Selection 0xFE , "60MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_InternalGraphics + Selection 2 , "AUTO" + Selection 1 , "Enable" + Selection 0 , "Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_AsyncOdtDis + Selection 0 , "Enabled" + Selection 1 , "Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CAVrefCtlOffset + Selection 0xF4 , "-12" + Selection 0xF5 , "-11" + Selection 0xF6 , "-10" + Selection 0xF7 , "-9" + Selection 0xF8 , "-8" + Selection 0xF9 , "-7" + Selection 0xFA , "-6" + Selection 0xFB , "-5" + Selection 0xFC , "-4" + Selection 0xFD , "-3" + Selection 0xFE , "-2" + Selection 0xFF , "-1" + Selection 0 , "0" + Selection 1 , "+1" + Selection 2 , "+2" + Selection 3 , "+3" + Selection 4 , "+4" + Selection 5 , "+5" + Selection 6 , "+6" + Selection 7 , "+7" + Selection 8 , "+8" + Selection 9 , "+9" + Selection 10 , "+10" + Selection 11 , "+11" + Selection 12 , "+12" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ClkPiCodeOffset + Selection 0xFA , "-6" + Selection 0xFB , "-5" + Selection 0xFC , "-4" + Selection 0xFD , "-3" + Selection 0xFE , "-2" + Selection 0xFF , "-1" + Selection 0 , "0" + Selection 1 , "+1" + Selection 2 , "+2" + Selection 3 , "+3" + Selection 4 , "+4" + Selection 5 , "+5" + Selection 6 , "+6" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RcvEnOffset + Selection 0xFD , "-3" + Selection 0xFE , "-2" + Selection 0xFF , "-1" + Selection 0 , "0" + Selection 1 , "+1" + Selection 2 , "+2" + Selection 3 , "+3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RxDqsOffset + Selection 0xFD , "-3" + Selection 0xFE , "-2" + Selection 0xFF , "-1" + Selection 0 , "0" + Selection 1 , "+1" + Selection 2 , "+2" + Selection 3 , "+3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TxDqOffset + Selection 0xFD , "-3" + Selection 0xFE , "-2" + Selection 0xFF , "-1" + Selection 0 , "0" + Selection 1 , "+1" + Selection 2 , "+2" + Selection 3 , "+3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TxDqsOffset + Selection 0xFD , "-3" + Selection 0xFE , "-2" + Selection 0xFF , "-1" + Selection 0 , "0" + Selection 1 , "+1" + Selection 2 , "+2" + Selection 3 , "+3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VrefOffset + Selection 0xFA , "-6" + Selection 0xFB , "-5" + Selection 0xFC , "-4" + Selection 0xFD , "-3" + Selection 0xFE , "-2" + Selection 0xFF , "-1" + Selection 0 , "0" + Selection 1 , "+1" + Selection 2 , "+2" + Selection 3 , "+3" + Selection 4 , "+4" + Selection 5 , "+5" + Selection 6 , "+6" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_Interpreter + Selection 0 , "CMOS" + Selection 1 , "Break" + Selection 2 , "Force" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IoOdtMode + Selection 0 , "Default" + Selection 1 , "Vtt" + Selection 2 , "Vddq" + Selection 3 , "Vss" + Selection 4 , "Max" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MimicWcDisaplayInIpq + Selection 1 , "1" + Selection 3 , "3" + Selection 0xf , "0xf" + Selection 0 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DprLock + Selection 0 , "Platform POR" + Selection 1 , " Enable" + Selection 2 , " Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BoardStackUp + Selection 0 , "Typical" + Selection 1 , "Freq Limited" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BoardTopology + Selection 0 , "Daisy Chain" + Selection 1 , "Tee" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SubChHashInterleaveBit + Selection 0 , "BIT6" + Selection 1 , "BIT7" + Selection 2 , "BIT8" + Selection 3 , "BIT9" + Selection 4 , "BIT10" + Selection 5 , "BIT11" + Selection 6 , "BIT12" + Selection 7 , "BIT13" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_AdjustWckMode + Selection 0 , "safe mode" + Selection 1 , "manual mode" + Selection 2 , "dynamic mode" + Selection 3 , "Default" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TelemetryControl + Selection 0 , " Default" + Selection 1 , " Enable" + Selection 2 , " Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PpinSupport + Selection 0 , " Disable" + Selection 1 , " Enable" + Selection 2 , " Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_AvxDisable + Selection 0 , " Enable" + Selection 1 , " Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ForcePrDemotion + Selection 0 , " Disable" + Selection 1 , " Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VrAlertDemotion + Selection 0 , " Disable" + Selection 1 , " Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BootFrequency + Selection 0 , "0" + Selection 1 , "1" + Selection 2 , "2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme + Selection 0 , " Single Range Output" + Selection 1 , " ToPA Output" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceBspOnly + Selection 0 , " all cores" + Selection 1 , " Bsp only" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IehMode + Selection 0 , " Bypass" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage + Selection 0 , "Disable" + Selection 1 , "Send in PEI" + Selection 2 , "Send in DXE" + Selection 3 , "Reserved" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear + Selection 0 , " Disable ME Unconfig On Rtc Clear" + Selection 1 , " Enable ME Unconfig On Rtc Clear" + Selection 2 , " Cmos is clear" + Selection 3 , " Reserved" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMethod + Selection 0 , " HardwareEq" + Selection 1 , " FixedEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMode + Selection 0 , " PresetEq" + Selection 1 , " CoefficientEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMethod + Selection 0 , " HardwareEq" + Selection 1 , " FixedEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMode + Selection 0 , " PresetEq" + Selection 1 , " CoefficientEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMethod + Selection 0 , " HardwareEq" + Selection 1 , " FixedEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMode + Selection 0 , " PresetEq" + Selection 1 , " CoefficientEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh3Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh3Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh23Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh23Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh23Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpLinkDownGpios + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieFomsCp + Selection 0 , " Auto" + Selection 1 , " Gen3 Foms" + Selection 2 , " Gen4 Foms" + Selection 3 , " Gen3 and Gen4 Foms" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieEqPhBypass + Selection 0 , " Auto" + Selection 1 , " Gen3 Foms" + Selection 2 , " Gen4 Foms" + Selection 3 , " Gen3 and Gen4 Foms" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_GlobalPcieAer + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CnviMode + Selection 0 , "Disable" + Selection 1 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CnviBtInterface + Selection 1 , "USB" + Selection 2 , "PCI" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency + Selection 0 , " 6MHz" + Selection 1 , " 12MHz" + Selection 2 , " 24MHz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyMode + Selection 0 , " No Microphone Privacy Support" + Selection 1 , " HW Managed Microphone Privacy" + Selection 2 , " FW Managed Microphone Privacy" + Selection 3 , " Force Microphone Mute" +EndList + +BeginInfoBlock + PPVer "0.1" + Description "Panther Lake Platform" +EndInfoBlock + +Page "Memory Reference Code" + Combo $gPlatformFspPkgTokenSpaceGuid_MemMapOverlapCheckSupport, "Enable/Disable MemoryOverlap check", &EN_DIS, + Help "Enable(Default): Enable MemoryOverlap check, Disable: Disable MemoryOverlap check" + Combo $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, "Memory Test on Warm Boot", &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, + Help "Run Base Memory Test on Warm Boot" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxEqTap0, "NnFlex Override for PHY RxEqTap0", HEX, + Help "Controlled by NnFlexPhyOvrdMask bit[0], 6 bit 2's complement" + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxEqTap1, "NnFlex Override for PHY RxEqTap1", HEX, + Help "Controlled by NnFlexPhyOvrdMask bit[1], 6 bit 2's complement, valid range: [-16..15]" + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyDqTcoComp, "NnFlex Override for PHY DqTcoComp", HEX, + Help "Controlled by NnFlexPhyOvrdMask bit[2], 6 bit 2's complement" + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxCtleR, "NnFlex Override for PHY RxCtleR", HEX, + Help "Controlled by NnFlexPhyOvrdMask bit[3]" + "Valid range: 0x00 ~ 0x03" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxCtleC, "NnFlex Override for PHY RxCtleC", HEX, + Help "Controlled by NnFlexPhyOvrdMask bit[4]" + "Valid range: 0x00 ~ 0x03" + EditNum $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize, "Platform Reserved Memory Size", HEX, + Help "The minimum platform memory size required to pass control into DXE" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, "SPD Data Length", &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, + Help "Length of SPD Data" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxCtleRcmn, "NnFlex Override for PHY RxCtleRcmn", HEX, + Help "Controlled by NnFlexPhyOvrdMask bit[5]" + "Valid range: 0x00 ~ 0x03" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxCtleEq, "NnFlex Override for PHY RxCtleEq", HEX, + Help "Controlled by NnFlexPhyOvrdMask bit[6]" + "Valid range: 0x00 ~ 0x07" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyRxCtleTailCtl, "NnFlex Override for PHY RxCtleTailCtl", HEX, + Help "Controlled by NnFlexPhyOvrdMask bit[7]" + "Valid range: 0x00 ~ 0x03" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5Dfeq, "NnFlex Override for LP5 Dfeq", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[0], MR24 encoding" + "Valid range: 0x00 ~ 0x07" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5PdDrvStr, "NnFlex Override for LP5 PdDrvStr", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[1], MR3 encoding" + "Valid range: 0x00 ~ 0x06" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5SocOdt, "NnFlex Override for LP5 SocOdt", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[2], MR17 encoding" + "Valid range: 0x00 ~ 0x06" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr000, "Memory SPD Pointer Controller 0 Channel 0 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr001, "Memory SPD Pointer Controller 0 Channel 0 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr010, "Memory SPD Pointer Controller 0 Channel 1 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr011, "Memory SPD Pointer Controller 0 Channel 1 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr020, "Memory SPD Pointer Controller 0 Channel 2 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr021, "Memory SPD Pointer Controller 0 Channel 2 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr030, "Memory SPD Pointer Controller 0 Channel 3 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr031, "Memory SPD Pointer Controller 0 Channel 3 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr100, "Memory SPD Pointer Controller 1 Channel 0 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr101, "Memory SPD Pointer Controller 1 Channel 0 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr110, "Memory SPD Pointer Controller 1 Channel 1 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr111, "Memory SPD Pointer Controller 1 Channel 1 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr120, "Memory SPD Pointer Controller 1 Channel 2 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr121, "Memory SPD Pointer Controller 1 Channel 2 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr130, "Memory SPD Pointer Controller 1 Channel 3 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr131, "Memory SPD Pointer Controller 1 Channel 3 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RcompResistor, "RcompResistor settings", HEX, + Help "Indicates RcompResistor settings: Board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RcompTarget, "RcompTarget settings", HEX, + Help "RcompTarget settings: board-dependent" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch0, "Dqs Map CPU to DRAM MC 0 CH 0", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch1, "Dqs Map CPU to DRAM MC 0 CH 1", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch2, "Dqs Map CPU to DRAM MC 0 CH 2", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch3, "Dqs Map CPU to DRAM MC 0 CH 3", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch0, "Dqs Map CPU to DRAM MC 1 CH 0", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch1, "Dqs Map CPU to DRAM MC 1 CH 1", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch2, "Dqs Map CPU to DRAM MC 1 CH 2", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch3, "Dqs Map CPU to DRAM MC 1 CH 3", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch0, "Dq Map CPU to DRAM MC 0 CH 0", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch1, "Dq Map CPU to DRAM MC 0 CH 1", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch2, "Dq Map CPU to DRAM MC 0 CH 2", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch3, "Dq Map CPU to DRAM MC 0 CH 3", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch0, "Dq Map CPU to DRAM MC 1 CH 0", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch1, "Dq Map CPU to DRAM MC 1 CH 1", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch2, "Dq Map CPU to DRAM MC 1 CH 2", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch3, "Dq Map CPU to DRAM MC 1 CH 3", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_LowerBasicMemTestSize, "LowerBasicMemTestSize", &EN_DIS, + Help "Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, shorter BasicMemTest (faster boot)" + Combo $gPlatformFspPkgTokenSpaceGuid_EccGranularity32BEn, "EccGranularity32BEn", &EN_DIS, + Help "Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, shorter BasicMemTest (faster boot)" + Combo $gPlatformFspPkgTokenSpaceGuid_EccCorrectionMode, "EccCorrectionMode", &EN_DIS, + Help "Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, shorter BasicMemTest (faster boot)" + EditNum $gPlatformFspPkgTokenSpaceGuid_CaVrefHigh, "CaVrefHigh", HEX, + Help "DDR5 CA Sweep High Vref Value for DDR5 OC" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CaVrefLow, "CaVrefLow", HEX, + Help "DDR5 CA Sweep Low Vref Value for DDR5 OC" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CsVrefHigh, "CsVrefHigh", HEX, + Help "DDR5 CS Sweep High Vref Value for DDR5 OC" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CsVrefLow, "CsVrefLow", HEX, + Help "DDR5 CS Sweep Low Vref Value for DDR5 OC" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DFETap1StepSize, "DIMM DFE Tap1 Step Size", HEX, + Help "DIMM DFE Tap1 Step Size for DDR5 OC" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DFETap2StepSize, "DIMM DFE Tap2 Step Size", HEX, + Help "DIMM DFE Tap2 Step Size for DDR5 OC" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl, "IbeccEccInjControl", &gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl, + Help "IBECC Error Injection Control" + EditNum $gPlatformFspPkgTokenSpaceGuid_Vdd2Mv, "VDD2 override", HEX, + Help "VDD2 override for DDR5 OC; 0 - Auto" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRAS, "tRAS", HEX, + Help "RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x40" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRCDtRP, "tRCD/tRP", HEX, + Help "RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tREFI, "tREFI", HEX, + Help "Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tCL, "tCL", HEX, + Help "CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tCWL, "tCWL", HEX, + Help "Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x22" + EditNum $gPlatformFspPkgTokenSpaceGuid_tFAW, "tFAW", HEX, + Help "Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC, "tRFC", HEX, + Help "Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x3FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD, "tRRD", HEX, + Help "Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRTP, "tRTP", HEX, + Help "Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x0F" + Combo $gPlatformFspPkgTokenSpaceGuid_tWR, "tWR", &gPlatformFspPkgTokenSpaceGuid_tWR, + Help "Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR, "tWTR", HEX, + Help "Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x1C" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_S, "tWTR_S", HEX, + Help "tWTR_S value for OC Custom Profile, 0 - Auto" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_L, "tWTR_L", HEX, + Help "tWTR_L value for OC Custom Profile, 0 - Auto" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tCCD_L, "tCCD_L", HEX, + Help "tCCD_L value for OC Custom Profile, 0 - Auto" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_S, "tRRD_S", HEX, + Help "tRRD_S value for OC Custom Profile, 0 - Auto" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_L, "tRRD_L", HEX, + Help "tRRD_L value for OC Custom Profile, 0 - Auto" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC4, "tRFC4", HEX, + Help "tRFC4 value for OC Custom Profile, 0 - Auto" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC2, "tRFC2", HEX, + Help "tRFC2 value for OC Custom Profile, 0 - Auto" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFCpb, "tRFCpb", HEX, + Help "tRFCpb value for OC Custom Profile, 0 - Auto" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tCCD_L_WR, "tCCD_L_WR", HEX, + Help "Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank groups, for OC Custom Profile, 0 - Auto" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EnPeriodicComp, "Periodic COMP", &EN_DIS, + Help "Enable/disable Periodic Compensation" + Combo $gPlatformFspPkgTokenSpaceGuid_LpMode4, "LPMode4 Support", &gPlatformFspPkgTokenSpaceGuid_LpMode4, + Help "LPMode4 Options" + EditNum $gPlatformFspPkgTokenSpaceGuid_LpMode, "LPMode Support", HEX, + Help "Bit[0]: Enable Lpmode0p5 (Idle_enable), Bit[1]: Enable Lpmode2 (Powerdown_enable), Bit[2]: Enable Lpmode3 (Selfrefresh_enable)" + "Valid range: 0x00 ~ 0x7" + Combo $gPlatformFspPkgTokenSpaceGuid_OpportunisticRead, "Opportunistic Read", &EN_DIS, + Help "Enables/Disable Opportunistic Read (Def= Enable)" + Combo $gPlatformFspPkgTokenSpaceGuid_Disable2CycleBypass, "Cycle Bypass Support", &EN_DIS, + Help "Enables/Disable Cycle Bypass Support(Def=Disable)" + Combo $gPlatformFspPkgTokenSpaceGuid_OCSafeMode, "MRC OCSafeMode", &EN_DIS, + Help "OverClocking Safe Mode for tCL" + Combo $gPlatformFspPkgTokenSpaceGuid_VrefCtlOffset, "DQ Vref Ctrl Offset", &gPlatformFspPkgTokenSpaceGuid_VrefCtlOffset, + Help "Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch0VrefCtl" + Combo $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved, "Dqs Pins Interleaved Setting", &EN_DIS, + Help "Indicates DqPinsInterleaved setting: board-dependent" + Combo $gPlatformFspPkgTokenSpaceGuid_SmramMask, "Smram Mask", &gPlatformFspPkgTokenSpaceGuid_SmramMask, + Help "The SMM Regions AB-SEG and/or H-SEG reserved" + Combo $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot, "MRC Fast Boot", &EN_DIS, + Help "Enables/Disable the MRC fast path thru the MRC" + Combo $gPlatformFspPkgTokenSpaceGuid_RmtPerTask, "Rank Margin Tool per Task", &EN_DIS, + Help "This option enables the user to execute Rank Margin Tool per major training step in the MRC." + Combo $gPlatformFspPkgTokenSpaceGuid_TrainTrace, "Training Trace", &EN_DIS, + Help "This option enables the trained state tracing feature in MRC. This feature will print out the key training parameters state across major training steps." + Combo $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace, "Probeless Trace", &EN_DIS, + Help "Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjCount, "IbeccEccInjCount", HEX, + Help "Number of memory transactions between ECC error injection" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, "DDR Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, + Help "Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto." + Combo $gPlatformFspPkgTokenSpaceGuid_SaGv, "SAGV", &gPlatformFspPkgTokenSpaceGuid_SaGv, + Help "System Agent dynamic frequency support." + Combo $gPlatformFspPkgTokenSpaceGuid_SaGvWpMask, "SAGV WP Mask", &gPlatformFspPkgTokenSpaceGuid_SaGvWpMask, + Help "System Agent dynamic frequency workpoints that memory will be training at the enabled frequencies." + EditNum $gPlatformFspPkgTokenSpaceGuid_SaGvGear, "SAGV Gear Ratio", HEX, + Help "Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaGvFreq, "SAGV Frequency", HEX, + Help "SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GearRatio, "SAGV Disabled Gear Ratio", HEX, + Help "Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_RMT, "Rank Margin Tool", &EN_DIS, + Help "Enable/disable Rank Margin Tool." + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch0, "Controller 0 Channel 0 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 0" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch1, "Controller 0 Channel 1 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 1" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch2, "Controller 0 Channel 2 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 2" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch3, "Controller 0 Channel 3 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 3" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch0, "Controller 1 Channel 0 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 0" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch1, "Controller 1 Channel 1 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 1" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch2, "Controller 1 Channel 2 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 2" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch3, "Controller 1 Channel 3 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 3" + Combo $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport, "Scrambler Support", &EN_DIS, + Help "This option enables data scrambling in memory." + Combo $gPlatformFspPkgTokenSpaceGuid_MsHashOverride, "Memory Slice Hash Override", &EN_DIS, + Help "Memory Slice (Controller) Hash Mask and LSB Override. 0 = Use default memory slice hash mask / lsb, 1 = Use values from MsHashMask and MsHashInterleaveBit" + Combo $gPlatformFspPkgTokenSpaceGuid_VddVoltage, "Memory Voltage", &gPlatformFspPkgTokenSpaceGuid_VddVoltage, + Help "DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM chips) in millivolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc." + Combo $gPlatformFspPkgTokenSpaceGuid_Ratio, "Memory Ratio", &gPlatformFspPkgTokenSpaceGuid_Ratio, + Help "Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below." + Combo $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, "SPD Profile Selected", &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, + Help "Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP Profile 1, 3=XMP Profile 2" + Combo $gPlatformFspPkgTokenSpaceGuid_RXVREFPERBIT, "RxVref Per-Bit Training", &EN_DIS, + Help "Enable/Disable RxVref Per-Bit Training" + Combo $gPlatformFspPkgTokenSpaceGuid_TXDQSDCC, "TXDQS DCC Training", &EN_DIS, + Help "Enables/Disable TXDQS DCC Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RXDQSDCC, "Rx DQS Duty Cycle Correction", &EN_DIS, + Help "Enables/Disable Rx DQS Duty Cycle Correction" + Combo $gPlatformFspPkgTokenSpaceGuid_ChHashOverride, "Ch Hash Override", &EN_DIS, + Help "Select if Channel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_VoltageReadout, "Voltage Readout", &EN_DIS, + Help "Enables/Disable Voltage Readout for VCCClk and PBias" + Combo $gPlatformFspPkgTokenSpaceGuid_DQSRF, "DQS Rise/Fall", &EN_DIS, + Help "Enables/Disable DQS Rise/Fall" + Combo $gPlatformFspPkgTokenSpaceGuid_RDDQSODTT, "DQS Rise/Fall", &EN_DIS, + Help "Enables/Disable DQS Rise/Fall" + Combo $gPlatformFspPkgTokenSpaceGuid_PRETRAIN, "PreTraining", &EN_DIS, + Help "Enables/Disable PreTraining" + Combo $gPlatformFspPkgTokenSpaceGuid_DUNITC, "DUNIT Configuration", &EN_DIS, + Help "Enables/Disable Dunit Configuration" + Combo $gPlatformFspPkgTokenSpaceGuid_FUNCDCCCLK, "Functional Duty Cycle Correction for DDR5 CLK", &gPlatformFspPkgTokenSpaceGuid_FUNCDCCCLK, + Help "Enable/Disable Functional Duty Cycle Correction for DDR5 CLK" + Combo $gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQS, "Functional Duty Cycle Correction for DDR5 DQS", &gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQS, + Help "Enable/Disable Functional Duty Cycle Correction for DDR5 DQS" + Combo $gPlatformFspPkgTokenSpaceGuid_DCCLP5WCKDCA, "Duty Cycle Correction for LP5 DCA", &EN_DIS, + Help "Enable/Disable Duty Cycle Correction for LP5 DCA" + Combo $gPlatformFspPkgTokenSpaceGuid_DQDQSSWZ, "DQ/DQS Swizzle Training", &EN_DIS, + Help "Enable/Disable DQ/DQS Swizzle Training" + Combo $gPlatformFspPkgTokenSpaceGuid_DCCLP5READDCA, "LP5 Dca Training", &EN_DIS, + Help "Enable/Disable LP5 Dca Training" + Combo $gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQ, "Functional Duty Cycle Correction for Data DQ", &gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQ, + Help "Enable/Disable Functional Duty Cycle Correction for Data DQ" + Combo $gPlatformFspPkgTokenSpaceGuid_SubChHashOverride, "SubCh Hash Override", &EN_DIS, + Help "Select if SubChannel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_Ddr5AutoPrechargeEnable, "DDR5 Auto Precharge Enable", &EN_DIS, + Help "Auto Precharge Enable for DDR5: O=Auto, 1=Disable, 2=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_Lp5SplitACTEnable, "Lp5 SplitACT Enable", &gPlatformFspPkgTokenSpaceGuid_Lp5SplitACTEnable, + Help "SplitACT enable for LP5" + Combo $gPlatformFspPkgTokenSpaceGuid_CccHalfFrequency, "CCC Half Frequency", &gPlatformFspPkgTokenSpaceGuid_CccHalfFrequency, + Help "CCC Half Frequency (CccGear4) Mode: 0 = Auto (Default), 1 = Disable, 2 = GroupGv0 (SaGv0 only), 3 = GroupGv1 (Up to SaGv1), 4 = GroupGv2 (Up to SaGv2), 5 = GroupGv3 (Up to SaGv3)" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMNTODT, "DIMM Non-Target ODT Training", &EN_DIS, + Help "Enables/Disable DIMM Non-Target ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RXUNMATCHEDCAL, "Unmatched Rx Calibration", &EN_DIS, + Help "Enable/Disable Rx Unmatched Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_PPR, "Hard Post Package Repair", &EN_DIS, + Help "Deprecated" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprTestType, "PPR Test Type", HEX, + Help "Deprecated" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PprRunOnce, "PPR Run Once", &EN_DIS, + Help "When Eanble, PPR will run only once and then is disabled at next training cycle" + Combo $gPlatformFspPkgTokenSpaceGuid_PprRunAtFastboot, "PPR Run During Fastboot", &EN_DIS, + Help "Deprecated" + Combo $gPlatformFspPkgTokenSpaceGuid_PprRepairType, "PPR Repair Type", &gPlatformFspPkgTokenSpaceGuid_PprRepairType, + Help "PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair" + Combo $gPlatformFspPkgTokenSpaceGuid_PprErrorInjection, "PPR Error Injection", &EN_DIS, + Help "When Eanble, PPR will inject bad rows during testing" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairController, "PPR Repair Controller", HEX, + Help "Deprecated" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairChannel, "PPR Repair Channel", HEX, + Help "Deprecated" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairDimm, "PPR Repair Dimm", HEX, + Help "Deprecated" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairRank, "PPR Repair Rank", HEX, + Help "Deprecated" + "Valid range: 0x00 ~ 0x01" + Combo $gPlatformFspPkgTokenSpaceGuid_MsHashInterleaveBit, "Memory Slice Hash LSB Bit", &gPlatformFspPkgTokenSpaceGuid_MsHashInterleaveBit, + Help "Memory Slice (Controller) Hash LSB bit. Valid values are 0..7 for BITS 6..13; used when MsHashOverride is set" + EditNum $gPlatformFspPkgTokenSpaceGuid_MsHashMask, "Memory Slice Hash Mask", HEX, + Help "Memory Slice (Controller) Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum); used when MsHashOverride is set" + "Valid range: 0x0000 ~ 0x3FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairRow, "PPR Repair Row", HEX, + Help "Deprecated" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairPhysicalAddrLow, "PPR Repair Physical Address Low", HEX, + Help "Deprecated" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairPhysicalAddrHigh, "PPR Repair Physical Address High", HEX, + Help "Deprecated" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairBankGroup, "PPR Repair BankGroup", HEX, + Help "Deprecated" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_LVRAUTOTRIM, "LVR Auto Trim", &EN_DIS, + Help "Enable/disable LVR Auto Trim" + Combo $gPlatformFspPkgTokenSpaceGuid_OPTIMIZECOMP, "Compensation Optimization", &EN_DIS, + Help "Enable/Disable Compensation Optimization" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTRETRAIN, "Write DQ/DQS Retraining", &EN_DIS, + Help "Enable/Disable Write DQ/DQS Retraining" + Combo $gPlatformFspPkgTokenSpaceGuid_PHASECLKCAL, "DCC Phase Clk Calibration", &EN_DIS, + Help "Enable/disable DCC Phase Clk Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_TLINECLKCAL, "DCC Tline Clk Calibration", &EN_DIS, + Help "Enable/disable DCC Tline Clk Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_DCCPISERIALCAL, "DCC Tline Serializer Calibration", &EN_DIS, + Help "Enable/disable DCC PI Serializer Calibratio" + Combo $gPlatformFspPkgTokenSpaceGuid_RDDQODTT, "RDDQODTT", &EN_DIS, + Help "Enable/disable Read DQ ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDCTLET, "RDCTLET", &EN_DIS, + Help "Enable/disable Read CTLE Training" + Combo $gPlatformFspPkgTokenSpaceGuid_EMPHASIS, "RxVref Pre EMPHASIS Training", &EN_DIS, + Help "Enable/Disable Pre EMPHASIS Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RXDQSVOCC, "RX DQS VOC Centring Training", &EN_DIS, + Help "Enable/Disable RX DQS VOC Centring Training" + EditNum $gPlatformFspPkgTokenSpaceGuid_NModeSupport, "NMode", HEX, + Help "System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N" + "Valid range: 0x00 ~ 0x02" + EditNum $gPlatformFspPkgTokenSpaceGuid_LpddrRttWr, "LPDDR ODT RttWr", HEX, + Help "Initial RttWr for LP4/5 in Ohms. 0x0 - Auto" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_RetrainOnFastFail, "Retrain on Fast flow Failure", &EN_DIS, + Help "Restart MRC in Cold mode if SW MemTest fails during Fast flow." + EditNum $gPlatformFspPkgTokenSpaceGuid_LpddrRttCa, "LPDDR ODT RttCa", HEX, + Help "Initial RttCa for LP4/5 in Ohms. 0x0 - Auto" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTDIMMDFE, "DIMM DFE Training", &EN_DIS, + Help "Enable/Disable DIMM DFE Training" + Combo $gPlatformFspPkgTokenSpaceGuid_DDR5ODTTIMING, "DDR5 ODT Timing Config", &EN_DIS, + Help "Enable/Disable DDR5 ODT TIMING CONFIG" + Combo $gPlatformFspPkgTokenSpaceGuid_HobBufferSize, "HobBufferSize", &gPlatformFspPkgTokenSpaceGuid_HobBufferSize, + Help "Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size)." + Combo $gPlatformFspPkgTokenSpaceGuid_ECT, "Early Command Training", &EN_DIS, + Help "Enables/Disable Early Command Training" + Combo $gPlatformFspPkgTokenSpaceGuid_SOT, "SenseAmp Offset Training", &EN_DIS, + Help "Enables/Disable SenseAmp Offset Training" + Combo $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D, "Early ReadMPR Timing Centering 2D", &EN_DIS, + Help "Enables/Disable Early ReadMPR Timing Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDMPRT, "Read MPR Training", &EN_DIS, + Help "Enables/Disable Read MPR Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RCVET, "Receive Enable Training", &EN_DIS, + Help "Enables/Disable Receive Enable Training" + Combo $gPlatformFspPkgTokenSpaceGuid_JWRL, "Jedec Write Leveling", &EN_DIS, + Help "Enables/Disable Jedec Write Leveling" + Combo $gPlatformFspPkgTokenSpaceGuid_EWRTC2D, "Early Write Time Centering 2D", &EN_DIS, + Help "Enables/Disable Early Write Time Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_ERDTC2D, "Early Read Time Centering 2D", &EN_DIS, + Help "Enables/Disable Early Read Time Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_UNMATCHEDWRTC1D, "Unmatched Write Time Centering 1D", &EN_DIS, + Help "Enable/Disable Unmatched Write Time Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTC1D, "Write Timing Centering 1D", &EN_DIS, + Help "Enables/Disable Write Timing Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_WRVC1D, "Write Voltage Centering 1D", &EN_DIS, + Help "Enables/Disable Write Voltage Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDTC1D, "Read Timing Centering 1D", &EN_DIS, + Help "Enables/Disable Read Timing Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTT, "Dimm ODT Training", &EN_DIS, + Help "Enables/Disable Dimm ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMRONT, "DIMM RON Training", &EN_DIS, + Help "Enables/Disable DIMM RON Training" + Combo $gPlatformFspPkgTokenSpaceGuid_WRDSEQT, "Write Drive Strength Training", &EN_DIS, + Help "Enables/Disable Write Drive Strength Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDEQT, "Read Equalization Training", &EN_DIS, + Help "Enables/Disable Read Equalization Training" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTC2D, "Write Timing Centering 2D", &EN_DIS, + Help "Enables/Disable Write Timing Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDTC2D, "Read Timing Centering 2D", &EN_DIS, + Help "Enables/Disable Read Timing Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_WRVC2D, "Write Voltage Centering 2D", &EN_DIS, + Help "Enables/Disable Write Voltage Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDVC2D, "Read Voltage Centering 2D", &EN_DIS, + Help "Enables/Disable Read Voltage Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDVC, "Command Voltage Centering", &EN_DIS, + Help "Enables/Disable Command Voltage Centering" + Combo $gPlatformFspPkgTokenSpaceGuid_LCT, "Late Command Training", &EN_DIS, + Help "Enables/Disable Late Command Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RTL, "Round Trip Latency Training", &EN_DIS, + Help "Enables/Disable Round Trip Latency Training" + Combo $gPlatformFspPkgTokenSpaceGuid_TAT, "Turn Around Timing Training", &EN_DIS, + Help "Enables/Disable Turn Around Timing Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RMTEVENODD, "Rmt Even Odd", &EN_DIS, + Help "Enables/Disable Rmt Even Odd" + Combo $gPlatformFspPkgTokenSpaceGuid_ALIASCHK, "DIMM SPD Alias Test", &EN_DIS, + Help "Enables/Disable DIMM SPD Alias Test" + Combo $gPlatformFspPkgTokenSpaceGuid_RCVENC1D, "Receive Enable Centering 1D", &EN_DIS, + Help "Enables/Disable Receive Enable Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_RMC, "Retrain Margin Check", &EN_DIS, + Help "Enables/Disable Retrain Margin Check" + Combo $gPlatformFspPkgTokenSpaceGuid_EccSupport, "ECC Support", &EN_DIS, + Help "Enables/Disable ECC Support" + Combo $gPlatformFspPkgTokenSpaceGuid_DLLDCC, "DLL DCC Calibration", &EN_DIS, + Help "Enables/Disable DLL DCC Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_DLLBWSEL, "DLL BW Select Calibration", &EN_DIS, + Help "Enables/Disable DLL BW Select Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_Ibecc, "Ibecc", &EN_DIS, + Help "In-Band ECC Support" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccParity, "IbeccParity", &EN_DIS, + Help "In-Band ECC Parity Control" + Combo $gPlatformFspPkgTokenSpaceGuid_MsHashEnable, "MsHashEnable", &EN_DIS, + Help "Controller Hash Enable: 0=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode, "IbeccOperationMode", &gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode, + Help "In-Band ECC Operation Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionEnable, "IbeccProtectedRegionEnable", &EN_DIS, + Help "In-Band ECC Protected Region Enable " + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5PreEmpDn, "NnFlex Override for LP5 PreEmpDn", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[3], MR58 encoding" + "Valid range: 0x00 ~ 0x03" + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionBase, "IbeccProtectedRegionBases", HEX, + Help "IBECC Protected Region Bases per IBECC instance" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionMask, "IbeccProtectedRegionMasks", HEX, + Help "IBECC Protected Region Masks" + "Valid range: 0x00 ~ 0x3FFF" + Combo $gPlatformFspPkgTokenSpaceGuid_RemapEnable, "Memory Remap", &EN_DIS, + Help "Enables/Disable Memory Remap" + Combo $gPlatformFspPkgTokenSpaceGuid_RankInterleave, "Rank Interleave support", &EN_DIS, + Help "Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time." + Combo $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave, "Enhanced Interleave support", &EN_DIS, + Help "Enables/Disable Enhanced Interleave support" + Combo $gPlatformFspPkgTokenSpaceGuid_ChHashEnable, "Ch Hash Support", &EN_DIS, + Help "Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn, "DDR PowerDown and idle counter", &EN_DIS, + Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" + Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr, "DDR PowerDown and idle counter", &EN_DIS, + Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" + Combo $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna, "SelfRefresh Enable", &EN_DIS, + Help "Enables/Disable SelfRefresh Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr, "Throttler CKEMin Defeature", &EN_DIS, + Help "Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)" + Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat, "Throttler CKEMin Defeature", &EN_DIS, + Help "Enables/Disable Throttler CKEMin Defeature" + Combo $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure, "Exit On Failure (MRC)", &EN_DIS, + Help "Enables/Disable Exit On Failure (MRC)" + Combo $gPlatformFspPkgTokenSpaceGuid_WCKPADDCCCAL, "Wck Pad DCC Calibration", &EN_DIS, + Help "Enable/disable Wck Pad DCC Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_DCCPICODELUT, "DCC PI Code LUT Calibration", &EN_DIS, + Help "Enable/Disable DCC PI Code LUT Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_RDVC1D, "Read Voltage Centering 1D", &EN_DIS, + Help "Enable/Disable Read Voltage Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_TXTCO, "TxDqTCO Comp Training", &EN_DIS, + Help "Enable/Disable TxDqTCO Comp Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CLKTCO, "ClkTCO Comp Training", &EN_DIS, + Help "Enable/Disable ClkTCO Comp Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDSR, "CMD Slew Rate Training", &EN_DIS, + Help "Enable/Disable CMD Slew Rate Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ, "CMD Drive Strength and Tx Equalization", &EN_DIS, + Help "Enable/Disable CMD Drive Strength and Tx Equalization" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTCA, "DIMM CA ODT Training", &EN_DIS, + Help "Enable/Disable DIMM CA ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDVREFDC, "Read Vref Decap Training*", &EN_DIS, + Help "Enable/Disable Read Vref Decap Training*" + Combo $gPlatformFspPkgTokenSpaceGuid_RMTBIT, "Rank Margin Tool Per Bit", &EN_DIS, + Help "Enable/Disable Rank Margin Tool Per Bit" + Combo $gPlatformFspPkgTokenSpaceGuid_REFPI, "Ref PI Calibration", &EN_DIS, + Help "Enable/Disable Ref PI Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_VCCCLKFF, "VccClk FF Offset Correction", &gPlatformFspPkgTokenSpaceGuid_VCCCLKFF, + Help "Enable/Disable VccClk FF Offset Correction" + Combo $gPlatformFspPkgTokenSpaceGuid_DATAPILIN, "Data PI Linearity Calibration", &EN_DIS, + Help "Enable/Disable {Data PI Linearity Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_DDR5XTALK, "Ddr5 Rx Cross-Talk Cancellation", &EN_DIS, + Help "Enable/Disable {Ddr5 Rx Cross-Talk Cancellation" + Combo $gPlatformFspPkgTokenSpaceGuid_RetrainToWorkingChannel, "Retrain On Working Channel", &EN_DIS, + Help "Enables/Disable Retrain On Working Channel feature" + Combo $gPlatformFspPkgTokenSpaceGuid_RowPressEn, "Row Press", &EN_DIS, + Help "Enables/Disable Row Press feature" + Combo $gPlatformFspPkgTokenSpaceGuid_DBI, "DBI feature", &EN_DIS, + Help "Enables/Disable DBI feature" + Combo $gPlatformFspPkgTokenSpaceGuid_IsDdr5MR7WicaSupported, "DDR5 MR7 WICA support", &EN_DIS, + Help "Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment" + Combo $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, "Ch Hash Interleaved Bit", &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, + Help "Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8" + Combo $gPlatformFspPkgTokenSpaceGuid_WREQT, "Write Equalization Training", &EN_DIS, + Help "Enables/Disables Write Equalization Training" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChHashMask, "Ch Hash Mask", HEX, + Help "Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC" + "Valid range: 0x0000 ~ 0x3FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CccPinsInterleaved, "CccPinsInterleaved", HEX, + Help "Interleaving mode of CCC pins which depends on board routing: 0=Disable, 1=Enable" + "Valid range: 0x0000 ~ 0x3FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr, "Throttler CKEMin Timer", HEX, + Help "Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Dfault is 0x00" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_AllowOppRefBelowWriteThrehold, "Allow Opp Ref Below Write Threhold", &EN_DIS, + Help "Allow opportunistic refreshes while we don't exit power down." + EditNum $gPlatformFspPkgTokenSpaceGuid_WriteThreshold, "Write Threshold", HEX, + Help "Number of writes that can be accumulated while CKE is low before CKE is asserted." + "Valid range: 0x00 ~ 0x3F" + Combo $gPlatformFspPkgTokenSpaceGuid_McRefreshRate, "MC_REFRESH_RATE", &gPlatformFspPkgTokenSpaceGuid_McRefreshRate, + Help "Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh" + Combo $gPlatformFspPkgTokenSpaceGuid_RefreshWm, "Refresh Watermarks", &gPlatformFspPkgTokenSpaceGuid_RefreshWm, + Help "Refresh Watermarks: 0-Low, 1-High (default)" + Combo $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable, "User Manual Threshold", &EN_DIS, + Help "Disabled: Predefined threshold will be used.\nEnabled: User Input will be used." + Combo $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable, "User Manual Budget", &EN_DIS, + Help "Disabled: Configuration of memories will defined the Budget value.\nEnabled: User Input will be used." + Combo $gPlatformFspPkgTokenSpaceGuid_PowerDownMode, "Power Down Mode", &gPlatformFspPkgTokenSpaceGuid_PowerDownMode, + Help "This option controls command bus tristating during idle periods" + EditNum $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter, "Pwr Down Idle Timer", HEX, + Help "The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout, "Page Close Idle Timeout", &gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout, + Help "This option controls Page Close Idle Timeout" + EditNum $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated, "Bitmask of ranks that have CA bus terminated", HEX, + Help "LPDDR5: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SafeModeOverride, "MRC Safe Mode Override", HEX, + Help "SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3] Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4] Enable SaGv safe mode override" + "Valid range: 0x00 ~ 0x7" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5PreEmpUp, "NnFlex Override for LP5 PreEmpUp", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[4], MR58 encoding" + "Valid range: 0x00 ~ 0x03" + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjAddrBase, "IbeccEccInjAddrBase", HEX, + Help "Address to match against for ECC error injection. Example: 1 = 32MB, 2 = 64MB" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DdrSafeMode, "DDR Phy Safe Mode Support", HEX, + Help "DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]: Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]: PLL Operation, DdrSafeMode[6]: Safe ODT" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_McSafeMode, "Mc Safe Mode Support", HEX, + Help "McSafeMode[0]: Reserved, McSafeMode[1]: OppSR" + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CleanMemory, "Ask MRC to clear memory content", &EN_DIS, + Help "Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory." + Combo $gPlatformFspPkgTokenSpaceGuid_RetryCount, "Tseg Retry Count", &gPlatformFspPkgTokenSpaceGuid_RetryCount, + Help "Tseg Retry count will increase based on TSEG Region Fail count" + Combo $gPlatformFspPkgTokenSpaceGuid_MrcPprStatus, "Mrc Ppr Status", &gPlatformFspPkgTokenSpaceGuid_MrcPprStatus, + Help " Get Mrc PPR Status after PPR Recovery flow will get Trigger" + Combo $gPlatformFspPkgTokenSpaceGuid_TsegMemoryTestStatus, "Tseg Memory Test Status", &gPlatformFspPkgTokenSpaceGuid_TsegMemoryTestStatus, + Help " If enabled, PPR Recovery flow will get Trigger" + Combo $gPlatformFspPkgTokenSpaceGuid_PprRecoveryStatusEnable, "Ppr Recovery Status Enable", &EN_DIS, + Help "0: Disabled(Default), 1: Enabled. If enabled, PPR Recovery flow will get Trigger." + Combo $gPlatformFspPkgTokenSpaceGuid_SafeLoadingBiosEnableState, "Safe Loading Bios Enable State", &EN_DIS, + Help "0: Disabled(Default), 1: Enabled. If enabled, Memory diagnostic will perform for TSEG Region." + Combo $gPlatformFspPkgTokenSpaceGuid_MrcBdatTestType, "BDAT test type", &gPlatformFspPkgTokenSpaceGuid_MrcBdatTestType, + Help "When BdatEnable is set to TRUE, this option selects the type of data which will be populated in the BIOS Data ACPI Tables: 0=RMT, 1=RMT Per Bit, 2=Margin 2D." + Combo $gPlatformFspPkgTokenSpaceGuid_MrcBdatEnable, "MrcBdatEnable", &EN_DIS, + Help "0: Disabled(Default), 1: Enabled. This field enables the generation of the BIOS DATA ACPI Tables: 0=FALSE, 1=TRUE." + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMrcRetraining, "DisableMrcRetraining", &EN_DIS, + Help "0: Disabled(Default), 1: Enabled. Enable/Disable DisableMrcRetraining" + EditNum $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount, "RMTLoopCount", HEX, + Help "Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO" + "Valid range: 0 ~ 0x20" + Combo $gPlatformFspPkgTokenSpaceGuid_DdrOneDpc, "DdrOneDpc", &gPlatformFspPkgTokenSpaceGuid_DdrOneDpc, + Help "DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, or on both (default)" + EditNum $gPlatformFspPkgTokenSpaceGuid_VddqVoltageOverride, "Vddq Voltage Override", HEX, + Help "# is multiple of 1mV where 0 means Auto." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccIogVoltageOverride, "VccIog Voltage Override", HEX, + Help "# is multiple of 1mV where 0 means Auto." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccClkVoltageOverride, "VccClk Voltage Override", HEX, + Help "# is multiple of 1mV where 0 means Auto." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr, "ThrtCkeMinTmrLpddr", HEX, + Help "Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, 0x00=Default" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5WckDcaWr, "NnFlex Override for LP5 WckDcaWr", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[5], 4-bit 2's complement, valid range: [-7..7]" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_MarginLimitL2, "Margin limit check L2", HEX, + Help "Margin limit check L2 threshold: 100=Default" + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ExtendedBankHashing, "Extended Bank Hashing", &EN_DIS, + Help "Eanble/Disable ExtendedBankHashing" + EditNum $gPlatformFspPkgTokenSpaceGuid_DrfmBrc, "DRFM Blast Radius Configuration", HEX, + Help "Row Hammer DRFM Blast Radius Configuration determines number of victim rows around aggressor row targeted to send the DRFM sequence to: 2=BlastRadius 2, 3=BlastRadius 3, 4=BlastRadius 4" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Lp5CccConfig, "LP5 Command Pins Mapping", HEX, + Help "BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CmdMirror, "Command Pins Mirrored", HEX, + Help "BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure, "Time Measure", &EN_DIS, + Help "Time Measure: 0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DvfsqEnabled, "DVFSQ Enabled", &EN_DIS, + Help "Enable/Disable DVFSQ" + Combo $gPlatformFspPkgTokenSpaceGuid_DvfscEnabled, "E-DVFSC Enabled", &EN_DIS, + Help "Eanble/Disable DVFSC" + Combo $gPlatformFspPkgTokenSpaceGuid_DCCDDR5READDCA, "Ddr5 Dca Training", &EN_DIS, + Help "Enable/Disable DDR5 Dca Training" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRunWCHMATS8, "PPR Run WCHMATS8", HEX, + Help "Run WCHMATS8 in Post Package Repair flow" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRunRetention, "PPR Run Retention", HEX, + Help "Run Data Retention in Post Package Repair flow" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRunXMarch, "PPR Run XMarch", HEX, + Help "Run XMarch in Post Package Repair flow" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRunXMarchG, "PPR Run XMarchG", HEX, + Help "Run XMarchG in Post Package Repair flow" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRunYMarchShort, "PPR Run YMarchShort", HEX, + Help "Run YMarchShort in Post Package Repair flow" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRunYMarchLong, "PPR Run YMarchLong", HEX, + Help "Run YMarchLong in Post Package Repair flow" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRunMmrw, "PPR Run Mmrw", HEX, + Help "Run Mmrw in Post Package Repair flow" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprTestDisabled, "PPR Test Disabled", HEX, + Help "Don't run any test in Post Package Repair flow" + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprEntryInfo, "PPR Entry Info", HEX, + Help "PPR Repair Info" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprEntryAddress, "PPR Entry Address", HEX, + Help "PPR Repair Memory Address" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_RDTCIDLE, "Read Vref Decap Training*", &EN_DIS, + Help "Enable/Disable Read Timing Centering Training with SR stress*" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRetryLimit, "PPR Retry Limit", HEX, + Help "Sets a limit on the number of times Memory Testing will be retried after attempting to repair using PPR." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_Use1p5ReadPostamble, "Use 1p5 Read Postamble", &EN_DIS, + Help "Enables/Disable using 1p5 tCK Read Postamble for higher freqencies" + Combo $gPlatformFspPkgTokenSpaceGuid_IsWckIdleExitEnabled, "IsWckIdleExitEnabled", &EN_DIS, + Help "Enables/Disables WCK Idle Exit" + Combo $gPlatformFspPkgTokenSpaceGuid_Lp5SafeSpeed, "LP5 Safe Speed", &EN_DIS, + Help "Enable / Disable LP5 Safe Speed feature" + Combo $gPlatformFspPkgTokenSpaceGuid_ForceInternalClkOn, "Force InternalClkOn", &EN_DIS, + Help "Force InternalClocksOn and TxPiOn to be set to 1 for frequencies >= 7467" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMRXOFFSET, "DIMM Rx Offset Calibration training", &EN_DIS, + Help "Enable/Disable DIMM Rx Offset Calibration training" + Combo $gPlatformFspPkgTokenSpaceGuid_FlexibleAnalogSettings, "Enable Flexible Analog Settings", &EN_DIS, + Help "Enable/Disable Flexible Analog Settings" + Combo $gPlatformFspPkgTokenSpaceGuid_ForceWRDSEQT2400, "Force WRDSEQT at 2400", &EN_DIS, + Help "Force Enable Write Drive Strength training at 2400" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5WckDcaRd, "NnFlex Override for LP5 WckDcaRd", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[6], 4-bit 2's complement, valid range: [-7..7]" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexLpddr5RttNT, "NnFlex Override for LP5 RttNT", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[7], MR41 encoding" + "Valid range: 0x00 ~ 0x07" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5DfeTap1, "NnFlex Override for DDR5 DfeTap1", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[0], 8-bit 2's complement, valid range: [-40..40]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5DfeTap2, "NnFlex Override for DDR5 DfeTap2", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[1], 8-bit 2's complement, valid range: [-15..15]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5RttWr, "NnFlex Override for DDR5 RttWr", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[2], MR34 encoding" + "Valid range: 0x00 ~ 0x07" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5RttNomWr, "NnFlex Override for DDR5 RttNomWr", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[3], MR35 encoding" + "Valid range: 0x00 ~ 0x07" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5RttNomRd, "NnFlex Override for DDR5 RttNomRd", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[4], MR35 encoding" + "Valid range: 0x00 ~ 0x07" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5RonUp, "NnFlex Override for DDR5 RonUp", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[5], MR5 encoding" + "Valid range: 0x00 ~ 0x02" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexDdr5RonDn, "NnFlex Override for DDR5 RonDn", HEX, + Help "Controlled by NnFlexDramOvrdMask bit[6], MR5 encoding" + "Valid range: 0x00 ~ 0x02" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexPhyOvrdMask, "NnFlex Phy Override Enable bit mask", HEX, + Help "Bitmask to enable PHY NnFlex overrides. [0]: PhyRxEqTap0 [1]: PhyRxEqTap1 [2]: PhyDqTcoComp [3]: PhyRxCtleR [4]: PhyRxCtleC [5]: PhyRxCtleRcmn [6]: PhyRxCtleEq [7]: PhyRxCtleTailCtl" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NnFlexDramOvrdMask, "NnFlex LP5/DDR5 Override Enable bit mask", HEX, + Help "Bitmask to enable LP5/DDR5 NnFlex overrides. [0]: Lp5Dfeq/Ddr5DfeTap1 [1]: Lp5PdDrvStr/Ddr5DfeTap2 [2]: Lp5SocOdt/Ddr5RttWr [3]: Lp5PreEmpDn/Ddr5RttNomWr [4]: Lp5PreEmpUp/Ddr5RttNomRd [5]: Lp5WckDcaWr/Ddr5RonUp [6]: Lp5WckDcaRd/Ddr5RonDn [7]: Lp5RttNT" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MrcPreMemRsvd, "MrcPreMemRsvd", &EN_DIS, + Help "Reserved for MRC Pre-Mem" + Combo $gPlatformFspPkgTokenSpaceGuid_UserBd, "Board Type", &gPlatformFspPkgTokenSpaceGuid_UserBd, + Help "MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server" + EditNum $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable, "Spd Address Table", HEX, + Help "Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TxtImplemented, "Enable/Disable MRC TXT dependency", &EN_DIS, + Help "When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieResizableBarSupport, "PCIE Resizable BAR Support", &EN_DIS, + Help "Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS, + Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices" + Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS, + Help "Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it" + Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType, + Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable, "Enable PCH HSIO PCIE Rx Set Ctle", HEX, + Help "Enable PCH PCIe Gen 3 Set CTLE Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle, "PCH HSIO PCIE Rx Set Ctle Value", HEX, + Help "PCH PCIe Gen 3 Set CTLE Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable, "Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp, "PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable, "Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph, "PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value", HEX, + Help "PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5, "PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0, "PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect, "HD Audio DMIC Link Clock Select", &gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect, + Help "Determines DMIC Clock Source. 0: Both, 1: ClkA, 2: ClkB" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable, "Enable Intel HD Audio (Azalia)", &EN_DIS, + Help "0: Disable, 1: Enable (Default) Azalia controller" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, + Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHdaEnable, "Enable HD Audio Link", &EN_DIS, + Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSdiEnable, "Enable HDA SDI lanes", HEX, + Help "Enable/disable HDA SDI lanes." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicEnable, "Enable HD Audio DMIC_N Link", HEX, + Help "Enable/disable HD Audio DMIC1 link. Muxed with SNDW3." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClkAPinMux, "DMIC ClkA Pin Muxing (N - DMIC number)", HEX, + Help "Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, + Help "Enable/disable HD Audio DSP feature." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicDataPinMux, "DMIC Data Pin Muxing", HEX, + Help "Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspEnable, "Enable HD Audio SSP0 Link", HEX, + Help "Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspSclkPinMux, "SSP Sclk Pin Muxing (N - SSP Number)", HEX, + Help "Determines SSP Sclk Pin muxing. See GPIOV2_*_MUXING_I2S*_SCLK" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspSfmrPinMux, "SSP Sfmr Pin Muxing (N - SSP Number)", HEX, + Help "Determines SSP Sfmr Pin muxing. See GPIOV2_*_MUXING_I2S*_SFMR" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspTxdPinMux, "SSP Txd Pin Muxing (N - SSP Number)", HEX, + Help "Determines SSP Txd Pin muxing. See GPIOV2_*_MUXING_I2S*_TXD" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspRxdPinMux, "SSP Rxd Pin Muxing (N - SSP Number)", HEX, + Help "Determines SSP Rxd Pin muxing. See GPIOV2_*_MUXING_I2S*_RXD" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndwEnable, "Enable HD Audio SoundWire#N Link", HEX, + Help "Enable/disable HD Audio SNDW#N link. Muxed with HDA." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, "iDisp-Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, + Help "iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, "iDisp-Link T-mode", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, + Help "iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdAudioSndwMultilaneEnable, "Sndw Multilane enablement", &EN_DIS, + Help "SoundWire Multiline enablement. Default is DISABLE. 0: DISABLE, 1: Two lines enabled, 2: Three lines enabled, 3: Four Lines enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkMultilaneClkPinMux, "SoundWire Clk Pin Muxing (N - SoundWire number)", HEX, + Help "Determines SoundWire Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_CLK*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkMultilaneData0PinMux, "SoundWire Multilane Data0 Pin Muxing (N - SoundWire number)", HEX, + Help "Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA0*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkMultilaneData1PinMux, "SoundWire Multilane Data1 Pin Muxing (N - SoundWire number)", HEX, + Help "Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA1*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkMultilaneData2PinMux, "SoundWire Multilane Data2 Pin Muxing (N - SoundWire number)", HEX, + Help "Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA2*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkMultilaneData3PinMux, "SoundWire Multilane Data3 Pin Muxing (N - SoundWire number)", HEX, + Help "Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA3*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect, "iDisplay Audio Codec disconnection", &EN_DIS, + Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdAudioSndwMultilaneSndwInterface, "Sndw Interface for Multilanes (N - SoundWire number)", &gPlatformFspPkgTokenSpaceGuid_PchHdAudioSndwMultilaneSndwInterface, + Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable." + EditNum $gPlatformFspPkgTokenSpaceGuid_ResetWaitTimer, "Audio Sub System IDs", HEX, + Help "Set default Audio Sub System IDs. If its set to 0 then value from Strap is used." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating, "HDA Power/Clock Gating (PGD/CGD)", &gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating, + Help "Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaTestLowFreqLinkClkSrc, "Low Frequency Link Clock Source (LFLCS)", &gPlatformFspPkgTokenSpaceGuid_PchHdaTestLowFreqLinkClkSrc, + Help "0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL)." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSubSystemIds, "Audio Sub System IDs", HEX, + Help "Set default Audio Sub System IDs. If its set to 0 then value from Strap is used." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwClockSourceSelect, "SoundWire clock source select", &EN_DIS, + Help "Select clock source for the SoundWire controllers. 0: XTAL, 1: Audio PLL." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding, "PCH LPC Enhance the port 8xh decoding", &EN_DIS, + Help "Original LPC only decodes one byte of port 80h." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage, "Usage type for ClkSrc", HEX, + Help "0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq, "ClkReq-to-ClkSrc mapping", HEX, + Help "Number of ClkReq signal assigned to ClkSrc" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkReqGpioMux, "Clk Req GPIO Pin", HEX, + Help "Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask, "Enable PCIE RP Mask", HEX, + Help "Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." + "Valid range: 0x00 ~ 0x00FFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, "Margin Limit Check", &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, + Help "Margin Limit Check. Choose level of margin check" + EditNum $gPlatformFspPkgTokenSpaceGuid_Lfsr1Mask, "Row Hammer pTRR LFSR1 Mask", HEX, + Help "Row Hammer pTRR LFSR1 Mask, 1/2^(value)" + "Valid range: 0x01 ~ 0xF" + Combo $gPlatformFspPkgTokenSpaceGuid_DramRfmMode, "Row Hammer DRAM Refresh Management Mode", &gPlatformFspPkgTokenSpaceGuid_DramRfmMode, + Help "Row Hammer Adaptive Refresh Management Level: 0-RFM (default), 1-ARFMLevel A, 2-ARFMLevel B, 3-ARFMLevel C, 4-Disable ARFM and RFM" + Combo $gPlatformFspPkgTokenSpaceGuid_TargetedRowRefreshMode, "Row Hammer Targeted Row Refresh Mode", &gPlatformFspPkgTokenSpaceGuid_TargetedRowRefreshMode, + Help "Row Hammer Targeted Row Refresh: 0-DRFM, 1-pTRR (default), 2-Disable DRFM and pTRR" + EditNum $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX, + Help "TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63" + "Valid range: 0x0A ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOffset, "Per-Atom-Cluster VF Offset", HEX, + Help "Array used to specifies the selected Atom Core Cluster Offset Voltage. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOffsetPrefix, "Per-Atom-Cluster VF Offset Prefix", HEX, + Help "Sets the PerAtomCLusterVoltageOffset value as positive or negative for the selected Core; 0: Positive ; 1: Negative." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageMode, "Per-Atom-Cluster Voltage Mode", HEX, + Help "Array used to specifies the selected Atom Core ClusterVoltage Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOverride, "Per-Atom-Cluster Voltage Override", HEX, + Help "Array used to specifies the selected Atom Core Cluster Voltage Override." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset, "Core VF Point Offset", HEX, + Help "Array used to specifies the Core Voltage Offset applied to the each selected VF Point. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, "Core VF Point Offset Prefix", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, + Help "Sets the CoreVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio, "Core VF Point Ratio", HEX, + Help "Array for the each selected Core VF Point to display the ration." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfConfigScope, "Core VF Configuration Scope", &gPlatformFspPkgTokenSpaceGuid_CoreVfConfigScope, + Help "Allows both all-core VF curve or per-core VF curve configuration; 0: All-core; 1: Per-core." + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOffset, "Per-core VF Offset", HEX, + Help "Array used to specifies the selected Core Offset Voltage. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOffsetPrefix, "Per-core VF Offset Prefix", HEX, + Help "Sets the PerCoreVoltageOffset value as positive or negative for the selected Core; 0: Positive ; 1: Negative." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PerCoreRatioOverride, "Per Core Max Ratio override", &EN_DIS, + Help "Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. 0: Disable, 1: enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageMode, "Per-core Voltage Mode", HEX, + Help "Array used to specifies the selected Core Voltage Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOverride, "Per-core Voltage Override", HEX, + Help "Array used to specifies the selected Core Voltage Override." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreRatio, "Per Core Current Max Ratio", HEX, + Help "Array for the Per Core Max Ratio" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomClusterRatio, "Atom Cluster Max Ratio", HEX, + Help "Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their max core ratio will be aligned." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PvdRatioThreshold, "Pvd Ratio Threshold for SOC/CPU die", HEX, + Help "Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio (P0 to Pn) to select the multiplier so that the output is within the DCO frequency range. As per the die selected, this threshold is applied to SA and MC/CMI PLL for SOC die and SA, Ring and Atom PLL for CPU die. Range 0-63. When the threshold is 0, static PVD ratio is selected based on the PVD Mode for SOC. 0: Default." + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PvdMode, "Pvd Mode SOC/CPU die", HEX, + Help "Array of PVD Mode. Value from 0 to 3 for SOC/CPU. 0x0 = div-1 (VCO = Output clock), 0x1 = div-2 (VCO = 2x Output clock), 0x2 = div-4 (VCO = 4x Output clock), 0x3 = div-8 (VCO = 8x Output clock)." + "Valid range: 0x0 ~ 0x3" + EditNum $gPlatformFspPkgTokenSpaceGuid_FllOverclockMode, "FLL Overclock Mode", HEX, + Help "Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated (3-5x) reference clock frequency and ratio limited to 63." + "Valid range: 0x0 ~ 0x3" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffset, "Ring VF Point Offset", HEX, + Help "Array used to specifies the Ring Voltage Offset applied to the each selected VF Point. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetPrefix, "Ring VF Point Offset Prefix", HEX, + Help "Sets the RingVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointRatio, "Ring VF Point Ratio", HEX, + Help "Array for the each selected Ring VF Point to display the ration." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SocDieSscEnable, "Soc Die SSC enable", &EN_DIS, + Help "Enable/Disable Soc-Die SSC Configuration. 0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_CoreOpPointReportingEn, "Core Operating Point Reporting", &gPlatformFspPkgTokenSpaceGuid_CoreOpPointReportingEn, + Help "Enables Core Operating point reporting. 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBclkOcFrequency, "CPU BCLK OC Frequency", HEX, + Help "CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is 40Mhz-1000Mhz." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SocBclkOcFrequency, "SOC BCLK OC Frequency", HEX, + Help "SOC BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is 40Mhz-1000Mhz." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DisablePerCoreMask, "Bitmask of disable cores", HEX, + Help "Core mask is a bitwise indication of which core should be disabled. 0x00=Default; Bit 0 - core 0, bit 7 - core 7." + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_GranularRatioOverride, "Granular Ratio Override", &EN_DIS, + Help "Enable or disable OC Granular Ratio Override. 0: Disable, 1: enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2VoltageScaleFactor, "Avx2 Voltage Guardband Scaling Factor", HEX, + Help "AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor." + "Valid range: 0x00 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset, "Ring PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + Combo $gPlatformFspPkgTokenSpaceGuid_OcPreMemRsvd, "OcPreMemRsvd", &EN_DIS, + Help "Reserved for OC Pre-Mem" + Combo $gPlatformFspPkgTokenSpaceGuid_PchIshEnable, "Enable PCH ISH Controller", &EN_DIS, + Help "0: Disable, 1: Enable (Default) ISH Controller" +EndPage + +Page "Overclocking" + Combo $gPlatformFspPkgTokenSpaceGuid_SaOcSupport, "Enable/Disable SA OcSupport", &EN_DIS, + Help "Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport" + EditNum $gPlatformFspPkgTokenSpaceGuid_VfPointCount, "VF Point Count", HEX, + Help "Number of supported Voltage & Frequency Point Offset" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessVmaxLimit, "ProcessVmaxLimit", HEX, + Help "Disabling Process Vmax Limit will allow user to set any voltage" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CorePllCurrentRefTuningOffset, "CorePllCurrentRefTuningOffset", HEX, + Help "Core PLL Current Reference Tuning Offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllCurrentRefTuningOffset, "RingPllCurrentRefTuningOffset", HEX, + Help "Ring PLL Current Reference Tuning Offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IaAtomPllCurrentRefTuningOffset, "IaAtomPllCurrentRefTuningOffset", HEX, + Help "IaAtom PLL Current Reference Tuning Offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreMinRatio, "CoreMinRatio", HEX, + Help "equest Core Min Ratio. Limit Core minimum ratio for extreme overclocking. Default 0 indicates no request" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NegativeTemperatureReporting, "CoreMiNegativeTemperatureReportingnRatio", HEX, + Help "Negative Temperature Reporting Enable. 0: Disable, 1: enable" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcorePowerDensityThrottle, "PcorePowerDensityThrottle", HEX, + Help "Power Density Throttle control allows user to disable P-core" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcorePowerDensityThrottle, "EcorePowerDensityThrottle", HEX, + Help "Power Density Throttle control allows user to disable P-core" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_OcSupport, "Over clocking support", &EN_DIS, + Help "Over clocking support; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_UnderVoltProtection, "UnderVolt Protection", &EN_DIS, + Help "When UnderVolt Protection is enabled, user will be not be able to program under voltage in OS runtime. 0: Disabled; 1: Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, "Realtime Memory Timing", &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, + Help "0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE." + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride, "core voltage override", HEX, + Help "The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset, "Core Turbo voltage Offset", HEX, + Help "The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000" + "Valid range: 0x00 ~ 0x3E8" + EditNum $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset, "Core PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset, "AVX2 Ratio Offset", HEX, + Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." + "Valid range: 0x00 ~ 0x1F" + Combo $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage, "BCLK Adaptive Voltage Enable", &EN_DIS, + Help "When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_RingDownBin, "Ring Downbin", &EN_DIS, + Help "Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_Lfsr0Mask, "Row Hammer pTRR LFSR0 Mask", HEX, + Help "Row Hammer pTRR LFSR0 Mask, 1/2^(value)" + "Valid range: 0x01 ~ 0xF" +EndPage + +Page "Debug" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, + Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMmioBase, "Serial Io Uart Debug Mmio Base", HEX, + Help "Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode = SerialIoUartPci." + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, + Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." + Combo $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, "SerialDebugMrcLevel", &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, + Help "MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, "Serial Io Uart Debug Controller Number", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, + Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, "Serial Io Uart Debug Parity", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, + Help "Set default Parity." + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate, "Serial Io Uart Debug BaudRate", DEC, + Help "Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000" + "Valid range: 0 ~ 6000000" + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, "Serial Io Uart Debug Stop Bits", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, + Help "Set default stop bits." + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits, "Serial Io Uart Debug Data Bits", HEX, + Help "Set default word length. 0: Default, 5,6,7,8" + "Valid range: 0x0 ~ 0x08" + EditNum $gPlatformFspPkgTokenSpaceGuid_ImguClkOutEn, "IMGU CLKOUT Configuration", HEX, + Help "The configuration of IMGU CLKOUT, 0: Disable;1: Enable." + "Valid range: 0x0 ~ 0x08" + Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable, "Enable/Disable SA IPU", &EN_DIS, + Help "Enable(Default): Enable SA IPU, Disable: Disable SA IPU" + Combo $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock, "Disable and Lock Watch Dog Register", &EN_DIS, + Help "Set 1 to clear WDT status, then disable and lock WDT registers." + Combo $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts, "HECI Timeouts", &EN_DIS, + Help "0: Disable, 1: Enable (Default) timeout check for HECI" + Combo $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2, "HECI2 Interface Communication", &EN_DIS, + Help "Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space." + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck, "Check HECI message before send", &EN_DIS, + Help "Test, 0: disable, 1: enable, Enable/Disable message check." + Combo $gPlatformFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS, + Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value" + Combo $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable, "Enable KT device", &EN_DIS, + Help "Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device." + Combo $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS, + Help "Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop" + Combo $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck, "Skip CPU replacement check", &EN_DIS, + Help "Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check" + Combo $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob, "Skip MBP HOB", &EN_DIS, + Help "Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob." + Combo $gPlatformFspPkgTokenSpaceGuid_HeciCommunication, "HECI Communication", &EN_DIS, + Help "Test, 0: POR, 1: enable, 2: disable, Disables HECI communication causing ME to enter error state." + Combo $gPlatformFspPkgTokenSpaceGuid_HeciCommunication3, "HECI3 Interface Communication", &EN_DIS, + Help "Test, 0: POR, 1: enable, 2: disable, Adds or Removes HECI3 Device from PCI space." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, + Help "Select ISA Serial Base address. Default is 0x3F8." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, + Help "Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200." + EditNum $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort, "Post Code Output Port", HEX, + Help "This option configures Post Code Output Port" + "Valid range: 0x0 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_I2cPostCodeEnable, "Enable/Disable I2cPostcode", &EN_DIS, + Help "Enable (Default): Postcode via I2C, Disable: Postcode via Port80" + EditNum $gPlatformFspPkgTokenSpaceGuid_FspmValidationPtr, "FSPM Validation Pointer", HEX, + Help "Point to FSPM Validation configuration structure" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ExtendedBiosDecodeRange, "Extended BIOS Support", &EN_DIS, + Help "Enable/Disable Extended BIOS Region Support. Default is DISABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeEnable, "Extented BIOS Direct Read Decode enable", &EN_DIS, + Help "Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. 0: disabled (default), 1: enabled" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeBase, "Extended BIOS Direct Read Decode Range base", HEX, + Help "Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeLimit, "Extended BIOS Direct Read Decode Range limit", HEX, + Help "Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode." + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusEnable, "Enable SMBus", &EN_DIS, + Help "Enable/disable SMBus controller." + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS, + Help "Enable SMBus ARP support." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX, + Help "The number of elements in the RsvdSmbusAddressTable." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX, + Help "SMBUS Base Address (IO space)." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable, "Enable SMBus Alert Pin", &EN_DIS, + Help "Enable SMBus Alert Pin." + EditNum $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr, "Point of RsvdSmbusAddressTable", HEX, + Help "Array of addresses reserved for non-ARP-capable SMBus devices." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating, "Smbus dynamic power gating", &EN_DIS, + Help "Disable or Enable Smbus dynamic power gating." + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS, + Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set." +EndPage + +Page "Security(PreMem)" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosSize, "BiosSize", HEX, + Help "The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected Range) so that a BIOS Update Script can be stored in the DPR." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS, + Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS, + Help "Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect. 0: Disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet, "Skip Stop PBET Timer Enable/Disable", &EN_DIS, + Help "Skip Stop PBET Timer; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ResetAux, "Reset Auxiliary content", &EN_DIS, + Help "Reset Auxiliary content, 0: Disabled, 1: Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_TseEnable, "TseEnable", &EN_DIS, + Help "Enable/Disable. 0: Disable, Enable/Disable Tse feature, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_TdxEnable, "Enable or Disable TDX", &EN_DIS, + Help "Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager (VMM)/hypervisor 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_GenerateNewTmeKey, "MKTME Key-Id Bits Override Enable", &EN_DIS, + Help "Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager (VMM)/hypervisor 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_TmeExcludeBase, "TME Exclude Base Address", HEX, + Help "TME Exclude Base Address." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TmeExcludeSize, "TME Exclude Size Value", HEX, + Help "TME Exclude Size Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdxActmModuleAddr, "TdxActmModuleAddr", HEX, + Help "Base address of Tdx Actm module, used for launching the Actm" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdxActmModuleSize, "TdxActmModuleSize", HEX, + Help "size of Tdx Actm module, used for launching the Actm" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdxSeamldrSvn, "TdxSeamldrSvn", HEX, + Help "TdxSeamldrSvn" + "Valid range: 0x00 ~ 0xFF" +EndPage + +Page "Management Engine(PreMem)" +EndPage + +Page "CPU(PreMem)" + EditNum $gPlatformFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[6]", HEX, + Help "BgpdtHash values" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr, "BiosGuardAttr", HEX, + Help "BiosGuardAttr default values" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr, "BiosGuardModulePtr", HEX, + Help "BiosGuardModulePtr default values" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcProvisionEav, "EcProvisionEav", HEX, + Help "EcProvisionEav function pointer. \n @code typedef EFI_STATUS (EFIAPI *EC_PROVISION_EAV) (IN UINT32 Eav, OUT UINT8 *ReturnValue); @endcode" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcBiosGuardCmdLock, "EcBiosGuardCmdLock", HEX, + Help "EcBiosGuardCmdLock function pointer. \n @code typedef EFI_STATUS (EFIAPI *EC_CMD_LOCK) (OUT UINT8 *ReturnValue); @endcode" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeHostDeviceEnabled, "PCH eSPI Host and Device BME enabled", &EN_DIS, + Help "PCH eSPI Host and Device BME enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration, "PCH eSPI Link Configuration Lock (SBLCL)", &EN_DIS, + Help "Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target addresseses from range 0x0 - 0x7FF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiHostC10ReportEnable, "Enable Host C10 reporting through eSPI", &EN_DIS, + Help "Enable/disable Host C10 reporting to Device via eSPI Virtual Wire." + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable, "Espi Lgmr Memory Range decode ", &EN_DIS, + Help "This option enables or disables espi lgmr " + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiPmHAE, "PCH eSPI PmHAE", &EN_DIS, + Help "This option enables or disables espi lgmr " + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiHideNonFatalErrors, "PCH eSPI HideNonFatalErrors ", &EN_DIS, + Help "This option enables or disables espi lgmr " + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiNmiEnableCs1, "PCH eSPI NmiEnableCs1 ", &EN_DIS, + Help "Set this bit to enable eSPI NMI VW events to be processed by the SOC" + Combo $gPlatformFspPkgTokenSpaceGuid_BootMaxFrequency, "Boot max frequency", &EN_DIS, + Help "Enable Boot Maximum Frequency in CPU strap. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_BistOnReset, "BIST on Reset", &EN_DIS, + Help "Enable/Disable BIST (Built-In Self Test) on reset. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ReduceXecores, "Reduce XeCores", &EN_DIS, + Help "Enable/Disable Reduce XeCores. 0: Disable(strap=1) ; 1: Enable(strap=0." + Combo $gPlatformFspPkgTokenSpaceGuid_VmxEnable, "Enable or Disable VMX", &EN_DIS, + Help "Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_FClkFrequency, "Processor Early Power On Configuration FCLK setting", &gPlatformFspPkgTokenSpaceGuid_FClkFrequency, + Help "FCLK frequency can take values of 400MHz, 800MHz and 1GHz. 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogEnable, "Enable CPU CrashLog", &EN_DIS, + Help "Enable or Disable CPU CrashLog; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_TmeEnable, "Enable or Disable TME", &EN_DIS, + Help "Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "CPU Run Control", &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, + Help "Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: No Change" + Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable, "CPU Run Control Lock", &EN_DIS, + Help "Lock or Unlock CPU Run Control; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_CrashLogGprs, "Enable CPU CrashLog GPRs dump", &gPlatformFspPkgTokenSpaceGuid_CrashLogGprs, + Help "Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only disable Smm GPRs dump" + Combo $gPlatformFspPkgTokenSpaceGuid_OcLock, "Over clocking Lock", &EN_DIS, + Help "Lock Overclocking. 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuRatio, "CPU ratio value", HEX, + Help "This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio set by Hardware (HFM). Valid Range 0 to 63." + "Valid range: 0x00 ~ 0x3F" + Combo $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, "Number of active big cores", &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, + Help "Number of P-cores to enable in each processor package. Note: Number of P-Cores and E-Cores are looked at together. When both are {0,0" + Combo $gPlatformFspPkgTokenSpaceGuid_ActiveSmallCoreCount, "Number of active small cores", &gPlatformFspPkgTokenSpaceGuid_ActiveSmallCoreCount, + Help "Number of E-cores to enable in each processor package. Note: Number of P-Cores and E-Cores are looked at together. When both are {0,0" + Combo $gPlatformFspPkgTokenSpaceGuid_ActiveLpAtomCoreCount, "Number of LP Atom cores", &gPlatformFspPkgTokenSpaceGuid_ActiveLpAtomCoreCount, + Help "Number of LP E-cores to enable in LP. 0: Disable all LP Atom cores; 1: 1; 2: 2; 0xFF: Active all LP Atom cores" + Combo $gPlatformFspPkgTokenSpaceGuid_DfdEnable, "DFD Enable", &EN_DIS, + Help "Enable or Disable DFD. 0: Disable, 1:Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PrmrrSize, "PrmrrSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_TsegSize, + Help "Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build" + Combo $gPlatformFspPkgTokenSpaceGuid_SmmRelocationEnable, "SmmRelocationEnable Enable", &EN_DIS, + Help "Enable or Disable SmmRelocationEnable. 0: Disable, 1:Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset, "TCC Activation Offset", HEX, + Help "TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts. Default = 0h." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power, "Platform PL1 power", HEX, + Help "Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. Any value can be programmed between Max and Min Power Limits. This setting will act as the new PL1 value for the Package RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PlatformAtxTelemetryUnit, "PlatformAtxTelemetryUnit Mode", &EN_DIS, + Help "Enable/Disable PlatformAtxTelemetryUnit Mode. 0: Disable ; 1:Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_CustomPowerLimit1, "Platform PL1 power", HEX, + Help " Short term Power Limit value for custom cTDP level. Units are 125 milliwatt." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CustomPowerLimit2, "Platform PL1 power", HEX, + Help " Short term Power Limit value for custom cTDP level. Units are 125 milliwatt." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power, "Platform PL2 power", HEX, + Help "Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. Any value can be programmed between Max and Min Power Limits. This setting will act as the new Max Turbo Power (PL2) value for the Package RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysMax, "Vsys Max System battery volatge", HEX, + Help "Vsys Max defined in 1/1000 increments. Range is 0-65535. For a 1.25 voltage, enter 1250. Default =0xFF." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ThETAIbattEnable, "ThETA Ibatt Feature", &EN_DIS, + Help "Enable or Disable ThETA Ibatt Feature. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_IsysCurrentLimitL1, "ISYS Current Limit L1", HEX, + Help "This field indicated the current limitiation of L1. Indicate current limit for which dependency is on AC/DC mode before PSYS.Units of measurements are 1/8 A" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IsysCurrentL1Tau, "ISYS Current Limit L1 Tau", HEX, + Help "This Specifies the time window used to calculate average current for ISYS_L1. The units of measuremnts are specified in PACKAGE_POWER_SKU[TIME_UNIT]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IsysCurrentLimitL2, "ISYS Current Limit L2", HEX, + Help "This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm.Indicate current limit for which dependency is on AC/DC mode before PSYS. Units of measurements are 1/8 A" + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_IsysCurrentLimitL1Enable, "ISYS Current Limit L1 Enable", &EN_DIS, + Help "This bits enables disables ISYS_CURRENT_LIMIT_L1 algorithm. It control loop based on the system power source AC or DC mode. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_IsysCurrentLimitL2Enable, "ISYS Current Limit L2 Enable", &EN_DIS, + Help "This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm. It control loop based on the system power source AC or DC mode. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Boost, "Package PL4 boost configuration", HEX, + Help "Configure Power Limit 4 Boost in Watts. Valid Range 0 to 63000 in step size of 125 mWatt. The value 0 means disable." + "Valid range: 0x00 ~ 0xF618" + EditNum $gPlatformFspPkgTokenSpaceGuid_SkinTargetTemp, "Skin Temperature Target", HEX, + Help "Target temperature is limit to which the control mechanism is regulating.It is defined in 1/2 C increments.Range is 0-255. Temperature Range is 0-122.5 C.0: Auto." + "Valid range: 0x00 ~ 0xFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SkinTempControlEnable, "Skin Control Temperature Enable MMIO", &EN_DIS, + Help "Enables the skin temperature control for MMIO register. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_SkinControlLoopGain, "Skin Temperature Loop Gain", HEX, + Help "Sets the aggressiveness of control loop where 0 is graceful, favors performance on expense of temperature overshoots and 7 is for aggressive, favors tight regulation over performance. Range is 0-7.0: Auto." + "Valid range: 0x00 ~ 0x777" + Combo $gPlatformFspPkgTokenSpaceGuid_SkinTempOverrideEnable, "Skin Temperature Override Enable", &EN_DIS, + Help "When set, Pcode will use TEMPERATURE_OVERRIDE values instead of reading from corresponding sensor.. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_SkinMinPerformanceLevel, "Skin Temperature Minimum Performance Level", HEX, + Help "Minimum Performance level below which the STC limit will not throttle. 0 - all levels of throttling allowed incl. survivability actions. 256 - no throttling allowed.0: Auto." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SkinTempOverride, "Skin Temperature Override", HEX, + Help "Allows SW to override the input temperature. Pcode will use this value instead of the sensor temperature. EC control is not impacted. Units: 0.5C. Values are 0 to 255 which represents 0C-122.5C range.0: Auto." + "Valid range: 0x00 ~ 0xFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SkinTempControl, "Skin Temperature Control Enable", &EN_DIS, + Help "Enables Skin Temperature Control Sensors Feature. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_AcDcPowerState, "AC or DC Power State", &gPlatformFspPkgTokenSpaceGuid_AcDcPowerState, + Help "AC or DC power State; 0: DC; 1: AC" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert, "Enable or Disable VR Thermal Alert", &EN_DIS, + Help "Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor, "Enable or Disable Thermal Monitor", &EN_DIS, + Help "Enable or Disable Thermal Monitor; 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", HEX, + Help "Assured Power (cTDP) Mode as Nominal/Level1/Level2/Deactivate Base Power (TDP) selection. Deactivate option will set MSR to Nominal and MMIO to Zero. 0: Base Power (TDP) Nominal; 1: Base Power (TDP) Down; 2: Base Power (TDP) Up;0xFF : Deactivate" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock, "ConfigTdp mode settings Lock", &EN_DIS, + Help "Assured Power (cTDP) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL. Note: When CTDP (Assured Power) Lock is enabled Custom ConfigTDP Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios, "Load Configurable TDP SSDT", &EN_DIS, + Help "Enables Assured Power (cTDP) control via runtime ACPI BIOS methods. This 'BIOS only' feature does not require EC or driver support. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_CustomTurboActivationRatio, "CustomTurboActivationRatio", &EN_DIS, + Help "Turbo Activation Ratio for custom cTDP level" + Combo $gPlatformFspPkgTokenSpaceGuid_CustomPowerLimit1Time, "CustomPowerLimit1Time", &EN_DIS, + Help "Short term Power Limit time window value for custom cTDP level." + Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1, "PL1 Enable value", &EN_DIS, + Help "Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time, "PL1 timewindow", HEX, + Help "Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform Processor Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" + "Valid range: 0x00 ~ 0x80" + Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2, "PL2 Enable Value", &EN_DIS, + Help "Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS will program the default values for Platform Power Limit 2. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time, "Package PL3 time window", HEX, + Help "Power Limit 3 Time Window value in Milli seconds. Indicates the time window over which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves the hardware default value. Valid value: 0, 3-8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56, 64." + "Valid range: 0x00 ~ 0x40" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time, "Package Long duration turbo mode time", HEX, + Help "Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which Processor Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" + "Valid range: 0x00 ~ 0x80" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1, "Package Long duration turbo mode power limit", HEX, + Help "Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit and Processor Base Power (TDP) Limit. If value is 0, BIOS will program Processor Base Power (TDP) value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power, "Package Short duration turbo mode power limit", HEX, + Help "Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor Base Power (TDP). Processor applies control policies such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3, "Package PL3 power limit", HEX, + Help "Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit and Processor Base Power (TDP) Limit. If the value is 0, BIOS leaves the hardware default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4, "Package PL4 power limit", HEX, + Help "Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1, "Short term Power Limit value for custom cTDP level 1", HEX, + Help "Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2, "Long term Power Limit value for custom cTDP level 1", HEX, + Help "Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Processor applies control policies such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ApplyConfigTdp, "Enable Configurable TDP", &EN_DIS, + Help "Applies Assured Power (cTDP) initialization settings based on non-Assured Power (cTDP) or Assured Power (cTDP). Default is 1: Applies to Assured Power (cTDP) ; if 0 then applies non-Assured Power (cTDP) and BIOS will bypass Assured Power (cTDP) initialization flow" + Combo $gPlatformFspPkgTokenSpaceGuid_DualTauBoost, "Dual Tau Boost", &EN_DIS, + Help "Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W sku. When DPTF is enabled this feature is ignored. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock, "Tcc Offset Lock", &EN_DIS, + Help "Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 1:Enabled ; 0: Disabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle, "Package PL3 Duty Cycle", HEX, + Help "Specify the duty cycle in percentage that the CPU is required to maintain over the configured time window. Range is 0-100." + "Valid range: 0x00 ~ 0x64" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock, "Package PL3 Lock", &EN_DIS, + Help "Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled PL3 configuration can be changed during OS. 0: Disable ; 1:Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock, "Package PL4 Lock", &EN_DIS, + Help "Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled PL4 configuration can be changed during OS. 0: Disable ; 1:Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit2, "Short Duration Turbo Mode", &EN_DIS, + Help "Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program the default values for Power Limit 2. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ResponseMode, "Response Mode", &EN_DIS, + Help "Enable/Disable Response Mode. 0: Disable ; 1:Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize, "SinitMemorySize", HEX, + Help "Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase, "TxtDprMemoryBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize, "TxtHeapMemorySize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize, "TxtDprMemorySize", HEX, + Help "Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase, "TxtLcpPdBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize, "TxtLcpPdSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase, "BiosAcmBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize, "BiosAcmSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ApStartupBase, "ApStartupBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TgaSize, "TgaSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence, "IsTPMPresence", HEX, + Help "IsTPMPresence default values" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation, "Acoustic Noise Mitigation feature", &EN_DIS, + Help "Enabling this option will help mitigate acoustic noise on certain SKUs when the CPU is in deeper C state. 0: Disabled; 1: Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_RfiMitigation, "RfiMitigation", &EN_DIS, + Help "Enable or Disable RFI Mitigation. 0: Disable - DCM is the IO_N default; 1: Enable - Enable IO_N DCM/CCM switching as RFI mitigation." + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysSlope, "Platform Psys slope correction", HEX, + Help "PSYS Slope defined in 1/100 increments. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25" + "Valid range: 0x00 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPmax, "Platform Power Pmax", HEX, + Help "PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W" + "Valid range: 0x00 ~ 0x400" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcCurrentLimit, "Thermal Design Current current limit", HEX, + Help "TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = 0 Amps. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved." + "Valid range: 0x00 ~ 0x7FFF7FFF7FFF7FFF7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DcLoadline, "DcLoadline", HEX, + Help "DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x18691869186918691869" + EditNum $gPlatformFspPkgTokenSpaceGuid_Ps1Threshold, "Power State 1 Threshold current", HEX, + Help "PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range 0-152, which translates to 0-38A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x02000200020002000200" + EditNum $gPlatformFspPkgTokenSpaceGuid_Ps2Threshold, "Power State 2 Threshold current", HEX, + Help "PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range 0-48, which translates to 0-12A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x02000200020002000200" + EditNum $gPlatformFspPkgTokenSpaceGuid_Ps3Threshold, "Power State 3 Threshold current", HEX, + Help "PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range 0-16, which translates to 0-4A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x02000200020002000200" + EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset, "Imon offset correction", HEX, + Help "IMON Offset is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset of 25.348, enter 25348. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IccMax, "Icc Max limit", HEX, + Help "Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 means AUTO. IA and GT, range 0-2047. SA range 0-1023. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x07FF07FF03FFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit, "VR Fast Vmode VoltageLimit support", HEX, + Help "Voltage Regulator Fast VoltageLimit ." + "Valid range: 0x00 ~ 0x07F807F807F807F807F8" + EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope, "Imon slope correction", HEX, + Help "IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x00C800C800C800C800C8" + EditNum $gPlatformFspPkgTokenSpaceGuid_Ps3Enable, "Power State 3 enable/disable", HEX, + Help "PS3 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Ps4Enable, "Power State 4 enable/disable", HEX, + Help "PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable, "Enable/Disable BIOS configuration of VR", HEX, + Help "VR Config Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. 0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcEnable, "Thermal Design Current enable/disable", HEX, + Help "Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcLock, "Thermal Design Current Lock", HEX, + Help "Thermal Design Current Lock; 0: Disable; 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisable, "Disable Fast Slew Rate for Deep Package C States for VR domains", &EN_DIS, + Help "This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. 0: False; 1: True" + Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRate, "Slew Rate configuration for Deep Package C States for VR domains", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRate, + Help "Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysOffset, "Platform Psys offset correction", HEX, + Help "PSYS Offset defined in 1/1000 increments. 0 - Auto This is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset of 25.348, enter 25348." + "Valid range: 0x0000 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow, "Thermal Design Current time window", HEX, + Help "Auto = 0 is default. Range is from 1ms to 448s. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved." + "Valid range: 0x00 ~ 0x0006D6000006D6000006D6000006D6000006D600" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcMode, "TDC Mode", HEX, + Help "TDC Mode based on IRMS supported bit from Mailbox. 0: iPL2; 1: Irms. [0] for IA, [1] for GT, [2] for SA, [3] for atom [4]-[5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_FivrSpectrumEnable, "DLVR RFI Enable", &EN_DIS, + Help "Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_DlvrSpreadSpectrumPercentage, "DLVR RFI Spread Spectrum Percentage", HEX, + Help "DLVR SSC in percentage with multiple of 0.25%. 0 = 0%, 10 = 4%. 0x00: 0% , 0x02: 0.5%, 0x04: 1% , 0x08: 2% ,0x10: 4%; u3.2 value from 0% - 4%." + "Valid range: 0x0 ~ 0x1F" + Combo $gPlatformFspPkgTokenSpaceGuid_DlvrRfiEnable, "DLVR RFI Enable", &EN_DIS, + Help "Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcoreHysteresisWindow, "Pcore VR Hysteresis time window", HEX, + Help "0 is default. Range of PcoreHysteresisWindow from 1ms to 50ms." + "Valid range: 0x00 ~ 0x32" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcoreHysteresisWindow, "Ecore VR Hysteresis time window", HEX, + Help "0 is default. Range of EcoreHysteresisWindow from 1ms to 50ms." + "Valid range: 0x00 ~ 0x32" + Combo $gPlatformFspPkgTokenSpaceGuid_VccsaShutdown, "VCCSA Shutdown", &EN_DIS, + Help "Enable/Disable VCCSA Shutdown hopping. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_DlvrRfiFrequency, "DLVR RFI Frequency", HEX, + Help "DLVR RFI Frequency in MHz. 0: 2227 MHz , 1: 2140MHZ." + "Valid range: 0x0 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign, "DLVR PHASE_SSC Enable", &EN_DIS, + Help "Enable/Disable DLVR PHASE_SSC. 0: Disable. 1:Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_DlvrPhaseSsc, "DLVR PHASE_SSC Enable", &EN_DIS, + Help "Enable/Disable DLVR PHASE_SSC. 0: Disable. 1:Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_EnableVsysCritical, "Vsys Critical", HEX, + Help "PCODE MMIO Mailbox: Vsys Critical. 0: Disable; 1: Enable Range is 0-255." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchMantissa, "Assertion Deglitch Mantissa", HEX, + Help "Assertion Deglitch Mantissa, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchExponent, "Assertion Deglitch Exponent", HEX, + Help "Assertion Deglitch Exponent, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchMantissa, "De assertion Deglitch Mantissa", HEX, + Help "De assertion Deglitch Mantissa, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchExponent, "De assertion Deglitch Exponent", HEX, + Help "De assertion Deglitch Exponent, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IccLimit, "VR Fast Vmode ICC Limit support", HEX, + Help "Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds to feature disabled (no reactive protection). This value represents the current threshold where the VR would initiate reactive protection if Fast Vmode is enabled. The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x07F807F807F807F807F8" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableFastVmode, "Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.", &gPlatformFspPkgTokenSpaceGuid_EnableFastVmode, + Help "Enable/Disable VR FastVmode; 0: Disable; 1: Enable.For all VR by domain" + Combo $gPlatformFspPkgTokenSpaceGuid_CepEnable, "Enable/Disable CEP", &gPlatformFspPkgTokenSpaceGuid_CepEnable, + Help "Control for enabling/disabling CEP (Current Excursion Protection). 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysFullScale, "Vsys Full Scale", DEC, + Help "Vsys Full Scale, Range is 0-255000mV" + "Valid range: 0 ~ 255000" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysCriticalThreshold, "Vsys Critical Threshold", DEC, + Help "Vsys Critical Threshold, Range is 0-255000mV " + "Valid range: 0 ~ 255000" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysFullScale, "Psys Full Scale", DEC, + Help "Psys Full Scale, Range is 0-255000mV" + "Valid range: 0 ~ 255000" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysCriticalThreshold, "Psys Critical Threshold", DEC, + Help "Psys Critical Threshold, Range is 0-255000mV " + "Valid range: 0 ~ 255000" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPmVrRsvd, "CpuPmVrRsvd", &EN_DIS, + Help "Reserved for CPU Power Mgmt VR Config" + Combo $gPlatformFspPkgTokenSpaceGuid_IoeDebugEn, "IOE Debug Enable", &EN_DIS, + Help "Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link will keep up and clock is enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_PmodeClkEn, "Pmode Clock Enable", &EN_DIS, + Help "Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPort80Route, "PCH Port80 Route", &EN_DIS, + Help "Control where the Port 80h cycles are sent, 0: LPC; 1: PCI." + EditNum $gPlatformFspPkgTokenSpaceGuid_GpioOverride, "GPIO Override", HEX, + Help "Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use" + "Valid range: 0x00 ~ 0x7" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcPrivacyConsent, "Pmc Privacy Consent", &EN_DIS, + Help "Enable/Disable Pmc Privacy Consent" + Combo $gPlatformFspPkgTokenSpaceGuid_PchTestDmiMeUmaRootSpaceCheck, "DMI ME UMA Root Space Check", &gPlatformFspPkgTokenSpaceGuid_PchTestDmiMeUmaRootSpaceCheck, + Help "DMI IOSF Root Space attribute check for RS3 for cycles targeting MEUMA." + EditNum $gPlatformFspPkgTokenSpaceGuid_DmaBufferSize, "PMR Size", HEX, + Help "Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PreBootDmaMask, "The policy for VTd driver behavior", HEX, + Help "BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmaControlGuarantee, "State of DMA_CONTROL_GUARANTEE bit in the DMAR table", &EN_DIS, + Help "0=Disable/Clear, 1=Enable/Set" + Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisable, "Disable VT-d", &EN_DIS, + Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" + EditNum $gPlatformFspPkgTokenSpaceGuid_VtdCapabilityControl, "State of Vtd Capabilities", HEX, + Help "0x0=(No operation), BIT0 = 1 (Defeature Nested Support), BIT1 = 1 (Defeature Posted Interrupt Support)" + "Valid range: 0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX, + Help "Base addresses for VT-d MMIO access per VT-d engine" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MchBar, "MMIO Size", HEX, + Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" + "Valid range: 0 ~ 0xC00" + EditNum $gPlatformFspPkgTokenSpaceGuid_RegBar, "MMIO Size", HEX, + Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" + "Valid range: 0 ~ 0xC00" + EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSize, "MMIO Size", HEX, + Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" + "Valid range: 0 ~ 0xC00" + EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment, "MMIO size adjustment for AUTO mode", HEX, + Help "Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ApicLocalAddress, "Temporary address for ApicLocalAddress", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NvmeHcPeiMmioBase, "Temporary address for NvmeHcPeiMmioBase", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NvmeHcPeiMmioLimit, "Temporary address for NvmeHcPeiMmioLimit", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AhciPeiMmioBase, "Temporary address for AhciPeiMmioBase", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AhciPeiMmioLimit, "Temporary address for AhciPeiMmioLimit", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcExtraIoBase, "Temporary address for EcExtraIoBase", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SioBaseAddress, "Temporary address for SioBaseAddress", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBar, "Temporary CfgBar address for VMD", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SafBar, "System Agent SafBar", HEX, + Help "Address of System Agent SafBar" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableAbove4GBMmio, "Enable above 4GB MMIO resource support", &EN_DIS, + Help "Enable/disable above 4GB MMIO resource support" + Combo $gPlatformFspPkgTokenSpaceGuid_CridEnable, "Enable/Disable SA CRID", &EN_DIS, + Help "Enable: SA CRID, Disable (Default): SA CRID" + Combo $gPlatformFspPkgTokenSpaceGuid_StreamTracerMode, "StreamTracer Mode", &gPlatformFspPkgTokenSpaceGuid_StreamTracerMode, + Help "Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended when all groups in high verbosity are traced in 'red', Auto: StreamTracer size 8MB - Recommended when using up to 8 groups red or up to 16 groups in green in med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogDevice, "Enable/Disable CrashLog Device", &EN_DIS, + Help "Enable or Disable CrashLog/Telemetry Device 0- Disable, 1- Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_StreamTracerBase, "StreamTracer physical address", HEX, + Help "StreamTracer physical address" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Bar, "Temporary MemBar1 address for VMD", HEX, + Help "StreamTracer physical address" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Bar, "Temporary MemBar2 address for VMD", HEX, + Help "StreamTracer physical address" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SiSkipOverrideBootModeWhenFwUpdate, "Skip override boot mode When Fw Update.", &EN_DIS, + Help "When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init." + Combo $gPlatformFspPkgTokenSpaceGuid_StaticContentSizeAt4Gb, "Static Content at 4GB Location", &gPlatformFspPkgTokenSpaceGuid_StaticContentSizeAt4Gb, + Help "0 (Default): No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB, 0x400:1GB, 0x800:2GB, 0xC00:3GB, 0x1000:4GB, 0x2000:8GB" + Combo $gPlatformFspPkgTokenSpaceGuid_PlatformDebugOption, "Platform Debug Option", &gPlatformFspPkgTokenSpaceGuid_PlatformDebugOption, + Help "Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n\nEnabled Trace ready: TraceHub is enabled and allowed S0ix.\n\nEnabled Trace power off: TraceHub is powergated, provide setting close to functional low power state\n\nManual: user needs to configure Advanced Debug Settings manually, aimed at advanced users" + EditNum $gPlatformFspPkgTokenSpaceGuid_CmosTxtOffset, "TXT CMOS Offset", HEX, + Help "CMOS Offset for TXT policy data. Default 0x2A" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SiPreMemRsvd, "SiPreMemRsvd", &EN_DIS, + Help "Reserved for SI Pre-Mem" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig, "Program GPIOs for LFP on DDI port-A device", &gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig, + Help "0=Disabled,1(Default)=eDP, 2=MIPI DSI" + EditNum $gPlatformFspPkgTokenSpaceGuid_HgSubSystemId, "HgSubSystemId", HEX, + Help "Hybrid Graphics SubSystemId" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig, "Program GPIOs for LFP on DDI port-B device", &gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig, + Help "0(Default)=Disabled,1=eDP, 2=MIPI DSI" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortAHpd, "Enable or disable HPD of DDI port A", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd, "Enable or disable HPD of DDI port B", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd, "Enable or disable HPD of DDI port C", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort1Hpd, "Enable or disable HPD of DDI port 1", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort2Hpd, "Enable or disable HPD of DDI port 2", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort3Hpd, "Enable or disable HPD of DDI port 3", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort4Hpd, "Enable or disable HPD of DDI port 4", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortADdc, "Enable or disable DDC of DDI port A", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc, "Enable or disable DDC of DDI port B", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc, "Enable or disable DDC of DDI port C", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort1Ddc, "Enable DDC setting of DDI Port 1", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort2Ddc, "Enable DDC setting of DDI Port 2", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort3Ddc, "Enable DDC setting of DDI Port 3", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort4Ddc, "Enable DDC setting of DDI Port 4", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Dealy Override", &EN_DIS, + Help "Oem T12 Dealy Override. 0(Default)=Disable 1=Enable " + EditNum $gPlatformFspPkgTokenSpaceGuid_LMemBar, "Temporary MMIO address for GMADR", HEX, + Help "The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1)" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GttMmAdr, "Temporary MMIO address for GTTMMADR", HEX, + Help "The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, + Help "Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate T12 Delay to max 500ms" + Combo $gPlatformFspPkgTokenSpaceGuid_MemoryBandwidthCompression, "Enable/Disable Memory Bandwidth Compression", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable, "Panel Power Enable", &EN_DIS, + Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, + Help "3(Default)=AUTO, 0=IGFX, 4=Hybrid Graphics" + Combo $gPlatformFspPkgTokenSpaceGuid_IGpuGsm2Size, "Internal Graphics Data Stolen Memory GSM2", &gPlatformFspPkgTokenSpaceGuid_IGpuGsm2Size, + Help "Size of memory preallocated for internal graphics GSM2." + EditNum $gPlatformFspPkgTokenSpaceGuid_VbtSize, "Intel Graphics VBT (Video BIOS Table) Size", HEX, + Help "Size of Internal Graphics VBT Image" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VbtPtr, "Graphics Configuration Ptr", HEX, + Help "Points to VBT" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VgaMessage, "SOL Training Message Pointer", HEX, + Help "Points to SOL Message String" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_LidStatus, "Platform LID Status for LFP Displays.", &gPlatformFspPkgTokenSpaceGuid_LidStatus, + Help "LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen." + Combo $gPlatformFspPkgTokenSpaceGuid_VgaInitControl, "Control SOL VGA Initialition sequence", &gPlatformFspPkgTokenSpaceGuid_VgaInitControl, + Help "Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),, BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported, 1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar), BIT5 - (0 : VGA Mode 12 16 Color Support, 1 : VGA Mode 12 Monochrome Black and White Support), BIT6-7 - (0 : No Higher Cd Clock, 1 : 442 MHz, 2 : 461 MHz, 3 : Reserved)" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight, "SOL VGA Graphics Mode 12 LogoPixelHeight", HEX, + Help "Heigh of VGA Graphics Mode 12 Logo" + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth, "SOL VGA Graphics Mode 12 LogoPixelWidth", HEX, + Help "Width of VGA Graphics Mode 12 Logo" + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoXPosition, "SOL VGA Graphics Mode 12 Image X Position", HEX, + Help "X position of Image on Display" + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VgaGraphicsMode12ImagePtr, "SOL VGA Graphics Mode 12 Image Pointer", HEX, + Help "Points to SOL VGA Graphics Graphics 12 Image, VgaPlanarImage200x58[4][58][25] for 58Hx200W as example, " + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoYPosition, "SOL VGA Graphics Mode 12 Image Y Position", HEX, + Help "Y position of Image on Display" + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssXhciEn, "TCSS USB HOST (xHCI) Enable", HEX, + Help "Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below" + "Valid range: 0x0 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_IomUsbCDpConfig, "IomUsbCDpConfig", &gPlatformFspPkgTokenSpaceGuid_IomUsbCDpConfig, + Help "Set IomUsbCDpConfig expect 4 values from 0 to 3" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssPort0, "TCSS Type C Port 0", &gPlatformFspPkgTokenSpaceGuid_TcssPort0, + Help "Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssPort1, "TCSS Type C Port 1", &gPlatformFspPkgTokenSpaceGuid_TcssPort1, + Help "Set TCSS Type C Port 1 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssPort2, "TCSS Type C Port 2", &gPlatformFspPkgTokenSpaceGuid_TcssPort2, + Help "Set TCSS Type C Port 2 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssPort3, "TCSS Type C Port 3", &gPlatformFspPkgTokenSpaceGuid_TcssPort3, + Help "Set TCSS Type C Port 3 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, 7=FULL_FUN" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssPlatConf, "TCSS Platform Configuration", HEX, + Help "Set TCSS Platform Configuration - Retimer Map, TCP0 - Bits[1:0], TCP1 - Bits[3:2], TCP2 - Bits[5:4], TCP3 - Bits[7:6]; 0=Retimerless, 1=Retimer" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IomTypeCPortPadCfg, "TypeC port GPIO setting", HEX, + Help "GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined in GpioPinsXXX.h as argument.(XXX is platform name, Ex: Ptl = PantherLake)" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssAuxOri, "TCSS Aux Orientation Override Enable", HEX, + Help "Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides" + "Valid range: 0x0 ~ 0x0FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssHslOri, "TCSS HSL Orientation Override Enable", HEX, + Help "Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides" + "Valid range: 0x0 ~ 0x0FFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviDdrRfim, "CNVi DDR RFI Mitigation", &EN_DIS, + Help "Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMode, "SOC Trace Hub Mode", &EN_DIS, + Help "Enable/Disable SOC TraceHub" + Combo $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg0Size, "SOC Trace Hub Memory Region 0 buffer Size", &gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg0Size, + Help "Select size of memory region 0 buffer. Memory allocated by BIOS only applies to ITH tool running on the host. For ITH tool running on the target, choose None/OS, memory shall be allocated by tool. User should be cautious to choose the amount of memory. If chosen size is larger than half of system memory, setup will automatically rollback to default value." + Combo $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg1Size, "SOC Trace Hub Memory Region 0 buffer Size", &gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg1Size, + Help "Select size of memory region 1 buffer. Memory allocated by BIOS only applies to ITH tool running on the host. For ITH tool running on the target, choose None/OS, memory shall be allocated by tool. User should be cautious to choose the amount of memory. If chosen size is larger than half of system memory, setup will automatically rollback to default value." + Combo $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, + Help "Size of memory preallocated for internal graphics." + Combo $gPlatformFspPkgTokenSpaceGuid_InternalGraphics, "Internal Graphics", &gPlatformFspPkgTokenSpaceGuid_InternalGraphics, + Help "Expect 3 values from 0 to 2" + Combo $gPlatformFspPkgTokenSpaceGuid_AsyncOdtDis, "Asynchronous ODT", &gPlatformFspPkgTokenSpaceGuid_AsyncOdtDis, + Help "This option configures the Memory Controler Asynchronous ODT control" + Combo $gPlatformFspPkgTokenSpaceGuid_WeaklockEn, "DLL Weak Lock Support", &EN_DIS, + Help "Enables/Disable DLL Weak Lock Support" + Combo $gPlatformFspPkgTokenSpaceGuid_RxDqsDelayCompEn, "Rx DQS Delay Comp Support", &EN_DIS, + Help "Enables/Disable Rx DQS Delay Comp Support" + Combo $gPlatformFspPkgTokenSpaceGuid_MrcFailureOnUnsupportedDimm, "Mrc Failure On Unsupported Dimm", &EN_DIS, + Help "Enables/Disable Mrc Failure On Unsupported Dimm" + Combo $gPlatformFspPkgTokenSpaceGuid_ForceSingleRank, "Fore Single Rank config", &EN_DIS, + Help "Enables/Disable Fore Single Rank config" + Combo $gPlatformFspPkgTokenSpaceGuid_DynamicMemoryBoost, "DynamicMemoryBoost", &EN_DIS, + Help "Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryFrequency, "RealtimeMemoryFrequency", &EN_DIS, + Help "Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_SrefCfgIdleTmr, "SelfRefresh IdleTimer", HEX, + Help "SelfRefresh IdleTimer, Default is 256" + "Valid range: 0x100 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MCREGOFFSET, "MC Register Offset", &EN_DIS, + Help "Apply user offsets to select MC registers(Def=Disable)" + Combo $gPlatformFspPkgTokenSpaceGuid_CAVrefCtlOffset, "CA Vref Ctl Offset", &gPlatformFspPkgTokenSpaceGuid_CAVrefCtlOffset, + Help "Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.CAVref" + Combo $gPlatformFspPkgTokenSpaceGuid_ClkPiCodeOffset, "Clk PI Code Offset", &gPlatformFspPkgTokenSpaceGuid_ClkPiCodeOffset, + Help "Offset to be applied to DDRCLKCH0_CR_DDRCRCLKPICODE.PiSettingRank[0-3]" + Combo $gPlatformFspPkgTokenSpaceGuid_RcvEnOffset, "RcvEn Offset", &gPlatformFspPkgTokenSpaceGuid_RcvEnOffset, + Help "Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RcvEn" + Combo $gPlatformFspPkgTokenSpaceGuid_RxDqsOffset, "Rx Dqs Offset", &gPlatformFspPkgTokenSpaceGuid_RxDqsOffset, + Help "Offset to be applied to DDRDATACHX_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset" + Combo $gPlatformFspPkgTokenSpaceGuid_TxDqOffset, "Tx Dq Offset", &gPlatformFspPkgTokenSpaceGuid_TxDqOffset, + Help "Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset" + Combo $gPlatformFspPkgTokenSpaceGuid_TxDqsOffset, "Tx Dqs Offset", &gPlatformFspPkgTokenSpaceGuid_TxDqsOffset, + Help "Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset" + Combo $gPlatformFspPkgTokenSpaceGuid_VrefOffset, "Vref Offset", &gPlatformFspPkgTokenSpaceGuid_VrefOffset, + Help "Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset" + EditNum $gPlatformFspPkgTokenSpaceGuid_CntrlrMask, "Controller mask", HEX, + Help "Controller mask to apply on parameter offset" + "Valid range: 0x00 ~ 0xff" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChMask, "Channel mask", HEX, + Help "Channel mask to apply on parameter offset" + "Valid range: 0x00 ~ 0xff" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRSG, "tRRSG Delta", HEX, + Help "Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRDG, "tRRDG Delta", HEX, + Help "Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRDR, "tRRDR Delta", HEX, + Help "Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRDD, "tRRDD Delta", HEX, + Help "Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWRSG, "tWRSG Delta", HEX, + Help "Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWRDG, "tWRDG Delta", HEX, + Help "Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWRDR, "tWRDR Delta", HEX, + Help "Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWRDD, "tWRDD Delta", HEX, + Help "Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWWSG, "tWWSG Delta", HEX, + Help "Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWWDG, "tWWDG Delta", HEX, + Help "Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWWDR, "tWWDR Delta", HEX, + Help "Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWWDD, "tWWDD Delta", HEX, + Help "Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRWSG, "tRWSG Delta", HEX, + Help "Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRWDG, "tRWDG Delta", HEX, + Help "Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRWDR, "tRWDR Delta", HEX, + Help "Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRWDD, "tRWDD Delta", HEX, + Help "Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_Interpreter, "MRC Interpreter", &gPlatformFspPkgTokenSpaceGuid_Interpreter, + Help "Select CMOS location match of DD01 or Ctrl-Break key or force entry" + Combo $gPlatformFspPkgTokenSpaceGuid_IoOdtMode, "ODT mode", &gPlatformFspPkgTokenSpaceGuid_IoOdtMode, + Help "ODT mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PerBankRefresh, "PerBankRefresh", &EN_DIS, + Help "Control of Per Bank Refresh feature for LPDDR DRAMs" + Combo $gPlatformFspPkgTokenSpaceGuid_MimicWcDisaplayInIpq, "Mimic WC display pattern in IPQ", &gPlatformFspPkgTokenSpaceGuid_MimicWcDisaplayInIpq, + Help "Using for Disable/Enable Mimic WC display pattern in IPQ: 0:Disable, 1:Enable 1 ACT resources usage, 3:Enable 2 ACT resources usage, 3:Enable 3 ACT resources usage,0xf: Enable 4 ACT resources usage" + Combo $gPlatformFspPkgTokenSpaceGuid_FakeSagv, "Fake SAGV", &EN_DIS, + Help "Fake SAGV: 0:Disabled, 1:Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_DprLock, "Lock DPR register", &gPlatformFspPkgTokenSpaceGuid_DprLock, + Help "Lock DPR register. 0: Platform POR ; 1: Enable; 2: Disable" + Combo $gPlatformFspPkgTokenSpaceGuid_BoardStackUp, "Board Stack Up", &gPlatformFspPkgTokenSpaceGuid_BoardStackUp, + Help "Board Stack Up: 0=Typical, 1=Freq Limited" + Combo $gPlatformFspPkgTokenSpaceGuid_PprForceRepair, "PPR ForceRepair", &EN_DIS, + Help "When Eanble, PPR will force repair some rows many times (90)" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairBank, "PPR Repair Bank", HEX, + Help "Deprecated" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_BoardTopology, "Board Topology", &gPlatformFspPkgTokenSpaceGuid_BoardTopology, + Help "Board Topology: 0=Daisy Chain, 1=Tee." + Combo $gPlatformFspPkgTokenSpaceGuid_SubChHashInterleaveBit, "SubCh Hash Interleaved Bit", &gPlatformFspPkgTokenSpaceGuid_SubChHashInterleaveBit, + Help "Select the MC Enhanced Channel interleave bit, to set different address bit for sub channel selection than bit-6" + EditNum $gPlatformFspPkgTokenSpaceGuid_SubChHashMask, "SubCh Hash Mask", HEX, + Help "Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x834" + "Valid range: 0x0000 ~ 0x3FFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ForceCkdBypass, "Force CKD in Bypass Mode", &EN_DIS, + Help "Enable/Disable Force CKD in Bypass Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableZq, "Disable Zq", &EN_DIS, + Help "Enable/Disable Zq Calibration: 0:Enabled, 1:Disabled" + Combo $gPlatformFspPkgTokenSpaceGuid_ReplicateSagv, "Replicate SAGV", &EN_DIS, + Help "Replicate SAGV: 0:Disabled, 1:Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_AdjustWckMode, "Adjust wck mode", &gPlatformFspPkgTokenSpaceGuid_AdjustWckMode, + Help "Adjust wck mode: 0:safe mode, 1:manual mode, 2:dynamic mode, 3:Default" + Combo $gPlatformFspPkgTokenSpaceGuid_TelemetryControl, "Control MC/PMA telemetry", &gPlatformFspPkgTokenSpaceGuid_TelemetryControl, + Help "Control MC/PMA telemetry: 0: Default, 1: Enable, 2: Disable" + Combo $gPlatformFspPkgTokenSpaceGuid_SpineAndPhclkGateControl, "PHclk\Qclk SPINE gating Control", &EN_DIS, + Help "PHclk\Qclk SPINE gating Control: 0:Disabled, 1:Enabled" + EditNum $gPlatformFspPkgTokenSpaceGuid_SpineGatePerLpmode, "SpineGating per lpmode", HEX, + Help "SpineGatePerLpmode[0]:Lpmode0.5, SpineGatePerLpmode[1]:Lpmode2, SpineGatePerLpmode[2]:Lpmode3, SpineGatePerLpmode[3]:Lpmode4" + "Valid range: 0x00 ~ 0xF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PhclkGatePerLpmode, "PhClkGating control per lpmode", HEX, + Help "PhclkGatePerLpmode[0]:Lpmode0.5, PhclkGatePerLpmode[1]:Lpmode1, PhclkGatePerLpmode[2]:Lpmode2, PhclkGatePerLpmode[3]:Lpmode3, PhclkGatePerLpmode[4]:Lpmode4" + "Valid range: 0x00 ~ 0x1F" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableSwitchDfiToMc, "DFI Control after cold boot", &EN_DIS, + Help "Disable Switch DFI Control to MC after cold boot: 0(Default)=switch DFI to MC, 1=Keep with PHY/MPTU" + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusPostCodeEnable, "Enable/Disable SmbusPostcode", &EN_DIS, + Help "Disable (Default): Postcode via Port80, Enable: Postcode via Smbus" + EditNum $gPlatformFspPkgTokenSpaceGuid_SmbusPostCodeAddress, "SmbusPostcode Address", HEX, + Help "Slave address for Smbus postcode device" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SmbusPostCodeCommand, "SmbusPostcode Command", HEX, + Help "Command value for Smbus postcode device" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChannelToCkdQckMapping, "Channel to CKD QCK Mapping", HEX, + Help "Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PhyClockToCkdDimm, "DDRIO Clock to CKD DIMM", HEX, + Help "Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CkdAddressTable, "CKD Address Table", HEX, + Help "Specify CKD Address table for all DIMMs" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SingleVdd2Rail, "Single VDD2 Rail", &EN_DIS, + Help "LP5x VDD2 rail: 0: Dual rail (E-DVFSC is possible), 1: Single rail(No E-DVFSC; VDD2L == VDD2H)" + EditNum $gPlatformFspPkgTokenSpaceGuid_Vdd2HVoltage, "VDD2 Voltage", HEX, + Help "Voltage is multiple of 5mV where 0 means Auto." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Vdd1Voltage, "VDD1 Voltage", HEX, + Help "Voltage is multiple of 5mV where 0 means Auto." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Vdd2LVoltage, "VDD2L Voltage Override", HEX, + Help "Voltage is multiple of 5mV where 0 means Auto." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VddqVoltage, "VDDQ Voltage Override", HEX, + Help "Voltage is multiple of 5mV where 0 means Auto." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GraphicsMode12FontPtr, "Graphics Mode 12 Font Pointer", HEX, + Help "Pointer to VGA Mode 12 Font Data (8x16 character set).\n Format: UINT8 array[256][16] where each character is 16 bytes (16 rows of 8 pixels).\n Must be provided if VGA Mode 12 is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MrcErrorKeyValueTablePtr, "MRC Error Key Value Table Pointer", HEX, + Help "Pointer to MRC Error Key Value Table. Table maps MRC error codes to error message strings for display during memory init. See FSP_MRC_ERROR_KEY_VALUE_TABLE." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" +EndPage + +Page "System Agent(PreMem)" +EndPage + +Page "PCH(PreMem)" +EndPage + +Page "Security(PostMem)" +EndPage + +Page "Management Engine(PostMem)" + Combo $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, "End of Post message", &gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, + Help "Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci, "D0I3 Setting for HECI Disable", &EN_DIS, + Help "Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices" + Combo $gPlatformFspPkgTokenSpaceGuid_MctpBroadcastCycle, "Mctp Broadcast Cycle", &EN_DIS, + Help "Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, "ME Unconfig on RTC clear", &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, + Help "0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved" + Combo $gPlatformFspPkgTokenSpaceGuid_CseDataResilience, "CSE Data Resilience Support", &EN_DIS, + Help "0: Disable CSE Data Resilience Support. 1: Enable CSE Data Resilience Support. 2: Enable CSE Data Resilience but defer to DXE." + Combo $gPlatformFspPkgTokenSpaceGuid_PseEomFlowEnable, "PSE EOM Flow Control", &EN_DIS, + Help "0: Disable PSE EOM Flow. 1: Enable PSE EOM Flow." + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI3cSdaPinMuxing, "ISH I3C SDA Pin Muxing", HEX, + Help "Select ISH I3C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SDA_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI3cSclPinMuxing, "ISH I3C SCL Pin Muxing", HEX, + Help "Select ISH I3C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SCL_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI3cSdaPadTermination, "ISH I3C SDA Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, and so on." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI3cSclPadTermination, "ISH I3C SCL Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshI3cEnable, "Enable PCH ISH I3C pins assigned", HEX, + Help "Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce, "Power button debounce configuration", HEX, + Help "Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range" + "Valid range: 0x00 ~ 0x009C4000" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcUsb2PhySusPgEnable, "PCH USB2 PHY Power Gating enable", &EN_DIS, + Help "1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert, "VRAlert# Pin", &EN_DIS, + Help "When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable, "ModPHY SUS Power Domain Dynamic Gating", &EN_DIS, + Help "Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcV1p05PhyExtFetControlEn, "V1p05-PHY supply external FET control", &EN_DIS, + Help "Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY supply. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcV1p05IsExtFetControlEn, "V1p05-IS supply external FET control", &EN_DIS, + Help "Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis, "PCH Pm PME_B0_S5_DIS", &EN_DIS, + Help "When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride, "PCH Pm Wol Enable Override", &EN_DIS, + Help "Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable, "PCH Pm WoW lan Enable", &EN_DIS, + Help "Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert, "PCH Pm Slp S3 Min Assert", HEX, + Help "SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert, "PCH Pm Slp S4 Min Assert", HEX, + Help "SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert, "PCH Pm Slp Sus Min Assert", HEX, + Help "SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert, "PCH Pm Slp A Min Assert", HEX, + Help "SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp, "PCH Pm Slp Strch Sus Up", &EN_DIS, + Help "Enable SLP_X Stretching After SUS Well Power Up." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc, "PCH Pm Slp Lan Low Dc", &EN_DIS, + Help "Enable/Disable SLP_LAN# Low on DC Power." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod, "PCH Pm Pwr Btn Override Period", HEX, + Help "PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton, "PCH Pm Disable Native Power Button", &EN_DIS, + Help "Power button native mode disable." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts, "PCH Pm ME_WAKE_STS", &EN_DIS, + Help "Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts, "PCH Pm WOL_OVR_WK_STS", &EN_DIS, + Help "Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur, "PCH Pm Reset Power Cycle Duration", HEX, + Help "Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ..." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc, "PCH Pm Pcie Pll Ssc", HEX, + Help "Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer, "Enable TCO timer.", &EN_DIS, + Help "When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS." + Combo $gPlatformFspPkgTokenSpaceGuid_PsOnEnable, "Enable PS_ON.", &EN_DIS, + Help "PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable, "Pmc Cpu C10 Gate Pin Enable", &EN_DIS, + Help "Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin." + Combo $gPlatformFspPkgTokenSpaceGuid_PmcOsIdleEnable, "OS IDLE Mode Enable", &EN_DIS, + Help "Enable/Disable OS Idle Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PchS0ixAutoDemotion, "S0ix Auto-Demotion", &EN_DIS, + Help "Enable/Disable the Low Power Mode Auto-Demotion Host Control feature." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLatchEventsC10Exit, "Latch Events C10 Exit", &EN_DIS, + Help "When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured on C10 exit (instead of C10 entry which is default)" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport, "PCH Energy Reporting", &EN_DIS, + Help "Disable/Enable PCH to CPU energy report feature." + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcLpmS0ixSubStateEnableMask, "Low Power Mode Enable/Disable config mask", HEX, + Help "Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmErDebugMode, "PCH PMC ER Debug mode", &EN_DIS, + Help "Disable/Enable Energy Reporting Debug Mode." + Combo $gPlatformFspPkgTokenSpaceGuid_PmcC10DynamicThresholdAdjustment, "PMC C10 dynamic threshold dajustment enable", &EN_DIS, + Help "Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock, "Enable LOCKDOWN BIOS LOCK", &EN_DIS, + Help "Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi, "Enable LOCKDOWN SMI", &EN_DIS, + Help "Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface, "Enable LOCKDOWN BIOS Interface", &EN_DIS, + Help "Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads, "Unlock all GPIO pads", &EN_DIS, + Help "Force all GPIO pads to be unlocked for debug purpose." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable, "PCH Flash Protection Ranges Write Enble", HEX, + Help "Write or erase is blocked by hardware." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable, "PCH Flash Protection Ranges Read Enble", HEX, + Help "Read is blocked by hardware." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit, "PCH Protect Range Limit", HEX, + Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase, "PCH Protect Range Base", HEX, + Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be 0." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PciePtm, "PCIe PTM enable/disable", HEX, + Help "Enable/disable Precision Time Measurement for PCIE Root Ports." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented, "PCH PCIe root port connection type", HEX, + Help "0: built-in device, 1:slot" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled, "PCIE RP Access Control Services Extended Capability", HEX, + Help "Enable/Disable PCIE RP Access Control Services Extended Capability" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm, "PCIE RP Clock Power Management", HEX, + Help "Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs, "PCIE RP Detect Timeout Ms", HEX, + Help "The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX, + Help "Indicate whether the root port is hot plug available." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci, "Enable PCIE RP Pm Sci", HEX, + Help "Indicate whether the root port power manager SCI is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX, + Help "Indicate whether the Transmitter Half Swing is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "Enable PCIE RP Clk Req Detect", HEX, + Help "Probe CLKREQ# signal before enabling CLKREQ# based power management." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX, + Help "Indicate whether the Advanced Error Reporting is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX, + Help "Indicate whether the Unsupported Request Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX, + Help "Indicate whether the Fatal Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX, + Help "Indicate whether the No Fatal Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX, + Help "Indicate whether the Correctable Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX, + Help "Indicate whether the System Error on Fatal Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX, + Help "Indicate whether the System Error on Non Fatal Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX, + Help "Indicate whether the System Error on Correctable Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload, "PCIE RP Max Payload", HEX, + Help "Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX, + Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCIE_SPEED)." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX, + Help "Indicates the slot number for the root port. Default is the value as root port index." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "PCIE RP Completion Timeout", HEX, + Help "The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX, + Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_HostL0sTxDis, "HostL0sTxDis", &EN_DIS, + Help "Disable Host L0 transmission state" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates, "PCIE RP L1 Substates", HEX, + Help "The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCIE RP Ltr Enable", HEX, + Help "Latency Tolerance Reporting Mechanism." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEqOverrideDefault, "PCIE RP override default settings for EQ", &EN_DIS, + Help "Choose PCIe EQ method" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMethod, "PCIE RP choose EQ method", &gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMethod, + Help "Choose PCIe EQ method" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMode, "PCIE RP choose EQ mode", &gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMode, + Help "Choose PCIe EQ mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqLocalTxOverrideEn, "PCIE RP EQ local transmitter override", &EN_DIS, + Help "Enable/Disable local transmitter override" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3NoOfPresetOrCoeff, "PCI RP number of valid list entries", HEX, + Help "Select number of presets or coefficients depending on the mode" + "Valid range: 0 ~ 11" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor0List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor0List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor1List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor1List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor2List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor2List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor3List, "PCIR RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor3List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor4List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor4List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor5List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor5List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor6List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor6List, "PCIe post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor7List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor7List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor8List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor8List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor9List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor9List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset0List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset1List, "PCIe preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset2List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset3List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset4List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset5List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset6List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset7List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset8List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset9List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset10List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh1DpTxPreset, "PCIe EQ phase 1 downstream transmitter port preset", HEX, + Help "Allows to select the downstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh1UpTxPreset, "PCIE RP EQ phase 1 upstream tranmitter port preset", HEX, + Help "Allows to select the upstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh2LocalTxOverridePreset, "PCIE RP EQ phase 2 local transmitter override preset", HEX, + Help "Allows to select the value of the preset used during phase 2 local transmitter override" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMethod, "PCIE RP choose EQ method", &gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMethod, + Help "Choose PCIe EQ method" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMode, "PCIE RP choose EQ mode", &gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMode, + Help "Choose PCIe EQ mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqLocalTxOverrideEn, "PCIE RP EQ local transmitter override", &EN_DIS, + Help "Enable/Disable local transmitter override" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3NoOfPresetOrCoeff, "PCI RP number of valid list entries", HEX, + Help "Select number of presets or coefficients depending on the mode" + "Valid range: 0 ~ 11" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor0List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor0List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor1List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor1List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor2List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor2List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor3List, "PCIR RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor3List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor4List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor4List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor5List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor5List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor6List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor6List, "PCIe post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor7List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor7List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor8List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor8List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor9List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor9List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset0List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset1List, "PCIe preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset2List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset3List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset4List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset5List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset6List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset7List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset8List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset9List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset10List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh1DpTxPreset, "PCIe EQ phase 1 downstream transmitter port preset", HEX, + Help "Allows to select the downstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh1UpTxPreset, "PCIE RP EQ phase 1 upstream tranmitter port preset", HEX, + Help "Allows to select the upstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh2LocalTxOverridePreset, "PCIE RP EQ phase 2 local transmitter override preset", HEX, + Help "Allows to select the value of the preset used during phase 2 local transmitter override" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMethod, "PCIE RP choose EQ method", &gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMethod, + Help "Choose PCIe EQ method" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMode, "PCIE RP choose EQ mode", &gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMode, + Help "Choose PCIe EQ mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqLocalTxOverrideEn, "PCIE RP EQ local transmitter override", &EN_DIS, + Help "Enable/Disable local transmitter override" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3NoOfPresetOrCoeff, "PCI RP number of valid list entries", HEX, + Help "Select number of presets or coefficients depending on the mode" + "Valid range: 0 ~ 11" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor0List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor0List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor1List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor1List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor2List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor2List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor3List, "PCIR RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor3List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor4List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor4List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor5List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor5List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor6List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor6List, "PCIe post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor7List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor7List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor8List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor8List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor9List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor9List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset0List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset1List, "PCIe preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset2List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset3List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset4List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset5List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset6List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset7List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset8List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset9List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset10List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh1DpTxPreset, "PCIe EQ phase 1 downstream transmitter port preset", HEX, + Help "Allows to select the downstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh1UpTxPreset, "PCIE RP EQ phase 1 upstream tranmitter port preset", HEX, + Help "Allows to select the upstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh2LocalTxOverridePreset, "PCIE RP EQ phase 2 local transmitter override preset", HEX, + Help "Allows to select the value of the preset used during phase 2 local transmitter override" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Bypass, "Phase3 RP Gen3 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Bypass, + Help "Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh3Bypass, "Phase3 RP Gen4 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh3Bypass, + Help "Phase3 Gen4 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh3Bypass, "Phase3 RP Gen5 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh3Bypass, + Help "Phase3 Gen5 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh23Bypass, "Phase2-3 RP Gen3 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh23Bypass, + Help "Phase2-3 Gen3 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): Enable Phase2-3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh23Bypass, "Phase2-3 RP Gen4 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh23Bypass, + Help "Phase2-3 Gen4 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): Enable Phase2-3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh23Bypass, "Phase2-3 RP Gen5 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh23Bypass, + Help "Phase2-3 Gen5 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): Enable Phase2-3" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3PcetTimer, "PCET Timer", HEX, + Help "Preset/Coefficient Evaluation Timeout Gen3 PCET Timer. See PCIE_GEN3_PCET. Default is 0x0(2ms)" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4PcetTimer, "Gen4 PCET Timer", HEX, + Help "Preset/Coefficient Evaluation Timeout - Gen4 PCET Timer. See PCIE_GEN4_PCET. Default is 0x0(2ms)" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5PcetTimer, "Gen5 PCET Timer", HEX, + Help "Preset/Coefficient Evaluation Timeout - Gen5 PCET Timer. See PCIE_GEN5_PCET. Default is 0x0(2ms)" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3TsLockTimer, "TS Lock Timer for Gen3", HEX, + Help "Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen3 TS Lock Timer. See PCIE_GEN3_TS_LOCK_TIMER. Default is 0x0" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4TsLockTimer, "PTS Lock Timer for Gen4", HEX, + Help "Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen4 TS Lock Timer. See PCIE_GEN4_TS_LCOK_TIMER. Default is 0x0" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5TsLockTimer, "PTS Lock Timer for Gen5", HEX, + Help "Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen5 TS Lock Timer. See PCIE_GEN5_TS_LCOK_TIMER. Default is 0x0" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieSetSecuredRegisterLock, "PCIE Secure Register Lock", &EN_DIS, + Help "Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled, load PcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTestAspmOc, "Enable/Disable ASPM Optionality Compliance", HEX, + Help "Enable/Disable ASPM Optionality Compliance." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite, "PCIE RP Enable Peer Memory Write", &EN_DIS, + Help "This member describes whether Peer Memory Writes are enabled on the platform." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpLinkDownGpios, "Assertion on Link Down GPIOs", &gPlatformFspPkgTokenSpaceGuid_PcieRpLinkDownGpios, + Help "GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS, + Help "Compliance Test Mode shall be enabled when using Compliance Load Board." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS, + Help "Allows BIOS to use root port function number swapping when root port of function 0 is disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieClockGating, "PCIe RootPort Clock Gating", &EN_DIS, + Help "Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_PciePowerGating, "PCIe RootPort Power Gating", &EN_DIS, + Help "Describes whether the PCI Express Power Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieVisaClockGating, "PCIe RootPort VISA Clock Gating", &EN_DIS, + Help "Describes whether the PCI Express VISA Clock Gating. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieAutoPowerGating, "PCIe RootPort AutoPower Gating", &EN_DIS, + Help "Describes the Auto Power Gating for per controller. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_PciePhyAutoPowerGating, "PCIe RootPort PHY AutoPower Gating", &EN_DIS, + Help "Describes the PHY Auto Power Gating for per controller. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieFomsCp, "FOMS Control Policy", &gPlatformFspPkgTokenSpaceGuid_PcieFomsCp, + Help "Choose the Foms Control Policy, Default = 0 " + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEqPhBypass, "EqPhBypass Control Policy", &gPlatformFspPkgTokenSpaceGuid_PcieEqPhBypass, + Help "PCIe Equalization Phase Enable Control, Disabled (0x0) : Disable Phase (Default), Enabled (0x1) : Enable Phase" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency, "PCIE RP Ltr Max Snoop Latency", HEX, + Help "Latency Tolerance Reporting, Max Snoop Latency." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency, "PCIE RP Ltr Max No Snoop Latency", HEX, + Help "Latency Tolerance Reporting, Max Non-Snoop Latency." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale, "PCIE RP Slot Power Limit Scale", HEX, + Help "Specifies scale used for slot power limit value. Leave as 0 to set to default." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue, "PCIE RP Slot Power Limit Value", HEX, + Help "Specifies upper limit on power supplie by slot. Leave as 0 to set to default." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode, "PCIE RP Enable Port8xh Decode", &EN_DIS, + Help "This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex, "PCIE Port8xh Decode Port Index", HEX, + Help "The Index of PCIe Port that is selected for Port8xh Decode (1 Based)." + "Valid range: 0x0 ~ 0x6" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrOverrideSpecCompliant, "PCIE RP LTR Override Spec Compliant", HEX, + Help "Override LTR based on Ep capability." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_GlobalPcieAer, "PCIe AER _OSC Setting", &gPlatformFspPkgTokenSpaceGuid_GlobalPcieAer, + Help "Enable/Disable Global PCIe Advanced Error Reporting" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieTbtPerfBoost, "PCIe TBT Performance Boost Bitmap", HEX, + Help "Bitmap of TBT performance boost enabled PCIe controllers to which discrete TBT controllers connect. Bit0: PXPA, Bit1: PXPB, Bit2: PXPC, Bit3: PXPD, Bit4: PXPE" + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiClkPinMux, "Serial IO SPI CLK Pin Muxing", HEX, + Help "Select SerialIo LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiCsPinMux, "Serial IO SPI CS Pin Muxing", HEX, + Help "Select SerialIo LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiMode, "SPIn Device Mode", HEX, + Help "Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:LpssSpiDisabled, 1:LpssSpiPci, 2:LpssSpiHidden" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiMosiPinMux, "LPSS SPI MOSI Pin Muxing", HEX, + Help "Select LPSS SPI MOSI pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MOSI* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiMisoPinMux, "LPSS SPI MISO Pin Muxing", HEX, + Help "Select Lpss SPI MISO pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MISO* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiCsPolarity, "SPI Chip Select Polarity", HEX, + Help "Sets polarity for each chip Select. Available options: 0:LpssSpiCsActiveLow, 1:LpssSpiCsActiveHigh" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiCsEnable, "SPI Chip Select Enable", HEX, + Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiCsMode, "SPIn Default Chip Select Mode HW/SW", HEX, + Help "Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, SPI1, ... Available options: 0:HW, 1:SW" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoLpssSpiCsState, "SPIn Default Chip Select State Low/High", HEX, + Help "Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... Available options: 0:Low, 1:High" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode, "UARTn Device Mode", HEX, + Help "Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate, "Default BaudRate for each Serial IO UART", HEX, + Help "Set default BaudRate Supported from 0 - default to 6000000" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity, "Default ParityType for each Serial IO UART", HEX, + Help "Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits, "Default DataBits for each Serial IO UART", HEX, + Help "Set default word length. 0: Default, 5,6,7,8" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits, "Default StopBits for each Serial IO UART", HEX, + Help "Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating, "Power Gating mode for each Serial IO UART that works in COM mode", HEX, + Help "Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable, "Enable Dma for each Serial IO UART that supports it", HEX, + Help "Set DMA/PIO mode. 0: Disabled, 1: Enabled" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow, "Enables UART hardware flow control, CTS and RTS lines", HEX, + Help "Enables UART hardware flow control, CTS and RTS lines." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRtsPinMuxPolicy, "SerialIoUartRtsPinMuxPolicy", HEX, + Help "Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRxPinMuxPolicy, "SerialIoUartRxPinMuxPolicy", HEX, + Help "Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartTxPinMuxPolicy, "SerialIoUartTxPinMuxPolicy", HEX, + Help "Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2, "Serial IO UART DBG2 table", HEX, + Help "Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPgDbg2, "Serial IO UART PG DBG2 table", HEX, + Help "Enable or disable Serial Io UART PG DBG2 table, default is Disable; 0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode, "I2Cn Device Mode", HEX, + Help "Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSdaPinMux, "Serial IO I2C SDA Pin Muxing", HEX, + Help "Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSclPinMux, "Serial IO I2C SCL Pin Muxing", HEX, + Help "Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination, "PCH SerialIo I2C Pads Termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cMode, "I3C Device Mode", HEX, + Help "Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci, 2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling)" + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSdaPinMux, "Serial IO I3C SDA Pin Muxing", HEX, + Help "Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSdaPadTermination, "Serial IO I3C SDA Pad Termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on." + "Valid range: 0 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclPinMux, "Serial IO I3C SCL Pin Muxing", HEX, + Help "Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclPadTermination, "Serial IO I3C SCL Pad Termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on." + "Valid range: 0 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclFbPinMux, "Serial IO I3C SCL FB Pin Muxing", HEX, + Help "Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclFbPadTermination, "Serial IO I3C SCL FB Pad Termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on." + "Valid range: 0 ~ 0xFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdEnable, "Enable VMD controller", &EN_DIS, + Help "Enable/disable to VMD controller.0: Disable; 1: Enable(Default)" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdGlobalMapping, "Enable VMD Global Mapping", &EN_DIS, + Help "Enable/disable to VMD controller.0: Disable(Default); 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdPort, "Map port under VMD", &EN_DIS, + Help "Map/UnMap port under VMD" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortBus, "VMD Port Bus", DEC, + Help "VMD Root port bus number." + "Valid range: 0 ~ 255" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortDev, "VMD Port Device", DEC, + Help "VMD Root port device number." + "Valid range: 0 ~ 31" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortFunc, "VMD Port Func", DEC, + Help "VMD Root port function number." + "Valid range: 0 ~ 7" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdVariablePtr, "VMD Variable", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBase, "Temporary CfgBar address for VMD", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Base, "Temporary MemBar1 address for VMD", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Base, "Temporary MemBar2 address for VMD", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_D3HotEnable, "Enable D3 Hot in TCSS ", &EN_DIS, + Help "This policy will enable/disable D3 hot support in IOM" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssTbtPerfBoost, "TCSS TBT Performance Boost Bitmap", HEX, + Help "Bitmap of TBT performance boost enabled TCSS PCIe root ports. Bit0: TCSS port0, Bit1: TCSS port1, Bit2: TCSS port2, Bit3: TCSS port3" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IomTypeCPortPadCfg, "TypeC port GPIO setting", HEX, + Help "GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Lnl = LunarLake)" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuUsb3OverCurrentPin, "CPU USB3 Port Over Current Pin", HEX, + Help "Describe the specific over current pin number of USBC Port N." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_D3ColdEnable, "Enable D3 Cold in TCSS ", &EN_DIS, + Help "This policy will enable/disable D3 cold support in IOM" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcCstateLimit, "TC State in TCSS ", HEX, + Help "This TC C-State Limit in IOM" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcNotifyIgd, "TC Notify Igd ", HEX, + Help "Tc Notify Igd" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssCpuUsbPdoProgramming, "TCSS CPU USB PDO Programming", &EN_DIS, + Help "Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcPdEnable, "Enable/Disable PMC-PD Solution ", &EN_DIS, + Help "This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssAuxOri, "TCSS Aux Orientation Override Enable", HEX, + Help "Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides" + "Valid range: 0x0 ~ 0x0FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssHslOri, "TCSS HSL Orientation Override Enable", HEX, + Help "Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides" + "Valid range: 0x0 ~ 0x0FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_UsbTcPortEn, "TCSS USB Port Enable", HEX, + Help "Bits 0, 1, ... max Type C port control enables" + "Valid range: 0x0 ~ 0x000F" + Combo $gPlatformFspPkgTokenSpaceGuid_VccSt, "VCCST request for IOM ", &EN_DIS, + Help "This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5" + Combo $gPlatformFspPkgTokenSpaceGuid_PtmEnabled, "Enable/Disable PTM", &EN_DIS, + Help "This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpLtrEnable, "PCIE RP Ltr Enable", HEX, + Help "Latency Tolerance Reporting Mechanism." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpForceLtrOverride, "Force LTR Override", HEX, + Help "Force LTR Override." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcssCovTypeA, "Type C Port x Convert to TypeA", &EN_DIS, + Help "Enable / Disable(default) Type C Port x Convert to TypeA" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcAssignment, "Touch Host Controller Assignment", HEX, + Help "Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcInterruptPinMuxing, "Touch Host Controller Interrupt Pin Mux", HEX, + Help "Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcMode, "Touch Host Controller Mode", HEX, + Help "Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcWakeOnTouch, "Touch Host Controller Wake On Touch", HEX, + Help "Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcActiveLtr, "Touch Host Controller Active Ltr", HEX, + Help "Expose Active Ltr for OS driver to set" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcIdleLtr, "Touch Host Controller Idle Ltr", HEX, + Help "Expose Idle Ltr for OS driver to set" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TimestampTimerMode, "Touch Host Controller Timestamp timer behavior in D0i2", HEX, + Help "Timestamp timer behavior in D0i2. 1 = Timer resets to 0 when entering D0i2 0 = Timer is paused instead of reset to 0 when entering D0i2" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DisplayFrameSyncPeriod, "Touch Host Controller Display Frame Sync Period", HEX, + Help "Period of the emulated display frame sync [ms] The minimum period is 2ms, maximum period is 100ms" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcResetPad, "Touch Host Controller ResetPad", HEX, + Help "ResetPad" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcResetPadTrigger, "Touch Host Controller ResetPad Trigger", HEX, + Help "Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcDsyncPad, "Touch Host Controller DYSync", HEX, + Help "Based on this setting GPIO for given THC will be in native mode" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiConnectionSpeed, "Touch Host Controller Hid Over Spi Connection Speed", HEX, + Help "Hid Over Spi Connection Speed - SPI Frequency" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiLimitPacketSize, "Touch Host Controller Hid Over Spi Limit PacketSize", HEX, + Help "When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcPerformanceLimitation, "Touch Host Controller Hid Over Spi Limit PacketSize", HEX, + Help "Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation and begin of read operation. This value shall be in 10us multiples 0x0: Disabled, 1-65535 (0xFFFF) - up to 655350 us" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiInputReportHeaderAddress, "Touch Host Controller Hid Over Spi Input Report Header Address", HEX, + Help "Hid Over Spi Input Report Header Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiInputReportBodyAddress, "Touch Host Controller Hid Over Spi Input Report Body Address", HEX, + Help "Hid Over Spi Input Report Body Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiOutputReportAddress, "Touch Host Controller Hid Over Spi Output Report Address", HEX, + Help "Hid Over Spi Output Report Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiReadOpcode, "Touch Host Controller Hid Over Spi Read Opcode", HEX, + Help "Hid Over Spi Read Opcode" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiWriteOpcode, "Touch Host Controller Hid Over Spi Write Opcode", HEX, + Help "Hid Over Spi Write Opcode" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiFlags, "Touch Host Controller Hid Over Spi Flags", HEX, + Help "Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcResetSequencingDelay, "Touch Host Controller Reset Sequencing Delay [ms]", HEX, + Help "Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cDeviceAddress, "Touch Host Controller Hid Over I2c Device Address", HEX, + Help "Hid Over I2c Device Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cConnectionSpeed, "Touch Host Controller Hid Over I2c Connection Speed", HEX, + Help "Hid Over I2c Connection Speed [Hz]" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cAddressingMode, "Touch Host Controller Hid Over I2c Addressing Mode", HEX, + Help "Hid Over I2c Addressing Mode - 0x1: The connection uses 10-bit addressing. 0x0: The connection uses 7-bit addressing." + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cDeviceDescriptorAddress, "Touch Host Controller Hid Over I2c Device Descriptor Address", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cStandardModeSerialClockLineHighPeriod, "Touch Host Controller Hid Over I2c Serial Clock Line High Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cStandardModeSerialClockLineLowPeriod, "Touch Host Controller Hid Over I2c Standard Mode Serial Clock Line Low Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cStandardModeSerialDataLineTransmitHoldPeriod, "Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Transmit Hold Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cStandardModeSerialDataLineReceiveHoldPeriod, "Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Receive Hold Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModeSerialClockLineHighPeriod, "Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line High Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModeSerialClockLineLowPeriod, "Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line Low Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModeSerialDataLineTransmitHoldPeriod, "Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Transmit Hold Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModeSerialDataLineReceiveHoldPeriod, "Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Receive Hold Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cMaxSuppressedSpikesSMFMFMP, "Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In Std Mode Fast Mode And Fast Mode Plus", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModePlusSerialClockLineHighPeriod, "Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line High Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModePlusSerialClockLineLowPeriod, "Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line Low Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModePlusSerialDataLineTransmitHoldPeriod, "Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Transmit Hold Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cFastModePlusSerialDataLineReceiveHoldPeriod, "Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Receive Hold Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cHighSpeedModePlusSerialClockLineHighPeriod, "Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line High Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cHighSpeedModePlusSerialClockLineLowPeriod, "Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line Low Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cHighSpeedModePlusSerialDataLineTransmitHoldPeriod, "Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Transmit Hold Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cHighSpeedModePlusSerialDataLineReceiveHoldPeriod, "Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Receive Hold Period", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cMaximumLengthOfSuppressedSpikesInHighSpeedMode, "Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In High Speed Mode", HEX, + Help "Hid Over I2c Device Descriptor Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcWotEdgeLevel, "THC Wake On Touch GPIO resource Edge or Level", HEX, + Help "Definition of GPIO resource configuration of Edge or Level" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcWotActiveLevel, "THC Wake On Touch GPIO resource of Active Level", HEX, + Help "Definition of GPIO resource configuration of Active Level" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcWotPinConfig, "THC Wake On Touch GPIO resource of pin configuration", HEX, + Help "Definition of GPIO resource configuration of pin configuration" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcCustomizedSsid, "THC customized SubSytem ID for Port", HEX, + Help "Definition of GPIO resource configuration of pin configuration" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcCustomizedSvid, "THC Sets Customized SubSytem Vendor ID for Port", HEX, + Help "Definition of GPIO resource configuration of pin configuration" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb31PortSpeed, "USB 3.1 Speed Selection", HEX, + Help "Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cMaxFrameSize, "Touch Host Controller Hid Over I2c Maximum Frame Size Enable ", HEX, + Help "Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cMaxFrameSizeValue, "Touch Host Controller Hid Over I2c Maximum Frame Size Value", HEX, + Help "Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cIntDelay, "Touch Host Controller Hid Over I2c Interrupt Delay Enable", HEX, + Help "Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidI2cIntDelayValue, "Touch Host Controller Hid Over I2c Interrupt Delay Value", HEX, + Help "Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPostMemRsvd, "PchPostMemRsvd", &EN_DIS, + Help "Reserved for PCH Post-Mem" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHotEnable, "PCHHOT# pin", &EN_DIS, + Help "Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchT0Level, "Thermal Throttling Custimized T0Level Value", HEX, + Help "Custimized T0Level value." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchT1Level, "Thermal Throttling Custimized T1Level Value", HEX, + Help "Custimized T1Level value." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchT2Level, "Thermal Throttling Custimized T2Level Value", HEX, + Help "Custimized T2Level value." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchTTEnable, "Enable The Thermal Throttle", &EN_DIS, + Help "Enable the thermal throttle function." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable, "PMSync State 13", &EN_DIS, + Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTTLock, "Thermal Throttle Lock", &EN_DIS, + Help "Thermal Throttle Lock." + Combo $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting, "Thermal Throttling Suggested Setting", &EN_DIS, + Help "Thermal Throttling Suggested Setting." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel, "Thermal Device Temperature", HEX, + Help "Decides the temperature." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchTsnEnable, "Enable PCH TSN", &EN_DIS, + Help "Enable/disable TSN on the PCH." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsn1MacAddressHigh, "PCH TSN MAC Address High Bits", HEX, + Help "Set TSN MAC Address High." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsn1MacAddressLow, "PCH TSN MAC Address Low Bits", HEX, + Help "Set TSN MAC Address Low." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsn2MacAddressHigh, "PCH TSN2 MAC Address High Bits", HEX, + Help "Set TSN2 MAC Address High." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsn2MacAddressLow, "PCH TSN2 MAC Address Low Bits", HEX, + Help "Set TSN2 MAC Address Low." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsn3MacAddressHigh, "PCH TSN3 MAC Address High Bits", HEX, + Help "Set TSN3 MAC Address High." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsn3MacAddressLow, "PCH TSN3 MAC Address Low Bits", HEX, + Help "Set TSN3 MAC Address Low." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsn4MacAddressHigh, "PCH TSN4 MAC Address High Bits", HEX, + Help "Set TSN4 MAC Address High." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsn4MacAddressLow, "PCH TSN MAC4 Address Low Bits", HEX, + Help "Set TSN MAC4 Address Low." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX, + Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX, + Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_XdciEnable, "Enable xDCI controller", &EN_DIS, + Help "Enable/disable to xDCI controller." + Combo $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming, "USB PDO Programming", &EN_DIS, + Help "Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciUaolEnable, "USB Audio Offload enable", &EN_DIS, + Help "Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default)" + Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable, "PCH USB OverCurrent mapping enable", &EN_DIS, + Help "1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin, "USB2 Port Over Current Pin", HEX, + Help "Describe the specific over current pin number of USB 2.0 Port N." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin, "USB3 Port Over Current Pin", HEX, + Help "Describe the specific over current pin number of USB 3.0 Port N." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable, "Enable xHCI LTR override", &EN_DIS, + Help "Enables override of recommended LTR values for xHCI" + Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciDwbEnable, "USB DWB enable", &EN_DIS, + Help "Enable/Disable USB DWB. 0: disabled, 1: enabled (default)" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride, "xHCI High Idle Time LTR override", HEX, + Help "Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride, "xHCI Medium Idle Time LTR override", HEX, + Help "Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride, "xHCI Low Idle Time LTR override", HEX, + Help "Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PortResetMessageEnable, "USB2 Port Reset Message Enable", HEX, + Help "0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must be enable for USB2 Port those are paired with CPU XHCI Port" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock, "PCH USB OverCurrent mapping lock enable", &EN_DIS, + Help "If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked." + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPetxiset, "USB Per Port HS Preemphasis Bias", HEX, + Help "USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyTxiset, "USB Per Port HS Transmitter Bias", HEX, + Help "USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPredeemp, "USB Per Port HS Transmitter Emphasis", HEX, + Help "USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPehalfbit, "USB Per Port Half Bit Pre-emphasis", HEX, + Help "USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable, "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment", HEX, + Help "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph, "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting", HEX, + Help "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable, "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, + Help "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp, "USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, + Help "USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 3", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 2", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 1", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 0", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieFiaProgramming, "PCIe Fia Programming", &EN_DIS, + Help "Load Fia configuration if enable. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_SseCommunication, "Enable SSE Device", &EN_DIS, + Help "Test, 0: POR, 1: enable, 2: disable, Enable/Disable SSE/SSE++ Devices from PCI config space" + Combo $gPlatformFspPkgTokenSpaceGuid_MePostMemRestrictedRsvd, "MePostMemRestrictedRsvd", &EN_DIS, + Help "Reserved for ME Post-Mem Restricted" + Combo $gPlatformFspPkgTokenSpaceGuid_NpuEnable, "Enable/Disable NPU Device", &EN_DIS, + Help "Enable(Default): Enable NPU Device, Disable: Disable NPU Device" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLanEnable, "Enable LAN", &EN_DIS, + Help "Enable/disable LAN controller." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS, + Help "0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLanWOLFastSupport, "PCH Lan WOL Fast Support", &EN_DIS, + Help "Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm." +EndPage + +Page "CPU(PostMem)" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBistData, "CpuBistData", HEX, + Help "Pointer CPU BIST Data" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi, "CpuMpPpi", HEX, + Help "Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. If not NULL, FSP will use the boot loader's implementation of multiprocessing. See section 5.1.4 of the FSP Integration Guide for more details." + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogEnable, "Enable/Disable CrashLog", &EN_DIS, + Help "Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog" + Combo $gPlatformFspPkgTokenSpaceGuid_StreamTracerMode, "StreamTracer Mode", &gPlatformFspPkgTokenSpaceGuid_StreamTracerMode, + Help "Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended when all groups in high verbosity are traced in 'red', Auto: StreamTracer size 8MB - Recommended when using up to 8 groups red or up to 16 groups in green in med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB" + EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase, "MicrocodeRegionBase", HEX, + Help "Memory Base of Microcode Updates" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize, "MicrocodeRegionSize", HEX, + Help "Size of Microcode Updates" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TxtEnable, "Enable or Disable TXT", &EN_DIS, + Help "Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect. 0: Disable, 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_PpinSupport, "PpinSupport to view Protected Processor Inventory Number", &gPlatformFspPkgTokenSpaceGuid_PpinSupport, + Help "PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn off this feature. When 'PPIN Enable Mode' is selected, this shows second option where feature can be enabled based on EOM (End of Manufacturing) flag or it is always enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_AesEnable, "Advanced Encryption Standard (AES) feature", &EN_DIS, + Help "Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_AvxDisable, "AvxDisable", &gPlatformFspPkgTokenSpaceGuid_AvxDisable, + Help "Enable/Disable the AVX and AVX2 Instructions" + Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicEnable, "X2ApicEnable", &EN_DIS, + Help "Enable/Disable X2APIC Operating Mode. When this option is configured as 'Enabled', 'VT-d' option must be 'Enabled'." + EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16, "P-state ratios for max 16 version of custom P-state table", HEX, + Help "P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F" + "Valid range: 0x00 ~ 0x7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F" + Combo $gPlatformFspPkgTokenSpaceGuid_Eist, "Enable or Disable Intel SpeedStep Technology", &EN_DIS, + Help "Allows more than two frequency ranges to be supported. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState, "Enable or Disable Energy Efficient P-state", &EN_DIS, + Help "Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 1 indicating Energy Efficient policy setting is supported. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, "Enable or Disable Energy Efficient Turbo", &EN_DIS, + Help "Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, leave enabled. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_TStates, "Enable or Disable T states", &EN_DIS, + Help "Enable or Disable T states; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_EnableAllThermalFunctions, "Enable or Disable Thermal Reporting", &EN_DIS, + Help "Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_Cx, "Enable or Disable CPU power states (C-states)", &EN_DIS, + Help "Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock, "Configure C-State Configuration Lock", &EN_DIS, + Help "Configure MSR to CFG Lock bit. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion, "Enable or Disable Package Cstate Demotion", &EN_DIS, + Help "Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Enable or Disable Package Cstate UnDemotion", &EN_DIS, + Help "Enable or Disable Package C-State Un-Demotion. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_CStatePreWake, "Enable or Disable CState-Pre wake", &EN_DIS, + Help "Disable - to disable the Cstate Pre-Wake. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_TimedMwait, "Enable or Disable TimedMwait Support.", &EN_DIS, + Help "Enable or Disable TimedMwait Support. 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit, "Set the Max Pkg Cstate", HEX, + Help "Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. Auto: Initializes to deepest available Package C State Limit. Valid values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 - CPU Default, 255 - Auto" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ForcePrDemotion, "ForcePr Demotion Algorithm configuration", &gPlatformFspPkgTokenSpaceGuid_ForcePrDemotion, + Help "ForcePr Demotion Algorithm configuration. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_VrAlertDemotion, "VrAlert Demotion Algorithm configuration", &gPlatformFspPkgTokenSpaceGuid_VrAlertDemotion, + Help "VrAlert Demotion Algorithm configuration. 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting, "Interrupt Redirection Mode Select", HEX, + Help "Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1: Round robin; 2: Hash vector; 7: No change." + "Valid range: 0x00 ~ 0x7" + Combo $gPlatformFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS, + Help "Enable/Disable processor Turbo Mode. 0:disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerFloorPcieGenDowngrade, "Power Floor PCIe Gen Downgrade", &EN_DIS, + Help "SoC can downgrade PCIe gen speed to lower SoC floor power (Default enabled). 0: Disable: Reduction in PCIe gen speed will not be used by SoC., 1: Enable " + EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatio, "P-state ratios for custom P-state table", HEX, + Help "P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F" + "Valid range: 0x00 ~ 0x7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F" + EditNum $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries, "Custom Ratio State Entries", HEX, + Help "The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table. Sets the number of custom P-states. At least 2 states must be present" + "Valid range: 0x00 ~ 0x28" + EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRatio, "Max P-State Ratio", HEX, + Help "Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F" + "Valid range: 0x00 ~ 0x7F" + Combo $gPlatformFspPkgTokenSpaceGuid_BootFrequency, "Boot frequency", &gPlatformFspPkgTokenSpaceGuid_BootFrequency, + Help "Select the performance state that the BIOS will set starting from reset vector. 0: Maximum battery performance. 1: Maximum non-turbo performance. 2: Turbo performance " + Combo $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock, "Turbo settings Lock", &EN_DIS, + Help "Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableFastMsrHwpReq, "FastMsrHwpReq", &EN_DIS, + Help "0: Disable; 1: Enable;" + EditNum $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitRatio, "Turbo Ratio Limit Ratio array", HEX, + Help "Performance-core Turbo Ratio Limit Ratio0-7 (TRLR) defines the turbo ratio (max is 85 in normal mode and 120 in core extension mode). Ratio[0]: This Turbo Ratio Limit Ratio0 must be greater than or equal all other ratio values. If this value is invalid, thn set all other active cores to minimum. Otherwise, align the Ratio Limit to 0. Please check each active cores. Ratio[1~7]: This Turbo Ratio Limit Ratio1 must be <= to Turbo Ratio Limit Ratio0~6." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitNumCore, "Turbo Ratio Limit Num Core array", HEX, + Help "Performance-core Turbo Ratio Limit Core0~7 defines the core range, the turbo ratio is defined in Turbo Ratio Limit Ratio0~7. If value is zero, this entry is ignored." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitRatio, "ATOM Turbo Ratio Limit Ratio array", HEX, + Help "Efficient-core Turbo Ratio Limit Ratio0-7 defines the turbo ratio (max is 85 irrespective of the core extension mode), the core range is defined in E-core Turbo Ratio Limit CoreCount0-7." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitNumCore, "ATOM Turbo Ratio Limit Num Core array", HEX, + Help "Efficient-core Turbo Ratio Limit CoreCount0-7 defines the core range, the turbo ratio is defined in E-core Turbo Ratio Limit Ratio0-7. If value is zero, this entry is ignored." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_RaceToHalt, "Race To Halt", &EN_DIS, + Help "Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion, "Enable or Disable C1 Cstate Demotion", &EN_DIS, + Help "Enable or Disable C1 Cstate Auto Demotion. Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion, "Enable or Disable C1 Cstate UnDemotion", &EN_DIS, + Help "Enable or Disable C1 Cstate Un-Demotion. Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit, "Minimum Ring ratio limit override", HEX, + Help "Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" + "Valid range: 0x00 ~ 0x53" + EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit, "Maximum Ring ratio limit override", HEX, + Help "Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" + "Valid range: 0x00 ~ 0x53" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableRp, "Resource Priority Feature", &EN_DIS, + Help "Enable/Disable Resource Priority Feature. Enable/Disable; 0: Disable, 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_Hwp, "Enable or Disable HWP", &EN_DIS, + Help "Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; 1: Enable;" + Combo $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl, "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT", &EN_DIS, + Help "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoPerCorePstate, "Enable or Disable HwP Autonomous Per Core P State OS control", &EN_DIS, + Help "Disable Autonomous PCPS Autonomous will request the same value for all cores all the time. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoEppGrouping, "Enable or Disable HwP Autonomous EPP Grouping", &EN_DIS, + Help "Enable EPP grouping Autonomous will request the same values for all cores with same EPP. Disable EPP grouping autonomous will not necessarily request same values for all cores with same EPP. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableDynamicEfficiencyControl, "Dynamic Efficiency Control", &EN_DIS, + Help "Enable or Disable SoC to control energy efficiency targets autonomously, regardless of EPP, EPB and other SW inputs. 0: Disable; 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_HwpLock, "Misc Power Management MSR Lock", &EN_DIS, + Help "Enable/Disable HWP Lock support in Misc Power Management MSR. 0: Disable, 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_PowerFloorManagement, "Power Floor Managment for SOC", &EN_DIS, + Help "Option to disable Power Floor Managment for SOC. Disabling this might effectively raise power floor of the SoC and may lead to stability issues. 0: Disable, 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_PowerFloorDisplayDisconnect, "Power Floor Disaplay Disconnect", &EN_DIS, + Help "SoC can disconnect secondary/external display to lower SoC floor power (Default disabled). 0: Disable: Display disconnect will not be used by SoC., 1: Enable " + EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemSize, "Memory size per thread allocated for Processor Trace", HEX, + Help "Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB.\n 0xff:none , 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k, 0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher, "Enable or Disable MLC Streamer Prefetcher", &EN_DIS, + Help "Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher, "Enable or Disable MLC Spatial Prefetcher", &EN_DIS, + Help "Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Enable or Disable Monitor /MWAIT instructions", &EN_DIS, + Help "Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner should not set in MWAIT Loop. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable, "Enable or Disable initialization of machine check registers", &EN_DIS, + Help "Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, "Control on Processor Trace output scheme", &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, + Help "Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output." + Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable, "Enable or Disable Processor Trace feature", &EN_DIS, + Help "Enable or Disable Processor Trace feature; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceBspOnly, "Processor trace enabled for Bsp only or all cores", &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceBspOnly, + Help "Processor trace enabled for Bsp only or all cores; 0: all cores; 1: Bsp only." + Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceTimingPacket, "Enable/Disable processor trace Timing Packet", &EN_DIS, + Help "Enable/Disable collocting processor trace performance (CYC, TSC); 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounter, "Enable or Disable Three Strike Counter", &EN_DIS, + Help "Enable (default): Three Strike counter will be incremented. Disable: Prevents Three Strike counter from incrementing; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_UfsEnable, "UFS enable/disable", &EN_DIS, + Help "Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller 0 and (0,1) to enable controller 1" + Combo $gPlatformFspPkgTokenSpaceGuid_UfsInlineEncryption, "UFS Inline Encryption enable/disable", &EN_DIS, + Help "Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0) to enable Inline Encryption for controller 0 and (0, 1) to enable Inline Encryption for controller 1" + Combo $gPlatformFspPkgTokenSpaceGuid_UfsDeviceConnected, "UFS Connection Status", &EN_DIS, + Help "UFS Connection Status, One byte for each Controller - (1,0) to UFS connected to controller 0 and (0,1) to UFS connected to controller 1" + Combo $gPlatformFspPkgTokenSpaceGuid_ITbtPcieTunnelingForUsb4, "Enable/Disable PCIe tunneling for USB4", &EN_DIS, + Help "Enable/Disable PCIe tunneling for USB4, default is enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_ITbtForcePowerOnTimeoutInMs, "ITBTForcePowerOn Timeout value", HEX, + Help "ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. 100 = 100 ms." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ITbtConnectTopologyTimeoutInMs, "ITbtConnectTopology Timeout value", HEX, + Help "ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range is 0-10000. 100 = 100 ms." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ITbtDmaLtr, "ITBT DMA LTR", HEX, + Help "TCSS DMA1, DMA2 LTR value" + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb4CmMode, "ITbt Usb4CmMode value", HEX, + Help "ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FspsValidationPtr, "FSPS Validation", HEX, + Help "Point to FSPS Validation configuration structure" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_IehMode, "IEH Mode", &gPlatformFspPkgTokenSpaceGuid_IehMode, + Help "Integrated Error Handler Mode, 0: Bypass, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_RtcBiosInterfaceLock, "RTC BIOS Interface Lock", &EN_DIS, + Help "Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed." + Combo $gPlatformFspPkgTokenSpaceGuid_RtcMemoryLock, "RTC Cmos Memory Lock", &EN_DIS, + Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM." + Combo $gPlatformFspPkgTokenSpaceGuid_AmtEnabled, "AMT Switch", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality." + Combo $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled, "SOL Switch", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." + Combo $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled, "WatchDog Timer Switch", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0." + EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs, "OS Timer", HEX, + Help "16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios, "BIOS Timer", HEX, + Help "16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_IaxEnable, "Iax Switch", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable Iax functionality." + EditNum $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPinMuxing, "ISH GP GPIO Pin Muxing", HEX, + Help "Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRxPinMuxing, "ISH UART Rx Pin Muxing", HEX, + Help "Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartTxPinMuxing, "ISH UART Tx Pin Muxing", HEX, + Help "Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPinMuxing, "ISH UART Rts Pin Muxing", HEX, + Help "Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPinMuxing, "ISH UART Rts Pin Muxing", HEX, + Help "Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPinMuxing, "ISH I2C SDA Pin Muxing", HEX, + Help "Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPinMuxing, "ISH I2C SCL Pin Muxing", HEX, + Help "Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPinMuxing, "ISH SPI MOSI Pin Muxing", HEX, + Help "Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPinMuxing, "ISH SPI MISO Pin Muxing", HEX, + Help "Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPinMuxing, "ISH SPI CLK Pin Muxing", HEX, + Help "Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPinMuxing, "ISH SPI CS#N Pin Muxing", HEX, + Help "Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS_* for possible values. N-SPI number, 0-1." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPadTermination, "ISH GP GPIO Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRxPadTermination, "ISH UART Rx Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 Rx, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartTxPadTermination, "ISH UART Tx Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 Tx, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPadTermination, "ISH UART Rts Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 Rts, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPadTermination, "ISH UART Rts Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 Cts, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPadTermination, "ISH I2C SDA Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPadTermination, "ISH I2C SCL Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPadTermination, "ISH SPI MOSI Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 Mosi, and so on." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPadTermination, "ISH SPI MISO Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 Miso, and so on." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPadTermination, "ISH SPI CLK Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, and so on." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPadTermination, "ISH SPI CS#N Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCsEnable, "Enable PCH ISH SPI Cs#N pins assigned", HEX, + Help "Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs number: 0-1" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCs0Enable, "Enable PCH ISH SPI Cs0 pins assigned", HEX, + Help "Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshSpiEnable, "Enable PCH ISH SPI pins assigned", HEX, + Help "Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshUartEnable, "Enable PCH ISH UART pins assigned", HEX, + Help "Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshI2cEnable, "Enable PCH ISH I2C pins assigned", HEX, + Help "Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshGpEnable, "Enable PCH ISH GP pins assigned", HEX, + Help "Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS, + Help "0: False; 1: True." + Combo $gPlatformFspPkgTokenSpaceGuid_PchIshMsiInterrupt, "PCH ISH MSI Interrupts", &EN_DIS, + Help "0: False; 1: True." +EndPage + +Page "System Agent(PostMem)" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight, "LogoPixelHeight Address", HEX, + Help "Address of LogoPixelHeight" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth, "LogoPixelWidth Address", HEX, + Help "Address of LogoPixelWidth" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress, "Blt Buffer Address", HEX, + Help "Address of Blt buffer" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr, "Graphics Configuration Ptr", HEX, + Help "Points to VBT" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SkipFspGop, "Enable/Disable SkipFspGop", &EN_DIS, + Help "Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigureMedia, "Enable/Disable Media Configuration", &EN_DIS, + Help "Enable(Default): Configure Media for use, Disable: Skip Media Configuration" + Combo $gPlatformFspPkgTokenSpaceGuid_RenderStandby, "Enable/Disable IGFX RenderStandby", &EN_DIS, + Help "Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigureGT, "Enable/Disable GT Configuration", &EN_DIS, + Help "Enable(Default): Configure GT for use, Disable: Skip GT Configuration" + Combo $gPlatformFspPkgTokenSpaceGuid_RC1pGtFreqEnable, "Enable RC1p GT frequency request to PMA (provided all other conditions are met)", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_RC1pMediaFreqEnable, "Enable RC1p Media frequency request to PMA (provided all other conditions are met)", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PavpEnable, "Enable/Disable PavpEnable", &EN_DIS, + Help "Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable" + Combo $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS, + Help "Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable: FSP will NOT initialize the framebuffer." + Combo $gPlatformFspPkgTokenSpaceGuid_MediaStandby, "Enable/Disable IGFX Media Standby", &EN_DIS, + Help "Enable(Default): Enable IGFX Media Standby, Disable: Disable IGFX MediaStandby" + Combo $gPlatformFspPkgTokenSpaceGuid_Dev2IsGfxWorkstation, "Enable/Disable Gfx Workstation", &EN_DIS, + Help "Enable(Default): Is a workstation, Disable: Is not a workstation" + EditNum $gPlatformFspPkgTokenSpaceGuid_VbtSize, "Intel Graphics VBT (Video BIOS Table) Size", HEX, + Help "Size of Internal Graphics VBT Image" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_LidStatus, "Platform LID Status for LFP Displays.", &gPlatformFspPkgTokenSpaceGuid_LidStatus, + Help "LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen." + EditNum $gPlatformFspPkgTokenSpaceGuid_MaxActiveDisplays, "Select MaxActiveDisplays", HEX, + Help "Max Active Display : 0 - Default VBT, 1 - 1 display, 2 - 2 displays, Maximum supported is 2 displays only" + "Valid range: 0x00 ~ 0x02" + EditNum $gPlatformFspPkgTokenSpaceGuid_HorizontalResolution, "HorizontalResolution for PEI Logo", HEX, + Help "HorizontalResolution from PEIm Gfx for PEI Logo" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VerticalResolution, "VerticalResolution for PEI Logo", HEX, + Help "VerticalResolution from PEIm Gfx for PEI Logo" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr, "Address of PCH_DEVICE_INTERRUPT_CONFIG table.", HEX, + Help "The address of the table of PCH_DEVICE_INTERRUPT_CONFIG." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig, "Number of DevIntConfig Entry", HEX, + Help "Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL." + "Valid range: 0x00 ~ 0x40" + EditNum $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute, "Select GPIO IRQ Route", HEX, + Help "GPIO IRQ Select. The valid value is 14 or 15." + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect, "Select SciIrqSelect", HEX, + Help "SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only." + "Valid range: 0x00 ~ 0x17" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect, "Select TcoIrqSelect", HEX, + Help "TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23." + "Valid range: 0x00 ~ 0x17" + Combo $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable, "Enable/Disable Tco IRQ", &EN_DIS, + Help "Enable/disable TCO IRQ" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrEn, "PMC ADR enable", &EN_DIS, + Help "Enable/disable asynchronous DRAM refresh" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimerEn, "PMC ADR timer configuration enable", &EN_DIS, + Help "Enable/disable ADR timer configuration" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimer1Val, "PMC ADR phase 1 timer value", HEX, + Help "Enable/disable ADR timer configuration" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcAdrMultiplier1Val, "PMC ADR phase 1 timer multiplier value", HEX, + Help "Specify the multiplier value for phase 1 ADR timer" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrHostPartitionReset, "PMC ADR host reset partition enable", &EN_DIS, + Help "Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailEnabledStates, "Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states", HEX, + Help "Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5" + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailSupportedVoltageStates, "Mask to enable the platform configuration of external V1p05 VR rail", HEX, + Help "External V1P05 Rail Supported Configuration" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailVoltage, "External V1P05 Voltage Value that will be used in S0i2/S0i3 states", HEX, + Help "Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)" + "Valid range: 0x0 ~ 0x07FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMax, "External V1P05 Icc Max Value", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 200mA" + "Valid range: 0x0 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailEnabledStates, "Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states", HEX, + Help "Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5" + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSupportedVoltageStates, "Mask to enable the platform configuration of external Vnn VR rail", HEX, + Help "External Vnn Rail Supported Configuration" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailVoltage, "External Vnn Voltage Value that will be used in S0ix/Sx states", HEX, + Help "Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420" + "Valid range: 0x0 ~ 0x07FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMax, "External Vnn Icc Max Value that will be used in S0ix/Sx states", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 200mA" + "Valid range: 0x0 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxEnabledStates, "Mask to enable the usage of external Vnn VR rail in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5" + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxVoltage, "External Vnn Voltage Value that will be used in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)" + "Valid range: 0x0 ~ 0x07FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMax, "External Vnn Icc Max Value that will be used in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 200mA" + "Valid range: 0x0 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxLowToHighCurModeVolTranTime, "Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToHighCurModeVolTranTime, "Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToLowCurModeVolTranTime, "Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxOffToHighCurModeVolTranTime, "Transition time in microseconds from Off (0V) to High Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 Transition to 0V is disabled." + "Valid range: 0x0 ~ 0x7FF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchFivrDynPm, "FIVR Dynamic Power Management", &EN_DIS, + Help "Enable/Disable FIVR Dynamic Power Management." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMaximum, "External V1P05 Icc Max Value", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 500mA" + "Valid range: 0x0 ~ 0x1F4" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMaximum, "External Vnn Icc Max Value that will be used in S0ix/Sx states", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 500mA" + "Valid range: 0x0 ~ 0x1F4" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMaximum, "External Vnn Icc Max Value that will be used in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 500mA" + "Valid range: 0x0 ~ 0x1F4" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailCtrlRampTmr, "External V1P05 Control Ramp Timer value", HEX, + Help "Hold off time to be used when changing the v1p05_ctrl for external bypass value in us" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailCtrlRampTmr, "External VNN Control Ramp Timer value", HEX, + Help "Hold off time to be used when changing the vnn_ctrl for external bypass value in us" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchCrid, "PCH Compatibility Revision ID", &EN_DIS, + Help "This member describes whether or not the CRID feature of PCH should be enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency, "PCH Legacy IO Low Latency Enable", &EN_DIS, + Help "Set to enable low latency of legacy IO. 0: Disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_SvTestUnhideP2sb, "PCH P2SB", &EN_DIS, + Help "PCH P2SB" + Combo $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock, "PCH Unlock SideBand access", &EN_DIS, + Help "The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access." + Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating, "Enable 8254 Static Clock Gating", &EN_DIS, + Help "Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3, "Enable 8254 Static Clock Gating On S3", &EN_DIS, + Help "This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming." + Combo $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119, "Enable PCH Io Apic Entry 24-119", &EN_DIS, + Help "0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicId, "PCH Io Apic ID", HEX, + Help "This member determines IOAPIC ID. Default is 0x02." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviMode, "CNVi Configuration", &gPlatformFspPkgTokenSpaceGuid_CnviMode, + Help "This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi." + Combo $gPlatformFspPkgTokenSpaceGuid_CnviWifiCore, "CNVi Wi-Fi Core", &EN_DIS, + Help "Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtCore, "CNVi BT Core", &EN_DIS, + Help "Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtInterface, "CNVi BT Interface", &gPlatformFspPkgTokenSpaceGuid_CnviBtInterface, + Help "This option configures BT device interface to either USB/PCI" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload, "CNVi BT Audio Offload", &EN_DIS, + Help "Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE" + EditNum $gPlatformFspPkgTokenSpaceGuid_CnviWwanCoex, "WWAN Coex", HEX, + Help "WWAN Coex is getting updated from UEFI variable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SkipBtPreInit, "Skip BtPreInit", HEX, + Help "BtPreInit can be skipped if SkipBtPreInit is enabled" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CnviRfResetPinMux, "CNVi RF_RESET pin muxing", HEX, + Help "Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CnviClkreqPinMux, "CNVi CLKREQ pin muxing", HEX, + Help "Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default) or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in GpioPins*.h." + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffloadInterface, "CNVi BT Audio OffOffloadInterfaceload", &EN_DIS, + Help "Enable/Disable BT Audio OffloadInterface, Default is ENABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_Device4Enable, "Enable Device 4", &EN_DIS, + Help "Enable/disable Device 4" + Combo $gPlatformFspPkgTokenSpaceGuid_SkipPamLock, "Skip PAM regsiter lock", &EN_DIS, + Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssLsxOe, "TCSS LSx OE Enable", HEX, + Help "Bits 0, 1, ... max Type C Rettimerless port LSx OE enables" + "Valid range: 0x0 ~ 0x000F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum, "PCH HDA Verb Table Entry Number", HEX, + Help "Number of Entries in Verb Table." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr, "PCH HDA Verb Table Pointer", HEX, + Help "Pointer to Array of pointers to Verb Table." + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaPme, "Enable Pme", &EN_DIS, + Help "Enable Azalia wake-on-ring." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, "HD Audio Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, + Help "HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyMode, "HD Audio Microphone Privacy Mode", &gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyMode, + Help "HD Audio Microphone Privacy Mode: 0: No Microphone Privacy Support; 1: HW Managed Microphone Privacy; 2: FW Managed Microphone Privacy; 3: Force Microphone Mute" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyDeglitch, "HD Audio Microphone Privacy Deglitch", &EN_DIS, + Help "HD Audio Microphone Privacy Deglitch: 0: Disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeSoundWire0, "HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode", &EN_DIS, + Help "HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeSoundWire1, "HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode", &EN_DIS, + Help "HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeSoundWire2, "HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode", &EN_DIS, + Help "HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeSoundWire3, "HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode", &EN_DIS, + Help "HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeSoundWire4, "HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode", &EN_DIS, + Help "HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyHwModeDmic, "HD Audio Microphone Privacy applied for Dmic in HW Mode", &EN_DIS, + Help "HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaMicPrivacyTimeout, "HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before forcing the actual microphone privacy DMA data zeroing.", HEX, + Help "HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before forcing the actual microphone privacy DMA data zeroing." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr, "Pointer to ChipsetInit Binary", HEX, + Help "ChipsetInit Binary Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen, "Length of ChipsetInit Binary", HEX, + Help "ChipsetInit Binary Length." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NphyBinPtr, "Pointer to NPHY Binary", HEX, + Help "Nphy Binary Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NphyBinLen, "Length of NPHY Binary", HEX, + Help "Nphy Binary Length." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinPtr, "Pointer to SYNPS PHY Binary", HEX, + Help "Synps Binary Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinLen, "Length of SYNPS PHY Binary", HEX, + Help "Synps Binary Length." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SiSkipBiosDoneWhenFwUpdate, "Skip setting BIOS_DONE When Fw Update.", &EN_DIS, + Help "When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,skip setting BIOS_DONE MSR at EndofPei. Note: BIOS_DONE MSR should be set in later phase before executing 3rd party code if SiSkipBiosDoneWhenFwUpdate set to TRUE." + Combo $gPlatformFspPkgTokenSpaceGuid_PmcWdtTimerEn, "PMC WDT enable", &EN_DIS, + Help "Enable/disable PMC WDT configuration" +EndPage + +Page "PCH(PostMem)" +EndPage + diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Fsp.fd b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Fsp.fd new file mode 100644 index 00000000..a381101c --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Fsp.fd @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:979e34da0827c3a71155d6a8ddfd8d3948c7d81c43da971ba60cf7895e0d2b92 +size 1613824 diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/FspPkgPcdShare.dsc b/fsp/ptl/4063.02/PantherLakeFspBinPkg/FspPkgPcdShare.dsc new file mode 100644 index 00000000..a50b4ca9 --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/FspPkgPcdShare.dsc @@ -0,0 +1,103 @@ +## @file +# Platform description for DynamicEx PCDs, defined in FSP Package +# and shared with Board Package. +# +# @copyright +# INTEL CONFIDENTIAL +# Copyright (C) 2018 Intel Corporation. +# +# This software and the related documents are Intel copyrighted materials, +# and your use of them is governed by the express license under which they +# were provided to you ("License"). Unless the License provides otherwise, +# you may not use, modify, copy, publish, distribute, disclose or transmit +# this software or the related documents without Intel's prior written +# permission. +# +# This software and the related documents are provided as is, with no +# express or implied warranties, other than those that are expressly stated +# in the License. +# +# @par Specification +## + +[PcdsDynamicExDefault] + + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processorss + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 + + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|0xE0000000 + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + + ## Specifies the base address of the first microcode Patch in the microcode Region. + # @Prompt Microcode Region base address. + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0 + + ## Specifies the size of the microcode Region. + # @Prompt Microcode Region size. + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0 + + ## Specifies the AP wait loop state during POST phase. + # The value is defined as below. + # 1: Place AP in the Hlt-Loop state. + # 2: Place AP in the Mwait-Loop state. + # 3: Place AP in the Run-Loop state. + # @Prompt The AP wait loop state. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 + + ## Specifies the AP target C-state for Mwait during POST phase. + # The default value 0 means C1 state. + # The value is defined as below.

+ # @Prompt The specified AP target C-state for Mwait. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 + + # + # Enable ACPI S3 support in FSP by default + # + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|1 + + ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA. + # @Prompt The pointer to a CPU S3 data buffer. + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x00 + + ## As input, specifies user's desired settings for enabling/disabling processor features. + ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature. + # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings. + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + + ## Contains the size of memory required when CPU processor trace is enabled.

+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.

+ # @Prompt The memory size used for processor trace if processor trace is enabled. + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0 + + ## Contains the processor trace output scheme when CPU processor trace is enabled.

+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.

+ # @Prompt The processor trace output scheme used when processor trace is enabled. + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0 + + ## Indicates processor feature capabilities, each bit corresponding to a specific feature. + # @Prompt Processor feature capabilities. + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + + # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 + + ## This dynamic PCD hold an address to point to private data structure used in DxeS3BootScriptLib library + # instance which records the S3 boot script table start address, length, etc. To introduce this PCD is + # only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the + # default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library. + # @Prompt S3 Boot Script Table Private Data pointer. + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0 + + ## This dynamic PCD hold an address to point to private data structure SMM copy used in DxeS3BootScriptLib library + # instance which records the S3 boot script table start address, length, etc. To introduce this PCD is + # only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the + # default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library. + # @Prompt S3 Boot Script Table Private Smm Data pointer. + # @ValidList 0x80000001 | 0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0 + + ## Indicates if the PCIe Resizable BAR Capability Supported or NOT. + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|FALSE \ No newline at end of file diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FirmwareVersionInfo.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FirmwareVersionInfo.h new file mode 100644 index 00000000..466cb8e7 --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FirmwareVersionInfo.h @@ -0,0 +1,55 @@ +/** @file + Intel Firmware Version Info (FVI) related definitions. + + @todo update document/spec reference + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12 + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" +#define INTEL_FVI_SMBIOS_TYPE 0xDD + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspPerformance.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspPerformance.h new file mode 100644 index 00000000..f26f4338 --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspPerformance.h @@ -0,0 +1,51 @@ +/** @file + Library for Fsp Performance Lib Config file. + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 2024 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification Reference: +**/ + +#ifndef _FSP_PERFORMANCE_H_ +#define _FSP_PERFORMANCE_H_ + +#define FSP_PERFORMANCE_HOB_GUID \ + { 0xaa4d127a, 0x6c1f, 0x4833, {0xa4, 0x6c, 0x07, 0xf2, 0x27, 0x14, 0x71, 0x69} } + +#define STRING_SIZE (10) +typedef struct { + EFI_PHYSICAL_ADDRESS Handle; + CHAR8 Token[STRING_SIZE]; ///< Measured token string name. + CHAR8 Module[STRING_SIZE]; ///< Module string name. + UINT64 StartTimeStamp; ///< Start time point. + UINT64 EndTimeStamp; ///< End time point. +} FSP_PERFORMANCE_HOB; + +// +// Performance Entries currently present +// +// 0. uGOP -> Identifier = FspuGopPerf +// 1. uGOP Exit -> Identifier = FspuGopExitPerf +// +// FspMaxPerf -> Holds the total count of entries +// +typedef enum { + FspuGopPerf, + FspuGopExitPerf, + FspMaxPerf +} FSP_PERFORMANCE; + +#endif // __FSP_PERFORMANCE_H_ diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspProducerDataHeader.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspProducerDataHeader.h new file mode 100644 index 00000000..831fd92a --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspProducerDataHeader.h @@ -0,0 +1,99 @@ +/** @file + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 2023 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification +**/ +#ifndef _FSP_PRODUCER_DATA_HEADER_H_ +#define _FSP_PRODUCER_DATA_HEADER_H_ + +#include + +#define BUILD_TIME_STAMP_SIZE 12 + +// +// FSP Header Data structure from FspHeader driver. +// +#pragma pack(1) +/// +/// FSP Producer Data Subtype - 1 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. + /// + UINT32 RcVersion; + /// + /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". + /// + UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; +} FSP_PRODUCER_DATA_TYPE1; + +/// +/// FSP Producer Data Subtype - 2 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. + /// + UINT8 MrcVersion [4]; +} FSP_PRODUCER_DATA_TYPE2; + + +typedef struct { + FSP_INFO_HEADER FspInfoHeader; + FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; + FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; + FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; + FSP_PATCH_TABLE FspPatchTable; +} FSP_PRODUCER_DATA_TABLES; +#pragma pack() + +#endif // _FSP_PRODUCER_DATA_HEADER_H diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspUpd.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspUpd.h new file mode 100644 index 00000000..bb25a32d --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2026, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C5450 /* 'PTLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5450 /* 'PTLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C5450 /* 'PTLUPD_S' */ + +#pragma pack() + +#endif diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspmUpd.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspmUpd.h new file mode 100644 index 00000000..26b2660c --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspmUpd.h @@ -0,0 +1,4888 @@ +/** @file + +Copyright (c) 2026, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +#pragma pack(1) + + +#include + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + +/// +/// MRC Error Key Value Entry structure maps an MRC error code to an error message string. +/// +/* +// +// MRC Error Key Value Table Entries +// OEM can customize this table to display error messages on VGA display +// The Key is used to look up the error message, and the Value is the message string +// +// Message types: +// - MRC_NO_MEMORY_DETECTED (0xDF7E) - "NO MEMORY DETECTED" +// - MRC_MEM_INIT_DONE_WITH_ERRORS (0xDF55) - "BASIC MEMORY TEST FAILED" +// - 0xFFFF (Fallback) - "MRC FAILED, POST CODE: " + POST code in hex +// Any other MRC failure (SPD processing, PLL lock, calibration, training etc.) +// will use the fallback message with the actual POST code appended. +// +// Maximum message length (excluding null terminator): +// - Exact match messages (specific POST code keys): 80 characters +// - Fallback message (key 0xFFFF): 73 characters (+ "0xXXXX" appended automatically) +// +*/ +typedef struct { + UINT32 Key; ///< MRC POST code (16-bit value, 0xFFFF = fallback key) + CONST CHAR8 *Value; ///< MRC error message string +} FSP_MRC_ERROR_KEY_VALUE_ENTRY; + +/// +/// MRC Error Key Value Table contains array of error code to message mappings. +/// +typedef struct { + UINT32 Count; ///< Number of entries in Entry[] array + UINT32 Size; ///< Total size of table in bytes + FSP_MRC_ERROR_KEY_VALUE_ENTRY Entry[]; ///< Variable length array of key-value pairs +} FSP_MRC_ERROR_KEY_VALUE_TABLE; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0060 - Serial Io Uart Debug Mode + Select SerialIo Uart Controller mode + 1:SerialIoUartPci, 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartDebugMode; + +/** Offset 0x0061 - Serial Io Uart Debug Auto Flow + Enables UART hardware flow control, CTS and RTS lines. + $EN_DIS +**/ + UINT8 SerialIoUartDebugAutoFlow; + +/** Offset 0x0062 +**/ + UINT8 FspmUpdRsvd0[2]; + +/** Offset 0x0064 - SerialIoUartDebugRxPinMux - FSPT + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugRxPinMux; + +/** Offset 0x0068 - SerialIoUartDebugTxPinMux - FSPM + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugTxPinMux; + +/** Offset 0x006C - SerialIoUartDebugRtsPinMux - FSPM + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartDebugRtsPinMux; + +/** Offset 0x0070 - SerialIoUartDebugCtsPinMux - FSPM + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartDebugCtsPinMux; + +/** Offset 0x0074 - SerialIo Uart PowerGating + Select SerialIo Uart Powergating mode + 0:Disabled, 1:Enabled, 2:Auto +**/ + UINT8 SerialIoUartPowerGating; + +/** Offset 0x0075 - DCI Enable + Determine if to enable DCI debug from host + $EN_DIS +**/ + UINT8 DciEn; + +/** Offset 0x0076 - DCI DbC Mode + Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: + Set both USB2/3DBCEN; No Change: Comply with HW value + 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change +**/ + UINT8 DciDbcMode; + +/** Offset 0x0077 - DCI Clock Enable + Enable/Disable DCI clock in lowest power state + $EN_DIS +**/ + UINT8 DciClkEnable; + +/** Offset 0x0078 - Keep Early Trace + Trace is activated by default. When enable, keep early trace data and keep tracing, + may block s0ix.\n + When disabled will abandon trace data and stop tracing which allows enter s0ix\n + \n + noted:enable this option will not enable TraceHub; When probe is connected, keep + early trace will then be configured by tool, this option will not take effect. + $EN_DIS +**/ + UINT8 KeepEarlyTrace; + +/** Offset 0x0079 - Enable/Disable MemoryOverlap check + Enable(Default): Enable MemoryOverlap check, Disable: Disable MemoryOverlap check + $EN_DIS +**/ + UINT8 MemMapOverlapCheckSupport; + +/** Offset 0x007A - Memory Test on Warm Boot + Run Base Memory Test on Warm Boot + 0:Disable, 1:Enable +**/ + UINT8 MemTestOnWarmBoot; + +/** Offset 0x007B - NnFlex Override for PHY RxEqTap0 + Controlled by NnFlexPhyOvrdMask bit[0], 6 bit 2's complement +**/ + UINT8 NnFlexPhyRxEqTap0; + +/** Offset 0x007C - NnFlex Override for PHY RxEqTap1 + Controlled by NnFlexPhyOvrdMask bit[1], 6 bit 2's complement, valid range: [-16..15] +**/ + UINT8 NnFlexPhyRxEqTap1; + +/** Offset 0x007D - NnFlex Override for PHY DqTcoComp + Controlled by NnFlexPhyOvrdMask bit[2], 6 bit 2's complement +**/ + UINT8 NnFlexPhyDqTcoComp; + +/** Offset 0x007E - NnFlex Override for PHY RxCtleR + Controlled by NnFlexPhyOvrdMask bit[3] +**/ + UINT8 NnFlexPhyRxCtleR; + +/** Offset 0x007F - NnFlex Override for PHY RxCtleC + Controlled by NnFlexPhyOvrdMask bit[4] +**/ + UINT8 NnFlexPhyRxCtleC; + +/** Offset 0x0080 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0088 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x008A - NnFlex Override for PHY RxCtleRcmn + Controlled by NnFlexPhyOvrdMask bit[5] +**/ + UINT8 NnFlexPhyRxCtleRcmn; + +/** Offset 0x008B - NnFlex Override for PHY RxCtleEq + Controlled by NnFlexPhyOvrdMask bit[6] +**/ + UINT8 NnFlexPhyRxCtleEq; + +/** Offset 0x008C - NnFlex Override for PHY RxCtleTailCtl + Controlled by NnFlexPhyOvrdMask bit[7] +**/ + UINT8 NnFlexPhyRxCtleTailCtl; + +/** Offset 0x008D - NnFlex Override for LP5 Dfeq + Controlled by NnFlexDramOvrdMask bit[0], MR24 encoding +**/ + UINT8 NnFlexLpddr5Dfeq; + +/** Offset 0x008E - NnFlex Override for LP5 PdDrvStr + Controlled by NnFlexDramOvrdMask bit[1], MR3 encoding +**/ + UINT8 NnFlexLpddr5PdDrvStr; + +/** Offset 0x008F - NnFlex Override for LP5 SocOdt + Controlled by NnFlexDramOvrdMask bit[2], MR17 encoding +**/ + UINT8 NnFlexLpddr5SocOdt; + +/** Offset 0x0090 - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr000; + +/** Offset 0x0098 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr001; + +/** Offset 0x00A0 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr010; + +/** Offset 0x00A8 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr011; + +/** Offset 0x00B0 - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr020; + +/** Offset 0x00B8 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr021; + +/** Offset 0x00C0 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr030; + +/** Offset 0x00C8 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr031; + +/** Offset 0x00D0 - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr100; + +/** Offset 0x00D8 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr101; + +/** Offset 0x00E0 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr110; + +/** Offset 0x00E8 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr111; + +/** Offset 0x00F0 - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr120; + +/** Offset 0x00F8 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr121; + +/** Offset 0x0100 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr130; + +/** Offset 0x0108 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr131; + +/** Offset 0x0110 - RcompResistor settings + Indicates RcompResistor settings: Board-dependent +**/ + UINT16 RcompResistor; + +/** Offset 0x0112 - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x011C - Dqs Map CPU to DRAM MC 0 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch0[2]; + +/** Offset 0x011E - Dqs Map CPU to DRAM MC 0 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch1[2]; + +/** Offset 0x0120 - Dqs Map CPU to DRAM MC 0 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch2[2]; + +/** Offset 0x0122 - Dqs Map CPU to DRAM MC 0 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch3[2]; + +/** Offset 0x0124 - Dqs Map CPU to DRAM MC 1 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch0[2]; + +/** Offset 0x0126 - Dqs Map CPU to DRAM MC 1 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch1[2]; + +/** Offset 0x0128 - Dqs Map CPU to DRAM MC 1 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch2[2]; + +/** Offset 0x012A - Dqs Map CPU to DRAM MC 1 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch3[2]; + +/** Offset 0x012C - Dq Map CPU to DRAM MC 0 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch0[16]; + +/** Offset 0x013C - Dq Map CPU to DRAM MC 0 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch1[16]; + +/** Offset 0x014C - Dq Map CPU to DRAM MC 0 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch2[16]; + +/** Offset 0x015C - Dq Map CPU to DRAM MC 0 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch3[16]; + +/** Offset 0x016C - Dq Map CPU to DRAM MC 1 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch0[16]; + +/** Offset 0x017C - Dq Map CPU to DRAM MC 1 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch1[16]; + +/** Offset 0x018C - Dq Map CPU to DRAM MC 1 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch2[16]; + +/** Offset 0x019C - Dq Map CPU to DRAM MC 1 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch3[16]; + +/** Offset 0x01AC - LowerBasicMemTestSize + Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, + shorter BasicMemTest (faster boot) + $EN_DIS +**/ + UINT8 LowerBasicMemTestSize; + +/** Offset 0x01AD - EccGranularity32BEn + Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, + shorter BasicMemTest (faster boot) + $EN_DIS +**/ + UINT8 EccGranularity32BEn; + +/** Offset 0x01AE - EccCorrectionMode + Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled, + shorter BasicMemTest (faster boot) + $EN_DIS +**/ + UINT8 EccCorrectionMode; + +/** Offset 0x01AF - CaVrefHigh + DDR5 CA Sweep High Vref Value for DDR5 OC +**/ + UINT8 CaVrefHigh; + +/** Offset 0x01B0 - CaVrefLow + DDR5 CA Sweep Low Vref Value for DDR5 OC +**/ + UINT8 CaVrefLow; + +/** Offset 0x01B1 - CsVrefHigh + DDR5 CS Sweep High Vref Value for DDR5 OC +**/ + UINT8 CsVrefHigh; + +/** Offset 0x01B2 - CsVrefLow + DDR5 CS Sweep Low Vref Value for DDR5 OC +**/ + UINT8 CsVrefLow; + +/** Offset 0x01B3 - DIMM DFE Tap1 Step Size + DIMM DFE Tap1 Step Size for DDR5 OC +**/ + UINT8 DFETap1StepSize; + +/** Offset 0x01B4 - DIMM DFE Tap2 Step Size + DIMM DFE Tap2 Step Size for DDR5 OC +**/ + UINT8 DFETap2StepSize; + +/** Offset 0x01B5 - IbeccEccInjControl + IBECC Error Injection Control + 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable + Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject + Uncorrectable Error on insertion counter +**/ + UINT8 IbeccEccInjControl; + +/** Offset 0x01B6 - VDD2 override + VDD2 override for DDR5 OC; 0 - Auto +**/ + UINT16 Vdd2Mv; + +/** Offset 0x01B8 - tRAS + RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRAS; + +/** Offset 0x01BA - tRCD/tRP + RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT16 tRCDtRP; + +/** Offset 0x01BC - tREFI + Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT32 tREFI; + +/** Offset 0x01C0 - tCL + CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tCL; + +/** Offset 0x01C2 - tCWL + Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tCWL; + +/** Offset 0x01C4 - tFAW + Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tFAW; + +/** Offset 0x01C6 - tRFC + Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC; + +/** Offset 0x01C8 - tRRD + Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRRD; + +/** Offset 0x01CA - tRTP + Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT16 tRTP; + +/** Offset 0x01CC - tWR + Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, + 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). + 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, + 34:34, 40:40 +**/ + UINT16 tWR; + +/** Offset 0x01CE - tWTR + Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tWTR; + +/** Offset 0x01D0 - tWTR_S + tWTR_S value for OC Custom Profile, 0 - Auto +**/ + UINT16 tWTR_S; + +/** Offset 0x01D2 - tWTR_L + tWTR_L value for OC Custom Profile, 0 - Auto +**/ + UINT16 tWTR_L; + +/** Offset 0x01D4 - tCCD_L + tCCD_L value for OC Custom Profile, 0 - Auto +**/ + UINT16 tCCD_L; + +/** Offset 0x01D6 - tRRD_S + tRRD_S value for OC Custom Profile, 0 - Auto +**/ + UINT16 tRRD_S; + +/** Offset 0x01D8 - tRRD_L + tRRD_L value for OC Custom Profile, 0 - Auto +**/ + UINT16 tRRD_L; + +/** Offset 0x01DA - tRFC4 + tRFC4 value for OC Custom Profile, 0 - Auto +**/ + UINT16 tRFC4; + +/** Offset 0x01DC - tRFC2 + tRFC2 value for OC Custom Profile, 0 - Auto +**/ + UINT16 tRFC2; + +/** Offset 0x01DE - tRFCpb + tRFCpb value for OC Custom Profile, 0 - Auto +**/ + UINT16 tRFCpb; + +/** Offset 0x01E0 - tCCD_L_WR + Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same + bank groups, for OC Custom Profile, 0 - Auto +**/ + UINT16 tCCD_L_WR; + +/** Offset 0x01E2 - Periodic COMP + Enable/disable Periodic Compensation + $EN_DIS +**/ + UINT8 EnPeriodicComp; + +/** Offset 0x01E3 - LPMode4 Support + LPMode4 Options + 0: Disable, 1:Enable, 2:Dynamic Threshold 2, 3:Dynamic Threshold 3 +**/ + UINT8 LpMode4; + +/** Offset 0x01E4 - LPMode Support + Bit[0]: Enable Lpmode0p5 (Idle_enable), Bit[1]: Enable Lpmode2 (Powerdown_enable), + Bit[2]: Enable Lpmode3 (Selfrefresh_enable) +**/ + UINT8 LpMode; + +/** Offset 0x01E5 - Opportunistic Read + Enables/Disable Opportunistic Read (Def= Enable) + $EN_DIS +**/ + UINT8 OpportunisticRead; + +/** Offset 0x01E6 - Cycle Bypass Support + Enables/Disable Cycle Bypass Support(Def=Disable) + $EN_DIS +**/ + UINT8 Disable2CycleBypass; + +/** Offset 0x01E7 - MRC OCSafeMode + OverClocking Safe Mode for tCL + $EN_DIS +**/ + UINT8 OCSafeMode; + +/** Offset 0x01E8 - DQ Vref Ctrl Offset + Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch0VrefCtl + 0xF4:-12,0xF5:-11, 0xF6:-10, 0xF7:-9, 0xF8:-8, 0xF9:-7, 0xFA:-6, 0xFB:-5, 0xFC:-4, + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, 5:+5, 6:+6, 7:+7, 8:+8, + 9:+9, 10:+10, 11:+11, 12:+12 +**/ + UINT8 VrefCtlOffset; + +/** Offset 0x01E9 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x01EA - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x01EB - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x01EC - Rank Margin Tool per Task + This option enables the user to execute Rank Margin Tool per major training step + in the MRC. + $EN_DIS +**/ + UINT8 RmtPerTask; + +/** Offset 0x01ED - Training Trace + This option enables the trained state tracing feature in MRC. This feature will + print out the key training parameters state across major training steps. + $EN_DIS +**/ + UINT8 TrainTrace; + +/** Offset 0x01EE - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. + This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x01EF - IbeccEccInjCount + Number of memory transactions between ECC error injection +**/ + UINT8 IbeccEccInjCount; + +/** Offset 0x01F0 - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x01F2 - SAGV + System Agent dynamic frequency support. + 0:Disabled, 1:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x01F3 - SAGV WP Mask + System Agent dynamic frequency workpoints that memory will be training at the enabled + frequencies. + 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3 +**/ + UINT8 SaGvWpMask; + +/** Offset 0x01F4 - SAGV Gear Ratio + Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 SaGvGear[4]; + +/** Offset 0x01F8 - SAGV Frequency + SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. +**/ + UINT16 SaGvFreq[4]; + +/** Offset 0x0200 - SAGV Disabled Gear Ratio + Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 GearRatio; + +/** Offset 0x0201 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x0202 - Controller 0 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc0Ch0; + +/** Offset 0x0203 - Controller 0 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc0Ch1; + +/** Offset 0x0204 - Controller 0 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc0Ch2; + +/** Offset 0x0205 - Controller 0 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc0Ch3; + +/** Offset 0x0206 - Controller 1 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc1Ch0; + +/** Offset 0x0207 - Controller 1 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc1Ch1; + +/** Offset 0x0208 - Controller 1 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc1Ch2; + +/** Offset 0x0209 - Controller 1 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc1Ch3; + +/** Offset 0x020A - Scrambler Support + This option enables data scrambling in memory. + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x020B - Memory Slice Hash Override + Memory Slice (Controller) Hash Mask and LSB Override. 0 = Use default memory slice + hash mask / lsb, 1 = Use values from MsHashMask and MsHashInterleaveBit + $EN_DIS +**/ + UINT8 MsHashOverride; + +/** Offset 0x020C - Memory Voltage + DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM + chips) in millivolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. + 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 + Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts +**/ + UINT16 VddVoltage; + +/** Offset 0x020E - Memory Ratio + Automatic or the frequency will equal ratio times reference clock. Set to Auto to + recalculate memory timings listed below. + 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT16 Ratio; + +/** Offset 0x0210 - SPD Profile Selected + Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP + Profile 1, 3=XMP Profile 2 + 0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2 +**/ + UINT8 SpdProfileSelected; + +/** Offset 0x0211 - RxVref Per-Bit Training + Enable/Disable RxVref Per-Bit Training + $EN_DIS +**/ + UINT8 RXVREFPERBIT; + +/** Offset 0x0212 - TXDQS DCC Training + Enables/Disable TXDQS DCC Training + $EN_DIS +**/ + UINT8 TXDQSDCC; + +/** Offset 0x0213 - Rx DQS Duty Cycle Correction + Enables/Disable Rx DQS Duty Cycle Correction + $EN_DIS +**/ + UINT8 RXDQSDCC; + +/** Offset 0x0214 - Ch Hash Override + Select if Channel Hash setting values will be taken from input parameters or automatically + taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashOverride; + +/** Offset 0x0215 - Voltage Readout + Enables/Disable Voltage Readout for VCCClk and PBias + $EN_DIS +**/ + UINT8 VoltageReadout; + +/** Offset 0x0216 - DQS Rise/Fall + Enables/Disable DQS Rise/Fall + $EN_DIS +**/ + UINT8 DQSRF; + +/** Offset 0x0217 - DQS Rise/Fall + Enables/Disable DQS Rise/Fall + $EN_DIS +**/ + UINT8 RDDQSODTT; + +/** Offset 0x0218 - PreTraining + Enables/Disable PreTraining + $EN_DIS +**/ + UINT8 PRETRAIN; + +/** Offset 0x0219 - DUNIT Configuration + Enables/Disable Dunit Configuration + $EN_DIS +**/ + UINT8 DUNITC; + +/** Offset 0x021A - Functional Duty Cycle Correction for DDR5 CLK + Enable/Disable Functional Duty Cycle Correction for DDR5 CLK + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCCLK; + +/** Offset 0x021B - Functional Duty Cycle Correction for DDR5 DQS + Enable/Disable Functional Duty Cycle Correction for DDR5 DQS + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCDQS; + +/** Offset 0x021C +**/ + UINT8 FUNCDCCWCK; + +/** Offset 0x021D - Duty Cycle Correction for LP5 DCA + Enable/Disable Duty Cycle Correction for LP5 DCA + $EN_DIS +**/ + UINT8 DCCLP5WCKDCA; + +/** Offset 0x021E - DQ/DQS Swizzle Training + Enable/Disable DQ/DQS Swizzle Training + $EN_DIS +**/ + UINT8 DQDQSSWZ; + +/** Offset 0x021F - LP5 Dca Training + Enable/Disable LP5 Dca Training + $EN_DIS +**/ + UINT8 DCCLP5READDCA; + +/** Offset 0x0220 - Functional Duty Cycle Correction for Data DQ + Enable/Disable Functional Duty Cycle Correction for Data DQ + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCDQ; + +/** Offset 0x0221 - SubCh Hash Override + Select if SubChannel Hash setting values will be taken from input parameters or + automatically taken from POR values depending on DRAM type detected. NOTE: ONLY + if Memory interleaved Mode + $EN_DIS +**/ + UINT8 SubChHashOverride; + +/** Offset 0x0222 - DDR5 Auto Precharge Enable + Auto Precharge Enable for DDR5: O=Auto, 1=Disable, 2=Enable + $EN_DIS +**/ + UINT8 Ddr5AutoPrechargeEnable; + +/** Offset 0x0223 - Lp5 SplitACT Enable + SplitACT enable for LP5 + 0:Auto, 1:Disable, 2:Enable +**/ + UINT8 Lp5SplitACTEnable; + +/** Offset 0x0224 - CCC Half Frequency + CCC Half Frequency (CccGear4) Mode: 0 = Auto (Default), 1 = Disable, 2 = GroupGv0 + (SaGv0 only), 3 = GroupGv1 (Up to SaGv1), 4 = GroupGv2 (Up to SaGv2), 5 = GroupGv3 + (Up to SaGv3) + 0: Auto, 1: Disable, 2: GroupGv0, 3: GroupGv1, 4: GroupGv2, 5: GroupGv3 +**/ + UINT8 CccHalfFrequency; + +/** Offset 0x0225 - DIMM Non-Target ODT Training + Enables/Disable DIMM Non-Target ODT Training + $EN_DIS +**/ + UINT8 DIMMNTODT; + +/** Offset 0x0226 - Unmatched Rx Calibration + Enable/Disable Rx Unmatched Calibration + $EN_DIS +**/ + UINT8 RXUNMATCHEDCAL; + +/** Offset 0x0227 - Hard Post Package Repair + Deprecated + $EN_DIS +**/ + UINT8 PPR; + +/** Offset 0x0228 - PPR Test Type + Deprecated +**/ + UINT8 PprTestType; + +/** Offset 0x0229 - PPR Run Once + When Eanble, PPR will run only once and then is disabled at next training cycle + $EN_DIS +**/ + UINT8 PprRunOnce; + +/** Offset 0x022A - PPR Run During Fastboot + Deprecated + $EN_DIS +**/ + UINT8 PprRunAtFastboot; + +/** Offset 0x022B - PPR Repair Type + PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair + 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair +**/ + UINT8 PprRepairType; + +/** Offset 0x022C - PPR Error Injection + When Eanble, PPR will inject bad rows during testing + $EN_DIS +**/ + UINT8 PprErrorInjection; + +/** Offset 0x022D - PPR Repair Controller + Deprecated +**/ + UINT8 PprRepairController; + +/** Offset 0x022E - PPR Repair Channel + Deprecated +**/ + UINT8 PprRepairChannel; + +/** Offset 0x022F - PPR Repair Dimm + Deprecated +**/ + UINT8 PprRepairDimm; + +/** Offset 0x0230 - PPR Repair Rank + Deprecated +**/ + UINT8 PprRepairRank; + +/** Offset 0x0231 - Memory Slice Hash LSB Bit + Memory Slice (Controller) Hash LSB bit. Valid values are 0..7 for BITS 6..13; used + when MsHashOverride is set + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 MsHashInterleaveBit; + +/** Offset 0x0232 - Memory Slice Hash Mask + Memory Slice (Controller) Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] + set(Maximum); used when MsHashOverride is set +**/ + UINT16 MsHashMask; + +/** Offset 0x0234 - PPR Repair Row + Deprecated +**/ + UINT32 PprRepairRow; + +/** Offset 0x0238 - PPR Repair Physical Address Low + Deprecated +**/ + UINT32 PprRepairPhysicalAddrLow; + +/** Offset 0x023C - PPR Repair Physical Address High + Deprecated +**/ + UINT32 PprRepairPhysicalAddrHigh; + +/** Offset 0x0240 - PPR Repair BankGroup + Deprecated +**/ + UINT8 PprRepairBankGroup; + +/** Offset 0x0241 - LVR Auto Trim + Enable/disable LVR Auto Trim + $EN_DIS +**/ + UINT8 LVRAUTOTRIM; + +/** Offset 0x0242 - Compensation Optimization + Enable/Disable Compensation Optimization + $EN_DIS +**/ + UINT8 OPTIMIZECOMP; + +/** Offset 0x0243 - Write DQ/DQS Retraining + Enable/Disable Write DQ/DQS Retraining + $EN_DIS +**/ + UINT8 WRTRETRAIN; + +/** Offset 0x0244 - DCC Phase Clk Calibration + Enable/disable DCC Phase Clk Calibration + $EN_DIS +**/ + UINT8 PHASECLKCAL; + +/** Offset 0x0245 - DCC Tline Clk Calibration + Enable/disable DCC Tline Clk Calibration + $EN_DIS +**/ + UINT8 TLINECLKCAL; + +/** Offset 0x0246 - DCC Tline Serializer Calibration + Enable/disable DCC PI Serializer Calibratio + $EN_DIS +**/ + UINT8 DCCPISERIALCAL; + +/** Offset 0x0247 - RDDQODTT + Enable/disable Read DQ ODT Training + $EN_DIS +**/ + UINT8 RDDQODTT; + +/** Offset 0x0248 - RDCTLET + Enable/disable Read CTLE Training + $EN_DIS +**/ + UINT8 RDCTLET; + +/** Offset 0x0249 - RxVref Pre EMPHASIS Training + Enable/Disable Pre EMPHASIS Training + $EN_DIS +**/ + UINT8 EMPHASIS; + +/** Offset 0x024A - RX DQS VOC Centring Training + Enable/Disable RX DQS VOC Centring Training + $EN_DIS +**/ + UINT8 RXDQSVOCC; + +/** Offset 0x024B - NMode + System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N +**/ + UINT8 NModeSupport; + +/** Offset 0x024C - LPDDR ODT RttWr + Initial RttWr for LP4/5 in Ohms. 0x0 - Auto +**/ + UINT8 LpddrRttWr; + +/** Offset 0x024D - Retrain on Fast flow Failure + Restart MRC in Cold mode if SW MemTest fails during Fast flow. + $EN_DIS +**/ + UINT8 RetrainOnFastFail; + +/** Offset 0x024E - LPDDR ODT RttCa + Initial RttCa for LP4/5 in Ohms. 0x0 - Auto +**/ + UINT8 LpddrRttCa; + +/** Offset 0x024F - DIMM DFE Training + Enable/Disable DIMM DFE Training + $EN_DIS +**/ + UINT8 WRTDIMMDFE; + +/** Offset 0x0250 - DDR5 ODT Timing Config + Enable/Disable DDR5 ODT TIMING CONFIG + $EN_DIS +**/ + UINT8 DDR5ODTTIMING; + +/** Offset 0x0251 - HobBufferSize + Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB + total HOB size). + 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value +**/ + UINT8 HobBufferSize; + +/** Offset 0x0252 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x0253 - SenseAmp Offset Training + Enables/Disable SenseAmp Offset Training + $EN_DIS +**/ + UINT8 SOT; + +/** Offset 0x0254 - Early ReadMPR Timing Centering 2D + Enables/Disable Early ReadMPR Timing Centering 2D + $EN_DIS +**/ + UINT8 ERDMPRTC2D; + +/** Offset 0x0255 - Read MPR Training + Enables/Disable Read MPR Training + $EN_DIS +**/ + UINT8 RDMPRT; + +/** Offset 0x0256 - Receive Enable Training + Enables/Disable Receive Enable Training + $EN_DIS +**/ + UINT8 RCVET; + +/** Offset 0x0257 - Jedec Write Leveling + Enables/Disable Jedec Write Leveling + $EN_DIS +**/ + UINT8 JWRL; + +/** Offset 0x0258 - Early Write Time Centering 2D + Enables/Disable Early Write Time Centering 2D + $EN_DIS +**/ + UINT8 EWRTC2D; + +/** Offset 0x0259 - Early Read Time Centering 2D + Enables/Disable Early Read Time Centering 2D + $EN_DIS +**/ + UINT8 ERDTC2D; + +/** Offset 0x025A - Unmatched Write Time Centering 1D + Enable/Disable Unmatched Write Time Centering 1D + $EN_DIS +**/ + UINT8 UNMATCHEDWRTC1D; + +/** Offset 0x025B - Write Timing Centering 1D + Enables/Disable Write Timing Centering 1D + $EN_DIS +**/ + UINT8 WRTC1D; + +/** Offset 0x025C - Write Voltage Centering 1D + Enables/Disable Write Voltage Centering 1D + $EN_DIS +**/ + UINT8 WRVC1D; + +/** Offset 0x025D - Read Timing Centering 1D + Enables/Disable Read Timing Centering 1D + $EN_DIS +**/ + UINT8 RDTC1D; + +/** Offset 0x025E - Dimm ODT Training + Enables/Disable Dimm ODT Training + $EN_DIS +**/ + UINT8 DIMMODTT; + +/** Offset 0x025F - DIMM RON Training + Enables/Disable DIMM RON Training + $EN_DIS +**/ + UINT8 DIMMRONT; + +/** Offset 0x0260 - Write Drive Strength Training + Enables/Disable Write Drive Strength Training + $EN_DIS +**/ + UINT8 WRDSEQT; + +/** Offset 0x0261 - Read Equalization Training + Enables/Disable Read Equalization Training + $EN_DIS +**/ + UINT8 RDEQT; + +/** Offset 0x0262 - Write Timing Centering 2D + Enables/Disable Write Timing Centering 2D + $EN_DIS +**/ + UINT8 WRTC2D; + +/** Offset 0x0263 - Read Timing Centering 2D + Enables/Disable Read Timing Centering 2D + $EN_DIS +**/ + UINT8 RDTC2D; + +/** Offset 0x0264 - Write Voltage Centering 2D + Enables/Disable Write Voltage Centering 2D + $EN_DIS +**/ + UINT8 WRVC2D; + +/** Offset 0x0265 - Read Voltage Centering 2D + Enables/Disable Read Voltage Centering 2D + $EN_DIS +**/ + UINT8 RDVC2D; + +/** Offset 0x0266 - Command Voltage Centering + Enables/Disable Command Voltage Centering + $EN_DIS +**/ + UINT8 CMDVC; + +/** Offset 0x0267 - Late Command Training + Enables/Disable Late Command Training + $EN_DIS +**/ + UINT8 LCT; + +/** Offset 0x0268 - Round Trip Latency Training + Enables/Disable Round Trip Latency Training + $EN_DIS +**/ + UINT8 RTL; + +/** Offset 0x0269 - Turn Around Timing Training + Enables/Disable Turn Around Timing Training + $EN_DIS +**/ + UINT8 TAT; + +/** Offset 0x026A - Rmt Even Odd + Enables/Disable Rmt Even Odd + $EN_DIS +**/ + UINT8 RMTEVENODD; + +/** Offset 0x026B - DIMM SPD Alias Test + Enables/Disable DIMM SPD Alias Test + $EN_DIS +**/ + UINT8 ALIASCHK; + +/** Offset 0x026C - Receive Enable Centering 1D + Enables/Disable Receive Enable Centering 1D + $EN_DIS +**/ + UINT8 RCVENC1D; + +/** Offset 0x026D - Retrain Margin Check + Enables/Disable Retrain Margin Check + $EN_DIS +**/ + UINT8 RMC; + +/** Offset 0x026E - ECC Support + Enables/Disable ECC Support + $EN_DIS +**/ + UINT8 EccSupport; + +/** Offset 0x026F - DLL DCC Calibration + Enables/Disable DLL DCC Calibration + $EN_DIS +**/ + UINT8 DLLDCC; + +/** Offset 0x0270 - DLL BW Select Calibration + Enables/Disable DLL BW Select Calibration + $EN_DIS +**/ + UINT8 DLLBWSEL; + +/** Offset 0x0271 - Ibecc + In-Band ECC Support + $EN_DIS +**/ + UINT8 Ibecc; + +/** Offset 0x0272 - IbeccParity + In-Band ECC Parity Control + $EN_DIS +**/ + UINT8 IbeccParity; + +/** Offset 0x0273 - MsHashEnable + Controller Hash Enable: 0=Disable, 1=Enable + $EN_DIS +**/ + UINT8 MsHashEnable; + +/** Offset 0x0274 - IbeccOperationMode + In-Band ECC Operation Mode + 0:Protect base on address range, 1: Non-protected, 2: All protected +**/ + UINT8 IbeccOperationMode; + +/** Offset 0x0275 - IbeccProtectedRegionEnable + In-Band ECC Protected Region Enable + $EN_DIS +**/ + UINT8 IbeccProtectedRegionEnable[8]; + +/** Offset 0x027D - NnFlex Override for LP5 PreEmpDn + Controlled by NnFlexDramOvrdMask bit[3], MR58 encoding +**/ + UINT8 NnFlexLpddr5PreEmpDn; + +/** Offset 0x027E - IbeccProtectedRegionBases + IBECC Protected Region Bases per IBECC instance +**/ + UINT16 IbeccProtectedRegionBase[8]; + +/** Offset 0x028E - IbeccProtectedRegionMasks + IBECC Protected Region Masks +**/ + UINT16 IbeccProtectedRegionMask[8]; + +/** Offset 0x029E - Memory Remap + Enables/Disable Memory Remap + $EN_DIS +**/ + UINT8 RemapEnable; + +/** Offset 0x029F - Rank Interleave support + Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at + the same time. + $EN_DIS +**/ + UINT8 RankInterleave; + +/** Offset 0x02A0 - Enhanced Interleave support + Enables/Disable Enhanced Interleave support + $EN_DIS +**/ + UINT8 EnhancedInterleave; + +/** Offset 0x02A1 - Ch Hash Support + Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashEnable; + +/** Offset 0x02A2 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDn; + +/** Offset 0x02A3 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDnLpddr; + +/** Offset 0x02A4 - SelfRefresh Enable + Enables/Disable SelfRefresh Enable + $EN_DIS +**/ + UINT8 SrefCfgEna; + +/** Offset 0x02A5 - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeatLpddr; + +/** Offset 0x02A6 - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeat; + +/** Offset 0x02A7 - Exit On Failure (MRC) + Enables/Disable Exit On Failure (MRC) + $EN_DIS +**/ + UINT8 ExitOnFailure; + +/** Offset 0x02A8 - Wck Pad DCC Calibration + Enable/disable Wck Pad DCC Calibration + $EN_DIS +**/ + UINT8 WCKPADDCCCAL; + +/** Offset 0x02A9 - DCC PI Code LUT Calibration + Enable/Disable DCC PI Code LUT Calibration + $EN_DIS +**/ + UINT8 DCCPICODELUT; + +/** Offset 0x02AA - Read Voltage Centering 1D + Enable/Disable Read Voltage Centering 1D + $EN_DIS +**/ + UINT8 RDVC1D; + +/** Offset 0x02AB - TxDqTCO Comp Training + Enable/Disable TxDqTCO Comp Training + $EN_DIS +**/ + UINT8 TXTCO; + +/** Offset 0x02AC - ClkTCO Comp Training + Enable/Disable ClkTCO Comp Training + $EN_DIS +**/ + UINT8 CLKTCO; + +/** Offset 0x02AD - CMD Slew Rate Training + Enable/Disable CMD Slew Rate Training + $EN_DIS +**/ + UINT8 CMDSR; + +/** Offset 0x02AE - CMD Drive Strength and Tx Equalization + Enable/Disable CMD Drive Strength and Tx Equalization + $EN_DIS +**/ + UINT8 CMDDSEQ; + +/** Offset 0x02AF - DIMM CA ODT Training + Enable/Disable DIMM CA ODT Training + $EN_DIS +**/ + UINT8 DIMMODTCA; + +/** Offset 0x02B0 - Read Vref Decap Training* + Enable/Disable Read Vref Decap Training* + $EN_DIS +**/ + UINT8 RDVREFDC; + +/** Offset 0x02B1 - Rank Margin Tool Per Bit + Enable/Disable Rank Margin Tool Per Bit + $EN_DIS +**/ + UINT8 RMTBIT; + +/** Offset 0x02B2 - Ref PI Calibration + Enable/Disable Ref PI Calibration + $EN_DIS +**/ + UINT8 REFPI; + +/** Offset 0x02B3 - VccClk FF Offset Correction + Enable/Disable VccClk FF Offset Correction + 0:Disable, 1:Enable +**/ + UINT8 VCCCLKFF; + +/** Offset 0x02B4 - Data PI Linearity Calibration + Enable/Disable {Data PI Linearity Calibration + $EN_DIS +**/ + UINT8 DATAPILIN; + +/** Offset 0x02B5 - Ddr5 Rx Cross-Talk Cancellation + Enable/Disable {Ddr5 Rx Cross-Talk Cancellation + $EN_DIS +**/ + UINT8 DDR5XTALK; + +/** Offset 0x02B6 - Retrain On Working Channel + Enables/Disable Retrain On Working Channel feature + $EN_DIS +**/ + UINT8 RetrainToWorkingChannel; + +/** Offset 0x02B7 - Row Press + Enables/Disable Row Press feature + $EN_DIS +**/ + UINT8 RowPressEn; + +/** Offset 0x02B8 - DBI feature + Enables/Disable DBI feature + $EN_DIS +**/ + UINT8 DBI; + +/** Offset 0x02B9 - DDR5 MR7 WICA support + Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment + $EN_DIS +**/ + UINT8 IsDdr5MR7WicaSupported; + +/** Offset 0x02BA - Ch Hash Interleaved Bit + Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave + the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 ChHashInterleaveBit; + +/** Offset 0x02BB - Write Equalization Training + Enables/Disables Write Equalization Training + $EN_DIS +**/ + UINT8 WREQT; + +/** Offset 0x02BC - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x02BE - CccPinsInterleaved + Interleaving mode of CCC pins which depends on board routing: 0=Disable, 1=Enable +**/ + UINT8 CccPinsInterleaved; + +/** Offset 0x02BF - Throttler CKEMin Timer + Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). + Dfault is 0x00 +**/ + UINT8 ThrtCkeMinTmr; + +/** Offset 0x02C0 - Allow Opp Ref Below Write Threhold + Allow opportunistic refreshes while we don't exit power down. + $EN_DIS +**/ + UINT8 AllowOppRefBelowWriteThrehold; + +/** Offset 0x02C1 - Write Threshold + Number of writes that can be accumulated while CKE is low before CKE is asserted. +**/ + UINT8 WriteThreshold; + +/** Offset 0x02C2 - MC_REFRESH_RATE + Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh + 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh +**/ + UINT8 McRefreshRate; + +/** Offset 0x02C3 - Refresh Watermarks + Refresh Watermarks: 0-Low, 1-High (default) + 0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default) +**/ + UINT8 RefreshWm; + +/** Offset 0x02C4 - User Manual Threshold + Disabled: Predefined threshold will be used.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserThresholdEnable; + +/** Offset 0x02C5 - User Manual Budget + Disabled: Configuration of memories will defined the Budget value.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserBudgetEnable; + +/** Offset 0x02C6 - Power Down Mode + This option controls command bus tristating during idle periods + 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto +**/ + UINT8 PowerDownMode; + +/** Offset 0x02C7 - Pwr Down Idle Timer + The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means + AUTO: 64 for ULX/ULT, 128 for DT/Halo +**/ + UINT8 PwdwnIdleCounter; + +/** Offset 0x02C8 - Page Close Idle Timeout + This option controls Page Close Idle Timeout + 0:Enabled, 1:Disabled +**/ + UINT8 DisPgCloseIdleTimeout; + +/** Offset 0x02C9 - Bitmask of ranks that have CA bus terminated + LPDDR5: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is + terminating and Rank1 is non-terminating +**/ + UINT8 CmdRanksTerminated; + +/** Offset 0x02CA - MRC Safe Mode Override + SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode + override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3] + Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4] + Enable SaGv safe mode override +**/ + UINT8 SafeModeOverride; + +/** Offset 0x02CB - NnFlex Override for LP5 PreEmpUp + Controlled by NnFlexDramOvrdMask bit[4], MR58 encoding +**/ + UINT8 NnFlexLpddr5PreEmpUp; + +/** Offset 0x02CC - IbeccEccInjAddrBase + Address to match against for ECC error injection. Example: 1 = 32MB, 2 = 64MB +**/ + UINT32 IbeccEccInjAddrBase; + +/** Offset 0x02D0 - DDR Phy Safe Mode Support + DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]: + Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]: + PLL Operation, DdrSafeMode[6]: Safe ODT +**/ + UINT32 DdrSafeMode; + +/** Offset 0x02D4 - Mc Safe Mode Support + McSafeMode[0]: Reserved, McSafeMode[1]: OppSR +**/ + UINT8 McSafeMode; + +/** Offset 0x02D5 - Ask MRC to clear memory content + Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. + $EN_DIS +**/ + UINT8 CleanMemory; + +/** Offset 0x02D6 - Tseg Retry Count + Tseg Retry count will increase based on TSEG Region Fail count + 0: Default, 1:3 +**/ + UINT8 RetryCount; + +/** Offset 0x02D7 - Mrc Ppr Status + Get Mrc PPR Status after PPR Recovery flow will get Trigger + 0: PASS, 1: FAIL(Default) +**/ + UINT8 MrcPprStatus; + +/** Offset 0x02D8 - Tseg Memory Test Status + If enabled, PPR Recovery flow will get Trigger + 0: PASS, 1: FAIL(Default) +**/ + UINT8 TsegMemoryTestStatus; + +/** Offset 0x02D9 - Ppr Recovery Status Enable + 0: Disabled(Default), 1: Enabled. If enabled, PPR Recovery flow will get Trigger. + $EN_DIS +**/ + UINT8 PprRecoveryStatusEnable; + +/** Offset 0x02DA - Safe Loading Bios Enable State + 0: Disabled(Default), 1: Enabled. If enabled, Memory diagnostic will perform for + TSEG Region. + $EN_DIS +**/ + UINT8 SafeLoadingBiosEnableState; + +/** Offset 0x02DB - BDAT test type + When BdatEnable is set to TRUE, this option selects the type of data which will + be populated in the BIOS Data ACPI Tables: 0=RMT, 1=RMT Per Bit, 2=Margin 2D. + 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D +**/ + UINT8 MrcBdatTestType; + +/** Offset 0x02DC - MrcBdatEnable + 0: Disabled(Default), 1: Enabled. This field enables the generation of the BIOS + DATA ACPI Tables: 0=FALSE, 1=TRUE. + $EN_DIS +**/ + UINT8 MrcBdatEnable; + +/** Offset 0x02DD - DisableMrcRetraining + 0: Disabled(Default), 1: Enabled. Enable/Disable DisableMrcRetraining + $EN_DIS +**/ + UINT8 DisableMrcRetraining; + +/** Offset 0x02DE - RMTLoopCount + Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO +**/ + UINT8 RMTLoopCount; + +/** Offset 0x02DF - DdrOneDpc + DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, + or on both (default) + 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled +**/ + UINT8 DdrOneDpc; + +/** Offset 0x02E0 - Vddq Voltage Override + # is multiple of 1mV where 0 means Auto. +**/ + UINT16 VddqVoltageOverride; + +/** Offset 0x02E2 - VccIog Voltage Override + # is multiple of 1mV where 0 means Auto. +**/ + UINT16 VccIogVoltageOverride; + +/** Offset 0x02E4 - VccClk Voltage Override + # is multiple of 1mV where 0 means Auto. +**/ + UINT16 VccClkVoltageOverride; + +/** Offset 0x02E6 - ThrtCkeMinTmrLpddr + Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, 0x00=Default +**/ + UINT8 ThrtCkeMinTmrLpddr; + +/** Offset 0x02E7 - NnFlex Override for LP5 WckDcaWr + Controlled by NnFlexDramOvrdMask bit[5], 4-bit 2's complement, valid range: [-7..7] +**/ + UINT8 NnFlexLpddr5WckDcaWr; + +/** Offset 0x02E8 - Margin limit check L2 + Margin limit check L2 threshold: 100=Default +**/ + UINT16 MarginLimitL2; + +/** Offset 0x02EA - Extended Bank Hashing + Eanble/Disable ExtendedBankHashing + $EN_DIS +**/ + UINT8 ExtendedBankHashing; + +/** Offset 0x02EB - DRFM Blast Radius Configuration + Row Hammer DRFM Blast Radius Configuration determines number of victim rows around + aggressor row targeted to send the DRFM sequence to: 2=BlastRadius 2, 3=BlastRadius + 3, 4=BlastRadius 4 +**/ + UINT8 DrfmBrc; + +/** Offset 0x02EC - LP5 Command Pins Mapping + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. +**/ + UINT8 Lp5CccConfig; + +/** Offset 0x02ED - Command Pins Mirrored + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. +**/ + UINT8 CmdMirror; + +/** Offset 0x02EE - Time Measure + Time Measure: 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 MrcTimeMeasure; + +/** Offset 0x02EF - DVFSQ Enabled + Enable/Disable DVFSQ + $EN_DIS +**/ + UINT8 DvfsqEnabled; + +/** Offset 0x02F0 - E-DVFSC Enabled + Eanble/Disable DVFSC + $EN_DIS +**/ + UINT8 DvfscEnabled; + +/** Offset 0x02F1 - Ddr5 Dca Training + Enable/Disable DDR5 Dca Training + $EN_DIS +**/ + UINT8 DCCDDR5READDCA; + +/** Offset 0x02F2 - PPR Run WCHMATS8 + Run WCHMATS8 in Post Package Repair flow +**/ + UINT8 PprRunWCHMATS8; + +/** Offset 0x02F3 - PPR Run Retention + Run Data Retention in Post Package Repair flow +**/ + UINT8 PprRunRetention; + +/** Offset 0x02F4 - PPR Run XMarch + Run XMarch in Post Package Repair flow +**/ + UINT8 PprRunXMarch; + +/** Offset 0x02F5 - PPR Run XMarchG + Run XMarchG in Post Package Repair flow +**/ + UINT8 PprRunXMarchG; + +/** Offset 0x02F6 - PPR Run YMarchShort + Run YMarchShort in Post Package Repair flow +**/ + UINT8 PprRunYMarchShort; + +/** Offset 0x02F7 - PPR Run YMarchLong + Run YMarchLong in Post Package Repair flow +**/ + UINT8 PprRunYMarchLong; + +/** Offset 0x02F8 - PPR Run Mmrw + Run Mmrw in Post Package Repair flow +**/ + UINT8 PprRunMmrw; + +/** Offset 0x02F9 - PPR Test Disabled + Don't run any test in Post Package Repair flow +**/ + UINT8 PprTestDisabled; + +/** Offset 0x02FA - PPR Entry Info + PPR Repair Info +**/ + UINT8 PprEntryInfo[16]; + +/** Offset 0x030A - PPR Entry Address + PPR Repair Memory Address +**/ + UINT8 PprEntryAddress[16]; + +/** Offset 0x031A - Read Vref Decap Training* + Enable/Disable Read Timing Centering Training with SR stress* + $EN_DIS +**/ + UINT8 RDTCIDLE; + +/** Offset 0x031B - PPR Retry Limit + Sets a limit on the number of times Memory Testing will be retried after attempting + to repair using PPR. +**/ + UINT8 PprRetryLimit; + +/** Offset 0x031C - Use 1p5 Read Postamble + Enables/Disable using 1p5 tCK Read Postamble for higher freqencies + $EN_DIS +**/ + UINT8 Use1p5ReadPostamble; + +/** Offset 0x031D - IsWckIdleExitEnabled + Enables/Disables WCK Idle Exit + $EN_DIS +**/ + UINT8 IsWckIdleExitEnabled; + +/** Offset 0x031E - LP5 Safe Speed + Enable / Disable LP5 Safe Speed feature + $EN_DIS +**/ + UINT8 Lp5SafeSpeed; + +/** Offset 0x031F - Force InternalClkOn + Force InternalClocksOn and TxPiOn to be set to 1 for frequencies >= 7467 + $EN_DIS +**/ + UINT8 ForceInternalClkOn; + +/** Offset 0x0320 - DIMM Rx Offset Calibration training + Enable/Disable DIMM Rx Offset Calibration training + $EN_DIS +**/ + UINT8 DIMMRXOFFSET; + +/** Offset 0x0321 - Enable Flexible Analog Settings + Enable/Disable Flexible Analog Settings + $EN_DIS +**/ + UINT8 FlexibleAnalogSettings; + +/** Offset 0x0322 - Force WRDSEQT at 2400 + Force Enable Write Drive Strength training at 2400 + $EN_DIS +**/ + UINT8 ForceWRDSEQT2400; + +/** Offset 0x0323 - NnFlex Override for LP5 WckDcaRd + Controlled by NnFlexDramOvrdMask bit[6], 4-bit 2's complement, valid range: [-7..7] +**/ + UINT8 NnFlexLpddr5WckDcaRd; + +/** Offset 0x0324 - NnFlex Override for LP5 RttNT + Controlled by NnFlexDramOvrdMask bit[7], MR41 encoding +**/ + UINT8 NnFlexLpddr5RttNT; + +/** Offset 0x0325 - NnFlex Override for DDR5 DfeTap1 + Controlled by NnFlexDramOvrdMask bit[0], 8-bit 2's complement, valid range: [-40..40] +**/ + UINT8 NnFlexDdr5DfeTap1; + +/** Offset 0x0326 - NnFlex Override for DDR5 DfeTap2 + Controlled by NnFlexDramOvrdMask bit[1], 8-bit 2's complement, valid range: [-15..15] +**/ + UINT8 NnFlexDdr5DfeTap2; + +/** Offset 0x0327 - NnFlex Override for DDR5 RttWr + Controlled by NnFlexDramOvrdMask bit[2], MR34 encoding +**/ + UINT8 NnFlexDdr5RttWr; + +/** Offset 0x0328 - NnFlex Override for DDR5 RttNomWr + Controlled by NnFlexDramOvrdMask bit[3], MR35 encoding +**/ + UINT8 NnFlexDdr5RttNomWr; + +/** Offset 0x0329 - NnFlex Override for DDR5 RttNomRd + Controlled by NnFlexDramOvrdMask bit[4], MR35 encoding +**/ + UINT8 NnFlexDdr5RttNomRd; + +/** Offset 0x032A - NnFlex Override for DDR5 RonUp + Controlled by NnFlexDramOvrdMask bit[5], MR5 encoding +**/ + UINT8 NnFlexDdr5RonUp; + +/** Offset 0x032B - NnFlex Override for DDR5 RonDn + Controlled by NnFlexDramOvrdMask bit[6], MR5 encoding +**/ + UINT8 NnFlexDdr5RonDn; + +/** Offset 0x032C - NnFlex Phy Override Enable bit mask + Bitmask to enable PHY NnFlex overrides. [0]: PhyRxEqTap0 [1]: PhyRxEqTap1 [2]: PhyDqTcoComp + [3]: PhyRxCtleR [4]: PhyRxCtleC [5]: PhyRxCtleRcmn [6]: PhyRxCtleEq [7]: PhyRxCtleTailCtl +**/ + UINT8 NnFlexPhyOvrdMask; + +/** Offset 0x032D - NnFlex LP5/DDR5 Override Enable bit mask + Bitmask to enable LP5/DDR5 NnFlex overrides. [0]: Lp5Dfeq/Ddr5DfeTap1 [1]: Lp5PdDrvStr/Ddr5DfeTap2 + [2]: Lp5SocOdt/Ddr5RttWr [3]: Lp5PreEmpDn/Ddr5RttNomWr [4]: Lp5PreEmpUp/Ddr5RttNomRd + [5]: Lp5WckDcaWr/Ddr5RonUp [6]: Lp5WckDcaRd/Ddr5RonDn [7]: Lp5RttNT +**/ + UINT8 NnFlexDramOvrdMask; + +/** Offset 0x032E - MrcPreMemRsvd + Reserved for MRC Pre-Mem + $EN_DIS +**/ + UINT8 MrcPreMemRsvd; + +/** Offset 0x032F - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x0330 - Spd Address Table + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[16]; + +/** Offset 0x0340 - Enable/Disable MRC TXT dependency + When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): + MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization + $EN_DIS +**/ + UINT8 TxtImplemented; + +/** Offset 0x0341 - PCIE Resizable BAR Support + Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default). + $EN_DIS +**/ + UINT8 PcieResizableBarSupport; + +/** Offset 0x0342 - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x0343 - Generate BIOS Data ACPI Table + Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it + $EN_DIS +**/ + UINT8 BdatEnable; + +/** Offset 0x0344 - BdatTestType + Indicates the type of Memory Training data to populate into the BDAT ACPI table. + 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D +**/ + UINT8 BdatTestType; + +/** Offset 0x0345 - Enable PCH HSIO PCIE Rx Set Ctle + Enable PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtleEnable[28]; + +/** Offset 0x0361 - PCH HSIO PCIE Rx Set Ctle Value + PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtle[28]; + +/** Offset 0x037D - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; + +/** Offset 0x0399 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; + +/** Offset 0x03B5 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; + +/** Offset 0x03D1 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; + +/** Offset 0x03ED - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; + +/** Offset 0x0409 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; + +/** Offset 0x0425 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; + +/** Offset 0x0441 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value + PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen1DeEmph[28]; + +/** Offset 0x045D - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; + +/** Offset 0x0479 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; + +/** Offset 0x0495 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; + +/** Offset 0x04B1 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; + +/** Offset 0x04CD - HD Audio DMIC Link Clock Select + Determines DMIC Clock Source. 0: Both, 1: ClkA, 2: ClkB + 0: Both, 1: ClkA, 2: ClkB +**/ + UINT8 PchHdaAudioLinkDmicClockSelect[2]; + +/** Offset 0x04CF - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x04D0 - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x04D1 - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x04D2 - Enable HDA SDI lanes + Enable/disable HDA SDI lanes. +**/ + UINT8 PchHdaSdiEnable[2]; + +/** Offset 0x04D4 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x04D6 +**/ + UINT8 FspmUpdRsvd1543[2]; + +/** Offset 0x04D8 - DMIC ClkA Pin Muxing (N - DMIC number) + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x04E0 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x04E1 +**/ + UINT8 FspmUpdRsvd1554[3]; + +/** Offset 0x04E4 - DMIC Data Pin Muxing + Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x04EC - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[7]; + +/** Offset 0x04F3 - PCH Hda Disc Bt Off Enabled + Hda Disc Bt Off Enabled +**/ + UINT8 PchHdaDiscBtOffEnabled; + +/** Offset 0x04F4 - PCH HDA Discrete BT Offload Ssp Link + Discrete BT Offload Ssp Link +**/ + UINT32 PchHdaDiscBtOffSspLink; + +/** Offset 0x04F8 - SSP Sclk Pin Muxing (N - SSP Number) + Determines SSP Sclk Pin muxing. See GPIOV2_*_MUXING_I2S*_SCLK +**/ + UINT32 PchHdaAudioLinkSspSclkPinMux[7]; + +/** Offset 0x0514 - SSP Sfmr Pin Muxing (N - SSP Number) + Determines SSP Sfmr Pin muxing. See GPIOV2_*_MUXING_I2S*_SFMR +**/ + UINT32 PchHdaAudioLinkSspSfmrPinMux[7]; + +/** Offset 0x0530 - SSP Txd Pin Muxing (N - SSP Number) + Determines SSP Txd Pin muxing. See GPIOV2_*_MUXING_I2S*_TXD +**/ + UINT32 PchHdaAudioLinkSspTxdPinMux[7]; + +/** Offset 0x054C - SSP Rxd Pin Muxing (N - SSP Number) + Determines SSP Rxd Pin muxing. See GPIOV2_*_MUXING_I2S*_RXD +**/ + UINT32 PchHdaAudioLinkSspRxdPinMux[7]; + +/** Offset 0x0568 - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[5]; + +/** Offset 0x056D - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x056E - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x056F - Sndw Multilane enablement + SoundWire Multiline enablement. Default is DISABLE. 0: DISABLE, 1: Two lines enabled, + 2: Three lines enabled, 3: Four Lines enabled. + $EN_DIS +**/ + UINT8 PchHdAudioSndwMultilaneEnable[2]; + +/** Offset 0x0571 +**/ + UINT8 FspmUpdRsvd10[3]; + +/** Offset 0x0574 - SoundWire Clk Pin Muxing (N - SoundWire number) + Determines SoundWire Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_CLK* +**/ + UINT32 PchHdaAudioLinkMultilaneClkPinMux[2]; + +/** Offset 0x057C - SoundWire Multilane Data0 Pin Muxing (N - SoundWire number) + Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA0* +**/ + UINT32 PchHdaAudioLinkMultilaneData0PinMux[2]; + +/** Offset 0x0584 - SoundWire Multilane Data1 Pin Muxing (N - SoundWire number) + Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA1* +**/ + UINT32 PchHdaAudioLinkMultilaneData1PinMux[2]; + +/** Offset 0x058C - SoundWire Multilane Data2 Pin Muxing (N - SoundWire number) + Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA2* +**/ + UINT32 PchHdaAudioLinkMultilaneData2PinMux[2]; + +/** Offset 0x0594 - SoundWire Multilane Data3 Pin Muxing (N - SoundWire number) + Determines SoundWire Multilane Clk Pin muxing. See GPIOV2_*_MUXING_SNDW_DATA3* +**/ + UINT32 PchHdaAudioLinkMultilaneData3PinMux[2]; + +/** Offset 0x059C - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x059D - Sndw Interface for Multilanes (N - SoundWire number) + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + 0: Sndw0, 1: Sndw1, 2: Sndw2, 3: Sndw3, 4: Sndw4, 5: Sndw5 +**/ + UINT8 PchHdAudioSndwMultilaneSndwInterface[2]; + +/** Offset 0x059F +**/ + UINT8 FspmUpdRsvd11; + +/** Offset 0x05A0 - Audio Sub System IDs + Set default Audio Sub System IDs. If its set to 0 then value from Strap is used. +**/ + UINT16 ResetWaitTimer; + +/** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD) + Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: + FORCE_ENABLE, 2: FORCE_DISABLE. + 0: POR, 1: Force Enable, 2: Force Disable +**/ + UINT8 PchHdaTestPowerClockGating; + +/** Offset 0x05A3 - Low Frequency Link Clock Source (LFLCS) + 0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL). + 0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL) +**/ + UINT8 PchHdaTestLowFreqLinkClkSrc; + +/** Offset 0x05A4 - Audio Sub System IDs + Set default Audio Sub System IDs. If its set to 0 then value from Strap is used. +**/ + UINT32 PchHdaSubSystemIds; + +/** Offset 0x05A8 - SoundWire clock source select + Select clock source for the SoundWire controllers. 0: XTAL, 1: Audio PLL. + $EN_DIS +**/ + UINT8 PchHdaSndwClockSourceSelect; + +/** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding + Original LPC only decodes one byte of port 80h. + $EN_DIS +**/ + UINT8 PchLpcEnhancePort8xhDecoding; + +/** Offset 0x05AA - Usage type for ClkSrc + 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[18]; + +/** Offset 0x05BC - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[18]; + +/** Offset 0x05CE +**/ + UINT8 PcieClkSrcClkReqRsvd[14]; + +/** Offset 0x05DC - Clk Req GPIO Pin + Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values. +**/ + UINT32 PcieClkReqGpioMux[8]; + +/** Offset 0x05FC - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x0600 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x0601 +**/ + UINT8 FspmUpdRsvd12[3]; + +/** Offset 0x0604 - Serial Io Uart Debug Mmio Base + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode + = SerialIoUartPci. +**/ + UINT32 SerialIoUartDebugMmioBase; + +/** Offset 0x0608 - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x0609 - SerialDebugMrcLevel + MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 SerialDebugMrcLevel; + +/** Offset 0x060A - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x060B - Serial Io Uart Debug Parity + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartDebugParity; + +/** Offset 0x060C - Serial Io Uart Debug BaudRate + Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, + 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 +**/ + UINT32 SerialIoUartDebugBaudRate; + +/** Offset 0x0610 - Serial Io Uart Debug Stop Bits + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 SerialIoUartDebugStopBits; + +/** Offset 0x0611 - Serial Io Uart Debug Data Bits + Set default word length. 0: Default, 5,6,7,8 + 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS +**/ + UINT8 SerialIoUartDebugDataBits; + +/** Offset 0x0612 - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;1: Enable. + $EN_DIS +**/ + UINT8 ImguClkOutEn[6]; + +/** Offset 0x0618 - Enable/Disable SA IPU + Enable(Default): Enable SA IPU, Disable: Disable SA IPU + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x0619 - Disable and Lock Watch Dog Register + Set 1 to clear WDT status, then disable and lock WDT registers. + $EN_DIS +**/ + UINT8 WdtDisableAndLock; + +/** Offset 0x061A +**/ + UINT8 FabricGVDisable; + +/** Offset 0x061B +**/ + UINT8 FspmUpdRsvd13[1]; + +/** Offset 0x061C - HECI Timeouts + 0: Disable, 1: Enable (Default) timeout check for HECI + $EN_DIS +**/ + UINT8 HeciTimeouts; + +/** Offset 0x061D - HECI2 Interface Communication + Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. + $EN_DIS +**/ + UINT8 HeciCommunication2; + +/** Offset 0x061E - Check HECI message before send + Test, 0: disable, 1: enable, Enable/Disable message check. + $EN_DIS +**/ + UINT8 DisableMessageCheck; + +/** Offset 0x061F - Force ME DID Init Status + Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set + ME DID init stat value + $EN_DIS +**/ + UINT8 DidInitStat; + +/** Offset 0x0620 - Enable KT device + Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device. + $EN_DIS +**/ + UINT8 KtDeviceEnable; + +/** Offset 0x0621 - CPU Replaced Polling Disable + Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop + $EN_DIS +**/ + UINT8 DisableCpuReplacedPolling; + +/** Offset 0x0622 - Skip CPU replacement check + Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check + $EN_DIS +**/ + UINT8 SkipCpuReplacementCheck; + +/** Offset 0x0623 - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob. + $EN_DIS +**/ + UINT8 SkipMbpHob; + +/** Offset 0x0624 - HECI Communication + Test, 0: POR, 1: enable, 2: disable, Disables HECI communication causing ME to enter + error state. + $EN_DIS +**/ + UINT8 HeciCommunication; + +/** Offset 0x0625 - HECI3 Interface Communication + Test, 0: POR, 1: enable, 2: disable, Adds or Removes HECI3 Device from PCI space. + $EN_DIS +**/ + UINT8 HeciCommunication3; + +/** Offset 0x0626 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0627 - PcdSerialDebugBaudRate + Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. + 3:9600, 4:19200, 6:56700, 7:115200 +**/ + UINT8 PcdSerialDebugBaudRate; + +/** Offset 0x0628 - Post Code Output Port + This option configures Post Code Output Port +**/ + UINT16 PostCodeOutputPort; + +/** Offset 0x062A - Enable/Disable I2cPostcode + Enable (Default): Postcode via I2C, Disable: Postcode via Port80 + $EN_DIS +**/ + UINT8 I2cPostCodeEnable; + +/** Offset 0x062B +**/ + UINT8 FspmUpdRsvd14[5]; + +/** Offset 0x0630 - FSPM Validation Pointer + Point to FSPM Validation configuration structure +**/ + UINT64 FspmValidationPtr; + +/** Offset 0x0638 - Extended BIOS Support + Enable/Disable Extended BIOS Region Support. Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 ExtendedBiosDecodeRange; + +/** Offset 0x0639 - Extented BIOS Direct Read Decode enable + Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. + 0: disabled (default), 1: enabled + $EN_DIS +**/ + UINT8 PchSpiExtendedBiosDecodeRangeEnable; + +/** Offset 0x063A +**/ + UINT8 FspmUpdRsvd15[2]; + +/** Offset 0x063C - Extended BIOS Direct Read Decode Range base + Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeBase; + +/** Offset 0x0640 - Extended BIOS Direct Read Decode Range limit + Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeLimit; + +/** Offset 0x0644 - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x0645 - Enable SMBus ARP support + Enable SMBus ARP support. + $EN_DIS +**/ + UINT8 SmbusArpEnable; + +/** Offset 0x0646 - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x0647 +**/ + UINT8 FspmUpdRsvd16; + +/** Offset 0x0648 - SMBUS Base Address + SMBUS Base Address (IO space). +**/ + UINT16 PchSmbusIoBase; + +/** Offset 0x064A - Enable SMBus Alert Pin + Enable SMBus Alert Pin. + $EN_DIS +**/ + UINT8 PchSmbAlertEnable; + +/** Offset 0x064B +**/ + UINT8 FspmUpdRsvd17[5]; + +/** Offset 0x0650 - Point of RsvdSmbusAddressTable + Array of addresses reserved for non-ARP-capable SMBus devices. +**/ + UINT64 RsvdSmbusAddressTablePtr; + +/** Offset 0x0658 - Smbus dynamic power gating + Disable or Enable Smbus dynamic power gating. + $EN_DIS +**/ + UINT8 SmbusDynamicPowerGating; + +/** Offset 0x0659 - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write + Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + UINT8 SmbusSpdWriteDisable; + +/** Offset 0x065A - Enable/Disable SA OcSupport + Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport + $EN_DIS +**/ + UINT8 SaOcSupport; + +/** Offset 0x065B - VF Point Count + Number of supported Voltage & Frequency Point Offset +**/ + UINT8 VfPointCount[10]; + +/** Offset 0x0665 - ProcessVmaxLimit + Disabling Process Vmax Limit will allow user to set any voltage +**/ + UINT8 ProcessVmaxLimit; + +/** Offset 0x0666 - CorePllCurrentRefTuningOffset + Core PLL Current Reference Tuning Offset. 0: No offset. Range 0-15 +**/ + UINT8 CorePllCurrentRefTuningOffset; + +/** Offset 0x0667 - RingPllCurrentRefTuningOffset + Ring PLL Current Reference Tuning Offset. 0: No offset. Range 0-15 +**/ + UINT8 RingPllCurrentRefTuningOffset; + +/** Offset 0x0668 - IaAtomPllCurrentRefTuningOffset + IaAtom PLL Current Reference Tuning Offset. 0: No offset. Range 0-15 +**/ + UINT8 IaAtomPllCurrentRefTuningOffset; + +/** Offset 0x0669 - CoreMinRatio + equest Core Min Ratio. Limit Core minimum ratio for extreme overclocking. Default + 0 indicates no request +**/ + UINT8 CoreMinRatio; + +/** Offset 0x066A - CoreMiNegativeTemperatureReportingnRatio + Negative Temperature Reporting Enable. 0: Disable, 1: enable +**/ + UINT8 NegativeTemperatureReporting; + +/** Offset 0x066B - PcorePowerDensityThrottle + Power Density Throttle control allows user to disable P-core +**/ + UINT8 PcorePowerDensityThrottle; + +/** Offset 0x066C - EcorePowerDensityThrottle + Power Density Throttle control allows user to disable P-core +**/ + UINT8 EcorePowerDensityThrottle; + +/** Offset 0x066D - Over clocking support + Over clocking support; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcSupport; + +/** Offset 0x066E - UnderVolt Protection + When UnderVolt Protection is enabled, user will be not be able to program under + voltage in OS runtime. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 UnderVoltProtection; + +/** Offset 0x066F - Realtime Memory Timing + 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform + realtime memory timing changes after MRC_DONE. + 0: Disabled, 1: Enabled +**/ + UINT8 RealtimeMemoryTiming; + +/** Offset 0x0670 - core voltage override + The core voltage override which is applied to the entire range of cpu core frequencies. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageOverride; + +/** Offset 0x0672 - Core Turbo voltage Offset + The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 +**/ + UINT16 CoreVoltageOffset; + +/** Offset 0x0674 - Core PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 CorePllVoltageOffset; + +/** Offset 0x0675 - AVX2 Ratio Offset + 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio + vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx2RatioOffset; + +/** Offset 0x0676 - BCLK Adaptive Voltage Enable + When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: + Disable; 1: Enable + $EN_DIS +**/ + UINT8 BclkAdaptiveVoltage; + +/** Offset 0x0677 - Ring Downbin + Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always + lower than the core ratio.0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 RingDownBin; + +/** Offset 0x0678 - Row Hammer pTRR LFSR0 Mask + Row Hammer pTRR LFSR0 Mask, 1/2^(value) +**/ + UINT8 Lfsr0Mask; + +/** Offset 0x0679 - Margin Limit Check + Margin Limit Check. Choose level of margin check + 0:Disable, 1:L1, 2:L2, 3:Both +**/ + UINT8 MarginLimitCheck; + +/** Offset 0x067A - Row Hammer pTRR LFSR1 Mask + Row Hammer pTRR LFSR1 Mask, 1/2^(value) +**/ + UINT8 Lfsr1Mask; + +/** Offset 0x067B - Row Hammer DRAM Refresh Management Mode + Row Hammer Adaptive Refresh Management Level: 0-RFM (default), 1-ARFMLevel A, 2-ARFMLevel + B, 3-ARFMLevel C, 4-Disable ARFM and RFM + 0: RFM, 1: ARFM Level A, 2: ARFM Level B, 3: ARFM Level C, 4: ARFM and RFM Disabled +**/ + UINT8 DramRfmMode; + +/** Offset 0x067C - Row Hammer Targeted Row Refresh Mode + Row Hammer Targeted Row Refresh: 0-DRFM, 1-pTRR (default), 2-Disable DRFM and pTRR + 0: DRFM, 1: pTRR, 2: Targeted Row Refresh Disabled +**/ + UINT8 TargetedRowRefreshMode; + +/** Offset 0x067D - TjMax Offset + TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support + TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 +**/ + UINT8 TjMaxOffset; + +/** Offset 0x067E - Per-Atom-Cluster VF Offset + Array used to specifies the selected Atom Core Cluster Offset Voltage. This voltage + is specified in millivolts. +**/ + UINT16 PerAtomClusterVoltageOffset[8]; + +/** Offset 0x068E - Per-Atom-Cluster VF Offset Prefix + Sets the PerAtomCLusterVoltageOffset value as positive or negative for the selected + Core; 0: Positive ; 1: Negative. +**/ + UINT8 PerAtomClusterVoltageOffsetPrefix[8]; + +/** Offset 0x0696 - Per-Atom-Cluster Voltage Mode + Array used to specifies the selected Atom Core ClusterVoltage Mode. +**/ + UINT8 PerAtomClusterVoltageMode[8]; + +/** Offset 0x069E - Per-Atom-Cluster Voltage Override + Array used to specifies the selected Atom Core Cluster Voltage Override. +**/ + UINT16 PerAtomClusterVoltageOverride[8]; + +/** Offset 0x06AE - Core VF Point Offset + Array used to specifies the Core Voltage Offset applied to the each selected VF + Point. This voltage is specified in millivolts. +**/ + UINT16 CoreVfPointOffset[15]; + +/** Offset 0x06CC - Core VF Point Offset Prefix + Sets the CoreVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. + 0:Positive, 1:Negative +**/ + UINT8 CoreVfPointOffsetPrefix[15]; + +/** Offset 0x06DB - Core VF Point Ratio + Array for the each selected Core VF Point to display the ration. +**/ + UINT8 CoreVfPointRatio[15]; + +/** Offset 0x06EA - Core VF Configuration Scope + Allows both all-core VF curve or per-core VF curve configuration; 0: All-core; + 1: Per-core. + 0:All-core, 1:Per-core +**/ + UINT8 CoreVfConfigScope; + +/** Offset 0x06EB +**/ + UINT8 FspmUpdRsvd18; + +/** Offset 0x06EC - Per-core VF Offset + Array used to specifies the selected Core Offset Voltage. This voltage is specified + in millivolts. +**/ + UINT16 PerCoreVoltageOffset[8]; + +/** Offset 0x06FC - Per-core VF Offset Prefix + Sets the PerCoreVoltageOffset value as positive or negative for the selected Core; + 0: Positive ; 1: Negative. +**/ + UINT8 PerCoreVoltageOffsetPrefix[8]; + +/** Offset 0x0704 - Per Core Max Ratio override + Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new + favored core ratio to each Core. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 PerCoreRatioOverride; + +/** Offset 0x0705 - Per-core Voltage Mode + Array used to specifies the selected Core Voltage Mode. +**/ + UINT8 PerCoreVoltageMode[8]; + +/** Offset 0x070D +**/ + UINT8 FspmUpdRsvd19; + +/** Offset 0x070E - Per-core Voltage Override + Array used to specifies the selected Core Voltage Override. +**/ + UINT16 PerCoreVoltageOverride[8]; + +/** Offset 0x071E - Per Core Current Max Ratio + Array for the Per Core Max Ratio +**/ + UINT8 PerCoreRatio[8]; + +/** Offset 0x0726 - Atom Cluster Max Ratio + Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their + max core ratio will be aligned. +**/ + UINT8 AtomClusterRatio[8]; + +/** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die + Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio + (P0 to Pn) to select the multiplier so that the output is within the DCO frequency + range. As per the die selected, this threshold is applied to SA and MC/CMI PLL + for SOC die and SA, Ring and Atom PLL for CPU die. Range 0-63. When the threshold + is 0, static PVD ratio is selected based on the PVD Mode for SOC. 0: Default. +**/ + UINT8 PvdRatioThreshold; + +/** Offset 0x072F - Pvd Mode SOC/CPU die + Array of PVD Mode. Value from 0 to 3 for SOC/CPU. 0x0 = div-1 (VCO = Output clock), + 0x1 = div-2 (VCO = 2x Output clock), 0x2 = div-4 (VCO = 4x Output clock), 0x3 = + div-8 (VCO = 8x Output clock). +**/ + UINT8 PvdMode; + +/** Offset 0x0730 - FLL Overclock Mode + Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking + with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated + (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated + (3-5x) reference clock frequency and ratio limited to 63. +**/ + UINT8 FllOverclockMode; + +/** Offset 0x0731 +**/ + UINT8 FspmUpdRsvd20; + +/** Offset 0x0732 - Ring VF Point Offset + Array used to specifies the Ring Voltage Offset applied to the each selected VF + Point. This voltage is specified in millivolts. +**/ + UINT16 RingVfPointOffset[15]; + +/** Offset 0x0750 - Ring VF Point Offset Prefix + Sets the RingVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. +**/ + UINT8 RingVfPointOffsetPrefix[15]; + +/** Offset 0x075F - Ring VF Point Ratio + Array for the each selected Ring VF Point to display the ration. +**/ + UINT8 RingVfPointRatio[15]; + +/** Offset 0x076E - Soc Die SSC enable + Enable/Disable Soc-Die SSC Configuration. 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 SocDieSscEnable; + +/** Offset 0x076F - Core Operating Point Reporting + Enables Core Operating point reporting. 0: Disable; 1: Enable + 0:Disable, 1:Enable +**/ + UINT8 CoreOpPointReportingEn; + +/** Offset 0x0770 - CPU BCLK OC Frequency + CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is + 40Mhz-1000Mhz. +**/ + UINT32 CpuBclkOcFrequency; + +/** Offset 0x0774 - SOC BCLK OC Frequency + SOC BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is + 40Mhz-1000Mhz. +**/ + UINT32 SocBclkOcFrequency; + +/** Offset 0x0778 - Bitmask of disable cores + Core mask is a bitwise indication of which core should be disabled. 0x00=Default; + Bit 0 - core 0, bit 7 - core 7. +**/ + UINT64 DisablePerCoreMask; + +/** Offset 0x0780 - Granular Ratio Override + Enable or disable OC Granular Ratio Override. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 GranularRatioOverride; + +/** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor + AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in + 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx2VoltageScaleFactor; + +/** Offset 0x0782 - Ring PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 RingPllVoltageOffset; + +/** Offset 0x0783 - OcPreMemRsvd + Reserved for OC Pre-Mem + $EN_DIS +**/ + UINT8 OcPreMemRsvd[5]; + +/** Offset 0x0788 - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x0789 +**/ + UINT8 FspmUpdRsvd21; + +/** Offset 0x078A - BiosSize + The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != + 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected + Range) so that a BIOS Update Script can be stored in the DPR. +**/ + UINT16 BiosSize; + +/** Offset 0x078C - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x078D +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x078E - Txt + Enables utilization of additional hardware capabilities provided by Intel (R) Trusted + Execution Technology. Changes require a full power cycle to take effect. 0: + Disable, 1: Enable + $EN_DIS +**/ + UINT8 Txt; + +/** Offset 0x078F - Skip Stop PBET Timer Enable/Disable + Skip Stop PBET Timer; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 SkipStopPbet; + +/** Offset 0x0790 - Reset Auxiliary content + Reset Auxiliary content, 0: Disabled, 1: Enabled + $EN_DIS +**/ + UINT8 ResetAux; + +/** Offset 0x0791 - TseEnable + Enable/Disable. 0: Disable, Enable/Disable Tse feature, 1: enable + $EN_DIS +**/ + UINT8 TseEnable; + +/** Offset 0x0792 - Enable or Disable TDX + Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager + (VMM)/hypervisor 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TdxEnable; + +/** Offset 0x0793 - MKTME Key-Id Bits Override Enable + Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager + (VMM)/hypervisor 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 GenerateNewTmeKey; + +/** Offset 0x0794 +**/ + UINT8 FspmUpdRsvd22[4]; + +/** Offset 0x0798 - TME Exclude Base Address + TME Exclude Base Address. +**/ + UINT64 TmeExcludeBase; + +/** Offset 0x07A0 - TME Exclude Size Value + TME Exclude Size Value. +**/ + UINT64 TmeExcludeSize; + +/** Offset 0x07A8 - TdxActmModuleAddr + Base address of Tdx Actm module, used for launching the Actm +**/ + UINT64 TdxActmModuleAddr; + +/** Offset 0x07B0 - TdxActmModuleSize + size of Tdx Actm module, used for launching the Actm +**/ + UINT32 TdxActmModuleSize; + +/** Offset 0x07B4 - TdxSeamldrSvn + TdxSeamldrSvn +**/ + UINT8 TdxSeamldrSvn; + +/** Offset 0x07B5 - Boot max frequency + Enable Boot Maximum Frequency in CPU strap. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 BootMaxFrequency; + +/** Offset 0x07B6 - BIST on Reset + Enable/Disable BIST (Built-In Self Test) on reset. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 BistOnReset; + +/** Offset 0x07B7 - Reduce XeCores + Enable/Disable Reduce XeCores. 0: Disable(strap=1) ; 1: Enable(strap=0. + $EN_DIS +**/ + UINT8 ReduceXecores; + +/** Offset 0x07B8 - Enable or Disable VMX + Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities + provided by Vanderpool Technology. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x07B9 - Processor Early Power On Configuration FCLK setting + FCLK frequency can take values of 400MHz, 800MHz and 1GHz. 0: 800 MHz (ULT/ULX). + 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x07BA - Enable CPU CrashLog + Enable or Disable CPU CrashLog; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x07BB - Enable or Disable TME + Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks. + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x07BC - CPU Run Control + Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: + No Change + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DebugInterfaceEnable; + +/** Offset 0x07BD - CPU Run Control Lock + Lock or Unlock CPU Run Control; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DebugInterfaceLockEnable; + +/** Offset 0x07BE - Enable CPU CrashLog GPRs dump + Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only + disable Smm GPRs dump + 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled +**/ + UINT8 CrashLogGprs; + +/** Offset 0x07BF - Over clocking Lock + Lock Overclocking. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcLock; + +/** Offset 0x07C0 - CPU ratio value + This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio + set by Hardware (HFM). Valid Range 0 to 63. +**/ + UINT8 CpuRatio; + +/** Offset 0x07C1 - Number of active big cores + Number of P-cores to enable in each processor package. Note: Number of P-Cores and + E-Cores are looked at together. When both are {0,0 + 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores +**/ + UINT8 ActiveCoreCount; + +/** Offset 0x07C2 - Number of active small cores + Number of E-cores to enable in each processor package. Note: Number of P-Cores and + E-Cores are looked at together. When both are {0,0 + 0:Disable all small cores, 1:1, 2:2, 3:3, 0xFF:Active all small cores +**/ + UINT8 ActiveSmallCoreCount; + +/** Offset 0x07C3 - Number of LP Atom cores + Number of LP E-cores to enable in LP. 0: Disable all LP Atom cores; 1: 1; 2: 2; + 0xFF: Active all LP Atom cores + 0:Disable all LP Atom cores, 1:1, 2:2, 0xFF:Active all cores +**/ + UINT8 ActiveLpAtomCoreCount; + +/** Offset 0x07C4 - DFD Enable + Enable or Disable DFD. 0: Disable, 1:Enable + $EN_DIS +**/ + UINT8 DfdEnable; + +/** Offset 0x07C5 +**/ + UINT8 FspmUpdRsvd23[3]; + +/** Offset 0x07C8 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x07CC - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x07D0 - SmmRelocationEnable Enable + Enable or Disable SmmRelocationEnable. 0: Disable, 1:Enable + $EN_DIS +**/ + UINT8 SmmRelocationEnable; + +/** Offset 0x07D1 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts. Default = 0h. +**/ + UINT8 TccActivationOffset; + +/** Offset 0x07D2 +**/ + UINT8 FspmUpdRsvd24[2]; + +/** Offset 0x07D4 - Platform PL1 power + Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W + when programming. Value set 120 = 15W. Any value can be programmed between Max + and Min Power Limits. This setting will act as the new PL1 value for the Package + RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range + 0 to 32767. +**/ + UINT32 PsysPowerLimit1Power; + +/** Offset 0x07D8 - PlatformAtxTelemetryUnit Mode + Enable/Disable PlatformAtxTelemetryUnit Mode. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT32 PlatformAtxTelemetryUnit; + +/** Offset 0x07DC - Platform PL1 power + Short term Power Limit value for custom cTDP level. Units are 125 milliwatt. +**/ + UINT16 CustomPowerLimit1; + +/** Offset 0x07DE - Platform PL1 power + Short term Power Limit value for custom cTDP level. Units are 125 milliwatt. +**/ + UINT16 CustomPowerLimit2; + +/** Offset 0x07E0 - Platform PL2 power + Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W + when programming. Value set 120 = 15W. Any value can be programmed between Max + and Min Power Limits. This setting will act as the new Max Turbo Power (PL2) value + for the Package RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PsysPowerLimit2Power; + +/** Offset 0x07E4 - Vsys Max System battery volatge + Vsys Max defined in 1/1000 increments. Range is 0-65535. For a 1.25 voltage, enter + 1250. Default =0xFF. +**/ + UINT16 VsysMax; + +/** Offset 0x07E6 - ThETA Ibatt Feature + Enable or Disable ThETA Ibatt Feature. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ThETAIbattEnable; + +/** Offset 0x07E7 +**/ + UINT8 FspmUpdRsvd25; + +/** Offset 0x07E8 - ISYS Current Limit L1 + This field indicated the current limitiation of L1. Indicate current limit for which + dependency is on AC/DC mode before PSYS.Units of measurements are 1/8 A +**/ + UINT16 IsysCurrentLimitL1; + +/** Offset 0x07EA - ISYS Current Limit L1 Tau + This Specifies the time window used to calculate average current for ISYS_L1. The + units of measuremnts are specified in PACKAGE_POWER_SKU[TIME_UNIT] +**/ + UINT8 IsysCurrentL1Tau; + +/** Offset 0x07EB +**/ + UINT8 FspmUpdRsvd26; + +/** Offset 0x07EC - ISYS Current Limit L2 + This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm.Indicate current limit + for which dependency is on AC/DC mode before PSYS. Units of measurements are 1/8 A +**/ + UINT16 IsysCurrentLimitL2; + +/** Offset 0x07EE - ISYS Current Limit L1 Enable + This bits enables disables ISYS_CURRENT_LIMIT_L1 algorithm. It control loop based + on the system power source AC or DC mode. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 IsysCurrentLimitL1Enable; + +/** Offset 0x07EF - ISYS Current Limit L2 Enable + This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm. It control loop based + on the system power source AC or DC mode. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 IsysCurrentLimitL2Enable; + +/** Offset 0x07F0 - Package PL4 boost configuration + Configure Power Limit 4 Boost in Watts. Valid Range 0 to 63000 in step size of 125 + mWatt. The value 0 means disable. +**/ + UINT16 PowerLimit4Boost; + +/** Offset 0x07F2 - Skin Temperature Target + Target temperature is limit to which the control mechanism is regulating.It is defined + in 1/2 C increments.Range is 0-255. Temperature Range is 0-122.5 C.0: Auto. +**/ + UINT8 SkinTargetTemp[3]; + +/** Offset 0x07F5 - Skin Control Temperature Enable MMIO + Enables the skin temperature control for MMIO register. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 SkinTempControlEnable[3]; + +/** Offset 0x07F8 - Skin Temperature Loop Gain + Sets the aggressiveness of control loop where 0 is graceful, favors performance + on expense of temperature overshoots and 7 is for aggressive, favors tight regulation + over performance. Range is 0-7.0: Auto. +**/ + UINT8 SkinControlLoopGain[3]; + +/** Offset 0x07FB - Skin Temperature Override Enable + When set, Pcode will use TEMPERATURE_OVERRIDE values instead of reading from corresponding + sensor.. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 SkinTempOverrideEnable[3]; + +/** Offset 0x07FE - Skin Temperature Minimum Performance Level + Minimum Performance level below which the STC limit will not throttle. 0 - all levels + of throttling allowed incl. survivability actions. 256 - no throttling allowed.0: Auto. +**/ + UINT8 SkinMinPerformanceLevel[3]; + +/** Offset 0x0801 - Skin Temperature Override + Allows SW to override the input temperature. Pcode will use this value instead of + the sensor temperature. EC control is not impacted. Units: 0.5C. Values are 0 to + 255 which represents 0C-122.5C range.0: Auto. +**/ + UINT8 SkinTempOverride[3]; + +/** Offset 0x0804 - Skin Temperature Control Enable + Enables Skin Temperature Control Sensors Feature. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 SkinTempControl; + +/** Offset 0x0805 - AC or DC Power State + AC or DC power State; 0: DC; 1: AC + 0:DC, 1:AC +**/ + UINT8 AcDcPowerState; + +/** Offset 0x0806 - Enable or Disable VR Thermal Alert + Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DisableVrThermalAlert; + +/** Offset 0x0807 - Enable or Disable Thermal Monitor + Enable or Disable Thermal Monitor; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ThermalMonitor; + +/** Offset 0x0808 - Configuration for boot TDP selection + Assured Power (cTDP) Mode as Nominal/Level1/Level2/Deactivate Base Power (TDP) selection. + Deactivate option will set MSR to Nominal and MMIO to Zero. 0: Base Power (TDP) + Nominal; 1: Base Power (TDP) Down; 2: Base Power (TDP) Up;0xFF : Deactivate +**/ + UINT8 ConfigTdpLevel; + +/** Offset 0x0809 - ConfigTdp mode settings Lock + Assured Power (cTDP) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and + CONFIG_TDP_CONTROL. Note: When CTDP (Assured Power) Lock is enabled Custom ConfigTDP + Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0. + 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ConfigTdpLock; + +/** Offset 0x080A - Load Configurable TDP SSDT + Enables Assured Power (cTDP) control via runtime ACPI BIOS methods. This 'BIOS only' + feature does not require EC or driver support. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ConfigTdpBios; + +/** Offset 0x080B - CustomTurboActivationRatio + Turbo Activation Ratio for custom cTDP level + $EN_DIS +**/ + UINT8 CustomTurboActivationRatio; + +/** Offset 0x080C - CustomPowerLimit1Time + Short term Power Limit time window value for custom cTDP level. + $EN_DIS +**/ + UINT8 CustomPowerLimit1Time; + +/** Offset 0x080D - PL1 Enable value + Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it + activates the PL1 value to be used by the processor to limit the average power + of given time window. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit1; + +/** Offset 0x080E - PL1 timewindow + Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to + 128. 0 = default values. Indicates the time window over which Platform Processor + Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to + 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 +**/ + UINT8 PsysPowerLimit1Time; + +/** Offset 0x080F - PL2 Enable Value + Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS + will program the default values for Platform Power Limit 2. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit2; + +/** Offset 0x0810 - Package PL3 time window + Power Limit 3 Time Window value in Milli seconds. Indicates the time window over + which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves + the hardware default value. Valid value: 0, 3-8, 10, 12, 14, 16, 20, 24, + 28, 32, 40, 48, 56, 64. +**/ + UINT8 PowerLimit3Time; + +/** Offset 0x0811 - Package Long duration turbo mode time + Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 + = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window + which Processor Base Power (TDP) value should be maintained. Valid values(Unit + in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , + 80 , 96 , 112 , 128 +**/ + UINT8 PowerLimit1Time; + +/** Offset 0x0812 +**/ + UINT8 FspmUpdRsvd27[2]; + +/** Offset 0x0814 - Package Long duration turbo mode power limit + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. If value is 0, BIOS will program Processor + Base Power (TDP) value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid + Range 0 to 32767. +**/ + UINT32 PowerLimit1; + +/** Offset 0x0818 - Package Short duration turbo mode power limit + Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor + Base Power (TDP). Processor applies control policies such that the package power + does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PowerLimit2Power; + +/** Offset 0x081C - Package PL3 power limit + Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value + must be between Max and Min Power Limits. Other SKUs: This value must be between + Min Power Limit and Processor Base Power (TDP) Limit. If the value is 0, BIOS leaves + the hardware default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PowerLimit3; + +/** Offset 0x0820 - Package PL4 power limit + Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based + on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767. +**/ + UINT32 PowerLimit4; + +/** Offset 0x0824 - Short term Power Limit value for custom cTDP level 1 + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom1PowerLimit1; + +/** Offset 0x0828 - Long term Power Limit value for custom cTDP level 1 + Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Processor applies control policies + such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom1PowerLimit2; + +/** Offset 0x082C - Enable Configurable TDP + Applies Assured Power (cTDP) initialization settings based on non-Assured Power + (cTDP) or Assured Power (cTDP). Default is 1: Applies to Assured Power (cTDP) ; + if 0 then applies non-Assured Power (cTDP) and BIOS will bypass Assured Power (cTDP) + initialization flow + $EN_DIS +**/ + UINT8 ApplyConfigTdp; + +/** Offset 0x082D - Dual Tau Boost + Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W + sku. When DPTF is enabled this feature is ignored. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 DualTauBoost; + +/** Offset 0x082E - Tcc Offset Lock + Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature + target; 1:Enabled ; 0: Disabled. + $EN_DIS +**/ + UINT8 TccOffsetLock; + +/** Offset 0x082F - Package PL3 Duty Cycle + Specify the duty cycle in percentage that the CPU is required to maintain over the + configured time window. Range is 0-100. +**/ + UINT8 PowerLimit3DutyCycle; + +/** Offset 0x0830 - Package PL3 Lock + Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled + PL3 configuration can be changed during OS. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit3Lock; + +/** Offset 0x0831 - Package PL4 Lock + Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled + PL4 configuration can be changed during OS. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit4Lock; + +/** Offset 0x0832 - Short Duration Turbo Mode + Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program + the default values for Power Limit 2. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PowerLimit2; + +/** Offset 0x0833 - Response Mode + Enable/Disable Response Mode. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 ResponseMode; + +/** Offset 0x0834 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x0838 - TxtDprMemoryBase + Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable +**/ + UINT64 TxtDprMemoryBase; + +/** Offset 0x0840 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x0844 - TxtDprMemorySize + Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize + , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x0848 - TxtLcpPdBase + Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable +**/ + UINT64 TxtLcpPdBase; + +/** Offset 0x0850 - TxtLcpPdSize + Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable +**/ + UINT64 TxtLcpPdSize; + +/** Offset 0x0858 - BiosAcmBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT64 BiosAcmBase; + +/** Offset 0x0860 - BiosAcmSize + Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable +**/ + UINT32 BiosAcmSize; + +/** Offset 0x0864 - ApStartupBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 ApStartupBase; + +/** Offset 0x0868 - TgaSize + Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable +**/ + UINT32 TgaSize; + +/** Offset 0x086C - IsTPMPresence + IsTPMPresence default values +**/ + UINT8 IsTPMPresence; + +/** Offset 0x086D - Acoustic Noise Mitigation feature + Enabling this option will help mitigate acoustic noise on certain SKUs when the + CPU is in deeper C state. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 AcousticNoiseMitigation; + +/** Offset 0x086E - RfiMitigation + Enable or Disable RFI Mitigation. 0: Disable - DCM is the IO_N default; 1: + Enable - Enable IO_N DCM/CCM switching as RFI mitigation. + $EN_DIS +**/ + UINT8 RfiMitigation; + +/** Offset 0x086F - Platform Psys slope correction + PSYS Slope defined in 1/100 increments. 0 - Auto Specified in 1/100 increment + values. Range is 0-200. 125 = 1.25 +**/ + UINT8 PsysSlope; + +/** Offset 0x0870 - Platform Power Pmax + PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 + Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W +**/ + UINT16 PsysPmax; + +/** Offset 0x0872 - Thermal Design Current current limit + TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current + Limit of 125A, enter 1000. 0 = 0 Amps. 0: Auto. [0] for IA, [1] for GT, + [2] for SA, [3] for atom, [4]-[5] are Reserved. +**/ + UINT16 TdcCurrentLimit[6]; + +/** Offset 0x087E - AcLoadline + AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 + mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 AcLoadline[6]; + +/** Offset 0x088A - DcLoadline + DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 + mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 DcLoadline[6]; + +/** Offset 0x0896 - Power State 1 Threshold current + PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-152, which translates to 0-38A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT16 Ps1Threshold[6]; + +/** Offset 0x08A2 - Power State 2 Threshold current + PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-48, which translates to 0-12A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT16 Ps2Threshold[6]; + +/** Offset 0x08AE - Power State 3 Threshold current + PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-16, which translates to 0-4A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3] + through [5] are Reserved. +**/ + UINT16 Ps3Threshold[6]; + +/** Offset 0x08BA +**/ + UINT8 FspmUpdRsvd28[2]; + +/** Offset 0x08BC - Imon offset correction + IMON Offset is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000, + 127999]. For an offset of 25.348, enter 25348. 0: Auto. [0] for IA, [1] + for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT32 ImonOffset[6]; + +/** Offset 0x08D4 - Icc Max limit + Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous + current allowed at any given time. The value is represented in 1/4 A increments. + A value of 400 = 100A. 0 means AUTO. IA and GT, range 0-2047. SA range 0-1023. + [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 IccMax[6]; + +/** Offset 0x08E0 - VR Fast Vmode VoltageLimit support + Voltage Regulator Fast VoltageLimit . +**/ + UINT16 VrVoltageLimit[6]; + +/** Offset 0x08EC - Imon slope correction + IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter + 125. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 ImonSlope[6]; + +/** Offset 0x08F8 - Power State 3 enable/disable + PS3 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT8 Ps3Enable[6]; + +/** Offset 0x08FE - Power State 4 enable/disable + PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT8 Ps4Enable[6]; + +/** Offset 0x0904 - Enable/Disable BIOS configuration of VR + VR Config Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. + 0: Disable; 1: Enable. +**/ + UINT8 VrConfigEnable[6]; + +/** Offset 0x090A - Thermal Design Current enable/disable + Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, + [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved. +**/ + UINT8 TdcEnable[6]; + +/** Offset 0x0910 - Thermal Design Current Lock + Thermal Design Current Lock; 0: Disable; 1: Enable. [0] for IA, [1] for GT, + [2] for SA, [3] for atom, [4]-[5] are Reserved. +**/ + UINT8 TdcLock[6]; + +/** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains + This option needs to be configured to reduce acoustic noise during deeper C states. + False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp + during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are + Reserved. 0: False; 1: True + $EN_DIS +**/ + UINT8 FastPkgCRampDisable[6]; + +/** Offset 0x091C - Slew Rate configuration for Deep Package C States for VR domains + Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate + equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew + rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. 0: + Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16, 0xFF: Ignore the configuration +**/ + UINT8 SlowSlewRate[6]; + +/** Offset 0x0922 +**/ + UINT8 FspmUpdRsvd29[2]; + +/** Offset 0x0924 - Platform Psys offset correction + PSYS Offset defined in 1/1000 increments. 0 - Auto This is an 32-bit signed + value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset + of 25.348, enter 25348. +**/ + UINT32 PsysOffset; + +/** Offset 0x0928 - Thermal Design Current time window + Auto = 0 is default. Range is from 1ms to 448s. 0: Auto. [0] for IA, [1] + for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved. +**/ + UINT32 TdcTimeWindow[6]; + +/** Offset 0x0940 - TDC Mode + TDC Mode based on IRMS supported bit from Mailbox. 0: iPL2; 1: Irms. [0] + for IA, [1] for GT, [2] for SA, [3] for atom [4]-[5] are Reserved. +**/ + UINT8 TdcMode[6]; + +/** Offset 0x0946 - DLVR RFI Enable + Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 FivrSpectrumEnable; + +/** Offset 0x0947 - DLVR RFI Spread Spectrum Percentage + DLVR SSC in percentage with multiple of 0.25%. 0 = 0%, 10 = 4%. 0x00: 0% , 0x02: + 0.5%, 0x04: 1% , 0x08: 2% ,0x10: 4%; u3.2 value from 0% - 4%. +**/ + UINT8 DlvrSpreadSpectrumPercentage; + +/** Offset 0x0948 - DLVR RFI Enable + Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DlvrRfiEnable; + +/** Offset 0x0949 - Pcore VR Hysteresis time window + 0 is default. Range of PcoreHysteresisWindow from 1ms to 50ms. +**/ + UINT8 PcoreHysteresisWindow; + +/** Offset 0x094A - Ecore VR Hysteresis time window + 0 is default. Range of EcoreHysteresisWindow from 1ms to 50ms. +**/ + UINT8 EcoreHysteresisWindow; + +/** Offset 0x094B - VCCSA Shutdown + Enable/Disable VCCSA Shutdown hopping. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VccsaShutdown; + +/** Offset 0x094C - DLVR RFI Frequency + DLVR RFI Frequency in MHz. 0: 2227 MHz , 1: 2140MHZ. +**/ + UINT16 DlvrRfiFrequency; + +/** Offset 0x094E - DLVR PHASE_SSC Enable + Enable/Disable DLVR PHASE_SSC. 0: Disable. 1:Enable. + $EN_DIS +**/ + UINT8 VrPowerDeliveryDesign; + +/** Offset 0x094F - DLVR PHASE_SSC Enable + Enable/Disable DLVR PHASE_SSC. 0: Disable. 1:Enable. + $EN_DIS +**/ + UINT8 DlvrPhaseSsc; + +/** Offset 0x0950 - Vsys Critical + PCODE MMIO Mailbox: Vsys Critical. 0: Disable; 1: Enable Range is 0-255. +**/ + UINT8 EnableVsysCritical; + +/** Offset 0x0951 - Assertion Deglitch Mantissa + Assertion Deglitch Mantissa, Range is 0-255 +**/ + UINT8 VsysAssertionDeglitchMantissa; + +/** Offset 0x0952 - Assertion Deglitch Exponent + Assertion Deglitch Exponent, Range is 0-255 +**/ + UINT8 VsysAssertionDeglitchExponent; + +/** Offset 0x0953 - De assertion Deglitch Mantissa + De assertion Deglitch Mantissa, Range is 0-255 +**/ + UINT8 VsysDeassertionDeglitchMantissa; + +/** Offset 0x0954 - De assertion Deglitch Exponent + De assertion Deglitch Exponent, Range is 0-255 +**/ + UINT8 VsysDeassertionDeglitchExponent; + +/** Offset 0x0955 +**/ + UINT8 FspmUpdRsvd31; + +/** Offset 0x0956 - VR Fast Vmode ICC Limit support + Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds + to feature disabled (no reactive protection). This value represents the current + threshold where the VR would initiate reactive protection if Fast Vmode is enabled. + The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 IccLimit[6]; + +/** Offset 0x0962 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. + Enable/Disable VR FastVmode; 0: Disable; 1: Enable.For all VR by domain + 0: Disable, 1: Enable +**/ + UINT8 EnableFastVmode[6]; + +/** Offset 0x0968 - Enable/Disable CEP + Control for enabling/disabling CEP (Current Excursion Protection). 0: Disable; 1: Enable + 0: Disable, 1: Enable +**/ + UINT8 CepEnable[6]; + +/** Offset 0x096E +**/ + UINT8 FspmUpdRsvd48[2]; + +/** Offset 0x0970 - Vsys Full Scale + Vsys Full Scale, Range is 0-255000mV +**/ + UINT32 VsysFullScale; + +/** Offset 0x0974 - Vsys Critical Threshold + Vsys Critical Threshold, Range is 0-255000mV +**/ + UINT32 VsysCriticalThreshold; + +/** Offset 0x0978 - Psys Full Scale + Psys Full Scale, Range is 0-255000mV +**/ + UINT32 PsysFullScale; + +/** Offset 0x097C - Psys Critical Threshold + Psys Critical Threshold, Range is 0-255000mV +**/ + UINT32 PsysCriticalThreshold; + +/** Offset 0x0980 - CpuPmVrRsvd + Reserved for CPU Power Mgmt VR Config + $EN_DIS +**/ + UINT8 CpuPmVrRsvd[8]; + +/** Offset 0x0988 - IOE Debug Enable + Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link will keep up and clock + is enabled + $EN_DIS +**/ + UINT8 IoeDebugEn; + +/** Offset 0x0989 - Pmode Clock Enable + Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use + $EN_DIS +**/ + UINT8 PmodeClkEn; + +/** Offset 0x098A - PCH Port80 Route + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + $EN_DIS +**/ + UINT8 PchPort80Route; + +/** Offset 0x098B - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use +**/ + UINT8 GpioOverride; + +/** Offset 0x098C - Pmc Privacy Consent + Enable/Disable Pmc Privacy Consent + $EN_DIS +**/ + UINT8 PmcPrivacyConsent; + +/** Offset 0x098D - DMI ME UMA Root Space Check + DMI IOSF Root Space attribute check for RS3 for cycles targeting MEUMA. + 0: POR, 1: enable, 2: disable +**/ + UINT8 PchTestDmiMeUmaRootSpaceCheck; + +/** Offset 0x098E +**/ + UINT8 FspmUpdRsvd32[2]; + +/** Offset 0x0990 - PMR Size + Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot +**/ + UINT32 DmaBufferSize; + +/** Offset 0x0994 - The policy for VTd driver behavior + BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS +**/ + UINT8 PreBootDmaMask; + +/** Offset 0x0995 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 DmaControlGuarantee; + +/** Offset 0x0996 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x0997 - State of Vtd Capabilities + 0x0=(No operation), BIT0 = 1 (Defeature Nested Support), BIT1 = 1 (Defeature Posted + Interrupt Support) +**/ + UINT8 VtdCapabilityControl; + +/** Offset 0x0998 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; + +/** Offset 0x09BC +**/ + UINT8 FspmUpdRsvd34[4]; + +/** Offset 0x09C0 - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT64 MchBar; + +/** Offset 0x09C8 - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT64 RegBar; + +/** Offset 0x09D0 - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT16 MmioSize; + +/** Offset 0x09D2 - MMIO size adjustment for AUTO mode + Positive number means increasing MMIO size, Negative value means decreasing MMIO + size: 0 (Default)=no change to AUTO mode MMIO size +**/ + UINT16 MmioSizeAdjustment; + +/** Offset 0x09D4 - Temporary address for ApicLocalAddress + The reference code will use this as Temporary address space +**/ + UINT32 ApicLocalAddress; + +/** Offset 0x09D8 - Temporary address for NvmeHcPeiMmioBase + The reference code will use this as Temporary address space +**/ + UINT32 NvmeHcPeiMmioBase; + +/** Offset 0x09DC - Temporary address for NvmeHcPeiMmioLimit + The reference code will use this as Temporary address space +**/ + UINT32 NvmeHcPeiMmioLimit; + +/** Offset 0x09E0 - Temporary address for AhciPeiMmioBase + The reference code will use this as Temporary address space +**/ + UINT32 AhciPeiMmioBase; + +/** Offset 0x09E4 - Temporary address for AhciPeiMmioLimit + The reference code will use this as Temporary address space +**/ + UINT32 AhciPeiMmioLimit; + +/** Offset 0x09E8 - Temporary address for EcExtraIoBase + The reference code will use this as Temporary address space +**/ + UINT16 EcExtraIoBase; + +/** Offset 0x09EA - Temporary address for SioBaseAddress + The reference code will use this as Temporary address space +**/ + UINT16 SioBaseAddress; + +/** Offset 0x09EC - Temporary CfgBar address for VMD + The reference code will use this as Temporary address space +**/ + UINT32 VmdCfgBarBar; + +/** Offset 0x09F0 - System Agent SafBar + Address of System Agent SafBar +**/ + UINT64 SafBar; + +/** Offset 0x09F8 - Enable above 4GB MMIO resource support + Enable/disable above 4GB MMIO resource support + $EN_DIS +**/ + UINT8 EnableAbove4GBMmio; + +/** Offset 0x09F9 - Enable/Disable SA CRID + Enable: SA CRID, Disable (Default): SA CRID + $EN_DIS +**/ + UINT8 CridEnable; + +/** Offset 0x09FA +**/ + UINT8 FspmUpdRsvd35[2]; + +/** Offset 0x09FC - StreamTracer Mode + Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended + when all groups in high verbosity are traced in 'red', Auto: StreamTracer size + 8MB - Recommended when using up to 8 groups red or up to 16 groups in green in + med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB + 0: Disable (Default), 524288: Advanced Tracing , 8192: Auto , 3: User input +**/ + UINT32 StreamTracerMode; + +/** Offset 0x0A00 +**/ + UINT32 StreamTracerSize; + +/** Offset 0x0A04 - Enable/Disable CrashLog Device + Enable or Disable CrashLog/Telemetry Device 0- Disable, 1- Enable + $EN_DIS +**/ + UINT32 CpuCrashLogDevice; + +/** Offset 0x0A08 - StreamTracer physical address + StreamTracer physical address +**/ + UINT64 StreamTracerBase; + +/** Offset 0x0A10 - Temporary MemBar1 address for VMD + StreamTracer physical address +**/ + UINT32 VmdMemBar1Bar; + +/** Offset 0x0A14 - Temporary MemBar2 address for VMD + StreamTracer physical address +**/ + UINT32 VmdMemBar2Bar; + +/** Offset 0x0A18 - Skip override boot mode When Fw Update. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to + BOOT_WITH_FULL_CONFIGURATION in PEI memory init. + $EN_DIS +**/ + UINT8 SiSkipOverrideBootModeWhenFwUpdate; + +/** Offset 0x0A19 +**/ + UINT8 FspmUpdRsvd36; + +/** Offset 0x0A1A - Static Content at 4GB Location + 0 (Default): No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB, + 0x400:1GB, 0x800:2GB, 0xC00:3GB, 0x1000:4GB, 0x2000:8GB + 0: No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB, 0x400:1GB, + 0x800:2GB, 0xC00:3GB, 0x1000:4GB, 0x2000:8GB +**/ + UINT16 StaticContentSizeAt4Gb; + +/** Offset 0x0A1C - Platform Debug Option + Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n + \n + Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n + \n + Enabled Trace power off: TraceHub is powergated, provide setting close to functional + low power state\n + \n + Manual: user needs to configure Advanced Debug Settings manually, aimed at advanced users + 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready, 6:Enable Trace Power-Off, 7:Manual +**/ + UINT8 PlatformDebugOption; + +/** Offset 0x0A1D - TXT CMOS Offset + CMOS Offset for TXT policy data. Default 0x2A +**/ + UINT8 CmosTxtOffset; + +/** Offset 0x0A1E - SiPreMemRsvd + Reserved for SI Pre-Mem + $EN_DIS +**/ + UINT8 SiPreMemRsvd[13]; + +/** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x0A2C - HgSubSystemId + Hybrid Graphics SubSystemId +**/ + UINT16 HgSubSystemId; + +/** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device + 0(Default)=Disabled,1=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortBConfig; + +/** Offset 0x0A2F - Enable or disable HPD of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortAHpd; + +/** Offset 0x0A30 - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x0A31 - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x0A32 - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x0A33 - Enable or disable HPD of DDI port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x0A34 - Enable or disable HPD of DDI port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x0A35 - Enable or disable HPD of DDI port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x0A36 - Enable or disable DDC of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortADdc; + +/** Offset 0x0A37 - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x0A38 - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x0A39 - Enable DDC setting of DDI Port 1 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x0A3A - Enable DDC setting of DDI Port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x0A3B - Enable DDC setting of DDI Port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x0A3C - Enable DDC setting of DDI Port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x0A3D - Oem T12 Dealy Override + Oem T12 Dealy Override. 0(Default)=Disable 1=Enable + $EN_DIS +**/ + UINT8 OemT12DelayOverride; + +/** Offset 0x0A3E +**/ + UINT8 FspmUpdRsvd37[2]; + +/** Offset 0x0A40 - Temporary MMIO address for GMADR + The reference code will use this as Temporary MMIO address space to access GMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to + (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1) +**/ + UINT64 LMemBar; + +/** Offset 0x0A48 - Temporary MMIO address for GTTMMADR + The reference code will use this as Temporary MMIO address space to access GTTMMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr + to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) +**/ + UINT64 GttMmAdr; + +/** Offset 0x0A50 - Delta T12 Power Cycle Delay required in ms + Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate + T12 Delay to max 500ms + 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay +**/ + UINT16 DeltaT12PowerCycleDelay; + +/** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 MemoryBandwidthCompression; + +/** Offset 0x0A53 - Panel Power Enable + Control for enabling/disabling VDD force bit (Required only for early enabling of + eDP panel). 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 PanelPowerEnable; + +/** Offset 0x0A54 - Selection of the primary display device + 3(Default)=AUTO, 0=IGFX, 4=Hybrid Graphics + 3:AUTO, 0:IGFX, 4:HG +**/ + UINT8 PrimaryDisplay; + +/** Offset 0x0A55 - Internal Graphics Data Stolen Memory GSM2 + Size of memory preallocated for internal graphics GSM2. + 0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB, + 11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation +**/ + UINT8 IGpuGsm2Size; + +/** Offset 0x0A56 +**/ + UINT8 FspmUpdRsvd46[2]; + +/** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size + Size of Internal Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x0A5C +**/ + UINT8 FspmUpdRsvd47[4]; + +/** Offset 0x0A60 - Graphics Configuration Ptr + Points to VBT +**/ + UINT64 VbtPtr; + +/** Offset 0x0A68 - SOL Training Message Pointer + Points to SOL Message String +**/ + UINT64 VgaMessage; + +/** Offset 0x0A70 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x0A71 - Control SOL VGA Initialition sequence + Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),, + BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported, + 1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During + MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar), BIT5 + - (0 : VGA Mode 12 16 Color Support, 1 : VGA Mode 12 Monochrome Black and White + Support), BIT6-7 - (0 : No Higher Cd Clock, 1 : 442 MHz, 2 : 461 MHz, 3 : Reserved) + 0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA +**/ + UINT8 VgaInitControl; + +/** Offset 0x0A72 - SOL VGA Graphics Mode 12 LogoPixelHeight + Heigh of VGA Graphics Mode 12 Logo +**/ + UINT16 LogoPixelHeight; + +/** Offset 0x0A74 - SOL VGA Graphics Mode 12 LogoPixelWidth + Width of VGA Graphics Mode 12 Logo +**/ + UINT16 LogoPixelWidth; + +/** Offset 0x0A76 - SOL VGA Graphics Mode 12 Image X Position + X position of Image on Display +**/ + UINT16 LogoXPosition; + +/** Offset 0x0A78 - SOL VGA Graphics Mode 12 Image Pointer + Points to SOL VGA Graphics Graphics 12 Image, VgaPlanarImage200x58[4][58][25] for + 58Hx200W as example, +**/ + UINT64 VgaGraphicsMode12ImagePtr; + +/** Offset 0x0A80 - SOL VGA Graphics Mode 12 Image Y Position + Y position of Image on Display +**/ + UINT16 LogoYPosition; + +/** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x0A83 - IomUsbCDpConfig + Set IomUsbCDpConfig expect 4 values from 0 to 3 + 0:Disabled, 1:IOM_DP, 2:IOM_HDMI, 3: IOM_EDP +**/ + UINT8 IomUsbCDpConfig[4]; + +/** Offset 0x0A87 - TCSS Type C Port 0 + Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, + 7=FULL_FUN + 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN +**/ + UINT8 TcssPort0; + +/** Offset 0x0A88 - TCSS Type C Port 1 + Set TCSS Type C Port 1 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, + 7=FULL_FUN + 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN +**/ + UINT8 TcssPort1; + +/** Offset 0x0A89 - TCSS Type C Port 2 + Set TCSS Type C Port 2 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, + 7=FULL_FUN + 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN +**/ + UINT8 TcssPort2; + +/** Offset 0x0A8A - TCSS Type C Port 3 + Set TCSS Type C Port 3 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, + 7=FULL_FUN + 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN +**/ + UINT8 TcssPort3; + +/** Offset 0x0A8B - TCSS Platform Configuration + Set TCSS Platform Configuration - Retimer Map, TCP0 - Bits[1:0], TCP1 - Bits[3:2], + TCP2 - Bits[5:4], TCP3 - Bits[7:6]; 0=Retimerless, 1=Retimer +**/ + UINT8 TcssPlatConf; + +/** Offset 0x0A8C - TypeC port GPIO setting + GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined + in GpioPinsXXX.h as argument.(XXX is platform name, Ex: Ptl = PantherLake) +**/ + UINT32 IomTypeCPortPadCfg[12]; + +/** Offset 0x0ABC - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x0ABE - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x0AC0 - CNVi DDR RFI Mitigation + Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviDdrRfim; + +/** Offset 0x0AC1 - SOC Trace Hub Mode + Enable/Disable SOC TraceHub + $EN_DIS +**/ + UINT8 SocTraceHubMode; + +/** Offset 0x0AC2 - SOC Trace Hub Memory Region 0 buffer Size + Select size of memory region 0 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 SocTraceHubMemReg0Size; + +/** Offset 0x0AC4 - SOC Trace Hub Memory Region 0 buffer Size + Select size of memory region 1 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 SocTraceHubMemReg1Size; + +/** Offset 0x0AC6 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, + 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, + 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT16 IgdDvmt50PreAlloc; + +/** Offset 0x0AC8 - Internal Graphics + Expect 3 values from 0 to 2 + 2:AUTO, 1:Enable, 0:Disable +**/ + UINT8 InternalGraphics; + +/** Offset 0x0AC9 - Asynchronous ODT + This option configures the Memory Controler Asynchronous ODT control + 0:Enabled, 1:Disabled +**/ + UINT8 AsyncOdtDis; + +/** Offset 0x0ACA - DLL Weak Lock Support + Enables/Disable DLL Weak Lock Support + $EN_DIS +**/ + UINT8 WeaklockEn; + +/** Offset 0x0ACB +**/ + UINT8 FspmUpdRsvd39; + +/** Offset 0x0ACC - Rx DQS Delay Comp Support + Enables/Disable Rx DQS Delay Comp Support + $EN_DIS +**/ + UINT8 RxDqsDelayCompEn; + +/** Offset 0x0ACD +**/ + UINT8 FspmUpdRsvd336[2]; + +/** Offset 0x0ACF - Mrc Failure On Unsupported Dimm + Enables/Disable Mrc Failure On Unsupported Dimm + $EN_DIS +**/ + UINT8 MrcFailureOnUnsupportedDimm; + +/** Offset 0x0AD0 - Fore Single Rank config + Enables/Disable Fore Single Rank config + $EN_DIS +**/ + UINT32 ForceSingleRank; + +/** Offset 0x0AD4 - DynamicMemoryBoost + Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is + an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled. + $EN_DIS +**/ + UINT32 DynamicMemoryBoost; + +/** Offset 0x0AD8 - RealtimeMemoryFrequency + Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected + is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled. + $EN_DIS +**/ + UINT32 RealtimeMemoryFrequency; + +/** Offset 0x0ADC - SelfRefresh IdleTimer + SelfRefresh IdleTimer, Default is 256 +**/ + UINT16 SrefCfgIdleTmr; + +/** Offset 0x0ADE - MC Register Offset + Apply user offsets to select MC registers(Def=Disable) + $EN_DIS +**/ + UINT8 MCREGOFFSET; + +/** Offset 0x0ADF - CA Vref Ctl Offset + Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.CAVref + 0xF4:-12,0xF5:-11, 0xF6:-10, 0xF7:-9, 0xF8:-8, 0xF9:-7, 0xFA:-6, 0xFB:-5, 0xFC:-4, + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, 5:+5, 6:+6, 7:+7, 8:+8, + 9:+9, 10:+10, 11:+11, 12:+12 +**/ + UINT8 CAVrefCtlOffset; + +/** Offset 0x0AE0 - Clk PI Code Offset + Offset to be applied to DDRCLKCH0_CR_DDRCRCLKPICODE.PiSettingRank[0-3] + 0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, + 5:+5, 6:+6 +**/ + UINT8 ClkPiCodeOffset; + +/** Offset 0x0AE1 - RcvEn Offset + Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RcvEn + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3 +**/ + UINT8 RcvEnOffset; + +/** Offset 0x0AE2 - Rx Dqs Offset + Offset to be applied to DDRDATACHX_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3 +**/ + UINT8 RxDqsOffset; + +/** Offset 0x0AE3 - Tx Dq Offset + Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3 +**/ + UINT8 TxDqOffset; + +/** Offset 0x0AE4 - Tx Dqs Offset + Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset + 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3 +**/ + UINT8 TxDqsOffset; + +/** Offset 0x0AE5 - Vref Offset + Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset + 0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, + 5:+5, 6:+6 +**/ + UINT8 VrefOffset; + +/** Offset 0x0AE6 - Controller mask + Controller mask to apply on parameter offset +**/ + UINT8 CntrlrMask; + +/** Offset 0x0AE7 - Channel mask + Channel mask to apply on parameter offset +**/ + UINT8 ChMask; + +/** Offset 0x0AE8 - tRRSG Delta + Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRRSG; + +/** Offset 0x0AE9 - tRRDG Delta + Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRRDG; + +/** Offset 0x0AEA - tRRDR Delta + Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRRDR; + +/** Offset 0x0AEB - tRRDD Delta + Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRRDD; + +/** Offset 0x0AEC - tWRSG Delta + Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tWRSG; + +/** Offset 0x0AED - tWRDG Delta + Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tWRDG; + +/** Offset 0x0AEE - tWRDR Delta + Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWRDR; + +/** Offset 0x0AEF - tWRDD Delta + Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWRDD; + +/** Offset 0x0AF0 - tWWSG Delta + Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tWWSG; + +/** Offset 0x0AF1 - tWWDG Delta + Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed + TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta + range of [-127..127] +**/ + UINT8 tWWDG; + +/** Offset 0x0AF2 - tWWDR Delta + Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWWDR; + +/** Offset 0x0AF3 - tWWDD Delta + Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWWDD; + +/** Offset 0x0AF4 - tRWSG Delta + Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRWSG; + +/** Offset 0x0AF5 - tRWDG Delta + Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [1..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRWDG; + +/** Offset 0x0AF6 - tRWDR Delta + Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRWDR; + +/** Offset 0x0AF7 - tRWDD Delta + Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [1..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRWDD; + +/** Offset 0x0AF8 - MRC Interpreter + Select CMOS location match of DD01 or Ctrl-Break key or force entry + 0:CMOS, 1:Break, 2:Force +**/ + UINT8 Interpreter; + +/** Offset 0x0AF9 - ODT mode + ODT mode + 0:Default, 1:Vtt, 2:Vddq, 3:Vss, 4:Max +**/ + UINT8 IoOdtMode; + +/** Offset 0x0AFA - PerBankRefresh + Control of Per Bank Refresh feature for LPDDR DRAMs + $EN_DIS +**/ + UINT8 PerBankRefresh; + +/** Offset 0x0AFB - Mimic WC display pattern in IPQ + Using for Disable/Enable Mimic WC display pattern in IPQ: 0:Disable, 1:Enable 1 + ACT resources usage, 3:Enable 2 ACT resources usage, 3:Enable 3 ACT resources usage,0xf: + Enable 4 ACT resources usage + 1:1, 3:3, 0xf:0xf, 0:Auto +**/ + UINT8 MimicWcDisaplayInIpq; + +/** Offset 0x0AFC - Fake SAGV + Fake SAGV: 0:Disabled, 1:Enabled + $EN_DIS +**/ + UINT32 FakeSagv; + +/** Offset 0x0B00 - Lock DPR register + Lock DPR register. 0: Platform POR ; 1: Enable; 2: Disable + 0:Platform POR, 1: Enable, 2: Disable +**/ + UINT32 DprLock; + +/** Offset 0x0B04 - Board Stack Up + Board Stack Up: 0=Typical, 1=Freq Limited + 0:Typical, 1:Freq Limited +**/ + UINT8 BoardStackUp; + +/** Offset 0x0B05 - PPR ForceRepair + When Eanble, PPR will force repair some rows many times (90) + $EN_DIS +**/ + UINT8 PprForceRepair; + +/** Offset 0x0B06 - PPR Repair Bank + Deprecated +**/ + UINT8 PprRepairBank; + +/** Offset 0x0B07 - Board Topology + Board Topology: 0=Daisy Chain, 1=Tee. + 0:Daisy Chain, 1:Tee +**/ + UINT8 BoardTopology; + +/** Offset 0x0B08 - SubCh Hash Interleaved Bit + Select the MC Enhanced Channel interleave bit, to set different address bit for + sub channel selection than bit-6 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 SubChHashInterleaveBit; + +/** Offset 0x0B09 +**/ + UINT8 FspmUpdRsvd40; + +/** Offset 0x0B0A - SubCh Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x834 +**/ + UINT16 SubChHashMask; + +/** Offset 0x0B0C - Force CKD in Bypass Mode + Enable/Disable Force CKD in Bypass Mode + $EN_DIS +**/ + UINT8 ForceCkdBypass; + +/** Offset 0x0B0D +**/ + UINT8 FspmUpdRsvd41[3]; + +/** Offset 0x0B10 - Disable Zq + Enable/Disable Zq Calibration: 0:Enabled, 1:Disabled + $EN_DIS +**/ + UINT32 DisableZq; + +/** Offset 0x0B14 - Replicate SAGV + Replicate SAGV: 0:Disabled, 1:Enabled + $EN_DIS +**/ + UINT32 ReplicateSagv; + +/** Offset 0x0B18 - Adjust wck mode + Adjust wck mode: 0:safe mode, 1:manual mode, 2:dynamic mode, 3:Default + 0:safe mode, 1:manual mode, 2:dynamic mode, 3:Default +**/ + UINT8 AdjustWckMode; + +/** Offset 0x0B19 - Control MC/PMA telemetry + Control MC/PMA telemetry: 0: Default, 1: Enable, 2: Disable + 0: Default, 1: Enable, 2: Disable +**/ + UINT8 TelemetryControl; + +/** Offset 0x0B1A - PHclk\Qclk SPINE gating Control + PHclk\Qclk SPINE gating Control: 0:Disabled, 1:Enabled + $EN_DIS +**/ + UINT8 SpineAndPhclkGateControl; + +/** Offset 0x0B1B - SpineGating per lpmode + SpineGatePerLpmode[0]:Lpmode0.5, SpineGatePerLpmode[1]:Lpmode2, SpineGatePerLpmode[2]:Lpmode3, + SpineGatePerLpmode[3]:Lpmode4 +**/ + UINT8 SpineGatePerLpmode; + +/** Offset 0x0B1C - PhClkGating control per lpmode + PhclkGatePerLpmode[0]:Lpmode0.5, PhclkGatePerLpmode[1]:Lpmode1, PhclkGatePerLpmode[2]:Lpmode2, + PhclkGatePerLpmode[3]:Lpmode3, PhclkGatePerLpmode[4]:Lpmode4 +**/ + UINT8 PhclkGatePerLpmode; + +/** Offset 0x0B1D - DFI Control after cold boot + Disable Switch DFI Control to MC after cold boot: 0(Default)=switch DFI to MC, 1=Keep + with PHY/MPTU + $EN_DIS +**/ + UINT8 DisableSwitchDfiToMc; + +/** Offset 0x0B1E - Enable/Disable SmbusPostcode + Disable (Default): Postcode via Port80, Enable: Postcode via Smbus + $EN_DIS +**/ + UINT8 SmbusPostCodeEnable; + +/** Offset 0x0B1F - SmbusPostcode Address + Slave address for Smbus postcode device +**/ + UINT8 SmbusPostCodeAddress; + +/** Offset 0x0B20 - SmbusPostcode Command + Command value for Smbus postcode device +**/ + UINT8 SmbusPostCodeCommand; + +/** Offset 0x0B21 - Channel to CKD QCK Mapping + Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1 +**/ + UINT8 ChannelToCkdQckMapping[8]; + +/** Offset 0x0B29 - DDRIO Clock to CKD DIMM + Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1 +**/ + UINT8 PhyClockToCkdDimm[8]; + +/** Offset 0x0B31 - CKD Address Table + Specify CKD Address table for all DIMMs +**/ + UINT8 CkdAddressTable[16]; + +/** Offset 0x0B41 - Single VDD2 Rail + LP5x VDD2 rail: 0: Dual rail (E-DVFSC is possible), 1: Single rail(No E-DVFSC; VDD2L == VDD2H) + $EN_DIS +**/ + UINT8 SingleVdd2Rail; + +/** Offset 0x0B42 - VDD2 Voltage + Voltage is multiple of 5mV where 0 means Auto. +**/ + UINT16 Vdd2HVoltage; + +/** Offset 0x0B44 - VDD1 Voltage + Voltage is multiple of 5mV where 0 means Auto. +**/ + UINT16 Vdd1Voltage; + +/** Offset 0x0B46 - VDD2L Voltage Override + Voltage is multiple of 5mV where 0 means Auto. +**/ + UINT16 Vdd2LVoltage; + +/** Offset 0x0B48 - VDDQ Voltage Override + Voltage is multiple of 5mV where 0 means Auto. +**/ + UINT16 VddqVoltage; + +/** Offset 0x0B4A +**/ + UINT8 FspmUpdRsvd50[6]; + +/** Offset 0x0B50 - Graphics Mode 12 Font Pointer + Pointer to VGA Mode 12 Font Data (8x16 character set).\n + Format: UINT8 array[256][16] where each character is 16 bytes (16 rows of 8 pixels).\n + Must be provided if VGA Mode 12 is enabled. +**/ + UINT64 GraphicsMode12FontPtr; + +/** Offset 0x0B58 - MRC Error Key Value Table Pointer + Pointer to MRC Error Key Value Table. Table maps MRC error codes to error message + strings for display during memory init. See FSP_MRC_ERROR_KEY_VALUE_TABLE. +**/ + UINT64 MrcErrorKeyValueTablePtr; + +/** Offset 0x0B60 +**/ + UINT8 FspmUpdRsvd49[5]; + +/** Offset 0x0B65 +**/ + UINT8 ReservedFspmUpd[3]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH2_UPD FspmArchUpd; + +/** Offset 0x0060 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0B68 +**/ + UINT8 FspmRsvd3834[6]; + +/** Offset 0x0B6E +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspsUpd.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspsUpd.h new file mode 100644 index 00000000..487211a2 --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FspsUpd.h @@ -0,0 +1,3943 @@ +/** @file + +Copyright (c) 2026, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0040 - BgpdtHash[6] + BgpdtHash values +**/ + UINT64 BgpdtHash[6]; + +/** Offset 0x0070 - BiosGuardAttr + BiosGuardAttr default values +**/ + UINT32 BiosGuardAttr; + +/** Offset 0x0074 +**/ + UINT8 FspsUpdRsvd0[4]; + +/** Offset 0x0078 - BiosGuardModulePtr + BiosGuardModulePtr default values +**/ + UINT64 BiosGuardModulePtr; + +/** Offset 0x0080 - EcProvisionEav + EcProvisionEav function pointer. \n + @code typedef EFI_STATUS (EFIAPI *EC_PROVISION_EAV) (IN UINT32 Eav, OUT UINT8 + *ReturnValue); @endcode +**/ + UINT64 EcProvisionEav; + +/** Offset 0x0088 - EcBiosGuardCmdLock + EcBiosGuardCmdLock function pointer. \n + @code typedef EFI_STATUS (EFIAPI *EC_CMD_LOCK) (OUT UINT8 *ReturnValue); @endcode +**/ + UINT64 EcBiosGuardCmdLock; + +/** Offset 0x0090 - PCH eSPI Host and Device BME enabled + PCH eSPI Host and Device BME enabled + $EN_DIS +**/ + UINT8 PchEspiBmeHostDeviceEnabled; + +/** Offset 0x0091 - PCH eSPI Link Configuration Lock (SBLCL) + Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target + addresseses from range 0x0 - 0x7FF + $EN_DIS +**/ + UINT8 PchEspiLockLinkConfiguration; + +/** Offset 0x0092 - Enable Host C10 reporting through eSPI + Enable/disable Host C10 reporting to Device via eSPI Virtual Wire. + $EN_DIS +**/ + UINT8 PchEspiHostC10ReportEnable; + +/** Offset 0x0093 - Espi Lgmr Memory Range decode + This option enables or disables espi lgmr + $EN_DIS +**/ + UINT8 PchEspiLgmrEnable; + +/** Offset 0x0094 - PCH eSPI PmHAE + This option enables or disables espi lgmr + $EN_DIS +**/ + UINT8 PchEspiPmHAE; + +/** Offset 0x0095 - PCH eSPI HideNonFatalErrors + This option enables or disables espi lgmr + $EN_DIS +**/ + UINT8 PchEspiHideNonFatalErrors; + +/** Offset 0x0096 - PCH eSPI NmiEnableCs1 + Set this bit to enable eSPI NMI VW events to be processed by the SOC + $EN_DIS +**/ + UINT8 PchEspiNmiEnableCs1; + +/** Offset 0x0097 +**/ + UINT8 FspsUpdRsvd1; + +/** Offset 0x0098 - CpuBistData + Pointer CPU BIST Data +**/ + UINT64 CpuBistData; + +/** Offset 0x00A0 - CpuMpPpi + Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. +**/ + UINT64 CpuMpPpi; + +/** Offset 0x00A8 - Enable/Disable CrashLog + Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x00A9 +**/ + UINT8 FspsUpdRsvd2[3]; + +/** Offset 0x00AC - StreamTracer Mode + Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended + when all groups in high verbosity are traced in 'red', Auto: StreamTracer size + 8MB - Recommended when using up to 8 groups red or up to 16 groups in green in + med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB + 0: Disable (Default), 524288: Advanced Tracing , 8192: Auto , 3: User input +**/ + UINT32 StreamTracerMode; + +/** Offset 0x00B0 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT64 MicrocodeRegionBase; + +/** Offset 0x00B8 - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT64 MicrocodeRegionSize; + +/** Offset 0x00C0 - Enable or Disable TXT + Enables utilization of additional hardware capabilities provided by Intel (R) Trusted + Execution Technology. Changes require a full power cycle to take effect. 0: + Disable, 1: Enable. + $EN_DIS +**/ + UINT8 TxtEnable; + +/** Offset 0x00C1 - PpinSupport to view Protected Processor Inventory Number + PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn + off this feature. When 'PPIN Enable Mode' is selected, this shows second option + where feature can be enabled based on EOM (End of Manufacturing) flag or it is + always enabled + 0: Disable, 1: Enable, 2: Auto +**/ + UINT8 PpinSupport; + +/** Offset 0x00C2 - Advanced Encryption Standard (AES) feature + Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 AesEnable; + +/** Offset 0x00C3 - AvxDisable + Enable/Disable the AVX and AVX2 Instructions + 0: Enable, 1: Disable +**/ + UINT8 AvxDisable; + +/** Offset 0x00C4 - X2ApicEnable + Enable/Disable X2APIC Operating Mode. When this option is configured as 'Enabled', + 'VT-d' option must be 'Enabled'. + $EN_DIS +**/ + UINT8 X2ApicEnable; + +/** Offset 0x00C5 - P-state ratios for max 16 version of custom P-state table + P-state ratios for max 16 version of custom P-state table. This table is used for + OS versions limited to a max of 16 P-States. If the first entry of this table is + 0, or if Number of Entries is 16 or less, then this table will be ignored, and + up to the top 16 values of the StateRatio table will be used instead. Valid Range + of each entry is 0 to 0x7F +**/ + UINT8 StateRatioMax16[16]; + +/** Offset 0x00D5 - Enable or Disable Intel SpeedStep Technology + Allows more than two frequency ranges to be supported. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Eist; + +/** Offset 0x00D6 - Enable or Disable Energy Efficient P-state + Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access + to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support + for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS + MSR and CPUID Function will read 1 indicating Energy Efficient policy setting is + supported. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientPState; + +/** Offset 0x00D7 - Enable or Disable Energy Efficient Turbo + Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically + lower the turbo frequency to increase efficiency. Recommended only to disable in + overclocking situations where turbo frequency must remain constant. Otherwise, + leave enabled. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientTurbo; + +/** Offset 0x00D8 - Enable or Disable T states + Enable or Disable T states; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TStates; + +/** Offset 0x00D9 - Enable or Disable Thermal Reporting + Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 EnableAllThermalFunctions; + +/** Offset 0x00DA - Enable or Disable CPU power states (C-states) + Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not + 100% utilized. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x00DB - Configure C-State Configuration Lock + Configure MSR to CFG Lock bit. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PmgCstCfgCtrlLock; + +/** Offset 0x00DC - Enable or Disable Package Cstate Demotion + Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateDemotion; + +/** Offset 0x00DD - Enable or Disable Package Cstate UnDemotion + Enable or Disable Package C-State Un-Demotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateUnDemotion; + +/** Offset 0x00DE - Enable or Disable CState-Pre wake + Disable - to disable the Cstate Pre-Wake. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 CStatePreWake; + +/** Offset 0x00DF - Enable or Disable TimedMwait Support. + Enable or Disable TimedMwait Support. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 TimedMwait; + +/** Offset 0x00E0 - Set the Max Pkg Cstate + Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. + Auto: Initializes to deepest available Package C State Limit. Valid values 0 - + C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 - + CPU Default, 255 - Auto +**/ + UINT8 PkgCStateLimit; + +/** Offset 0x00E1 - ForcePr Demotion Algorithm configuration + ForcePr Demotion Algorithm configuration. 0: Disable; 1: Enable + 0: Disable, 1: Enable +**/ + UINT8 ForcePrDemotion; + +/** Offset 0x00E2 - VrAlert Demotion Algorithm configuration + VrAlert Demotion Algorithm configuration. 0: Disable; 1: Enable + 0: Disable, 1: Enable +**/ + UINT8 VrAlertDemotion; + +/** Offset 0x00E3 - Interrupt Redirection Mode Select + Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1: + Round robin; 2: Hash vector; 7: No change. +**/ + UINT8 PpmIrmSetting; + +/** Offset 0x00E4 - Turbo Mode + Enable/Disable processor Turbo Mode. 0:disable, 1: Enable + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x00E5 - Power Floor PCIe Gen Downgrade + SoC can downgrade PCIe gen speed to lower SoC floor power (Default enabled). 0: + Disable: Reduction in PCIe gen speed will not be used by SoC., 1: Enable + $EN_DIS +**/ + UINT8 PowerFloorPcieGenDowngrade; + +/** Offset 0x00E6 - P-state ratios for custom P-state table + P-state ratios for custom P-state table. NumberOfEntries has valid range between + 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] + are configurable. Valid Range of each entry is 0 to 0x7F +**/ + UINT8 StateRatio[40]; + +/** Offset 0x010E - Custom Ratio State Entries + The number of custom ratio state entries, ranges from 0 to 40 for a valid custom + ratio table. Sets the number of custom P-states. At least 2 states must be present +**/ + UINT8 NumberOfEntries; + +/** Offset 0x010F - Max P-State Ratio + Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F +**/ + UINT8 MaxRatio; + +/** Offset 0x0110 - Boot frequency + Select the performance state that the BIOS will set starting from reset vector. + 0: Maximum battery performance. 1: Maximum non-turbo performance. 2: Turbo performance + 0:0, 1:1, 2:2 +**/ + UINT8 BootFrequency; + +/** Offset 0x0111 - Turbo settings Lock + Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT + MSR will be locked and a reset will be required to unlock the register. 0: Disable; + 1: Enable + $EN_DIS +**/ + UINT8 TurboPowerLimitLock; + +/** Offset 0x0112 - FastMsrHwpReq + 0: Disable; 1: Enable; + $EN_DIS +**/ + UINT8 EnableFastMsrHwpReq; + +/** Offset 0x0113 - Turbo Ratio Limit Ratio array + Performance-core Turbo Ratio Limit Ratio0-7 (TRLR) defines the turbo ratio (max + is 85 in normal mode and 120 in core extension mode). Ratio[0]: This Turbo Ratio + Limit Ratio0 must be greater than or equal all other ratio values. If this value + is invalid, thn set all other active cores to minimum. Otherwise, align the Ratio + Limit to 0. Please check each active cores. Ratio[1~7]: This Turbo Ratio Limit + Ratio1 must be <= to Turbo Ratio Limit Ratio0~6. +**/ + UINT8 TurboRatioLimitRatio[8]; + +/** Offset 0x011B - Turbo Ratio Limit Num Core array + Performance-core Turbo Ratio Limit Core0~7 defines the core range, the turbo ratio + is defined in Turbo Ratio Limit Ratio0~7. If value is zero, this entry is ignored. +**/ + UINT8 TurboRatioLimitNumCore[8]; + +/** Offset 0x0123 - ATOM Turbo Ratio Limit Ratio array + Efficient-core Turbo Ratio Limit Ratio0-7 defines the turbo ratio (max is 85 irrespective + of the core extension mode), the core range is defined in E-core Turbo Ratio Limit + CoreCount0-7. +**/ + UINT8 AtomTurboRatioLimitRatio[8]; + +/** Offset 0x012B - ATOM Turbo Ratio Limit Num Core array + Efficient-core Turbo Ratio Limit CoreCount0-7 defines the core range, the turbo + ratio is defined in E-core Turbo Ratio Limit Ratio0-7. If value is zero, this entry + is ignored. +**/ + UINT8 AtomTurboRatioLimitNumCore[8]; + +/** Offset 0x0133 - Race To Halt + Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency + in order to enter pkg C-State faster to reduce overall power. 0: Disable; 1: + Enable + $EN_DIS +**/ + UINT8 RaceToHalt; + +/** Offset 0x0134 - Enable or Disable C1 Cstate Demotion + Enable or Disable C1 Cstate Auto Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateAutoDemotion; + +/** Offset 0x0135 - Enable or Disable C1 Cstate UnDemotion + Enable or Disable C1 Cstate Un-Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateUnDemotion; + +/** Offset 0x0136 - Minimum Ring ratio limit override + Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MinRingRatioLimit; + +/** Offset 0x0137 - Maximum Ring ratio limit override + Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MaxRingRatioLimit; + +/** Offset 0x0138 - Resource Priority Feature + Enable/Disable Resource Priority Feature. Enable/Disable; 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 EnableRp; + +/** Offset 0x0139 - Enable or Disable HWP + Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the + CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; 1: + Enable; + $EN_DIS +**/ + UINT8 Hwp; + +/** Offset 0x013A - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 HwpInterruptControl; + +/** Offset 0x013B - Enable or Disable HwP Autonomous Per Core P State OS control + Disable Autonomous PCPS Autonomous will request the same value for all cores all + the time. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoPerCorePstate; + +/** Offset 0x013C - Enable or Disable HwP Autonomous EPP Grouping + Enable EPP grouping Autonomous will request the same values for all cores with same + EPP. Disable EPP grouping autonomous will not necessarily request same values for + all cores with same EPP. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoEppGrouping; + +/** Offset 0x013D - Dynamic Efficiency Control + Enable or Disable SoC to control energy efficiency targets autonomously, regardless + of EPP, EPB and other SW inputs. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableDynamicEfficiencyControl; + +/** Offset 0x013E - Misc Power Management MSR Lock + Enable/Disable HWP Lock support in Misc Power Management MSR. 0: Disable, 1: + Enable + $EN_DIS +**/ + UINT8 HwpLock; + +/** Offset 0x013F - Power Floor Managment for SOC + Option to disable Power Floor Managment for SOC. Disabling this might effectively + raise power floor of the SoC and may lead to stability issues. 0: Disable, 1: + Enable + $EN_DIS +**/ + UINT8 PowerFloorManagement; + +/** Offset 0x0140 - Power Floor Disaplay Disconnect + SoC can disconnect secondary/external display to lower SoC floor power (Default + disabled). 0: Disable: Display disconnect will not be used by SoC., 1: Enable + $EN_DIS +**/ + UINT8 PowerFloorDisplayDisconnect; + +/** Offset 0x0141 - Memory size per thread allocated for Processor Trace + Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment + and size in bytes per thread, from 4KB to 128MB.\n + 0xff:none , 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k, + 0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M +**/ + UINT8 ProcessorTraceMemSize; + +/** Offset 0x0142 - Enable or Disable MLC Streamer Prefetcher + Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MlcStreamerPrefetcher; + +/** Offset 0x0143 - Enable or Disable MLC Spatial Prefetcher + Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 MlcSpatialPrefetcher; + +/** Offset 0x0144 - Enable or Disable Monitor /MWAIT instructions + Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner + should not set in MWAIT Loop. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MonitorMwaitEnable; + +/** Offset 0x0145 - Enable or Disable initialization of machine check registers + Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MachineCheckEnable; + +/** Offset 0x0146 - Control on Processor Trace output scheme + Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. + 0: Single Range Output, 1: ToPA Output +**/ + UINT8 ProcessorTraceOutputScheme; + +/** Offset 0x0147 - Enable or Disable Processor Trace feature + Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ProcessorTraceEnable; + +/** Offset 0x0148 - Processor trace enabled for Bsp only or all cores + Processor trace enabled for Bsp only or all cores; 0: all cores; 1: Bsp only. + 0: all cores, 1: Bsp only +**/ + UINT8 ProcessorTraceBspOnly; + +/** Offset 0x0149 - Enable/Disable processor trace Timing Packet + Enable/Disable collocting processor trace performance (CYC, TSC); 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 ProcessorTraceTimingPacket; + +/** Offset 0x014A - Enable or Disable Three Strike Counter + Enable (default): Three Strike counter will be incremented. Disable: Prevents Three + Strike counter from incrementing; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ThreeStrikeCounter; + +/** Offset 0x014B - UFS enable/disable + Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller + 0 and (0,1) to enable controller 1 + $EN_DIS +**/ + UINT8 UfsEnable[2]; + +/** Offset 0x014D - UFS Inline Encryption enable/disable + Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0) + to enable Inline Encryption for controller 0 and (0, 1) to enable Inline Encryption + for controller 1 + $EN_DIS +**/ + UINT8 UfsInlineEncryption[2]; + +/** Offset 0x014F - UFS Connection Status + UFS Connection Status, One byte for each Controller - (1,0) to UFS connected to + controller 0 and (0,1) to UFS connected to controller 1 + $EN_DIS +**/ + UINT8 UfsDeviceConnected[2]; + +/** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4 + Enable/Disable PCIe tunneling for USB4, default is enable + $EN_DIS +**/ + UINT8 ITbtPcieTunnelingForUsb4; + +/** Offset 0x0152 +**/ + UINT8 FspsUpdRsvd3[2]; + +/** Offset 0x0154 - ITBTForcePowerOn Timeout value + ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. + 100 = 100 ms. +**/ + UINT16 ITbtForcePowerOnTimeoutInMs; + +/** Offset 0x0156 - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x0158 - ITBT DMA LTR + TCSS DMA1, DMA2 LTR value +**/ + UINT16 ITbtDmaLtr[2]; + +/** Offset 0x015C - ITbt Usb4CmMode value + ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM +**/ + UINT8 Usb4CmMode; + +/** Offset 0x015D +**/ + UINT8 FspsUpdRsvd4[11]; + +/** Offset 0x0168 - FSPS Validation + Point to FSPS Validation configuration structure +**/ + UINT64 FspsValidationPtr; + +/** Offset 0x0170 - IEH Mode + Integrated Error Handler Mode, 0: Bypass, 1: Enable + 0: Bypass, 1:Enable +**/ + UINT8 IehMode; + +/** Offset 0x0171 - RTC BIOS Interface Lock + Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. + $EN_DIS +**/ + UINT8 RtcBiosInterfaceLock; + +/** Offset 0x0172 - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x0173 - AMT Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. + $EN_DIS +**/ + UINT8 AmtEnabled; + +/** Offset 0x0174 - SOL Switch + Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. + Setting is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 AmtSolEnabled; + +/** Offset 0x0175 - WatchDog Timer Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting + is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 WatchDogEnabled; + +/** Offset 0x0176 - OS Timer + 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerOs; + +/** Offset 0x0178 - BIOS Timer + 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerBios; + +/** Offset 0x017A - Iax Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable Iax functionality. + $EN_DIS +**/ + UINT8 IaxEnable; + +/** Offset 0x017B +**/ + UINT8 FspsUpdRsvd5; + +/** Offset 0x017C - ISH GP GPIO Pin Muxing + Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER +**/ + UINT32 IshGpGpioPinMuxing[12]; + +/** Offset 0x01AC - ISH UART Rx Pin Muxing + Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_* +**/ + UINT32 IshUartRxPinMuxing[3]; + +/** Offset 0x01B8 - ISH UART Tx Pin Muxing + Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_* +**/ + UINT32 IshUartTxPinMuxing[3]; + +/** Offset 0x01C4 - ISH UART Rts Pin Muxing + Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values. +**/ + UINT32 IshUartRtsPinMuxing[3]; + +/** Offset 0x01D0 - ISH UART Rts Pin Muxing + Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values. +**/ + UINT32 IshUartCtsPinMuxing[3]; + +/** Offset 0x01DC - ISH I2C SDA Pin Muxing + Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values. +**/ + UINT32 IshI2cSdaPinMuxing[3]; + +/** Offset 0x01E8 - ISH I2C SCL Pin Muxing + Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values. +**/ + UINT32 IshI2cSclPinMuxing[3]; + +/** Offset 0x01F4 - ISH SPI MOSI Pin Muxing + Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values. +**/ + UINT32 IshSpiMosiPinMuxing[2]; + +/** Offset 0x01FC - ISH SPI MISO Pin Muxing + Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values. +**/ + UINT32 IshSpiMisoPinMuxing[2]; + +/** Offset 0x0204 - ISH SPI CLK Pin Muxing + Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values. +**/ + UINT32 IshSpiClkPinMuxing[2]; + +/** Offset 0x020C - ISH SPI CS#N Pin Muxing + Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS_* for possible + values. N-SPI number, 0-1. +**/ + UINT32 IshSpiCsPinMuxing[4]; + +/** Offset 0x021C - ISH GP GPIO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination + respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index + 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31 +**/ + UINT8 IshGpGpioPadTermination[12]; + +/** Offset 0x0228 - ISH UART Rx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 + Rx, and so on. +**/ + UINT8 IshUartRxPadTermination[3]; + +/** Offset 0x022B - ISH UART Tx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 + Tx, and so on. +**/ + UINT8 IshUartTxPadTermination[3]; + +/** Offset 0x022E - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 + Rts, and so on. +**/ + UINT8 IshUartRtsPadTermination[3]; + +/** Offset 0x0231 - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 + Cts, and so on. +**/ + UINT8 IshUartCtsPadTermination[3]; + +/** Offset 0x0234 - ISH I2C SDA Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, + and so on. +**/ + UINT8 IshI2cSdaPadTermination[3]; + +/** Offset 0x0237 - ISH I2C SCL Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, + and so on. +**/ + UINT8 IshI2cSclPadTermination[3]; + +/** Offset 0x023A - ISH SPI MOSI Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 + Mosi, and so on. +**/ + UINT8 IshSpiMosiPadTermination[2]; + +/** Offset 0x023C - ISH SPI MISO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 + Miso, and so on. +**/ + UINT8 IshSpiMisoPadTermination[2]; + +/** Offset 0x023E - ISH SPI CLK Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, + and so on. +**/ + UINT8 IshSpiClkPadTermination[2]; + +/** Offset 0x0240 - ISH SPI CS#N Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination + respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 + Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3 +**/ + UINT8 IshSpiCsPadTermination[4]; + +/** Offset 0x0244 - Enable PCH ISH SPI Cs#N pins assigned + Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs + number: 0-1 +**/ + UINT8 PchIshSpiCsEnable[4]; + +/** Offset 0x0248 - Enable PCH ISH SPI Cs0 pins assigned + Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiCs0Enable[1]; + +/** Offset 0x0249 - Enable PCH ISH SPI pins assigned + Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiEnable[1]; + +/** Offset 0x024A - Enable PCH ISH UART pins assigned + Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshUartEnable[2]; + +/** Offset 0x024C - Enable PCH ISH I2C pins assigned + Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI2cEnable[3]; + +/** Offset 0x024F - Enable PCH ISH GP pins assigned + Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshGpEnable[12]; + +/** Offset 0x025B - PCH ISH PDT Unlock Msg + 0: False; 1: True. + $EN_DIS +**/ + UINT8 PchIshPdtUnlock; + +/** Offset 0x025C - PCH ISH MSI Interrupts + 0: False; 1: True. + $EN_DIS +**/ + UINT8 PchIshMsiInterrupt; + +/** Offset 0x025D - End of Post message + Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): + EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE + 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved +**/ + UINT8 EndOfPostMessage; + +/** Offset 0x025E - D0I3 Setting for HECI Disable + Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all + HECI devices + $EN_DIS +**/ + UINT8 DisableD0I3SettingForHeci; + +/** Offset 0x025F - Mctp Broadcast Cycle + Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MctpBroadcastCycle; + +/** Offset 0x0260 - ME Unconfig on RTC clear + 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. + 2: Cmos is clear, status unkonwn. 3: Reserved + 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos + is clear, 3: Reserved +**/ + UINT8 MeUnconfigOnRtcClear; + +/** Offset 0x0261 - CSE Data Resilience Support + 0: Disable CSE Data Resilience Support. 1: Enable CSE Data Resilience Support. + 2: Enable CSE Data Resilience but defer to DXE. + $EN_DIS +**/ + UINT8 CseDataResilience; + +/** Offset 0x0262 - PSE EOM Flow Control + 0: Disable PSE EOM Flow. 1: Enable PSE EOM Flow. + $EN_DIS +**/ + UINT8 PseEomFlowEnable; + +/** Offset 0x0263 - ISH I3C SDA Pin Muxing + Select ISH I3C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SDA_* for possible values. +**/ + UINT8 IshI3cSdaPinMuxing[8]; + +/** Offset 0x026B - ISH I3C SCL Pin Muxing + Select ISH I3C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SCL_* for possible values. +**/ + UINT8 IshI3cSclPinMuxing[8]; + +/** Offset 0x0273 - ISH I3C SDA Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, + and so on. +**/ + UINT8 IshI3cSdaPadTermination[2]; + +/** Offset 0x0275 - ISH I3C SCL Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, + and so on. +**/ + UINT8 IshI3cSclPadTermination[2]; + +/** Offset 0x0277 - Enable PCH ISH I3C pins assigned + Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI3cEnable[2]; + +/** Offset 0x0279 +**/ + UINT8 FspsUpdRsvd6[3]; + +/** Offset 0x027C - Power button debounce configuration + Debounce time for PWRBTN in microseconds. For values not supported by HW, they will + be rounded down to closest supported on. 0: disable, 250-1024000us: supported range +**/ + UINT32 PmcPowerButtonDebounce; + +/** Offset 0x0280 - PCH USB2 PHY Power Gating enable + 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY + Sus Well PG + $EN_DIS +**/ + UINT8 PmcUsb2PhySusPgEnable; + +/** Offset 0x0281 - VRAlert# Pin + When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling + to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchPmVrAlert; + +/** Offset 0x0282 - ModPHY SUS Power Domain Dynamic Gating + Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on + PCH-H. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcModPhySusPgEnable; + +/** Offset 0x0283 - V1p05-PHY supply external FET control + Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05PhyExtFetControlEn; + +/** Offset 0x0284 - V1p05-IS supply external FET control + Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05IsExtFetControlEn; + +/** Offset 0x0285 - PCH Pm PME_B0_S5_DIS + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. + $EN_DIS +**/ + UINT8 PchPmPmeB0S5Dis; + +/** Offset 0x0286 - PCH Pm Wol Enable Override + Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. + $EN_DIS +**/ + UINT8 PchPmWolEnableOverride; + +/** Offset 0x0287 - PCH Pm WoW lan Enable + Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanEnable; + +/** Offset 0x0288 - PCH Pm Slp S3 Min Assert + SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. +**/ + UINT8 PchPmSlpS3MinAssert; + +/** Offset 0x0289 - PCH Pm Slp S4 Min Assert + SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. +**/ + UINT8 PchPmSlpS4MinAssert; + +/** Offset 0x028A - PCH Pm Slp Sus Min Assert + SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. +**/ + UINT8 PchPmSlpSusMinAssert; + +/** Offset 0x028B - PCH Pm Slp A Min Assert + SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. +**/ + UINT8 PchPmSlpAMinAssert; + +/** Offset 0x028C - PCH Pm Slp Strch Sus Up + Enable SLP_X Stretching After SUS Well Power Up. + $EN_DIS +**/ + UINT8 PchPmSlpStrchSusUp; + +/** Offset 0x028D - PCH Pm Slp Lan Low Dc + Enable/Disable SLP_LAN# Low on DC Power. + $EN_DIS +**/ + UINT8 PchPmSlpLanLowDc; + +/** Offset 0x028E - PCH Pm Pwr Btn Override Period + PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. +**/ + UINT8 PchPmPwrBtnOverridePeriod; + +/** Offset 0x028F - PCH Pm Disable Native Power Button + Power button native mode disable. + $EN_DIS +**/ + UINT8 PchPmDisableNativePowerButton; + +/** Offset 0x0290 - PCH Pm ME_WAKE_STS + Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmMeWakeSts; + +/** Offset 0x0291 - PCH Pm WOL_OVR_WK_STS + Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmWolOvrWkSts; + +/** Offset 0x0292 - PCH Pm Reset Power Cycle Duration + Could be customized in the unit of second. Please refer to EDS for all support settings. + 0 is default, 1 is 1 second, 2 is 2 seconds, ... +**/ + UINT8 PchPmPwrCycDur; + +/** Offset 0x0293 - PCH Pm Pcie Pll Ssc + Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No + BIOS override. +**/ + UINT8 PchPmPciePllSsc; + +/** Offset 0x0294 - Enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have + huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer + emulation must be enabled, and WDAT table must not be exposed to the OS. + $EN_DIS +**/ + UINT8 EnableTcoTimer; + +/** Offset 0x0295 - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x0296 - Pmc Cpu C10 Gate Pin Enable + Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO + and VccSTG rails instead of SLP_S0# pin. + $EN_DIS +**/ + UINT8 PmcCpuC10GatePinEnable; + +/** Offset 0x0297 - OS IDLE Mode Enable + Enable/Disable OS Idle Mode + $EN_DIS +**/ + UINT8 PmcOsIdleEnable; + +/** Offset 0x0298 - S0ix Auto-Demotion + Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. + $EN_DIS +**/ + UINT8 PchS0ixAutoDemotion; + +/** Offset 0x0299 - Latch Events C10 Exit + When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are + captured on C10 exit (instead of C10 entry which is default) + $EN_DIS +**/ + UINT8 PchPmLatchEventsC10Exit; + +/** Offset 0x029A - PCH Energy Reporting + Disable/Enable PCH to CPU energy report feature. + $EN_DIS +**/ + UINT8 PchPmDisableEnergyReport; + +/** Offset 0x029B - Low Power Mode Enable/Disable config mask + Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds + to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. +**/ + UINT8 PmcLpmS0ixSubStateEnableMask; + +/** Offset 0x029C - PCH PMC ER Debug mode + Disable/Enable Energy Reporting Debug Mode. + $EN_DIS +**/ + UINT8 PchPmErDebugMode; + +/** Offset 0x029D - PMC C10 dynamic threshold dajustment enable + Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs + $EN_DIS +**/ + UINT8 PmcC10DynamicThresholdAdjustment; + +/** Offset 0x029E - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x029F - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x02A0 - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x02A1 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x02A2 - PCH Flash Protection Ranges Write Enble + Write or erase is blocked by hardware. +**/ + UINT8 PchWriteProtectionEnable[5]; + +/** Offset 0x02A7 - PCH Flash Protection Ranges Read Enble + Read is blocked by hardware. +**/ + UINT8 PchReadProtectionEnable[5]; + +/** Offset 0x02AC - PCH Protect Range Limit + Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for + limit comparison. +**/ + UINT16 PchProtectedRangeLimit[5]; + +/** Offset 0x02B6 - PCH Protect Range Base + Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. +**/ + UINT16 PchProtectedRangeBase[5]; + +/** Offset 0x02C0 - PCIe PTM enable/disable + Enable/disable Precision Time Measurement for PCIE Root Ports. +**/ + UINT8 PciePtm[28]; + +/** Offset 0x02DC - PCH PCIe root port connection type + 0: built-in device, 1:slot +**/ + UINT8 PcieRpSlotImplemented[28]; + +/** Offset 0x02F8 - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability +**/ + UINT8 PcieRpAcsEnabled[28]; + +/** Offset 0x0314 - PCIE RP Clock Power Management + Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal + can still be controlled by L1 PM substates mechanism +**/ + UINT8 PcieRpEnableCpm[28]; + +/** Offset 0x0330 - PCIE RP Detect Timeout Ms + The number of milliseconds within 0~65535 in reference code will wait for link to + exit Detect state for enabled ports before assuming there is no device and potentially + disabling the port. +**/ + UINT16 PcieRpDetectTimeoutMs[24]; + +/** Offset 0x0360 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[28]; + +/** Offset 0x037C - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 PcieRpPmSci[28]; + +/** Offset 0x0398 - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 PcieRpTransmitterHalfSwing[28]; + +/** Offset 0x03B4 - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[28]; + +/** Offset 0x03D0 - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[28]; + +/** Offset 0x03EC - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 PcieRpUnsupportedRequestReport[28]; + +/** Offset 0x0408 - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 PcieRpFatalErrorReport[28]; + +/** Offset 0x0424 - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 PcieRpNoFatalErrorReport[28]; + +/** Offset 0x0440 - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 PcieRpCorrectableErrorReport[28]; + +/** Offset 0x045C - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnFatalError[28]; + +/** Offset 0x0478 - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnNonFatalError[28]; + +/** Offset 0x0494 - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnCorrectableError[28]; + +/** Offset 0x04B0 - PCIE RP Max Payload + Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[28]; + +/** Offset 0x04CC - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: + PCIE_SPEED). +**/ + UINT8 PcieRpPcieSpeed[28]; + +/** Offset 0x04E8 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 PcieRpPhysicalSlotNumber[28]; + +/** Offset 0x0504 - PCIE RP Completion Timeout + The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. +**/ + UINT8 PcieRpCompletionTimeout[28]; + +/** Offset 0x0520 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[28]; + +/** Offset 0x053C - HostL0sTxDis + Disable Host L0 transmission state + $EN_DIS +**/ + UINT8 HostL0sTxDis[28]; + +/** Offset 0x0558 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[28]; + +/** Offset 0x0574 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[28]; + +/** Offset 0x0590 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 PcieRpLtrConfigLock[28]; + +/** Offset 0x05AC - PCIE RP override default settings for EQ + Choose PCIe EQ method + $EN_DIS +**/ + UINT8 PcieEqOverrideDefault[12]; + +/** Offset 0x05B8 - PCIE RP choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieGen3EqMethod[12]; + +/** Offset 0x05C4 - PCIE RP choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieGen3EqMode[12]; + +/** Offset 0x05D0 - PCIE RP EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieGen3EqLocalTxOverrideEn[12]; + +/** Offset 0x05DC - PCI RP number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieGen3EqPh3NoOfPresetOrCoeff[12]; + +/** Offset 0x05E8 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor0List[12]; + +/** Offset 0x05F4 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor0List[12]; + +/** Offset 0x0600 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor1List[12]; + +/** Offset 0x060C - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor1List[12]; + +/** Offset 0x0618 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor2List[12]; + +/** Offset 0x0624 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor2List[12]; + +/** Offset 0x0630 - PCIR RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor3List[12]; + +/** Offset 0x063C - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor3List[12]; + +/** Offset 0x0648 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor4List[12]; + +/** Offset 0x0654 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor4List[12]; + +/** Offset 0x0660 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor5List[12]; + +/** Offset 0x066C - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor5List[12]; + +/** Offset 0x0678 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor6List[12]; + +/** Offset 0x0684 - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor6List[12]; + +/** Offset 0x0690 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor7List[12]; + +/** Offset 0x069C - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor7List[12]; + +/** Offset 0x06A8 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor8List[12]; + +/** Offset 0x06B4 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor8List[12]; + +/** Offset 0x06C0 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor9List[12]; + +/** Offset 0x06CC - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor9List[12]; + +/** Offset 0x06D8 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset0List[12]; + +/** Offset 0x06E4 - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset1List[12]; + +/** Offset 0x06F0 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset2List[12]; + +/** Offset 0x06FC - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset3List[12]; + +/** Offset 0x0708 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset4List[12]; + +/** Offset 0x0714 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset5List[12]; + +/** Offset 0x0720 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset6List[12]; + +/** Offset 0x072C - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset7List[12]; + +/** Offset 0x0738 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset8List[12]; + +/** Offset 0x0744 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset9List[12]; + +/** Offset 0x0750 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset10List[12]; + +/** Offset 0x075C - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT8 PcieGen3EqPh1DpTxPreset[12]; + +/** Offset 0x0768 - PCIE RP EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT8 PcieGen3EqPh1UpTxPreset[12]; + +/** Offset 0x0774 - PCIE RP EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieGen3EqPh2LocalTxOverridePreset[12]; + +/** Offset 0x0780 - PCIE RP choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieGen4EqMethod[12]; + +/** Offset 0x078C - PCIE RP choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieGen4EqMode[12]; + +/** Offset 0x0798 - PCIE RP EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieGen4EqLocalTxOverrideEn[12]; + +/** Offset 0x07A4 - PCI RP number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieGen4EqPh3NoOfPresetOrCoeff[12]; + +/** Offset 0x07B0 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor0List[12]; + +/** Offset 0x07BC - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor0List[12]; + +/** Offset 0x07C8 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor1List[12]; + +/** Offset 0x07D4 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor1List[12]; + +/** Offset 0x07E0 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor2List[12]; + +/** Offset 0x07EC - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor2List[12]; + +/** Offset 0x07F8 - PCIR RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor3List[12]; + +/** Offset 0x0804 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor3List[12]; + +/** Offset 0x0810 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor4List[12]; + +/** Offset 0x081C - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor4List[12]; + +/** Offset 0x0828 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor5List[12]; + +/** Offset 0x0834 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor5List[12]; + +/** Offset 0x0840 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor6List[12]; + +/** Offset 0x084C - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor6List[12]; + +/** Offset 0x0858 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor7List[12]; + +/** Offset 0x0864 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor7List[12]; + +/** Offset 0x0870 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor8List[12]; + +/** Offset 0x087C - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor8List[12]; + +/** Offset 0x0888 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor9List[12]; + +/** Offset 0x0894 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor9List[12]; + +/** Offset 0x08A0 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset0List[12]; + +/** Offset 0x08AC - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset1List[12]; + +/** Offset 0x08B8 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset2List[12]; + +/** Offset 0x08C4 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset3List[12]; + +/** Offset 0x08D0 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset4List[12]; + +/** Offset 0x08DC - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset5List[12]; + +/** Offset 0x08E8 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset6List[12]; + +/** Offset 0x08F4 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset7List[12]; + +/** Offset 0x0900 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset8List[12]; + +/** Offset 0x090C - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset9List[12]; + +/** Offset 0x0918 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset10List[12]; + +/** Offset 0x0924 - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT8 PcieGen4EqPh1DpTxPreset[12]; + +/** Offset 0x0930 - PCIE RP EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT8 PcieGen4EqPh1UpTxPreset[12]; + +/** Offset 0x093C - PCIE RP EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieGen4EqPh2LocalTxOverridePreset[12]; + +/** Offset 0x0948 - PCIE RP choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieGen5EqMethod[12]; + +/** Offset 0x0954 - PCIE RP choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieGen5EqMode[12]; + +/** Offset 0x0960 - PCIE RP EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieGen5EqLocalTxOverrideEn[12]; + +/** Offset 0x096C - PCI RP number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieGen5EqPh3NoOfPresetOrCoeff[12]; + +/** Offset 0x0978 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor0List[12]; + +/** Offset 0x0984 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor0List[12]; + +/** Offset 0x0990 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor1List[12]; + +/** Offset 0x099C - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor1List[12]; + +/** Offset 0x09A8 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor2List[12]; + +/** Offset 0x09B4 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor2List[12]; + +/** Offset 0x09C0 - PCIR RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor3List[12]; + +/** Offset 0x09CC - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor3List[12]; + +/** Offset 0x09D8 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor4List[12]; + +/** Offset 0x09E4 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor4List[12]; + +/** Offset 0x09F0 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor5List[12]; + +/** Offset 0x09FC - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor5List[12]; + +/** Offset 0x0A08 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor6List[12]; + +/** Offset 0x0A14 - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor6List[12]; + +/** Offset 0x0A20 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor7List[12]; + +/** Offset 0x0A2C - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor7List[12]; + +/** Offset 0x0A38 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor8List[12]; + +/** Offset 0x0A44 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor8List[12]; + +/** Offset 0x0A50 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor9List[12]; + +/** Offset 0x0A5C - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor9List[12]; + +/** Offset 0x0A68 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset0List[12]; + +/** Offset 0x0A74 - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset1List[12]; + +/** Offset 0x0A80 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset2List[12]; + +/** Offset 0x0A8C - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset3List[12]; + +/** Offset 0x0A98 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset4List[12]; + +/** Offset 0x0AA4 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset5List[12]; + +/** Offset 0x0AB0 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset6List[12]; + +/** Offset 0x0ABC - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset7List[12]; + +/** Offset 0x0AC8 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset8List[12]; + +/** Offset 0x0AD4 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset9List[12]; + +/** Offset 0x0AE0 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset10List[12]; + +/** Offset 0x0AEC - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT8 PcieGen5EqPh1DpTxPreset[12]; + +/** Offset 0x0AF8 - PCIE RP EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT8 PcieGen5EqPh1UpTxPreset[12]; + +/** Offset 0x0B04 - PCIE RP EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieGen5EqPh2LocalTxOverridePreset[12]; + +/** Offset 0x0B10 - Phase3 RP Gen3 EQ enable + Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen3EqPh3Bypass[12]; + +/** Offset 0x0B1C - Phase3 RP Gen4 EQ enable + Phase3 Gen4 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen4EqPh3Bypass[12]; + +/** Offset 0x0B28 - Phase3 RP Gen5 EQ enable + Phase3 Gen5 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen5EqPh3Bypass[12]; + +/** Offset 0x0B34 - Phase2-3 RP Gen3 EQ enable + Phase2-3 Gen3 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): + Enable Phase2-3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen3EqPh23Bypass[12]; + +/** Offset 0x0B40 - Phase2-3 RP Gen4 EQ enable + Phase2-3 Gen4 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): + Enable Phase2-3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen4EqPh23Bypass[12]; + +/** Offset 0x0B4C - Phase2-3 RP Gen5 EQ enable + Phase2-3 Gen5 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): + Enable Phase2-3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen5EqPh23Bypass[12]; + +/** Offset 0x0B58 - PCET Timer + Preset/Coefficient Evaluation Timeout Gen3 PCET Timer. See PCIE_GEN3_PCET. Default + is 0x0(2ms) +**/ + UINT8 PcieGen3PcetTimer[12]; + +/** Offset 0x0B64 - Gen4 PCET Timer + Preset/Coefficient Evaluation Timeout - Gen4 PCET Timer. See PCIE_GEN4_PCET. Default + is 0x0(2ms) +**/ + UINT8 PcieGen4PcetTimer[12]; + +/** Offset 0x0B70 - Gen5 PCET Timer + Preset/Coefficient Evaluation Timeout - Gen5 PCET Timer. See PCIE_GEN5_PCET. Default + is 0x0(2ms) +**/ + UINT8 PcieGen5PcetTimer[12]; + +/** Offset 0x0B7C - TS Lock Timer for Gen3 + Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen3 TS Lock + Timer. See PCIE_GEN3_TS_LOCK_TIMER. Default is 0x0 +**/ + UINT8 PcieGen3TsLockTimer[12]; + +/** Offset 0x0B88 - PTS Lock Timer for Gen4 + Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen4 TS Lock + Timer. See PCIE_GEN4_TS_LCOK_TIMER. Default is 0x0 +**/ + UINT8 PcieGen4TsLockTimer[12]; + +/** Offset 0x0B94 - PTS Lock Timer for Gen5 + Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen5 TS Lock + Timer. See PCIE_GEN5_TS_LCOK_TIMER. Default is 0x0 +**/ + UINT8 PcieGen5TsLockTimer[12]; + +/** Offset 0x0BA0 - PCIE Secure Register Lock + Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled, + load PcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 PcieSetSecuredRegisterLock; + +/** Offset 0x0BA1 - Enable/Disable ASPM Optionality Compliance + Enable/Disable ASPM Optionality Compliance. +**/ + UINT8 PcieRpTestAspmOc[12]; + +/** Offset 0x0BAD - PCIE RP Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + UINT8 PcieEnablePeerMemoryWrite[12]; + +/** Offset 0x0BB9 - Assertion on Link Down GPIOs + GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down + GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs + 0:Disable, 1:Enable +**/ + UINT8 PcieRpLinkDownGpios[12]; + +/** Offset 0x0BC5 - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + UINT8 PcieComplianceTestMode; + +/** Offset 0x0BC6 - PCIE Rp Function Swap + Allows BIOS to use root port function number swapping when root port of function + 0 is disabled. + $EN_DIS +**/ + UINT8 PcieRpFunctionSwap; + +/** Offset 0x0BC7 - PCIe RootPort Clock Gating + Describes whether the PCI Express Clock Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieClockGating[12]; + +/** Offset 0x0BD3 - PCIe RootPort Power Gating + Describes whether the PCI Express Power Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PciePowerGating[12]; + +/** Offset 0x0BDF - PCIe RootPort VISA Clock Gating + Describes whether the PCI Express VISA Clock Gating. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieVisaClockGating[12]; + +/** Offset 0x0BEB - PCIe RootPort AutoPower Gating + Describes the Auto Power Gating for per controller. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieAutoPowerGating[12]; + +/** Offset 0x0BF7 - PCIe RootPort PHY AutoPower Gating + Describes the PHY Auto Power Gating for per controller. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PciePhyAutoPowerGating; + +/** Offset 0x0BF8 - FOMS Control Policy + Choose the Foms Control Policy, Default = 0 + 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms +**/ + UINT8 PcieFomsCp[12]; + +/** Offset 0x0C04 - EqPhBypass Control Policy + PCIe Equalization Phase Enable Control, Disabled (0x0) : Disable Phase + (Default), Enabled (0x1) : Enable Phase + 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms +**/ + UINT8 PcieEqPhBypass[12]; + +/** Offset 0x0C10 - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[24]; + +/** Offset 0x0C40 - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[24]; + +/** Offset 0x0C70 - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 PcieRpSnoopLatencyOverrideMode[28]; + +/** Offset 0x0C8C - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpSnoopLatencyOverrideMultiplier[28]; + +/** Offset 0x0CA8 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 PcieRpSnoopLatencyOverrideValue[24]; + +/** Offset 0x0CD8 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMode[28]; + +/** Offset 0x0CF4 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[28]; + +/** Offset 0x0D10 - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; + +/** Offset 0x0D40 - PCIE RP Slot Power Limit Scale + Specifies scale used for slot power limit value. Leave as 0 to set to default. +**/ + UINT8 PcieRpSlotPowerLimitScale[28]; + +/** Offset 0x0D5C - PCIE RP Slot Power Limit Value + Specifies upper limit on power supplie by slot. Leave as 0 to set to default. +**/ + UINT16 PcieRpSlotPowerLimitValue[24]; + +/** Offset 0x0D8C - PCIE RP Enable Port8xh Decode + This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PcieEnablePort8xhDecode; + +/** Offset 0x0D8D - PCIE Port8xh Decode Port Index + The Index of PCIe Port that is selected for Port8xh Decode (1 Based). +**/ + UINT8 PchPciePort8xhDecodePortIndex; + +/** Offset 0x0D8E - PCIE RP LTR Override Spec Compliant + Override LTR based on Ep capability. +**/ + UINT8 PcieRpLtrOverrideSpecCompliant[28]; + +/** Offset 0x0DAA - PCIe AER _OSC Setting + Enable/Disable Global PCIe Advanced Error Reporting + 0:Disable, 1:Enable +**/ + UINT8 GlobalPcieAer; + +/** Offset 0x0DAB - PCIe TBT Performance Boost Bitmap + Bitmap of TBT performance boost enabled PCIe controllers to which discrete TBT controllers + connect. Bit0: PXPA, Bit1: PXPB, Bit2: PXPC, Bit3: PXPD, Bit4: PXPE +**/ + UINT8 PcieTbtPerfBoost; + +/** Offset 0x0DAC - Serial IO SPI CLK Pin Muxing + Select SerialIo LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* + for possible values. +**/ + UINT32 SerialIoLpssSpiClkPinMux[7]; + +/** Offset 0x0DC8 - Serial IO SPI CS Pin Muxing + Select SerialIo LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* + for possible values. +**/ + UINT32 SerialIoLpssSpiCsPinMux[14]; + +/** Offset 0x0E00 - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:LpssSpiDisabled, 1:LpssSpiPci, 2:LpssSpiHidden +**/ + UINT8 SerialIoLpssSpiMode[7]; + +/** Offset 0x0E07 +**/ + UINT8 FspsUpdRsvd8; + +/** Offset 0x0E08 - LPSS SPI MOSI Pin Muxing + Select LPSS SPI MOSI pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MOSI* for possible values. +**/ + UINT32 SerialIoLpssSpiMosiPinMux[7]; + +/** Offset 0x0E24 - LPSS SPI MISO Pin Muxing + Select Lpss SPI MISO pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MISO* for possible values. +**/ + UINT32 SerialIoLpssSpiMisoPinMux[7]; + +/** Offset 0x0E40 - SPI Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:LpssSpiCsActiveLow, 1:LpssSpiCsActiveHigh +**/ + UINT8 SerialIoLpssSpiCsPolarity[14]; + +/** Offset 0x0E4E - SPI Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 SerialIoLpssSpiCsEnable[14]; + +/** Offset 0x0E5C - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoLpssSpiCsMode[7]; + +/** Offset 0x0E63 - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoLpssSpiCsState[7]; + +/** Offset 0x0E6A - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x0E71 +**/ + UINT8 FspsUpdRsvd9[3]; + +/** Offset 0x0E74 - Default BaudRate for each Serial IO UART + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 SerialIoUartBaudRate[7]; + +/** Offset 0x0E90 - Default ParityType for each Serial IO UART + Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartParity[7]; + +/** Offset 0x0E97 - Default DataBits for each Serial IO UART + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 SerialIoUartDataBits[7]; + +/** Offset 0x0E9E - Default StopBits for each Serial IO UART + Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: + TwoStopBits +**/ + UINT8 SerialIoUartStopBits[7]; + +/** Offset 0x0EA5 - Power Gating mode for each Serial IO UART that works in COM mode + Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto +**/ + UINT8 SerialIoUartPowerGating[7]; + +/** Offset 0x0EAC - Enable Dma for each Serial IO UART that supports it + Set DMA/PIO mode. 0: Disabled, 1: Enabled +**/ + UINT8 SerialIoUartDmaEnable[7]; + +/** Offset 0x0EB3 - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[7]; + +/** Offset 0x0EBA +**/ + UINT8 FspsUpdRsvd10[2]; + +/** Offset 0x0EBC - SerialIoUartRtsPinMuxPolicy + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartRtsPinMuxPolicy[7]; + +/** Offset 0x0ED8 - SerialIoUartRxPinMuxPolicy + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMuxPolicy[7]; + +/** Offset 0x0EF4 - SerialIoUartTxPinMuxPolicy + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMuxPolicy[7]; + +/** Offset 0x0F10 - Serial IO UART DBG2 table + Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; + 1: Enable. +**/ + UINT8 SerialIoUartDbg2[7]; + +/** Offset 0x0F17 - Serial IO UART PG DBG2 table + Enable or disable Serial Io UART PG DBG2 table, default is Disable; 0: Disable; + 1: Enable. +**/ + UINT8 SerialIoUartPgDbg2[7]; + +/** Offset 0x0F1E - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x0F26 +**/ + UINT8 FspsUpdRsvd11[2]; + +/** Offset 0x0F28 - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. +**/ + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x0F48 - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x0F68 - PCH SerialIo I2C Pads Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination + respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + UINT8 PchSerialIoI2cPadsTermination[8]; + +/** Offset 0x0F70 - I3C Device Mode + Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci, + 2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling) +**/ + UINT8 SerialIoI3cMode[3]; + +/** Offset 0x0F73 +**/ + UINT8 FspsUpdRsvd12; + +/** Offset 0x0F74 - Serial IO I3C SDA Pin Muxing + Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for + possible values. +**/ + UINT32 SerialIoI3cSdaPinMux[3]; + +/** Offset 0x0F80 - Serial IO I3C SDA Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination + respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on. +**/ + UINT8 SerialIoI3cSdaPadTermination[3]; + +/** Offset 0x0F83 +**/ + UINT8 FspsUpdRsvd13; + +/** Offset 0x0F84 - Serial IO I3C SCL Pin Muxing + Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for + possible values. +**/ + UINT32 SerialIoI3cSclPinMux[3]; + +/** Offset 0x0F90 - Serial IO I3C SCL Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination + respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on. +**/ + UINT8 SerialIoI3cSclPadTermination[3]; + +/** Offset 0x0F93 +**/ + UINT8 FspsUpdRsvd14; + +/** Offset 0x0F94 - Serial IO I3C SCL FB Pin Muxing + Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB* + for possible values. +**/ + UINT32 SerialIoI3cSclFbPinMux[3]; + +/** Offset 0x0FA0 - Serial IO I3C SCL FB Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination + respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on. +**/ + UINT8 SerialIoI3cSclFbPadTermination[3]; + +/** Offset 0x0FA3 - Enable VMD controller + Enable/disable to VMD controller.0: Disable; 1: Enable(Default) + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x0FA4 - Enable VMD Global Mapping + Enable/disable to VMD controller.0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 VmdGlobalMapping; + +/** Offset 0x0FA5 - Map port under VMD + Map/UnMap port under VMD + $EN_DIS +**/ + UINT8 VmdPort[31]; + +/** Offset 0x0FC4 - VMD Port Bus + VMD Root port bus number. +**/ + UINT8 VmdPortBus[31]; + +/** Offset 0x0FE3 - VMD Port Device + VMD Root port device number. +**/ + UINT8 VmdPortDev[31]; + +/** Offset 0x1002 - VMD Port Func + VMD Root port function number. +**/ + UINT8 VmdPortFunc[31]; + +/** Offset 0x1021 +**/ + UINT8 FspsUpdRsvd37[7]; + +/** Offset 0x1028 - VMD Variable + VMD Variable Pointer. +**/ + UINT64 VmdVariablePtr; + +/** Offset 0x1030 - Temporary CfgBar address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdCfgBarBase; + +/** Offset 0x1034 - Temporary MemBar1 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar1Base; + +/** Offset 0x1038 - Temporary MemBar2 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar2Base; + +/** Offset 0x103C - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x103D - TCSS TBT Performance Boost Bitmap + Bitmap of TBT performance boost enabled TCSS PCIe root ports. Bit0: TCSS port0, + Bit1: TCSS port1, Bit2: TCSS port2, Bit3: TCSS port3 +**/ + UINT8 TcssTbtPerfBoost; + +/** Offset 0x103E +**/ + UINT8 FspsUpdRsvd15[2]; + +/** Offset 0x1040 - TypeC port GPIO setting + GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Lnl + = LunarLake) +**/ + UINT32 IomTypeCPortPadCfg[12]; + +/** Offset 0x1070 - CPU USB3 Port Over Current Pin + Describe the specific over current pin number of USBC Port N. +**/ + UINT8 CpuUsb3OverCurrentPin[10]; + +/** Offset 0x107A - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x107B - TC State in TCSS + This TC C-State Limit in IOM +**/ + UINT8 TcCstateLimit; + +/** Offset 0x107C - TC Notify Igd + Tc Notify Igd +**/ + UINT8 TcNotifyIgd; + +/** Offset 0x107D - TCSS CPU USB PDO Programming + Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow + for programming during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 TcssCpuUsbPdoProgramming; + +/** Offset 0x107E - Enable/Disable PMC-PD Solution + This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution + $EN_DIS +**/ + UINT8 PmcPdEnable; + +/** Offset 0x107F +**/ + UINT8 FspsUpdRsvd16; + +/** Offset 0x1080 - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x1082 - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x1084 - TCSS USB Port Enable + Bits 0, 1, ... max Type C port control enables +**/ + UINT8 UsbTcPortEn; + +/** Offset 0x1085 - VCCST request for IOM + This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 + $EN_DIS +**/ + UINT8 VccSt; + +/** Offset 0x1086 - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x108A - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 SaPcieItbtRpLtrEnable[4]; + +/** Offset 0x108E - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; + +/** Offset 0x1092 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x1096 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; + +/** Offset 0x109E - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; + +/** Offset 0x10A2 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x10A6 - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; + +/** Offset 0x10AE - Force LTR Override + Force LTR Override. +**/ + UINT8 SaPcieItbtRpForceLtrOverride[4]; + +/** Offset 0x10B2 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 SaPcieItbtRpLtrConfigLock[4]; + +/** Offset 0x10B6 - Type C Port x Convert to TypeA + Enable / Disable(default) Type C Port x Convert to TypeA + $EN_DIS +**/ + UINT8 EnableTcssCovTypeA[4]; + +/** Offset 0x10BA - Touch Host Controller Assignment + Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1 +**/ + UINT8 ThcAssignment[2]; + +/** Offset 0x10BC - Touch Host Controller Interrupt Pin Mux + Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* + for possible values. +**/ + UINT8 ThcInterruptPinMuxing[8]; + +/** Offset 0x10C4 - Touch Host Controller Mode + Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid +**/ + UINT8 ThcMode[2]; + +/** Offset 0x10C6 - Touch Host Controller Wake On Touch + Based on this setting vGPIO for given THC will be in native mode, and additional + _CRS for wake will be exposed in ACPI +**/ + UINT8 ThcWakeOnTouch[2]; + +/** Offset 0x10C8 - Touch Host Controller Active Ltr + Expose Active Ltr for OS driver to set +**/ + UINT32 ThcActiveLtr[2]; + +/** Offset 0x10D0 - Touch Host Controller Idle Ltr + Expose Idle Ltr for OS driver to set +**/ + UINT32 ThcIdleLtr[2]; + +/** Offset 0x10D8 - Touch Host Controller Timestamp timer behavior in D0i2 + Timestamp timer behavior in D0i2. 1 = Timer resets to 0 when entering D0i2 0 = Timer + is paused instead of reset to 0 when entering D0i2 +**/ + UINT8 TimestampTimerMode[2]; + +/** Offset 0x10DA +**/ + UINT8 FspsUpdRsvd17[2]; + +/** Offset 0x10DC - Touch Host Controller Display Frame Sync Period + Period of the emulated display frame sync [ms] The minimum period is 2ms, maximum + period is 100ms +**/ + UINT32 DisplayFrameSyncPeriod[2]; + +/** Offset 0x10E4 - Touch Host Controller ResetPad + ResetPad +**/ + UINT32 ThcResetPad[2]; + +/** Offset 0x10EC - Touch Host Controller ResetPad Trigger + Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High +**/ + UINT32 ThcResetPadTrigger[2]; + +/** Offset 0x10F4 - Touch Host Controller DYSync + Based on this setting GPIO for given THC will be in native mode +**/ + UINT8 ThcDsyncPad[2]; + +/** Offset 0x10F6 +**/ + UINT8 FspsUpdRsvd18[2]; + +/** Offset 0x10F8 - Touch Host Controller Hid Over Spi Connection Speed + Hid Over Spi Connection Speed - SPI Frequency +**/ + UINT32 ThcHidSpiConnectionSpeed[2]; + +/** Offset 0x1100 - Touch Host Controller Hid Over Spi Limit PacketSize + When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc + packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes +**/ + UINT32 ThcHidSpiLimitPacketSize[2]; + +/** Offset 0x1108 - Touch Host Controller Hid Over Spi Limit PacketSize + Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation + and begin of read operation. This value shall be in 10us multiples 0x0: Disabled, + 1-65535 (0xFFFF) - up to 655350 us +**/ + UINT32 ThcPerformanceLimitation[2]; + +/** Offset 0x1110 - Touch Host Controller Hid Over Spi Input Report Header Address + Hid Over Spi Input Report Header Address +**/ + UINT32 ThcHidSpiInputReportHeaderAddress[2]; + +/** Offset 0x1118 - Touch Host Controller Hid Over Spi Input Report Body Address + Hid Over Spi Input Report Body Address +**/ + UINT32 ThcHidSpiInputReportBodyAddress[2]; + +/** Offset 0x1120 - Touch Host Controller Hid Over Spi Output Report Address + Hid Over Spi Output Report Address +**/ + UINT32 ThcHidSpiOutputReportAddress[2]; + +/** Offset 0x1128 - Touch Host Controller Hid Over Spi Read Opcode + Hid Over Spi Read Opcode +**/ + UINT32 ThcHidSpiReadOpcode[2]; + +/** Offset 0x1130 - Touch Host Controller Hid Over Spi Write Opcode + Hid Over Spi Write Opcode +**/ + UINT32 ThcHidSpiWriteOpcode[2]; + +/** Offset 0x1138 - Touch Host Controller Hid Over Spi Flags + Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode +**/ + UINT32 ThcHidSpiFlags[2]; + +/** Offset 0x1140 - Touch Host Controller Reset Sequencing Delay [ms] + Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms +**/ + UINT16 ThcResetSequencingDelay[2]; + +/** Offset 0x1144 - Touch Host Controller Hid Over I2c Device Address + Hid Over I2c Device Address +**/ + UINT32 ThcHidI2cDeviceAddress[2]; + +/** Offset 0x114C - Touch Host Controller Hid Over I2c Connection Speed + Hid Over I2c Connection Speed [Hz] +**/ + UINT32 ThcHidI2cConnectionSpeed[2]; + +/** Offset 0x1154 - Touch Host Controller Hid Over I2c Addressing Mode + Hid Over I2c Addressing Mode - 0x1: The connection uses 10-bit addressing. 0x0: + The connection uses 7-bit addressing. +**/ + UINT8 ThcHidI2cAddressingMode[2]; + +/** Offset 0x1156 +**/ + UINT8 FspsUpdRsvd19[2]; + +/** Offset 0x1158 - Touch Host Controller Hid Over I2c Device Descriptor Address + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cDeviceDescriptorAddress[2]; + +/** Offset 0x1160 - Touch Host Controller Hid Over I2c Serial Clock Line High Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cStandardModeSerialClockLineHighPeriod[2]; + +/** Offset 0x1168 - Touch Host Controller Hid Over I2c Standard Mode Serial Clock Line Low Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cStandardModeSerialClockLineLowPeriod[2]; + +/** Offset 0x1170 - Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Transmit Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cStandardModeSerialDataLineTransmitHoldPeriod[2]; + +/** Offset 0x1178 - Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Receive Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cStandardModeSerialDataLineReceiveHoldPeriod[2]; + +/** Offset 0x1180 - Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line High Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModeSerialClockLineHighPeriod[2]; + +/** Offset 0x1188 - Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line Low Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModeSerialClockLineLowPeriod[2]; + +/** Offset 0x1190 - Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Transmit Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModeSerialDataLineTransmitHoldPeriod[2]; + +/** Offset 0x1198 - Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Receive Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModeSerialDataLineReceiveHoldPeriod[2]; + +/** Offset 0x11A0 - Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In Std Mode Fast Mode And Fast Mode Plus + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cMaxSuppressedSpikesSMFMFMP[2]; + +/** Offset 0x11A8 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line High Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModePlusSerialClockLineHighPeriod[2]; + +/** Offset 0x11B0 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line Low Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModePlusSerialClockLineLowPeriod[2]; + +/** Offset 0x11B8 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Transmit Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModePlusSerialDataLineTransmitHoldPeriod[2]; + +/** Offset 0x11C0 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Receive Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cFastModePlusSerialDataLineReceiveHoldPeriod[2]; + +/** Offset 0x11C8 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line High Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cHighSpeedModePlusSerialClockLineHighPeriod[2]; + +/** Offset 0x11D0 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line Low Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cHighSpeedModePlusSerialClockLineLowPeriod[2]; + +/** Offset 0x11D8 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Transmit Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cHighSpeedModePlusSerialDataLineTransmitHoldPeriod[2]; + +/** Offset 0x11E0 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Receive Hold Period + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cHighSpeedModePlusSerialDataLineReceiveHoldPeriod[2]; + +/** Offset 0x11E8 - Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In High Speed Mode + Hid Over I2c Device Descriptor Address +**/ + UINT32 ThcHidI2cMaximumLengthOfSuppressedSpikesInHighSpeedMode[2]; + +/** Offset 0x11F0 - THC Wake On Touch GPIO resource Edge or Level + Definition of GPIO resource configuration of Edge or Level +**/ + UINT8 ThcWotEdgeLevel[2]; + +/** Offset 0x11F2 - THC Wake On Touch GPIO resource of Active Level + Definition of GPIO resource configuration of Active Level +**/ + UINT8 ThcWotActiveLevel[2]; + +/** Offset 0x11F4 - THC Wake On Touch GPIO resource of pin configuration + Definition of GPIO resource configuration of pin configuration +**/ + UINT8 ThcWotPinConfig[2]; + +/** Offset 0x11F6 - THC customized SubSytem ID for Port + Definition of GPIO resource configuration of pin configuration +**/ + UINT16 ThcCustomizedSsid[2]; + +/** Offset 0x11FA - THC Sets Customized SubSytem Vendor ID for Port + Definition of GPIO resource configuration of pin configuration +**/ + UINT16 ThcCustomizedSvid[2]; + +/** Offset 0x11FE +**/ + UINT8 FspsUpdRsvd38[2]; + +/** Offset 0x1200 - USB 3.1 Speed Selection + Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2 +**/ + UINT32 Usb31PortSpeed; + +/** Offset 0x1204 - Touch Host Controller Hid Over I2c Maximum Frame Size Enable + Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2 +**/ + UINT8 ThcHidI2cMaxFrameSize[2]; + +/** Offset 0x1206 - Touch Host Controller Hid Over I2c Maximum Frame Size Value + Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2 +**/ + UINT16 ThcHidI2cMaxFrameSizeValue[2]; + +/** Offset 0x120A - Touch Host Controller Hid Over I2c Interrupt Delay Enable + Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2 +**/ + UINT8 ThcHidI2cIntDelay[2]; + +/** Offset 0x120C - Touch Host Controller Hid Over I2c Interrupt Delay Value + Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2 +**/ + UINT16 ThcHidI2cIntDelayValue[2]; + +/** Offset 0x1210 - PchPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 PchPostMemRsvd[9]; + +/** Offset 0x1219 - PCHHOT# pin + Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchHotEnable; + +/** Offset 0x121A - Thermal Throttling Custimized T0Level Value + Custimized T0Level value. +**/ + UINT16 PchT0Level; + +/** Offset 0x121C - Thermal Throttling Custimized T1Level Value + Custimized T1Level value. +**/ + UINT16 PchT1Level; + +/** Offset 0x121E - Thermal Throttling Custimized T2Level Value + Custimized T2Level value. +**/ + UINT16 PchT2Level; + +/** Offset 0x1220 - Enable The Thermal Throttle + Enable the thermal throttle function. + $EN_DIS +**/ + UINT8 PchTTEnable; + +/** Offset 0x1221 - PMSync State 13 + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force + at least T2 state. + $EN_DIS +**/ + UINT8 PchTTState13Enable; + +/** Offset 0x1222 - Thermal Throttle Lock + Thermal Throttle Lock. + $EN_DIS +**/ + UINT8 PchTTLock; + +/** Offset 0x1223 - Thermal Throttling Suggested Setting + Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 TTSuggestedSetting; + +/** Offset 0x1224 - Thermal Device Temperature + Decides the temperature. +**/ + UINT16 PchTemperatureHotLevel; + +/** Offset 0x1226 - Enable PCH TSN + Enable/disable TSN on the PCH. + $EN_DIS +**/ + UINT8 PchTsnEnable[4]; + +/** Offset 0x122A +**/ + UINT16 FspsUpdRsvd20; + +/** Offset 0x122C - PCH TSN MAC Address High Bits + Set TSN MAC Address High. +**/ + UINT32 PchTsn1MacAddressHigh; + +/** Offset 0x1230 - PCH TSN MAC Address Low Bits + Set TSN MAC Address Low. +**/ + UINT32 PchTsn1MacAddressLow; + +/** Offset 0x1234 - PCH TSN2 MAC Address High Bits + Set TSN2 MAC Address High. +**/ + UINT32 PchTsn2MacAddressHigh; + +/** Offset 0x1238 - PCH TSN2 MAC Address Low Bits + Set TSN2 MAC Address Low. +**/ + UINT32 PchTsn2MacAddressLow; + +/** Offset 0x123C - PCH TSN3 MAC Address High Bits + Set TSN3 MAC Address High. +**/ + UINT32 PchTsn3MacAddressHigh; + +/** Offset 0x1240 - PCH TSN3 MAC Address Low Bits + Set TSN3 MAC Address Low. +**/ + UINT32 PchTsn3MacAddressLow; + +/** Offset 0x1244 - PCH TSN4 MAC Address High Bits + Set TSN4 MAC Address High. +**/ + UINT32 PchTsn4MacAddressHigh; + +/** Offset 0x1248 - PCH TSN MAC4 Address Low Bits + Set TSN MAC4 Address Low. +**/ + UINT32 PchTsn4MacAddressLow; + +/** Offset 0x124C - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x125C - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x1266 - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x1267 - USB PDO Programming + Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming + during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 UsbPdoProgramming; + +/** Offset 0x1268 - USB Audio Offload enable + Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default) + $EN_DIS +**/ + UINT8 PchXhciUaolEnable; + +/** Offset 0x1269 - PCH USB OverCurrent mapping enable + 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin + mapping allow for NOA usage of OC pins + $EN_DIS +**/ + UINT8 PchUsbOverCurrentEnable; + +/** Offset 0x126A - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x127A - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x1284 - Enable xHCI LTR override + Enables override of recommended LTR values for xHCI + $EN_DIS +**/ + UINT8 PchUsbLtrOverrideEnable; + +/** Offset 0x1285 - USB DWB enable + Enable/Disable USB DWB. 0: disabled, 1: enabled (default) + $EN_DIS +**/ + UINT8 PchXhciDwbEnable; + +/** Offset 0x1286 +**/ + UINT8 FspsUpdRsvd21[2]; + +/** Offset 0x1288 - xHCI High Idle Time LTR override + Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting +**/ + UINT32 PchUsbLtrHighIdleTimeOverride; + +/** Offset 0x128C - xHCI Medium Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting +**/ + UINT32 PchUsbLtrMediumIdleTimeOverride; + +/** Offset 0x1290 - xHCI Low Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting +**/ + UINT32 PchUsbLtrLowIdleTimeOverride; + +/** Offset 0x1294 - USB2 Port Reset Message Enable + 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must + be enable for USB2 Port those are paired with CPU XHCI Port +**/ + UINT8 PortResetMessageEnable[16]; + +/** Offset 0x12A4 - PCH USB OverCurrent mapping lock enable + If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning + that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. + $EN_DIS +**/ + UINT8 PchXhciOcLock; + +/** Offset 0x12A5 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x12B5 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x12C5 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x12D5 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x12E5 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x12EF - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x12F9 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x1303 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default + = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x130D +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10]; + +/** Offset 0x1317 +**/ + UINT8 PchUsb3HsioFilterSelNEnable[10]; + +/** Offset 0x1321 +**/ + UINT8 PchUsb3HsioFilterSelPEnable[10]; + +/** Offset 0x132B +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10]; + +/** Offset 0x1335 +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10]; + +/** Offset 0x133F +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10]; + +/** Offset 0x1349 +**/ + UINT8 PchUsb3HsioFilterSelN[10]; + +/** Offset 0x1353 +**/ + UINT8 PchUsb3HsioFilterSelP[10]; + +/** Offset 0x135D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTranEnable[10]; + +/** Offset 0x1367 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 + USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default + = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTran[10]; + +/** Offset 0x1371 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTranEnable[10]; + +/** Offset 0x137B - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 + USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTran[10]; + +/** Offset 0x1385 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTranEnable[10]; + +/** Offset 0x138F - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 + USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTran[10]; + +/** Offset 0x1399 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTranEnable[10]; + +/** Offset 0x13A3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 + USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTran[10]; + +/** Offset 0x13AD - PCIe Fia Programming + Load Fia configuration if enable. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieFiaProgramming; + +/** Offset 0x13AE - Enable SSE Device + Test, 0: POR, 1: enable, 2: disable, Enable/Disable SSE/SSE++ Devices from PCI config space + $EN_DIS +**/ + UINT8 SseCommunication; + +/** Offset 0x13AF - MePostMemRestrictedRsvd + Reserved for ME Post-Mem Restricted + $EN_DIS +**/ + UINT8 MePostMemRestrictedRsvd[2]; + +/** Offset 0x13B1 - Enable/Disable NPU Device + Enable(Default): Enable NPU Device, Disable: Disable NPU Device + $EN_DIS +**/ + UINT8 NpuEnable; + +/** Offset 0x13B2 - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x13B3 - Enable PCH Lan LTR capabilty of PCH internal LAN + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchLanLtrEnable; + +/** Offset 0x13B4 - PCH Lan WOL Fast Support + Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm. + $EN_DIS +**/ + UINT8 PchLanWOLFastSupport; + +/** Offset 0x13B5 - Skip Ssid Programming. + When set to TRUE, silicon code will not do any SSID programming and platform code + needs to handle that by itself properly. + $EN_DIS +**/ + UINT8 SiSkipSsidProgramming; + +/** Offset 0x13B6 - Change Default SVID + Change the default SVID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSvid; + +/** Offset 0x13B8 - Change Default SSID + Change the default SSID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSsid; + +/** Offset 0x13BA - CAN Configurations + Enable/Disable CAN Controllers.0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchCanEnable[2]; + +/** Offset 0x13BC +**/ + UINT8 FspsUpdRsvd22[4]; + +/** Offset 0x13C0 - SVID SDID table Poniter. + The address of the table of SVID SDID to customize each SVID SDID entry. This is + only valid when SkipSsidProgramming is FALSE. +**/ + UINT64 SiSsidTablePtr; + +/** Offset 0x13C8 - Number of ssid table. + SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. + This is only valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiNumberOfSsidTableEntry; + +/** Offset 0x13CA - Skip DFX. + Skip DFX. + $EN_DIS +**/ + UINT8 DfxSkipBiosDone; + +/** Offset 0x13CB - SiPostMemRsvd + Reserved for SI Post-Mem + $EN_DIS +**/ + UINT8 SiPostMemRsvd[6]; + +/** Offset 0x13D1 +**/ + UINT8 FspsUpdRsvd23[3]; + +/** Offset 0x13D4 - LogoPixelHeight Address + Address of LogoPixelHeight +**/ + UINT32 LogoPixelHeight; + +/** Offset 0x13D8 - LogoPixelWidth Address + Address of LogoPixelWidth +**/ + UINT32 LogoPixelWidth; + +/** Offset 0x13DC +**/ + UINT8 FspsUpdRsvd24[4]; + +/** Offset 0x13E0 - Blt Buffer Address + Address of Blt buffer +**/ + UINT64 BltBufferAddress; + +/** Offset 0x13E8 - Graphics Configuration Ptr + Points to VBT +**/ + UINT64 GraphicsConfigPtr; + +/** Offset 0x13F0 - Enable/Disable SkipFspGop + Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver + $EN_DIS +**/ + UINT8 SkipFspGop; + +/** Offset 0x13F1 - Enable/Disable Media Configuration + Enable(Default): Configure Media for use, Disable: Skip Media Configuration + $EN_DIS +**/ + UINT8 ConfigureMedia; + +/** Offset 0x13F2 - Enable/Disable IGFX RenderStandby + Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby + $EN_DIS +**/ + UINT8 RenderStandby; + +/** Offset 0x13F3 - Enable/Disable GT Configuration + Enable(Default): Configure GT for use, Disable: Skip GT Configuration + $EN_DIS +**/ + UINT8 ConfigureGT; + +/** Offset 0x13F4 - Enable RC1p GT frequency request to PMA (provided all other conditions are met) + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 RC1pGtFreqEnable; + +/** Offset 0x13F5 - Enable RC1p Media frequency request to PMA (provided all other conditions are met) + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 RC1pMediaFreqEnable; + +/** Offset 0x13F6 - Enable/Disable PavpEnable + Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable + $EN_DIS +**/ + UINT8 PavpEnable; + +/** Offset 0x13F7 - Enable/Disable PeiGraphicsPeimInit + Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable: FSP will NOT initialize the framebuffer. + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x13F8 - Enable/Disable IGFX Media Standby + Enable(Default): Enable IGFX Media Standby, Disable: Disable IGFX MediaStandby + $EN_DIS +**/ + UINT8 MediaStandby; + +/** Offset 0x13F9 - Enable/Disable Gfx Workstation + Enable(Default): Is a workstation, Disable: Is not a workstation + $EN_DIS +**/ + UINT8 Dev2IsGfxWorkstation; + +/** Offset 0x13FA +**/ + UINT8 FspsUpdRsvd25[2]; + +/** Offset 0x13FC - Intel Graphics VBT (Video BIOS Table) Size + Size of Internal Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x1400 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x1401 - Select MaxActiveDisplays + Max Active Display : 0 - Default VBT, 1 - 1 display, 2 - 2 displays, Maximum supported + is 2 displays only +**/ + UINT8 MaxActiveDisplays; + +/** Offset 0x1402 +**/ + UINT8 FspsUpdRsvd26[2]; + +/** Offset 0x1404 - HorizontalResolution for PEI Logo + HorizontalResolution from PEIm Gfx for PEI Logo +**/ + UINT32 HorizontalResolution; + +/** Offset 0x1408 - VerticalResolution for PEI Logo + VerticalResolution from PEIm Gfx for PEI Logo +**/ + UINT32 VerticalResolution; + +/** Offset 0x140C +**/ + UINT8 FspsUpdRsvd388[56]; + +/** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 DevIntConfigPtr; + +/** Offset 0x1448 - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr + must not be NULL. +**/ + UINT8 NumOfDevIntConfig; + +/** Offset 0x1449 - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. +**/ + UINT8 GpioIrqRoute; + +/** Offset 0x144A - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. +**/ + UINT8 SciIrqSelect; + +/** Offset 0x144B - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. +**/ + UINT8 TcoIrqSelect; + +/** Offset 0x144C - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + UINT8 TcoIrqEnable; + +/** Offset 0x144D - PMC ADR enable + Enable/disable asynchronous DRAM refresh + $EN_DIS +**/ + UINT8 PmcAdrEn; + +/** Offset 0x144E - PMC ADR timer configuration enable + Enable/disable ADR timer configuration + $EN_DIS +**/ + UINT8 PmcAdrTimerEn; + +/** Offset 0x144F - PMC ADR phase 1 timer value + Enable/disable ADR timer configuration +**/ + UINT8 PmcAdrTimer1Val; + +/** Offset 0x1450 - PMC ADR phase 1 timer multiplier value + Specify the multiplier value for phase 1 ADR timer +**/ + UINT8 PmcAdrMultiplier1Val; + +/** Offset 0x1451 - PMC ADR host reset partition enable + Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message + $EN_DIS +**/ + UINT8 PmcAdrHostPartitionReset; + +/** Offset 0x1452 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states + Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtV1p05RailEnabledStates; + +/** Offset 0x1453 - Mask to enable the platform configuration of external V1p05 VR rail + External V1P05 Rail Supported Configuration +**/ + UINT8 PchFivrExtV1p05RailSupportedVoltageStates; + +/** Offset 0x1454 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtV1p05RailVoltage; + +/** Offset 0x1456 - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtV1p05RailIccMax; + +/** Offset 0x1457 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states + Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailEnabledStates; + +/** Offset 0x1458 - Mask to enable the platform configuration of external Vnn VR rail + External Vnn Rail Supported Configuration +**/ + UINT8 PchFivrExtVnnRailSupportedVoltageStates; + +/** Offset 0x1459 +**/ + UINT8 FspsUpdRsvd27; + +/** Offset 0x145A - External Vnn Voltage Value that will be used in S0ix/Sx states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 +**/ + UINT16 PchFivrExtVnnRailVoltage; + +/** Offset 0x145C - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailIccMax; + +/** Offset 0x145D - Mask to enable the usage of external Vnn VR rail in Sx states + Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in + Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailSxEnabledStates; + +/** Offset 0x145E - External Vnn Voltage Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments + (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailSxVoltage; + +/** Offset 0x1460 - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailSxIccMax; + +/** Offset 0x1461 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x1462 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x1463 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; + +/** Offset 0x1464 - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x1466 - FIVR Dynamic Power Management + Enable/Disable FIVR Dynamic Power Management. + $EN_DIS +**/ + UINT8 PchFivrDynPm; + +/** Offset 0x1467 +**/ + UINT8 FspsUpdRsvd28; + +/** Offset 0x1468 - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtV1p05RailIccMaximum; + +/** Offset 0x146A - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailIccMaximum; + +/** Offset 0x146C - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailSxIccMaximum; + +/** Offset 0x146E - External V1P05 Control Ramp Timer value + Hold off time to be used when changing the v1p05_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtV1p05RailCtrlRampTmr; + +/** Offset 0x146F - External VNN Control Ramp Timer value + Hold off time to be used when changing the vnn_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtVnnRailCtrlRampTmr; + +/** Offset 0x1470 - PCH Compatibility Revision ID + This member describes whether or not the CRID feature of PCH should be enabled. + $EN_DIS +**/ + UINT8 PchCrid; + +/** Offset 0x1471 - PCH Legacy IO Low Latency Enable + Set to enable low latency of legacy IO. 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchLegacyIoLowLatency; + +/** Offset 0x1472 - PCH P2SB + PCH P2SB + $EN_DIS +**/ + UINT8 SvTestUnhideP2sb; + +/** Offset 0x1473 - PCH Unlock SideBand access + The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before + 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. + $EN_DIS +**/ + UINT8 PchSbAccessUnlock; + +/** Offset 0x1474 - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x1475 - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x1476 - Enable PCH Io Apic Entry 24-119 + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIoApicEntry24_119; + +/** Offset 0x1477 - PCH Io Apic ID + This member determines IOAPIC ID. Default is 0x02. +**/ + UINT8 PchIoApicId; + +/** Offset 0x1478 - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x1479 - CNVi Wi-Fi Core + Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviWifiCore; + +/** Offset 0x147A - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x147B - CNVi BT Interface + This option configures BT device interface to either USB/PCI + 1:USB, 2:PCI +**/ + UINT8 CnviBtInterface; + +/** Offset 0x147C - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x147D - WWAN Coex + WWAN Coex is getting updated from UEFI variable +**/ + UINT8 CnviWwanCoex; + +/** Offset 0x147E - Skip BtPreInit + BtPreInit can be skipped if SkipBtPreInit is enabled +**/ + UINT8 SkipBtPreInit; + +/** Offset 0x147F +**/ + UINT8 FspsUpdRsvd29[1]; + +/** Offset 0x1480 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x1484 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in + GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x1488 - CNVi BT Audio OffOffloadInterfaceload + Enable/Disable BT Audio OffloadInterface, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffloadInterface; + +/** Offset 0x1489 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x148A - Skip PAM regsiter lock + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + $EN_DIS +**/ + UINT8 SkipPamLock; + +/** Offset 0x148B - TCSS LSx OE Enable + Bits 0, 1, ... max Type C Rettimerless port LSx OE enables +**/ + UINT8 TcssLsxOe; + +/** Offset 0x148C - PCH HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + UINT8 PchHdaVerbTableEntryNum; + +/** Offset 0x148D +**/ + UINT8 FspsUpdRsvd30[3]; + +/** Offset 0x1490 - PCH HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + UINT64 PchHdaVerbTablePtr; + +/** Offset 0x1498 - PCH HDA Codec Sx Wake Capability + Capability to detect wake initiated by a codec in Sx +**/ + UINT8 PchHdaCodecSxWakeCapability; + +/** Offset 0x1499 - Enable Pme + Enable Azalia wake-on-ring. + $EN_DIS +**/ + UINT8 PchHdaPme; + +/** Offset 0x149A - HD Audio Link Frequency + HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. + 0: 6MHz, 1: 12MHz, 2: 24MHz +**/ + UINT8 PchHdaLinkFrequency; + +/** Offset 0x149B - HD Audio Microphone Privacy Mode + HD Audio Microphone Privacy Mode: 0: No Microphone Privacy Support; 1: HW Managed + Microphone Privacy; 2: FW Managed Microphone Privacy; 3: Force Microphone Mute + 0: No Microphone Privacy Support, 1: HW Managed Microphone Privacy, 2: FW Managed + Microphone Privacy, 3: Force Microphone Mute +**/ + UINT8 PchHdaMicPrivacyMode; + +/** Offset 0x149C - HD Audio Microphone Privacy Deglitch + HD Audio Microphone Privacy Deglitch: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyDeglitch; + +/** Offset 0x149D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode + HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeSoundWire0; + +/** Offset 0x149E - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode + HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeSoundWire1; + +/** Offset 0x149F - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode + HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeSoundWire2; + +/** Offset 0x14A0 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode + HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeSoundWire3; + +/** Offset 0x14A1 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode + HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeSoundWire4; + +/** Offset 0x14A2 - HD Audio Microphone Privacy applied for Dmic in HW Mode + HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchHdaMicPrivacyHwModeDmic; + +/** Offset 0x14A3 +**/ + UINT8 FspsUpdRsvd31; + +/** Offset 0x14A4 - HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before forcing the actual microphone privacy DMA data zeroing. + HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before + forcing the actual microphone privacy DMA data zeroing. +**/ + UINT32 PchHdaMicPrivacyTimeout; + +/** Offset 0x14A8 +**/ + UINT8 PchHdaRsvd[5]; + +/** Offset 0x14AD +**/ + UINT8 FspsUpdRsvd32[3]; + +/** Offset 0x14B0 - Pointer to ChipsetInit Binary + ChipsetInit Binary Pointer. +**/ + UINT64 ChipsetInitBinPtr; + +/** Offset 0x14B8 - Length of ChipsetInit Binary + ChipsetInit Binary Length. +**/ + UINT32 ChipsetInitBinLen; + +/** Offset 0x14BC +**/ + UINT8 FspsUpdRsvd33[4]; + +/** Offset 0x14C0 - Pointer to NPHY Binary + Nphy Binary Pointer. +**/ + UINT64 NphyBinPtr; + +/** Offset 0x14C8 - Length of NPHY Binary + Nphy Binary Length. +**/ + UINT32 NphyBinLen; + +/** Offset 0x14CC +**/ + UINT8 FspsUpdRsvd34[4]; + +/** Offset 0x14D0 - Pointer to SYNPS PHY Binary + Synps Binary Pointer. +**/ + UINT64 SynpsPhyBinPtr; + +/** Offset 0x14D8 - Length of SYNPS PHY Binary + Synps Binary Length. +**/ + UINT32 SynpsPhyBinLen; + +/** Offset 0x14DC - Skip setting BIOS_DONE When Fw Update. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,skip setting BIOS_DONE MSR + at EndofPei. Note: BIOS_DONE MSR should be set in later phase before executing + 3rd party code if SiSkipBiosDoneWhenFwUpdate set to TRUE. + $EN_DIS +**/ + UINT8 SiSkipBiosDoneWhenFwUpdate; + +/** Offset 0x14DD - PMC WDT enable + Enable/disable PMC WDT configuration + $EN_DIS +**/ + UINT8 PmcWdtTimerEn; + +/** Offset 0x14DE +**/ + UINT8 FspsUpdRsvd35; + +/** Offset 0x14DF +**/ + UINT8 ReservedFspsUpd; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_ARCH2_UPD FspsArchUpd; + +/** Offset 0x0040 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x14E0 +**/ + UINT8 FspsUpdRsvd36[6]; + +/** Offset 0x14E6 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FsptUpd.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FsptUpd.h new file mode 100644 index 00000000..16ea8ac3 --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/FsptUpd.h @@ -0,0 +1,424 @@ +/** @file + +Copyright (c) 2026, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include + +#pragma pack(1) + + +/** Fsp T Core UPD +**/ +typedef struct { + +/** Offset 0x0040 +**/ + EFI_PHYSICAL_ADDRESS MicrocodeRegionBase; + +/** Offset 0x0048 +**/ + UINT64 MicrocodeRegionSize; + +/** Offset 0x0050 +**/ + EFI_PHYSICAL_ADDRESS CodeRegionBase; + +/** Offset 0x0058 +**/ + UINT64 CodeRegionSize; +} FSPT_CORE_UPD; + +/** Fsp T Configuration +**/ +typedef struct { + +/** Offset 0x0060 - PcdLpssUartDebugEnable + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdLpssUartDebugEnable; + +/** Offset 0x0061 - PcdLpssUartNumber + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdLpssUartNumber; + +/** Offset 0x0062 - PcdLpssUartMode - FSPT + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 PcdLpssUartMode; + +/** Offset 0x0063 - PcdLpssUartPowerGating - FSPT + Select SerialIo Uart Controller Powergating mode + 0:Disabled, 1:Enabled, 2:Auto +**/ + UINT8 PcdLpssUartPowerGating; + +/** Offset 0x0064 - PcdLpssUartBaudRate - FSPT + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 PcdLpssUartBaudRate; + +/** Offset 0x0068 - Pci Express Base Address + Base address to be programmed for Pci Express +**/ + UINT64 PcdPciExpressBaseAddress; + +/** Offset 0x0070 - Pci Express Region Length + Region Length to be programmed for Pci Express +**/ + UINT32 PcdPciExpressRegionLength; + +/** Offset 0x0074 - PcdLpssUartParity - FSPT + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 PcdLpssUartParity; + +/** Offset 0x0075 - PcdLpssUartDataBits - FSPT + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 PcdLpssUartDataBits; + +/** Offset 0x0076 - PcdLpssUartStopBits - FSPT + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 PcdLpssUartStopBits; + +/** Offset 0x0077 - PcdLpssUartAutoFlow - FSPT + Enables UART hardware flow control, CTS and RTS lines. + 0: Disable, 1:Enable +**/ + UINT8 PcdLpssUartAutoFlow; + +/** Offset 0x0078 - PcdLpssUartRxPinMux - FSPT + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 PcdLpssUartRxPinMux; + +/** Offset 0x007C - PcdLpssUartTxPinMux - FSPT + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 PcdLpssUartTxPinMux; + +/** Offset 0x0080 - PcdLpssUartRtsPinMux - FSPT + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 PcdLpssUartRtsPinMux; + +/** Offset 0x0084 - PcdLpssUartCtsPinMux - FSPT + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 PcdLpssUartCtsPinMux; + +/** Offset 0x0088 - PcdLpssUartDebugMmioBase - FSPT + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode + = SerialIoUartPci. +**/ + UINT32 PcdLpssUartDebugMmioBase; + +/** Offset 0x008C - PcdLpssUartDebugPciCfgBase - FSPT + Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0 +**/ + UINT32 PcdLpssUartDebugPciCfgBase; + +/** Offset 0x0090 - PcdLpcUartDebugEnable + Enable to initialize LPC Uart device in FSP. + 0:Disable, 1:Enable +**/ + UINT8 PcdLpcUartDebugEnable; + +/** Offset 0x0091 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x0092 - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x0093 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0094 - PcdLpssUart2ndEnable + Enable Additional SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdLpssUart2ndEnable; + +/** Offset 0x0095 - PcdLpssUart2ndNumber + Select SerialIo Uart Controller Number + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdLpssUart2ndNumber; + +/** Offset 0x0096 - PcdLpssUart2ndMode - FSPT + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 PcdLpssUart2ndMode; + +/** Offset 0x0097 +**/ + UINT8 FsptUpdRsvd196; + +/** Offset 0x0098 - PcdLpssUart2ndBaudRate - FSPT + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 PcdLpssUart2ndBaudRate; + +/** Offset 0x009C - PcdLpssUart2ndParity - FSPT + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 PcdLpssUart2ndParity; + +/** Offset 0x009D - PcdLpssUart2ndDataBits - FSPT + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 PcdLpssUart2ndDataBits; + +/** Offset 0x009E - PcdLpssUart2ndStopBits - FSPT + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 PcdLpssUart2ndStopBits; + +/** Offset 0x009F - PcdLpssUart2ndAutoFlow - FSPT + Enables UART hardware flow control, CTS and RTS lines. + 0: Disable, 1:Enable +**/ + UINT8 PcdLpssUart2ndAutoFlow; + +/** Offset 0x00A0 - PcdLpssUart2ndRxPinMux - FSPT + Select RX pin muxing for SerialIo UART +**/ + UINT32 PcdLpssUart2ndRxPinMux; + +/** Offset 0x00A4 - PcdLpssUart2ndTxPinMux - FSPT + Select TX pin muxing for SerialIo UART +**/ + UINT32 PcdLpssUart2ndTxPinMux; + +/** Offset 0x00A8 - PcdLpssUart2ndRtsPinMux - FSPT + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 PcdLpssUart2ndRtsPinMux; + +/** Offset 0x00AC - PcdLpssUart2ndCtsPinMux - FSPT + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 PcdLpssUart2ndCtsPinMux; + +/** Offset 0x00B0 - PcdLpssUart2ndMmioBase - FSPT + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUart2ndMode + = SerialIoUartPci. +**/ + UINT32 PcdLpssUart2ndMmioBase; + +/** Offset 0x00B4 - PcdLpssUart2ndPciCfgBase - FSPT + Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0 +**/ + UINT32 PcdLpssUart2ndPciCfgBase; + +/** Offset 0x00B8 +**/ + UINT32 TopMemoryCacheSize; + +/** Offset 0x00BC - Serial Io SPI Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, + 1:SerialIoSpiCsActiveHigh +**/ + UINT8 PcdSerialIoSpiCsPolarity[2]; + +/** Offset 0x00BE - Serial Io SPI Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 PcdSerialIoSpiCsEnable[2]; + +/** Offset 0x00C0 - Serial Io SPI Device Mode + When mode is set to Pci, controller is initalized in early stage. Available modes: + 0:SerialIoSpiDisabled, 1:SerialIoSpiPci. +**/ + UINT8 PcdSerialIoSpiMode; + +/** Offset 0x00C1 - Serial Io SPI Default Chip Select Output + Sets Default CS as Output. Available options: 0:CS0, 1:CS1 +**/ + UINT8 PcdSerialIoSpiDefaultCsOutput; + +/** Offset 0x00C2 - Serial Io SPI Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW +**/ + UINT8 PcdSerialIoSpiCsMode; + +/** Offset 0x00C3 - Serial Io SPI Default Chip Select State Low/High + Sets Default CS State Low or High. Available options: 0:Low, 1:High +**/ + UINT8 PcdSerialIoSpiCsState; + +/** Offset 0x00C4 - Serial Io SPI Device Number + Select which Serial Io SPI controller is initalized in early stage. +**/ + UINT8 PcdSerialIoSpiNumber; + +/** Offset 0x00C5 +**/ + UINT8 FsptUpdRsvd0[3]; + +/** Offset 0x00C8 - Serial Io SPI Device MMIO Base + Assigns MMIO for Serial Io SPI controller usage in early stage. +**/ + UINT32 PcdSerialIoSpiMmioBase; + +/** Offset 0x00CC - Serial IO SPI CS Pin Muxing + Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for + possible values. +**/ + UINT32 PcdSerialIoSpiCsPinMux[2]; + +/** Offset 0x00D4 - Serial IO SPI CLK Pin Muxing + Select SerialIo SPI CLK pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for + possible values. +**/ + UINT32 PcdSerialIoSpiClkPinMux; + +/** Offset 0x00D8 - Serial IO SPI MISO Pin Muxing + Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO* + for possible values. +**/ + UINT32 PcdSerialIoSpiMisoPinMux; + +/** Offset 0x00DC - Serial IO SPI MOSI Pin Muxing + Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI* + for possible values. +**/ + UINT32 PcdSerialIoSpiMosiPinMux; + +/** Offset 0x00E0 - Serial Io I2C Device MMIO Base + Assigns MMIO for Serial Io I2C controller usage in early stage. +**/ + UINT32 PcdSerialIoI2cMmioBase; + +/** Offset 0x00E4 - Serial Io I2C Sda Gpio Pin + Select SerialIo I2C Rts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SDA* for possible values. +**/ + UINT32 PcdSerialIoI2cSdaPin; + +/** Offset 0x00E8 - Serial Io I2C Scl Gpio Pin + Select SerialIo I2C Cts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SCL* for possible values. +**/ + UINT32 PcdSerialIoI2cSclPin; + +/** Offset 0x00EC - Serial Io I2C Gpio Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination + respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + UINT8 PcdSerialIoI2cPadsTerm; + +/** Offset 0x00ED - Serial Io I2c Controller Number + Select SerialIo I2C Controller number to be intilizaed during early boot. Default is 0xFF + 0:SerialIoI2c0, 1:SerialIoI2c1, 2:SerialIoI2c2, 0xFF:Disable +**/ + UINT8 PcdSerialIoI2cNumber; + +/** Offset 0x00EE - Enable Secondary Data Cache Region + Enable Secondary Data Cache Region + 0:Disable, 1:Enable +**/ + UINT8 EnableSecondaryDataCache; + +/** Offset 0x00EF - Enable Signed FSP Code Cache Programming + Enable Signed FSP Code Cache Programming + 0:Disable, 1:Enable +**/ + UINT8 ProgramWriteBackCodeCache; + +/** Offset 0x00F0 +**/ + UINT8 ReservedFsptUpd1[8]; +} FSP_T_CONFIG; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_ARCH2_UPD FsptArchUpd; + +/** Offset 0x0040 +**/ + FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0060 +**/ + FSP_T_CONFIG FsptConfig; + +/** Offset 0x00F8 +**/ + UINT8 FsptUpdRsvd2[6]; + +/** Offset 0x00FE +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/GpioV2Config.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/GpioV2Config.h new file mode 100644 index 00000000..a837a7ba --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/GpioV2Config.h @@ -0,0 +1,115 @@ +/** @file + Header file for GpioConfig structure used by GPIO library. + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 2021 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification Reference: +**/ +#ifndef _GPIOV2_CONFIG_H_ +#define _GPIOV2_CONFIG_H_ + +#include + +#pragma pack(push, 1) + +/** + GPIO configuration structure used for pin programming. + Structure contains fields that can be used to configure pad. +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. + Refer to definition of GPIOV2_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 5; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIOV2_HOSTSW_OWN. + **/ + UINT32 HostOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. + Refer to definition of GPIOV2_DIRECTION for supported settings. + **/ + UINT32 Direction : 6; + /** + Output State + Set Pad output value. + Refer to definition of GPIOV2_PAD_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). + This setting is applicable only if GPIO is in GpioMode with input enabled. + Refer to definition of GPIOV2_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 9; + /** + GPIO Reset Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIOV2_RESET_CONFIG for supported settings. + **/ + UINT32 ResetConfig : 8; + /** + GPIO Electrical Configuration + This setting controls pads termination. + Refer to definition of GPIOV2_TERMINATION_CONFIG for supported settings. + **/ + UINT32 TerminationConfig : 9; + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIOV2_PAD_LOCK for supported settings. + **/ + UINT32 LockConfig : 2; + /** + GPIO Lock Output State + This setting controls pads lock. + Refer to definition of GPIOV2_PAD_LOCK for supported settings. + **/ + UINT32 LockTx : 2; + /** + Additional GPIO configuration + Refer to definition of GPIOV2_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 9; + + /** + Virtual GPIO eSPI Chip Select configuration + This setting selects between CS0 and CS1. + Refer to definition of VGPIO_CS_CONFIG for supported settings. + **/ + UINT32 VgpioCs : 2; + + UINT32 RsvdBits : 9; ///< Reserved bits for future extension +} GPIOV2_CONFIG; + +#pragma pack(pop) + +typedef struct { + GPIOV2_PAD GpioPad; + GPIOV2_CONFIG GpioConfig; +} GPIOV2_INIT_CONFIG; + +#endif //_GPIO_CONFIG_H_ diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/GpioV2Pad.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/GpioV2Pad.h new file mode 100644 index 00000000..93cbcf5c --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/GpioV2Pad.h @@ -0,0 +1,632 @@ +/** @file + General GPIO V2 Pad definition + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 2021 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification Reference: +**/ + +#ifndef _GPIOV2_PAD_H_ +#define _GPIOV2_PAD_H_ + +typedef UINT32 GPIOV2_PAD; +typedef UINT32 GPIOV2_NATIVE_PAD; +typedef UINT32 GPIOV2_PAD_GROUP; + + +#define GPIOV2_PAD_NONE 0 +#define GPIOV2_PAD_INVALID 0xFFFFFFFF +#define GPIOV2_PAD_GROUP_NONE 0 + +// If Bit 0 is 0 then Library ignores remaining value +// If Bit 0 is 1 then Library programes remaining value. +#define GPIO_ASSIGN_VALUE(Val) (Val << 1) | 0x01 + +#define GPIO_STATE(Val) (UINT32) ((Val >> 1) & 0x01) + +#define GPIOV2_PAD_MASK_FUNCTIONALITY (0x3FF) +#define GPIOV2_PAD_POS_FUNCTIONALITY (22) +#define GPIOV2_PAD_MASK_CHIPSETID (0x1F) +#define GPIOV2_PAD_POS_CHIPSETID (17) +#define GPIOV2_PAD_MASK_NATIVE_FUNCTION (0xF) +#define GPIOV2_PAD_POS_NATIVE_FUNCTION (13) +#define GPIOV2_PAD_MASK_COMMUNITY_INDEX (0x7) +#define GPIOV2_PAD_POS_COMMUNITY_INDEX (10) +#define GPIOV2_PAD_MASK_GROUP_INDEX (0x7) +#define GPIOV2_PAD_POS_GROUP_INDEX (7) +#define GPIOV2_PAD_MASK_PAD_INDEX (0x7F) +#define GPIOV2_PAD_POS_PAD_INDEX (0) + +#define GPIOV2_PAD_ID(Functionality, ChipsetId, NativeFunction, CommunityIndex, GroupIndex, PadIndex) \ + ( ((Functionality & GPIOV2_PAD_MASK_FUNCTIONALITY) << GPIOV2_PAD_POS_FUNCTIONALITY) |\ + ((ChipsetId & GPIOV2_PAD_MASK_CHIPSETID) << GPIOV2_PAD_POS_CHIPSETID) |\ + ((NativeFunction & GPIOV2_PAD_MASK_NATIVE_FUNCTION) << GPIOV2_PAD_POS_NATIVE_FUNCTION) |\ + ((CommunityIndex & GPIOV2_PAD_MASK_COMMUNITY_INDEX) << GPIOV2_PAD_POS_COMMUNITY_INDEX) |\ + ((GroupIndex & GPIOV2_PAD_MASK_GROUP_INDEX) << GPIOV2_PAD_POS_GROUP_INDEX) |\ + ((PadIndex & GPIOV2_PAD_MASK_PAD_INDEX) << GPIOV2_PAD_POS_PAD_INDEX) \ + ) + +#define GPIOV2_PAD_SET_FUNCTIONALITY(PadDefinition, Functionality) \ + ( (PadDefinition & ~(GPIOV2_PAD_MASK_FUNCTIONALITY << GPIOV2_PAD_POS_FUNCTIONALITY)) | \ + ((Functionality & GPIOV2_PAD_MASK_FUNCTIONALITY) << GPIOV2_PAD_POS_FUNCTIONALITY) \ + ) + +#define GPIOV2_PAD_SET_CHIPSETID(PadDefinition, ChipsetId) \ + ( (PadDefinition & ~(GPIOV2_PAD_MASK_CHIPSETID << GPIOV2_PAD_POS_CHIPSETID)) | \ + ((ChipsetId & GPIOV2_PAD_MASK_CHIPSETID) << GPIOV2_PAD_POS_CHIPSETID) \ + ) + +#define GPIOV2_PAD_SET_NATIVE_FUNCTION(PadDefinition, NativeFunction) \ + ( (PadDefinition & ~(GPIOV2_PAD_MASK_NATIVE_FUNCTION << GPIOV2_PAD_POS_NATIVE_FUNCTION)) | \ + ((NativeFunction & GPIOV2_PAD_MASK_NATIVE_FUNCTION) << GPIOV2_PAD_POS_NATIVE_FUNCTION) \ + ) + +#define GPIOV2_PAD_SET_COMMUNITY_INDEX(PadDefinition, CommunityIndex) \ + ( (PadDefinition & ~(GPIOV2_PAD_MASK_COMMUNITY_INDEX << GPIOV2_PAD_POS_COMMUNITY_INDEX)) | \ + ((CommunityIndex & GPIOV2_PAD_MASK_COMMUNITY_INDEX) << GPIOV2_PAD_POS_COMMUNITY_INDEX) \ + ) + +#define GPIOV2_PAD_SET_GROUP_INDEX(PadDefinition, GroupIndex) \ + ( (PadDefinition & ~(GPIOV2_PAD_MASK_GROUP_INDEX << GPIOV2_PAD_POS_GROUP_INDEX)) | \ + ((GroupIndex & GPIOV2_PAD_MASK_GROUP_INDEX) << GPIOV2_PAD_POS_GROUP_INDEX) \ + ) + +#define GPIOV2_PAD_SET_PAD_INDEX(PadDefinition, PadIndex) \ + ( (PadDefinition & ~(GPIOV2_PAD_MASK_PAD_INDEX << GPIOV2_PAD_POS_PAD_INDEX)) | \ + ((PadIndex & GPIOV2_PAD_MASK_PAD_INDEX) << GPIOV2_PAD_POS_PAD_INDEX) \ + ) + +#define GPIOV2_PAD_GET_FUNCTIONALITY(PadDefinition) \ + ( (PadDefinition >> GPIOV2_PAD_POS_FUNCTIONALITY) & GPIOV2_PAD_MASK_FUNCTIONALITY ) + +#define GPIOV2_PAD_GET_CHIPSETID(PadDefinition) \ + ( (PadDefinition >> GPIOV2_PAD_POS_CHIPSETID) & GPIOV2_PAD_MASK_CHIPSETID ) + +#define GPIOV2_PAD_GET_NATIVE_FUNCTION(PadDefinition) \ + ( (PadDefinition >> GPIOV2_PAD_POS_NATIVE_FUNCTION) & GPIOV2_PAD_MASK_NATIVE_FUNCTION ) + +#define GPIOV2_PAD_GET_COMMUNITY_INDEX(PadDefinition) \ + ( (PadDefinition >> GPIOV2_PAD_POS_COMMUNITY_INDEX) & GPIOV2_PAD_MASK_COMMUNITY_INDEX ) + +#define GPIOV2_PAD_GET_GROUP_INDEX(PadDefinition) \ + ( (PadDefinition >> GPIOV2_PAD_POS_GROUP_INDEX) & GPIOV2_PAD_MASK_GROUP_INDEX ) + +#define GPIOV2_PAD_GET_PAD_INDEX(PadDefinition) \ + ( (PadDefinition >> GPIOV2_PAD_POS_PAD_INDEX) & GPIOV2_PAD_MASK_PAD_INDEX ) + +#define GPIOV2_PAD_GET_PAD_MODE(PadDefinition) \ + ( ((GPIOV2_PAD_GET_NATIVE_FUNCTION(PadDefinition)) << 1 ) | 0x1 ) + +typedef enum { + GpioV2PadModeHardwareDefault = 0x0, + GpioV2PadModeGpio = GPIO_ASSIGN_VALUE(0x0), + GpioV2PadModeNative1 = GPIO_ASSIGN_VALUE(0x1), + GpioV2PadModeNative2 = GPIO_ASSIGN_VALUE(0x2), + GpioV2PadModeNative3 = GPIO_ASSIGN_VALUE(0x3), + GpioV2PadModeNative4 = GPIO_ASSIGN_VALUE(0x4), + GpioV2PadModeNative5 = GPIO_ASSIGN_VALUE(0x5), + GpioV2PadModeNative6 = GPIO_ASSIGN_VALUE(0x6), + GpioV2PadModeNative7 = GPIO_ASSIGN_VALUE(0x7), + GpioV2PadModeNative8 = GPIO_ASSIGN_VALUE(0x8), + GpioV2PadModeNative9 = GPIO_ASSIGN_VALUE(0x9), + GpioV2PadModeNative10 = GPIO_ASSIGN_VALUE(0xA), + GpioV2PadModeNative11 = GPIO_ASSIGN_VALUE(0xB), + GpioV2PadModeNative12 = GPIO_ASSIGN_VALUE(0xC), + GpioV2PadModeNative13 = GPIO_ASSIGN_VALUE(0xD), + GpioV2PadModeNative14 = GPIO_ASSIGN_VALUE(0xE), + GpioV2PadModeNative15 = GPIO_ASSIGN_VALUE(0xF) +} GPIOV2_PAD_MODE; + +#define GPIOV2_PAD_MODE_MASK (0xF) +#define GPIOV2_PAD_MODE_DW0_POS (10) + +typedef enum { + GpioV2InputInversionHardwareDefault = 0x0, + GpioV2InputInversionDisable = GPIO_ASSIGN_VALUE(0x0), + GpioV2InputInversionEnable = GPIO_ASSIGN_VALUE(0x1) +} GPIOV2_PAD_INPUT_INVERSION; + +#define GPIOV2_PAD_INPUT_INVERSION_MASK (0x1) +#define GPIOV2_PAD_INPUT_INVERSION_DW0_POS (23) + +typedef enum { + GpioV2LockHardwareDefault = 0x0, + GpioV2Unlock = GPIO_ASSIGN_VALUE(0x0), ///< Leave Pad configuration unlocked + GpioV2Lock = GPIO_ASSIGN_VALUE(0x1) ///< Lock Pad configuration +} GPIOV2_PAD_LOCK; + +#define GPIOV2_PAD_LOCK_MASK (0x1) + +typedef enum { + GpioV2StateDefault = 0x0, + GpioV2StateLow = GPIO_ASSIGN_VALUE(0x0), + GpioV2StateHigh = GPIO_ASSIGN_VALUE(0x1) +} GPIOV2_PAD_STATE; + +#define GPIOV2_PAD_OUTPUT_STATE_MASK (0x1) +#define GPIOV2_PAD_OUTPUT_STATE_DW0_POS (0) + +#define GPIOV2_PAD_INPUT_STATE_MASK (0x1) +#define GPIOV2_PAD_INPUT_STATE_DW0_POS (1) + +#define GPIOV2_PAD_TX_DISABLE_MASK (0x1) +#define GPIOV2_PAD_TX_DISABLE_DW0_POS (8) + +#define GPIOV2_PAD_RX_DISABLE_MASK (0x1) +#define GPIOV2_PAD_RX_DISABLE_DW0_POS (9) + +typedef enum { + GpioV2ResetDefault = 0x00, ///< Leave value of pad reset unmodified + /** + Resume Reset (RSMRST) + GPP: PadRstCfg = 00b = "Powergood" + GPD: PadRstCfg = 11b = "Resume Reset" + Pad setting will reset on: + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + **/ + GpioV2ResetResume = GPIO_ASSIGN_VALUE(0x0), + /** + Host Deep Reset + PadRstCfg = 01b = "Deep GPIO Reset" + Pad settings will reset on: + - Warm/Cold/Global reset + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + **/ + GpioV2ResetHostDeep = GPIO_ASSIGN_VALUE(0x1), + /** + Platform Reset (PLTRST) + PadRstCfg = 10b = "GPIO Reset" + Pad settings will reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + - G3 + **/ + GpioV2ResetHost = GPIO_ASSIGN_VALUE(0x2), + /** + Deep Sleep Well Reset (DSW_PWROK) + GPP: not applicable + GPD: PadRstCfg = 00b = "Powergood" + Pad settings will reset on: + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + **/ + GpioV2DswReset = GPIO_ASSIGN_VALUE(0x3), + /** + Global reset. + PadRstCfg = 11b = "Global reset" + Pad settings will reset on: + - Global reset + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold reset + - DeepSx transition + **/ + GpioV2ResetGlobal = GPIO_ASSIGN_VALUE(0x4) +} GPIOV2_RESET_CONFIG; + + +#define GPIOV2_PAD_RESET_CONFIG_MASK (0x3) +#define GPIOV2_PAD_RESET_CONFIG_DW0_POS (30) + +typedef enum { + GpioV2TermDefault = 0x0, ///< Leave termination setting unmodified + GpioV2TermNone = 0x1, ///< none + GpioV2TermWpd5K = 0x5, ///< 5kOhm weak pull-down + GpioV2TermWpd20K = 0x9, ///< 20kOhm weak pull-down + GpioV2TermWpu1K = 0x13, ///< 1kOhm weak pull-up + GpioV2TermWpu2K = 0x17, ///< 2kOhm weak pull-up + GpioV2TermWpu5K = 0x15, ///< 5kOhm weak pull-up + GpioV2TermWpu20K = 0x19, ///< 20kOhm weak pull-up + GpioV2TermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up + /** + Native function controls pads termination + This setting is applicable only to some native modes. + Please check EDS to determine which native functionality + can control pads termination + **/ + GpioV2TermNative = 0x1F +} GPIOV2_TERMINATION_CONFIG; + +#define GPIOV2_PAD_TERMINATION_CONFIG_MASK (0xF) +#define GPIOV2_PAD_TERMINATION_CONFIG_DW1_POS (10) + +typedef enum { + GpioV2IosStateDefault = 0x0, + GpioV2IosStateLatchLastValue = GPIO_ASSIGN_VALUE(0x0), ///< Latch last value driven on TX, TX Enable and RX Enable + GpioV2IosStateTx0Rx0RxDis = GPIO_ASSIGN_VALUE(0x1), ///< TX: 0, RX: 0 (internally), RX disabled + GpioV2IosStateTx0Rx1RxDis = GPIO_ASSIGN_VALUE(0x2), ///< TX: 0, RX: 1 (internally), RX disabled + GpioV2IosStateTx1Rx0RxDis = GPIO_ASSIGN_VALUE(0x3), ///< TX: 1, RX: 0 (internally), RX disabled + GpioV2IosStateTx1Rx1RxDis = GPIO_ASSIGN_VALUE(0x4), ///< TX: 1, RX: 1 (internally), RX disabled + GpioV2IosStateTx0RxEn = GPIO_ASSIGN_VALUE(0x5), ///< TX: 0, RX enabled + GpioV2IosStateTx1RxEn = GPIO_ASSIGN_VALUE(0x6), ///< TX: 1, RX enabled + GpioV2IosStateHizRx0 = GPIO_ASSIGN_VALUE(0x7), ///< Hi-Z, RX: 0 (internally) + GpioV2IosStateHizRx1 = GPIO_ASSIGN_VALUE(0x8), ///< Hi-Z, RX: 1 (internally) + GpioV2IosStateTxDisRxEn = GPIO_ASSIGN_VALUE(0x9), ///< TX Disabled and RX Enabled (i.e. wake or interrupt) + GpioV2IosStateMasked = GPIO_ASSIGN_VALUE(0xF) ///< IO Standby signal is masked for this pad. In this mode, a pad operates as if IOStandby has not been asserted. +} GPIOV2_IOSTANDBY_STATE; + +#define GPIOV2_PAD_IOSTANDBY_STATE_MASK (0xF) +#define GPIOV2_PAD_IOSTANDBY_STATE_DW1_POS (14) + +/** + GPIO Standby Term configuration + Standby Termination options for GPIO Pads +**/ +typedef enum { + GpioV2IosTermDefault = 0x00, + GpioV2IosTermSame = GPIO_ASSIGN_VALUE(0x0), ///< Same as state specified in Term + GpioV2IosTermPuDisPdDis = GPIO_ASSIGN_VALUE(0x1), ///< Disable Pullup and Pulldown + GpioV2IosTermPuDisPdEn = GPIO_ASSIGN_VALUE(0x2), ///< Enable Pulldown + GpioV2IosTermPuEnPdDis = GPIO_ASSIGN_VALUE(0x3) ///< Enable Pullup +} GPIOV2_IOSTANDBY_TERM; + +#define GPIOV2_PAD_IOSTANDBY_TERM_MASK (0x3) +#define GPIOV2_PAD_IOSTANDBY_TERM_DW1_POS (8) + +#define GPIOV2_PAD_DEBOUNCE_ENABLE_MASK (0x1) +#define GPIOV2_PAD_DEBOUNCE_ENABLE_DW2_POS (0) + +#define GPIOV2_PAD_DEBOUNCE_TIMER_MASK (0xF) +#define GPIOV2_PAD_DEBOUNCE_TIMER_DW2_POS (1) + +#define GPIOV2_PAD_OWNERSHIP_HOST (0x00) +#define GPIOV2_PAD_OWNERSHIP_CSME (0x01) +#define GPIOV2_PAD_OWNERSHIP_ISH (0x02) +#define GPIOV2_PAD_OWNERSHIP_IE (0x03) +typedef enum { + GpioV2PadOwnHost = GPIO_ASSIGN_VALUE(GPIOV2_PAD_OWNERSHIP_HOST), + GpioV2PadOwnCsme = GPIO_ASSIGN_VALUE(GPIOV2_PAD_OWNERSHIP_CSME), + GpioV2PadOwnIsh = GPIO_ASSIGN_VALUE(GPIOV2_PAD_OWNERSHIP_ISH), + GpioV2PadOwnIe = GPIO_ASSIGN_VALUE(GPIOV2_PAD_OWNERSHIP_IE), +} GPIOV2_PAD_OWN; + +#define GPIOV2_PAD_OWNERSHIP_MASK_REV1 (0x7) +#define GPIOV2_PAD_OWNERSHIP_MASK (0x3) +#define GPIOV2_PAD_OWNERSHIP_POS (0) + +/** + Pad Own Register Revision. + Supported settings: + 0x0 : Multiple pad shares same PAD Ownership register and bit field is 2 bit wide for each Pad. + 0x1 : Each pad has dedicated Pad Ownership register and bit field is 3 bit wide. +**/ +typedef enum { + GpioV2PadOwnRegRev0 = 0x0, + GpioV2PadOwnRegRev1 = 0x1 +} GPIOV2_PAD_OWN_REG_REV; + +/** + Host Software Pad Ownership modes + This setting affects GPIO interrupt status registers. Depending on chosen ownership + some GPIO Interrupt status register get updated and other masked. + Please refer to EDS for HOSTSW_OWN register description. +**/ +typedef enum { + GpioV2HostOwnDefault = 0x0, ///< Leave ownership value unmodified + /** + Set HOST ownership to ACPI. + Use this setting if pad is not going to be used by GPIO OS driver. + If GPIO is configured to generate SCI/SMI/NMI then this setting must be + used for interrupts to work + **/ + GpioV2HostOwnAcpi = GPIO_ASSIGN_VALUE(0x0), + /** + Set HOST ownership to GPIO Driver mode. + Use this setting only if GPIO pad should be controlled by GPIO OS Driver. + GPIO OS Driver will be able to control the pad if appropriate entry in + ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) + **/ + GpioV2HostOwnGpio = GPIO_ASSIGN_VALUE(0x1) +} GPIOV2_HOSTSW_OWN; + +#define GPIOV2_PAD_HOST_OWNERSHIP_MASK (0x1) +#define GPIOV2_PAD_HOST_OWNERSHIP_POS (0x0) + +#define GPIOV2_PAD_GPI_IE_MASK (0x1) +#define GPIOV2_PAD_GPI_IE_POS (0x0) + +#define GPIOV2_PAD_GPI_IS_MASK (0x1) +#define GPIOV2_PAD_GPI_IS_POS (0x0) + +#define GPIOV2_PAD_GPI_GPE_EN_MASK (0x1) +#define GPIOV2_PAD_GPI_GPE_EN_POS (0x0) + +#define GPIOV2_PAD_GPI_GPE_STS_MASK (0x1) +#define GPIOV2_PAD_GPI_GPE_STS_POS (0x0) + +#define GPIOV2_PAD_NMI_EN_MASK (0x1) +#define GPIOV2_PAD_NMI_EN_POS (0x0) + +#define GPIOV2_PAD_NMI_STS_MASK (0x1) +#define GPIOV2_PAD_NMI_STS_POS (0x0) + +#define GPIOV2_PAD_SMI_EN_MASK (0x1) +#define GPIOV2_PAD_SMI_EN_POS (0x0) + +#define GPIOV2_PAD_SMI_STS_MASK (0x1) +#define GPIOV2_PAD_SMI_STS_POS (0x0) + +typedef enum { + GpioV2IntRxEvCfgDefault = 0x00, + GpioV2IntRxEvCfgLevel = GPIO_ASSIGN_VALUE(0x0), + GpioV2IntRxEvCfgEdge = GPIO_ASSIGN_VALUE(0x1), + GpioV2IntRxEvCfgDisable = GPIO_ASSIGN_VALUE(0x2), + GpioV2IntRxEvCfgLevelEdge = GPIO_ASSIGN_VALUE(0x3), +} GPIOV2_RXEVCFG; + +#define GPIOV2_PAD_RXEV_MASK (0x3) +#define GPIOV2_PAD_RXEV_DW0_POS (25) + +/// +/// GPIO Direction +/// +typedef enum { + GpioV2DirDefault = 0x0, ///< Leave pad direction setting unmodified + GpioV2DirInOut = GPIO_ASSIGN_VALUE(0x1), ///< Set pad for both output and input + GpioV2DirInInvOut = GPIO_ASSIGN_VALUE(0x2), ///< Set pad for both output and input with inversion + GpioV2DirIn = GPIO_ASSIGN_VALUE(0x3), ///< Set pad for input only + GpioV2DirInInv = GPIO_ASSIGN_VALUE(0x4), ///< Set pad for input with inversion + GpioV2DirOut = GPIO_ASSIGN_VALUE(0x5), ///< Set pad for output only + GpioV2DirNone = GPIO_ASSIGN_VALUE(0x6) ///< Disable both output and input +} GPIOV2_DIRECTION; + +/** + GPIO interrupt configuration + This setting is applicable only if pad is in GPIO mode and has input enabled. + GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) + and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in + EDS for details on this settings. + Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge + to describe an interrupt e.g. GpioIntApic | GpioIntLevel + If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. + If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. + Not all GPIO are capable of generating an SMI or NMI interrupt. + When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this + interrupt cannot be shared and its IRQn number is not configurable. + Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) + If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor + exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). + This type of GPIO Driver interrupt doesn't have any additional routing setting + required to be set by BIOS. Interrupt is handled by GPIO OS Driver. +**/ + +typedef enum { + GpioV2IntDefault = 0x0, ///< Leave value of interrupt routing unmodified + GpioV2IntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation + GpioV2IntNmi = GPIO_ASSIGN_VALUE(0x1), ///< Enable NMI interrupt only + GpioV2IntSmi = GPIO_ASSIGN_VALUE(0x2), ///< Enable SMI interrupt only + GpioV2IntSci = GPIO_ASSIGN_VALUE(0x4), ///< Enable SCI interrupt only + GpioV2IntApic = GPIO_ASSIGN_VALUE(0x8), ///< Enable IOxAPIC interrupt only + GpioV2IntLevel = GPIO_ASSIGN_VALUE(0x10), ///< Set interrupt as level triggered + GpioV2IntEdge = GPIO_ASSIGN_VALUE(0x20), ///< Set interrupt as edge triggered (type of edge depends on input inversion) + GpioV2IntLvlEdgDis = GPIO_ASSIGN_VALUE(0x40), ///< Disable interrupt trigger + GpioV2IntBothEdge = GPIO_ASSIGN_VALUE(0x80), ///< Set interrupt as both edge triggered +} GPIOV2_INT_CONFIG; + +#define GPIOV2_PAD_GPIROUTNMI_DW0_POS (17) +#define GPIOV2_PAD_GPIROUTNMI_DW0_MASK (1) + +#define GPIOV2_PAD_GPIROUTSMI_DW0_POS (18) +#define GPIOV2_PAD_GPIROUTSMI_DW0_MASK (1) + +#define GPIOV2_PAD_GPIROUTSCI_DW0_POS (19) +#define GPIOV2_PAD_GPIROUTSCI_DW0_MASK (1) + +#define GPIOV2_PAD_GPIROUTIOXAPIC_DW0_POS (20) +#define GPIOV2_PAD_GPIROUTIOXAPIC_DW0_MASK (1) + +/** + Other GPIO Configuration + GPIO_OTHER_CONFIG is used for less often settings and for future extensions + Supported settings: + - RX raw override to '1' - allows to override input value to '1' + This setting is applicable only if in input mode (both in GPIO and native usage). + The override takes place at the internal pad state directly from buffer and before the RXINV. +**/ +typedef enum { + GpioV2RxRaw1Default = 0x0, ///< Use default input override value + GpioV2RxRaw1Dis = 0x1, ///< Don't override input + GpioV2RxRaw1En = 0x3 ///< Override input to '1' +} GPIOV2_OTHER_CONFIG; + + +// +// Structure for native pin data +// +typedef struct { + GPIOV2_PAD Pad; + GPIOV2_PAD_MODE Mode; + GPIOV2_IOSTANDBY_STATE IosState; + GPIOV2_IOSTANDBY_TERM IosTerm; +} GPIOV2_PAD_NATIVE_FUNCTION; + +typedef enum { + // Ownership related registers + GpioV2PadOwnReg, + GpioV2PadHostSwOwnReg, + + // Lock related registers + GpioV2PadCfgLockReg, + GpioV2PadCfgLockTxReg, + + // Interrupts related registers + GpioV2GpiIsReg, + GpioV2GpiIeReg, + GpioV2GpiGpeStsReg, + GpioV2GpiGpeEnReg, + GpioV2SmiStsReg, + GpioV2SmiEnReg, + GpioV2NmiStsReg, + GpioV2NmiEnReg, + + // Configuration registers + GpioV2Dw0Reg, + GpioV2Dw1Reg, + GpioV2Dw2Reg, + + // Community registers + GpioV2MiscCfg, + GpioV2AcReg, + GpioV2Pwmc + +} GPIOV2_REGISTER; + +typedef struct { + UINT16 PadOwn; + UINT16 PadCfgLock; + UINT16 PadCfgLockTx; + UINT16 HostOwn; + UINT16 GpiIs; + UINT16 GpiIe; + UINT16 GpiGpeSts; + UINT16 GpiGpeEn; + UINT16 SmiSts; + UINT16 SmiEn; + UINT16 NmiSts; + UINT16 NmiEn; + UINT16 Dw0; +} GPIOV2_GROUP_REGISTERS_OFFSETS; + +// +// Access Control Registers +// +typedef struct { + UINT32 Rcp; + UINT16 Rrac; + UINT16 Rwac; +} GPIOV2_ACCESS_CONTROL_REGISTERS_OFFSETS; + +typedef struct { + UINT32 Policy; + UINT32 Read; + UINT32 Write; +} GPIOV2_ACCESS_CONTROL_SAI_DW_DATA; + +// +// Community Registers Offsets +// +typedef struct { + UINT16 MiscCfg; + UINT16 AcSaiGrup0RcpDw0; + UINT16 Pwmc; +} GPIOV2_COMMUNITY_REGISTERS_OFFSETS; + +// +// DDPx pins +// +typedef enum { + GpioV2Ddp1 = 0x01, + GpioV2Ddp2 = 0x02, + GpioV2Ddp3 = 0x03, + GpioV2Ddp4 = 0x04, + GpioV2DdpA = 0x10, + GpioV2DdpB = 0x11, + GpioV2DdpC = 0x12, + GpioV2DdpD = 0x13, + GpioV2DdpF = 0x15, +} GPIOV2_DDP; + +// +// DDI Port TBT_LSX interface +// +typedef enum { + GpioV2TbtLsxDdi1, + GpioV2TbtLsxDdi2, + GpioV2TbtLsxDdi3, + GpioV2TbtLsxDdi4, + GpioV2TbtLsxDdi5, + GpioV2TbtLsxDdi6 +} GPIOV2_TBT_LSX; + +// +// TBT_LSX_OE interface +// +typedef enum { + GpioV2TbtLsxOe0, + GpioV2TbtLsxOe1, + GpioV2TbtLsxOe2 +} GPIOV2_TBT_LSX_OE; + +/** + CNVi Bluetooth UART connection options +**/ +typedef enum { + GpioV2CnviBtIfUart = 0, + GpioV2CnviBtIfUsb, + GpioV2CnviBtIfPci, +} VGPIOV2_CNVI_BT_INTERFACE; + +/** + CNVi Bluetooth I2S connection options +**/ +typedef enum { + GpioV2CnviBtI2sNotConnected, + GpioV2CnviBtI2sToSsp0, + GpioV2CnviBtI2sToSsp1, + GpioV2CnviBtI2sToSsp2, + GpioV2CnviBtI2sToExternalPads +} VGPIOV2_CNVI_BT_I2S_CONNECTION_TYPE; + +/** + CNVi Bluetooth UART connection options +**/ +typedef enum { + GpioV2CnviBtUartNotConnected, + GpioV2CnviBtUartToSerialIoUart0, + GpioV2CnviBtUartToIshUart0, + GpioV2CnviBtUartToExternalPads +} VGPIOV2_CNVI_BT_UART_CONNECTION_TYPE; + +/** + CNVi MultiFunction UART connection options +**/ +typedef enum { + GpioV2CnviMfUart1NotConnected, + GpioV2CnviMfUart1ToSerialIoUart2, + GpioV2CnviMfUart1ToIshUart0, + GpioV2CnviMfUart1ToExternalPads +} VGPIOV2_CNVI_MF_UART1_CONNECTION_TYPE; + +/** + VCCIO level selection +**/ +typedef enum { + GpioV2Vcc3v3, + GpioV2Vcc1v8, + GpioV2MaxVccioSel +} GPIOV2_VCCIO_SEL; + +/** + VGPIO CS selection +**/ +typedef enum { + GpioV2VgpioCs0, + GpioV2VgpioCs1 +} GPIOV2_VGPIO_CS; + +#endif // _GPIOV2_PAD_H_ diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/MemInfoHob.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/MemInfoHob.h new file mode 100644 index 00000000..d587b1f9 --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/MemInfoHob.h @@ -0,0 +1,423 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 1999 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryS3Data2Guid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 2 +#define MAX_CH 4 +#define MAX_DDR5_CH 2 +#define MAX_DIMM 2 + +// Must be same or higher than the corresponding definitions in MrcGlobalDefinitions.h +#define _MAX_RANK_IN_CHANNEL (4) ///< The maximum number of ranks per channel. +#define _MAX_SDRAM_IN_DIMM (5) ///< The maximum number of SDRAMs per DIMM. + +// Must match the corresponding definition in CMrcExtTypes.h +#define PPR_REQUEST_MAX (2) + +// Must match definitions in +// Intel\OneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h +#define HOB_MAX_SAGV_POINTS 4 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 39 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 0 +#endif +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 2 +#endif + +#define MAX_PROFILE_NUM 7 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported + +#ifndef MAX_RCOMP_TARGETS +#define MAX_RCOMP_TARGETS 5 +#endif + +#ifndef MAX_ODT_ENTRIES +#define MAX_ODT_ENTRIES 11 +#endif + +#ifndef MAX_COPY_DIMM_DFE_TAPS +#define MAX_COPY_DIMM_DFE_TAPS 2 +#endif + +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT32 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. + UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group. + UINT8 Resv[2]; ///< Reserved. +} MRC_CH_TIMING; + +typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + +typedef union { + struct { + UINT16 ContinuationCount : 7; ///< Bits 6:0 + UINT16 ContinuationParity : 1; ///< Bits 7:7 + UINT16 LastNonZeroByte : 8; ///< Bits 15:8 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} HOB_MANUFACTURER_ID_CODE; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + HOB_MANUFACTURER_ID_CODE MfgId; ///< Dram module manufacturer ID + HOB_MANUFACTURER_ID_CODE CkdMfgID; ///< Clock Driver (CKD) Manufacturer ID + UINT8 CkdDeviceRev; ///< Clock Driver (CKD) device revision + HOB_MANUFACTURER_ID_CODE DramMfgID; ///< Manufacturer ID code for DRAM chip on the module + UINT8 ModulePartNum[30]; ///< Module part number in ASCII + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. + UINT8 Banks; ///< Number of banks the DIMM contains. + UINT8 BankGroups; ///< Number of bank groups the DIMM contains. + UINT8 DeviceDensity; ///< Device Density in Gb + UINT32 SerialNumber; ///< DIMM Serial Number + UINT8 TotalWidth; ///< Total Data width in bits + UINT8 DataWidth; ///< Primary bus width in bits +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +// +// Each DIMM Slot Mechanical present bit map +// +typedef struct { + UINT8 MrcSlotMap[MAX_NODE][MAX_CH]; +} MRC_SLOTMAP; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific + UINT16 MaxMemoryBandwidth; ///< Maximum theoretical bandwidth in GB/s supported by GV +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + +typedef struct _PPR_RESULT_COLUMNS_HOB { + UINT8 PprRowRepairsSuccessful; + UINT8 Controller; + UINT8 Channel; + UINT8 Rank; + UINT8 BankGroup; + UINT8 Bank; + UINT32 Row; + UINT8 Device; +} PPR_RESULT_COLUMNS_HOB; + +/** + Memory Info Data Hob + + Revision 1: + - Initial version. (from MTL) + Revision 2: + - Added MopPackages, MopDensity, MopRanks, MopVendor fields + Revision 3: + - Added MaxRankCapacity + - Removed DataWidth + - DIMM_INFO: increased ModulePartNum from 20 to 30 chars + - DIMM_INFO: Added SerialNumber, TotalWidth and DataWidth + - DIMM_INFO: Removed SpdModuleMemoryBusWidth + - MFG ID fields: use HOB_MANUFACTURER_ID_CODE instead of UINT16 for easier parsing + Revision 4: + - Added FailingChannelMask +**/ +typedef struct { + UINT8 Revision; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR5 or LPDDR5, uses SMBIOS MEMORY_DEVICE_TYPE encoding + UINT16 MaximumMemoryClockSpeed; ///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed + BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. + UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; + UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS]; + UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES]; + INT8 DimmDFE[MAX_PROFILE_NUM][MAX_DDR5_CH][MAX_DIMM][MAX_COPY_DIMM_DFE_TAPS]; + CONTROLLER_INFO Controller[MAX_NODE]; + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. + BOOLEAN IsIbeccEnabled; + UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels + UINT8 MopPackages; ///< Mop DRAM package population + UINT8 MopDensity; ///< Mop DRAM die density + UINT8 MopRanks; ///< Mop Number of ranks + UINT8 MopVendor; ///< Mop DRAM vendor ID + UINT8 PprRanInLastBoot; ///< Whether PPR ran in the prior boot + UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows + UINT16 PprRepairFails; ///< PPR: Counts of repair failure + UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status + UINT16 PprRepairsSuccessful; ///< PPR: Counts of repair successes + PPR_RESULT_COLUMNS_HOB PprErrorInfo; ///< PPR: Error location + UINT8 PprAvailableResources[MAX_NODE][MAX_CH][_MAX_RANK_IN_CHANNEL][_MAX_SDRAM_IN_DIMM]; ///< PPR available resources per device + BOOLEAN MixedEccDimms; ///< TRUE if both ECC and nonECC Dimms were detected in the system + UINT8 MaxRankCapacity; ///< Maximum possible rank capacity in [GB] + UINT16 PprFailingChannelBitMask; ///< PPR failing channel mask + BOOLEAN PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed) + UINT8 FailingChannelMask; ///< Limp Home mode failing channel bitmask +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; + PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; + BOOLEAN MrcBasicMemoryTestPass; + UINT8 Reserved1[3]; // Reserved for alignment + UINT64 BiosPeiMemoryBaseAddress; + UINT64 BiosPeiMemoryLength; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#define EFI_RMT_OS_VARIABLE_NAME L"Rmt" +#define RMT_ENABLE 1 +#define RMT_DISABLE 0 + +extern EFI_GUID gRmtVariableGuid; + +//Structure of RMT UEFI variable which should be R/W by OS +//EnDsRmt - To enable Memory margining support + +typedef struct { + UINT8 EnDsRmt; +} RMT_VAR; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/SmbiosCacheInfoHob.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/SmbiosCacheInfoHob.h new file mode 100644 index 00000000..936ee266 --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/SmbiosCacheInfoHob.h @@ -0,0 +1,57 @@ +/** @file + Header file for SMBIOS Cache Info HOB + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 2015 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification +**/ + +#ifndef _SMBIOS_CACHE_INFO_HOB_H_ +#define _SMBIOS_CACHE_INFO_HOB_H_ + +#include +#include + +#pragma pack(1) +/// +/// SMBIOS Cache Info HOB Structure +/// +typedef struct { + UINT16 ProcessorSocketNumber; + UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3 + UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE" + UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36 + UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 + UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 + UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown. + UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3 + UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4 + UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5 + // + // Add for smbios 3.1.0 + // + UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + /** + String Buffer - each string terminated by NULL "0x00" + String buffer terminated by double NULL "0x0000" + **/ +} SMBIOS_CACHE_INFO; +#pragma pack() + +#endif // _SMBIOS_CACHE_INFO_HOB_H_ diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h new file mode 100644 index 00000000..be68f3cf --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h @@ -0,0 +1,69 @@ +/** @file + Header file for SMBIOS Processor Info HOB + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 2015 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification +**/ + +#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_ +#define _SMBIOS_PROCESSOR_INFO_HOB_H_ + +#include +#include + +#pragma pack(1) +/// +/// SMBIOS Processor Info HOB Structure +/// +typedef struct { + UINT16 TotalNumberOfSockets; + UINT16 CurrentSocketNumber; + UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1 + /** This info is used for both ProcessorFamily and ProcessorFamily2 fields + See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2 + **/ + UINT16 ProcessorFamily; + UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer + UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3 + UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer + UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4 + UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown. + UINT16 MaxSpeedInMHz; ///< Snapshot of Max processor speed during boot + UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot + UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21 + UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5 + /** This info is used for both CoreCount & CoreCount2 fields + See detailed description in SMBIOS Spec v3.1 Section 7.5.6 + **/ + UINT16 CoreCount; + /** This info is used for both CoreEnabled & CoreEnabled2 fields + See detailed description in SMBIOS Spec v3.1 Section 7.5.7 + **/ + UINT16 EnabledCoreCount; + /** This info is used for both ThreadCount & ThreadCount2 fields + See detailed description in SMBIOS Spec v3.1 Section 7.5.8 + **/ + UINT16 ThreadCount; + UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9 + /** + String Buffer - each string terminated by NULL "0x00" + String buffer terminated by double NULL "0x0000" + **/ +} SMBIOS_PROCESSOR_INFO; +#pragma pack() + +#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_ diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c new file mode 100644 index 00000000..1197d449 --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c @@ -0,0 +1,35 @@ +/** @file + Library instance to list all DynamicEx PCD FSP consumes. + No real functionality. + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 2019 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification Reference: +**/ + +#include + +/** + Do nothing function. + +**/ +VOID +FspPcdListLibNull ( + VOID + ) +{ + return; +} diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf new file mode 100644 index 00000000..6d851143 --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf @@ -0,0 +1,75 @@ +## @file +# Library instance to list all DynamicEx PCD FSP consumes. +# +# @copyright +# INTEL CONFIDENTIAL +# Copyright (C) 2019 Intel Corporation. +# +# This software and the related documents are Intel copyrighted materials, +# and your use of them is governed by the express license under which they +# were provided to you ("License"). Unless the License provides otherwise, +# you may not use, modify, copy, publish, distribute, disclose or transmit +# this software or the related documents without Intel's prior written +# permission. +# +# This software and the related documents are provided as is, with no +# express or implied warranties, other than those that are expressly stated +# in the License. +# +# @par Specification Reference: +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = FspPcdListLibNull + FILE_GUID = C5D4D79E-3D5C-4EB6-899E-6F1563CB0B32 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = NULL +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + OneSiliconPkg/SiPkg.dec + +[Sources] + FspPcdListLibNull.c + +[Pcd] + # + # List all the DynamicEx PCDs that FSP will consume. + # FSP Dispatch mode bootloader will include this INF to ensure all the PCDs are + # built into PCD database. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceBspOnly ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTracePerformanceCollecting ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONSUMES + diff --git a/fsp/ptl/4063.02/PantherLakeFspBinPkg/PantherLakeFspBinPkg.dec b/fsp/ptl/4063.02/PantherLakeFspBinPkg/PantherLakeFspBinPkg.dec new file mode 100644 index 00000000..c54e7057 --- /dev/null +++ b/fsp/ptl/4063.02/PantherLakeFspBinPkg/PantherLakeFspBinPkg.dec @@ -0,0 +1,30 @@ +## @file +# Component description file for PantherLake Fsp Bin package. +# +# @copyright +# INTEL CONFIDENTIAL +# Copyright (C) 2016 Intel Corporation. +# +# This software and the related documents are Intel copyrighted materials, +# and your use of them is governed by the express license under which they +# were provided to you ("License"). Unless the License provides otherwise, +# you may not use, modify, copy, publish, distribute, disclose or transmit +# this software or the related documents without Intel's prior written +# permission. +# +# This software and the related documents are provided as is, with no +# express or implied warranties, other than those that are expressly stated +# in the License. +# +# @par Specification +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = PantherLakeFspBinPkg + PACKAGE_GUID = 5A536013-A46E-44AD-8B30-738235F77B06 + PACKAGE_VERSION = 1.02 + +[Includes] + Include + diff --git a/models/lemp14/PantherLakeFspBinPkg b/models/lemp14/PantherLakeFspBinPkg new file mode 120000 index 00000000..ae493717 --- /dev/null +++ b/models/lemp14/PantherLakeFspBinPkg @@ -0,0 +1 @@ +../../fsp/ptl/4063.02/PantherLakeFspBinPkg \ No newline at end of file diff --git a/models/lemp14/README.md b/models/lemp14/README.md new file mode 100644 index 00000000..3b1280d4 --- /dev/null +++ b/models/lemp14/README.md @@ -0,0 +1,12 @@ +# System76 Lemur Pro (lemp14) + +## Contents + +- [EC](./ec.rom) + - *Read Error: No such file or directory (os error 2)* +- [FD](./fd.rom) + - Size: 16 KB + - HAP: true +- [ME](./me.rom) + - Size: 9176 KB + - Version: 21.0.2.1482 diff --git a/models/lemp14/README.md.in b/models/lemp14/README.md.in new file mode 100644 index 00000000..bd2cd041 --- /dev/null +++ b/models/lemp14/README.md.in @@ -0,0 +1 @@ +# System76 Lemur Pro (lemp14) diff --git a/models/lemp14/chip.txt b/models/lemp14/chip.txt new file mode 100644 index 00000000..01a0b645 --- /dev/null +++ b/models/lemp14/chip.txt @@ -0,0 +1 @@ +PY25F256LC diff --git a/models/lemp14/coreboot-collector.txt b/models/lemp14/coreboot-collector.txt new file mode 100644 index 00000000..52f78eec --- /dev/null +++ b/models/lemp14/coreboot-collector.txt @@ -0,0 +1,255 @@ +## PCI ## +PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0xB001, Revision 0x04 +PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0xB082, Revision 0x04 +PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xB01D, Revision 0x04 +PCI Device: 0000:00:07.0: Class 0x00060400, Vendor 0x8086, Device 0xE44E, Revision 0x01 +PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xB07D, Revision 0x04 +PCI Device: 0000:00:0b.0: Class 0x00120000, Vendor 0x8086, Device 0xB03E, Revision 0x04 +PCI Device: 0000:00:0d.0: Class 0x000C0330, Vendor 0x8086, Device 0xE431, Revision 0x01 +PCI Device: 0000:00:0d.2: Class 0x000C0340, Vendor 0x8086, Device 0xE433, Revision 0x01 +PCI Device: 0000:00:13.0: Class 0x00078000, Vendor 0x8086, Device 0xE462, Revision 0x01 +PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0xE47D, Revision 0x01 +PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0xE47F, Revision 0x01 +PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0xE440, Revision 0x01 +PCI Device: 0000:00:14.7: Class 0x000D1100, Vendor 0x8086, Device 0xE476, Revision 0x01 +PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0xE478, Revision 0x01 +PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0xE479, Revision 0x01 +PCI Device: 0000:00:15.2: Class 0x000C8000, Vendor 0x8086, Device 0xE47A, Revision 0x01 +PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0xE470, Revision 0x01 +PCI Device: 0000:00:18.0: Class 0x00078000, Vendor 0x8086, Device 0xE45D, Revision 0x01 +PCI Device: 0000:00:19.0: Class 0x000C8000, Vendor 0x8086, Device 0xE450, Revision 0x01 +PCI Device: 0000:00:19.1: Class 0x000C8000, Vendor 0x8086, Device 0xE451, Revision 0x01 +PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0xE438, Revision 0x01 +PCI Device: 0000:00:1c.6: Class 0x00060400, Vendor 0x8086, Device 0xE43E, Revision 0x01 +PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0xE402, Revision 0x01 +PCI Device: 0000:00:1f.3: Class 0x00040380, Vendor 0x8086, Device 0xE428, Revision 0x01 +PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0xE422, Revision 0x01 +PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0xE423, Revision 0x01 +PCI Device: 0000:2b:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00 +PCI Device: 0000:2c:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01 +## GPIO ## +PTL-H/U PCH +GPP_V0 (0x59,0x00) 0x44000702 0x0003f018 0x00000000 0x00000000 +GPP_V1 (0x59,0x02) 0x44000702 0x0003fc19 0x00000000 0x00000000 +GPP_V2 (0x59,0x04) 0x44000702 0x0003fc1a 0x00000000 0x00000000 +GPP_V3 (0x59,0x06) 0x44000702 0x0003f01b 0x00000000 0x00000000 +GPP_V4 (0x59,0x08) 0x44000600 0x0003c01c 0x00000000 0x00000000 +GPP_V5 (0x59,0x0A) 0x44000600 0x0003c01d 0x00000000 0x00000000 +GPP_V6 (0x59,0x0C) 0x44000600 0x0003c01e 0x00000000 0x00000000 +GPP_V7 (0x59,0x0E) 0x44000600 0x0003c01f 0x00000000 0x00000000 +GPP_V8 (0x59,0x10) 0x44000201 0x0003c020 0x00000000 0x00000000 +GPP_V9 (0x59,0x12) 0x44000201 0x0003c021 0x00000000 0x00000000 +GPP_V10 (0x59,0x14) 0x44000201 0x0003c022 0x00000000 0x00000000 +GPP_V11 (0x59,0x16) 0x44000201 0x0003c023 0x00000000 0x00000000 +GPP_V12 (0x59,0x18) 0x44000602 0x0003c024 0x00000000 0x00000000 +GPP_V13 (0x59,0x1A) 0x44000601 0x0003c025 0x00000000 0x00000000 +GPP_V14 (0x59,0x1C) 0x44000603 0x0003c026 0x00000000 0x00000000 +GPP_V15 (0x59,0x1E) 0x44000601 0x0003c027 0x00000000 0x00000000 +GPP_V16 (0x59,0x20) 0x44000600 0x0003c028 0x00000000 0x00000000 +GPP_V17 (0x59,0x22) 0x44000201 0x00000029 0x00000000 0x00000000 +GPP_C0 (0x59,0x30) 0x44000502 0x0003f02a 0x00000000 0x00000000 +GPP_C1 (0x59,0x32) 0x44000502 0x0003f02b 0x00000000 0x00000000 +GPP_C2 (0x59,0x34) 0x44000201 0x0003c02c 0x00000800 0x00000000 +GPP_C3 (0x59,0x36) 0x44000702 0x0003c02d 0x00000000 0x00000000 +GPP_C4 (0x59,0x38) 0x44000702 0x0003c02e 0x00000000 0x00000000 +GPP_C5 (0x59,0x3A) 0x44000201 0x0000002f 0x00000000 0x00000000 +GPP_C6 (0x59,0x3C) 0x44000300 0x00000030 0x00000000 0x00000000 +GPP_C7 (0x59,0x3E) 0x44000300 0x00000031 0x00000000 0x00000000 +GPP_C8 (0x59,0x40) 0x44000201 0x00000032 0x00000000 0x00000000 +GPP_C9 (0x59,0x42) 0x44000201 0x00000033 0x00000000 0x00000000 +GPP_C10 (0x59,0x44) 0x44000201 0x00000034 0x00000000 0x00000000 +GPP_C11 (0x59,0x46) 0x44000201 0x00000035 0x00000000 0x00000000 +GPP_C12 (0x59,0x48) 0x84000702 0x00000036 0x00000000 0x00000000 +GPP_C13 (0x59,0x4A) 0x84000702 0x00000037 0x00000000 0x00000000 +GPP_C14 (0x59,0x4C) 0x84000702 0x00000038 0x00000000 0x00000000 +GPP_C15 (0x59,0x4E) 0x44000201 0x00000039 0x00000000 0x00000000 +GPP_C16 (0x59,0x50) 0xc4000700 0x0003c03a 0x00000000 0x00000000 +GPP_C17 (0x59,0x52) 0xc4000700 0x0003c03b 0x00000000 0x00000000 +GPP_C18 (0x59,0x54) 0x44000201 0x0000003c 0x00000000 0x00000000 +GPP_C19 (0x59,0x56) 0x44000201 0x0000003d 0x00000000 0x00000000 +GPP_C20 (0x59,0x58) 0x44000201 0x0000003e 0x00000000 0x00000000 +GPP_C21 (0x59,0x5A) 0x44000201 0x0000003f 0x00000000 0x00000000 +GPP_C22 (0x59,0x5C) 0x44000b00 0x0001c040 0x00000000 0x00000000 +GPP_C23 (0x59,0x5E) 0x44000b02 0x0001c041 0x00000000 0x00000000 +GPP_F0 (0x5A,0x00) 0x44000700 0x0003c042 0x00000000 0x00000000 +GPP_F1 (0x5A,0x02) 0x44000700 0x0003f043 0x00000000 0x00000000 +GPP_F2 (0x5A,0x04) 0x44000700 0x0003c044 0x00000000 0x00000000 +GPP_F3 (0x5A,0x06) 0x44000700 0x0003f045 0x00000000 0x00000000 +GPP_F4 (0x5A,0x08) 0x44000700 0x0003c046 0x00000000 0x00000000 +GPP_F5 (0x5A,0x0A) 0x44000f00 0x0003c047 0x00000000 0x00000000 +GPP_F6 (0x5A,0x0C) 0x44000201 0x00000048 0x00000000 0x00000000 +GPP_F7 (0x5A,0x0E) 0x44000201 0x0003c049 0x00000000 0x00000000 +GPP_F8 (0x5A,0x10) 0x44000201 0x0003c04a 0x00000000 0x00000000 +GPP_F9 (0x5A,0x12) 0x44000102 0x0000004b 0x00000000 0x00000000 +GPP_F10 (0x5A,0x14) 0x44000201 0x0000004c 0x00000000 0x00000000 +GPP_F11 (0x5A,0x16) 0x44000201 0x0003c04d 0x00000000 0x00000000 +GPP_F12 (0x5A,0x18) 0x44002302 0x0000004e 0x00000000 0x00000000 +GPP_F13 (0x5A,0x1A) 0x44002302 0x0000004f 0x00000000 0x00000000 +GPP_F14 (0x5A,0x1C) 0x44000201 0x0003c050 0x00000000 0x00000000 +GPP_F15 (0x5A,0x1E) 0x44000201 0x0003c051 0x00000000 0x00000000 +GPP_F16 (0x5A,0x20) 0x84000201 0x0003c052 0x00000000 0x00000000 +GPP_F17 (0x5A,0x22) 0x44000201 0x0003c053 0x00000000 0x00000000 +GPP_F18 (0x5A,0x24) 0x80800102 0x0003c054 0x00000000 0x00000000 +GPP_F19 (0x5A,0x26) 0x44000201 0x00000055 0x00000000 0x00000000 +GPP_F20 (0x5A,0x28) 0x44000201 0x00000056 0x00000000 0x00000000 +GPP_F21 (0x5A,0x2A) 0x44000201 0x00000057 0x00000000 0x00000000 +GPP_F22 (0x5A,0x2C) 0x44000201 0x0003c058 0x00000000 0x00000000 +GPP_F23 (0x5A,0x2E) 0x44000201 0x00000059 0x00000000 0x00000000 +GPP_E1 (0x5A,0x36) 0x42880102 0x0003c05b 0x00000000 0x00000000 +GPP_E2 (0x5A,0x38) 0x44000300 0x0000005c 0x00000000 0x00000000 +GPP_E3 (0x5A,0x3A) 0x44000201 0x0000005d 0x00000000 0x00000000 +GPP_E4 (0x5A,0x3C) 0x44000201 0x0000005e 0x00000000 0x00000000 +GPP_E5 (0x5A,0x3E) 0x44000201 0x0000005f 0x00000000 0x00000000 +GPP_E6 (0x5A,0x40) 0x44000201 0x00000060 0x00000800 0x00000000 +GPP_E7 (0x5A,0x42) 0x44000201 0x00000061 0x00000000 0x00000000 +GPP_E8 (0x5A,0x44) 0x44000300 0x00000062 0x00000000 0x00000000 +GPP_E9 (0x5A,0x46) 0x44000300 0x00000063 0x00000800 0x00000000 +GPP_E10 (0x5A,0x48) 0x44000201 0x00000064 0x00000000 0x00000000 +GPP_E11 (0x5A,0x4A) 0x44000100 0x0003c065 0x00000000 0x00000000 +GPP_E12 (0x5A,0x4C) 0x44002302 0x00000066 0x00000000 0x00000000 +GPP_E13 (0x5A,0x4E) 0x44002302 0x00000067 0x00000000 0x00000000 +GPP_E14 (0x5A,0x50) 0x44000100 0x0003c068 0x00000000 0x00000000 +GPP_E15 (0x5A,0x52) 0x44000100 0x0003c069 0x00000000 0x00000000 +GPP_E16 (0x5A,0x54) 0x44000201 0x0003c06a 0x00000000 0x00000000 +GPP_E17 (0x5A,0x56) 0x44000102 0x0003c06b 0x00000000 0x00000000 +GPP_E18 (0x5A,0x58) 0x44000201 0x0003c06c 0x00000000 0x00000000 +GPP_E19 (0x5A,0x5A) 0x44000201 0x0003c06d 0x00000000 0x00000000 +GPP_E20 (0x5A,0x5C) 0x44000201 0x0003c06e 0x00000000 0x00000000 +GPP_E21 (0x5A,0x5E) 0x04000702 0x0003c06f 0x00000000 0x00000000 +GPP_E22 (0x5A,0x60) 0x44000201 0x0003c070 0x00000000 0x00000000 +GPP_H0 (0x5B,0x00) 0x40000700 0x0003c000 0x00000000 0x00000000 +GPP_H1 (0x5B,0x02) 0x40000700 0x0003c000 0x00000000 0x00000000 +GPP_H2 (0x5B,0x04) 0x40000702 0x0003c000 0x00000000 0x00000000 +GPP_H3 (0x5B,0x06) 0x40000702 0x0003c000 0x00000000 0x00000000 +GPP_H4 (0x5B,0x08) 0x40000702 0x0003c000 0x00000000 0x00000000 +GPP_H5 (0x5B,0x0A) 0x40000702 0x0003c000 0x00000000 0x00000000 +GPP_H6 (0x5B,0x0C) 0x40000702 0x0003f000 0x00000000 0x00000000 +GPP_H7 (0x5B,0x0E) 0x40000700 0x0003c000 0x00000000 0x00000000 +GPP_H8 (0x5B,0x10) 0x40000702 0x0003c000 0x00000000 0x00000000 +GPP_H9 (0x5B,0x12) 0x40000702 0x0003f000 0x00000000 0x00000000 +GPP_H10 (0x5B,0x14) 0x40000702 0x0003f000 0x00000000 0x00000000 +GPP_H11 (0x5B,0x16) 0x40000700 0x0003d000 0x00000000 0x00000000 +GPP_H12 (0x5B,0x18) 0x40000700 0x0003e400 0x00000800 0x00000000 +GPP_H13 (0x5B,0x1A) 0x40000700 0x0003d000 0x00000000 0x00000000 +GPP_H14 (0x5B,0x1C) 0x40000700 0x00024000 0x00000000 0x00000000 +GPP_H15 (0x5B,0x1E) 0x44000201 0x00000023 0x00000000 0x00000000 +GPP_H16 (0x5B,0x20) 0x44000201 0x00000024 0x00000000 0x00000000 +GPP_H17 (0x5B,0x22) 0x44000201 0x00000025 0x00000000 0x00000000 +GPP_H18 (0x5B,0x24) 0x44000300 0x0003c026 0x00000000 0x00000000 +GPP_H19 (0x5B,0x26) 0x44000601 0x00000027 0x00000000 0x00000000 +GPP_H20 (0x5B,0x28) 0x44000601 0x00000028 0x00000000 0x00000000 +GPP_H21 (0x5B,0x2A) 0x44000201 0x00000029 0x00000000 0x00000000 +GPP_H22 (0x5B,0x2C) 0x44000201 0x0000002a 0x00000000 0x00000000 +GPP_H23 (0x5B,0x2E) 0x44000300 0x0000002b 0x00000000 0x00000000 +GPP_H24 (0x5B,0x30) 0x44000300 0x0000002c 0x00000000 0x00000000 +GPP_A0 (0x5B,0x38) 0x44000700 0x0003c030 0x00000000 0x00000000 +GPP_A1 (0x5B,0x3A) 0x44000201 0x00000031 0x00000000 0x00000000 +GPP_A2 (0x5B,0x3C) 0x44000201 0x00000032 0x00000000 0x00000000 +GPP_A3 (0x5B,0x3E) 0x44000201 0x00000033 0x00000000 0x00000000 +GPP_A4 (0x5B,0x40) 0x44000201 0x00000034 0x00000000 0x00000000 +GPP_A5 (0x5B,0x42) 0x44000201 0x00000035 0x00000000 0x00000000 +GPP_A6 (0x5B,0x44) 0x44000201 0x00000036 0x00000000 0x00000000 +GPP_A7 (0x5B,0x46) 0x44000201 0x00000037 0x00000000 0x00000000 +GPP_A8 (0x5B,0x48) 0x44000702 0x00000038 0x00000000 0x00000000 +GPP_A9 (0x5B,0x4A) 0x44000602 0x00000039 0x00000000 0x00000000 +GPP_A10 (0x5B,0x4C) 0x44000700 0x0003f03a 0x00000000 0x00000000 +GPP_A11 (0x5B,0x4E) 0x44000700 0x0003f03b 0x00000000 0x00000000 +GPP_A12 (0x5B,0x50) 0x40000300 0x00003c00 0x00000000 0x00000000 +GPP_A13 (0x5B,0x52) 0x40000b02 0x00003c00 0x00000000 0x00000000 +GPP_A14 (0x5B,0x54) 0x40001302 0x00003c00 0x00000000 0x00000000 +GPP_A15 (0x5B,0x56) 0x44000700 0x0003f071 0x00000000 0x00000000 +GPP_A16 (0x5B,0x58) 0x44000702 0x0003f072 0x00000000 0x00000000 +GPP_A17 (0x5B,0x5A) 0x44000700 0x0003f073 0x00000000 0x00000000 +GPP_S0 (0x5C,0x00) 0x44000201 0x01c00019 0x06000000 0x00000000 +GPP_S1 (0x5C,0x02) 0x44000201 0x01c0001a 0x06000000 0x00000000 +GPP_S2 (0x5C,0x04) 0x44000201 0x01c0001b 0x06000000 0x00000000 +GPP_S3 (0x5C,0x06) 0x44000201 0x01c0001c 0x06000000 0x00000000 +GPP_S4 (0x5C,0x08) 0x44000201 0x01c0001d 0x06000000 0x00000000 +GPP_S5 (0x5C,0x0A) 0x44000201 0x01c0001e 0x06000000 0x00000000 +GPP_S6 (0x5C,0x0C) 0x44000201 0x01c0001f 0x06000000 0x00000000 +GPP_S7 (0x5C,0x0E) 0x44000201 0x01c00020 0x06000000 0x00000000 +GPP_B0 (0x5D,0x00) 0x04000702 0x0003c042 0x00000000 0x00000000 +GPP_B1 (0x5D,0x02) 0x04000702 0x0003c043 0x00000000 0x00000000 +GPP_B2 (0x5D,0x04) 0x44000201 0x00000044 0x00000000 0x00000000 +GPP_B3 (0x5D,0x06) 0x44000201 0x00000045 0x00000000 0x00000000 +GPP_B4 (0x5D,0x08) 0x44000201 0x00000046 0x00000000 0x00000000 +GPP_B5 (0x5D,0x0A) 0x44000201 0x00000047 0x00000000 0x00000000 +GPP_B6 (0x5D,0x0C) 0x84000200 0x00000048 0x00000000 0x00000000 +GPP_B7 (0x5D,0x0E) 0x44000201 0x00000049 0x00000000 0x00000000 +GPP_B8 (0x5D,0x10) 0x44000201 0x0000004a 0x00000000 0x00000000 +GPP_B9 (0x5D,0x12) 0x84000201 0x0000004b 0x00000000 0x00000000 +GPP_B10 (0x5D,0x14) 0x84000201 0x0000004c 0x00000000 0x00000000 +GPP_B11 (0x5D,0x16) 0x44000300 0x0000004d 0x00000000 0x00000000 +GPP_B12 (0x5D,0x18) 0x44000700 0x0003c04e 0x00000000 0x00000000 +GPP_B13 (0x5D,0x1A) 0x44000700 0x0003c04f 0x00000000 0x00000000 +GPP_B14 (0x5D,0x1C) 0x44000a02 0x00024050 0x00000000 0x00000000 +GPP_B15 (0x5D,0x1E) 0x44000300 0x00000051 0x00000000 0x00000000 +GPP_B16 (0x5D,0x20) 0x44000201 0x00000052 0x00000000 0x00000000 +GPP_B17 (0x5D,0x22) 0x44000201 0x00000053 0x00000000 0x00000000 +GPP_B18 (0x5D,0x24) 0x44000201 0x00000054 0x00000000 0x00000000 +GPP_B19 (0x5D,0x26) 0x44000201 0x00000055 0x00000000 0x00000000 +GPP_B20 (0x5D,0x28) 0x44000300 0x00000056 0x00000000 0x00000000 +GPP_B21 (0x5D,0x2A) 0x84000200 0x00000057 0x00000000 0x00000000 +GPP_B22 (0x5D,0x2C) 0x44000201 0x00000058 0x00000000 0x00000000 +GPP_B23 (0x5D,0x2E) 0x44000201 0x00000059 0x00000000 0x00000000 +GPP_B24 (0x5D,0x30) 0x44000201 0x0003c05a 0x00000000 0x00000000 +GPP_B25 (0x5D,0x32) 0x44000201 0x0003c05b 0x00000000 0x00000000 +GPP_D0 (0x5D,0x36) 0x84000201 0x0000005c 0x00000000 0x00000000 +GPP_D1 (0x5D,0x38) 0x44000201 0x0000005d 0x00000000 0x00000000 +GPP_D2 (0x5D,0x3A) 0x44000201 0x0000005e 0x00000000 0x00000000 +GPP_D3 (0x5D,0x3C) 0x44000201 0x0000005f 0x00000000 0x00000000 +GPP_D4 (0x5D,0x3E) 0x44000201 0x00000060 0x00000000 0x00000000 +GPP_D5 (0x5D,0x40) 0x44000201 0x00000061 0x00000000 0x00000000 +GPP_D6 (0x5D,0x42) 0x44000201 0x00000062 0x00000000 0x00000000 +GPP_D7 (0x5D,0x44) 0x44000201 0x00000063 0x00000000 0x00000000 +GPP_D8 (0x5D,0x46) 0x44000201 0x00000064 0x00000000 0x00000000 +GPP_D9 (0x5D,0x48) 0x44000201 0x00000065 0x00000000 0x00000000 +GPP_D10 (0x5D,0x4A) 0x44000600 0x0003c066 0x00000000 0x00000000 +GPP_D11 (0x5D,0x4C) 0x44000700 0x0003fc67 0x00000000 0x00000000 +GPP_D12 (0x5D,0x4E) 0x44000600 0x0003fc68 0x00000000 0x00000000 +GPP_D13 (0x5D,0x50) 0x44000700 0x0003fc69 0x00000000 0x00000000 +GPP_D14 (0x5D,0x52) 0x44000201 0x0000006a 0x00000000 0x00000000 +GPP_D15 (0x5D,0x54) 0x44000300 0x0000006b 0x00000000 0x00000000 +GPP_D16 (0x5D,0x56) 0x44000700 0x0003c06c 0x00000000 0x00000000 +GPP_D17 (0x5D,0x58) 0x44000201 0x0003c06d 0x00000000 0x00000000 +GPP_D18 (0x5D,0x5A) 0x84000700 0x0000006e 0x00000000 0x00000000 +GPP_D19 (0x5D,0x5C) 0x84000201 0x0000006f 0x00000000 0x00000000 +GPP_D20 (0x5D,0x5E) 0x44000201 0x00000070 0x00000000 0x00000000 +GPP_D21 (0x5D,0x60) 0x44000201 0x0003c071 0x00000000 0x00000000 +GPP_D22 (0x5D,0x62) 0x44000700 0x0003fc72 0x00000000 0x00000000 +GPP_D23 (0x5D,0x64) 0x44000702 0x0003fc73 0x00000000 0x00000000 +GPP_D24 (0x5D,0x66) 0x44000201 0x0003c074 0x00000000 0x00000000 +GPP_D25 (0x5D,0x68) 0x44000201 0x0003c075 0x00000000 0x00000000 +## HDAUDIO ## +hdaudioC0D0 + vendor_name: Realtek + chip_name: ALC245 + vendor_id: 0x10ec0245 + subsystem_id: 0x15582a00 + revision_id: 0x100001 + 0x12: 0x90a60130 + 0x13: 0x40000000 + 0x14: 0x411111f0 + 0x17: 0x90170110 + 0x18: 0x411111f0 + 0x19: 0x411111f0 + 0x1a: 0x411111f0 + 0x1b: 0x411111f0 + 0x1d: 0x41789b2d + 0x1e: 0x411111f0 + 0x21: 0x04211020 +hdaudioC0D2 + vendor_name: Intel + chip_name: Panther Lake HDMI + vendor_id: 0x80862822 + subsystem_id: 0x80860101 + revision_id: 0x100000 + 0x04: 0x18560010 + 0x06: 0x18560010 + 0x08: 0x18560010 + 0x0a: 0x18560010 + 0x0b: 0x18560010 + 0x0c: 0x18560010 + 0x0d: 0x18560010 + 0x0e: 0x18560010 + 0x0f: 0x18560010 diff --git a/models/lemp14/coreboot.config b/models/lemp14/coreboot.config new file mode 100644 index 00000000..dd652224 --- /dev/null +++ b/models/lemp14/coreboot.config @@ -0,0 +1,23 @@ +CONFIG_VENDOR_SYSTEM76=y +CONFIG_BOARD_SYSTEM76_LEMP14=y +CONFIG_CCACHE=y +CONFIG_CONSOLE_SERIAL=n +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/PantherLakeFspBinPkg/Fsp.fd" +CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/PantherLakeFspBinPkg/Include" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom" +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom" +CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom" +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)" +CONFIG_POST_IO=n +CONFIG_SMMSTORE=y +CONFIG_SMMSTORE_V2=y +CONFIG_TPM_PPI=y +CONFIG_USE_OPTION_TABLE=y +CONFIG_VALIDATE_INTEL_DESCRIPTOR=y +#CONFIG_CONSOLE_SYSTEM76_EC=y diff --git a/models/lemp14/ec.config b/models/lemp14/ec.config new file mode 100644 index 00000000..5ccb1d9a --- /dev/null +++ b/models/lemp14/ec.config @@ -0,0 +1 @@ +BOARD=system76/lemp14 diff --git a/models/lemp14/ecspy.txt b/models/lemp14/ecspy.txt new file mode 100644 index 00000000..412d361e --- /dev/null +++ b/models/lemp14/ecspy.txt @@ -0,0 +1,113 @@ +id 5570 rev 7 +A0: data 0 mirror 0 pot 0 control 82 +A1: data 1 mirror 1 pot 0 control 80 +A2: data 0 mirror 0 pot 0 control 00 +A3: data 1 mirror 1 pot 0 control 40 +A4: data 1 mirror 1 pot 0 control 44 +A5: data 0 mirror 0 pot 0 control 00 +A6: data 0 mirror 0 pot 0 control 00 +A7: data 0 mirror 0 pot 0 control 40 +B0: data 0 mirror 0 pot 0 control 84 +B1: data 1 mirror 1 pot 0 control 84 +B2: data 1 mirror 1 pot 0 control 80 +B3: data 1 mirror 1 pot 0 control 80 +B4: data 1 mirror 1 pot 0 control 40 +B5: data 1 mirror 1 pot 0 control 80 +B6: data 1 mirror 1 pot 0 control 44 +B7: data 1 mirror 1 pot 0 control 80 +C0: data 1 mirror 1 pot 0 control 80 +C1: data 1 mirror 1 pot 0 control 04 +C2: data 1 mirror 1 pot 0 control 04 +C3: data 0 mirror 0 pot 0 control 04 +C4: data 0 mirror 0 pot 0 control 84 +C5: data 0 mirror 0 pot 0 control 04 +C6: data 1 mirror 1 pot 0 control 80 +C7: data 1 mirror 1 pot 0 control 44 +D0: data 1 mirror 1 pot 0 control 40 +D1: data 1 mirror 1 pot 0 control 44 +D2: data 1 mirror 1 pot 0 control 00 +D3: data 1 mirror 1 pot 0 control 80 +D4: data 1 mirror 1 pot 0 control 40 +D5: data 1 mirror 1 pot 0 control 40 +D6: data 1 mirror 1 pot 0 control 02 +D7: data 0 mirror 0 pot 0 control 80 +E0: data 1 mirror 1 pot 0 control 04 +E1: data 0 mirror 0 pot 0 control 80 +E2: data 1 mirror 1 pot 0 control 80 +E3: data 1 mirror 1 pot 0 control 40 +E4: data 1 mirror 1 pot 0 control 40 +E5: data 1 mirror 1 pot 0 control 40 +E6: data 0 mirror 0 pot 0 control 80 +E7: data 1 mirror 1 pot 0 control 04 +F0: data 0 mirror 0 pot 0 control 44 +F1: data 1 mirror 1 pot 0 control 40 +F2: data 1 mirror 1 pot 0 control 44 +F3: data 1 mirror 1 pot 0 control 44 +F4: data 1 mirror 1 pot 0 control 04 +F5: data 1 mirror 1 pot 0 control 04 +F6: data 1 mirror 1 pot 0 control 00 +F7: data 1 mirror 1 pot 0 control 80 +G0: data 0 mirror 0 pot 0 control 80 +G1: data 1 mirror 1 pot 0 control 80 +G2: data 1 mirror 1 pot 0 control 80 +G3: data 0 mirror 0 pot 0 control 00 +G4: data 0 mirror 0 pot 0 control 00 +G5: data 0 mirror 0 pot 0 control 00 +G6: data 0 mirror 0 pot 0 control 40 +G7: data 0 mirror 0 pot 0 control 00 +H0: data 1 mirror 1 pot 0 control 80 +H1: data 1 mirror 1 pot 0 control 80 +H2: data 0 mirror 0 pot 0 control 44 +H3: data 1 mirror 1 pot 0 control 44 +H4: data 1 mirror 1 pot 0 control 44 +H5: data 0 mirror 0 pot 0 control 40 +H6: data 1 mirror 1 pot 0 control 40 +H7: data 1 mirror 1 pot 0 control 40 +I0: data 0 mirror 0 pot 0 control 00 +I1: data 0 mirror 0 pot 0 control 00 +I2: data 1 mirror 1 pot 0 control 84 +I3: data 0 mirror 0 pot 0 control 00 +I4: data 0 mirror 0 pot 0 control 00 +I5: data 1 mirror 1 pot 0 control 44 +I6: data 0 mirror 0 pot 0 control 00 +I7: data 0 mirror 0 pot 0 control 00 +J0: data 0 mirror 0 pot 0 control 80 +J1: data 1 mirror 1 pot 0 control 40 +J2: data 0 mirror 0 pot 0 control 00 +J3: data 1 mirror 1 pot 0 control 80 +J4: data 1 mirror 1 pot 0 control 40 +J5: data 1 mirror 1 pot 0 control 80 +J6: data 0 mirror 0 pot 0 control 44 +J7: data 0 mirror 0 pot 0 control 80 +M0: data 1 mirror 1 control 06 +M1: data 1 mirror 1 control 06 +M2: data 1 mirror 1 control 06 +M3: data 1 mirror 1 control 06 +M4: data 0 mirror 0 control 06 +M5: data 1 mirror 1 control 00 +M6: data 0 mirror 0 control 86 +M7: data 0 mirror 0 control 00 +GCR: 0x04 +GCR1: 0x00 +GCR2: 0x10 +GCR3: 0x40 +GCR4: 0x00 +GCR5: 0x00 +GCR6: 0x00 +GCR7: 0x00 +GCR8: 0x10 +GCR9: 0x20 +GCR10: 0x02 +GCR11: 0x00 +GCR12: 0x00 +GCR13: 0x00 +GCR14: 0x00 +GCR15: 0x10 +GCR16: 0x00 +GCR17: 0x00 +GCR18: 0x00 +GCR19: 0x81 +GCR20: 0x80 +GCR21: 0x66 +GCR22: 0x80 +GCR23: 0x01 diff --git a/models/lemp14/edk2.config b/models/lemp14/edk2.config new file mode 100644 index 00000000..b2378083 --- /dev/null +++ b/models/lemp14/edk2.config @@ -0,0 +1,9 @@ +BOOTLOADER=COREBOOT +DISABLE_SERIAL_TERMINAL=TRUE +PLATFORM_BOOT_TIMEOUT=2 +PS2_KEYBOARD_ENABLE=TRUE +SECURE_BOOT_ENABLE=TRUE +SERIAL_DRIVER_ENABLE=FALSE +SHELL_TYPE=NONE +TPM_ENABLE=TRUE +#SYSTEM76_EC_LOGGING=TRUE diff --git a/models/lemp14/fd.rom b/models/lemp14/fd.rom new file mode 100644 index 00000000..28b8428b --- /dev/null +++ b/models/lemp14/fd.rom @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:051ca696f1e565e2bfa3025442742d6bc7116ee5a64f91ad0af05a0a3680795d +size 16384 diff --git a/models/lemp14/gpio.c b/models/lemp14/gpio.c new file mode 100644 index 00000000..85b59c81 --- /dev/null +++ b/models/lemp14/gpio.c @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A1, 1, DEEP), + PAD_CFG_GPO(GPP_A2, 1, DEEP), + PAD_CFG_GPO(GPP_A3, 1, DEEP), + PAD_CFG_GPO(GPP_A4, 1, DEEP), + PAD_CFG_GPO(GPP_A5, 1, DEEP), + PAD_CFG_GPO(GPP_A6, 1, DEEP), + PAD_CFG_GPO(GPP_A7, 1, DEEP), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), + PAD_NC(GPP_A12, NATIVE), + PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF2), + _PAD_CFG_STRUCT(GPP_A14, 0x40001300, 0x3c00), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A17, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B0, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_B1, NONE, PWROK, NF1), + PAD_CFG_GPO(GPP_B2, 1, DEEP), + PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_GPO(GPP_B5, 1, DEEP), + PAD_CFG_GPO(GPP_B6, 0, PLTRST), + PAD_CFG_GPO(GPP_B7, 1, DEEP), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_CFG_GPO(GPP_B9, 1, PLTRST), + PAD_CFG_GPO(GPP_B10, 1, PLTRST), + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), + PAD_NC(GPP_B15, NONE), + PAD_CFG_GPO(GPP_B16, 1, DEEP), + PAD_CFG_GPO(GPP_B17, 1, DEEP), + PAD_CFG_GPO(GPP_B18, 1, DEEP), + PAD_CFG_GPO(GPP_B19, 1, DEEP), + PAD_NC(GPP_B20, NONE), + PAD_CFG_GPO(GPP_B21, 0, PLTRST), + PAD_CFG_GPO(GPP_B22, 1, DEEP), + PAD_CFG_GPO(GPP_B23, 1, DEEP), + PAD_CFG_GPO(GPP_B24, 1, DEEP), + PAD_CFG_GPO(GPP_B25, 1, DEEP), + PAD_CFG_NF(GPP_C0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C1, UP_20K, DEEP, NF1), + PAD_CFG_GPO(GPP_C2, 1, DEEP), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_C5, 1, DEEP), + PAD_NC(GPP_C6, NONE), + PAD_NC(GPP_C7, NONE), + PAD_CFG_GPO(GPP_C8, 1, DEEP), + PAD_CFG_GPO(GPP_C9, 1, DEEP), + PAD_CFG_GPO(GPP_C10, 1, DEEP), + PAD_CFG_GPO(GPP_C11, 1, DEEP), + PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_C15, 1, DEEP), + PAD_CFG_NF(GPP_C16, NONE, TODO_0xc4000700, NF1), + PAD_CFG_NF(GPP_C17, NONE, TODO_0xc4000700, NF1), + PAD_CFG_GPO(GPP_C18, 1, DEEP), + PAD_CFG_GPO(GPP_C19, 1, DEEP), + PAD_CFG_GPO(GPP_C20, 1, DEEP), + PAD_CFG_GPO(GPP_C21, 1, DEEP), + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), + PAD_CFG_GPO(GPP_D0, 1, PLTRST), + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPO(GPP_D2, 1, DEEP), + PAD_CFG_GPO(GPP_D3, 1, DEEP), + PAD_CFG_GPO(GPP_D4, 1, DEEP), + PAD_CFG_GPO(GPP_D5, 1, DEEP), + PAD_CFG_GPO(GPP_D6, 1, DEEP), + PAD_CFG_GPO(GPP_D7, 1, DEEP), + PAD_CFG_GPO(GPP_D8, 1, DEEP), + PAD_CFG_GPO(GPP_D9, 1, DEEP), + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), + PAD_CFG_GPO(GPP_D14, 1, DEEP), + PAD_NC(GPP_D15, NONE), + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_D17, 1, DEEP), + PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + PAD_CFG_GPO(GPP_D20, 1, DEEP), + PAD_CFG_GPO(GPP_D21, 1, DEEP), + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), + PAD_CFG_GPO(GPP_D24, 1, DEEP), + PAD_CFG_GPO(GPP_D25, 1, DEEP), + _PAD_CFG_STRUCT(GPP_E1, 0x42880100, 0x0000), + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO(GPP_E4, 1, DEEP), + PAD_CFG_GPO(GPP_E5, 1, DEEP), + PAD_CFG_GPO(GPP_E6, 1, DEEP), + PAD_CFG_GPO(GPP_E7, 1, DEEP), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_CFG_GPO(GPP_E10, 1, DEEP), + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + _PAD_CFG_STRUCT(GPP_E12, 0x44002300, 0x0000), + _PAD_CFG_STRUCT(GPP_E13, 0x44002300, 0x0000), + PAD_CFG_GPI(GPP_E14, NONE, DEEP), + PAD_CFG_GPI(GPP_E15, NONE, DEEP), + PAD_CFG_GPO(GPP_E16, 1, DEEP), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), + PAD_CFG_GPO(GPP_E18, 1, DEEP), + PAD_CFG_GPO(GPP_E19, 1, DEEP), + PAD_CFG_GPO(GPP_E20, 1, DEEP), + PAD_CFG_NF(GPP_E21, NONE, PWROK, NF1), + PAD_CFG_GPO(GPP_E22, 1, DEEP), + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + PAD_CFG_GPO(GPP_F6, 1, DEEP), + PAD_CFG_GPO(GPP_F7, 1, DEEP), + PAD_CFG_GPO(GPP_F8, 1, DEEP), + PAD_CFG_GPI(GPP_F9, NONE, DEEP), + PAD_CFG_GPO(GPP_F10, 1, DEEP), + PAD_CFG_GPO(GPP_F11, 1, DEEP), + _PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000), + _PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000), + PAD_CFG_GPO(GPP_F14, 1, DEEP), + PAD_CFG_GPO(GPP_F15, 1, DEEP), + PAD_CFG_GPO(GPP_F16, 1, PLTRST), + PAD_CFG_GPO(GPP_F17, 1, DEEP), + _PAD_CFG_STRUCT(GPP_F18, 0x80800100, 0x0000), + PAD_CFG_GPO(GPP_F19, 1, DEEP), + PAD_CFG_GPO(GPP_F20, 1, DEEP), + PAD_CFG_GPO(GPP_F21, 1, DEEP), + PAD_CFG_GPO(GPP_F22, 1, DEEP), + PAD_CFG_GPO(GPP_F23, 1, DEEP), + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H6, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H9, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_H10, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_H11, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_H12, TODO_0x2400, DEEP, NF1), + PAD_CFG_NF(GPP_H13, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_H15, 1, DEEP), + PAD_CFG_GPO(GPP_H16, 1, DEEP), + PAD_CFG_GPO(GPP_H17, 1, DEEP), + PAD_NC(GPP_H18, NONE), + _PAD_CFG_STRUCT(GPP_H19, 0x44000601, 0x0000), + _PAD_CFG_STRUCT(GPP_H20, 0x44000601, 0x0000), + PAD_CFG_GPO(GPP_H21, 1, DEEP), + PAD_CFG_GPO(GPP_H22, 1, DEEP), + PAD_NC(GPP_H23, NONE), + PAD_NC(GPP_H24, NONE), + PAD_CFG_GPO(GPP_S0, 1, DEEP), + PAD_CFG_GPO(GPP_S1, 1, DEEP), + PAD_CFG_GPO(GPP_S2, 1, DEEP), + PAD_CFG_GPO(GPP_S3, 1, DEEP), + PAD_CFG_GPO(GPP_S4, 1, DEEP), + PAD_CFG_GPO(GPP_S5, 1, DEEP), + PAD_CFG_GPO(GPP_S6, 1, DEEP), + PAD_CFG_GPO(GPP_S7, 1, DEEP), + PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_V1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_V2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_V4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_V5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_V6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_V7, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_V8, 1, DEEP), + PAD_CFG_GPO(GPP_V9, 1, DEEP), + PAD_CFG_GPO(GPP_V10, 1, DEEP), + PAD_CFG_GPO(GPP_V11, 1, DEEP), + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_V13, 0x44000601, 0x0000), + _PAD_CFG_STRUCT(GPP_V14, 0x44000601, 0x0000), + _PAD_CFG_STRUCT(GPP_V15, 0x44000601, 0x0000), + PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_V17, 1, DEEP), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/models/lemp14/hda_verb.c b/models/lemp14/hda_verb.c new file mode 100644 index 00000000..1eadb793 --- /dev/null +++ b/models/lemp14/hda_verb.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x15582a00, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15582a00), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41789b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* Intel, PantherLakeHDMI */ + 0x80862822, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_RESET(1), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/models/lemp14/me.rom b/models/lemp14/me.rom new file mode 100644 index 00000000..c097f3fe --- /dev/null +++ b/models/lemp14/me.rom @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:eaee9c54daabe841cb4b9b8df75af3e54784c8f013c7ce71bfd7433b5c0d0f8a +size 9396224 diff --git a/models/lemp14/microcode.rom b/models/lemp14/microcode.rom new file mode 100644 index 00000000..ef595bc2 --- /dev/null +++ b/models/lemp14/microcode.rom @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5ab294764746a087abcc7144eea230a5a187cd010a4c1bdcf6f356bac75ad9b9 +size 162816 diff --git a/models/lemp14/vbt.rom b/models/lemp14/vbt.rom new file mode 100644 index 00000000..4f1404ec --- /dev/null +++ b/models/lemp14/vbt.rom @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cb424bc2cb9ca6ed8c85844e202a44d9a4a5b9dce847bd8e768153c36271ca70 +size 7680 diff --git a/scripts/generate.sh b/scripts/generate.sh index 6b967e73..9d32cb8e 100755 --- a/scripts/generate.sh +++ b/scripts/generate.sh @@ -71,24 +71,30 @@ then fi # Get the Video BIOS Table and GOP driver for Intel systems -if sudo [ -e /sys/kernel/debug/dri/1/i915_vbt ] -then - sudo cat /sys/kernel/debug/dri/1/i915_vbt > "${MODEL_DIR}/vbt.rom" +for dri_id in 0 1 +do + vbt_path="/sys/kernel/debug/dri/${dri_id}/i915_vbt" + if sudo [ -e "${vbt_path}" ] + then + sudo cat "${vbt_path}" > "${MODEL_DIR}/vbt.rom" - INTEL_GOP_DRIVER_GUID="7755CA7B-CA8F-43C5-889B-E1F59A93D575" - EXTRACT_DIR="extract" + INTEL_GOP_DRIVER_GUID="7755CA7B-CA8F-43C5-889B-E1F59A93D575" + EXTRACT_DIR="extract" - if [ -n "${BIOS_IMAGE}" ] - then - if "${SCRIPT_DIR}/extract.sh" "${BIOS_IMAGE}" "${INTEL_GOP_DRIVER_GUID}" -o "${EXTRACT_DIR}" > /dev/null + if [ -n "${BIOS_IMAGE}" ] then - cp -v "$(find "${EXTRACT_DIR}" | grep IntelGopDriver | grep PE32 | grep body.bin)" "${MODEL_DIR}/IntelGopDriver.efi" - rm -rf "${EXTRACT_DIR}" - else - echo "IntelGopDriver not present in firmware image" + if "${SCRIPT_DIR}/extract.sh" "${BIOS_IMAGE}" "${INTEL_GOP_DRIVER_GUID}" -o "${EXTRACT_DIR}" > /dev/null + then + cp -v "$(find "${EXTRACT_DIR}" | grep IntelGopDriver | grep PE32 | grep body.bin)" "${MODEL_DIR}/IntelGopDriver.efi" + rm -rf "${EXTRACT_DIR}" + else + echo "IntelGopDriver not present in firmware image" + fi fi + + break fi -fi +done # XXX: More reliable way to determine if system has an EC? DMI_CHASSIS_TYPE=$(cat /sys/class/dmi/id/chassis_type) @@ -100,7 +106,7 @@ then cp "${EC_ROM}" "${MODEL_DIR}/ec.rom" else echo "Generating output for System76 EC firmware" - pushd ec/ecspy + pushd ec/tools/ecspy cargo build --release # TODO: Set backlights and fans to max and restore after sudo target/release/ecspy > "${MODEL_DIR}/ecspy.txt" diff --git a/tools/coreboot-collector b/tools/coreboot-collector index b0426101..d7d99128 160000 --- a/tools/coreboot-collector +++ b/tools/coreboot-collector @@ -1 +1 @@ -Subproject commit b0426101d6557b9bb0d5b89f773c657520dbdbd0 +Subproject commit d7d99128acf2f28e95056e60d2767697bfe7a91f