Merge pull request #29 from tancheng/utilization

Report tile utilization with DVFS info

Author: tancheng

.github/workflows/cmake.yml

@@ -36,20 +36,25 @@ jobs:
       # Build your program with the given configuration
       run: make
 
-    - name: Test Nonlinear Feature
-      working-directory: ${{github.workspace}}/test/nonlinear_test
+    # Testing.
+    - name: Test fusion via Nonlinear kernel
+      working-directory: ${{github.workspace}}/test/nonlinear
       run: |
         clang-12 -emit-llvm -O3 -fno-unroll-loops -fno-vectorize -o nonlinear_test.bc -c nonlinear_test.cpp
-        opt-12 -load ../../build/src/libmapperPass.so -load ${LOCALBASE}/lib/libLLVMSupport.so -load ${LOCALBASE}/lib/libclangAST.so -mapperPass -verify -mapperPass nonlinear_test.bc
-        sh test.sh
+        opt-12 -load ../../build/src/libmapperPass.so -mapperPass nonlinear_test.bc
+        sh verify.sh
 
-    - name: Test Idiv Feature
-      working-directory: ${{github.workspace}}/test/idiv_test
+    - name: Test split via Idiv kernel
+      working-directory: ${{github.workspace}}/test/idiv
       run: |
         clang-12 -emit-llvm -O3 -fno-unroll-loops -fno-vectorize -o idiv_test.bc -c idiv_test.cpp 
         opt-12 -load ../../build/src/libmapperPass.so -mapperPass idiv_test.bc
-        sh test.sh
- 
+        sh verify.sh
 
+    - name: Test DVFS
+      working-directory: ${{github.workspace}}/test/dvfs
+      run: |
+        clang-12 -emit-llvm -O3 -fno-unroll-loops -fno-vectorize -o kernel.bc -c kernel.cpp
+        opt-12 -load ../../build/src/libmapperPass.so -mapperPass kernel.bc > trace.log
+        sh verify.sh
 
-      

src/CGRA.cpp

@@ -16,12 +16,15 @@ using json = nlohmann::json;
 
 CGRA::CGRA(int t_rows, int t_columns, bool t_diagonalVectorization,
 	   bool t_heterogeneity, bool t_parameterizableCGRA,
-	   map<string, list<int>*>* t_additionalFunc) {
+	   map<string, list<int>*>* t_additionalFunc,
+	   bool t_supportDVFS, int t_DVFSIslandDim) {
   m_rows = t_rows;
   m_columns = t_columns;
   m_FUCount = t_rows * t_columns;
+  m_supportDVFS = t_supportDVFS;
+  m_DVFSIslandDim = t_DVFSIslandDim;
   m_supportComplex = new list<string>();
-  m_supportCall    = new list<string>();
+  m_supportCall = new list<string>();
   nodes = new CGRANode**[t_rows];
 
   // Initialize the m_supportComplex & m_supportCall list.
@@ -185,7 +188,6 @@ CGRA::CGRA(int t_rows, int t_columns, bool t_diagonalVectorization,
       }
     }
 
-
     // Enable the heterogeneity.
     if (t_heterogeneity) {
       // for (int r=0; r<t_rows; ++r) {
@@ -240,6 +242,27 @@ CGRA::CGRA(int t_rows, int t_columns, bool t_diagonalVectorization,
     disableSpecificConnections();
   }
 
+  if (t_supportDVFS) {
+    for (int r=0; r<t_rows; ++r) {
+      for (int c=0; c<t_columns; ++c) {
+        nodes[r][c]->enableDVFS();
+	int DVFSIslandX = c / t_DVFSIslandDim;
+	int DVFSIslandY = r / t_DVFSIslandDim;
+	int DVFSIslandId = DVFSIslandX + DVFSIslandY * t_columns / t_DVFSIslandDim;
+        nodes[r][c]->setDVFSIsland(DVFSIslandX, DVFSIslandY, DVFSIslandId);
+	// Islandize the CGRA nodes. In the prototype, each set of 2x2 nodes are
+        // grouped as one island. For example, a 4x4 CGRA has 2x2 islands, the
+        // tiles of (0, 2), (0, 3), (1, 2), (1, 3) are viewd as the (0, 1) island.
+	if (m_DVFSIslands.find(DVFSIslandId) != m_DVFSIslands.end()) {
+          m_DVFSIslands[DVFSIslandId].push_back(nodes[r][c]);
+	} else {
+          vector<CGRANode*> tiles{nodes[r][c]};
+          m_DVFSIslands[DVFSIslandId] = tiles;
+	}
+      }
+    }
+  }
+
 /*
   cout<<"[connection] horizontal and vertical."<<endl;
   // Connect the CGRA nodes with diagonal links.
@@ -357,3 +380,17 @@ CGRALink* CGRA::getLink(CGRANode* t_n1, CGRANode* t_n2) {
 int CGRA::getLinkCount() {
   return m_LinkCount;
 }
+
+map<int, vector<CGRANode*>> CGRA::getDVFSIslands() {
+  return m_DVFSIslands;
+}
+
+void CGRA::syncDVFSIsland(CGRANode* t_node) {
+  int islandID = t_node->getDVFSIslandID();
+  for (auto& nodeWithinIsland : m_DVFSIslands[islandID]) {
+    nodeWithinIsland->setDVFSLatencyMultiple(t_node->getDVFSLatencyMultiple());
+    nodeWithinIsland->syncDVFS();
+    cout << "[cheng] synced for node: " << nodeWithinIsland->getID() << "; check synced: " << nodeWithinIsland->isSynced() << "; addr: " << nodeWithinIsland << endl;
+  }
+}
+

src/CGRA.h

@@ -22,12 +22,15 @@ class CGRA {
     int m_LinkCount;
     int m_rows;
     int m_columns;
+    bool m_supportDVFS;
+    int m_DVFSIslandDim;
+    map<int, vector<CGRANode*>> m_DVFSIslands;
     list<string>* m_supportComplex;
     list<string>* m_supportCall;
     void disableSpecificConnections();
 
   public:
-    CGRA(int, int, bool, bool, bool, map<string, list<int>*>*);
+    CGRA(int, int, bool, bool, bool, map<string, list<int>*>*, bool, int);
     CGRANode ***nodes;
     CGRALink **links;
     int getFUCount();
@@ -40,6 +43,11 @@ class CGRA {
     void setBypassConstraint(int);
     void setCtrlMemConstraint(int);
     void setRegConstraint(int);
+    map<int, vector<CGRANode*>> getDVFSIslands();
+    // Aligns all the CGRA nodes within the same DVFS island to the
+    // same DVFS level based on the DVFS level of the given CGRA node.
+    void syncDVFSIsland(CGRANode*);
     list<string>* getSupportComplex();
     list<string>* getSupportCall();
 };
+

src/CGRALink.cpp

@@ -20,6 +20,7 @@ CGRALink::CGRALink(int t_linkId) {
   m_generatedOut = new bool[1];
   m_arrived = new bool[1];
   m_disabled = false;
+  m_mapped = false;
 }
 
 void CGRALink::setCtrlMemConstraint(int t_ctrlMemConstraint) {
@@ -52,6 +53,10 @@ void CGRALink::setID(int t_id) {
   m_id = t_id;
 }
 
+bool CGRALink::isMapped() {
+  return m_mapped;
+}
+
 void CGRALink::constructMRRG(int t_CGRANodeCount, int t_II) {
   m_II = t_II;
   m_cycleBoundary = t_CGRANodeCount*t_II*t_II;
@@ -152,7 +157,23 @@ bool CGRALink::canOccupy(DFGNode* t_srcDFGNode, CGRANode* t_srcCGRANode,
         m_generatedOut[t]) {
       return false;
     }
+  }
 
+  // Checks whether the DVFS long execution (low frequency indicates
+  // `pseudo` multi-cycle execution) is enabled. If enabled, only the
+  // last cycle (i.e., last pipe stage) can send out the data. This
+  // feature is used to mimic the asynchronous buffer on the link.
+  // if (getSrc()->isFrequencyLowered() && !getSrc()->isEndPipe(t_cycle, t_II)) {
+  // FIXME: this should be revised to align with the sync().
+  int cycle_in_II = (t_cycle+t_II) % t_II;
+  if (getDst()->isDVFSEnabled() and getDst()->getDVFSLatencyMultiple() > 1 and
+      cycle_in_II % getDst()->getDVFSLatencyMultiple() != 0) {
+  // if (getDst()->isDVFSEnabled() and getDst()->getDVFSLatencyMultiple() > 1 and
+  //     cycle_in_II % getDst()->getDVFSLatencyMultiple() == 1) {
+  //   // The output should be blocked by the low frequency computation.
+  //   // This should roughly model the behavior of the DVFS asynchronous
+  //   // buffer.
+    return false;
   }
 
   return true;
@@ -196,6 +217,7 @@ bool CGRALink::isReused(int t_cycle) {
 
 void CGRALink::occupy(DFGNode* t_srcDFGNode, int t_cycle, int duration,
     int t_II, bool t_isBypass, bool t_isGeneratedOut, bool t_isStaticElasticCGRA) {
+  m_mapped = true;
   int interval = t_II;
   if (t_isStaticElasticCGRA) {
     interval = 1;

src/CGRALink.h

@@ -32,6 +32,7 @@ class CGRALink
     int m_ctrlMemSize;
     int m_bypassConstraint;
     int m_currentCtrlMemItems;
+    bool m_mapped;
 
     int m_cycleBoundary;
     bool m_disabled;
@@ -66,6 +67,7 @@ class CGRALink
     void setBypassConstraint(int);
     int getBypassConstraint();
     void disable();
+    bool isMapped();
 };
 
 #endif