Introduce aarch64 board-specific config, plus GIC fixes (#915)

* New `arm_boards` crate: per-board definitions for aarch64 builds
  * The default is for QEMU's basic `virt` machine spec.
  * Currently, this specifies the number of CPUs, their IDs, and
    the interrupt controller configuration including one GIC
    redistributor base address per core.
  * The `gic` crate now uses this instead of defining its own
    internal configuration values specific to QEMU.
  * `multicore_bringup` now uses the list of `CpuId`s from
    the selected ARM board configuration.

* The redistributor initialization routine code now enables
  the dispatch of "1 of N"-distributed SPIs.
  * All CPUs' redistributors are now initialized by the
    bootstrap processor as part of `interrupts::init()`.

* Incorporates two fixes from #910:
  * Fix a bug in `get_spi_target` & `set_spi_target` where
    an atomic u32 read/write was used to manipulate a
    u64 MMIO register.
  * Introduce `Offset32` and `Offset64` types to distinguish
    32-bit and 64-bit registers more clearly.

Co-authored-by: Kevin Boos <[email protected]>

Author: NathanRoyer

Cargo.lock

@@ -0,0 +1,18 @@
+[package]
+authors = ["Nathan Royer <[email protected]>"]
+name = "arm_boards"
+description = "Board-specific configuration and definitions for aarch64 systems"
+version = "0.1.0"
+edition = "2021"
+
+[dependencies]
+cfg-if = "1.0.0"
+memory_structs = { path = "../memory_structs" }
+derive_more = "0.99.0"
+
+[features]
+default = [ "qemu_virt" ]
+qemu_virt = []
+
+[lib]
+crate-type = ["rlib"]

kernel/arm_boards/Cargo.toml

@@ -0,0 +1,36 @@
+//! Board configuration for QEMU's basic `virt` machine with 4 CPUs.
+
+use super::{
+    InterruptControllerConfig::GicV3, GicV3InterruptControllerConfig,
+    BoardConfig, mpidr::DefinedMpidrValue,
+};
+use memory_structs::PhysicalAddress;
+
+/// Generates an MPIDR value from a CPU's 0th affinity level.
+const fn cpu_id(aff0: u8) -> DefinedMpidrValue {
+    DefinedMpidrValue::new(0, 0, 0, aff0)
+}
+
+/// Generates a Redistributor base address from a CPU's 0th affinity level.
+const fn redist(aff0: usize) -> PhysicalAddress {
+    PhysicalAddress::new_canonical(0x080A0000 + 0x20000 * aff0)
+}
+
+pub const NUM_CPUS: usize = 4;
+pub static BOARD_CONFIG: BoardConfig = BoardConfig {
+    cpu_ids: [
+        cpu_id(0),
+        cpu_id(1),
+        cpu_id(2),
+        cpu_id(3),
+    ],
+    interrupt_controller: GicV3(GicV3InterruptControllerConfig {
+        distributor_base_address: PhysicalAddress::new_canonical(0x08000000),
+        redistributor_base_addresses: [
+            redist(0),
+            redist(1),
+            redist(2),
+            redist(3),
+        ],
+    }),
+};

kernel/arm_boards/src/boards/qemu_virt.rs

@@ -0,0 +1,3 @@
+//! Invalid board config file that throws a compile error if a board config wasn't selected.
+
+compile_error!("Please select a board config feature in the arm_boards crate");

kernel/arm_boards/src/boards/unselected.rs

@@ -0,0 +1,53 @@
+//! Configuration and definitions for specific boards on aarch64 systems.
+//!
+//! | Board Name | Num CPUs  | Interrupt Controller | Secondary CPU Startup Method |
+//! | ---------- | --------- | -------------------- | ---------------------------- |
+//! | qemu_virt  | 4         | GICv3                | PSCI                         |
+//!
+
+#![no_std]
+#![feature(const_trait_impl)]
+
+cfg_if::cfg_if! {
+if #[cfg(target_arch = "aarch64")] {
+
+use memory_structs::PhysicalAddress;
+
+#[derive(Debug, Copy, Clone)]
+pub struct GicV3InterruptControllerConfig {
+    pub distributor_base_address: PhysicalAddress,
+    pub redistributor_base_addresses: [PhysicalAddress; board::NUM_CPUS],
+}
+
+#[derive(Debug, Copy, Clone)]
+pub enum InterruptControllerConfig {
+    GicV3(GicV3InterruptControllerConfig),
+}
+
+/*
+TODO: multicore_bringup: wake secondary cores based on this:
+pub enum SecondaryCoresStartup {
+    Psci,
+}
+*/
+
+#[derive(Debug, Clone)]
+pub struct BoardConfig {
+    pub cpu_ids: [mpidr::DefinedMpidrValue; board::NUM_CPUS],
+    pub interrupt_controller: InterruptControllerConfig,
+}
+
+// by default & on x86_64, the default.rs file is used
+#[cfg_attr(feature = "qemu_virt", path = "boards/qemu_virt.rs")]
+#[cfg_attr(not(any(
+    feature = "qemu_virt",
+)), path = "boards/unselected.rs")]
+mod board;
+
+pub mod mpidr;
+
+pub use board::{NUM_CPUS, BOARD_CONFIG};
+
+
+} // end of cfg(target_arch = "aarch64")
+} // end of cfg_if

kernel/arm_boards/src/lib.rs

@@ -0,0 +1,25 @@
+use derive_more::{Display, Binary, Octal, LowerHex, UpperHex};
+
+/// A unique identifier for a CPU, hardcoded in `arm_boards`.
+#[derive(
+    Clone, Copy, Debug, Display, PartialEq, Eq, PartialOrd, Ord,
+    Hash, Binary, Octal, LowerHex, UpperHex,
+)]
+#[repr(transparent)]
+pub struct DefinedMpidrValue(u64);
+
+impl DefinedMpidrValue {
+    /// Returns the contained value
+    pub fn value(self) -> u64 {
+        self.0
+    }
+
+    /// Create an `MpidrValue` from its four affinity numbers
+    pub(crate) const fn new(aff3: u8, aff2: u8, aff1: u8, aff0: u8) -> Self {
+        let aff3 = (aff3 as u64) << 32;
+        let aff2 = (aff2 as u64) << 16;
+        let aff1 = (aff1 as u64) <<  8;
+        let aff0 = (aff0 as u64) <<  0;
+        Self(aff3 | aff2 | aff1 | aff0)
+    }
+}

kernel/arm_boards/src/mpidr.rs

@@ -8,14 +8,14 @@ edition = "2021"
 [dependencies]
 derive_more = "0.99.0"
 
-
 [target.'cfg(target_arch = "x86_64")'.dependencies]
 apic = { path = "../apic" }
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]
+irq_safety = { git = "https://github.com/theseus-os/irq_safety" }
+arm_boards = { path = "../arm_boards" }
 tock-registers = "0.7.0"
 cortex-a = "7.5.0"
-irq_safety = { git = "https://github.com/theseus-os/irq_safety" }
 
 [lib]
 crate-type = ["rlib"]

kernel/cpu/Cargo.toml

@@ -6,6 +6,7 @@ use derive_more::{Display, Binary, Octal, LowerHex, UpperHex};
 use irq_safety::RwLockIrqSafe;
 use core::fmt;
 use alloc::vec::Vec;
+use arm_boards::mpidr::DefinedMpidrValue;
 
 use super::CpuId;
 
@@ -89,14 +90,17 @@ impl MpidrValue {
         };
         (self.0 >> shift) as u8
     }
+}
+
+impl From<DefinedMpidrValue> for MpidrValue {
+    fn from(def_mpidr: DefinedMpidrValue) -> Self {
+        Self(def_mpidr.value())
+    }
+}
 
-    /// Create an `MpidrValue` from its four affinity numbers
-    pub fn new(aff3: u8, aff2: u8, aff1: u8, aff0: u8) -> Self {
-        let aff3 = (aff3 as u64) << 32;
-        let aff2 = (aff2 as u64) << 16;
-        let aff1 = (aff1 as u64) <<  8;
-        let aff0 = (aff0 as u64) <<  0;
-        Self(aff3 | aff2 | aff1 | aff0)
+impl From<DefinedMpidrValue> for CpuId {
+    fn from(def_mpidr: DefinedMpidrValue) -> Self {
+        Self::from(MpidrValue::from(def_mpidr))
     }
 }
 

kernel/cpu/src/aarch64.rs

@@ -12,3 +12,5 @@ zerocopy = "0.5.0"
 log = "0.4.8"
 
 memory = { path = "../memory" }
+cpu = { path = "../cpu" }
+arm_boards = { path = "../arm_boards" }

kernel/gic/Cargo.toml

@@ -7,17 +7,16 @@
 //! - Sending End-Of-Interrupts signals
 
 use super::GicRegisters;
-use super::U32BYTES;
 use super::Priority;
 use super::InterruptNumber;
 
 mod offset {
-    use super::U32BYTES;
-    pub const CTLR: usize = 0x00 / U32BYTES;
-    pub const PMR:  usize = 0x04 / U32BYTES;
-    pub const IAR:  usize = 0x0C / U32BYTES;
-    pub const RPR:  usize = 0x14 / U32BYTES;
-    pub const EOIR: usize = 0x10 / U32BYTES;
+    use crate::Offset32;
+    pub(crate) const CTLR: Offset32 = Offset32::from_byte_offset(0x00);
+    pub(crate) const PMR:  Offset32 = Offset32::from_byte_offset(0x04);
+    pub(crate) const IAR:  Offset32 = Offset32::from_byte_offset(0x0C);
+    pub(crate) const RPR:  Offset32 = Offset32::from_byte_offset(0x14);
+    pub(crate) const EOIR: Offset32 = Offset32::from_byte_offset(0x10);
 }
 
 // enable group 0