UefiPayloadPkg/PLatformHookLib: Set PcdSerialClockRate using HOB data

MrChromebox · MrChromebox · commit d05a6e577cf8 · 2024-09-18T14:18:16.000-05:00
Fixes serial output on platforms using coreboot and a non-default clock
rate such as AMD Picasso and newer.

Signed-off-by: Matt DeVillier &lt;matt.devillier@gmail.com&gt;
Change-Id: I91290397852176754e9a34ec6e5829044f41d15a
diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
@@ -94,6 +94,11 @@ PlatformHookSerialPortInitialize (
       return Status;
     }
 
+    Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo->ClockRate);
+    if (RETURN_ERROR (Status)) {
+      return Status;
+    }
+
     return RETURN_SUCCESS;
   }
 
diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
@@ -38,3 +38,4 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase    ## PRODUCES
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate        ## PRODUCES
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride  ## PRODUCES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate       ## PRODUCES

Original file line number	Diff line number	Diff line change
`@@ -94,6 +94,11 @@ PlatformHookSerialPortInitialize (`
`94`	`94`	`return Status;`
`95`	`95`	`}`
`96`	`96`
	`97`	`+ Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo->ClockRate);`
	`98`	`+ if (RETURN_ERROR (Status)) {`
	`99`	`+ return Status;`
	`100`	`+ }`
	`101`	`+`
`97`	`102`	`return RETURN_SUCCESS;`
`98`	`103`	`}`
`99`	`104`