Update docs

Author: github-actions[bot]

_sources/autoapi/tilelang/carver/arch/cdna/index.rst.txt

@@ -30,6 +30,9 @@ Module Contents
    Bases: :py:obj:`tilelang.carver.arch.arch_base.TileDevice`
 
 
+   Represents the architecture of a computing device, capturing various hardware specifications.
+
+
    .. py:attribute:: target
 
 

_sources/autoapi/tilelang/carver/arch/cpu/index.rst.txt

@@ -30,6 +30,9 @@ Module Contents
    Bases: :py:obj:`tilelang.carver.arch.arch_base.TileDevice`
 
 
+   Represents the architecture of a computing device, capturing various hardware specifications.
+
+
    .. py:attribute:: target
 
 

_sources/autoapi/tilelang/carver/arch/cuda/index.rst.txt

@@ -92,6 +92,9 @@ Module Contents
    Bases: :py:obj:`tilelang.carver.arch.arch_base.TileDevice`
 
 
+   Represents the architecture of a computing device, capturing various hardware specifications.
+
+
    .. py:attribute:: target
 
 

_sources/autoapi/tilelang/carver/roller/hint/index.rst.txt

@@ -307,12 +307,12 @@ Module Contents
 
 
    .. py:property:: raxis_order
-      :type: List[int]
+      :type: tilelang.carver.roller.rasterization.List[int]
 
 
 
    .. py:property:: step
-      :type: List[int]
+      :type: tilelang.carver.roller.rasterization.List[int]
 
 
 

_sources/autoapi/tilelang/carver/roller/policy/tensorcore/index.rst.txt

@@ -30,11 +30,15 @@ Module Contents
 
 .. py:data:: logger
 
-.. py:class:: TensorCorePolicy
+.. py:class:: TensorCorePolicy(arch, tags = None)
 
    Bases: :py:obj:`tilelang.carver.roller.policy.default.DefaultPolicy`
 
 
+   Default Policy for fastdlight, a heuristic plan that tries to
+   minimize memory traffic and maximize parallelism.for BitBLAS Schedule.
+
+
    .. py:attribute:: wmma_k
       :type:  int
       :value: 16
@@ -61,16 +65,67 @@ Module Contents
 
    .. py:method:: infer_node_smem_usage(td, node)
 
+      Infers the shared memory usage of a node given a TileDict configuration.
+
+      :param td: The TileDict object containing the tile configuration.
+      :type td: TileDict
+      :param node: The node for which to infer the shared memory usage.
+      :type node: PrimFuncNode
+
+      :returns: The estimated amount of shared memory used by the node.
+      :rtype: int
+
+
 
    .. py:method:: get_node_reduce_step_candidates(node)
 
+      Calculates reduction step candidates for each reduction axis in a PrimFuncNode. General idea : use factor first, since it does not require extra boundary check. for large prime number, which is rare case, use power of 2.
+
+      :param node: The node for which to calculate reduction step candidates. It contains reduction axes (raxis)
+                   with their domains (dom.extent).
+      :type node: PrimFuncNode
+
+      :returns: A dictionary mapping axis variable names to lists of step candidates. For each axis in the node,
+                this function calculates possible step sizes. For axes with a large prime domain, it uses powers of 2
+                as step candidates; for others, it uses all factors of the domain.
+      :rtype: Dict[str, List[int]]
+
+
 
    .. py:method:: check_tile_shape_isvalid(td)
 
+      Checks if the tile shapes in the TileDict are valid for the nodes in this context.
+
+      Parameters:
+      - td (TileDict): The TileDict object containing tile shapes and other configurations.
+
+      Returns:
+      - bool: True if all tile shapes are valid, False otherwise.
+
+
 
    .. py:method:: compute_node_stride_map(node, td)
 
+      Computes the stride map for a given node based on the TileDict configuration.
+
+      :param node: The node for which to compute the stride map.
+      :type node: PrimFuncNode
+      :param td: The TileDict object containing the tile configuration.
+      :type td: TileDict
+
+      :returns: A tuple of dictionaries containing the output strides and tensor strides.
+      :rtype: Tuple[Dict, Dict]
+
+
 
    .. py:method:: plan_rasterization(td)
 
+      Plans the rasterization for the given TileDict. This function is not implemented yet.
+
+      :param td: The TileDict object to plan rasterization for.
+      :type td: TileDict
+
+      :raises RasterRationPlan: This function is not implemented yet.
+
+
 

_sources/autoapi/tilelang/jit/adapter/dlpack/index.rst.txt

@@ -20,8 +20,12 @@ Classes
 Module Contents
 ---------------
 
-.. py:class:: TorchDLPackKernelAdapter
+.. py:class:: TorchDLPackKernelAdapter(mod, params, result_idx)
 
    Bases: :py:obj:`tilelang.jit.adapter.base.BaseKernelAdapter`
 
 
+   Helper class that provides a standard way to create an ABC using
+   inheritance.
+
+

_sources/autoapi/tilelang/jit/adapter/nvrtc/adapter/index.rst.txt

@@ -80,6 +80,8 @@ Module Contents
 
 
    .. py:attribute:: target
+      :value: None
+
 
 
    .. py:attribute:: verbose

_sources/autoapi/tilelang/layout/layout/index.rst.txt

@@ -25,6 +25,9 @@ Module Contents
    Bases: :py:obj:`tvm.ir.Node`
 
 
+   Base class of all IR Nodes.
+
+
    .. py:property:: index
 
       Property to retrieve the forward index of the layout.

autoapi/tilelang/carver/arch/cdna/index.html

@@ -465,7 +465,7 @@ <h2>Classes<a class="headerlink" href="#classes" title="Link to this heading">¶
 <table class="autosummary longtable docutils align-default">
 <tbody>
 <tr class="row-odd"><td><p><a class="reference internal" href="#tilelang.carver.arch.cdna.CDNA" title="tilelang.carver.arch.cdna.CDNA"><code class="xref py py-obj docutils literal notranslate"><span class="pre">CDNA</span></code></a></p></td>
-<td><p></p></td>
+<td><p>Represents the architecture of a computing device, capturing various hardware specifications.</p></td>
 </tr>
 </tbody>
 </table>
@@ -502,6 +502,7 @@ <h2>Module Contents<a class="headerlink" href="#module-contents" title="Link to
 <dt class="sig sig-object py" id="tilelang.carver.arch.cdna.CDNA">
 <em class="property"><span class="pre">class</span><span class="w"> </span></em><span class="sig-prename descclassname"><span class="pre">tilelang.carver.arch.cdna.</span></span><span class="sig-name descname"><span class="pre">CDNA</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">target</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#tilelang.carver.arch.cdna.CDNA" title="Link to this definition">¶</a></dt>
 <dd><p>Bases: <a class="reference internal" href="../arch_base/index.html#tilelang.carver.arch.arch_base.TileDevice" title="tilelang.carver.arch.arch_base.TileDevice"><code class="xref py py-obj docutils literal notranslate"><span class="pre">tilelang.carver.arch.arch_base.TileDevice</span></code></a></p>
+<p>Represents the architecture of a computing device, capturing various hardware specifications.</p>
 <dl class="field-list simple">
 <dt class="field-odd">Parameters<span class="colon">:</span></dt>
 <dd class="field-odd"><p><strong>target</strong> (<em>Union</em><em>[</em><em>tvm.target.Target</em><em>, </em><em>str</em><em>]</em>)</p>

autoapi/tilelang/carver/arch/cpu/index.html

@@ -465,7 +465,7 @@ <h2>Classes<a class="headerlink" href="#classes" title="Link to this heading">¶
 <table class="autosummary longtable docutils align-default">
 <tbody>
 <tr class="row-odd"><td><p><a class="reference internal" href="#tilelang.carver.arch.cpu.CPU" title="tilelang.carver.arch.cpu.CPU"><code class="xref py py-obj docutils literal notranslate"><span class="pre">CPU</span></code></a></p></td>
-<td><p></p></td>
+<td><p>Represents the architecture of a computing device, capturing various hardware specifications.</p></td>
 </tr>
 </tbody>
 </table>
@@ -502,6 +502,7 @@ <h2>Module Contents<a class="headerlink" href="#module-contents" title="Link to
 <dt class="sig sig-object py" id="tilelang.carver.arch.cpu.CPU">
 <em class="property"><span class="pre">class</span><span class="w"> </span></em><span class="sig-prename descclassname"><span class="pre">tilelang.carver.arch.cpu.</span></span><span class="sig-name descname"><span class="pre">CPU</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">target</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#tilelang.carver.arch.cpu.CPU" title="Link to this definition">¶</a></dt>
 <dd><p>Bases: <a class="reference internal" href="../arch_base/index.html#tilelang.carver.arch.arch_base.TileDevice" title="tilelang.carver.arch.arch_base.TileDevice"><code class="xref py py-obj docutils literal notranslate"><span class="pre">tilelang.carver.arch.arch_base.TileDevice</span></code></a></p>
+<p>Represents the architecture of a computing device, capturing various hardware specifications.</p>
 <dl class="field-list simple">
 <dt class="field-odd">Parameters<span class="colon">:</span></dt>
 <dd class="field-odd"><p><strong>target</strong> (<em>tvm.target.Target</em>)</p>