@@ -94,83 +94,83 @@ handle_command_write(vfu_ctx_t *ctx, vfu_pci_config_space_t *pci,
9494 if ((v & PCI_COMMAND_IO ) == PCI_COMMAND_IO ) {
9595 if (!pci -> hdr .cmd .iose ) {
9696 pci -> hdr .cmd .iose = 0x1 ;
97- vfu_log (ctx , LOG_INFO , "I/O space enabled" );
97+ vfu_log (ctx , LOG_DEBUG , "I/O space enabled" );
9898 }
9999 v &= ~PCI_COMMAND_IO ;
100100 } else {
101101 if (pci -> hdr .cmd .iose ) {
102102 pci -> hdr .cmd .iose = 0x0 ;
103- vfu_log (ctx , LOG_INFO , "I/O space disabled" );
103+ vfu_log (ctx , LOG_DEBUG , "I/O space disabled" );
104104 }
105105 }
106106
107107 if ((v & PCI_COMMAND_MEMORY ) == PCI_COMMAND_MEMORY ) {
108108 if (!pci -> hdr .cmd .mse ) {
109109 pci -> hdr .cmd .mse = 0x1 ;
110- vfu_log (ctx , LOG_INFO , "memory space enabled" );
110+ vfu_log (ctx , LOG_DEBUG , "memory space enabled" );
111111 }
112112 v &= ~PCI_COMMAND_MEMORY ;
113113 } else {
114114 if (pci -> hdr .cmd .mse ) {
115115 pci -> hdr .cmd .mse = 0x0 ;
116- vfu_log (ctx , LOG_INFO , "memory space disabled" );
116+ vfu_log (ctx , LOG_DEBUG , "memory space disabled" );
117117 }
118118 }
119119
120120 if ((v & PCI_COMMAND_MASTER ) == PCI_COMMAND_MASTER ) {
121121 if (!pci -> hdr .cmd .bme ) {
122122 pci -> hdr .cmd .bme = 0x1 ;
123- vfu_log (ctx , LOG_INFO , "bus master enabled" );
123+ vfu_log (ctx , LOG_DEBUG , "bus master enabled" );
124124 }
125125 v &= ~PCI_COMMAND_MASTER ;
126126 } else {
127127 if (pci -> hdr .cmd .bme ) {
128128 pci -> hdr .cmd .bme = 0x0 ;
129- vfu_log (ctx , LOG_INFO , "bus master disabled" );
129+ vfu_log (ctx , LOG_DEBUG , "bus master disabled" );
130130 }
131131 }
132132
133133 if ((v & PCI_COMMAND_SERR ) == PCI_COMMAND_SERR ) {
134134 if (!pci -> hdr .cmd .see ) {
135135 pci -> hdr .cmd .see = 0x1 ;
136- vfu_log (ctx , LOG_INFO , "SERR# enabled" );
136+ vfu_log (ctx , LOG_DEBUG , "SERR# enabled" );
137137 }
138138 v &= ~PCI_COMMAND_SERR ;
139139 } else {
140140 if (pci -> hdr .cmd .see ) {
141141 pci -> hdr .cmd .see = 0x0 ;
142- vfu_log (ctx , LOG_INFO , "SERR# disabled" );
142+ vfu_log (ctx , LOG_DEBUG , "SERR# disabled" );
143143 }
144144 }
145145
146146 if ((v & PCI_COMMAND_INTX_DISABLE ) == PCI_COMMAND_INTX_DISABLE ) {
147147 if (!pci -> hdr .cmd .id ) {
148148 pci -> hdr .cmd .id = 0x1 ;
149- vfu_log (ctx , LOG_INFO , "INTx emulation disabled" );
149+ vfu_log (ctx , LOG_DEBUG , "INTx emulation disabled" );
150150 }
151151 v &= ~PCI_COMMAND_INTX_DISABLE ;
152152 } else {
153153 if (pci -> hdr .cmd .id ) {
154154 pci -> hdr .cmd .id = 0x0 ;
155- vfu_log (ctx , LOG_INFO , "INTx emulation enabled" );
155+ vfu_log (ctx , LOG_DEBUG , "INTx emulation enabled" );
156156 }
157157 }
158158
159159 if ((v & PCI_COMMAND_INVALIDATE ) == PCI_COMMAND_INVALIDATE ) {
160160 if (!pci -> hdr .cmd .mwie ) {
161161 pci -> hdr .cmd .mwie = 1U ;
162- vfu_log (ctx , LOG_INFO , "memory write and invalidate enabled" );
162+ vfu_log (ctx , LOG_DEBUG , "memory write and invalidate enabled" );
163163 }
164164 v &= ~PCI_COMMAND_INVALIDATE ;
165165 } else {
166166 if (pci -> hdr .cmd .mwie ) {
167167 pci -> hdr .cmd .mwie = 0 ;
168- vfu_log (ctx , LOG_INFO , "memory write and invalidate disabled" );
168+ vfu_log (ctx , LOG_DEBUG , "memory write and invalidate disabled" );
169169 }
170170 }
171171
172172 if ((v & PCI_COMMAND_VGA_PALETTE ) == PCI_COMMAND_VGA_PALETTE ) {
173- vfu_log (ctx , LOG_INFO , "enabling VGA palette snooping ignored" );
173+ vfu_log (ctx , LOG_DEBUG , "enabling VGA palette snooping ignored" );
174174 v &= ~PCI_COMMAND_VGA_PALETTE ;
175175 }
176176
@@ -194,12 +194,12 @@ handle_erom_write(vfu_ctx_t *ctx, vfu_pci_config_space_t *pci,
194194 v = * (uint32_t * )buf ;
195195
196196 if (v == (uint32_t )PCI_ROM_ADDRESS_MASK ) {
197- vfu_log (ctx , LOG_INFO , "write mask to EROM ignored" );
197+ vfu_log (ctx , LOG_DEBUG , "write mask to EROM ignored" );
198198 } else if (v == 0 ) {
199- vfu_log (ctx , LOG_INFO , "cleared EROM" );
199+ vfu_log (ctx , LOG_DEBUG , "cleared EROM" );
200200 pci -> hdr .erom = 0 ;
201201 } else if (v == (uint32_t )~PCI_ROM_ADDRESS_ENABLE ) {
202- vfu_log (ctx , LOG_INFO , "EROM disable ignored" );
202+ vfu_log (ctx , LOG_DEBUG , "EROM disable ignored" );
203203 } else if (v == ~0U ) {
204204 vfu_log (ctx , LOG_INFO , "EROM not implemented" );
205205 } else {
@@ -249,7 +249,7 @@ pci_hdr_write(vfu_ctx_t *vfu_ctx, const char *buf, loff_t offset)
249249 break ;
250250 case PCI_LATENCY_TIMER :
251251 cfg_space -> hdr .mlt = (uint8_t )buf [0 ];
252- vfu_log (vfu_ctx , LOG_INFO , "set to latency timer to %hhx" ,
252+ vfu_log (vfu_ctx , LOG_DEBUG , "set to latency timer to %hhx" ,
253253 cfg_space -> hdr .mlt );
254254 break ;
255255 case PCI_BASE_ADDRESS_0 :
@@ -264,7 +264,7 @@ pci_hdr_write(vfu_ctx_t *vfu_ctx, const char *buf, loff_t offset)
264264 ret = handle_erom_write (vfu_ctx , cfg_space , buf );
265265 break ;
266266 default :
267- vfu_log (vfu_ctx , LOG_INFO , "PCI config write %#lx not handled" ,
267+ vfu_log (vfu_ctx , LOG_ERR , "PCI config write %#lx not handled" ,
268268 offset );
269269 ret = ERROR_INT (EINVAL );
270270 }
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