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lab03.cr.mti
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/home/archord/Downloads/lab03/vhdl/buttons.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/buttons.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity buttons
-- Compiling architecture synth of buttons
} {} {}} /home/archord/Downloads/lab03/vhdl/extend.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/extend.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity extend
-- Compiling architecture synth of extend
} {} {}} /home/archord/Downloads/lab03/vhdl/RAM.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/RAM.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity RAM
-- Compiling architecture synth of RAM
} {} {}} /home/archord/Downloads/lab03/vhdl/comparator.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/comparator.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity comparator
-- Compiling architecture synth of comparator
} {} {}} /home/archord/Downloads/lab03/testbench/tb_GECKO.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/testbench/tb_GECKO.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity tb_GECKO
-- Compiling architecture testbench of tb_GECKO
-- Loading entity GECKO
} {} {}} /home/archord/Downloads/lab03/vhdl/CPU.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/CPU.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity CPU
-- Compiling architecture bdf_type of CPU
} {} {}} /home/archord/Downloads/lab03/testbench/check_functions.vhd {2 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/testbench/check_functions.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Compiling package check_functions
-- Compiling package body check_functions
-- Loading package check_functions
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(49): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(59): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(65): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(67): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(68): (vcom-1283) Cannot reference file "text_report" inside pure function "scheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(83): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(93): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(99): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(101): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(102): (vcom-1283) Cannot reference file "text_report" inside pure function "icheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(117): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(127): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(133): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(135): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(136): (vcom-1283) Cannot reference file "text_report" inside pure function "hcheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(151): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(161): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(167): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(169): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
** Warning: /home/archord/Downloads/lab03/testbench/check_functions.vhd(170): (vcom-1283) Cannot reference file "text_report" inside pure function "bcheck".
} {} {}} /home/archord/Downloads/lab03/vhdl/mux2x32.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/mux2x32.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x32
-- Compiling architecture synth of mux2x32
} {} {}} /home/archord/Downloads/lab03/vhdl/mux2x5.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/mux2x5.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x5
-- Compiling architecture synth of mux2x5
} {} {}} /home/archord/Downloads/lab03/vhdl/GECKO.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/GECKO.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity GECKO
-- Compiling architecture bdf_type of GECKO
} {} {}} /home/archord/Downloads/lab03/vhdl/PC.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/PC.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity PC
-- Compiling architecture synth of PC
} {} {}} /home/archord/Downloads/lab03/vhdl/IR.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/IR.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity IR
-- Compiling architecture synth of IR
} {} {}} /home/archord/Downloads/lab03/vhdl/mux2x16.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/mux2x16.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2x16
-- Compiling architecture synth of mux2x16
} {} {}} /home/archord/Downloads/lab03/vhdl/decoder.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/decoder.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity decoder
-- Compiling architecture synth of decoder
} {} {}} /home/archord/Downloads/lab03/vhdl/rgb_led96.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/rgb_led96.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package STD_LOGIC_UNSIGNED
-- Compiling package pack
-- Compiling package body pack
-- Loading package pack
-- Loading package pack
-- Compiling entity rgb_led96
-- Compiling architecture arch of rgb_led96
} {} {}} /home/archord/Downloads/lab03/vhdl/ROM_Block.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/ROM_Block.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ROM_Block
-- Compiling architecture SYN of rom_block
} {} {}} /home/archord/Downloads/lab03/vhdl/LEDs.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/LEDs.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity LEDs
-- Compiling architecture synth of LEDs
} {} {}} /home/archord/Downloads/lab03/testbench/tb_PC.vhd {2 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/testbench/tb_PC.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_PC
-- Compiling architecture testbench of tb_PC
** Warning: /home/archord/Downloads/lab03/testbench/tb_PC.vhd(57): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: /home/archord/Downloads/lab03/testbench/tb_PC.vhd(59): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
} {} {}} /home/archord/Downloads/lab03/testbench/tb_IR.vhd {2 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/testbench/tb_IR.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package check_functions
-- Compiling entity tb_IR
-- Compiling architecture testbench of tb_IR
** Warning: /home/archord/Downloads/lab03/testbench/tb_IR.vhd(42): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
** Warning: /home/archord/Downloads/lab03/testbench/tb_IR.vhd(44): (vcom-1194) FILE declaration was written using VHDL 1987 syntax.
} {} {}} /home/archord/Downloads/lab03/vhdl/ALU.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/ALU.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ALU
-- Compiling architecture bdf_type of ALU
} {} {}} /home/archord/Downloads/lab03/vhdl/add_sub.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/add_sub.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity add_sub
-- Compiling architecture synth of add_sub
} {} {}} /home/archord/Downloads/lab03/vhdl/multiplexer.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/multiplexer.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity multiplexer
-- Compiling architecture synth of multiplexer
} {} {}} /home/archord/Downloads/lab03/vhdl/register_file.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/register_file.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity register_file
-- Compiling architecture synth of register_file
} {} {}} /home/archord/Downloads/lab03/vhdl/shift_unit.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/shift_unit.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity shift_unit
-- Compiling architecture synth of shift_unit
} {} {}} /home/archord/Downloads/lab03/vhdl/logic_unit.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/logic_unit.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity logic_unit
-- Compiling architecture synth of logic_unit
} {} {}} /home/archord/Downloads/lab03/vhdl/ROM.vhd {1 {vcom -work work -2002 -explicit -stats=none /home/archord/Downloads/lab03/vhdl/ROM.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ROM
-- Compiling architecture synth of ROM
} {} {}}