diff --git a/MAINTAINERS b/MAINTAINERS index b6fb84e8267c1..ffc828ba2729c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -110,6 +110,12 @@ F: disas/arm.c F: disas/arm-a64.cc F: disas/libvixl/ +Blackfin +M: Mike Frysinger +S: Maintained +F: target-bfin/ +F: hw/bfin/ + CRIS M: Edgar E. Iglesias S: Maintained diff --git a/arch_init.c b/arch_init.c index fa059731ed3f8..777a584b5cf88 100644 --- a/arch_init.c +++ b/arch_init.c @@ -50,6 +50,8 @@ int graphic_depth = 32; #define QEMU_ARCH QEMU_ARCH_ALPHA #elif defined(TARGET_ARM) #define QEMU_ARCH QEMU_ARCH_ARM +#elif defined(TARGET_BFIN) +#define QEMU_ARCH QEMU_ARCH_BFIN #elif defined(TARGET_CRIS) #define QEMU_ARCH QEMU_ARCH_CRIS #elif defined(TARGET_I386) diff --git a/configure b/configure index 4b808f9d17f64..b218df3e043d0 100755 --- a/configure +++ b/configure @@ -378,7 +378,7 @@ strip="${STRIP-${cross_prefix}strip}" windres="${WINDRES-${cross_prefix}windres}" pkg_config_exe="${PKG_CONFIG-${cross_prefix}pkg-config}" query_pkg_config() { - "${pkg_config_exe}" ${QEMU_PKG_CONFIG_FLAGS} "$@" + ${pkg_config_exe} ${QEMU_PKG_CONFIG_FLAGS} "$@" } pkg_config=query_pkg_config sdl_config="${SDL_CONFIG-${cross_prefix}sdl-config}" @@ -1762,7 +1762,7 @@ fi ########################################## # pkg-config probe -if ! has "$pkg_config_exe"; then +if ! has $pkg_config_exe; then error_exit "pkg-config binary '$pkg_config_exe' not found" fi @@ -5663,6 +5663,9 @@ case "$target_name" in bflt="yes" gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" ;; + bfin) + bflt="yes" + ;; cris) ;; lm32) @@ -5861,6 +5864,10 @@ for i in $ARCH $TARGET_BASE_ARCH ; do disas_config "ARM_A64" fi ;; + bfin) + echo "CONFIG_BFIN_DIS=y" >> $config_target_mak + echo "CONFIG_BFIN_DIS=y" >> config-all-disas.mak + ;; cris) disas_config "CRIS" ;; diff --git a/default-configs/bfin-linux-user.mak b/default-configs/bfin-linux-user.mak new file mode 100644 index 0000000000000..5f7aefb5b08bb --- /dev/null +++ b/default-configs/bfin-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for bfin-linux-user diff --git a/default-configs/bfin-softmmu.mak b/default-configs/bfin-softmmu.mak new file mode 100644 index 0000000000000..c881648792437 --- /dev/null +++ b/default-configs/bfin-softmmu.mak @@ -0,0 +1,12 @@ +# Default configuration for arm-softmmu + +CONFIG_NAND=y +CONFIG_ECC=y +CONFIG_SERIAL=y +CONFIG_SD=y +CONFIG_SSI_SD=y +CONFIG_SMC91C111=y +CONFIG_PFLASH_CFI01=y +CONFIG_PFLASH_CFI02=y +CONFIG_SSI=y +CONFIG_SSI_M25P80=y diff --git a/disas.c b/disas.c index 05a7a1260acbf..187dcec249c0b 100644 --- a/disas.c +++ b/disas.c @@ -302,6 +302,9 @@ void disas(FILE *out, void *code, unsigned long size) s.info.mach = bfd_mach_sparc_v9b; #elif defined(__arm__) print_insn = print_insn_arm; +#elif defined(__bfin__) + s.info.mach = bfd_mach_bfin; + print_insn = print_insn_bfin; #elif defined(__MIPSEB__) print_insn = print_insn_big_mips; #elif defined(__MIPSEL__) diff --git a/disas/Makefile.objs b/disas/Makefile.objs index abeba846617e9..9954f63d26a32 100644 --- a/disas/Makefile.objs +++ b/disas/Makefile.objs @@ -8,6 +8,7 @@ libvixldir = $(SRC_PATH)/disas/libvixl # some signed-unsigned equality comparisons in libvixl which later gcc # versions do not. arm-a64.o-cflags := -I$(libvixldir) -Wno-sign-compare +common-obj-$(CONFIG_BFIN_DIS) += bfin.o common-obj-$(CONFIG_CRIS_DIS) += cris.o common-obj-$(CONFIG_HPPA_DIS) += hppa.o common-obj-$(CONFIG_I386_DIS) += i386.o diff --git a/disas/bfin.c b/disas/bfin.c new file mode 100644 index 0000000000000..e64ee3c21a6d6 --- /dev/null +++ b/disas/bfin.c @@ -0,0 +1,4816 @@ +/* Disassemble ADI Blackfin Instructions. + Copyright 2005 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "qemu/osdep.h" +#include "disas/bfd.h" +#include "target-bfin/opcode/bfin.h" + +#ifndef PRINTF +#define PRINTF printf +#endif + +#ifndef EXIT +#define EXIT exit +#endif + +typedef long TIword; + +#define HOST_LONG_WORD_SIZE (sizeof (long) * 8) +#define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p)) +#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n))) +#define MASKBITS(val, bits) (val & ((1 << bits) - 1)) + +typedef unsigned int bu32; + +struct private +{ + TIword iw0; + bfd_boolean comment, parallel; +}; + +typedef enum +{ + c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4, + c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6, + c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10, + c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4, + c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e, +} const_forms_t; + +static const struct +{ + const char *name; + const int nbits; + const char reloc; + const char issigned; + const char pcrel; + const char scale; + const char offset; + const char negative; + const char positive; + const char decimal; + const char leading; + const char exact; +} constant_formats[] = +{ + { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0}, + { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0}, + { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0}, + { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0}, + { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0}, + { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0}, + { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0}, + { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0}, + { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0}, + { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0}, + { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0}, + { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1}, +}; + +static const char * +fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf) +{ + static char buf[60]; + + if (constant_formats[cf].reloc) + { + bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits) + : x) + constant_formats[cf].offset) << constant_formats[cf].scale); + if (constant_formats[cf].pcrel) + ea += pc; + + /* truncate to 32-bits for proper symbol lookup/matching */ + ea = (bu32)ea; + + if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact) + { + outf->print_address_func (ea, outf); + return ""; + } + else + { + sprintf (buf, "%lx", (unsigned long) x); + return buf; + } + } + + /* Negative constants have an implied sign bit. */ + if (constant_formats[cf].negative) + { + int nb = constant_formats[cf].nbits + 1; + + x = x | (1 << constant_formats[cf].nbits); + x = SIGNEXTEND (x, nb); + } + else + x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x; + + if (constant_formats[cf].offset) + x += constant_formats[cf].offset; + + if (constant_formats[cf].scale) + x <<= constant_formats[cf].scale; + + if (constant_formats[cf].decimal) + sprintf (buf, "%*li", constant_formats[cf].leading, x); + else + { + if (constant_formats[cf].issigned && x < 0) + sprintf (buf, "-0x%x", abs (x)); + else + sprintf (buf, "0x%lx", (unsigned long) x); + } + + return buf; +} + +static bu32 +fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc) +{ + if (0 && constant_formats[cf].reloc) + { + bu32 ea = (((constant_formats[cf].pcrel + ? SIGNEXTEND (x, constant_formats[cf].nbits) + : x) + constant_formats[cf].offset) + << constant_formats[cf].scale); + if (constant_formats[cf].pcrel) + ea += pc; + + return ea; + } + + /* Negative constants have an implied sign bit. */ + if (constant_formats[cf].negative) + { + int nb = constant_formats[cf].nbits + 1; + x = x | (1 << constant_formats[cf].nbits); + x = SIGNEXTEND (x, nb); + } + else if (constant_formats[cf].issigned) + x = SIGNEXTEND (x, constant_formats[cf].nbits); + + x += constant_formats[cf].offset; + x <<= constant_formats[cf].scale; + + return x; +} + +enum machine_registers +{ + REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, + REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3, + REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w, + REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, + REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, + REG_L2, REG_L3, + REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S, + REG_AQ, REG_V, REG_VS, + REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0, + REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1, + REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, + REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, + REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP, + REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP, + REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3, + REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3, + REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3, + REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3, + REG_AC0_COPY, REG_V_COPY, REG_RND_MOD, + REG_LASTREG, +}; + +enum reg_class +{ + rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext, + rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs, + rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2, + rc_sysregs3, rc_allregs, + LIM_REG_CLASSES +}; + +static const char * const reg_names[] = +{ + "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", + "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", + "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3", + "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W", + "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1", + "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1", + "L2", "L3", + "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S", + "AQ", "V", "VS", + "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0", + "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1", + "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", + "RETE", "EMUDAT", + "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", + "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", + "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", + "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L", + "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L", + "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H", + "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H", + "AC0_COPY", "V_COPY", "RND_MOD", + "LASTREG", + 0 +}; + +#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......") + +/* RL(0..7). */ +static const enum machine_registers decode_dregs_lo[] = +{ + REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, +}; + +#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7]) + +/* RH(0..7). */ +static const enum machine_registers decode_dregs_hi[] = +{ + REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, +}; + +#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7]) + +/* R(0..7). */ +static const enum machine_registers decode_dregs[] = +{ + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, +}; + +#define dregs(x) REGNAME (decode_dregs[(x) & 7]) + +/* R BYTE(0..7). */ +static const enum machine_registers decode_dregs_byte[] = +{ + REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7, +}; + +#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7]) + +/* P(0..5) SP FP. */ +static const enum machine_registers decode_pregs[] = +{ + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, +}; + +#define pregs(x) REGNAME (decode_pregs[(x) & 7]) +#define spfp(x) REGNAME (decode_spfp[(x) & 1]) +#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)]) +#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1]) +#define accum_word(x) REGNAME (decode_accum_word[(x) & 1]) +#define accum(x) REGNAME (decode_accum[(x) & 1]) + +/* I(0..3). */ +static const enum machine_registers decode_iregs[] = +{ + REG_I0, REG_I1, REG_I2, REG_I3, +}; + +#define iregs(x) REGNAME (decode_iregs[(x) & 3]) + +/* M(0..3). */ +static const enum machine_registers decode_mregs[] = +{ + REG_M0, REG_M1, REG_M2, REG_M3, +}; + +#define mregs(x) REGNAME (decode_mregs[(x) & 3]) +#define bregs(x) REGNAME (decode_bregs[(x) & 3]) +#define lregs(x) REGNAME (decode_lregs[(x) & 3]) + +/* dregs pregs. */ +static const enum machine_registers decode_dpregs[] = +{ + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, +}; + +#define dpregs(x) REGNAME (decode_dpregs[(x) & 15]) + +/* [dregs pregs]. */ +static const enum machine_registers decode_gregs[] = +{ + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, +}; + +#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)]) + +/* [dregs pregs (iregs mregs) (bregs lregs)]. */ +static const enum machine_registers decode_regs[] = +{ + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, + REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, + REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, +}; + +#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)]) + +/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */ +static const enum machine_registers decode_regs_lo[] = +{ + REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, + REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP, + REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3, + REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3, +}; + +#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)]) + +/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */ +static const enum machine_registers decode_regs_hi[] = +{ + REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, + REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP, + REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3, + REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3, +}; + +#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)]) + +static const enum machine_registers decode_statbits[] = +{ + REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY, + REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG, + REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG, + REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG, + REG_AV0, REG_AV0S, REG_AV1, REG_AV1S, + REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, + REG_V, REG_VS, REG_LASTREG, REG_LASTREG, + REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, +}; + +#define statbits(x) REGNAME (decode_statbits[(x) & 31]) + +/* LC0 LC1. */ +static const enum machine_registers decode_counters[] = +{ + REG_LC0, REG_LC1, +}; + +#define counters(x) REGNAME (decode_counters[(x) & 1]) +#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7]) + +/* [dregs pregs (iregs mregs) (bregs lregs) + dregs2_sysregs1 open sysregs2 sysregs3]. */ +static const enum machine_registers decode_allregs[] = +{ + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, + REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, + REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, + REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS, + REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, + REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, + REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, + REG_LASTREG, +}; + +#define IS_DREG(g,r) ((g) == 0 && (r) < 8) +#define IS_PREG(g,r) ((g) == 1 && (r) < 8) +#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4) +#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r)) +#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8) +#define IS_SYSREG(g,r) \ + (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7) +#define IS_RESERVEDREG(g,r) \ + (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5) + +#define allreg(r,g) (!IS_RESERVEDREG (g, r)) +#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r))) + +#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)]) +#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf) +#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf) +#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf) +#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf) +#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf) +#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf) +#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf) +#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf) +#define rimm16(x) fmtconst (c_rimm16, x, 0, outf) +#define huimm16(x) fmtconst (c_huimm16, x, 0, outf) +#define imm16(x) fmtconst (c_imm16, x, 0, outf) +#define imm16d(x) fmtconst (c_imm16d, x, 0, outf) +#define uimm2(x) fmtconst (c_uimm2, x, 0, outf) +#define uimm3(x) fmtconst (c_uimm3, x, 0, outf) +#define luimm16(x) fmtconst (c_luimm16, x, 0, outf) +#define uimm4(x) fmtconst (c_uimm4, x, 0, outf) +#define uimm5(x) fmtconst (c_uimm5, x, 0, outf) +#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf) +#define uimm8(x) fmtconst (c_uimm8, x, 0, outf) +#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf) +#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf) +#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf) +#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf) +#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf) +#define imm3(x) fmtconst (c_imm3, x, 0, outf) +#define imm4(x) fmtconst (c_imm4, x, 0, outf) +#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf) +#define imm5(x) fmtconst (c_imm5, x, 0, outf) +#define imm5d(x) fmtconst (c_imm5d, x, 0, outf) +#define imm6(x) fmtconst (c_imm6, x, 0, outf) +#define imm7(x) fmtconst (c_imm7, x, 0, outf) +#define imm7d(x) fmtconst (c_imm7d, x, 0, outf) +#define imm8(x) fmtconst (c_imm8, x, 0, outf) +#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf) +#define uimm16(x) fmtconst (c_uimm16, x, 0, outf) +#define uimm32(x) fmtconst (c_uimm32, x, 0, outf) +#define imm32(x) fmtconst (c_imm32, x, 0, outf) +#define huimm32(x) fmtconst (c_huimm32, x, 0, outf) +#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf) +#define imm7_val(x) fmtconst_val (c_imm7, x, 0) +#define imm16_val(x) fmtconst_val (c_uimm16, x, 0) +#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0) + +/* (arch.pm)arch_disassembler_functions. */ +#ifndef OUTS +#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt) +#endif +#define OUT(p, txt, ...) (p)->fprintf_func ((p)->stream, txt, ## __VA_ARGS__) + +static void +amod0 (int s0, int x0, disassemble_info *outf) +{ + if (s0 == 1 && x0 == 0) + OUTS (outf, " (S)"); + else if (s0 == 0 && x0 == 1) + OUTS (outf, " (CO)"); + else if (s0 == 1 && x0 == 1) + OUTS (outf, " (SCO)"); +} + +static void +amod1 (int s0, int x0, disassemble_info *outf) +{ + if (s0 == 0 && x0 == 0) + OUTS (outf, " (NS)"); + else if (s0 == 1 && x0 == 0) + OUTS (outf, " (S)"); +} + +static void +amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf) +{ + if (s0 == 1 && x0 == 0 && aop0 == 0) + OUTS (outf, " (S)"); + else if (s0 == 0 && x0 == 1 && aop0 == 0) + OUTS (outf, " (CO)"); + else if (s0 == 1 && x0 == 1 && aop0 == 0) + OUTS (outf, " (SCO)"); + else if (s0 == 0 && x0 == 0 && aop0 == 2) + OUTS (outf, " (ASR)"); + else if (s0 == 1 && x0 == 0 && aop0 == 2) + OUTS (outf, " (S, ASR)"); + else if (s0 == 0 && x0 == 1 && aop0 == 2) + OUTS (outf, " (CO, ASR)"); + else if (s0 == 1 && x0 == 1 && aop0 == 2) + OUTS (outf, " (SCO, ASR)"); + else if (s0 == 0 && x0 == 0 && aop0 == 3) + OUTS (outf, " (ASL)"); + else if (s0 == 1 && x0 == 0 && aop0 == 3) + OUTS (outf, " (S, ASL)"); + else if (s0 == 0 && x0 == 1 && aop0 == 3) + OUTS (outf, " (CO, ASL)"); + else if (s0 == 1 && x0 == 1 && aop0 == 3) + OUTS (outf, " (SCO, ASL)"); +} + +static void +searchmod (int r0, disassemble_info *outf) +{ + if (r0 == 0) + OUTS (outf, "GT"); + else if (r0 == 1) + OUTS (outf, "GE"); + else if (r0 == 2) + OUTS (outf, "LT"); + else if (r0 == 3) + OUTS (outf, "LE"); +} + +static void +aligndir (int r0, disassemble_info *outf) +{ + if (r0 == 1) + OUTS (outf, " (R)"); +} + +static int +decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf) +{ + const char *s0, *s1; + + if (h0) + s0 = dregs_hi (src0); + else + s0 = dregs_lo (src0); + + if (h1) + s1 = dregs_hi (src1); + else + s1 = dregs_lo (src1); + + OUTS (outf, s0); + OUTS (outf, " * "); + OUTS (outf, s1); + return 0; +} + +static int +decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf) +{ + const char *a; + const char *sop = ""; + + if (which) + a = "A1"; + else + a = "A0"; + + if (op == 3) + { + OUTS (outf, a); + return 0; + } + + switch (op) + { + case 0: sop = " = "; break; + case 1: sop = " += "; break; + case 2: sop = " -= "; break; + default: break; + } + + OUTS (outf, a); + OUTS (outf, sop); + decode_multfunc (h0, h1, src0, src1, outf); + + return 0; +} + +static void +decode_optmode (int mod, int MM, disassemble_info *outf) +{ + if (mod == 0 && MM == 0) + return; + + OUTS (outf, " ("); + + if (MM && !mod) + { + OUTS (outf, "M)"); + return; + } + + if (MM) + OUTS (outf, "M, "); + + if (mod == M_S2RND) + OUTS (outf, "S2RND"); + else if (mod == M_T) + OUTS (outf, "T"); + else if (mod == M_W32) + OUTS (outf, "W32"); + else if (mod == M_FU) + OUTS (outf, "FU"); + else if (mod == M_TFU) + OUTS (outf, "TFU"); + else if (mod == M_IS) + OUTS (outf, "IS"); + else if (mod == M_ISS2) + OUTS (outf, "ISS2"); + else if (mod == M_IH) + OUTS (outf, "IH"); + else if (mod == M_IU) + OUTS (outf, "IU"); + else + abort (); + + OUTS (outf, ")"); +} + +static struct saved_state +{ + bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4]; + bu32 ax[2], aw[2]; + bu32 lt[2], lc[2], lb[2]; + bu32 rets; +} saved_state; + +#define DREG(x) (saved_state.dpregs[x]) +#define GREG(x, i) DPREG ((x) | ((i) << 3)) +#define DPREG(x) (saved_state.dpregs[x]) +#define DREG(x) (saved_state.dpregs[x]) +#define PREG(x) (saved_state.dpregs[(x) + 8]) +#define SPREG PREG (6) +#define FPREG PREG (7) +#define IREG(x) (saved_state.iregs[x]) +#define MREG(x) (saved_state.mregs[x]) +#define BREG(x) (saved_state.bregs[x]) +#define LREG(x) (saved_state.lregs[x]) +#define AXREG(x) (saved_state.ax[x]) +#define AWREG(x) (saved_state.aw[x]) +#define LCREG(x) (saved_state.lc[x]) +#define LTREG(x) (saved_state.lt[x]) +#define LBREG(x) (saved_state.lb[x]) +#define RETSREG (saved_state.rets) + +static bu32 * +get_allreg (int grp, int reg) +{ + int fullreg = (grp << 3) | reg; + /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, + REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, + REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, + REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS, + , , , , , , , , + REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, + REG_CYCLES2, + REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, + REG_LASTREG */ + switch (fullreg >> 2) + { + case 0: case 1: return &DREG (reg); + case 2: case 3: return &PREG (reg); + case 4: return &IREG (reg & 3); + case 5: return &MREG (reg & 3); + case 6: return &BREG (reg & 3); + case 7: return &LREG (reg & 3); + default: + switch (fullreg) + { + case 32: return &AXREG (0); + case 33: return &AWREG (0); + case 34: return &AXREG (1); + case 35: return &AWREG (1); + case 39: return &RETSREG; + case 48: return &LCREG (0); + case 49: return <REG (0); + case 50: return &LBREG (0); + case 51: return &LCREG (1); + case 52: return <REG (1); + case 53: return &LBREG (1); + } + } + abort (); +} + +static int +decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* ProgCtrl + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask); + int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask); + + if (prgfunc == 0 && poprnd == 0) + OUTS (outf, "NOP"); + else if (priv->parallel) + return 0; + else if (prgfunc == 1 && poprnd == 0) + OUTS (outf, "RTS"); + else if (prgfunc == 1 && poprnd == 1) + OUTS (outf, "RTI"); + else if (prgfunc == 1 && poprnd == 2) + OUTS (outf, "RTX"); + else if (prgfunc == 1 && poprnd == 3) + OUTS (outf, "RTN"); + else if (prgfunc == 1 && poprnd == 4) + OUTS (outf, "RTE"); + else if (prgfunc == 2 && poprnd == 0) + OUTS (outf, "IDLE"); + else if (prgfunc == 2 && poprnd == 3) + OUTS (outf, "CSYNC"); + else if (prgfunc == 2 && poprnd == 4) + OUTS (outf, "SSYNC"); + else if (prgfunc == 2 && poprnd == 5) + OUTS (outf, "EMUEXCPT"); + else if (prgfunc == 3 && IS_DREG (0, poprnd)) + { + OUTS (outf, "CLI "); + OUTS (outf, dregs (poprnd)); + } + else if (prgfunc == 4 && IS_DREG (0, poprnd)) + { + OUTS (outf, "STI "); + OUTS (outf, dregs (poprnd)); + } + else if (prgfunc == 5 && IS_PREG (1, poprnd)) + { + OUTS (outf, "JUMP ("); + OUTS (outf, pregs (poprnd)); + OUTS (outf, ")"); + } + else if (prgfunc == 6 && IS_PREG (1, poprnd)) + { + OUTS (outf, "CALL ("); + OUTS (outf, pregs (poprnd)); + OUTS (outf, ")"); + } + else if (prgfunc == 7 && IS_PREG (1, poprnd)) + { + OUTS (outf, "CALL (PC + "); + OUTS (outf, pregs (poprnd)); + OUTS (outf, ")"); + } + else if (prgfunc == 8 && IS_PREG (1, poprnd)) + { + OUTS (outf, "JUMP (PC + "); + OUTS (outf, pregs (poprnd)); + OUTS (outf, ")"); + } + else if (prgfunc == 9) + { + OUTS (outf, "RAISE "); + OUTS (outf, uimm4 (poprnd)); + } + else if (prgfunc == 10) + { + OUTS (outf, "EXCPT "); + OUTS (outf, uimm4 (poprnd)); + } + else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5) + { + OUTS (outf, "TESTSET ("); + OUTS (outf, pregs (poprnd)); + OUTS (outf, ")"); + } + else + return 0; + return 2; +} + +static int +decode_CaCTRL_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* CaCTRL + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask); + int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask); + int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask); + + if (priv->parallel) + return 0; + + if (a == 0 && op == 0) + { + OUTS (outf, "PREFETCH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "]"); + } + else if (a == 0 && op == 1) + { + OUTS (outf, "FLUSHINV["); + OUTS (outf, pregs (reg)); + OUTS (outf, "]"); + } + else if (a == 0 && op == 2) + { + OUTS (outf, "FLUSH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "]"); + } + else if (a == 0 && op == 3) + { + OUTS (outf, "IFLUSH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "]"); + } + else if (a == 1 && op == 0) + { + OUTS (outf, "PREFETCH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "++]"); + } + else if (a == 1 && op == 1) + { + OUTS (outf, "FLUSHINV["); + OUTS (outf, pregs (reg)); + OUTS (outf, "++]"); + } + else if (a == 1 && op == 2) + { + OUTS (outf, "FLUSH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "++]"); + } + else if (a == 1 && op == 3) + { + OUTS (outf, "IFLUSH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "++]"); + } + else + return 0; + return 2; +} + +static int +decode_PushPopReg_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* PushPopReg + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask); + int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask); + int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask); + + if (priv->parallel) + return 0; + + if (W == 0 && mostreg (reg, grp)) + { + OUTS (outf, allregs (reg, grp)); + OUTS (outf, " = [SP++]"); + } + else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6)) + { + OUTS (outf, "[--SP] = "); + OUTS (outf, allregs (reg, grp)); + } + else + return 0; + return 2; +} + +static int +decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* PushPopMultiple + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask); + int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask); + int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask); + int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask); + int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask); + + if (priv->parallel) + return 0; + + if (pr > 5) + return 0; + + if (W == 1 && d == 1 && p == 1) + { + OUTS (outf, "[--SP] = (R7:"); + OUTS (outf, imm5d (dr)); + OUTS (outf, ", P5:"); + OUTS (outf, imm5d (pr)); + OUTS (outf, ")"); + } + else if (W == 1 && d == 1 && p == 0 && pr == 0) + { + OUTS (outf, "[--SP] = (R7:"); + OUTS (outf, imm5d (dr)); + OUTS (outf, ")"); + } + else if (W == 1 && d == 0 && p == 1 && dr == 0) + { + OUTS (outf, "[--SP] = (P5:"); + OUTS (outf, imm5d (pr)); + OUTS (outf, ")"); + } + else if (W == 0 && d == 1 && p == 1) + { + OUTS (outf, "(R7:"); + OUTS (outf, imm5d (dr)); + OUTS (outf, ", P5:"); + OUTS (outf, imm5d (pr)); + OUTS (outf, ") = [SP++]"); + } + else if (W == 0 && d == 1 && p == 0 && pr == 0) + { + OUTS (outf, "(R7:"); + OUTS (outf, imm5d (dr)); + OUTS (outf, ") = [SP++]"); + } + else if (W == 0 && d == 0 && p == 1 && dr == 0) + { + OUTS (outf, "(P5:"); + OUTS (outf, imm5d (pr)); + OUTS (outf, ") = [SP++]"); + } + else + return 0; + return 2; +} + +static int +decode_ccMV_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* ccMV + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask); + int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask); + int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask); + int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask); + int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask); + + if (priv->parallel) + return 0; + + if (T == 1) + { + OUTS (outf, "IF CC "); + OUTS (outf, gregs (dst, d)); + OUTS (outf, " = "); + OUTS (outf, gregs (src, s)); + } + else if (T == 0) + { + OUTS (outf, "IF !CC "); + OUTS (outf, gregs (dst, d)); + OUTS (outf, " = "); + OUTS (outf, gregs (src, s)); + } + else + return 0; + return 2; +} + +static int +decode_CCflag_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* CCflag + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask); + int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask); + int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask); + int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask); + int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask); + + if (priv->parallel) + return 0; + + if (opc == 0 && I == 0 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " == "); + OUTS (outf, dregs (y)); + } + else if (opc == 1 && I == 0 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " < "); + OUTS (outf, dregs (y)); + } + else if (opc == 2 && I == 0 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " <= "); + OUTS (outf, dregs (y)); + } + else if (opc == 3 && I == 0 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " < "); + OUTS (outf, dregs (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 4 && I == 0 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " <= "); + OUTS (outf, dregs (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 0 && I == 1 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " == "); + OUTS (outf, imm3 (y)); + } + else if (opc == 1 && I == 1 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " < "); + OUTS (outf, imm3 (y)); + } + else if (opc == 2 && I == 1 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " <= "); + OUTS (outf, imm3 (y)); + } + else if (opc == 3 && I == 1 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " < "); + OUTS (outf, uimm3 (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 4 && I == 1 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " <= "); + OUTS (outf, uimm3 (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 0 && I == 0 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " == "); + OUTS (outf, pregs (y)); + } + else if (opc == 1 && I == 0 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " < "); + OUTS (outf, pregs (y)); + } + else if (opc == 2 && I == 0 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " <= "); + OUTS (outf, pregs (y)); + } + else if (opc == 3 && I == 0 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " < "); + OUTS (outf, pregs (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 4 && I == 0 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " <= "); + OUTS (outf, pregs (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 0 && I == 1 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " == "); + OUTS (outf, imm3 (y)); + } + else if (opc == 1 && I == 1 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " < "); + OUTS (outf, imm3 (y)); + } + else if (opc == 2 && I == 1 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " <= "); + OUTS (outf, imm3 (y)); + } + else if (opc == 3 && I == 1 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " < "); + OUTS (outf, uimm3 (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 4 && I == 1 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " <= "); + OUTS (outf, uimm3 (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0) + OUTS (outf, "CC = A0 == A1"); + + else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0) + OUTS (outf, "CC = A0 < A1"); + + else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0) + OUTS (outf, "CC = A0 <= A1"); + + else + return 0; + return 2; +} + +static int +decode_CC2dreg_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* CC2dreg + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask); + int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask); + + if (priv->parallel) + return 0; + + if (op == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = CC"); + } + else if (op == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (reg)); + } + else if (op == 3 && reg == 0) + OUTS (outf, "CC = !CC"); + else + return 0; + + return 2; +} + +static int +decode_CC2stat_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* CC2stat + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask); + int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask); + int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask); + + const char *bitname = statbits (cbit); + const char * const op_names[] = { "", "|", "&", "^" } ; + + if (priv->parallel) + return 0; + + if (decode_statbits[cbit] == REG_LASTREG) + { + /* All ASTAT bits except CC may be operated on in hardware, but may + not have a dedicated insn, so still decode "valid" insns. */ + static char bitnames[64]; + if (cbit != 5) + sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit); + else + return 0; + + bitname = bitnames; + } + + if (D == 0) + OUT (outf, "CC %s= %s", op_names[op], bitname); + else + OUT (outf, "%s %s= CC", bitname, op_names[op]); + + return 2; +} + +static int +decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* BRCC + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask); + int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask); + int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask); + + if (priv->parallel) + return 0; + + if (T == 1 && B == 1) + { + OUTS (outf, "IF CC JUMP 0x"); + OUTS (outf, pcrel10 (offset)); + OUTS (outf, " (BP)"); + } + else if (T == 0 && B == 1) + { + OUTS (outf, "IF !CC JUMP 0x"); + OUTS (outf, pcrel10 (offset)); + OUTS (outf, " (BP)"); + } + else if (T == 1) + { + OUTS (outf, "IF CC JUMP 0x"); + OUTS (outf, pcrel10 (offset)); + } + else if (T == 0) + { + OUTS (outf, "IF !CC JUMP 0x"); + OUTS (outf, pcrel10 (offset)); + } + else + return 0; + + return 2; +} + +static int +decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* UJUMP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 1 | 0 |.offset........................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask); + + if (priv->parallel) + return 0; + + OUTS (outf, "JUMP.S 0x"); + OUTS (outf, pcrel12 (offset)); + return 2; +} + +static int +decode_REGMV_0 (TIword iw0, disassemble_info *outf) +{ + /* REGMV + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask); + int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask); + int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask); + int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask); + + /* Reserved slots cannot be a src/dst. */ + if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst)) + goto invalid_move; + + /* Standard register moves */ + if ((gs < 2) || /* Dregs/Pregs as source */ + (gd < 2) || /* Dregs/Pregs as dest */ + (gs == 4 && src < 4) || /* Accumulators as source */ + (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */ + (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */ + (gd == 7 && dst == 7)) /* EMUDAT as dest */ + goto valid_move; + + /* dareg = dareg (IMBL) */ + if (gs < 4 && gd < 4) + goto valid_move; + + /* USP can be src to sysregs, but not dagregs. */ + if ((gs == 7 && src == 0) && (gd >= 4)) + goto valid_move; + + /* USP can move between genregs (only check Accumulators). */ + if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) || + ((gd == 7 && dst == 0) && (gs == 4 && src < 4))) + goto valid_move; + + /* Still here ? Invalid reg pair. */ + invalid_move: + return 0; + + valid_move: + OUTS (outf, allregs (dst, gd)); + OUTS (outf, " = "); + OUTS (outf, allregs (src, gs)); + return 2; +} + +static int +decode_ALU2op_0 (TIword iw0, disassemble_info *outf) +{ + /* ALU2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask); + int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask); + int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask); + + if (opc == 0) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " >>>= "); + OUTS (outf, dregs (src)); + } + else if (opc == 1) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " >>= "); + OUTS (outf, dregs (src)); + } + else if (opc == 2) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " <<= "); + OUTS (outf, dregs (src)); + } + else if (opc == 3) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " *= "); + OUTS (outf, dregs (src)); + } + else if (opc == 4) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = ("); + OUTS (outf, dregs (dst)); + OUTS (outf, " + "); + OUTS (outf, dregs (src)); + OUTS (outf, ") << 0x1"); + } + else if (opc == 5) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = ("); + OUTS (outf, dregs (dst)); + OUTS (outf, " + "); + OUTS (outf, dregs (src)); + OUTS (outf, ") << 0x2"); + } + else if (opc == 8) + { + OUTS (outf, "DIVQ ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, dregs (src)); + OUTS (outf, ")"); + } + else if (opc == 9) + { + OUTS (outf, "DIVS ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, dregs (src)); + OUTS (outf, ")"); + } + else if (opc == 10) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src)); + OUTS (outf, " (X)"); + } + else if (opc == 11) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src)); + OUTS (outf, " (Z)"); + } + else if (opc == 12) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs_byte (src)); + OUTS (outf, " (X)"); + } + else if (opc == 13) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs_byte (src)); + OUTS (outf, " (Z)"); + } + else if (opc == 14) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = -"); + OUTS (outf, dregs (src)); + } + else if (opc == 15) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " =~ "); + OUTS (outf, dregs (src)); + } + else + return 0; + + return 2; +} + +static int +decode_PTR2op_0 (TIword iw0, disassemble_info *outf) +{ + /* PTR2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask); + int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask); + int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask); + + if (opc == 0) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " -= "); + OUTS (outf, pregs (src)); + } + else if (opc == 1) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src)); + OUTS (outf, " << 0x2"); + } + else if (opc == 3) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src)); + OUTS (outf, " >> 0x2"); + } + else if (opc == 4) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src)); + OUTS (outf, " >> 0x1"); + } + else if (opc == 5) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " += "); + OUTS (outf, pregs (src)); + OUTS (outf, " (BREV)"); + } + else if (opc == 6) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = ("); + OUTS (outf, pregs (dst)); + OUTS (outf, " + "); + OUTS (outf, pregs (src)); + OUTS (outf, ") << 0x1"); + } + else if (opc == 7) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = ("); + OUTS (outf, pregs (dst)); + OUTS (outf, " + "); + OUTS (outf, pregs (src)); + OUTS (outf, ") << 0x2"); + } + else + return 0; + + return 2; +} + +static int +decode_LOGI2op_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* LOGI2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask); + int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask); + int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask); + + if (priv->parallel) + return 0; + + if (opc == 0) + { + OUTS (outf, "CC = !BITTST ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, uimm5 (src)); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + priv->comment = TRUE; + } + else if (opc == 1) + { + OUTS (outf, "CC = BITTST ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, uimm5 (src)); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + priv->comment = TRUE; + } + else if (opc == 2) + { + OUTS (outf, "BITSET ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, uimm5 (src)); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + priv->comment = TRUE; + } + else if (opc == 3) + { + OUTS (outf, "BITTGL ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, uimm5 (src)); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + priv->comment = TRUE; + } + else if (opc == 4) + { + OUTS (outf, "BITCLR ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, uimm5 (src)); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + priv->comment = TRUE; + } + else if (opc == 5) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " >>>= "); + OUTS (outf, uimm5 (src)); + } + else if (opc == 6) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " >>= "); + OUTS (outf, uimm5 (src)); + } + else if (opc == 7) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " <<= "); + OUTS (outf, uimm5 (src)); + } + else + return 0; + + return 2; +} + +static int +decode_COMP3op_0 (TIword iw0, disassemble_info *outf) +{ + /* COMP3op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask); + int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask); + int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); + int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask); + + if (opc == 5 && src1 == src0) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src0)); + OUTS (outf, " << 0x1"); + } + else if (opc == 1) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + } + else if (opc == 2) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " & "); + OUTS (outf, dregs (src1)); + } + else if (opc == 3) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " | "); + OUTS (outf, dregs (src1)); + } + else if (opc == 4) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " ^ "); + OUTS (outf, dregs (src1)); + } + else if (opc == 5) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src0)); + OUTS (outf, " + "); + OUTS (outf, pregs (src1)); + } + else if (opc == 6) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src0)); + OUTS (outf, " + ("); + OUTS (outf, pregs (src1)); + OUTS (outf, " << 0x1)"); + } + else if (opc == 7) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src0)); + OUTS (outf, " + ("); + OUTS (outf, pregs (src1)); + OUTS (outf, " << 0x2)"); + } + else if (opc == 0) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + } + else + return 0; + + return 2; +} + +static int +decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* COMPI2opD + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask); + int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask); + int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask); + + bu32 *pval = get_allreg (0, dst); + + if (priv->parallel) + return 0; + + /* Since we don't have 32-bit immediate loads, we allow the disassembler + to combine them, so it prints out the right values. + Here we keep track of the registers. */ + if (op == 0) + { + *pval = imm7_val (src); + if (src & 0x40) + *pval |= 0xFFFFFF80; + else + *pval &= 0x7F; + } + + if (op == 0) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, imm7 (src)); + OUTS (outf, " (X);\t\t/*\t\t"); + OUTS (outf, dregs (dst)); + OUTS (outf, "="); + OUTS (outf, uimm32 (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ") */"); + priv->comment = TRUE; + } + else if (op == 1) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " += "); + OUTS (outf, imm7 (src)); + OUTS (outf, ";\t\t/* ("); + OUTS (outf, imm7d (src)); + OUTS (outf, ") */"); + priv->comment = TRUE; + } + else + return 0; + + return 2; +} + +static int +decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* COMPI2opP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask); + int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask); + int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask); + + bu32 *pval = get_allreg (1, dst); + + if (priv->parallel) + return 0; + + if (op == 0) + { + *pval = imm7_val (src); + if (src & 0x40) + *pval |= 0xFFFFFF80; + else + *pval &= 0x7F; + } + + if (op == 0) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, imm7 (src)); + OUTS (outf, " (X);\t\t/*\t\t"); + OUTS (outf, pregs (dst)); + OUTS (outf, "="); + OUTS (outf, uimm32 (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ") */"); + priv->comment = TRUE; + } + else if (op == 1) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " += "); + OUTS (outf, imm7 (src)); + OUTS (outf, ";\t\t/* ("); + OUTS (outf, imm7d (src)); + OUTS (outf, ") */"); + priv->comment = TRUE; + } + else + return 0; + + return 2; +} + +static int +decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf) +{ + /* LDSTpmod + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask); + int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask); + int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask); + int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask); + int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask); + + if (aop == 1 && W == 0 && idx == ptr) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "]"); + } + else if (aop == 2 && W == 0 && idx == ptr) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "]"); + } + else if (aop == 1 && W == 1 && idx == ptr) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, dregs_lo (reg)); + } + else if (aop == 2 && W == 1 && idx == ptr) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, dregs_hi (reg)); + } + else if (aop == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "]"); + } + else if (aop == 1 && W == 0) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "]"); + } + else if (aop == 2 && W == 0) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "]"); + } + else if (aop == 3 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "] (Z)"); + } + else if (aop == 3 && W == 1) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "] (X)"); + } + else if (aop == 0 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 1 && W == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "] = "); + OUTS (outf, dregs_lo (reg)); + } + else if (aop == 2 && W == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "] = "); + OUTS (outf, dregs_hi (reg)); + } + else + return 0; + + return 2; +} + +static int +decode_dagMODim_0 (TIword iw0, disassemble_info *outf) +{ + /* dagMODim + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask); + int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask); + int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask); + int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask); + + if (op == 0 && br == 1) + { + OUTS (outf, iregs (i)); + OUTS (outf, " += "); + OUTS (outf, mregs (m)); + OUTS (outf, " (BREV)"); + } + else if (op == 0) + { + OUTS (outf, iregs (i)); + OUTS (outf, " += "); + OUTS (outf, mregs (m)); + } + else if (op == 1 && br == 0) + { + OUTS (outf, iregs (i)); + OUTS (outf, " -= "); + OUTS (outf, mregs (m)); + } + else + return 0; + + return 2; +} + +static int +decode_dagMODik_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* dagMODik + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask); + int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask); + + if (op == 0) + { + OUTS (outf, iregs (i)); + OUTS (outf, " += 0x2"); + } + else if (op == 1) + { + OUTS (outf, iregs (i)); + OUTS (outf, " -= 0x2"); + } + else if (op == 2) + { + OUTS (outf, iregs (i)); + OUTS (outf, " += 0x4"); + } + else if (op == 3) + { + OUTS (outf, iregs (i)); + OUTS (outf, " -= 0x4"); + } + else + return 0; + + if (!priv->parallel) + { + OUTS (outf, ";\t\t/* ( "); + if (op == 0 || op == 1) + OUTS (outf, "2"); + else if (op == 2 || op == 3) + OUTS (outf, "4"); + OUTS (outf, ") */"); + priv->comment = TRUE; + } + + return 2; +} + +static int +decode_dspLDST_0 (TIword iw0, disassemble_info *outf) +{ + /* dspLDST + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask); + int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask); + int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask); + int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask); + int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask); + + if (aop == 0 && W == 0 && m == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, iregs (i)); + OUTS (outf, "++]"); + } + else if (aop == 0 && W == 0 && m == 1) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "++]"); + } + else if (aop == 0 && W == 0 && m == 2) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "++]"); + } + else if (aop == 1 && W == 0 && m == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, iregs (i)); + OUTS (outf, "--]"); + } + else if (aop == 1 && W == 0 && m == 1) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "--]"); + } + else if (aop == 1 && W == 0 && m == 2) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "--]"); + } + else if (aop == 2 && W == 0 && m == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, iregs (i)); + OUTS (outf, "]"); + } + else if (aop == 2 && W == 0 && m == 1) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "]"); + } + else if (aop == 2 && W == 0 && m == 2) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "]"); + } + else if (aop == 0 && W == 1 && m == 0) + { + OUTS (outf, "["); + OUTS (outf, iregs (i)); + OUTS (outf, "++] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 0 && W == 1 && m == 1) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "++] = "); + OUTS (outf, dregs_lo (reg)); + } + else if (aop == 0 && W == 1 && m == 2) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "++] = "); + OUTS (outf, dregs_hi (reg)); + } + else if (aop == 1 && W == 1 && m == 0) + { + OUTS (outf, "["); + OUTS (outf, iregs (i)); + OUTS (outf, "--] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 1 && W == 1 && m == 1) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "--] = "); + OUTS (outf, dregs_lo (reg)); + } + else if (aop == 1 && W == 1 && m == 2) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "--] = "); + OUTS (outf, dregs_hi (reg)); + } + else if (aop == 2 && W == 1 && m == 0) + { + OUTS (outf, "["); + OUTS (outf, iregs (i)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 2 && W == 1 && m == 1) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "] = "); + OUTS (outf, dregs_lo (reg)); + } + else if (aop == 2 && W == 1 && m == 2) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "] = "); + OUTS (outf, dregs_hi (reg)); + } + else if (aop == 3 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, iregs (i)); + OUTS (outf, " ++ "); + OUTS (outf, mregs (m)); + OUTS (outf, "]"); + } + else if (aop == 3 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, iregs (i)); + OUTS (outf, " ++ "); + OUTS (outf, mregs (m)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else + return 0; + + return 2; +} + +static int +decode_LDST_0 (TIword iw0, disassemble_info *outf) +{ + /* LDST + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask); + int W = ((iw0 >> LDST_W_bits) & LDST_W_mask); + int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask); + int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask); + int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask); + int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask); + + if (aop == 0 && sz == 0 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++]"); + } + else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr) + { + OUTS (outf, pregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++]"); + } + else if (aop == 0 && sz == 1 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] (Z)"); + } + else if (aop == 0 && sz == 1 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] (X)"); + } + else if (aop == 0 && sz == 2 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] (Z)"); + } + else if (aop == 0 && sz == 2 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] (X)"); + } + else if (aop == 1 && sz == 0 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--]"); + } + else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr) + { + OUTS (outf, pregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--]"); + } + else if (aop == 1 && sz == 1 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] (Z)"); + } + else if (aop == 1 && sz == 1 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] (X)"); + } + else if (aop == 1 && sz == 2 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] (Z)"); + } + else if (aop == 1 && sz == 2 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] (X)"); + } + else if (aop == 2 && sz == 0 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "]"); + } + else if (aop == 2 && sz == 0 && Z == 1 && W == 0) + { + OUTS (outf, pregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "]"); + } + else if (aop == 2 && sz == 1 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] (Z)"); + } + else if (aop == 2 && sz == 1 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] (X)"); + } + else if (aop == 2 && sz == 2 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] (Z)"); + } + else if (aop == 2 && sz == 2 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] (X)"); + } + else if (aop == 0 && sz == 0 && Z == 0 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 0 && sz == 0 && Z == 1 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] = "); + OUTS (outf, pregs (reg)); + } + else if (aop == 0 && sz == 1 && Z == 0 && W == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 0 && sz == 2 && Z == 0 && W == 1) + { + OUTS (outf, "B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 1 && sz == 0 && Z == 0 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 1 && sz == 0 && Z == 1 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] = "); + OUTS (outf, pregs (reg)); + } + else if (aop == 1 && sz == 1 && Z == 0 && W == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 1 && sz == 2 && Z == 0 && W == 1) + { + OUTS (outf, "B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 2 && sz == 0 && Z == 0 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 2 && sz == 0 && Z == 1 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, pregs (reg)); + } + else if (aop == 2 && sz == 1 && Z == 0 && W == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 2 && sz == 2 && Z == 0 && W == 1) + { + OUTS (outf, "B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else + return 0; + + return 2; +} + +static int +decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf) +{ + /* LDSTiiFP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask); + int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask); + int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask); + + if (W == 0) + { + OUTS (outf, dpregs (reg)); + OUTS (outf, " = [FP "); + OUTS (outf, negimm5s4 (offset)); + OUTS (outf, "]"); + } + else if (W == 1) + { + OUTS (outf, "[FP "); + OUTS (outf, negimm5s4 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dpregs (reg)); + } + else + return 0; + + return 2; +} + +static int +decode_LDSTii_0 (TIword iw0, disassemble_info *outf) +{ + /* LDSTii + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask); + int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask); + int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask); + int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask); + int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask); + + if (W == 0 && op == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s4 (offset)); + OUTS (outf, "]"); + } + else if (W == 0 && op == 1) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s2 (offset)); + OUTS (outf, "] (Z)"); + } + else if (W == 0 && op == 2) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s2 (offset)); + OUTS (outf, "] (X)"); + } + else if (W == 0 && op == 3) + { + OUTS (outf, pregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s4 (offset)); + OUTS (outf, "]"); + } + else if (W == 1 && op == 0) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s4 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (W == 1 && op == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s2 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (W == 1 && op == 3) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s4 (offset)); + OUTS (outf, "] = "); + OUTS (outf, pregs (reg)); + } + else + return 0; + + return 2; +} + +static int +decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* LoopSetup + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......| + |.reg...........| - | - |.eoffset...............................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask); + int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask); + int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask); + int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask); + int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask); + + if (priv->parallel) + return 0; + + if (reg > 7) + return 0; + + if (rop == 0) + { + OUTS (outf, "LSETUP"); + OUTS (outf, "(0x"); + OUTS (outf, pcrel4 (soffset)); + OUTS (outf, ", 0x"); + OUTS (outf, lppcrel10 (eoffset)); + OUTS (outf, ") "); + OUTS (outf, counters (c)); + } + else if (rop == 1) + { + OUTS (outf, "LSETUP"); + OUTS (outf, "(0x"); + OUTS (outf, pcrel4 (soffset)); + OUTS (outf, ", 0x"); + OUTS (outf, lppcrel10 (eoffset)); + OUTS (outf, ") "); + OUTS (outf, counters (c)); + OUTS (outf, " = "); + OUTS (outf, pregs (reg)); + } + else if (rop == 3) + { + OUTS (outf, "LSETUP"); + OUTS (outf, "(0x"); + OUTS (outf, pcrel4 (soffset)); + OUTS (outf, ", 0x"); + OUTS (outf, lppcrel10 (eoffset)); + OUTS (outf, ") "); + OUTS (outf, counters (c)); + OUTS (outf, " = "); + OUTS (outf, pregs (reg)); + OUTS (outf, " >> 0x1"); + } + else + return 0; + + return 4; +} + +static int +decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* LDIMMhalf + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......| + |.hword.........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask); + int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask); + int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask); + int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask); + int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask); + int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask); + + bu32 *pval = get_allreg (grp, reg); + + if (priv->parallel) + return 0; + + /* Since we don't have 32-bit immediate loads, we allow the disassembler + to combine them, so it prints out the right values. + Here we keep track of the registers. */ + if (H == 0 && S == 1 && Z == 0) + { + /* regs = imm16 (x) */ + *pval = imm16_val (hword); + if (hword & 0x8000) + *pval |= 0xFFFF0000; + else + *pval &= 0xFFFF; + } + else if (H == 0 && S == 0 && Z == 1) + { + /* regs = luimm16 (Z) */ + *pval = luimm16_val (hword); + *pval &= 0xFFFF; + } + else if (H == 0 && S == 0 && Z == 0) + { + /* regs_lo = luimm16 */ + *pval &= 0xFFFF0000; + *pval |= luimm16_val (hword); + } + else if (H == 1 && S == 0 && Z == 0) + { + /* regs_hi = huimm16 */ + *pval &= 0xFFFF; + *pval |= luimm16_val (hword) << 16; + } + + /* Here we do the disassembly */ + if (grp == 0 && H == 0 && S == 0 && Z == 0) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + } + else if (grp == 0 && H == 1 && S == 0 && Z == 0) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + } + else if (grp == 0 && H == 0 && S == 1 && Z == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = "); + OUTS (outf, imm16 (hword)); + OUTS (outf, " (X)"); + } + else if (H == 0 && S == 1 && Z == 0) + { + OUTS (outf, regs (reg, grp)); + OUTS (outf, " = "); + OUTS (outf, imm16 (hword)); + OUTS (outf, " (X)"); + } + else if (H == 0 && S == 0 && Z == 1) + { + OUTS (outf, regs (reg, grp)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + OUTS (outf, " (Z)"); + } + else if (H == 0 && S == 0 && Z == 0) + { + OUTS (outf, regs_lo (reg, grp)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + } + else if (H == 1 && S == 0 && Z == 0) + { + OUTS (outf, regs_hi (reg, grp)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + } + else + return 0; + + /* And we print out the 32-bit value if it is a pointer. */ + if (S == 0 && Z == 0) + { + OUTS (outf, ";\t\t/* ("); + OUTS (outf, imm16d (hword)); + OUTS (outf, ")\t"); + + /* If it is an MMR, don't print the symbol. */ + if (*pval < 0xFFC00000 && grp == 1) + { + OUTS (outf, regs (reg, grp)); + OUTS (outf, "=0x"); + OUTS (outf, huimm32e (*pval)); + } + else + { + OUTS (outf, regs (reg, grp)); + OUTS (outf, "=0x"); + OUTS (outf, huimm32e (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ")"); + } + + OUTS (outf, " */"); + priv->comment = TRUE; + } + if (S == 1 || Z == 1) + { + OUTS (outf, ";\t\t/*\t\t"); + OUTS (outf, regs (reg, grp)); + OUTS (outf, "=0x"); + OUTS (outf, huimm32e (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ") */"); + priv->comment = TRUE; + } + return 4; +} + +static int +decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* CALLa + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................| + |.lsw...........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask); + int lsw = ((iw1 >> 0) & 0xffff); + int msw = ((iw0 >> 0) & 0xff); + + if (priv->parallel) + return 0; + + if (S == 1) + OUTS (outf, "CALL 0x"); + else if (S == 0) + OUTS (outf, "JUMP.L 0x"); + else + return 0; + + OUTS (outf, pcrel24 (((msw) << 16) | (lsw))); + return 4; +} + +static int +decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* LDSTidxI + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......| + |.offset........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask); + int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask); + int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask); + int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask); + int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask); + int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask); + + if (W == 0 && sz == 0 && Z == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s4 (offset)); + OUTS (outf, "]"); + } + else if (W == 0 && sz == 0 && Z == 1) + { + OUTS (outf, pregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s4 (offset)); + OUTS (outf, "]"); + } + else if (W == 0 && sz == 1 && Z == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s2 (offset)); + OUTS (outf, "] (Z)"); + } + else if (W == 0 && sz == 1 && Z == 1) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s2 (offset)); + OUTS (outf, "] (X)"); + } + else if (W == 0 && sz == 2 && Z == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16 (offset)); + OUTS (outf, "] (Z)"); + } + else if (W == 0 && sz == 2 && Z == 1) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16 (offset)); + OUTS (outf, "] (X)"); + } + else if (W == 1 && sz == 0 && Z == 0) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s4 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (W == 1 && sz == 0 && Z == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s4 (offset)); + OUTS (outf, "] = "); + OUTS (outf, pregs (reg)); + } + else if (W == 1 && sz == 1 && Z == 0) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s2 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (W == 1 && sz == 2 && Z == 0) + { + OUTS (outf, "B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else + return 0; + + return 4; +} + +static int +decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* linkage + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.| + |.framesize.....................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask); + int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask); + + if (priv->parallel) + return 0; + + if (R == 0) + { + OUTS (outf, "LINK "); + OUTS (outf, uimm16s4 (framesize)); + OUTS (outf, ";\t\t/* ("); + OUTS (outf, uimm16s4d (framesize)); + OUTS (outf, ") */"); + priv->comment = TRUE; + } + else if (R == 1) + OUTS (outf, "UNLINK"); + else + return 0; + + return 4; +} + +static int +decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* dsp32mac + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| + |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask); + int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); + int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); + int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask); + int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); + int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); + int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); + int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask); + int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); + int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); + int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask); + int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); + int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask); + int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask); + + if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3) + return 0; + + if (op1 == 3 && MM) + return 0; + + if ((w1 || w0) && mmod == M_W32) + return 0; + + if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0) + return 0; + + if (w1 == 1 || op1 != 3) + { + if (w1) + OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst)); + + if (op1 == 3) + OUTS (outf, " = A1"); + else + { + if (w1) + OUTS (outf, " = ("); + decode_macfunc (1, op1, h01, h11, src0, src1, outf); + if (w1) + OUTS (outf, ")"); + } + + if (w0 == 1 || op0 != 3) + { + if (MM) + OUTS (outf, " (M)"); + OUTS (outf, ", "); + } + } + + if (w0 == 1 || op0 != 3) + { + /* Clear MM option since it only matters for MAC1, and if we made + it this far, we've already shown it or we want to ignore it. */ + MM = 0; + + if (w0) + OUTS (outf, P ? dregs (dst) : dregs_lo (dst)); + + if (op0 == 3) + OUTS (outf, " = A0"); + else + { + if (w0) + OUTS (outf, " = ("); + decode_macfunc (0, op0, h00, h10, src0, src1, outf); + if (w0) + OUTS (outf, ")"); + } + } + + decode_optmode (mmod, MM, outf); + + return 4; +} + +static int +decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* dsp32mult + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| + |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); + int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); + int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask); + int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); + int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); + int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); + int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask); + int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); + int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); + int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask); + int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask); + int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask); + + if (w1 == 0 && w0 == 0) + return 0; + + if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0) + return 0; + + if (w1) + { + OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst)); + OUTS (outf, " = "); + decode_multfunc (h01, h11, src0, src1, outf); + + if (w0) + { + if (MM) + OUTS (outf, " (M)"); + MM = 0; + OUTS (outf, ", "); + } + } + + if (w0) + { + OUTS (outf, P ? dregs (dst) : dregs_lo (dst)); + OUTS (outf, " = "); + decode_multfunc (h00, h10, src0, src1, outf); + } + + decode_optmode (mmod, MM, outf); + return 4; +} + +static int +decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* dsp32alu + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| + |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask); + int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask); + int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask); + int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); + int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask); + int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask); + int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask); + int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask); + int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask); + + if (aop == 0 && aopcde == 9 && HL == 0 && s == 0) + { + OUTS (outf, "A0.L = "); + OUTS (outf, dregs_lo (src0)); + } + else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0) + { + OUTS (outf, "A1.H = "); + OUTS (outf, dregs_hi (src0)); + } + else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0) + { + OUTS (outf, "A1.L = "); + OUTS (outf, dregs_lo (src0)); + } + else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0) + { + OUTS (outf, "A0.H = "); + OUTS (outf, dregs_hi (src0)); + } + else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND20)"); + } + else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND20)"); + } + else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND12)"); + } + else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND12)"); + } + else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND20)"); + } + else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND12)"); + } + else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND20)"); + } + else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND12)"); + } + else if (HL == 1 && aop == 0 && aopcde == 2) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 1 && aopcde == 2) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 2 && aopcde == 2) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 3 && aopcde == 2) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 0 && aopcde == 3) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 1 && aopcde == 3) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 3 && aopcde == 2) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 0 && aopcde == 3) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 1 && aopcde == 3) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 2 && aopcde == 3) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 3 && aopcde == 3) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 2 && aopcde == 2) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 1 && aopcde == 2) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 2 && aopcde == 3) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 3 && aopcde == 3) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 0 && aopcde == 2) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (aop == 0 && aopcde == 9 && s == 1) + { + OUTS (outf, "A0 = "); + OUTS (outf, dregs (src0)); + } + else if (aop == 3 && aopcde == 11 && s == 0) + OUTS (outf, "A0 -= A1"); + + else if (aop == 3 && aopcde == 11 && s == 1) + OUTS (outf, "A0 -= A1 (W32)"); + + else if (aop == 1 && aopcde == 22 && HL == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP2P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (TH"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 1 && aopcde == 22 && HL == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP2P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (TL"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 0 && aopcde == 22 && HL == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP2P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (RNDH"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 0 && aopcde == 22 && HL == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP2P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (RNDL"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 0 && s == 0 && aopcde == 8) + OUTS (outf, "A0 = 0"); + + else if (aop == 0 && s == 1 && aopcde == 8) + OUTS (outf, "A0 = A0 (S)"); + + else if (aop == 1 && s == 0 && aopcde == 8) + OUTS (outf, "A1 = 0"); + + else if (aop == 1 && s == 1 && aopcde == 8) + OUTS (outf, "A1 = A1 (S)"); + + else if (aop == 2 && s == 0 && aopcde == 8) + OUTS (outf, "A1 = A0 = 0"); + + else if (aop == 2 && s == 1 && aopcde == 8) + OUTS (outf, "A1 = A1 (S), A0 = A0 (S)"); + + else if (aop == 3 && s == 0 && aopcde == 8) + OUTS (outf, "A0 = A1"); + + else if (aop == 3 && s == 1 && aopcde == 8) + OUTS (outf, "A1 = A0"); + + else if (aop == 1 && aopcde == 9 && s == 0) + { + OUTS (outf, "A0.X = "); + OUTS (outf, dregs_lo (src0)); + } + else if (aop == 1 && HL == 0 && aopcde == 11) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = (A0 += A1)"); + } + else if (aop == 3 && HL == 0 && aopcde == 16) + OUTS (outf, "A1 = ABS A1, A0 = ABS A0"); + + else if (aop == 0 && aopcde == 23 && HL == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP3P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (HI"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 3 && aopcde == 9 && s == 0) + { + OUTS (outf, "A1.X = "); + OUTS (outf, dregs_lo (src0)); + } + else if (aop == 1 && HL == 1 && aopcde == 16) + OUTS (outf, "A1 = ABS A1"); + + else if (aop == 0 && HL == 1 && aopcde == 16) + OUTS (outf, "A1 = ABS A0"); + + else if (aop == 2 && aopcde == 9 && s == 1) + { + OUTS (outf, "A1 = "); + OUTS (outf, dregs (src0)); + } + else if (HL == 0 && aop == 3 && aopcde == 12) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " (RND)"); + } + else if (aop == 1 && HL == 0 && aopcde == 16) + OUTS (outf, "A0 = ABS A1"); + + else if (aop == 0 && HL == 0 && aopcde == 16) + OUTS (outf, "A0 = ABS A0"); + + else if (aop == 3 && HL == 0 && aopcde == 15) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = -"); + OUTS (outf, dregs (src0)); + OUTS (outf, " (V)"); + } + else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = -"); + OUTS (outf, dregs (src0)); + OUTS (outf, " (S)"); + } + else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = -"); + OUTS (outf, dregs (src0)); + OUTS (outf, " (NS)"); + } + else if (aop == 1 && HL == 1 && aopcde == 11) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = (A0 += A1)"); + } + else if (aop == 2 && aopcde == 11 && s == 0) + OUTS (outf, "A0 += A1"); + + else if (aop == 2 && aopcde == 11 && s == 1) + OUTS (outf, "A0 += A1 (W32)"); + + else if (aop == 3 && HL == 0 && aopcde == 14) + OUTS (outf, "A1 = -A1, A0 = -A0"); + + else if (HL == 1 && aop == 3 && aopcde == 12) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " (RND)"); + } + else if (aop == 0 && aopcde == 23 && HL == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP3P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (LO"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 0 && HL == 0 && aopcde == 14) + OUTS (outf, "A0 = -A0"); + + else if (aop == 1 && HL == 0 && aopcde == 14) + OUTS (outf, "A0 = -A1"); + + else if (aop == 0 && HL == 1 && aopcde == 14) + OUTS (outf, "A1 = -A0"); + + else if (aop == 1 && HL == 1 && aopcde == 14) + OUTS (outf, "A1 = -A1"); + + else if (aop == 0 && aopcde == 12) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGN ("); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, ") * "); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, " + SIGN ("); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ") * "); + OUTS (outf, dregs_lo (src1)); + } + else if (aop == 2 && aopcde == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " -|+ "); + OUTS (outf, dregs (src1)); + amod0 (s, x, outf); + } + else if (aop == 1 && aopcde == 12) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = A1.L + A1.H, "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = A0.L + A0.H"); + } + else if (aop == 2 && aopcde == 4) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aopcde == 1) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " +|+ "); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " -|- "); + OUTS (outf, dregs (src1)); + amod0amod2 (s, x, aop, outf); + } + else if (aop == 0 && aopcde == 11) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = (A0 += A1)"); + } + else if (aop == 0 && aopcde == 10) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = A0.X"); + } + else if (aop == 1 && aopcde == 10) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = A1.X"); + } + else if (aop == 1 && aopcde == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " +|- "); + OUTS (outf, dregs (src1)); + amod0 (s, x, outf); + } + else if (aop == 3 && aopcde == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " -|- "); + OUTS (outf, dregs (src1)); + amod0 (s, x, outf); + } + else if (aop == 1 && aopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + amod1 (s, x, outf); + } + else if (aop == 0 && aopcde == 17) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = A1 + A0, "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = A1 - A0"); + amod1 (s, x, outf); + } + else if (aop == 1 && aopcde == 17) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = A0 + A1, "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = A0 - A1"); + amod1 (s, x, outf); + } + else if (aop == 0 && aopcde == 18) + { + OUTS (outf, "SAA ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); + aligndir (s, outf); + } + else if (aop == 3 && aopcde == 18) + OUTS (outf, "DISALGNEXCPT"); + + else if (aop == 0 && aopcde == 20) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP1P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); + aligndir (s, outf); + } + else if (aop == 1 && aopcde == 20) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP1P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (T"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 0 && aopcde == 21) + { + OUTS (outf, "("); + OUTS (outf, dregs (dst1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, ") = BYTEOP16P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); + aligndir (s, outf); + } + else if (aop == 1 && aopcde == 21) + { + OUTS (outf, "("); + OUTS (outf, dregs (dst1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, ") = BYTEOP16M ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); + aligndir (s, outf); + } + else if (aop == 2 && aopcde == 7) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ABS "); + OUTS (outf, dregs (src0)); + } + else if (aop == 1 && aopcde == 7) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = MIN ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ")"); + } + else if (aop == 0 && aopcde == 7) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = MAX ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ")"); + } + else if (aop == 2 && aopcde == 6) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ABS "); + OUTS (outf, dregs (src0)); + OUTS (outf, " (V)"); + } + else if (aop == 1 && aopcde == 6) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = MIN ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ") (V)"); + } + else if (aop == 0 && aopcde == 6) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = MAX ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ") (V)"); + } + else if (HL == 1 && aopcde == 1) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " +|- "); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " -|+ "); + OUTS (outf, dregs (src1)); + amod0amod2 (s, x, aop, outf); + } + else if (aop == 0 && aopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + amod1 (s, x, outf); + } + else if (aop == 0 && aopcde == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " +|+ "); + OUTS (outf, dregs (src1)); + amod0 (s, x, outf); + } + else if (aop == 0 && aopcde == 24) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEPACK ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ")"); + } + else if (aop == 1 && aopcde == 24) + { + OUTS (outf, "("); + OUTS (outf, dregs (dst1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, ") = BYTEUNPACK "); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + aligndir (s, outf); + } + else if (aopcde == 13) + { + OUTS (outf, "("); + OUTS (outf, dregs (dst1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, ") = SEARCH "); + OUTS (outf, dregs (src0)); + OUTS (outf, " ("); + searchmod (aop, outf); + OUTS (outf, ")"); + } + else + return 0; + + return 4; +} + +static int +decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* dsp32shift + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| + |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask); + int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask); + int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); + int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask); + int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask); + int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask); + const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1"; + + if (HLs == 0 && sop == 0 && sopcde == 0) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (HLs == 1 && sop == 0 && sopcde == 0) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (HLs == 2 && sop == 0 && sopcde == 0) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (HLs == 3 && sop == 0 && sopcde == 0) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (HLs == 0 && sop == 1 && sopcde == 0) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (S)"); + } + else if (HLs == 1 && sop == 1 && sopcde == 0) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (S)"); + } + else if (HLs == 2 && sop == 1 && sopcde == 0) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (S)"); + } + else if (HLs == 3 && sop == 1 && sopcde == 0) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (S)"); + } + else if (sop == 2 && sopcde == 0) + { + OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0)); + OUTS (outf, " = LSHIFT "); + OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 0 && sopcde == 3) + { + OUTS (outf, acc01); + OUTS (outf, " = ASHIFT "); + OUTS (outf, acc01); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 1 && sopcde == 3) + { + OUTS (outf, acc01); + OUTS (outf, " = LSHIFT "); + OUTS (outf, acc01); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 2 && sopcde == 3) + { + OUTS (outf, acc01); + OUTS (outf, " = ROT "); + OUTS (outf, acc01); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 3 && sopcde == 3) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ROT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 1 && sopcde == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (V, S)"); + } + else if (sop == 0 && sopcde == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (V)"); + } + else if (sop == 0 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 1 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (S)"); + } + else if (sop == 2 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = LSHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 3 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ROT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 2 && sopcde == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = LSHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (V)"); + } + else if (sop == 0 && sopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = PACK ("); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ")"); + } + else if (sop == 1 && sopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = PACK ("); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, ")"); + } + else if (sop == 2 && sopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = PACK ("); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ")"); + } + else if (sop == 3 && sopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = PACK ("); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, ")"); + } + else if (sop == 0 && sopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGNBITS "); + OUTS (outf, dregs (src1)); + } + else if (sop == 1 && sopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGNBITS "); + OUTS (outf, dregs_lo (src1)); + } + else if (sop == 2 && sopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGNBITS "); + OUTS (outf, dregs_hi (src1)); + } + else if (sop == 0 && sopcde == 6) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGNBITS A0"); + } + else if (sop == 1 && sopcde == 6) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGNBITS A1"); + } + else if (sop == 3 && sopcde == 6) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = ONES "); + OUTS (outf, dregs (src1)); + } + else if (sop == 0 && sopcde == 7) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = EXPADJ ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ")"); + } + else if (sop == 1 && sopcde == 7) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = EXPADJ ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ") (V)"); + } + else if (sop == 2 && sopcde == 7) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = EXPADJ ("); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ")"); + } + else if (sop == 3 && sopcde == 7) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = EXPADJ ("); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ")"); + } + else if (sop == 0 && sopcde == 8) + { + OUTS (outf, "BITMUX ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ", A0) (ASR)"); + } + else if (sop == 1 && sopcde == 8) + { + OUTS (outf, "BITMUX ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ", A0) (ASL)"); + } + else if (sop == 0 && sopcde == 9) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = VIT_MAX ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ") (ASL)"); + } + else if (sop == 1 && sopcde == 9) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = VIT_MAX ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ") (ASR)"); + } + else if (sop == 2 && sopcde == 9) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = VIT_MAX ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ") (ASL)"); + } + else if (sop == 3 && sopcde == 9) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = VIT_MAX ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ") (ASR)"); + } + else if (sop == 0 && sopcde == 10) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = EXTRACT ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ") (Z)"); + } + else if (sop == 1 && sopcde == 10) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = EXTRACT ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ") (X)"); + } + else if (sop == 2 && sopcde == 10) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = DEPOSIT ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else if (sop == 3 && sopcde == 10) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = DEPOSIT ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ") (X)"); + } + else if (sop == 0 && sopcde == 11) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = CC = BXORSHIFT (A0, "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else if (sop == 1 && sopcde == 11) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = CC = BXOR (A0, "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else if (sop == 0 && sopcde == 12) + OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)"); + + else if (sop == 1 && sopcde == 12) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = CC = BXOR (A0, A1, CC)"); + } + else if (sop == 0 && sopcde == 13) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ALIGN8 ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else if (sop == 1 && sopcde == 13) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ALIGN16 ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else if (sop == 2 && sopcde == 13) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ALIGN24 ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else + return 0; + + return 4; +} + +static int +decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* dsp32shiftimm + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| + |.sop...|.HLs...|.dst0......|.immag.................|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask); + int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask); + int bit8 = ((iw1 >> 8) & 0x1); + int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask); + int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask); + int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask); + int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask); + int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask); + + if (sop == 0 && sopcde == 0) + { + OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); + OUTS (outf, " >>> "); + OUTS (outf, uimm4 (newimmag)); + } + else if (sop == 1 && sopcde == 0 && bit8 == 0) + { + OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); + OUTS (outf, " << "); + OUTS (outf, uimm4 (immag)); + OUTS (outf, " (S)"); + } + else if (sop == 1 && sopcde == 0 && bit8 == 1) + { + OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); + OUTS (outf, " >>> "); + OUTS (outf, uimm4 (newimmag)); + OUTS (outf, " (S)"); + } + else if (sop == 2 && sopcde == 0 && bit8 == 0) + { + OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); + OUTS (outf, " << "); + OUTS (outf, uimm4 (immag)); + } + else if (sop == 2 && sopcde == 0 && bit8 == 1) + { + OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); + OUTS (outf, " >> "); + OUTS (outf, uimm4 (newimmag)); + } + else if (sop == 2 && sopcde == 3 && HLs == 1) + { + OUTS (outf, "A1 = ROT A1 BY "); + OUTS (outf, imm6 (immag)); + } + else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0) + { + OUTS (outf, "A0 = A0 << "); + OUTS (outf, uimm5 (immag)); + } + else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1) + { + OUTS (outf, "A0 = A0 >>> "); + OUTS (outf, uimm5 (newimmag)); + } + else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0) + { + OUTS (outf, "A1 = A1 << "); + OUTS (outf, uimm5 (immag)); + } + else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1) + { + OUTS (outf, "A1 = A1 >>> "); + OUTS (outf, uimm5 (newimmag)); + } + else if (sop == 1 && sopcde == 3 && HLs == 0) + { + OUTS (outf, "A0 = A0 >> "); + OUTS (outf, uimm5 (newimmag)); + } + else if (sop == 1 && sopcde == 3 && HLs == 1) + { + OUTS (outf, "A1 = A1 >> "); + OUTS (outf, uimm5 (newimmag)); + } + else if (sop == 2 && sopcde == 3 && HLs == 0) + { + OUTS (outf, "A0 = ROT A0 BY "); + OUTS (outf, imm6 (immag)); + } + else if (sop == 1 && sopcde == 1 && bit8 == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " << "); + OUTS (outf, uimm5 (immag)); + OUTS (outf, " (V, S)"); + } + else if (sop == 1 && sopcde == 1 && bit8 == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " >>> "); + OUTS (outf, imm5 (-immag)); + OUTS (outf, " (V, S)"); + } + else if (sop == 2 && sopcde == 1 && bit8 == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " >> "); + OUTS (outf, uimm5 (newimmag)); + OUTS (outf, " (V)"); + } + else if (sop == 2 && sopcde == 1 && bit8 == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " << "); + OUTS (outf, imm5 (immag)); + OUTS (outf, " (V)"); + } + else if (sop == 0 && sopcde == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " >>> "); + OUTS (outf, uimm5 (newimmag)); + OUTS (outf, " (V)"); + } + else if (sop == 1 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " << "); + OUTS (outf, uimm5 (immag)); + OUTS (outf, " (S)"); + } + else if (sop == 2 && sopcde == 2 && bit8 == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " >> "); + OUTS (outf, uimm5 (newimmag)); + } + else if (sop == 2 && sopcde == 2 && bit8 == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " << "); + OUTS (outf, uimm5 (immag)); + } + else if (sop == 3 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ROT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, imm6 (immag)); + } + else if (sop == 0 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " >>> "); + OUTS (outf, uimm5 (newimmag)); + } + else + return 0; + + return 4; +} + +static int +decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* pseudoDEBUG + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask); + int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask); + int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask); + + if (priv->parallel) + return 0; + + if (reg == 0 && fn == 3) + OUTS (outf, "DBG A0"); + + else if (reg == 1 && fn == 3) + OUTS (outf, "DBG A1"); + + else if (reg == 3 && fn == 3) + OUTS (outf, "ABORT"); + + else if (reg == 4 && fn == 3) + OUTS (outf, "HLT"); + + else if (reg == 5 && fn == 3) + OUTS (outf, "DBGHALT"); + + else if (reg == 6 && fn == 3) + { + OUTS (outf, "DBGCMPLX ("); + OUTS (outf, dregs (grp)); + OUTS (outf, ")"); + } + else if (reg == 7 && fn == 3) + OUTS (outf, "DBG"); + + else if (grp == 0 && fn == 2) + { + OUTS (outf, "OUTC "); + OUTS (outf, dregs (reg)); + } + else if (fn == 0) + { + OUTS (outf, "DBG "); + OUTS (outf, allregs (reg, grp)); + } + else if (fn == 1) + { + OUTS (outf, "PRNT "); + OUTS (outf, allregs (reg, grp)); + } + else + return 0; + + return 2; +} + +static int +decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* psedoOChar + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask); + + if (priv->parallel) + return 0; + + OUTS (outf, "OUTC "); + OUTS (outf, uimm8 (ch)); + + return 2; +} + +static int +decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + /* pseudodbg_assert + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...| + |.expected......................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask); + int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask); + int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask); + int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask); + + if (priv->parallel) + return 0; + + if (dbgop == 0) + { + OUTS (outf, "DBGA ("); + OUTS (outf, regs_lo (regtest, grp)); + OUTS (outf, ", "); + OUTS (outf, uimm16 (expected)); + OUTS (outf, ")"); + } + else if (dbgop == 1) + { + OUTS (outf, "DBGA ("); + OUTS (outf, regs_hi (regtest, grp)); + OUTS (outf, ", "); + OUTS (outf, uimm16 (expected)); + OUTS (outf, ")"); + } + else if (dbgop == 2) + { + OUTS (outf, "DBGAL ("); + OUTS (outf, allregs (regtest, grp)); + OUTS (outf, ", "); + OUTS (outf, uimm16 (expected)); + OUTS (outf, ")"); + } + else if (dbgop == 3) + { + OUTS (outf, "DBGAH ("); + OUTS (outf, allregs (regtest, grp)); + OUTS (outf, ", "); + OUTS (outf, uimm16 (expected)); + OUTS (outf, ")"); + } + else + return 0; + return 4; +} + +static int +ifetch (bfd_vma pc, disassemble_info *outf, TIword *iw) +{ + bfd_byte buf[2]; + int status; + + status = (*outf->read_memory_func) (pc, buf, 2, outf); + if (status != 0) + { + (*outf->memory_error_func) (status, pc, outf); + return -1; + } + + *iw = bfd_getl16 (buf); + return 0; +} + +static int +_print_insn_bfin (bfd_vma pc, disassemble_info *outf) +{ + struct private *priv = outf->private_data; + TIword iw0; + TIword iw1; + int rv = 0; + + /* The PC must be 16-bit aligned. */ + if (pc & 1) + { + OUTS (outf, "ILLEGAL (UNALIGNED)"); + /* For people dumping data, just re-align the return value. */ + return 1; + } + + if (ifetch (pc, outf, &iw0)) + return -1; + priv->iw0 = iw0; + + if ((iw0 & 0xc000) == 0xc000) + { + /* 32-bit insn. */ + if (ifetch (pc + 2, outf, &iw1)) + return -1; + } + else + /* 16-bit insn. */ + iw1 = 0; + + if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800) + { + if (priv->parallel) + { + OUTS (outf, "ILLEGAL"); + return 0; + } + OUTS (outf, "MNOP"); + return 4; + } + else if ((iw0 & 0xff00) == 0x0000) + rv = decode_ProgCtrl_0 (iw0, outf); + else if ((iw0 & 0xffc0) == 0x0240) + rv = decode_CaCTRL_0 (iw0, outf); + else if ((iw0 & 0xff80) == 0x0100) + rv = decode_PushPopReg_0 (iw0, outf); + else if ((iw0 & 0xfe00) == 0x0400) + rv = decode_PushPopMultiple_0 (iw0, outf); + else if ((iw0 & 0xfe00) == 0x0600) + rv = decode_ccMV_0 (iw0, outf); + else if ((iw0 & 0xf800) == 0x0800) + rv = decode_CCflag_0 (iw0, outf); + else if ((iw0 & 0xffe0) == 0x0200) + rv = decode_CC2dreg_0 (iw0, outf); + else if ((iw0 & 0xff00) == 0x0300) + rv = decode_CC2stat_0 (iw0, outf); + else if ((iw0 & 0xf000) == 0x1000) + rv = decode_BRCC_0 (iw0, pc, outf); + else if ((iw0 & 0xf000) == 0x2000) + rv = decode_UJUMP_0 (iw0, pc, outf); + else if ((iw0 & 0xf000) == 0x3000) + rv = decode_REGMV_0 (iw0, outf); + else if ((iw0 & 0xfc00) == 0x4000) + rv = decode_ALU2op_0 (iw0, outf); + else if ((iw0 & 0xfe00) == 0x4400) + rv = decode_PTR2op_0 (iw0, outf); + else if ((iw0 & 0xf800) == 0x4800) + rv = decode_LOGI2op_0 (iw0, outf); + else if ((iw0 & 0xf000) == 0x5000) + rv = decode_COMP3op_0 (iw0, outf); + else if ((iw0 & 0xf800) == 0x6000) + rv = decode_COMPI2opD_0 (iw0, outf); + else if ((iw0 & 0xf800) == 0x6800) + rv = decode_COMPI2opP_0 (iw0, outf); + else if ((iw0 & 0xf000) == 0x8000) + rv = decode_LDSTpmod_0 (iw0, outf); + else if ((iw0 & 0xff60) == 0x9e60) + rv = decode_dagMODim_0 (iw0, outf); + else if ((iw0 & 0xfff0) == 0x9f60) + rv = decode_dagMODik_0 (iw0, outf); + else if ((iw0 & 0xfc00) == 0x9c00) + rv = decode_dspLDST_0 (iw0, outf); + else if ((iw0 & 0xf000) == 0x9000) + rv = decode_LDST_0 (iw0, outf); + else if ((iw0 & 0xfc00) == 0xb800) + rv = decode_LDSTiiFP_0 (iw0, outf); + else if ((iw0 & 0xe000) == 0xA000) + rv = decode_LDSTii_0 (iw0, outf); + else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000) + rv = decode_LoopSetup_0 (iw0, iw1, pc, outf); + else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000) + rv = decode_LDIMMhalf_0 (iw0, iw1, outf); + else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000) + rv = decode_CALLa_0 (iw0, iw1, pc, outf); + else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000) + rv = decode_LDSTidxI_0 (iw0, iw1, outf); + else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000) + rv = decode_linkage_0 (iw0, iw1, outf); + else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000) + rv = decode_dsp32mac_0 (iw0, iw1, outf); + else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000) + rv = decode_dsp32mult_0 (iw0, iw1, outf); + else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000) + rv = decode_dsp32alu_0 (iw0, iw1, outf); + else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000) + rv = decode_dsp32shift_0 (iw0, iw1, outf); + else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000) + rv = decode_dsp32shiftimm_0 (iw0, iw1, outf); + else if ((iw0 & 0xff00) == 0xf800) + rv = decode_pseudoDEBUG_0 (iw0, outf); + else if ((iw0 & 0xFF00) == 0xF900) + rv = decode_pseudoOChar_0 (iw0, outf); + else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000) + rv = decode_pseudodbg_assert_0 (iw0, iw1, outf); + + if (rv == 0) + OUTS (outf, "ILLEGAL"); + + return rv; +} + +int +print_insn_bfin (bfd_vma pc, disassemble_info *outf) +{ + struct private priv; + int count; + + priv.parallel = FALSE; + priv.comment = FALSE; + outf->private_data = &priv; + + count = _print_insn_bfin (pc, outf); + if (count == -1) + return -1; + + /* Proper display of multiple issue instructions. */ + + if (count == 4 && (priv.iw0 & 0xc000) == 0xc000 && (priv.iw0 & BIT_MULTI_INS) + && ((priv.iw0 & 0xe800) != 0xe800 /* Not Linkage. */ )) + { + bfd_boolean legal = TRUE; + int len; + + priv.parallel = TRUE; + OUTS (outf, " || "); + len = _print_insn_bfin (pc + 4, outf); + if (len == -1) + return -1; + OUTS (outf, " || "); + if (len != 2) + legal = FALSE; + len = _print_insn_bfin (pc + 6, outf); + if (len == -1) + return -1; + if (len != 2) + legal = FALSE; + + if (legal) + count = 8; + else + { + OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */"); + priv.comment = TRUE; + count = 0; + } + } + + if (!priv.comment) + OUTS (outf, ";"); + + if (count == 0) + return 2; + + return count; +} diff --git a/hw/bfin/Makefile.objs b/hw/bfin/Makefile.objs new file mode 100644 index 0000000000000..f589c49b6f429 --- /dev/null +++ b/hw/bfin/Makefile.objs @@ -0,0 +1,12 @@ +obj-y += bfin_boards.o + +# Core models. +obj-y += bfin_evt.o +obj-y += bfin_mmu.o +obj-y += bfin_trace.o + +# Peripheral models. +obj-y += bfin_dma.o +obj-y += bfin_pll.o +obj-y += bfin_sic.o +obj-y += bfin_uart.o diff --git a/hw/bfin/bfin_boards.c b/hw/bfin/bfin_boards.c new file mode 100644 index 0000000000000..7969e02e6c835 --- /dev/null +++ b/hw/bfin/bfin_boards.c @@ -0,0 +1,185 @@ +/* + * Blackfin board models + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "elf.h" +#include "hw/sysbus.h" +#include "sysemu/char.h" +#include "sysemu/sysemu.h" +#include "exec/address-spaces.h" + +struct bfin_memory_layout { + hwaddr addr; + ram_addr_t len; + const char *name; +}; +#define LAYOUT(_addr, _len, _name) { .addr = _addr, .len = _len, .name = _name, } + +static const struct bfin_memory_layout bf537_mem[] = +{ + LAYOUT(0xFF800000, 0x4000, "L1 Data A"), + LAYOUT(0xFF804000, 0x4000, "Data A Cache"), + LAYOUT(0xFF900000, 0x4000, "Data B"), + LAYOUT(0xFF904000, 0x4000, "Data B Cache"), + LAYOUT(0xFFA00000, 0x8000, "Inst A"), + LAYOUT(0xFFA08000, 0x4000, "Inst B"), + LAYOUT(0xFFA10000, 0x4000, "Inst Cache"), + LAYOUT(0, 0, "SDRAM"), +}; + +static const struct bfin_memory_layout bf51x_mem[] = +{ + LAYOUT(0xEF000000, 0x8000, "Boot ROM"), + LAYOUT(0xFF800000, 0x4000, "L1 Data A"), + LAYOUT(0xFF804000, 0x4000, "Data A Cache"), + LAYOUT(0xFF900000, 0x4000, "Data B"), + LAYOUT(0xFF904000, 0x4000, "Data B Cache"), + LAYOUT(0xFFA00000, 0x4000, "Inst A"), + LAYOUT(0xFFA04000, 0x4000, "Inst B"), + LAYOUT(0xFFA10000, 0x4000, "Inst Cache"), + LAYOUT(0xFFB00000, 0x1000, "Scratchpad SRAM"), + LAYOUT(0, 0, "SDRAM"), +}; + +static void bfin_memory_init(const struct bfin_memory_layout mem_layout[], ram_addr_t ram_size) +{ + MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *mem; + size_t i; + + for (i = 0; mem_layout[i].len; ++i) { + mem = g_new(MemoryRegion, 1); + memory_region_init_ram(mem, NULL, mem_layout[i].name, mem_layout[i].len, + &error_abort); + vmstate_register_ram_global(mem); + memory_region_add_subregion(address_space_mem, mem_layout[i].addr, mem); + } + + if (ram_size) { + mem = g_new(MemoryRegion, 1); + memory_region_init_ram(mem, NULL, mem_layout[i].name, ram_size, + &error_abort); + vmstate_register_ram_global(mem); + memory_region_add_subregion(address_space_mem, mem_layout[i].addr, mem); + } + + /* Address space reserved for on-chip (system) devices */ + mem = g_new(MemoryRegion, 1); + memory_region_init_reservation(mem, NULL, "System MMRs", 0x200000); + memory_region_add_subregion(address_space_mem, 0xFFC00000, mem); + + /* Address space reserved for on-chip (core) devices */ + mem = g_new(MemoryRegion, 1); + memory_region_init_reservation(mem, NULL, "Core MMRs", 0x200000); + memory_region_add_subregion(address_space_mem, 0xFFE00000, mem); +} + +static void bfin_device_init(void) +{ + /* Core peripherals */ + sysbus_create_simple("bfin_mmu", 0xFFE00000, NULL); + sysbus_create_simple("bfin_evt", 0xFFE02000, NULL); + sysbus_create_simple("bfin_trace", 0xFFE06000, NULL); + + /* System peripherals */ + /* XXX: BF537-specific */ + sysbus_create_simple("bfin_pll", 0xFFC00000, NULL); + sysbus_create_simple("bfin_sic", 0xFFC00100, NULL); + qemu_chr_new("bfin_uart0", "null", NULL); + sysbus_create_simple("bfin_uart", 0xFFC00400, NULL); + qemu_chr_new("bfin_uart1", "null", NULL); + sysbus_create_simple("bfin_uart", 0xFFC02000, NULL); +} + +static void bfin_common_init(const struct bfin_memory_layout mem_layout[], + ram_addr_t ram_size, const char *cpu_model, + const char *kernel_filename, const char *kernel_cmdline) +{ + CPUState *cs = NULL; + int n; + + ram_size *= 1024 * 1024; + bfin_memory_init(mem_layout, ram_size); + bfin_device_init(); + + for (n = 0; n < smp_cpus; n++) { + cs = cpu_init(cpu_model); + if (cs == NULL) { + fprintf(stderr, "Unable to find CPU definition!\n"); + exit(1); + } + } + + if (kernel_filename) { + uint64_t entry; + long kernel_size; + /* TODO: Not SMP safe. */ + CPUArchState *env = cs->env_ptr; + + kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL, + 0, ELF_MACHINE, 0, 0); + if (kernel_size < 0) { + kernel_size = load_image_targphys(kernel_filename, 0, ram_size); + } + if (kernel_size < 0) { + fprintf(stderr, "qemu: could not load kernel '%s'\n", + kernel_filename); + exit(1); + } + env->pc = entry; + + if (kernel_cmdline) { + pstrcpy_targphys("cmdline", kernel_size, -1, kernel_cmdline); + } + } +} + +static void bf537_stamp_init(MachineState *machine) +{ + bfin_common_init(bf537_mem, 64, "bf537", machine->kernel_filename, + machine->kernel_cmdline); +} + +static void bf537_stamp_machine_init(MachineClass *mc) +{ + mc->desc = "Analog Devices Blackfin ADSP-BF537 STAMP"; + mc->init = bf537_stamp_init; + mc->max_cpus = 1; + mc->is_default = 1; +} +DEFINE_MACHINE("bf537-stamp", bf537_stamp_machine_init) + +static void bf537_ezkit_machine_init(MachineClass *mc) +{ + mc->desc = "Analog Devices Blackfin ADSP-BF537 EZ-KIT"; + mc->init = bf537_stamp_init; + mc->max_cpus = 1; + mc->is_default = 0; +} +DEFINE_MACHINE("bf537-ezkit", bf537_ezkit_machine_init) + +static void bf514_dr05_init(MachineState *machine) +{ + bfin_common_init(bf51x_mem, 16, "bf514", machine->kernel_filename, + machine->kernel_cmdline); +} + +static void bf514_dr05_machine_init(MachineClass *mc) +{ + mc->desc = "Tascam DR-05 digital audio recorder"; + mc->init = bf514_dr05_init; + mc->max_cpus = 1; + mc->is_default = 0; +} +DEFINE_MACHINE("bf514-dr05", bf514_dr05_machine_init) diff --git a/hw/bfin/bfin_devices.h b/hw/bfin/bfin_devices.h new file mode 100644 index 0000000000000..552c74e67efac --- /dev/null +++ b/hw/bfin/bfin_devices.h @@ -0,0 +1,30 @@ +/* + * Common Blackfin device model code + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#ifndef BFIN_DEVICES_H +#define BFIN_DEVICES_H + +#define mmr_size() (sizeof(BfinMMRState) - mmr_base()) +#define mmr_offset(mmr) (offsetof(BfinMMRState, mmr) - mmr_base()) +#define mmr_idx(mmr) (mmr_offset(mmr) / 4) +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +#define HW_TRACE_WRITE() trace_bfin_reg_memory_write(addr + s->iomem.addr, \ + mmr_name (addr), size, value) +#define HW_TRACE_READ() trace_bfin_reg_memory_read(addr + s->iomem.addr, \ + mmr_name (addr), size) + +typedef int16_t bs16; +typedef int32_t bs32; +typedef uint16_t bu16; +typedef uint32_t bu32; + +#define BFIN_MMR_16(mmr) mmr, __pad_##mmr + +#endif diff --git a/hw/bfin/bfin_dma.c b/hw/bfin/bfin_dma.c new file mode 100644 index 0000000000000..29c66a81a7ad7 --- /dev/null +++ b/hw/bfin/bfin_dma.c @@ -0,0 +1,114 @@ +/* + * Blackfin Direct Memory Access (DMA) Channel model. + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "trace.h" +#include "bfin_devices.h" + +#define TYPE_BFIN_DMA "bfin_dma" +#define BFIN_DMA(obj) OBJECT_CHECK(BfinDMAState, (obj), TYPE_BFIN_DMA) + +typedef struct BfinDMAState { + SysBusDevice parent_obj; + MemoryRegion iomem; + + /* Order after here is important -- matches hardware MMR layout. */ + union { + struct { bu16 ndpl, ndph; }; + bu32 next_desc_ptr; + }; + union { + struct { bu16 sal, sah; }; + bu32 start_addr; + }; + bu16 BFIN_MMR_16 (config); + bu32 _pad0; + bu16 BFIN_MMR_16 (x_count); + bs16 BFIN_MMR_16 (x_modify); + bu16 BFIN_MMR_16 (y_count); + bs16 BFIN_MMR_16 (y_modify); + bu32 curr_desc_ptr, curr_addr; + bu16 BFIN_MMR_16 (irq_status); + bu16 BFIN_MMR_16 (peripheral_map); + bu16 BFIN_MMR_16 (curr_x_count); + bu32 _pad1; + bu16 BFIN_MMR_16 (curr_y_count); + bu32 _pad2; +} BfinDMAState; +#define BfinMMRState BfinDMAState +#define mmr_base() offsetof(BfinMMRState, next_desc_ptr) + +static const char * const mmr_names[] = +{ + "NEXT_DESC_PTR", "START_ADDR", "CONFIG", "", "X_COUNT", "X_MODIFY", + "Y_COUNT", "Y_MODIFY", "CURR_DESC_PTR", "CURR_ADDR", "IRQ_STATUS", + "PERIPHERAL_MAP", "CURR_X_COUNT", "", "CURR_Y_COUNT", "", +}; + +static void bfin_dma_io_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + BfinDMAState *s = opaque; + + HW_TRACE_WRITE(); +} + +static uint64_t bfin_dma_io_read(void *opaque, hwaddr addr, unsigned size) +{ + BfinDMAState *s = opaque; + + HW_TRACE_READ(); + + return 0; +} + +static const MemoryRegionOps bfin_dma_io_ops = { + .read = bfin_dma_io_read, + .write = bfin_dma_io_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 2, + .max_access_size = 4, + }, +}; + +static int bfin_dma_init(SysBusDevice *sbd) +{ + DeviceState *dev = DEVICE(sbd); + BfinDMAState *s = BFIN_DMA(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &bfin_dma_io_ops, s, "dma", mmr_size()); + sysbus_init_mmio(sbd, &s->iomem); + + return 0; +} + +static void bfin_dma_class_init(ObjectClass *klass, void *data) +{ +// DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = bfin_dma_init; +} + +static TypeInfo bfin_dma_info = { + .name = "bfin_dma", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BfinDMAState), + .class_init = bfin_dma_class_init, +}; + +static void bfin_dma_register_types(void) +{ + type_register_static(&bfin_dma_info); +} + +type_init(bfin_dma_register_types) diff --git a/hw/bfin/bfin_evt.c b/hw/bfin/bfin_evt.c new file mode 100644 index 0000000000000..a31ee1493ae50 --- /dev/null +++ b/hw/bfin/bfin_evt.c @@ -0,0 +1,96 @@ +/* + * Blackfin Event Vector Table (EVT) model. + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "trace.h" +#include "bfin_devices.h" + +#define TYPE_BFIN_EVT "bfin_evt" +#define BFIN_EVT(obj) OBJECT_CHECK(BfinEVTState, (obj), TYPE_BFIN_EVT) + +typedef struct BfinEVTState { + SysBusDevice parent_obj; + MemoryRegion iomem; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 evt[16]; +} BfinEVTState; +#define BfinMMRState BfinEVTState +#define mmr_base() offsetof(BfinMMRState, evt[0]) + +static const char * const mmr_names[0x2000 / 4] = +{ + "EVT0", "EVT1", "EVT2", "EVT3", "EVT4", "EVT5", "EVT6", "EVT7", "EVT8", + "EVT9", "EVT10", "EVT11", "EVT12", "EVT13", "EVT14", "EVT15", +}; + +static void bfin_evt_io_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + BfinEVTState *s = opaque; + bu32 *valuep = (void *)((uintptr_t)s + mmr_base() + addr); + + HW_TRACE_WRITE(); + + *valuep = value; +} + +static uint64_t bfin_evt_io_read(void *opaque, hwaddr addr, unsigned size) +{ + BfinEVTState *s = opaque; + bu32 *valuep = (void *)((uintptr_t)s + mmr_base() + addr); + + HW_TRACE_READ(); + + return *valuep; +} + +static const MemoryRegionOps bfin_evt_io_ops = { + .read = bfin_evt_io_read, + .write = bfin_evt_io_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static int bfin_evt_init(SysBusDevice *sbd) +{ + DeviceState *dev = DEVICE(sbd); + BfinEVTState *s = BFIN_EVT(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &bfin_evt_io_ops, s, "evt", mmr_size()); + sysbus_init_mmio(sbd, &s->iomem); + + return 0; +} + +static void bfin_evt_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = bfin_evt_init; +} + +static TypeInfo bfin_evt_info = { + .name = TYPE_BFIN_EVT, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BfinEVTState), + .class_init = bfin_evt_class_init, +}; + +static void bfin_evt_register_types(void) +{ + type_register_static(&bfin_evt_info); +} + +type_init(bfin_evt_register_types) diff --git a/hw/bfin/bfin_mmu.c b/hw/bfin/bfin_mmu.c new file mode 100644 index 0000000000000..38bdbca4f3ac5 --- /dev/null +++ b/hw/bfin/bfin_mmu.c @@ -0,0 +1,136 @@ +/* + * Blackfin Memory Management Unit (MMU) model. + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "trace.h" +#include "bfin_devices.h" + +#define TYPE_BFIN_MMU "bfin_mmu" +#define BFIN_MMU(obj) OBJECT_CHECK(BfinMMUState, (obj), TYPE_BFIN_MMU) + +typedef struct BfinMMUState { + SysBusDevice parent_obj; + MemoryRegion iomem; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 sram_base_address; + + bu32 dmem_control, dcplb_fault_status, dcplb_fault_addr; + char _dpad0[0x100 - 0x0 - (4 * 4)]; + bu32 dcplb_addr[16]; + char _dpad1[0x200 - 0x100 - (4 * 16)]; + bu32 dcplb_data[16]; + char _dpad2[0x300 - 0x200 - (4 * 16)]; + bu32 dtest_command; + char _dpad3[0x400 - 0x300 - (4 * 1)]; + bu32 dtest_data[2]; + + char _dpad4[0x1000 - 0x400 - (4 * 2)]; + + bu32 idk; /* Filler MMR; hardware simply ignores. */ + bu32 imem_control, icplb_fault_status, icplb_fault_addr; + char _ipad0[0x100 - 0x0 - (4 * 4)]; + bu32 icplb_addr[16]; + char _ipad1[0x200 - 0x100 - (4 * 16)]; + bu32 icplb_data[16]; + char _ipad2[0x300 - 0x200 - (4 * 16)]; + bu32 itest_command; + char _ipad3[0x400 - 0x300 - (4 * 1)]; + bu32 itest_data[2]; +} BfinMMUState; +#define BfinMMRState BfinMMUState +#define mmr_base() offsetof(BfinMMRState, sram_base_address) + +static const char * const mmr_names[0x2000 / 4] = +{ + "SRAM_BASE_ADDRESS", "DMEM_CONTROL", "DCPLB_FAULT_STATUS", "DCPLB_FAULT_ADDR", + [mmr_idx (dcplb_addr[0])] = "DCPLB_ADDR0", + "DCPLB_ADDR1", "DCPLB_ADDR2", "DCPLB_ADDR3", "DCPLB_ADDR4", "DCPLB_ADDR5", + "DCPLB_ADDR6", "DCPLB_ADDR7", "DCPLB_ADDR8", "DCPLB_ADDR9", "DCPLB_ADDR10", + "DCPLB_ADDR11", "DCPLB_ADDR12", "DCPLB_ADDR13", "DCPLB_ADDR14", "DCPLB_ADDR15", + [mmr_idx (dcplb_data[0])] = "DCPLB_DATA0", + "DCPLB_DATA1", "DCPLB_DATA2", "DCPLB_DATA3", "DCPLB_DATA4", "DCPLB_DATA5", + "DCPLB_DATA6", "DCPLB_DATA7", "DCPLB_DATA8", "DCPLB_DATA9", "DCPLB_DATA10", + "DCPLB_DATA11", "DCPLB_DATA12", "DCPLB_DATA13", "DCPLB_DATA14", "DCPLB_DATA15", + [mmr_idx (dtest_command)] = "DTEST_COMMAND", + [mmr_idx (dtest_data[0])] = "DTEST_DATA0", "DTEST_DATA1", + [mmr_idx (imem_control)] = "IMEM_CONTROL", "ICPLB_FAULT_STATUS", "ICPLB_FAULT_ADDR", + [mmr_idx (icplb_addr[0])] = "ICPLB_ADDR0", + "ICPLB_ADDR1", "ICPLB_ADDR2", "ICPLB_ADDR3", "ICPLB_ADDR4", "ICPLB_ADDR5", + "ICPLB_ADDR6", "ICPLB_ADDR7", "ICPLB_ADDR8", "ICPLB_ADDR9", "ICPLB_ADDR10", + "ICPLB_ADDR11", "ICPLB_ADDR12", "ICPLB_ADDR13", "ICPLB_ADDR14", "ICPLB_ADDR15", + [mmr_idx (icplb_data[0])] = "ICPLB_DATA0", + "ICPLB_DATA1", "ICPLB_DATA2", "ICPLB_DATA3", "ICPLB_DATA4", "ICPLB_DATA5", + "ICPLB_DATA6", "ICPLB_DATA7", "ICPLB_DATA8", "ICPLB_DATA9", "ICPLB_DATA10", + "ICPLB_DATA11", "ICPLB_DATA12", "ICPLB_DATA13", "ICPLB_DATA14", "ICPLB_DATA15", + [mmr_idx (itest_command)] = "ITEST_COMMAND", + [mmr_idx (itest_data[0])] = "ITEST_DATA0", "ITEST_DATA1", +}; + +static void bfin_mmu_io_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + BfinMMUState *s = opaque; + + HW_TRACE_WRITE(); +} + +static uint64_t bfin_mmu_io_read(void *opaque, hwaddr addr, unsigned size) +{ + BfinMMUState *s = opaque; + + HW_TRACE_READ(); + + return 0; +} + +static const MemoryRegionOps bfin_mmu_io_ops = { + .read = bfin_mmu_io_read, + .write = bfin_mmu_io_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static int bfin_mmu_init(SysBusDevice *sbd) +{ + DeviceState *dev = DEVICE(sbd); + BfinMMUState *s = BFIN_MMU(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &bfin_mmu_io_ops, s, "mmu", mmr_size()); + sysbus_init_mmio(sbd, &s->iomem); + + return 0; +} + +static void bfin_mmu_class_init(ObjectClass *klass, void *data) +{ +// DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = bfin_mmu_init; +} + +static TypeInfo bfin_mmu_info = { + .name = "bfin_mmu", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BfinMMUState), + .class_init = bfin_mmu_class_init, +}; + +static void bfin_mmu_register_types(void) +{ + type_register_static(&bfin_mmu_info); +} + +type_init(bfin_mmu_register_types) diff --git a/hw/bfin/bfin_pll.c b/hw/bfin/bfin_pll.c new file mode 100644 index 0000000000000..56f4fb9dcab31 --- /dev/null +++ b/hw/bfin/bfin_pll.c @@ -0,0 +1,132 @@ +/* + * Blackfin Phase Lock Loop (PLL) model. + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "trace.h" +#include "bfin_devices.h" + +#define TYPE_BFIN_PLL "bfin_pll" +#define BFIN_PLL(obj) OBJECT_CHECK(BfinPLLState, (obj), TYPE_BFIN_PLL) + +typedef struct BfinPLLState { + SysBusDevice parent_obj; + MemoryRegion iomem; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(pll_ctl); + bu16 BFIN_MMR_16(pll_div); + bu16 BFIN_MMR_16(vr_ctl); + bu16 BFIN_MMR_16(pll_stat); + bu16 BFIN_MMR_16(pll_lockcnt); + + /* XXX: Not really the best place for this ... */ + bu32 chipid; +} BfinPLLState; +#define BfinMMRState BfinPLLState +#define mmr_base() offsetof(BfinMMRState, pll_ctl) + +static const char * const mmr_names[] = +{ + "PLL_CTL", "PLL_DIV", "VR_CTL", "PLL_STAT", "PLL_LOCKCNT", "CHIPID", +}; + +static void bfin_pll_io_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + BfinPLLState *s = opaque; + bu16 *valuep = (void *)((uintptr_t)s + mmr_base() + addr); + + HW_TRACE_WRITE(); + + switch (addr) { + case mmr_offset(pll_stat): + case mmr_offset(chipid): + /* Discard writes. */ + break; + + default: + *valuep = value; + break; + } +} + +static uint64_t bfin_pll_io_read(void *opaque, hwaddr addr, unsigned size) +{ + BfinPLLState *s = opaque; + bu16 *valuep = (void *)((uintptr_t)s + mmr_base() + addr); + + HW_TRACE_READ(); + + switch (addr) { + case mmr_offset(chipid): + return s->chipid; + + default: + return *valuep; + } +} + +static const MemoryRegionOps bfin_pll_io_ops = { + .read = bfin_pll_io_read, + .write = bfin_pll_io_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 2, + .max_access_size = 4, + }, +}; + +static void pll_reset(DeviceState *d) +{ + BfinPLLState *s = BFIN_PLL(d); + + /* XXX: Depends on cpu/board. */ + s->pll_ctl = 0x1400; + s->pll_div = 0x0005; + s->vr_ctl = 0x40DB; + s->pll_stat = 0x00A2; + s->pll_lockcnt = 0x0200; + s->chipid = 0x1234; +} + +static int bfin_pll_init(SysBusDevice *sbd) +{ + DeviceState *dev = DEVICE(sbd); + BfinPLLState *s = BFIN_PLL(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &bfin_pll_io_ops, s, "pll", mmr_size()); + sysbus_init_mmio(sbd, &s->iomem); + + return 0; +} + +static void bfin_pll_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = bfin_pll_init; + dc->reset = pll_reset; +} + +static TypeInfo bfin_pll_info = { + .name = "bfin_pll", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BfinPLLState), + .class_init = bfin_pll_class_init, +}; + +static void bfin_pll_register_types(void) +{ + type_register_static(&bfin_pll_info); +} + +type_init(bfin_pll_register_types) diff --git a/hw/bfin/bfin_sic.c b/hw/bfin/bfin_sic.c new file mode 100644 index 0000000000000..7e43c61523beb --- /dev/null +++ b/hw/bfin/bfin_sic.c @@ -0,0 +1,126 @@ +/* + * Blackfin System Interrupt Controller (SIC) model. + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "trace.h" +#include "bfin_devices.h" + +#define TYPE_BFIN_SIC "bfin_sic" +#define BFIN_SIC(obj) OBJECT_CHECK(BfinSICState, (obj), TYPE_BFIN_SIC) + +typedef struct BfinSICState { + SysBusDevice parent_obj; + MemoryRegion iomem; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(swrst); + bu16 BFIN_MMR_16(syscr); + bu16 BFIN_MMR_16(rvect); /* XXX: BF59x has a 32bit AUX_REVID here. */ + union { + struct { + bu32 imask0; + bu32 iar0, iar1, iar2, iar3; + bu32 isr0, iwr0; + bu32 _pad0[9]; + bu32 imask1; + bu32 iar4, iar5, iar6, iar7; + bu32 isr1, iwr1; + } bf52x; + struct { + bu32 imask; + bu32 iar0, iar1, iar2, iar3; + bu32 isr, iwr; + } bf537; + struct { + bu32 imask0, imask1, imask2; + bu32 isr0, isr1, isr2; + bu32 iwr0, iwr1, iwr2; + bu32 iar0, iar1, iar2, iar3; + bu32 iar4, iar5, iar6, iar7; + bu32 iar8, iar9, iar10, iar11; + } bf54x; + struct { + bu32 imask0, imask1; + bu32 iar0, iar1, iar2, iar3; + bu32 iar4, iar5, iar6, iar7; + bu32 isr0, isr1; + bu32 iwr0, iwr1; + } bf561; + }; +} BfinSICState; +#define BfinMMRState BfinSICState +#define mmr_base() offsetof(BfinMMRState, swrst) + +static const char * const mmr_names[] = +{ + "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK", "SIC_IAR0", "SIC_IAR1", + "SIC_IAR2", "SIC_IAR3", "SIC_ISR", "SIC_IWR", +}; + +static void bfin_sic_io_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + BfinSICState *s = opaque; + + HW_TRACE_WRITE(); +} + +static uint64_t bfin_sic_io_read(void *opaque, hwaddr addr, unsigned size) +{ + BfinSICState *s = opaque; + + HW_TRACE_READ(); + + return 0; +} + +static const MemoryRegionOps bfin_sic_io_ops = { + .read = bfin_sic_io_read, + .write = bfin_sic_io_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 2, + .max_access_size = 4, + }, +}; + +static int bfin_sic_init(SysBusDevice *sbd) +{ + DeviceState *dev = DEVICE(sbd); + BfinSICState *s = BFIN_SIC(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &bfin_sic_io_ops, s, "sic", mmr_size()); + sysbus_init_mmio(sbd, &s->iomem); + + return 0; +} + +static void bfin_sic_class_init(ObjectClass *klass, void *data) +{ +// DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = bfin_sic_init; +} + +static TypeInfo bfin_sic_info = { + .name = "bfin_sic", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BfinSICState), + .class_init = bfin_sic_class_init, +}; + +static void bfin_sic_register_types(void) +{ + type_register_static(&bfin_sic_info); +} + +type_init(bfin_sic_register_types) diff --git a/hw/bfin/bfin_trace.c b/hw/bfin/bfin_trace.c new file mode 100644 index 0000000000000..1d1e99e07748f --- /dev/null +++ b/hw/bfin/bfin_trace.c @@ -0,0 +1,150 @@ +/* + * Blackfin Trace (TBUF) model. + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "trace.h" +#include "bfin_devices.h" + +#define TYPE_BFIN_TRACE "bfin_trace" +#define BFIN_TRACE(obj) OBJECT_CHECK(BfinTraceState, (obj), TYPE_BFIN_TRACE) + +/* Note: The circular buffering here might look a little buggy wrt mid-reads + and consuming the top entry, but this is simulating hardware behavior. + The hardware is simple, dumb, and fast. Don't write dumb Blackfin + software and you won't have a problem. */ + +/* The hardware is limited to 16 entries and defines TBUFCTL. Let's extend it ;). */ +#ifndef SIM_BFIN_TRACE_DEPTH +#define SIM_BFIN_TRACE_DEPTH 6 +#endif +#define SIM_BFIN_TRACE_LEN (1 << SIM_BFIN_TRACE_DEPTH) +#define SIM_BFIN_TRACE_LEN_MASK (SIM_BFIN_TRACE_LEN - 1) + +struct bfin_trace_entry { + bu32 src, dst; +}; + +typedef struct BfinTraceState { + SysBusDevice parent_obj; + MemoryRegion iomem; + + struct bfin_trace_entry buffer[SIM_BFIN_TRACE_LEN]; + int top, bottom; + bool mid; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 tbufctl, tbufstat; + char _pad[0x100 - 0x8]; + bu32 tbuf; +} BfinTraceState; +#define BfinMMRState BfinTraceState +#define mmr_base() offsetof(BfinMMRState, tbufctl) + +static const char * const mmr_names[] = +{ + "TBUFCTL", "TBUFSTAT", [mmr_offset (tbuf) / 4] = "TBUF", +}; + +/* Ugh, circular buffers. */ +#define TBUF_LEN(t) ((t)->top - (t)->bottom) +#define TBUF_IDX(i) ((i) & SIM_BFIN_TRACE_LEN_MASK) +/* TOP is the next slot to fill. */ +#define TBUF_TOP(t) (&(t)->buffer[TBUF_IDX((t)->top)]) +/* LAST is the latest valid slot. */ +#define TBUF_LAST(t) (&(t)->buffer[TBUF_IDX((t)->top - 1)]) +/* LAST_LAST is the second-to-last valid slot. */ +#define TBUF_LAST_LAST(t) (&(t)->buffer[TBUF_IDX((t)->top - 2)]) + +static void bfin_trace_io_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + BfinTraceState *s = opaque; + + HW_TRACE_WRITE(); + + switch (addr) { + case mmr_offset(tbufctl): + s->tbufctl = value; + break; + case mmr_offset(tbufstat): + case mmr_offset(tbuf): + /* Discard writes to these. */ + break; + default: + /* TODO: Throw an invalid mmr exception. */ + break; + } +} + +static uint64_t bfin_trace_io_read(void *opaque, hwaddr addr, unsigned size) +{ + BfinTraceState *s = opaque; + + HW_TRACE_READ(); + + switch (addr) { + case mmr_offset(tbufctl): + return s->tbufctl; + case mmr_offset(tbufstat): + /* Hardware is limited to 16 entries, so to stay compatible with + software, limit the value to 16. For software algorithms that + keep reading while (TBUFSTAT != 0), they'll get all of it. */ + return MIN(TBUF_LEN(s), 16); + case mmr_offset(tbuf): + /* XXX: Implement this. */ + return 0; + default: + /* TODO: Throw an invalid mmr exception. */ + return 0; + } +} + +static const MemoryRegionOps bfin_trace_io_ops = { + .read = bfin_trace_io_read, + .write = bfin_trace_io_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static int bfin_trace_init(SysBusDevice *sbd) +{ + DeviceState *dev = DEVICE(sbd); + BfinTraceState *s = BFIN_TRACE(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &bfin_trace_io_ops, s, "trace", mmr_size()); + sysbus_init_mmio(sbd, &s->iomem); + + return 0; +} + +static void bfin_trace_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = bfin_trace_init; +} + +static TypeInfo bfin_trace_info = { + .name = "bfin_trace", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BfinTraceState), + .class_init = bfin_trace_class_init, +}; + +static void bfin_trace_register_types(void) +{ + type_register_static(&bfin_trace_info); +} + +type_init(bfin_trace_register_types) diff --git a/hw/bfin/bfin_uart.c b/hw/bfin/bfin_uart.c new file mode 100644 index 0000000000000..b4a0c7499ba4b --- /dev/null +++ b/hw/bfin/bfin_uart.c @@ -0,0 +1,305 @@ +/* + * Blackfin Universal Asynchronous Receiver/Transmitter (UART) model. + * For "old style" UARTs on BF53x/etc... parts. + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "sysemu/char.h" +#include "trace.h" +#include "bfin_uart.h" +#include "bfin_devices.h" + +#define TYPE_BFIN_UART "bfin_uart" +#define BFIN_UART(obj) OBJECT_CHECK(BfinUARTState, (obj), TYPE_BFIN_UART) + +typedef struct BfinUARTState { + SysBusDevice parent_obj; + CharDriverState *chr; + + MemoryRegion iomem; + + unsigned char saved_byte; + int saved_count; + + /* This is aliased to DLH. */ + bu16 ier; + /* These are aliased to DLL. */ + bu16 thr, rbr; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(dll); + bu16 BFIN_MMR_16(dlh); + bu16 BFIN_MMR_16(iir); + bu16 BFIN_MMR_16(lcr); + bu16 BFIN_MMR_16(mcr); + bu16 BFIN_MMR_16(lsr); + bu16 BFIN_MMR_16(msr); + bu16 BFIN_MMR_16(scr); + bu16 _pad0[2]; + bu16 BFIN_MMR_16(gctl); +} BfinUARTState; +#define BfinMMRState BfinUARTState +#define mmr_base() offsetof(BfinMMRState, dll) + +static const char * const mmr_names[] = +{ + "UART_RBR/UART_THR", "UART_IER", "UART_IIR", "UART_LCR", "UART_MCR", + "UART_LSR", "UART_MSR", "UART_SCR", "", "UART_GCTL", +}; + +#undef mmr_name +static const char *mmr_name(BfinUARTState *uart, bu32 idx) +{ + if (uart->lcr & DLAB) + if (idx < 2) + return idx == 0 ? "UART_DLL" : "UART_DLH"; + return mmr_names[idx]; +} +#define mmr_name(off) mmr_name(s, (off) / 4) + +static bu16 +bfin_uart_write_byte(BfinUARTState *s, bu16 thr, bu16 mcr) +{ + unsigned char ch = thr; + + if (mcr & LOOP_ENA) { + /* XXX: This probably doesn't work exactly right with + external FIFOs ... */ + s->saved_byte = thr; + s->saved_count = 1; + } + + qemu_chr_fe_write(s->chr, &ch, 1); + + return thr; +} + +static void bfin_uart_io_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + BfinUARTState *s = opaque; + bu16 *valuep = (void *)((uintptr_t)s + mmr_base() + addr); + + HW_TRACE_WRITE(); + + switch (addr) { + case mmr_offset(dll): + if (s->lcr & DLAB) { + s->dll = value; + } else { + s->thr = bfin_uart_write_byte(s, value, s->mcr); + +/* + if (uart->ier & ETBEI) { + hw_port_event (me, DV_PORT_TX, 1); + } +*/ + } + break; + case mmr_offset(dlh): + if (s->lcr & DLAB) + s->dlh = value; + else + s->ier = value; + break; + case mmr_offset(iir): + case mmr_offset(lsr): + /* XXX: Writes are ignored ? */ + break; + case mmr_offset(lcr): + s->lcr = value; break; + case mmr_offset(mcr): + case mmr_offset(scr): + case mmr_offset(gctl): + *valuep = value; + break; + } +} + +static bu16 +bfin_uart_get_next_byte(BfinUARTState *s, bu16 rbr, bu16 mcr, bool *fresh) +{ + bool _fresh; + + /* NB: The "uart" here may only use interal state. */ + + if (!fresh) { + fresh = &_fresh; + } + + *fresh = false; + + if (s->saved_count > 0) { + *fresh = true; + rbr = s->saved_byte; + --s->saved_count; + } + + /* RX is disconnected, so only return local data. */ + if (!(mcr & LOOP_ENA)) { + qemu_chr_accept_input(s->chr); + } + + return rbr; +} + +static uint64_t bfin_uart_io_read(void *opaque, hwaddr addr, unsigned size) +{ + BfinUARTState *s = opaque; + bu16 *valuep = (void *)((uintptr_t)s + mmr_base() + addr); + + HW_TRACE_READ(); + + switch (addr) { + case mmr_offset(dll): + if (s->lcr & DLAB) { + return s->dll; + } else { + s->rbr = bfin_uart_get_next_byte(s, s->rbr, s->mcr, NULL); + return s->rbr; + } + case mmr_offset(dlh): + if (s->lcr & DLAB) { + return s->dlh; + } else { + return s->ier; + } + case mmr_offset(lsr): { + uint64_t ret; + /* XXX: Reads are destructive on most parts, but not all ... */ + s->lsr |= TEMT | THRE | (s->saved_count > 0 ? DR : 0); // bfin_uart_get_status (me); + ret = s->lsr; + s->lsr = 0; + return ret; + } + case mmr_offset(iir): + /* XXX: Reads are destructive ... */ + case mmr_offset(lcr): + case mmr_offset(mcr): + case mmr_offset(scr): + case mmr_offset(gctl): + return *valuep; + } + + return 0; +} + +static const MemoryRegionOps bfin_uart_io_ops = { + .read = bfin_uart_io_read, + .write = bfin_uart_io_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 2, + .max_access_size = 2, + }, +}; + +static Property bfin_uart_properties[] = { + DEFINE_PROP_CHR("chardev", BfinUARTState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void uart_rx(void *opaque, const uint8_t *buf, int size) +{ + BfinUARTState *s = opaque; + + if (s->lsr & DR) { + s->lsr |= OE; + } + + s->lsr |= DR; + s->saved_byte = *buf; + s->saved_count = 1; + +// uart_update_irq(s); +} + +static int uart_can_rx(void *opaque) +{ + BfinUARTState *s = opaque; + + return !(s->lsr & DR); +} + +static void uart_event(void *opaque, int event) +{ +} + +static void uart_reset(DeviceState *d) +{ + BfinUARTState *s = BFIN_UART(d); + + s->ier = 0; + s->thr = 0; + s->rbr = 0; + s->dll = 0x0001; + s->dlh = 0; + s->iir = 0x0001; + s->lcr = 0; + s->mcr = 0; + s->lsr = 0x0060; + s->msr = 0; + s->scr = 0; + s->gctl = 0; +} + +static void bfin_uart_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + BfinUARTState *s = BFIN_UART(obj); + + memory_region_init_io(&s->iomem, OBJECT(s), &bfin_uart_io_ops, s, "uart", mmr_size()); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void bfin_uart_realize(DeviceState *dev, Error **errp) +{ + BfinUARTState *s = BFIN_UART(dev); + + if (s->chr) { + qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); + } +} + +static const VMStateDescription vmstate_bfin_uart = { + .name = "bfin-uart", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { +// VMSTATE_UINT32_ARRAY(regs, BfinUartState, R_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static void bfin_uart_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = uart_reset; + dc->vmsd = &vmstate_bfin_uart; + dc->props = bfin_uart_properties; + dc->realize = bfin_uart_realize; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); +} + +static TypeInfo bfin_uart_info = { + .name = TYPE_BFIN_UART, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BfinUARTState), + .instance_init = bfin_uart_init, + .class_init = bfin_uart_class_init, +}; + +static void bfin_uart_register_types(void) +{ + type_register_static(&bfin_uart_info); +} + +type_init(bfin_uart_register_types) diff --git a/hw/bfin/bfin_uart.h b/hw/bfin/bfin_uart.h new file mode 100644 index 0000000000000..0d034a9830248 --- /dev/null +++ b/hw/bfin/bfin_uart.h @@ -0,0 +1,42 @@ +/* + * Blackfin Universal Asynchronous Receiver/Transmitter (UART) model. + * For "old style" UARTs on BF53x/etc... parts. + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#ifndef DV_BFIN_UART_H +#define DV_BFIN_UART_H + +/* UART_LCR */ +#define DLAB (1 << 7) + +/* UART_LSR */ +#define TFI (1 << 7) +#define TEMT (1 << 6) +#define THRE (1 << 5) +#define BI (1 << 4) +#define FE (1 << 3) +#define PE (1 << 2) +#define OE (1 << 1) +#define DR (1 << 0) + +/* UART_IER */ +#define ERBFI (1 << 0) +#define ETBEI (1 << 1) +#define ELSI (1 << 2) + +/* UART_MCR */ +#define XOFF (1 << 0) +#define MRTS (1 << 1) +#define RFIT (1 << 2) +#define RFRT (1 << 3) +#define LOOP_ENA (1 << 4) +#define FCPOL (1 << 5) +#define ARTS (1 << 6) +#define ACTS (1 << 7) + +#endif diff --git a/include/disas/bfd.h b/include/disas/bfd.h index 8a3488c2c5155..7a2d5b712c876 100644 --- a/include/disas/bfd.h +++ b/include/disas/bfd.h @@ -213,6 +213,8 @@ enum bfd_architecture #define bfd_mach_m32r 0 /* backwards compatibility */ bfd_arch_mn10200, /* Matsushita MN10200 */ bfd_arch_mn10300, /* Matsushita MN10300 */ + bfd_arch_bfin, /* ADI Blackfin */ +#define bfd_mach_bfin 1 bfd_arch_cris, /* Axis CRIS */ #define bfd_mach_cris_v0_v10 255 #define bfd_mach_cris_v32 32 @@ -388,6 +390,7 @@ int print_insn_arm_a64 (bfd_vma, disassemble_info*); int print_insn_alpha (bfd_vma, disassemble_info*); disassembler_ftype arc_get_disassembler (int, int); int print_insn_arm (bfd_vma, disassemble_info*); +int print_insn_bfin (bfd_vma, disassemble_info*); int print_insn_sparc (bfd_vma, disassemble_info*); int print_insn_big_a29k (bfd_vma, disassemble_info*); int print_insn_little_a29k (bfd_vma, disassemble_info*); diff --git a/include/elf.h b/include/elf.h index 1c2975dc82be6..887cb03a9c680 100644 --- a/include/elf.h +++ b/include/elf.h @@ -106,6 +106,7 @@ typedef int64_t Elf64_Sxword; #define EM_H8_300H 47 /* Hitachi H8/300H */ #define EM_H8S 48 /* Hitachi H8S */ +#define EM_BLACKFIN 106 /* Analog Devices Blackfin */ #define EM_LATTICEMICO32 138 /* LatticeMico32 */ #define EM_OPENRISC 92 /* OpenCores OpenRISC */ @@ -968,6 +969,11 @@ typedef struct { #define EF_ALPHA_32BIT 1 /* All addresses are below 2GB */ +/* Blackfin specific definitions. */ + +#define EF_BFIN_PIC 0x00000001 /* -fpic */ +#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */ + /* HPPA specific definitions. */ /* Legal values for e_flags field of Elf32_Ehdr. */ diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 46187bbc7eb45..8687e90ab2aab 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -106,6 +106,96 @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) } #endif +/** + * clz8 - count leading zeros in a 8-bit value. + * @val: The value to search + * + * Returns 8 if the value is zero. Note that the GCC builtin is + * undefined if the value is zero. + */ +static inline int clz8(uint8_t val) +{ + /* Binary search for the leading one bit. */ + int cnt = 0; + + if (!(val & 0xF0U)) { + cnt += 4; + val <<= 4; + } + if (!(val & 0xC0U)) { + cnt += 2; + val <<= 2; + } + if (!(val & 0x80U)) { + cnt++; + val <<= 1; + } + if (!(val & 0x80U)) { + cnt++; + } + return cnt; +} + +/** + * clo8 - count leading ones in a 8-bit value. + * @val: The value to search + * + * Returns 8 if the value is -1. + */ +static inline int clo8(uint8_t val) +{ + return clz8(~val); +} + +/** + * clz16 - count leading zeros in a 16-bit value. + * @val: The value to search + * + * Returns 16 if the value is zero. Note that the GCC builtin is + * undefined if the value is zero. + */ +static inline int clz16(uint16_t val) +{ +#if QEMU_GNUC_PREREQ(3, 4) && defined(__i386__) + return val ? __builtin_clzs(val) : 16; +#else + /* Binary search for the leading one bit. */ + int cnt = 0; + + if (!(val & 0xFF00U)) { + cnt += 8; + val <<= 8; + } + if (!(val & 0xF000U)) { + cnt += 4; + val <<= 4; + } + if (!(val & 0xC000U)) { + cnt += 2; + val <<= 2; + } + if (!(val & 0x8000U)) { + cnt++; + val <<= 1; + } + if (!(val & 0x8000U)) { + cnt++; + } + return cnt; +#endif +} + +/** + * clo16 - count leading ones in a 16-bit value. + * @val: The value to search + * + * Returns 16 if the value is -1. + */ +static inline int clo16(uint16_t val) +{ + return clz16(~val); +} + /** * clz32 - count leading zeros in a 32-bit value. * @val: The value to search diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 9e9fa6154642e..8c761cb9d5184 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -85,6 +85,10 @@ extern int daemon(int, int); #include #include +#ifdef __linux__ +#include +#endif + #ifdef __OpenBSD__ #include #endif diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index d690dfabdfb54..35c32bd8ec58c 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -23,6 +23,7 @@ enum { QEMU_ARCH_UNICORE32 = (1 << 14), QEMU_ARCH_MOXIE = (1 << 15), QEMU_ARCH_TRICORE = (1 << 16), + QEMU_ARCH_BFIN = (1 << 17), }; extern const uint32_t arch_type; diff --git a/linux-user/bfin/syscall_nr.h b/linux-user/bfin/syscall_nr.h new file mode 100644 index 0000000000000..d4567956c54fe --- /dev/null +++ b/linux-user/bfin/syscall_nr.h @@ -0,0 +1,407 @@ +/* + * This file contains the system call numbers. + */ +#define TARGET_NR_restart_syscall 0 +#define TARGET_NR_exit 1 +#define TARGET_NR_fork 2 +#define TARGET_NR_read 3 +#define TARGET_NR_write 4 +#define TARGET_NR_open 5 +#define TARGET_NR_close 6 + /* 7 TARGET_NR_waitpid obsolete */ +#define TARGET_NR_creat 8 +#define TARGET_NR_link 9 +#define TARGET_NR_unlink 10 +#define TARGET_NR_execve 11 +#define TARGET_NR_chdir 12 +#define TARGET_NR_time 13 +#define TARGET_NR_mknod 14 +#define TARGET_NR_chmod 15 +#define TARGET_NR_chown 16 + /* 17 TARGET_NR_break obsolete */ + /* 18 TARGET_NR_oldstat obsolete */ +#define TARGET_NR_lseek 19 +#define TARGET_NR_getpid 20 +#define TARGET_NR_mount 21 + /* 22 TARGET_NR_umount obsolete */ +#define TARGET_NR_setuid 23 +#define TARGET_NR_getuid 24 +#define TARGET_NR_stime 25 +#define TARGET_NR_ptrace 26 +#define TARGET_NR_alarm 27 + /* 28 TARGET_NR_oldfstat obsolete */ +#define TARGET_NR_pause 29 + /* 30 TARGET_NR_utime obsolete */ + /* 31 TARGET_NR_stty obsolete */ + /* 32 TARGET_NR_gtty obsolete */ +#define TARGET_NR_access 33 +#define TARGET_NR_nice 34 + /* 35 TARGET_NR_ftime obsolete */ +#define TARGET_NR_sync 36 +#define TARGET_NR_kill 37 +#define TARGET_NR_rename 38 +#define TARGET_NR_mkdir 39 +#define TARGET_NR_rmdir 40 +#define TARGET_NR_dup 41 +#define TARGET_NR_pipe 42 +#define TARGET_NR_times 43 + /* 44 TARGET_NR_prof obsolete */ +#define TARGET_NR_brk 45 +#define TARGET_NR_setgid 46 +#define TARGET_NR_getgid 47 + /* 48 TARGET_NR_signal obsolete */ +#define TARGET_NR_geteuid 49 +#define TARGET_NR_getegid 50 +#define TARGET_NR_acct 51 +#define TARGET_NR_umount2 52 + /* 53 TARGET_NR_lock obsolete */ +#define TARGET_NR_ioctl 54 +#define TARGET_NR_fcntl 55 + /* 56 TARGET_NR_mpx obsolete */ +#define TARGET_NR_setpgid 57 + /* 58 TARGET_NR_ulimit obsolete */ + /* 59 TARGET_NR_oldolduname obsolete */ +#define TARGET_NR_umask 60 +#define TARGET_NR_chroot 61 +#define TARGET_NR_ustat 62 +#define TARGET_NR_dup2 63 +#define TARGET_NR_getppid 64 +#define TARGET_NR_getpgrp 65 +#define TARGET_NR_setsid 66 + /* 67 TARGET_NR_sigaction obsolete */ +#define TARGET_NR_sgetmask 68 +#define TARGET_NR_ssetmask 69 +#define TARGET_NR_setreuid 70 +#define TARGET_NR_setregid 71 + /* 72 TARGET_NR_sigsuspend obsolete */ + /* 73 TARGET_NR_sigpending obsolete */ +#define TARGET_NR_sethostname 74 +#define TARGET_NR_setrlimit 75 + /* 76 TARGET_NR_old_getrlimit obsolete */ +#define TARGET_NR_getrusage 77 +#define TARGET_NR_gettimeofday 78 +#define TARGET_NR_settimeofday 79 +#define TARGET_NR_getgroups 80 +#define TARGET_NR_setgroups 81 + /* 82 TARGET_NR_select obsolete */ +#define TARGET_NR_symlink 83 + /* 84 TARGET_NR_oldlstat obsolete */ +#define TARGET_NR_readlink 85 + /* 86 TARGET_NR_uselib obsolete */ + /* 87 TARGET_NR_swapon obsolete */ +#define TARGET_NR_reboot 88 + /* 89 TARGET_NR_readdir obsolete */ + /* 90 TARGET_NR_mmap obsolete */ +#define TARGET_NR_munmap 91 +#define TARGET_NR_truncate 92 +#define TARGET_NR_ftruncate 93 +#define TARGET_NR_fchmod 94 +#define TARGET_NR_fchown 95 +#define TARGET_NR_getpriority 96 +#define TARGET_NR_setpriority 97 + /* 98 TARGET_NR_profil obsolete */ +#define TARGET_NR_statfs 99 +#define TARGET_NR_fstatfs 100 + /* 101 TARGET_NR_ioperm */ + /* 102 TARGET_NR_socketcall obsolete */ +#define TARGET_NR_syslog 103 +#define TARGET_NR_setitimer 104 +#define TARGET_NR_getitimer 105 +#define TARGET_NR_stat 106 +#define TARGET_NR_lstat 107 +#define TARGET_NR_fstat 108 + /* 109 TARGET_NR_olduname obsolete */ + /* 110 TARGET_NR_iopl obsolete */ +#define TARGET_NR_vhangup 111 + /* 112 TARGET_NR_idle obsolete */ + /* 113 TARGET_NR_vm86old */ +#define TARGET_NR_wait4 114 + /* 115 TARGET_NR_swapoff obsolete */ +#define TARGET_NR_sysinfo 116 + /* 117 TARGET_NR_ipc oboslete */ +#define TARGET_NR_fsync 118 + /* 119 TARGET_NR_sigreturn obsolete */ +#define TARGET_NR_clone 120 +#define TARGET_NR_setdomainname 121 +#define TARGET_NR_uname 122 + /* 123 TARGET_NR_modify_ldt obsolete */ +#define TARGET_NR_adjtimex 124 +#define TARGET_NR_mprotect 125 + /* 126 TARGET_NR_sigprocmask obsolete */ + /* 127 TARGET_NR_create_module obsolete */ +#define TARGET_NR_init_module 128 +#define TARGET_NR_delete_module 129 + /* 130 TARGET_NR_get_kernel_syms obsolete */ +#define TARGET_NR_quotactl 131 +#define TARGET_NR_getpgid 132 +#define TARGET_NR_fchdir 133 +#define TARGET_NR_bdflush 134 + /* 135 was sysfs */ +#define TARGET_NR_personality 136 + /* 137 TARGET_NR_afs_syscall */ +#define TARGET_NR_setfsuid 138 +#define TARGET_NR_setfsgid 139 +#define TARGET_NR__llseek 140 +#define TARGET_NR_getdents 141 + /* 142 TARGET_NR__newselect obsolete */ +#define TARGET_NR_flock 143 + /* 144 TARGET_NR_msync obsolete */ +#define TARGET_NR_readv 145 +#define TARGET_NR_writev 146 +#define TARGET_NR_getsid 147 +#define TARGET_NR_fdatasync 148 +#define TARGET_NR__sysctl 149 + /* 150 TARGET_NR_mlock */ + /* 151 TARGET_NR_munlock */ + /* 152 TARGET_NR_mlockall */ + /* 153 TARGET_NR_munlockall */ +#define TARGET_NR_sched_setparam 154 +#define TARGET_NR_sched_getparam 155 +#define TARGET_NR_sched_setscheduler 156 +#define TARGET_NR_sched_getscheduler 157 +#define TARGET_NR_sched_yield 158 +#define TARGET_NR_sched_get_priority_max 159 +#define TARGET_NR_sched_get_priority_min 160 +#define TARGET_NR_sched_rr_get_interval 161 +#define TARGET_NR_nanosleep 162 +#define TARGET_NR_mremap 163 +#define TARGET_NR_setresuid 164 +#define TARGET_NR_getresuid 165 + /* 166 TARGET_NR_vm86 */ + /* 167 TARGET_NR_query_module */ + /* 168 TARGET_NR_poll */ +#define TARGET_NR_nfsservctl 169 +#define TARGET_NR_setresgid 170 +#define TARGET_NR_getresgid 171 +#define TARGET_NR_prctl 172 +#define TARGET_NR_rt_sigreturn 173 +#define TARGET_NR_rt_sigaction 174 +#define TARGET_NR_rt_sigprocmask 175 +#define TARGET_NR_rt_sigpending 176 +#define TARGET_NR_rt_sigtimedwait 177 +#define TARGET_NR_rt_sigqueueinfo 178 +#define TARGET_NR_rt_sigsuspend 179 +#define TARGET_NR_pread 180 +#define TARGET_NR_pwrite 181 +#define TARGET_NR_lchown 182 +#define TARGET_NR_getcwd 183 +#define TARGET_NR_capget 184 +#define TARGET_NR_capset 185 +#define TARGET_NR_sigaltstack 186 +#define TARGET_NR_sendfile 187 + /* 188 TARGET_NR_getpmsg */ + /* 189 TARGET_NR_putpmsg */ +#define TARGET_NR_vfork 190 +#define TARGET_NR_getrlimit 191 +#define TARGET_NR_mmap2 192 /* xxx: this is mmap2 !? */ +#define TARGET_NR_truncate64 193 +#define TARGET_NR_ftruncate64 194 +#define TARGET_NR_stat64 195 +#define TARGET_NR_lstat64 196 +#define TARGET_NR_fstat64 197 +#define TARGET_NR_chown32 198 +#define TARGET_NR_getuid32 199 +#define TARGET_NR_getgid32 200 +#define TARGET_NR_geteuid32 201 +#define TARGET_NR_getegid32 202 +#define TARGET_NR_setreuid32 203 +#define TARGET_NR_setregid32 204 +#define TARGET_NR_getgroups32 205 +#define TARGET_NR_setgroups32 206 +#define TARGET_NR_fchown32 207 +#define TARGET_NR_setresuid32 208 +#define TARGET_NR_getresuid32 209 +#define TARGET_NR_setresgid32 210 +#define TARGET_NR_getresgid32 211 +#define TARGET_NR_lchown32 212 +#define TARGET_NR_setuid32 213 +#define TARGET_NR_setgid32 214 +#define TARGET_NR_setfsuid32 215 +#define TARGET_NR_setfsgid32 216 +#define TARGET_NR_pivot_root 217 + /* 218 TARGET_NR_mincore */ + /* 219 TARGET_NR_madvise */ +#define TARGET_NR_getdents64 220 +#define TARGET_NR_fcntl64 221 + /* 222 reserved for TUX */ + /* 223 reserved for TUX */ +#define TARGET_NR_gettid 224 +#define TARGET_NR_readahead 225 +#define TARGET_NR_setxattr 226 +#define TARGET_NR_lsetxattr 227 +#define TARGET_NR_fsetxattr 228 +#define TARGET_NR_getxattr 229 +#define TARGET_NR_lgetxattr 230 +#define TARGET_NR_fgetxattr 231 +#define TARGET_NR_listxattr 232 +#define TARGET_NR_llistxattr 233 +#define TARGET_NR_flistxattr 234 +#define TARGET_NR_removexattr 235 +#define TARGET_NR_lremovexattr 236 +#define TARGET_NR_fremovexattr 237 +#define TARGET_NR_tkill 238 +#define TARGET_NR_sendfile64 239 +#define TARGET_NR_futex 240 +#define TARGET_NR_sched_setaffinity 241 +#define TARGET_NR_sched_getaffinity 242 + /* 243 TARGET_NR_set_thread_area */ + /* 244 TARGET_NR_get_thread_area */ +#define TARGET_NR_io_setup 245 +#define TARGET_NR_io_destroy 246 +#define TARGET_NR_io_getevents 247 +#define TARGET_NR_io_submit 248 +#define TARGET_NR_io_cancel 249 + /* 250 TARGET_NR_alloc_hugepages */ + /* 251 TARGET_NR_free_hugepages */ +#define TARGET_NR_exit_group 252 +#define TARGET_NR_lookup_dcookie 253 +#define TARGET_NR_bfin_spinlock 254 + +#define TARGET_NR_epoll_create 255 +#define TARGET_NR_epoll_ctl 256 +#define TARGET_NR_epoll_wait 257 + /* 258 TARGET_NR_remap_file_pages */ +#define TARGET_NR_set_tid_address 259 +#define TARGET_NR_timer_create 260 +#define TARGET_NR_timer_settime 261 +#define TARGET_NR_timer_gettime 262 +#define TARGET_NR_timer_getoverrun 263 +#define TARGET_NR_timer_delete 264 +#define TARGET_NR_clock_settime 265 +#define TARGET_NR_clock_gettime 266 +#define TARGET_NR_clock_getres 267 +#define TARGET_NR_clock_nanosleep 268 +#define TARGET_NR_statfs64 269 +#define TARGET_NR_fstatfs64 270 +#define TARGET_NR_tgkill 271 +#define TARGET_NR_utimes 272 +#define TARGET_NR_fadvise64_64 273 + /* 274 TARGET_NR_vserver */ + /* 275 TARGET_NR_mbind */ + /* 276 TARGET_NR_get_mempolicy */ + /* 277 TARGET_NR_set_mempolicy */ +#define TARGET_NR_mq_open 278 +#define TARGET_NR_mq_unlink 279 +#define TARGET_NR_mq_timedsend 280 +#define TARGET_NR_mq_timedreceive 281 +#define TARGET_NR_mq_notify 282 +#define TARGET_NR_mq_getsetattr 283 +#define TARGET_NR_kexec_load 284 +#define TARGET_NR_waitid 285 +#define TARGET_NR_add_key 286 +#define TARGET_NR_request_key 287 +#define TARGET_NR_keyctl 288 +#define TARGET_NR_ioprio_set 289 +#define TARGET_NR_ioprio_get 290 +#define TARGET_NR_inotify_init 291 +#define TARGET_NR_inotify_add_watch 292 +#define TARGET_NR_inotify_rm_watch 293 + /* 294 TARGET_NR_migrate_pages */ +#define TARGET_NR_openat 295 +#define TARGET_NR_mkdirat 296 +#define TARGET_NR_mknodat 297 +#define TARGET_NR_fchownat 298 +#define TARGET_NR_futimesat 299 +#define TARGET_NR_fstatat64 300 +#define TARGET_NR_unlinkat 301 +#define TARGET_NR_renameat 302 +#define TARGET_NR_linkat 303 +#define TARGET_NR_symlinkat 304 +#define TARGET_NR_readlinkat 305 +#define TARGET_NR_fchmodat 306 +#define TARGET_NR_faccessat 307 +#define TARGET_NR_pselect6 308 +#define TARGET_NR_ppoll 309 +#define TARGET_NR_unshare 310 + +/* Blackfin private syscalls */ +#define TARGET_NR_sram_alloc 311 +#define TARGET_NR_sram_free 312 +#define TARGET_NR_dma_memcpy 313 + +/* socket syscalls */ +#define TARGET_NR_accept 314 +#define TARGET_NR_bind 315 +#define TARGET_NR_connect 316 +#define TARGET_NR_getpeername 317 +#define TARGET_NR_getsockname 318 +#define TARGET_NR_getsockopt 319 +#define TARGET_NR_listen 320 +#define TARGET_NR_recv 321 +#define TARGET_NR_recvfrom 322 +#define TARGET_NR_recvmsg 323 +#define TARGET_NR_send 324 +#define TARGET_NR_sendmsg 325 +#define TARGET_NR_sendto 326 +#define TARGET_NR_setsockopt 327 +#define TARGET_NR_shutdown 328 +#define TARGET_NR_socket 329 +#define TARGET_NR_socketpair 330 + +/* sysv ipc syscalls */ +#define TARGET_NR_semctl 331 +#define TARGET_NR_semget 332 +#define TARGET_NR_semop 333 +#define TARGET_NR_msgctl 334 +#define TARGET_NR_msgget 335 +#define TARGET_NR_msgrcv 336 +#define TARGET_NR_msgsnd 337 +#define TARGET_NR_shmat 338 +#define TARGET_NR_shmctl 339 +#define TARGET_NR_shmdt 340 +#define TARGET_NR_shmget 341 + +#define TARGET_NR_splice 342 +#define TARGET_NR_sync_file_range 343 +#define TARGET_NR_tee 344 +#define TARGET_NR_vmsplice 345 + +#define TARGET_NR_epoll_pwait 346 +#define TARGET_NR_utimensat 347 +#define TARGET_NR_signalfd 348 +#define TARGET_NR_timerfd_create 349 +#define TARGET_NR_eventfd 350 +#define TARGET_NR_pread64 351 +#define TARGET_NR_pwrite64 352 +#define TARGET_NR_fadvise64 353 +#define TARGET_NR_set_robust_list 354 +#define TARGET_NR_get_robust_list 355 +#define TARGET_NR_fallocate 356 +#define TARGET_NR_semtimedop 357 +#define TARGET_NR_timerfd_settime 358 +#define TARGET_NR_timerfd_gettime 359 +#define TARGET_NR_signalfd4 360 +#define TARGET_NR_eventfd2 361 +#define TARGET_NR_epoll_create1 362 +#define TARGET_NR_dup3 363 +#define TARGET_NR_pipe2 364 +#define TARGET_NR_inotify_init1 365 +#define TARGET_NR_preadv 366 +#define TARGET_NR_pwritev 367 +#define TARGET_NR_rt_tgsigqueueinfo 368 +#define TARGET_NR_perf_event_open 369 +#define TARGET_NR_recvmmsg 370 +#define TARGET_NR_fanotify_init 371 +#define TARGET_NR_fanotify_mark 372 +#define TARGET_NR_prlimit64 373 +#define TARGET_NR_cacheflush 374 +#define TARGET_NR_name_to_handle_at 375 +#define TARGET_NR_open_by_handle_at 376 +#define TARGET_NR_clock_adjtime 377 +#define TARGET_NR_syncfs 378 +#define TARGET_NR_setns 379 +#define TARGET_NR_sendmmsg 380 +#define TARGET_NR_process_vm_readv 381 +#define TARGET_NR_process_vm_writev 382 +#define TARGET_NR_kcmp 383 +#define TARGET_NR_finit_module 384 +#define TARGET_NR_sched_setattr 385 +#define TARGET_NR_sched_getattr 386 +#define TARGET_NR_renameat2 387 +#define TARGET_NR_seccomp 388 +#define TARGET_NR_getrandom 389 +#define TARGET_NR_memfd_create 390 +#define TARGET_NR_bpf 391 +#define TARGET_NR_execveat 392 + +#define TARGET_NR_syscall 393 diff --git a/linux-user/bfin/target_cpu.h b/linux-user/bfin/target_cpu.h new file mode 100644 index 0000000000000..4e59f076ab8b6 --- /dev/null +++ b/linux-user/bfin/target_cpu.h @@ -0,0 +1,24 @@ +/* + * Blackfin specific CPU ABI and functions for linux-user + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#ifndef TARGET_CPU_H +#define TARGET_CPU_H + +static inline void cpu_clone_regs(CPUArchState *env, target_ulong newsp) +{ + if (newsp) + env->spreg = newsp; +} + +static inline void cpu_set_tls(CPUArchState *env, target_ulong newtls) +{ + /* Blackfin does not do TLS currently. */ +} + +#endif diff --git a/linux-user/bfin/target_flat.h b/linux-user/bfin/target_flat.h new file mode 100644 index 0000000000000..9acc44c24fbc1 --- /dev/null +++ b/linux-user/bfin/target_flat.h @@ -0,0 +1,93 @@ +/* + * uClinux flat-format executables + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2003-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 + */ + +#define FLAT_BFIN_RELOC_TYPE_16_BIT 0 +#define FLAT_BFIN_RELOC_TYPE_16H_BIT 1 +#define FLAT_BFIN_RELOC_TYPE_32_BIT 2 + +#define flat_argvp_envp_on_stack() 0 +#define flat_reloc_valid(reloc, size) ((reloc) <= (size)) +#define flat_old_ram_flag(flag) (flag) +#define flat_get_relocate_addr(relval) ((relval) & 0x03ffffff) + +static inline int flat_set_persistent(abi_ulong relval, abi_ulong *persistent) +{ + int type = (relval >> 26) & 7; + if (type == 3) { + *persistent = relval << 16; + return 1; + } + return 0; +} + +static abi_ulong +flat_get_addr_from_rp(abi_ulong ul_ptr, abi_ulong relval, abi_ulong flags, abi_ulong *persistent) +{ + int type = (relval >> 26) & 7; + abi_ulong val; + +#ifdef DEBUG + printf("%s:%i: ptr:%8x relval:%8x type:%x flags:%x persistent:%x", + __func__, __LINE__, ul_ptr, relval, type, flags, *persistent); +#endif + + switch (type) { + case FLAT_BFIN_RELOC_TYPE_16_BIT: + case FLAT_BFIN_RELOC_TYPE_16H_BIT: + if (get_user_u16(val, ul_ptr)) { + fprintf(stderr, "BINFMT_FLAT: unable to read reloc at %#x\n", ul_ptr); + abort(); + } + val += *persistent; + break; + case FLAT_BFIN_RELOC_TYPE_32_BIT: + if (get_user_u32(val, ul_ptr)) { + fprintf(stderr, "BINFMT_FLAT: unable to read reloc at %#x\n", ul_ptr); + abort(); + } + break; + default: + fprintf(stderr, "BINFMT_FLAT: Unknown relocation type %x\n", type); + abort(); + break; + } +#ifdef DEBUG + printf(" val:%x\n", val); +#endif + + /* + * Stack-relative relocs contain the offset into the stack, we + * have to add the stack's start address here and return 1 from + * flat_addr_absolute to prevent the normal address calculations + */ + if (relval & (1 << 29)) { + fprintf(stderr, "BINFMT_FLAT: stack relocs not supported\n"); + abort(); + /*return val + current->mm->context.end_brk;*/ + } + + if ((flags & FLAT_FLAG_GOTPIC) == 0) + val = ntohl(val); + + return val; +} + +static int +flat_put_addr_at_rp(abi_ulong ptr, abi_ulong addr, abi_ulong relval) +{ + int type = (relval >> 26) & 7; + + switch (type) { + case FLAT_BFIN_RELOC_TYPE_16_BIT: return put_user_u16(addr, ptr); + case FLAT_BFIN_RELOC_TYPE_16H_BIT: return put_user_u16(addr >> 16, ptr); + case FLAT_BFIN_RELOC_TYPE_32_BIT: return put_user_u32(addr, ptr); + } + + abort(); +} diff --git a/linux-user/bfin/target_sigcontext.h b/linux-user/bfin/target_sigcontext.h new file mode 100644 index 0000000000000..10d61e2592ac5 --- /dev/null +++ b/linux-user/bfin/target_sigcontext.h @@ -0,0 +1,61 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef TARGET_SIGCONTEXT_H +#define TARGET_SIGCONTEXT_H + +/* Add new entries at the end of the structure only. */ +struct target_sigcontext { + abi_ulong sc_r0; + abi_ulong sc_r1; + abi_ulong sc_r2; + abi_ulong sc_r3; + abi_ulong sc_r4; + abi_ulong sc_r5; + abi_ulong sc_r6; + abi_ulong sc_r7; + abi_ulong sc_p0; + abi_ulong sc_p1; + abi_ulong sc_p2; + abi_ulong sc_p3; + abi_ulong sc_p4; + abi_ulong sc_p5; + abi_ulong sc_usp; + abi_ulong sc_a0w; + abi_ulong sc_a1w; + abi_ulong sc_a0x; + abi_ulong sc_a1x; + abi_ulong sc_astat; + abi_ulong sc_rets; + abi_ulong sc_pc; + abi_ulong sc_retx; + abi_ulong sc_fp; + abi_ulong sc_i0; + abi_ulong sc_i1; + abi_ulong sc_i2; + abi_ulong sc_i3; + abi_ulong sc_m0; + abi_ulong sc_m1; + abi_ulong sc_m2; + abi_ulong sc_m3; + abi_ulong sc_l0; + abi_ulong sc_l1; + abi_ulong sc_l2; + abi_ulong sc_l3; + abi_ulong sc_b0; + abi_ulong sc_b1; + abi_ulong sc_b2; + abi_ulong sc_b3; + abi_ulong sc_lc0; + abi_ulong sc_lc1; + abi_ulong sc_lt0; + abi_ulong sc_lt1; + abi_ulong sc_lb0; + abi_ulong sc_lb1; + abi_ulong sc_seqstat; +}; + +#endif diff --git a/linux-user/bfin/target_signal.h b/linux-user/bfin/target_signal.h new file mode 100644 index 0000000000000..7367c0a7ac4a3 --- /dev/null +++ b/linux-user/bfin/target_signal.h @@ -0,0 +1,31 @@ +#ifndef TARGET_SIGNAL_H +#define TARGET_SIGNAL_H + +#include "cpu.h" + +/* this struct defines a stack used during syscall handling */ + +typedef struct target_sigaltstack { + abi_ulong ss_sp; + abi_long ss_flags; + abi_ulong ss_size; +} target_stack_t; + + +/* + * sigaltstack controls + */ +#define TARGET_SS_ONSTACK 1 +#define TARGET_SS_DISABLE 2 + +#define TARGET_MINSIGSTKSZ 2048 +#define TARGET_SIGSTKSZ 8192 + +static inline abi_ulong get_sp_from_cpustate(CPUArchState *env) +{ + return env->spreg; +} + +#define TARGET_SIGRETURN_STUB 0x400 + +#endif /* TARGET_SIGNAL_H */ diff --git a/linux-user/bfin/target_structs.h b/linux-user/bfin/target_structs.h new file mode 100644 index 0000000000000..d741ede73a4d2 --- /dev/null +++ b/linux-user/bfin/target_structs.h @@ -0,0 +1,58 @@ +/* + * Blackfin specific structures for linux-user + * + * Copyright (c) 2013 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#ifndef TARGET_STRUCTS_H +#define TARGET_STRUCTS_H + +struct target_ipc_perm { + abi_int __key; /* Key. */ + abi_uint uid; /* Owner's user ID. */ + abi_uint gid; /* Owner's group ID. */ + abi_uint cuid; /* Creator's user ID. */ + abi_uint cgid; /* Creator's group ID. */ + abi_ushort mode; /* Read/write permission. */ + abi_ushort __pad1; + abi_ushort __seq; /* Sequence number. */ + abi_ushort __pad2; + abi_ulong __unused1; + abi_ulong __unused2; +}; + +struct target_shmid_ds { + struct target_ipc_perm shm_perm; /* operation permission struct */ + abi_long shm_segsz; /* size of segment in bytes */ + abi_ulong shm_atime; /* time of last shmat() */ +#if TARGET_ABI_BITS == 32 + abi_ulong __unused1; +#endif + abi_ulong shm_dtime; /* time of last shmdt() */ +#if TARGET_ABI_BITS == 32 + abi_ulong __unused2; +#endif + abi_ulong shm_ctime; /* time of last change by shmctl() */ +#if TARGET_ABI_BITS == 32 + abi_ulong __unused3; +#endif + abi_int shm_cpid; /* pid of creator */ + abi_int shm_lpid; /* pid of last shmop */ + abi_ulong shm_nattch; /* number of current attaches */ + abi_ulong __unused4; + abi_ulong __unused5; +}; + +#endif diff --git a/linux-user/bfin/target_syscall.h b/linux-user/bfin/target_syscall.h new file mode 100644 index 0000000000000..3619eeecfd054 --- /dev/null +++ b/linux-user/bfin/target_syscall.h @@ -0,0 +1,61 @@ +struct target_pt_regs { + abi_ulong orig_pc; + abi_ulong ipend; + abi_ulong seqstat; + abi_ulong rete; + abi_ulong retn; + abi_ulong retx; + abi_ulong pc; /* PC == RETI */ + abi_ulong rets; + abi_ulong reserved; /* Used as scratch during system calls */ + abi_ulong astat; + abi_ulong lb1; + abi_ulong lb0; + abi_ulong lt1; + abi_ulong lt0; + abi_ulong lc1; + abi_ulong lc0; + abi_ulong a1w; + abi_ulong a1x; + abi_ulong a0w; + abi_ulong a0x; + abi_ulong b3; + abi_ulong b2; + abi_ulong b1; + abi_ulong b0; + abi_ulong l3; + abi_ulong l2; + abi_ulong l1; + abi_ulong l0; + abi_ulong m3; + abi_ulong m2; + abi_ulong m1; + abi_ulong m0; + abi_ulong i3; + abi_ulong i2; + abi_ulong i1; + abi_ulong i0; + abi_ulong usp; + abi_ulong fp; + abi_ulong p5; + abi_ulong p4; + abi_ulong p3; + abi_ulong p2; + abi_ulong p1; + abi_ulong p0; + abi_ulong r7; + abi_ulong r6; + abi_ulong r5; + abi_ulong r4; + abi_ulong r3; + abi_ulong r2; + abi_ulong r1; + abi_ulong r0; + abi_ulong orig_r0; + abi_ulong orig_p0; + abi_ulong syscfg; +}; + +#define UNAME_MACHINE "blackfin" + +#define UNAME_MINIMUM_RELEASE "2.6.32" diff --git a/linux-user/bfin/termbits.h b/linux-user/bfin/termbits.h new file mode 100644 index 0000000000000..5c5fa0148d95b --- /dev/null +++ b/linux-user/bfin/termbits.h @@ -0,0 +1,227 @@ +/* from asm/termbits.h */ +/* NOTE: exactly the same as i386 */ + +#define TARGET_NCCS 19 + +struct target_termios { + uint32_t c_iflag; /* input mode flags */ + uint32_t c_oflag; /* output mode flags */ + uint32_t c_cflag; /* control mode flags */ + uint32_t c_lflag; /* local mode flags */ + uint8_t c_line; /* line discipline */ + uint8_t c_cc[TARGET_NCCS]; /* control characters */ +}; + +/* c_iflag bits */ +#define TARGET_IGNBRK 0000001 +#define TARGET_BRKINT 0000002 +#define TARGET_IGNPAR 0000004 +#define TARGET_PARMRK 0000010 +#define TARGET_INPCK 0000020 +#define TARGET_ISTRIP 0000040 +#define TARGET_INLCR 0000100 +#define TARGET_IGNCR 0000200 +#define TARGET_ICRNL 0000400 +#define TARGET_IUCLC 0001000 +#define TARGET_IXON 0002000 +#define TARGET_IXANY 0004000 +#define TARGET_IXOFF 0010000 +#define TARGET_IMAXBEL 0020000 +#define TARGET_IUTF8 0040000 + +/* c_oflag bits */ +#define TARGET_OPOST 0000001 +#define TARGET_OLCUC 0000002 +#define TARGET_ONLCR 0000004 +#define TARGET_OCRNL 0000010 +#define TARGET_ONOCR 0000020 +#define TARGET_ONLRET 0000040 +#define TARGET_OFILL 0000100 +#define TARGET_OFDEL 0000200 +#define TARGET_NLDLY 0000400 +#define TARGET_NL0 0000000 +#define TARGET_NL1 0000400 +#define TARGET_CRDLY 0003000 +#define TARGET_CR0 0000000 +#define TARGET_CR1 0001000 +#define TARGET_CR2 0002000 +#define TARGET_CR3 0003000 +#define TARGET_TABDLY 0014000 +#define TARGET_TAB0 0000000 +#define TARGET_TAB1 0004000 +#define TARGET_TAB2 0010000 +#define TARGET_TAB3 0014000 +#define TARGET_XTABS 0014000 +#define TARGET_BSDLY 0020000 +#define TARGET_BS0 0000000 +#define TARGET_BS1 0020000 +#define TARGET_VTDLY 0040000 +#define TARGET_VT0 0000000 +#define TARGET_VT1 0040000 +#define TARGET_FFDLY 0100000 +#define TARGET_FF0 0000000 +#define TARGET_FF1 0100000 + +/* c_cflag bit meaning */ +#define TARGET_CBAUD 0010017 +#define TARGET_B0 0000000 /* hang up */ +#define TARGET_B50 0000001 +#define TARGET_B75 0000002 +#define TARGET_B110 0000003 +#define TARGET_B134 0000004 +#define TARGET_B150 0000005 +#define TARGET_B200 0000006 +#define TARGET_B300 0000007 +#define TARGET_B600 0000010 +#define TARGET_B1200 0000011 +#define TARGET_B1800 0000012 +#define TARGET_B2400 0000013 +#define TARGET_B4800 0000014 +#define TARGET_B9600 0000015 +#define TARGET_B19200 0000016 +#define TARGET_B38400 0000017 +#define TARGET_EXTA B19200 +#define TARGET_EXTB B38400 +#define TARGET_CSIZE 0000060 +#define TARGET_CS5 0000000 +#define TARGET_CS6 0000020 +#define TARGET_CS7 0000040 +#define TARGET_CS8 0000060 +#define TARGET_CSTOPB 0000100 +#define TARGET_CREAD 0000200 +#define TARGET_PARENB 0000400 +#define TARGET_PARODD 0001000 +#define TARGET_HUPCL 0002000 +#define TARGET_CLOCAL 0004000 +#define TARGET_CBAUDEX 0010000 +#define TARGET_B57600 0010001 +#define TARGET_B115200 0010002 +#define TARGET_B230400 0010003 +#define TARGET_B460800 0010004 +#define TARGET_B500000 0010005 +#define TARGET_B576000 0010006 +#define TARGET_B921600 0010007 +#define TARGET_B1000000 0010010 +#define TARGET_B1152000 0010011 +#define TARGET_B1500000 0010012 +#define TARGET_B2000000 0010013 +#define TARGET_B2500000 0010014 +#define TARGET_B3000000 0010015 +#define TARGET_B3500000 0010016 +#define TARGET_B4000000 0010017 +#define TARGET_CIBAUD 002003600000 /* input baud rate (not used) */ +#define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */ +#define TARGET_CRTSCTS 020000000000 /* flow control */ + +/* c_lflag bits */ +#define TARGET_ISIG 0000001 +#define TARGET_ICANON 0000002 +#define TARGET_XCASE 0000004 +#define TARGET_ECHO 0000010 +#define TARGET_ECHOE 0000020 +#define TARGET_ECHOK 0000040 +#define TARGET_ECHONL 0000100 +#define TARGET_NOFLSH 0000200 +#define TARGET_TOSTOP 0000400 +#define TARGET_ECHOCTL 0001000 +#define TARGET_ECHOPRT 0002000 +#define TARGET_ECHOKE 0004000 +#define TARGET_FLUSHO 0010000 +#define TARGET_PENDIN 0040000 +#define TARGET_IEXTEN 0100000 + +/* c_cc character offsets */ +#define TARGET_VINTR 0 +#define TARGET_VQUIT 1 +#define TARGET_VERASE 2 +#define TARGET_VKILL 3 +#define TARGET_VEOF 4 +#define TARGET_VTIME 5 +#define TARGET_VMIN 6 +#define TARGET_VSWTC 7 +#define TARGET_VSTART 8 +#define TARGET_VSTOP 9 +#define TARGET_VSUSP 10 +#define TARGET_VEOL 11 +#define TARGET_VREPRINT 12 +#define TARGET_VDISCARD 13 +#define TARGET_VWERASE 14 +#define TARGET_VLNEXT 15 +#define TARGET_VEOL2 16 + +/* ioctls */ + +#define TARGET_TCGETS 0x5401 +#define TARGET_TCSETS 0x5402 +#define TARGET_TCSETSW 0x5403 +#define TARGET_TCSETSF 0x5404 +#define TARGET_TCGETA 0x5405 +#define TARGET_TCSETA 0x5406 +#define TARGET_TCSETAW 0x5407 +#define TARGET_TCSETAF 0x5408 +#define TARGET_TCSBRK 0x5409 +#define TARGET_TCXONC 0x540A +#define TARGET_TCFLSH 0x540B + +#define TARGET_TIOCEXCL 0x540C +#define TARGET_TIOCNXCL 0x540D +#define TARGET_TIOCSCTTY 0x540E +#define TARGET_TIOCGPGRP 0x540F +#define TARGET_TIOCSPGRP 0x5410 +#define TARGET_TIOCOUTQ 0x5411 +#define TARGET_TIOCSTI 0x5412 +#define TARGET_TIOCGWINSZ 0x5413 +#define TARGET_TIOCSWINSZ 0x5414 +#define TARGET_TIOCMGET 0x5415 +#define TARGET_TIOCMBIS 0x5416 +#define TARGET_TIOCMBIC 0x5417 +#define TARGET_TIOCMSET 0x5418 +#define TARGET_TIOCGSOFTCAR 0x5419 +#define TARGET_TIOCSSOFTCAR 0x541A +#define TARGET_FIONREAD 0x541B +#define TARGET_TIOCINQ TARGET_FIONREAD +#define TARGET_TIOCLINUX 0x541C +#define TARGET_TIOCCONS 0x541D +#define TARGET_TIOCGSERIAL 0x541E +#define TARGET_TIOCSSERIAL 0x541F +#define TARGET_TIOCPKT 0x5420 +#define TARGET_FIONBIO 0x5421 +#define TARGET_TIOCNOTTY 0x5422 +#define TARGET_TIOCSETD 0x5423 +#define TARGET_TIOCGETD 0x5424 +#define TARGET_TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ +#define TARGET_TIOCTTYGSTRUCT 0x5426 /* For debugging only */ +#define TARGET_TIOCSBRK 0x5427 /* BSD compatibility */ +#define TARGET_TIOCCBRK 0x5428 /* BSD compatibility */ +#define TARGET_TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TARGET_TIOCGPTN TARGET_IOR('T',0x30, uint32_t) /* Get Pty Number (of pty-mux device) */ +#define TARGET_TIOCSPTLCK TARGET_IOW('T',0x31, int32_t) /* Lock/unlock Pty */ + +#define TARGET_FIONCLEX 0x5450 /* these numbers need to be adjusted. */ +#define TARGET_FIOCLEX 0x5451 +#define TARGET_FIOASYNC 0x5452 +#define TARGET_TIOCSERCONFIG 0x5453 +#define TARGET_TIOCSERGWILD 0x5454 +#define TARGET_TIOCSERSWILD 0x5455 +#define TARGET_TIOCGLCKTRMIOS 0x5456 +#define TARGET_TIOCSLCKTRMIOS 0x5457 +#define TARGET_TIOCSERGSTRUCT 0x5458 /* For debugging only */ +#define TARGET_TIOCSERGETLSR 0x5459 /* Get line status register */ +#define TARGET_TIOCSERGETMULTI 0x545A /* Get multiport config */ +#define TARGET_TIOCSERSETMULTI 0x545B /* Set multiport config */ + +#define TARGET_TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ +#define TARGET_TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ +#define TARGET_TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */ +#define TARGET_TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */ + +/* Used for packet mode */ +#define TARGET_TIOCPKT_DATA 0 +#define TARGET_TIOCPKT_FLUSHREAD 1 +#define TARGET_TIOCPKT_FLUSHWRITE 2 +#define TARGET_TIOCPKT_STOP 4 +#define TARGET_TIOCPKT_START 8 +#define TARGET_TIOCPKT_NOSTOP 16 +#define TARGET_TIOCPKT_DOSTOP 32 + +#define TARGET_TIOCSER_TEMT 0x01 /* Transmitter physically empty */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f807baf38965a..45b8247c58cda 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1152,6 +1152,48 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUM68KState *e #endif +#ifdef TARGET_BFIN + +#define ELF_START_MMAP 0x00000000 + +#define elf_check_arch(x) ( (x) == EM_BLACKFIN ) +#define elf_is_fdpic(e) ( (e)->e_flags & EF_BFIN_FDPIC ) + +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_BLACKFIN + +static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) +{ + if (infop->personality == PER_LINUX_FDPIC) { + if (infop->other_info) { + /* dynamic */ + regs->p0 = tswapl(infop->loadmap_addr); + regs->p1 = tswapl(infop->other_info->loadmap_addr); + regs->p2 = tswapl(infop->other_info->pt_dynamic_addr); + } else { + /* static */ + regs->p0 = tswapl(infop->loadmap_addr); + regs->p1 = 0; + regs->p2 = tswapl(infop->pt_dynamic_addr); + } + regs->r7 = 0; + } else if (infop->start_code == 0) { + /* Must be bare metal ELF ... */ + infop->personality = PER_MASK; + } + regs->pc = tswapl(infop->entry); + regs->usp = tswapl(infop->start_stack); +} + +#define ELF_EXEC_PAGESIZE 4096 + +/* See linux kernel: arch/blackfin/include/asm/elf.h. */ +#define ELF_NREG 40 +typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG]; + +#endif + #ifdef TARGET_ALPHA #define ELF_START_MMAP (0x30000000000ULL) @@ -1875,6 +1917,11 @@ static void load_elf_image(const char *image_name, int image_fd, address does not conflict with MMAP_MIN_ADDR or the QEMU application itself. */ probe_guest_base(image_name, loaddr, hiaddr); +#ifdef TARGET_BFIN + /* Make space for the fixed code region */ + if (elf_is_fdpic(ehdr) && load_addr < 0x1000) + load_addr += 0x1000; +#endif } load_bias = load_addr - loaddr; diff --git a/linux-user/main.c b/linux-user/main.c index f2f4d2f05a2df..6fbab81b707ab 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3163,6 +3163,115 @@ void cpu_loop(CPUM68KState *env) } #endif /* TARGET_M68K */ +#ifdef TARGET_BFIN + +#include "disas/disas.h" + +void cpu_loop(CPUArchState *env) +{ + CPUState *cs = ENV_GET_CPU(env); + int trapnr, gdbsig; + target_siginfo_t info; + + for (;;) { + cpu_exec_start(cs); + trapnr = cpu_exec(cs); + cpu_exec_end(cs); + gdbsig = 0; + + switch (trapnr) { + case EXCP_SYSCALL: + env->pc += 2; + env->dreg[0] = do_syscall(env, + env->preg[0], + env->dreg[0], + env->dreg[1], + env->dreg[2], + env->dreg[3], + env->dreg[4], + env->dreg[5], 0, 0); + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_DEBUG: + /* XXX: does this handle hwloops ? */ + /*env->pc += 2;*/ + /* EMUEXCPT signals debugger only if attached; NOP otherwise */ + gdbsig = TARGET_SIGTRAP; + break; + case EXCP_SOFT_BP: + { + int sig = gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) { + info.si_signo = sig; + info.si_errno = 0; + info.si_code = TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, &info); + } + } + break; + case EXCP_HLT: + do_syscall(env, TARGET_NR_exit, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case EXCP_ABORT: + do_syscall(env, TARGET_NR_exit, 1, 0, 0, 0, 0, 0, 0, 0); + break; + case EXCP_DBGA: + fprintf(stderr, "qemu: DBGA failed\n"); + cpu_dump_state(cs, stderr, fprintf, 0); + gdbsig = TARGET_SIGABRT; + break; + case EXCP_UNDEF_INST: + fprintf(stderr, "qemu: unhandled insn @ %#x\n", env->pc); + log_target_disas(cs, env->pc, 8, 0); + gdbsig = TARGET_SIGILL; + break; + case EXCP_DCPLB_VIOLATE: + fprintf(stderr, "qemu: memory violation @ %#x\n", env->pc); + log_target_disas(cs, env->pc, 8, 0); + cpu_dump_state(cs, stderr, fprintf, 0); + gdbsig = TARGET_SIGSEGV; + break; + case EXCP_ILL_SUPV: + fprintf(stderr, "qemu: supervisor mode required @ %#x\n", env->pc); + log_target_disas(cs, env->pc, 8, 0); + gdbsig = TARGET_SIGILL; + break; + case EXCP_MISALIG_INST: + fprintf(stderr, "qemu: unaligned insn fetch @ %#x\n", env->pc); + log_target_disas(cs, env->pc, 8, 0); + cpu_dump_state(cs, stderr, fprintf, 0); + gdbsig = TARGET_SIGSEGV; + break; + case EXCP_DATA_MISALGIN: + fprintf(stderr, "qemu: unaligned data fetch @ %#x\n", env->pc); + log_target_disas(cs, env->pc, 8, 0); + cpu_dump_state(cs, stderr, fprintf, 0); + gdbsig = TARGET_SIGSEGV; + break; + default: + fprintf(stderr, "qemu: unhandled CPU exception %#x - aborting\n", + trapnr); + cpu_dump_state(cs, stderr, fprintf, 0); + gdbsig = TARGET_SIGILL; + break; + } + + if (gdbsig) { + gdb_handlesig(cs, gdbsig); + /* XXX: should we let people continue if gdb handles the signal ? */ + if (gdbsig != TARGET_SIGTRAP) { + exit(1); + } + } + + process_pending_signals(env); + } +} + +#endif + #ifdef TARGET_ALPHA static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) { @@ -4315,7 +4424,7 @@ int main(int argc, char **argv, char **envp) qemu_host_page_size */ cpu = cpu_init(cpu_model); if (!cpu) { - fprintf(stderr, "Unable to find CPU definition\n"); + fprintf(stderr, "Unable to find CPU definition: %s\n", cpu_model); exit(EXIT_FAILURE); } env = cpu->env_ptr; @@ -4741,6 +4850,57 @@ int main(int argc, char **argv, char **envp) } env->pc = regs->pc; } +#elif defined(TARGET_BFIN) + { + env->personality = info->personality; + env->dreg[0] = regs->r0; + env->dreg[1] = regs->r1; + env->dreg[2] = regs->r2; + env->dreg[3] = regs->r3; + env->dreg[4] = regs->r4; + env->dreg[5] = regs->r5; + env->dreg[6] = regs->r6; + env->dreg[7] = regs->r7; + env->preg[0] = regs->p0; + env->preg[1] = regs->p1; + env->preg[2] = regs->p2; + env->preg[3] = regs->p3; + env->preg[4] = regs->p4; + env->preg[5] = regs->p5; + env->spreg = regs->usp; + env->fpreg = regs->fp; + env->uspreg = regs->usp; + env->breg[0] = regs->b0; + env->breg[1] = regs->b1; + env->breg[2] = regs->b2; + env->breg[3] = regs->b3; + env->lreg[0] = regs->l0; + env->lreg[1] = regs->l1; + env->lreg[2] = regs->l2; + env->lreg[3] = regs->l3; + env->mreg[0] = regs->m0; + env->mreg[1] = regs->m1; + env->mreg[2] = regs->m2; + env->mreg[3] = regs->m3; + env->ireg[0] = regs->i0; + env->ireg[1] = regs->i1; + env->ireg[2] = regs->i2; + env->ireg[3] = regs->i3; + env->lcreg[0] = regs->lc0; + env->ltreg[0] = regs->lt0; + env->lbreg[0] = regs->lb0; + env->lcreg[1] = regs->lc1; + env->ltreg[1] = regs->lt1; + env->lbreg[1] = regs->lb1; + env->areg[0] = ((uint64_t)regs->a0x << 32) | regs->a0w; + env->areg[1] = ((uint64_t)regs->a1x << 32) | regs->a1w; + env->rets = regs->rets; + env->rete = regs->rete; + env->retn = regs->retn; + env->retx = regs->retx; + env->pc = regs->pc; + bfin_astat_write(env, regs->astat); + } #elif defined(TARGET_ALPHA) { int i; diff --git a/linux-user/qemu.h b/linux-user/qemu.h index bef465de4d933..46158789d2032 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -25,6 +25,10 @@ */ #define SIGSET_T_SIZE (_NSIG / 8) +#ifdef TARGET_BFIN +#define CONFIG_USE_FDPIC +#endif + /* This struct is used to hold certain information about the image. * Basically, it replicates in user space what would be certain * task_struct fields in the kernel diff --git a/linux-user/signal.c b/linux-user/signal.c index 9a4d894e3afe3..80b2906330073 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -254,7 +254,7 @@ int do_sigprocmask(int how, const sigset_t *set, sigset_t *oldset) } #if !defined(TARGET_OPENRISC) && !defined(TARGET_UNICORE32) && \ - !defined(TARGET_X86_64) + !defined(TARGET_X86_64) && !defined(TARGET_BFIN) /* Just set the guest's signal mask to the specified value; the * caller is assumed to have called block_signals() already. */ @@ -5797,6 +5797,220 @@ long do_rt_sigreturn(CPUTLGState *env) force_sig(TARGET_SIGSEGV); } +#elif defined(TARGET_BFIN) + +#include "target_sigcontext.h" +#include "target_ucontext.h" + +struct target_rt_sigframe { + int32_t sig; + abi_ulong pinfo; + abi_ulong puc; + /* This is no longer needed by the kernel, but unfortunately userspace + * code expects it to be there. */ + char retcode[8]; + target_siginfo_t info; + struct target_ucontext uc; +}; + +struct fdpic_func_descriptor { + abi_ulong text; + abi_ulong GOT; +}; + +#define rreg dreg + +static inline void +target_rt_restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc, long *ret) +{ + uint32_t reg; + +#define RESTORE2(e, x) __get_user(env->e, &sc->sc_##x) +#define RESTOREA(r, i) RESTORE2(r##reg[i], r##i) +#define RESTORE(x) RESTORE2(x, x) + + /* restore passed registers */ + RESTOREA(r, 0); RESTOREA(r, 1); RESTOREA(r, 2); RESTOREA(r, 3); + RESTOREA(r, 4); RESTOREA(r, 5); RESTOREA(r, 6); RESTOREA(r, 7); + RESTOREA(p, 0); RESTOREA(p, 1); RESTOREA(p, 2); RESTOREA(p, 3); + RESTOREA(p, 4); RESTOREA(p, 5); + RESTORE2(spreg, usp); + __get_user(reg, &sc->sc_a0x); + env->areg[0] = reg; + __get_user(reg, &sc->sc_a0w); + env->areg[0] = (env->areg[0] << 32) | reg; + __get_user(reg, &sc->sc_a1x); + env->areg[1] = reg; + __get_user(reg, &sc->sc_a1w); + env->areg[1] = (env->areg[1] << 32) | reg; + __get_user(reg, &sc->sc_astat); + bfin_astat_write(env, reg); + RESTORE(rets); + RESTORE(pc); + RESTORE(retx); + RESTORE2(fpreg, fp); + RESTOREA(i, 0); RESTOREA(i, 1); RESTOREA(i, 2); RESTOREA(i, 3); + RESTOREA(m, 0); RESTOREA(m, 1); RESTOREA(m, 2); RESTOREA(m, 3); + RESTOREA(l, 0); RESTOREA(l, 1); RESTOREA(l, 2); RESTOREA(l, 3); + RESTOREA(b, 0); RESTOREA(b, 1); RESTOREA(b, 2); RESTOREA(b, 3); + RESTOREA(lc, 0); RESTOREA(lc, 1); + RESTOREA(lt, 0); RESTOREA(lt, 1); + RESTOREA(lb, 0); RESTOREA(lb, 1); + RESTORE(seqstat); + + *ret = env->dreg[0]; +} + +static inline void +target_rt_setup_sigcontext(struct target_sigcontext *sc, CPUArchState *env) +{ +#define SETUP2(e, x) __put_user(env->e, &sc->sc_##x) +#define SETUPA(r, i) SETUP2(r##reg[i], r##i) +#define SETUP(x) SETUP2(x, x) + + SETUPA(r, 0); SETUPA(r, 1); SETUPA(r, 2); SETUPA(r, 3); + SETUPA(r, 4); SETUPA(r, 5); SETUPA(r, 6); SETUPA(r, 7); + SETUPA(p, 0); SETUPA(p, 1); SETUPA(p, 2); SETUPA(p, 3); + SETUPA(p, 4); SETUPA(p, 5); + SETUP2(spreg, usp); + __put_user((uint32_t)env->areg[0], &sc->sc_a0w); + __put_user((uint32_t)env->areg[1], &sc->sc_a1w); + __put_user((uint32_t)(env->areg[0] >> 32), &sc->sc_a0x); + __put_user((uint32_t)(env->areg[1] >> 32), &sc->sc_a1x); + __put_user(bfin_astat_read(env), &sc->sc_astat); + SETUP(rets); + SETUP(pc); + SETUP(retx); + SETUP2(fpreg, fp); + SETUPA(i, 0); SETUPA(i, 1); SETUPA(i, 2); SETUPA(i, 3); + SETUPA(m, 0); SETUPA(m, 1); SETUPA(m, 2); SETUPA(m, 3); + SETUPA(l, 0); SETUPA(l, 1); SETUPA(l, 2); SETUPA(l, 3); + SETUPA(b, 0); SETUPA(b, 1); SETUPA(b, 2); SETUPA(b, 3); + SETUPA(lc, 0); SETUPA(lc, 1); + SETUPA(lt, 0); SETUPA(lt, 1); + SETUPA(lb, 0); SETUPA(lb, 1); + SETUP(seqstat); +} + +#undef rreg + +static inline abi_ulong +get_sigframe(struct target_sigaction *ka, CPUArchState *env, size_t frame_size) +{ + abi_ulong usp; + + /* Default to using normal stack. */ + usp = env->spreg; + + /* This is the X/Open sanctioned signal stack switching. */ + if ((ka->sa_flags & TARGET_SA_ONSTACK) && (sas_ss_flags(usp) == 0)) { + usp = target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_size; + } + + return ((usp - frame_size) & -8UL); +} + +static void setup_rt_frame(int sig, struct target_sigaction *ka, + target_siginfo_t *info, + target_sigset_t *set, CPUArchState *env) +{ + struct target_rt_sigframe *frame; + abi_ulong frame_addr; + abi_ulong info_addr; + abi_ulong uc_addr; + int i; + + frame_addr = get_sigframe(ka, env, sizeof(*frame)); + if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) + goto give_sigsegv; + + __put_user(sig, &frame->sig); + + info_addr = frame_addr + offsetof(struct target_rt_sigframe, info); + __put_user(info_addr, &frame->pinfo); + uc_addr = frame_addr + offsetof(struct target_rt_sigframe, uc); + __put_user(uc_addr, &frame->puc); + tswap_siginfo(&frame->info, info); + + /* Create the ucontext. */ + __put_user(0, &frame->uc.tuc_flags); + __put_user(0, &frame->uc.tuc_link); + __put_user(target_sigaltstack_used.ss_sp, &frame->uc.tuc_stack.ss_sp); + __put_user(sas_ss_flags(env->spreg), &frame->uc.tuc_stack.ss_flags); + __put_user(target_sigaltstack_used.ss_size, &frame->uc.tuc_stack.ss_size); + target_rt_setup_sigcontext(&frame->uc.tuc_mcontext, env); + + for (i = 0; i < TARGET_NSIG_WORDS; i++) { + __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]); + } + + /* Set up registers for signal handler */ + env->spreg = frame_addr; + if (env->personality & 0x0080000/*FDPIC_FUNCPTRS*/) { + struct fdpic_func_descriptor *funcptr; + if (!lock_user_struct(VERIFY_READ, funcptr, ka->_sa_handler, 1)) + goto give_sigsegv; + __get_user(env->pc, &funcptr->text); + __get_user(env->preg[3], &funcptr->GOT); + unlock_user_struct(funcptr, ka->_sa_handler, 0); + } else { + env->pc = ka->_sa_handler; + } + env->rets = TARGET_SIGRETURN_STUB; + + env->dreg[0] = frame->sig; + env->dreg[1] = info_addr; + env->dreg[2] = uc_addr; + + unlock_user_struct(frame, frame_addr, 1); + return; + + give_sigsegv: + unlock_user_struct(frame, frame_addr, 1); + force_sig(TARGET_SIGSEGV); +} + +static void setup_frame(int sig, struct target_sigaction *ka, + target_sigset_t *set, CPUArchState *env) +{ + target_siginfo_t info; + setup_rt_frame(sig, ka, &info, set, env); +} + +long do_sigreturn(CPUArchState *env) +{ + fprintf(stderr, "do_sigreturn: not implemented\n"); + return -TARGET_ENOSYS; +} + +/* NB: This version should work for any arch ... */ +long do_rt_sigreturn(CPUArchState *env) +{ + long ret; + abi_ulong frame_addr = env->spreg; + struct target_rt_sigframe *frame; + sigset_t host_set; + + if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) + goto badframe; + + target_to_host_sigset(&host_set, &frame->uc.tuc_sigmask); + sigprocmask(SIG_SETMASK, &host_set, NULL); + + target_rt_restore_sigcontext(env, &frame->uc.tuc_mcontext, &ret); + + if (do_sigaltstack(frame_addr + offsetof(struct target_rt_sigframe, uc.tuc_stack), 0, get_sp_from_cpustate(env)) == -EFAULT) + goto badframe; + + unlock_user_struct(frame, frame_addr, 0); + return ret; + + badframe: + unlock_user_struct(frame, frame_addr, 0); + force_sig(TARGET_SIGSEGV); + return 0; +} + #else static void setup_frame(int sig, struct target_sigaction *ka, diff --git a/linux-user/strace.list b/linux-user/strace.list index aa967a24754e7..d6e58fb59b460 100644 --- a/linux-user/strace.list +++ b/linux-user/strace.list @@ -105,6 +105,9 @@ #ifdef TARGET_NR_dipc { TARGET_NR_dipc, "dipc" , NULL, NULL, NULL }, #endif +#ifdef TARGET_NR_dma_memcpy +{ TARGET_NR_dma_memcpy, "dma_memcpy" , NULL, NULL, NULL }, +#endif #ifdef TARGET_NR_dup { TARGET_NR_dup, "dup" , NULL, NULL, NULL }, #endif @@ -1304,6 +1307,12 @@ #ifdef TARGET_NR_splice { TARGET_NR_splice, "splice" , NULL, NULL, NULL }, #endif +#ifdef TARGET_NR_sram_alloc +{ TARGET_NR_sram_alloc, "sram_alloc" , NULL, NULL, NULL }, +#endif +#ifdef TARGET_NR_sram_free +{ TARGET_NR_sram_free, "sram_free" , NULL, NULL, NULL }, +#endif #ifdef TARGET_NR_ssetmask { TARGET_NR_ssetmask, "ssetmask" , NULL, NULL, NULL }, #endif diff --git a/linux-user/syscall.c b/linux-user/syscall.c index ca06943f3b286..250b91e65f4fe 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -7301,6 +7301,14 @@ static target_timer_t get_timer_id(abi_long arg) return timerid; } +#ifdef TARGET_NR_sram_alloc +struct sram_frag { + struct sram_frag *next; + abi_ulong addr, size; +}; +static struct sram_frag *sfrags; +#endif + /* do_syscall() should always have a single exit point at the end so that actions, such as logging of syscall results, can be performed. All errnos that do_syscall() returns must be -TARGET_. */ @@ -8894,6 +8902,72 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, case TARGET_NR_munlockall: ret = get_errno(munlockall()); break; +#endif +#ifdef TARGET_NR_sram_alloc + case TARGET_NR_sram_alloc: + { + /* We don't want L1 insn to be read/write, but doing that + * keeps standard qemu funcs from being able to read/write + * that too. So grant r/w access to all. */ + int prot = PROT_READ | PROT_WRITE; + if ((arg2 & 1 /*L1_INST_SRAM*/) || (arg2 & 8 /*L2_SRAM*/)) { + prot |= PROT_EXEC; + } + + ret = get_errno(target_mmap(0, arg1, prot, MAP_PRIVATE | + MAP_ANONYMOUS, -1, 0)); + + if (!is_error(ret)) { + struct sram_frag *sf = malloc(sizeof(*sf)); + sf->addr = ret; + sf->size = arg1; + if (sfrags) { + sf->next = sfrags; + sfrags = sf; + } else { + sf->next = NULL; + sfrags = sf; + } + } + } + break; +#endif +#ifdef TARGET_NR_sram_free + case TARGET_NR_sram_free: + { + struct sram_frag *sf, *prev; + + ret = -TARGET_EINVAL; + + sf = prev = sfrags; + while (sf) { + if (sf->addr == arg1) { + ret = get_errno(target_munmap(arg1, sf->size)); + if (!is_error(ret)) { + if (sfrags == sf) { + sfrags = sf->next; + } else { + prev->next = sf->next; + } + free(sf); + } + break; + } + prev = sf; + sf = sf->next; + } + } + break; +#endif +#ifdef TARGET_NR_dma_memcpy + case TARGET_NR_dma_memcpy: + p = alloca(arg3); + if (copy_from_user(p, arg2, arg3)) + goto efault; + if (copy_to_user(arg1, p, arg3)) + goto efault; + ret = arg1; + break; #endif case TARGET_NR_truncate: if (!(p = lock_user_string(arg1))) diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 783565463fe1c..6ba9f70355467 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -68,7 +68,8 @@ #if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SH4) \ || defined(TARGET_M68K) || defined(TARGET_CRIS) \ || defined(TARGET_UNICORE32) || defined(TARGET_S390X) \ - || defined(TARGET_OPENRISC) || defined(TARGET_TILEGX) + || defined(TARGET_OPENRISC) || defined(TARGET_TILEGX) \ + || defined(TARGET_BFIN) #define TARGET_IOC_SIZEBITS 14 #define TARGET_IOC_DIRBITS 2 @@ -387,7 +388,7 @@ int do_sigaction(int sig, const struct target_sigaction *act, || defined(TARGET_M68K) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) \ || defined(TARGET_MICROBLAZE) || defined(TARGET_UNICORE32) \ || defined(TARGET_S390X) || defined(TARGET_OPENRISC) \ - || defined(TARGET_TILEGX) + || defined(TARGET_TILEGX) || defined(TARGET_BFIN) #if defined(TARGET_SPARC) #define TARGET_SA_NOCLDSTOP 8u @@ -1763,6 +1764,68 @@ struct target_stat64 { int64_t st_blocks; }; +#elif defined(TARGET_BFIN) + +struct target_stat { + uint16_t st_dev; + uint16_t __pad1; + abi_ulong st_ino; + uint16_t st_mode; + uint16_t st_nlink; + uint16_t st_uid; + uint16_t st_gid; + uint16_t st_rdev; + uint16_t __pad2; + abi_ulong st_size; + abi_ulong st_blksize; + abi_ulong st_blocks; + abi_ulong target_st_atime; + abi_ulong __unused1; + abi_ulong target_st_mtime; + abi_ulong __unused2; + abi_ulong target_st_ctime; + abi_ulong __unused3; + abi_ulong __unused4; + abi_ulong __unused5; +} __attribute__((packed)); + +/* This matches struct stat64 in glibc2.1, hence the absolutely + * insane amounts of padding around dev_t's. + */ +#define TARGET_HAS_STRUCT_STAT64 +struct target_stat64 { + uint64_t st_dev; + unsigned char __pad1[4]; + +#define STAT64_HAS_BROKEN_ST_INO 1 + abi_ulong __st_ino; + + uint32_t st_mode; + uint32_t st_nlink; + + abi_ulong st_uid; + abi_ulong st_gid; + + uint64_t st_rdev; + unsigned char __pad2[4]; + + int64_t st_size; + abi_ulong st_blksize; + + int64_t st_blocks; /* Number 512-byte blocks allocated. */ + + abi_ulong target_st_atime; + abi_ulong target_st_atime_nsec; + + abi_ulong target_st_mtime; + abi_ulong target_st_mtime_nsec; + + abi_ulong target_st_ctime; + abi_ulong target_st_ctime_nsec; + + uint64_t st_ino; +} __attribute__((packed)); + #elif defined(TARGET_ALPHA) struct target_stat { @@ -2256,6 +2319,11 @@ struct target_statfs64 { #define TARGET_O_CLOEXEC 0x400000 #define TARGET___O_SYNC 0x800000 #define TARGET_O_PATH 0x1000000 +#elif defined (TARGET_BFIN) +#define TARGET_O_DIRECTORY 040000 +#define TARGET_O_NOFOLLOW 0100000 +#define TARGET_O_DIRECT 0200000 +#define TARGET_O_LARGEFILE 0400000 #endif /* values follow. */ diff --git a/linux-user/target_ucontext.h b/linux-user/target_ucontext.h new file mode 100644 index 0000000000000..49706b41a1d4a --- /dev/null +++ b/linux-user/target_ucontext.h @@ -0,0 +1,14 @@ +/* This is the asm-generic/ucontext.h version */ + +#ifndef TARGET_UCONTEXT_H +#define TARGET_UCONTEXT_H + +struct target_ucontext { + abi_ulong tuc_flags; + abi_ulong tuc_link; + target_stack_t tuc_stack; + struct target_sigcontext tuc_mcontext; + target_sigset_t tuc_sigmask; /* mask last for extensibility */ +}; + +#endif diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index de4d1c13d49ba..30a1c840870f5 100755 --- a/scripts/qemu-binfmt-conf.sh +++ b/scripts/qemu-binfmt-conf.sh @@ -3,7 +3,7 @@ qemu_target_list="i386 i486 alpha arm sparc32plus ppc ppc64 ppc64le m68k \ mips mipsel mipsn32 mipsn32el mips64 mips64el \ -sh4 sh4eb s390x aarch64" +sh4 sh4eb s390x aarch64 bfin_elf bfin_flat" i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00' i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' @@ -25,6 +25,14 @@ armeb_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00 armeb_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff' armeb_family=arm +bfin_elf_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x6A\x00' +bfin_elf_mask='' +bfin_elf_family=bfin + +bfin_flat_magic='bFLT\x00\x00\x00\x04' +bfin_flat_mask='' +bfin_flat_family=bfin + sparc_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x02' sparc_mask='\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff' sparc_family=sparc diff --git a/target-bfin/Makefile.objs b/target-bfin/Makefile.objs new file mode 100644 index 0000000000000..9931261d8dc23 --- /dev/null +++ b/target-bfin/Makefile.objs @@ -0,0 +1,2 @@ +obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o +obj-$(CONFIG_SOFTMMU) += machine.o monitor.o diff --git a/target-bfin/README b/target-bfin/README new file mode 100644 index 0000000000000..25f7fdef34435 --- /dev/null +++ b/target-bfin/README @@ -0,0 +1,32 @@ +------------------ +Blackfin QEMU port +------------------ + +There are some things we don't bother handling in the port for speed reasons. +If you want an accurate (but not as fast) simulator, then use the GNU sim as +found in the GNU toolchain (part of gdb). + +Things we do not currently handle by design: + + - invalid parallel instruction combinations + - no toolchain will output these + - things like jumps + + - invalid register combinations + - some insns cannot have same register be both source and dest + - no toolchain will output these + + - transactional parallel instructions + - on the hardware, if a load/store causes an exception, the other + insns do not change register states either. in qemu, they do, + but since those exceptions will kill the program anyways, who + cares. no intermediate store buffers! + + - AC0_COPY and V_COPY + - no one has ever used these instead of AC0 or V + + - no support for RND_MOD + +There are a few insns/modes we don't currently handle, but it's more a matter +of nothing really uses these, so we haven't bothered. If these matter to you, +then feel free to request support for them. diff --git a/target-bfin/TODO b/target-bfin/TODO new file mode 100644 index 0000000000000..80802bd14cf91 --- /dev/null +++ b/target-bfin/TODO @@ -0,0 +1,25 @@ +CEC behavior in user-emulation (SP vs USP) + +see if making a global "0", "1", "2", and "4" register speeds things up + +TB chaining is not implemented + +we often over-translate code blocks. consider a bfin mem/str func: + { + [1] setup code + [2] hwloop0 + [3] some other stuff + [4] hwloop1 + [5] clean up / return + } +the first TB will go from the start to the end (since there are no +unconditional branches). then when we hit the hwloop bottom, we jump +back up to the top of the hwloop and a new TB which goes all the way +to the end of the func. so we end up with the TBs covering: + {1-5} {2-5} {3-5} {4-5} {5-5} +In reality, we probably want to have the TBs to be like: + {[1] to LSETUP then to LT0 (usually the same)} + {[2] LT0 to LB0} + {[3] to LSETUP then to LT1 (usually the same)} + {[4] LT1 to LB1} + {[5]} diff --git a/target-bfin/bfin-sim.c b/target-bfin/bfin-sim.c new file mode 100644 index 0000000000000..7df07b7941567 --- /dev/null +++ b/target-bfin/bfin-sim.c @@ -0,0 +1,3679 @@ +/* + * Simulator for Analog Devices Blackfin processors. + * + * Copyright 2005-2016 Mike Frysinger + * Copyright 2005-2011 Analog Devices, Inc. + * + * Licensed under the GPL 2 or later. + */ + +#include "qemu/osdep.h" + +#define TRACE_EXTRACT(fmt, args...) \ +do { \ + if (1) { \ + qemu_log_mask(CPU_LOG_TB_CPU, "%s: " fmt "\n", __func__, ## args); \ + } \ +} while (0) + +static void +illegal_instruction(DisasContext *dc) +{ + cec_exception(dc, EXCP_UNDEF_INST); +} + +static void +unhandled_instruction(DisasContext *dc, const char *insn) +{ + qemu_log_mask(LOG_UNIMP, "unhandled insn: %s\n", insn); + illegal_instruction(dc); +} + +typedef enum { + c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4, + c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, + c_imm5d, c_uimm5, c_imm6, c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, + c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10, c_pcrel12, c_imm16s4, + c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4, + c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e, +} const_forms_t; + +static const struct { + const char *name; + const int nbits; + const char reloc; + const char issigned; + const char pcrel; + const char scale; + const char offset; + const char negative; + const char positive; + const char decimal; + const char leading; + const char exact; +} constant_formats[] = { + { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0}, + { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0}, + { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0}, + { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0}, + { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0}, + { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0}, + { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0}, + { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0}, + { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0}, + { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0}, + { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0}, + { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1}, +}; + +#define HOST_LONG_WORD_SIZE (sizeof(long) * 8) +#define SIGNEXTEND(v, n) (((int32_t)(v) << (HOST_LONG_WORD_SIZE - (n))) \ + >> (HOST_LONG_WORD_SIZE - (n))) + +static uint32_t +fmtconst_val(const_forms_t cf, uint32_t x) +{ + /* Negative constants have an implied sign bit. */ + if (constant_formats[cf].negative) { + int nb = constant_formats[cf].nbits + 1; + x = x | (1 << constant_formats[cf].nbits); + x = SIGNEXTEND(x, nb); + } else if (constant_formats[cf].issigned) { + x = SIGNEXTEND(x, constant_formats[cf].nbits); + } + + x += constant_formats[cf].offset; + x <<= constant_formats[cf].scale; + + return x; +} + +#define uimm16s4(x) fmtconst_val(c_uimm16s4, x) +#define uimm16s4d(x) fmtconst_val(c_uimm16s4d, x) +#define pcrel4(x) fmtconst_val(c_pcrel4, x) +#define pcrel8(x) fmtconst_val(c_pcrel8, x) +#define pcrel8s4(x) fmtconst_val(c_pcrel8s4, x) +#define pcrel10(x) fmtconst_val(c_pcrel10, x) +#define pcrel12(x) fmtconst_val(c_pcrel12, x) +#define negimm5s4(x) fmtconst_val(c_negimm5s4, x) +#define rimm16(x) fmtconst_val(c_rimm16, x) +#define huimm16(x) fmtconst_val(c_huimm16, x) +#define imm16(x) fmtconst_val(c_imm16, x) +#define imm16d(x) fmtconst_val(c_imm16d, x) +#define uimm2(x) fmtconst_val(c_uimm2, x) +#define uimm3(x) fmtconst_val(c_uimm3, x) +#define luimm16(x) fmtconst_val(c_luimm16, x) +#define uimm4(x) fmtconst_val(c_uimm4, x) +#define uimm5(x) fmtconst_val(c_uimm5, x) +#define imm16s2(x) fmtconst_val(c_imm16s2, x) +#define uimm8(x) fmtconst_val(c_uimm8, x) +#define imm16s4(x) fmtconst_val(c_imm16s4, x) +#define uimm4s2(x) fmtconst_val(c_uimm4s2, x) +#define uimm4s4(x) fmtconst_val(c_uimm4s4, x) +#define uimm4s4d(x) fmtconst_val(c_uimm4s4d, x) +#define lppcrel10(x) fmtconst_val(c_lppcrel10, x) +#define imm3(x) fmtconst_val(c_imm3, x) +#define imm4(x) fmtconst_val(c_imm4, x) +#define uimm8s4(x) fmtconst_val(c_uimm8s4, x) +#define imm5(x) fmtconst_val(c_imm5, x) +#define imm5d(x) fmtconst_val(c_imm5d, x) +#define imm6(x) fmtconst_val(c_imm6, x) +#define imm7(x) fmtconst_val(c_imm7, x) +#define imm7d(x) fmtconst_val(c_imm7d, x) +#define imm8(x) fmtconst_val(c_imm8, x) +#define pcrel24(x) fmtconst_val(c_pcrel24, x) +#define uimm16(x) fmtconst_val(c_uimm16, x) +#define uimm32(x) fmtconst_val(c_uimm32, x) +#define imm32(x) fmtconst_val(c_imm32, x) +#define huimm32(x) fmtconst_val(c_huimm32, x) +#define huimm32e(x) fmtconst_val(c_huimm32e, x) + +/* Table C-4. Core Register Encoding Map */ +const char * const greg_names[] = { + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", + "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", + "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3", + "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3", + "A0.X", "A0.W", "A1.X", "A1.W", "", "", "ASTAT", "RETS", + "", "", "", "", "", "", "", "", + "LC0", "LT0", "LB0", "LC1", "LT1", "LB1", "CYCLES", "CYCLES2", + "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT", +}; + +const char * +get_allreg_name(int grp, int reg) +{ + return greg_names[(grp << 3) | reg]; +} + +static TCGv * const cpu_regs[] = { + &cpu_dreg[0], &cpu_dreg[1], &cpu_dreg[2], &cpu_dreg[3], + &cpu_dreg[4], &cpu_dreg[5], &cpu_dreg[6], &cpu_dreg[7], + &cpu_preg[0], &cpu_preg[1], &cpu_preg[2], &cpu_preg[3], + &cpu_preg[4], &cpu_preg[5], &cpu_preg[6], &cpu_preg[7], + &cpu_ireg[0], &cpu_ireg[1], &cpu_ireg[2], &cpu_ireg[3], + &cpu_mreg[0], &cpu_mreg[1], &cpu_mreg[2], &cpu_mreg[3], + &cpu_breg[0], &cpu_breg[1], &cpu_breg[2], &cpu_breg[3], + &cpu_lreg[0], &cpu_lreg[1], &cpu_lreg[2], &cpu_lreg[3], + NULL, NULL, NULL, NULL, NULL, NULL, NULL, &cpu_rets, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + &cpu_lcreg[0], &cpu_ltreg[0], &cpu_lbreg[0], &cpu_lcreg[1], + &cpu_ltreg[1], &cpu_lbreg[1], &cpu_cycles[0], &cpu_cycles[1], + &cpu_uspreg, &cpu_seqstat, &cpu_syscfg, &cpu_reti, + &cpu_retx, &cpu_retn, &cpu_rete, &cpu_emudat, +}; + +static TCGv +get_allreg(DisasContext *dc, int grp, int reg) +{ + TCGv *ret = cpu_regs[(grp << 3) | reg]; + if (ret) { + return *ret; + } + /* We need to update all the callers to handle a NULL return. + Use abort here so that we don't chase down random crashes. */ + abort(); + illegal_instruction(dc); +} + +static void +reg_check_sup(DisasContext *dc, int grp, int reg) +{ + if (grp == 7) { + cec_require_supervisor(dc); + } +} + +#define gen_unextend_acc(acc) tcg_gen_andi_i64(acc, acc, 0xffffffffffull) +#define gen_extend_acc(acc) gen_extNsi_i64(acc, acc, 40) + +/* Perform a multiplication of D registers SRC0 and SRC1, sign- or + zero-extending the result to 64 bit. H0 and H1 determine whether the + high part or the low part of the source registers is used. Store 1 in + *PSAT if saturation occurs, 0 otherwise. */ +static TCGv +decode_multfunc_tl(DisasContext *dc, int h0, int h1, int src0, int src1, + int mmod, int MM, TCGv psat) +{ + TCGv s0, s1, val; + + s0 = tcg_temp_local_new(); + if (h0) { + tcg_gen_shri_tl(s0, cpu_dreg[src0], 16); + } else { + tcg_gen_andi_tl(s0, cpu_dreg[src0], 0xffff); + } + + s1 = tcg_temp_local_new(); + if (h1) { + tcg_gen_shri_tl(s1, cpu_dreg[src1], 16); + } else { + tcg_gen_andi_tl(s1, cpu_dreg[src1], 0xffff); + } + + if (MM) { + tcg_gen_ext16s_tl(s0, s0); + } else { + switch (mmod) { + case 0: + case M_S2RND: + case M_T: + case M_IS: + case M_ISS2: + case M_IH: + case M_W32: + tcg_gen_ext16s_tl(s0, s0); + tcg_gen_ext16s_tl(s1, s1); + break; + case M_FU: + case M_IU: + case M_TFU: + break; + default: + illegal_instruction(dc); + } + } + + val = tcg_temp_local_new(); + tcg_gen_mul_tl(val, s0, s1); + tcg_temp_free(s0); + tcg_temp_free(s1); + + /* Perform shift correction if appropriate for the mode. */ + tcg_gen_movi_tl(psat, 0); + if (!MM && (mmod == 0 || mmod == M_T || mmod == M_S2RND || mmod == M_W32)) { + TCGLabel *l, *endl; + + l = gen_new_label(); + endl = gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_NE, val, 0x40000000, l); + if (mmod == M_W32) { + tcg_gen_movi_tl(val, 0x7fffffff); + } else { + tcg_gen_movi_tl(val, 0x80000000); + } + tcg_gen_movi_tl(psat, 1); + tcg_gen_br(endl); + + gen_set_label(l); + tcg_gen_shli_tl(val, val, 1); + + gen_set_label(endl); + } + + return val; +} + +static TCGv_i64 +decode_multfunc_i64(DisasContext *dc, int h0, int h1, int src0, int src1, + int mmod, int MM, TCGv psat) +{ + TCGv val; + TCGv_i64 val1; + TCGLabel *l; + + val = decode_multfunc_tl(dc, h0, h1, src0, src1, mmod, MM, psat); + val1 = tcg_temp_local_new_i64(); + tcg_gen_extu_i32_i64(val1, val); + tcg_temp_free(val); + + if (mmod == 0 || mmod == M_IS || mmod == M_T || mmod == M_S2RND || + mmod == M_ISS2 || mmod == M_IH || (MM && mmod == M_FU)) { + gen_extNsi_i64(val1, val1, 40); + } + + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, psat, 0, l); + tcg_gen_ext32u_i64(val1, val1); + gen_set_label(l); + + return val1; +} + +static void +saturate_s32(TCGv_i64 val, TCGv overflow) +{ + TCGLabel *l, *endl; + + endl = gen_new_label(); + + l = gen_new_label(); + tcg_gen_brcondi_i64(TCG_COND_GE, val, -0x80000000ll, l); + tcg_gen_movi_tl(overflow, 1); + tcg_gen_movi_i64(val, 0x80000000); + tcg_gen_br(endl); + gen_set_label(l); + + l = gen_new_label(); + tcg_gen_brcondi_i64(TCG_COND_LE, val, 0x7fffffff, l); + tcg_gen_movi_tl(overflow, 1); + tcg_gen_movi_i64(val, 0x7fffffff); + gen_set_label(l); + + gen_set_label(endl); +} + +static TCGv +decode_macfunc(DisasContext *dc, int which, int op, int h0, int h1, int src0, + int src1, int mmod, int MM, int fullword, int *overflow) +{ + /* XXX: Very incomplete. */ + TCGv_i64 acc; + + if (mmod == 0 || mmod == M_T || mmod == M_IS || mmod == M_ISS2 || + mmod == M_S2RND || mmod == M_IH || mmod == M_W32) { + gen_extend_acc(cpu_areg[which]); + } else { + gen_unextend_acc(cpu_areg[which]); + } + acc = cpu_areg[which]; + + if (op != 3) { + /* this can't saturate, so we don't keep track of the sat flag */ + TCGv tsat = tcg_temp_local_new();; + TCGv_i64 res = decode_multfunc_i64(dc, h0, h1, src0, src1, mmod, MM, + tsat); + tcg_temp_free(tsat); + + /* Perform accumulation. */ + switch (op) { + case 0: + tcg_gen_mov_i64(acc, res); + break; + case 1: + tcg_gen_add_i64(acc, acc, res); + break; + case 2: + tcg_gen_sub_i64(acc, acc, res); + break; + } + tcg_temp_free_i64(res); + + /* XXX: Saturate. */ + } + + TCGv tmp = tcg_temp_local_new(); + tcg_gen_extrl_i64_i32(tmp, acc); + return tmp; +} + +static void +decode_ProgCtrl_0(DisasContext *dc, uint16_t iw0) +{ + /* ProgCtrl + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask); + int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask); + + TRACE_EXTRACT("poprnd:%i prgfunc:%i", poprnd, prgfunc); + + if (prgfunc == 0 && poprnd == 0) { + /* NOP */; + } else if (prgfunc == 1 && poprnd == 0) { + /* RTS; */ + dc->is_jmp = DISAS_JUMP; + dc->hwloop_callback = gen_hwloop_br_direct; + dc->hwloop_data = &cpu_rets; + } else if (prgfunc == 1 && poprnd == 1) { + /* RTI; */ + cec_require_supervisor(dc); + } else if (prgfunc == 1 && poprnd == 2) { + /* RTX; */ + cec_require_supervisor(dc); + } else if (prgfunc == 1 && poprnd == 3) { + /* RTN; */ + cec_require_supervisor(dc); + } else if (prgfunc == 1 && poprnd == 4) { + /* RTE; */ + cec_require_supervisor(dc); + } else if (prgfunc == 2 && poprnd == 0) { + /* IDLE; */ + /* just NOP it */; + } else if (prgfunc == 2 && poprnd == 3) { + /* CSYNC; */ + /* just NOP it */; + } else if (prgfunc == 2 && poprnd == 4) { + /* SSYNC; */ + /* just NOP it */; + } else if (prgfunc == 2 && poprnd == 5) { + /* EMUEXCPT; */ + cec_exception(dc, EXCP_DEBUG); + } else if (prgfunc == 3 && poprnd < 8) { + /* CLI Dreg{poprnd}; */ + cec_require_supervisor(dc); + } else if (prgfunc == 4 && poprnd < 8) { + /* STI Dreg{poprnd}; */ + cec_require_supervisor(dc); + } else if (prgfunc == 5 && poprnd < 8) { + /* JUMP (Preg{poprnd}); */ + dc->is_jmp = DISAS_JUMP; + dc->hwloop_callback = gen_hwloop_br_direct; + dc->hwloop_data = &cpu_preg[poprnd]; + } else if (prgfunc == 6 && poprnd < 8) { + /* CALL (Preg{poprnd}); */ + dc->is_jmp = DISAS_CALL; + dc->hwloop_callback = gen_hwloop_br_direct; + dc->hwloop_data = &cpu_preg[poprnd]; + } else if (prgfunc == 7 && poprnd < 8) { + /* CALL (PC + Preg{poprnd}); */ + dc->is_jmp = DISAS_CALL; + dc->hwloop_callback = gen_hwloop_br_pcrel; + dc->hwloop_data = &cpu_preg[poprnd]; + } else if (prgfunc == 8 && poprnd < 8) { + /* JUMP (PC + Preg{poprnd}); */ + dc->is_jmp = DISAS_JUMP; + dc->hwloop_callback = gen_hwloop_br_pcrel; + dc->hwloop_data = &cpu_preg[poprnd]; + } else if (prgfunc == 9) { + /* RAISE imm{poprnd}; */ + /* int raise = uimm4 (poprnd); */ + cec_require_supervisor(dc); + } else if (prgfunc == 10) { + /* EXCPT imm{poprnd}; */ + int excpt = uimm4(poprnd); + cec_exception(dc, excpt); + } else if (prgfunc == 11 && poprnd < 6) { + /* TESTSET (Preg{poprnd}); */ + /* Note: This is isn't really atomic. But that's OK because the + * hardware itself can't be relied upon. It doesn't work with cached + * memory (which Linux always runs under), and has some anomalies + * which prevents it from working even with on-chip memory. As such, + * we'll just do a "stupid" implementation here. */ + TCGv tmp = tcg_temp_new(); + tcg_gen_qemu_ld8u(tmp, cpu_preg[poprnd], dc->mem_idx); + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_cc, tmp, 0); + tcg_gen_ori_tl(tmp, tmp, 0x80); + tcg_gen_qemu_st8(tmp, cpu_preg[poprnd], dc->mem_idx); + tcg_temp_free(tmp); + } else { + illegal_instruction(dc); + } +} + +static void +decode_CaCTRL_0(DisasContext *dc, uint16_t iw0) +{ + /* CaCTRL + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask); + int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask); + int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask); + + TRACE_EXTRACT("a:%i op:%i reg:%i", a, op, reg); + + /* + * PREFETCH [Preg{reg}]; + * PREFETCH [Preg{reg}++{a}]; + * FLUSHINV [Preg{reg}]; + * FLUSHINV [Preg{reg}++{a}]; + * FLUSH [Preg{reg}]; + * FLUSH [Preg{reg}++{a}]; + * IFLUSH [Preg{reg}]; + * IFLUSH [Preg{reg}++{a}]; + */ + + /* No cache simulation, and we'll ignore the implicit CPLB aspects */ + + if (a) { + tcg_gen_addi_tl(cpu_preg[reg], cpu_preg[reg], BFIN_L1_CACHE_BYTES); + } +} + +static void +decode_PushPopReg_0(DisasContext *dc, uint16_t iw0) +{ + /* PushPopReg + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask); + int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask); + int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask); + TCGv treg = 0, tmp; + TCGv_i64 tmp64; + + TRACE_EXTRACT("W:%i grp:%i reg:%i", W, grp, reg); + + reg_check_sup(dc, grp, reg); + + /* Everything here needs to be aligned, so check once */ + gen_align_check(dc, cpu_spreg, 4, false); + + if (W == 0) { + /* Dreg and Preg are not supported by this instruction */ + if (grp == 0 || grp == 1) { + illegal_instruction(dc); + } + + /* genreg{grp,reg} [SP++]; */ + if (grp == 4 && reg == 6) { + /* Pop ASTAT */ + tmp = tcg_temp_new(); + tcg_gen_qemu_ld32u(tmp, cpu_spreg, dc->mem_idx); + gen_astat_store(dc, tmp); + tcg_temp_free(tmp); + } else if (grp == 4 && (reg == 0 || reg == 2)) { + /* Pop A#.X */ + tmp = tcg_temp_new(); + tcg_gen_qemu_ld8u(tmp, cpu_spreg, dc->mem_idx); + tmp64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(tmp64, tmp); + tcg_temp_free(tmp); + + tcg_gen_deposit_i64(cpu_areg[reg >> 1], cpu_areg[reg >> 1], + tmp64, 32, 32); + tcg_temp_free_i64(tmp64); + } else if (grp == 4 && (reg == 1 || reg == 3)) { + /* Pop A#.W */ + tmp = tcg_temp_new(); + tcg_gen_qemu_ld32u(tmp, cpu_spreg, dc->mem_idx); + tmp64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(tmp64, tmp); + tcg_temp_free(tmp); + + tcg_gen_deposit_i64(cpu_areg[reg >> 1], cpu_areg[reg >> 1], + tmp64, 0, 32); + tcg_temp_free_i64(tmp64); + } else { + treg = get_allreg(dc, grp, reg); + tcg_gen_qemu_ld32u(treg, cpu_spreg, dc->mem_idx); + + if (grp == 6 && (reg == 1 || reg == 4)) { + /* LT loads auto clear the LSB */ + tcg_gen_andi_tl(treg, treg, ~1); + } + } + + /* Delay the SP update till the end in case an exception occurs. */ + tcg_gen_addi_tl(cpu_spreg, cpu_spreg, 4); + gen_maybe_lb_exit_tb(dc, treg); + } else { + /* [--SP] = genreg{grp,reg}; */ + TCGv tmp_sp; + + /* Delay the SP update till the end in case an exception occurs. */ + tmp_sp = tcg_temp_new(); + tcg_gen_subi_tl(tmp_sp, cpu_spreg, 4); + if (grp == 4 && reg == 6) { + /* Push ASTAT */ + tmp = tcg_temp_new(); + gen_astat_load(dc, tmp); + tcg_gen_qemu_st32(tmp, tmp_sp, dc->mem_idx); + tcg_temp_free(tmp); + } else if (grp == 4 && (reg == 0 || reg == 2)) { + /* Push A#.X */ + tmp64 = tcg_temp_new_i64(); + tcg_gen_shri_i64(tmp64, cpu_areg[reg >> 1], 32); + tmp = tcg_temp_new(); + tcg_gen_extrl_i64_i32(tmp, tmp64); + tcg_temp_free_i64(tmp64); + /* A# is a 40 bit reg and A#.X refers to the top 8 bits. But we + * don't always mask out the top 24 bits during operations because + * we're lazy during intermediate operations (like maintaining the + * sign bit). */ + tcg_gen_andi_tl(tmp, tmp, 0xff); + tcg_gen_qemu_st32(tmp, tmp_sp, dc->mem_idx); + tcg_temp_free(tmp); + } else if (grp == 4 && (reg == 1 || reg == 3)) { + /* Push A#.W */ + tmp = tcg_temp_new(); + tcg_gen_extrl_i64_i32(tmp, cpu_areg[reg >> 1]); + tcg_gen_qemu_st32(tmp, tmp_sp, dc->mem_idx); + tcg_temp_free(tmp); + } else { + treg = get_allreg(dc, grp, reg); + tcg_gen_qemu_st32(treg, tmp_sp, dc->mem_idx); + } + tcg_gen_mov_tl(cpu_spreg, tmp_sp); + tcg_temp_free(tmp_sp); + } +} + +static void +decode_PushPopMultiple_0(DisasContext *dc, uint16_t iw0) +{ + /* PushPopMultiple + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask); + int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask); + int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask); + int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask); + int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask); + int i; + TCGv tmp_sp; + + TRACE_EXTRACT("d:%i p:%i W:%i dr:%i pr:%i", d, p, W, dr, pr); + + if ((d == 0 && p == 0) || (p && imm5(pr) > 5) || + (d && !p && pr) || (p && !d && dr)) { + illegal_instruction(dc); + } + + /* Everything here needs to be aligned, so check once */ + gen_align_check(dc, cpu_spreg, 4, false); + + /* Delay the SP update till the end in case an exception occurs. */ + tmp_sp = tcg_temp_new(); + tcg_gen_mov_tl(tmp_sp, cpu_spreg); + if (W == 1) { + /* [--SP] = ({d}R7:imm{dr}, {p}P5:imm{pr}); */ + if (d) { + for (i = dr; i < 8; i++) { + tcg_gen_subi_tl(tmp_sp, tmp_sp, 4); + tcg_gen_qemu_st32(cpu_dreg[i], tmp_sp, dc->mem_idx); + } + } + if (p) { + for (i = pr; i < 6; i++) { + tcg_gen_subi_tl(tmp_sp, tmp_sp, 4); + tcg_gen_qemu_st32(cpu_preg[i], tmp_sp, dc->mem_idx); + } + } + } else { + /* ({d}R7:imm{dr}, {p}P5:imm{pr}) = [SP++]; */ + if (p) { + for (i = 5; i >= pr; i--) { + tcg_gen_qemu_ld32u(cpu_preg[i], tmp_sp, dc->mem_idx); + tcg_gen_addi_tl(tmp_sp, tmp_sp, 4); + } + } + if (d) { + for (i = 7; i >= dr; i--) { + tcg_gen_qemu_ld32u(cpu_dreg[i], tmp_sp, dc->mem_idx); + tcg_gen_addi_tl(tmp_sp, tmp_sp, 4); + } + } + } + tcg_gen_mov_tl(cpu_spreg, tmp_sp); + tcg_temp_free(tmp_sp); +} + +static void +decode_ccMV_0(DisasContext *dc, uint16_t iw0) +{ + /* ccMV + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask); + int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask); + int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask); + int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask); + int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask); + TCGv tmp, reg_src, reg_dst; + + TRACE_EXTRACT("T:%i d:%i s:%i dst:%i src:%i", + T, d, s, dst, src); + + /* IF !{T} CC DPreg{d,dst} = DPreg{s,src}; */ + reg_src = get_allreg(dc, s, src); + reg_dst = get_allreg(dc, d, dst); + tmp = tcg_const_tl(T); + tcg_gen_movcond_tl(TCG_COND_EQ, reg_dst, cpu_cc, tmp, reg_src, reg_dst); + tcg_temp_free(tmp); +} + +static void +decode_CCflag_0(DisasContext *dc, uint16_t iw0) +{ + /* CCflag + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask); + int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask); + int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask); + int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask); + int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask); + + TRACE_EXTRACT("I:%i opc:%i G:%i y:%i x:%i", + I, opc, G, y, x); + + if (opc > 4) { + TCGv_i64 tmp64; + TCGCond cond = 0; + + if (opc == 5 && I == 0 && G == 0) { + /* CC = A0 == A1; */ + cond = TCG_COND_EQ; + } else if (opc == 6 && I == 0 && G == 0) { + /* CC = A0 < A1; */ + cond = TCG_COND_LT; + } else if (opc == 7 && I == 0 && G == 0) { + /* CC = A0 <= A1; */ + cond = TCG_COND_LE; + } else { + illegal_instruction(dc); + } + + tmp64 = tcg_temp_new_i64(); + tcg_gen_setcond_i64(cond, tmp64, cpu_areg[0], cpu_areg[1]); + tcg_gen_extrl_i64_i32(cpu_cc, tmp64); + tcg_temp_free_i64(tmp64); + } else { + int issigned = opc < 3; + uint32_t dst_imm = issigned ? imm3(y) : uimm3(y); + TCGv src_reg = G ? cpu_preg[x] : cpu_dreg[x]; + TCGv dst_reg = G ? cpu_preg[y] : cpu_dreg[y]; + TCGv tmp; + TCGCond cond; + enum astat_ops astat_op; + + switch (opc) { + default: /* shutup useless gcc warnings */ + case 0: /* signed == */ + cond = TCG_COND_EQ; + break; + case 1: /* signed < */ + cond = TCG_COND_LT; + break; + case 2: /* signed <= */ + cond = TCG_COND_LE; + break; + case 3: /* unsigned < */ + cond = TCG_COND_LTU; + break; + case 4: /* unsigned <= */ + cond = TCG_COND_LEU; + break; + } + if (issigned) { + astat_op = ASTAT_OP_COMPARE_SIGNED; + } else { + astat_op = ASTAT_OP_COMPARE_UNSIGNED; + } + + if (I) { + /* Compare to an immediate rather than a reg */ + tmp = tcg_const_tl(dst_imm); + dst_reg = tmp; + } + tcg_gen_setcond_tl(cond, cpu_cc, src_reg, dst_reg); + + /* Pointer compares only touch CC. */ + if (!G) { + astat_queue_state2(dc, astat_op, src_reg, dst_reg); + } + + if (I) { + tcg_temp_free(tmp); + } + } +} + +static void +decode_CC2dreg_0(DisasContext *dc, uint16_t iw0) +{ + /* CC2dreg + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask); + int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask); + + TRACE_EXTRACT("op:%i reg:%i", op, reg); + + if (op == 0) { + /* Dreg{reg} = CC; */ + tcg_gen_mov_tl(cpu_dreg[reg], cpu_cc); + } else if (op == 1) { + /* CC = Dreg{reg}; */ + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_cc, cpu_dreg[reg], 0); + } else if (op == 3 && reg == 0) { + /* CC = !CC; */ + tcg_gen_xori_tl(cpu_cc, cpu_cc, 1); + } else { + illegal_instruction(dc); + } +} + +static void +decode_CC2stat_0(DisasContext *dc, uint16_t iw0) +{ + /* CC2stat + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask); + int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask); + int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask); + TCGv tmp; + + TRACE_EXTRACT("D:%i op:%i cbit:%i", D, op, cbit); + + /* CC = CC; is invalid. */ + if (cbit == 5) { + illegal_instruction(dc); + } + + gen_astat_update(dc, true); + + if (D == 0) { + switch (op) { + case 0: /* CC = ASTAT[cbit] */ + tcg_gen_ld_tl(cpu_cc, cpu_env, offsetof(CPUArchState, astat[cbit])); + break; + case 1: /* CC |= ASTAT[cbit] */ + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUArchState, astat[cbit])); + tcg_gen_or_tl(cpu_cc, cpu_cc, tmp); + tcg_temp_free(tmp); + break; + case 2: /* CC &= ASTAT[cbit] */ + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUArchState, astat[cbit])); + tcg_gen_and_tl(cpu_cc, cpu_cc, tmp); + tcg_temp_free(tmp); + break; + case 3: /* CC ^= ASTAT[cbit] */ + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUArchState, astat[cbit])); + tcg_gen_xor_tl(cpu_cc, cpu_cc, tmp); + tcg_temp_free(tmp); + break; + } + } else { + switch (op) { + case 0: /* ASTAT[cbit] = CC */ + tcg_gen_st_tl(cpu_cc, cpu_env, offsetof(CPUArchState, astat[cbit])); + break; + case 1: /* ASTAT[cbit] |= CC */ + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUArchState, astat[cbit])); + tcg_gen_or_tl(tmp, tmp, cpu_cc); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUArchState, astat[cbit])); + tcg_temp_free(tmp); + break; + case 2: /* ASTAT[cbit] &= CC */ + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUArchState, astat[cbit])); + tcg_gen_and_tl(tmp, tmp, cpu_cc); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUArchState, astat[cbit])); + tcg_temp_free(tmp); + break; + case 3: /* ASTAT[cbit] ^= CC */ + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUArchState, astat[cbit])); + tcg_gen_xor_tl(tmp, tmp, cpu_cc); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUArchState, astat[cbit])); + tcg_temp_free(tmp); + break; + } + } +} + +static void +decode_BRCC_0(DisasContext *dc, uint16_t iw0) +{ + /* BRCC + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask); + int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask); + int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask); + int pcrel = pcrel10(offset); + + TRACE_EXTRACT("T:%i B:%i offset:%#x", T, B, offset); + + /* IF !{T} CC JUMP imm{offset} (bp){B}; */ + dc->hwloop_callback = gen_hwloop_br_pcrel_cc; + dc->hwloop_data = (void *)(unsigned long)(pcrel | T); +} + +static void +decode_UJUMP_0(DisasContext *dc, uint16_t iw0) +{ + /* UJUMP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 1 | 0 |.offset........................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask); + int pcrel = pcrel12(offset); + + TRACE_EXTRACT("offset:%#x", offset); + + /* JUMP.S imm{offset}; */ + dc->is_jmp = DISAS_JUMP; + dc->hwloop_callback = gen_hwloop_br_pcrel_imm; + dc->hwloop_data = (void *)(unsigned long)pcrel; +} + +static void +decode_REGMV_0(DisasContext *dc, uint16_t iw0) +{ + /* REGMV + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask); + int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask); + int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask); + int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask); + TCGv reg_src, reg_dst, tmp; + TCGv_i64 tmp64; + bool istmp; + + TRACE_EXTRACT("gd:%i gs:%i dst:%i src:%i", + gd, gs, dst, src); + + /* genreg{gd,dst} = genreg{gs,src}; */ + + reg_check_sup(dc, gs, src); + reg_check_sup(dc, gd, dst); + + if (gs == 4 && src == 6) { + /* Reads of ASTAT */ + tmp = tcg_temp_new(); + gen_astat_load(dc, tmp); + reg_src = tmp; + istmp = true; + } else if (gs == 4 && (src == 0 || src == 2)) { + /* Reads of A#.X */ + tmp = tcg_temp_new(); + tmp64 = tcg_temp_new_i64(); + tcg_gen_shri_i64(tmp64, cpu_areg[src >> 1], 32); + tcg_gen_extrl_i64_i32(tmp, tmp64); + tcg_temp_free_i64(tmp64); + tcg_gen_ext8s_tl(tmp, tmp); + reg_src = tmp; + istmp = true; + } else if (gs == 4 && (src == 1 || src == 3)) { + /* Reads of A#.W */ + tmp = tcg_temp_new(); + tcg_gen_extrl_i64_i32(tmp, cpu_areg[src >> 1]); + reg_src = tmp; + istmp = true; + } else if (gs == 6 && src == 6) { + /* Reads of CYCLES cascades changes w/CYCLES2. */ + tmp = tcg_temp_new(); + gen_helper_cycles_read(tmp, cpu_env); + reg_src = tmp; + istmp = true; + } else { + reg_src = get_allreg(dc, gs, src); + istmp = false; + } + + if (gd == 4 && dst == 6) { + /* Writes to ASTAT */ + gen_astat_store(dc, reg_src); + } else if (gd == 4 && (dst == 0 || dst == 2)) { + /* Writes to A#.X */ + tmp64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(tmp64, reg_src); + tcg_gen_deposit_i64(cpu_areg[dst >> 1], cpu_areg[dst >> 1], tmp64, + 32, 8); + tcg_temp_free_i64(tmp64); + } else if (gd == 4 && (dst == 1 || dst == 3)) { + /* Writes to A#.W */ + tcg_gen_andi_i64(cpu_areg[dst >> 1], cpu_areg[dst >> 1], 0xff00000000); + tmp64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(tmp64, reg_src); + tcg_gen_or_i64(cpu_areg[dst >> 1], cpu_areg[dst >> 1], tmp64); + tcg_temp_free_i64(tmp64); + } else if (gd == 6 && (dst == 1 || dst == 4)) { + /* Writes to LT# */ + /* LT loads auto clear the LSB */ + tcg_gen_andi_tl(cpu_ltreg[dst >> 2], reg_src, ~1); + } else { + reg_dst = get_allreg(dc, gd, dst); + tcg_gen_mov_tl(reg_dst, reg_src); + gen_maybe_lb_exit_tb(dc, reg_dst); + } + + if (istmp) { + tcg_temp_free(tmp); + } +} + +static void +decode_ALU2op_0(DisasContext *dc, uint16_t iw0) +{ + /* ALU2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask); + int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask); + int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask); + TCGLabel *l; + TCGv tmp; + + TRACE_EXTRACT("opc:%i src:%i dst:%i", opc, src, dst); + + if (opc == 0) { + /* Dreg{dst} >>>= Dreg{src}; */ + tmp = tcg_temp_local_new(); + + /* Clip the shift magnitude to 31 bits */ + tcg_gen_movi_tl(tmp, 31); + tcg_gen_movcond_tl(TCG_COND_LTU, tmp, cpu_dreg[src], tmp, cpu_dreg[src], tmp); + + tcg_gen_sar_tl(cpu_dreg[dst], cpu_dreg[dst], tmp); + + tcg_temp_free(tmp); + + astat_queue_state1(dc, ASTAT_OP_LSHIFT_RT32, cpu_dreg[dst]); + } else if (opc == 1) { + /* Dreg{dst} >>= Dreg{src}; */ + l = gen_new_label(); + tmp = tcg_temp_local_new(); + + /* Clip the shift magnitude to 31 bits */ + tcg_gen_mov_tl(tmp, cpu_dreg[src]); + tcg_gen_brcondi_tl(TCG_COND_LEU, tmp, 31, l); + tcg_gen_movi_tl(tmp, 0); + tcg_gen_mov_tl(cpu_dreg[dst], tmp); + gen_set_label(l); + + tcg_gen_shr_tl(cpu_dreg[dst], cpu_dreg[dst], tmp); + + tcg_temp_free(tmp); + + astat_queue_state1(dc, ASTAT_OP_LSHIFT_RT32, cpu_dreg[dst]); + } else if (opc == 2) { + /* Dreg{dst} <<= Dreg{src}; */ + l = gen_new_label(); + tmp = tcg_temp_local_new(); + + /* Clip the shift magnitude to 31 bits */ + tcg_gen_mov_tl(tmp, cpu_dreg[src]); + tcg_gen_brcondi_tl(TCG_COND_LEU, tmp, 31, l); + tcg_gen_movi_tl(tmp, 0); + tcg_gen_mov_tl(cpu_dreg[dst], tmp); + gen_set_label(l); + + tcg_gen_shl_tl(cpu_dreg[dst], cpu_dreg[dst], tmp); + + tcg_temp_free(tmp); + + astat_queue_state1(dc, ASTAT_OP_LSHIFT32, cpu_dreg[dst]); + } else if (opc == 3) { + /* Dreg{dst} *= Dreg{src}; */ + tcg_gen_mul_tl(cpu_dreg[dst], cpu_dreg[dst], cpu_dreg[src]); + } else if (opc == 4 || opc == 5) { + /* Dreg{dst} = (Dreg{dst} + Dreg{src}) << imm{opc}; */ + tcg_gen_add_tl(cpu_dreg[dst], cpu_dreg[dst], cpu_dreg[src]); + tcg_gen_shli_tl(cpu_dreg[dst], cpu_dreg[dst], (opc - 3)); + astat_queue_state1(dc, ASTAT_OP_LSHIFT32, cpu_dreg[dst]); + } else if (opc == 8) { + /* DIVQ (Dreg, Dreg); */ + gen_divq(cpu_dreg[dst], cpu_dreg[src]); + } else if (opc == 9) { + /* DIVS (Dreg, Dreg); */ + gen_divs(cpu_dreg[dst], cpu_dreg[src]); + } else if (opc == 10) { + /* Dreg{dst} = Dreg_lo{src} (X); */ + tcg_gen_ext16s_tl(cpu_dreg[dst], cpu_dreg[src]); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } else if (opc == 11) { + /* Dreg{dst} = Dreg_lo{src} (Z); */ + tcg_gen_ext16u_tl(cpu_dreg[dst], cpu_dreg[src]); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } else if (opc == 12) { + /* Dreg{dst} = Dreg_byte{src} (X); */ + tcg_gen_ext8s_tl(cpu_dreg[dst], cpu_dreg[src]); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } else if (opc == 13) { + /* Dreg{dst} = Dreg_byte{src} (Z); */ + tcg_gen_ext8u_tl(cpu_dreg[dst], cpu_dreg[src]); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } else if (opc == 14) { + /* Dreg{dst} = -Dreg{src}; */ + /* XXX: Documentation isn't entirely clear about av0 and av1. */ + tcg_gen_neg_tl(cpu_dreg[dst], cpu_dreg[src]); + astat_queue_state1(dc, ASTAT_OP_NEGATE, cpu_dreg[dst]); + } else if (opc == 15) { + /* Dreg = ~Dreg; */ + tcg_gen_not_tl(cpu_dreg[dst], cpu_dreg[src]); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } +} + +static void +decode_PTR2op_0(DisasContext *dc, uint16_t iw0) +{ + /* PTR2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask); + int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask); + int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask); + + TRACE_EXTRACT("opc:%i src:%i dst:%i", opc, src, dst); + + if (opc == 0) { + /* Preg{dst} -= Preg{src}; */ + tcg_gen_sub_tl(cpu_preg[dst], cpu_preg[dst], cpu_preg[src]); + } else if (opc == 1) { + /* Preg{dst} = Preg{src} << 2; */ + tcg_gen_shli_tl(cpu_preg[dst], cpu_preg[src], 2); + } else if (opc == 3) { + /* Preg{dst} = Preg{src} >> 2; */ + tcg_gen_shri_tl(cpu_preg[dst], cpu_preg[src], 2); + } else if (opc == 4) { + /* Preg{dst} = Preg{src} >> 1; */ + tcg_gen_shri_tl(cpu_preg[dst], cpu_preg[src], 1); + } else if (opc == 5) { + /* Preg{dst} += Preg{src} (BREV); */ + gen_helper_add_brev(cpu_preg[dst], cpu_preg[dst], cpu_preg[src]); + } else { /*(opc == 6 || opc == 7)*/ + /* Preg{dst} = (Preg{dst} + Preg{src}) << imm{opc}; */ + tcg_gen_add_tl(cpu_preg[dst], cpu_preg[dst], cpu_preg[src]); + tcg_gen_shli_tl(cpu_preg[dst], cpu_preg[dst], (opc - 5)); + } +} + +static void +decode_LOGI2op_0(DisasContext *dc, uint16_t iw0) +{ + /* LOGI2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask); + int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask); + int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask); + int uimm = uimm5(src); + + TRACE_EXTRACT("opc:%i src:%i dst:%i", opc, src, dst); + + if (opc == 0) { + /* CC = ! BITTST (Dreg{dst}, imm{uimm}); */ + tcg_gen_shri_tl(cpu_cc, cpu_dreg[dst], uimm); + tcg_gen_not_tl(cpu_cc, cpu_cc); + tcg_gen_andi_tl(cpu_cc, cpu_cc, 1); + } else if (opc == 1) { + /* CC = BITTST (Dreg{dst}, imm{uimm}); */ + tcg_gen_shri_tl(cpu_cc, cpu_dreg[dst], uimm); + tcg_gen_andi_tl(cpu_cc, cpu_cc, 1); + } else if (opc == 2) { + /* BITSET (Dreg{dst}, imm{uimm}); */ + tcg_gen_ori_tl(cpu_dreg[dst], cpu_dreg[dst], 1 << uimm); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } else if (opc == 3) { + /* BITTGL (Dreg{dst}, imm{uimm}); */ + tcg_gen_xori_tl(cpu_dreg[dst], cpu_dreg[dst], 1 << uimm); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } else if (opc == 4) { + /* BITCLR (Dreg{dst}, imm{uimm}); */ + tcg_gen_andi_tl(cpu_dreg[dst], cpu_dreg[dst], ~(1 << uimm)); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } else if (opc == 5) { + /* Dreg{dst} >>>= imm{uimm}; */ + tcg_gen_sari_tl(cpu_dreg[dst], cpu_dreg[dst], uimm); + astat_queue_state1(dc, ASTAT_OP_LSHIFT_RT32, cpu_dreg[dst]); + } else if (opc == 6) { + /* Dreg{dst} >>= imm{uimm}; */ + tcg_gen_shri_tl(cpu_dreg[dst], cpu_dreg[dst], uimm); + astat_queue_state1(dc, ASTAT_OP_LSHIFT_RT32, cpu_dreg[dst]); + } else { /*(opc == 7)*/ + /* Dreg{dst} <<= imm{uimm}; */ + tcg_gen_shli_tl(cpu_dreg[dst], cpu_dreg[dst], uimm); + astat_queue_state1(dc, ASTAT_OP_LSHIFT32, cpu_dreg[dst]); + } +} + +static void +decode_COMP3op_0(DisasContext *dc, uint16_t iw0) +{ + /* COMP3op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask); + int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask); + int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); + int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask); + TCGv tmp; + + TRACE_EXTRACT("opc:%i dst:%i src1:%i src0:%i", + opc, dst, src1, src0); + + tmp = tcg_temp_local_new(); + if (opc == 0) { + /* Dreg{dst} = Dreg{src0} + Dreg{src1}; */ + tcg_gen_add_tl(tmp, cpu_dreg[src0], cpu_dreg[src1]); + astat_queue_state3(dc, ASTAT_OP_ADD32, tmp, cpu_dreg[src0], + cpu_dreg[src1]); + tcg_gen_mov_tl(cpu_dreg[dst], tmp); + } else if (opc == 1) { + /* Dreg{dst} = Dreg{src0} - Dreg{src1}; */ + tcg_gen_sub_tl(tmp, cpu_dreg[src0], cpu_dreg[src1]); + astat_queue_state3(dc, ASTAT_OP_SUB32, tmp, cpu_dreg[src0], + cpu_dreg[src1]); + tcg_gen_mov_tl(cpu_dreg[dst], tmp); + } else if (opc == 2) { + /* Dreg{dst} = Dreg{src0} & Dreg{src1}; */ + tcg_gen_and_tl(cpu_dreg[dst], cpu_dreg[src0], cpu_dreg[src1]); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } else if (opc == 3) { + /* Dreg{dst} = Dreg{src0} | Dreg{src1}; */ + tcg_gen_or_tl(cpu_dreg[dst], cpu_dreg[src0], cpu_dreg[src1]); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } else if (opc == 4) { + /* Dreg{dst} = Dreg{src0} ^ Dreg{src1}; */ + tcg_gen_xor_tl(cpu_dreg[dst], cpu_dreg[src0], cpu_dreg[src1]); + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst]); + } else if (opc == 5) { + /* Preg{dst} = Preg{src0} + Preg{src1}; */ + /* If src0 == src1 this is disassembled as a shift by 1, but this + distinction doesn't matter for our purposes */ + tcg_gen_add_tl(cpu_preg[dst], cpu_preg[src0], cpu_preg[src1]); + } else { /*(opc == 6 || opc == 7)*/ + /* Preg{dst} = Preg{src0} + Preg{src1} << imm{opc}; */ + /* The dst/src0/src1 might all be the same register, so we need + the temp here to avoid clobbering source values too early. + This could be optimized a little, but for now we'll leave it. */ + tcg_gen_shli_tl(tmp, cpu_preg[src1], (opc - 5)); + tcg_gen_add_tl(cpu_preg[dst], cpu_preg[src0], tmp); + } + tcg_temp_free(tmp); +} + +static void +decode_COMPI2opD_0(DisasContext *dc, uint16_t iw0) +{ + /* COMPI2opD + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask); + int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask); + int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask); + int imm = imm7(src); + TCGv tmp; + + TRACE_EXTRACT("op:%i src:%i dst:%i", op, src, dst); + + if (op == 0) { + /* Dreg{dst} = imm{src} (X); */ + tcg_gen_movi_tl(cpu_dreg[dst], imm); + } else { + /* Dreg{dst} += imm{src}; */ + tmp = tcg_const_tl(imm); + tcg_gen_mov_tl(cpu_astat_arg[1], cpu_dreg[dst]); + tcg_gen_add_tl(cpu_dreg[dst], cpu_astat_arg[1], tmp); + astat_queue_state3(dc, ASTAT_OP_ADD32, cpu_dreg[dst], cpu_astat_arg[1], + tmp); + tcg_temp_free(tmp); + } +} + +static void +decode_COMPI2opP_0(DisasContext *dc, uint16_t iw0) +{ + /* COMPI2opP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask); + int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask); + int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask); + int imm = imm7(src); + + TRACE_EXTRACT("op:%i src:%i dst:%i", op, src, dst); + + if (op == 0) { + /* Preg{dst} = imm{src}; */ + tcg_gen_movi_tl(cpu_preg[dst], imm); + } else { + /* Preg{dst} += imm{src}; */ + tcg_gen_addi_tl(cpu_preg[dst], cpu_preg[dst], imm); + } +} + +static void +decode_LDSTpmod_0(DisasContext *dc, uint16_t iw0) +{ + /* LDSTpmod + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask); + int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask); + int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask); + int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask); + int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask); + TCGv tmp; + + TRACE_EXTRACT("W:%i aop:%i reg:%i idx:%i ptr:%i", + W, aop, reg, idx, ptr); + + if (aop == 1 && W == 0 && idx == ptr) { + /* Dreg_lo{reg} = W[Preg{ptr}]; */ + tmp = tcg_temp_local_new(); + gen_aligned_qemu_ld16u(dc, tmp, cpu_preg[ptr]); + tcg_gen_deposit_tl(cpu_dreg[reg], cpu_dreg[reg], tmp, 0, 16); + tcg_temp_free(tmp); + } else if (aop == 2 && W == 0 && idx == ptr) { + /* Dreg_hi{reg} = W[Preg{ptr}]; */ + tmp = tcg_temp_local_new(); + gen_aligned_qemu_ld16u(dc, tmp, cpu_preg[ptr]); + tcg_gen_deposit_tl(cpu_dreg[reg], cpu_dreg[reg], tmp, 16, 16); + tcg_temp_free(tmp); + } else if (aop == 1 && W == 1 && idx == ptr) { + /* W[Preg{ptr}] = Dreg_lo{reg}; */ + gen_aligned_qemu_st16(dc, cpu_dreg[reg], cpu_preg[ptr]); + } else if (aop == 2 && W == 1 && idx == ptr) { + /* W[Preg{ptr}] = Dreg_hi{reg}; */ + tmp = tcg_temp_local_new(); + tcg_gen_shri_tl(tmp, cpu_dreg[reg], 16); + gen_aligned_qemu_st16(dc, tmp, cpu_preg[ptr]); + tcg_temp_free(tmp); + } else if (aop == 0 && W == 0) { + /* Dreg{reg} = [Preg{ptr} ++ Preg{idx}]; */ + gen_aligned_qemu_ld32u(dc, cpu_dreg[reg], cpu_preg[ptr]); + if (ptr != idx) { + tcg_gen_add_tl(cpu_preg[ptr], cpu_preg[ptr], cpu_preg[idx]); + } + } else if (aop == 1 && W == 0) { + /* Dreg_lo{reg} = W[Preg{ptr} ++ Preg{idx}]; */ + tmp = tcg_temp_local_new(); + gen_aligned_qemu_ld16u(dc, tmp, cpu_preg[ptr]); + tcg_gen_deposit_tl(cpu_dreg[reg], cpu_dreg[reg], tmp, 0, 16); + if (ptr != idx) { + tcg_gen_add_tl(cpu_preg[ptr], cpu_preg[ptr], cpu_preg[idx]); + } + tcg_temp_free(tmp); + } else if (aop == 2 && W == 0) { + /* Dreg_hi{reg} = W[Preg{ptr} ++ Preg{idx}]; */ + tmp = tcg_temp_local_new(); + gen_aligned_qemu_ld16u(dc, tmp, cpu_preg[ptr]); + tcg_gen_deposit_tl(cpu_dreg[reg], cpu_dreg[reg], tmp, 16, 16); + if (ptr != idx) { + tcg_gen_add_tl(cpu_preg[ptr], cpu_preg[ptr], cpu_preg[idx]); + } + tcg_temp_free(tmp); + } else if (aop == 3 && W == 0) { + /* R%i = W[Preg{ptr} ++ Preg{idx}] (Z); */ + gen_aligned_qemu_ld16u(dc, cpu_dreg[reg], cpu_preg[ptr]); + if (ptr != idx) { + tcg_gen_add_tl(cpu_preg[ptr], cpu_preg[ptr], cpu_preg[idx]); + } + } else if (aop == 3 && W == 1) { + /* R%i = W[Preg{ptr} ++ Preg{idx}] (X); */ + gen_aligned_qemu_ld16s(dc, cpu_dreg[reg], cpu_preg[ptr]); + if (ptr != idx) { + tcg_gen_add_tl(cpu_preg[ptr], cpu_preg[ptr], cpu_preg[idx]); + } + } else if (aop == 0 && W == 1) { + /* [Preg{ptr} ++ Preg{idx}] = R%i; */ + gen_aligned_qemu_st32(dc, cpu_dreg[reg], cpu_preg[ptr]); + if (ptr != idx) { + tcg_gen_add_tl(cpu_preg[ptr], cpu_preg[ptr], cpu_preg[idx]); + } + } else if (aop == 1 && W == 1) { + /* W[Preg{ptr} ++ Preg{idx}] = Dreg_lo{reg}; */ + gen_aligned_qemu_st16(dc, cpu_dreg[reg], cpu_preg[ptr]); + if (ptr != idx) { + tcg_gen_add_tl(cpu_preg[ptr], cpu_preg[ptr], cpu_preg[idx]); + } + } else if (aop == 2 && W == 1) { + /* W[Preg{ptr} ++ Preg{idx}] = Dreg_hi{reg}; */ + tmp = tcg_temp_local_new(); + tcg_gen_shri_tl(tmp, cpu_dreg[reg], 16); + gen_aligned_qemu_st16(dc, tmp, cpu_preg[ptr]); + if (ptr != idx) { + tcg_gen_add_tl(cpu_preg[ptr], cpu_preg[ptr], cpu_preg[idx]); + } + tcg_temp_free(tmp); + } else { + illegal_instruction(dc); + } +} + +static void +decode_dagMODim_0(DisasContext *dc, uint16_t iw0) +{ + /* dagMODim + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask); + int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask); + int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask); + int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask); + + TRACE_EXTRACT("br:%i op:%i m:%i i:%i", br, op, m, i); + + if (op == 0 && br == 1) { + /* Ireg{i} += Mreg{m} (BREV); */ + gen_helper_add_brev(cpu_ireg[i], cpu_ireg[i], cpu_mreg[m]); + } else if (op == 0) { + /* Ireg{i} += Mreg{m}; */ + gen_dagadd(dc, i, cpu_mreg[m]); + } else if (op == 1 && br == 0) { + /* Ireg{i} -= Mreg{m}; */ + gen_dagsub(dc, i, cpu_mreg[m]); + } else { + illegal_instruction(dc); + } +} + +static void +decode_dagMODik_0(DisasContext *dc, uint16_t iw0) +{ + /* dagMODik + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask); + int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask); + int mod = (op & 2) + 2; + + TRACE_EXTRACT("op:%i i:%i", op, i); + + if (op & 1) { + /* Ireg{i} -= 2 or 4; */ + gen_dagsubi(dc, i, mod); + } else { + /* Ireg{i} += 2 or 4; */ + gen_dagaddi(dc, i, mod); + } +} + +static void +disalgnexcpt_ld32u(DisasContext *dc, TCGv ret, TCGv addr) +{ + if (dc->disalgnexcpt) { + TCGv tmp = tcg_temp_new(); + tcg_gen_andi_tl(tmp, addr, ~0x3); + tcg_gen_qemu_ld32u(ret, tmp, dc->mem_idx); + tcg_temp_free(tmp); + } else { + gen_aligned_qemu_ld32u(dc, ret, addr); + } +} + +static void +decode_dspLDST_0(DisasContext *dc, uint16_t iw0) +{ + /* dspLDST + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask); + int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask); + int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask); + int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask); + int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask); + TCGv tmp; + + TRACE_EXTRACT("aop:%i m:%i i:%i reg:%i", aop, m, i, reg); + + if (aop == 0 && W == 0 && m == 0) { + /* Dreg{reg} = [Ireg{i}++]; */ + disalgnexcpt_ld32u(dc, cpu_dreg[reg], cpu_ireg[i]); + gen_dagaddi(dc, i, 4); + } else if (aop == 0 && W == 0 && m == 1) { + /* Dreg_lo{reg} = W[Ireg{i}++]; */ + tmp = tcg_temp_local_new(); + gen_aligned_qemu_ld16u(dc, tmp, cpu_ireg[i]); + gen_mov_l_tl(cpu_dreg[reg], tmp); + tcg_temp_free(tmp); + gen_dagaddi(dc, i, 2); + } else if (aop == 0 && W == 0 && m == 2) { + /* Dreg_hi{reg} = W[Ireg{i}++]; */ + tmp = tcg_temp_local_new(); + gen_aligned_qemu_ld16u(dc, tmp, cpu_ireg[i]); + gen_mov_h_tl(cpu_dreg[reg], tmp); + tcg_temp_free(tmp); + gen_dagaddi(dc, i, 2); + } else if (aop == 1 && W == 0 && m == 0) { + /* Dreg{reg} = [Ireg{i}--]; */ + disalgnexcpt_ld32u(dc, cpu_dreg[reg], cpu_ireg[i]); + gen_dagsubi(dc, i, 4); + } else if (aop == 1 && W == 0 && m == 1) { + /* Dreg_lo{reg} = W[Ireg{i}--]; */ + tmp = tcg_temp_local_new(); + gen_aligned_qemu_ld16u(dc, tmp, cpu_ireg[i]); + gen_mov_l_tl(cpu_dreg[reg], tmp); + tcg_temp_free(tmp); + gen_dagsubi(dc, i, 2); + } else if (aop == 1 && W == 0 && m == 2) { + /* Dreg_hi{reg} = W[Ireg{i}--]; */ + tmp = tcg_temp_local_new(); + gen_aligned_qemu_ld16u(dc, tmp, cpu_ireg[i]); + gen_mov_h_tl(cpu_dreg[reg], tmp); + tcg_temp_free(tmp); + gen_dagsubi(dc, i, 2); + } else if (aop == 2 && W == 0 && m == 0) { + /* Dreg{reg} = [Ireg{i}]; */ + disalgnexcpt_ld32u(dc, cpu_dreg[reg], cpu_ireg[i]); + } else if (aop == 2 && W == 0 && m == 1) { + /* Dreg_lo{reg} = W[Ireg{i}]; */ + tmp = tcg_temp_local_new(); + gen_aligned_qemu_ld16u(dc, tmp, cpu_ireg[i]); + gen_mov_l_tl(cpu_dreg[reg], tmp); + tcg_temp_free(tmp); + } else if (aop == 2 && W == 0 && m == 2) { + /* Dreg_hi{reg} = W[Ireg{i}]; */ + tmp = tcg_temp_local_new(); + gen_aligned_qemu_ld16u(dc, tmp, cpu_ireg[i]); + gen_mov_h_tl(cpu_dreg[reg], tmp); + tcg_temp_free(tmp); + } else if (aop == 0 && W == 1 && m == 0) { + /* [Ireg{i}++] = Dreg{reg}; */ + gen_aligned_qemu_st32(dc, cpu_dreg[reg], cpu_ireg[i]); + gen_dagaddi(dc, i, 4); + } else if (aop == 0 && W == 1 && m == 1) { + /* W[Ireg{i}++] = Dreg_lo{reg}; */ + gen_aligned_qemu_st16(dc, cpu_dreg[reg], cpu_ireg[i]); + gen_dagaddi(dc, i, 2); + } else if (aop == 0 && W == 1 && m == 2) { + /* W[Ireg{i}++] = Dreg_hi{reg}; */ + tmp = tcg_temp_local_new(); + tcg_gen_shri_tl(tmp, cpu_dreg[reg], 16); + gen_aligned_qemu_st16(dc, tmp, cpu_ireg[i]); + tcg_temp_free(tmp); + gen_dagaddi(dc, i, 2); + } else if (aop == 1 && W == 1 && m == 0) { + /* [Ireg{i}--] = Dreg{reg}; */ + gen_aligned_qemu_st32(dc, cpu_dreg[reg], cpu_ireg[i]); + gen_dagsubi(dc, i, 4); + } else if (aop == 1 && W == 1 && m == 1) { + /* W[Ireg{i}--] = Dreg_lo{reg}; */ + gen_aligned_qemu_st16(dc, cpu_dreg[reg], cpu_ireg[i]); + gen_dagsubi(dc, i, 2); + } else if (aop == 1 && W == 1 && m == 2) { + /* W[Ireg{i}--] = Dreg_hi{reg}; */ + tmp = tcg_temp_local_new(); + tcg_gen_shri_tl(tmp, cpu_dreg[reg], 16); + gen_aligned_qemu_st16(dc, tmp, cpu_ireg[i]); + tcg_temp_free(tmp); + gen_dagsubi(dc, i, 2); + } else if (aop == 2 && W == 1 && m == 0) { + /* [Ireg{i}] = Dreg{reg}; */ + gen_aligned_qemu_st32(dc, cpu_dreg[reg], cpu_ireg[i]); + } else if (aop == 2 && W == 1 && m == 1) { + /* W[Ireg{i}] = Dreg_lo{reg}; */ + gen_aligned_qemu_st16(dc, cpu_dreg[reg], cpu_ireg[i]); + } else if (aop == 2 && W == 1 && m == 2) { + /* W[Ireg{i}] = Dreg_hi{reg}; */ + tmp = tcg_temp_local_new(); + tcg_gen_shri_tl(tmp, cpu_dreg[reg], 16); + gen_aligned_qemu_st16(dc, tmp, cpu_ireg[i]); + tcg_temp_free(tmp); + } else if (aop == 3 && W == 0) { + /* Dreg{reg} = [Ireg{i} ++ Mreg{m}]; */ + disalgnexcpt_ld32u(dc, cpu_dreg[reg], cpu_ireg[i]); + gen_dagadd(dc, i, cpu_mreg[m]); + } else if (aop == 3 && W == 1) { + /* [Ireg{i} ++ Mreg{m}] = Dreg{reg}; */ + gen_aligned_qemu_st32(dc, cpu_dreg[reg], cpu_ireg[i]); + gen_dagadd(dc, i, cpu_mreg[m]); + } else { + illegal_instruction(dc); + } +} + +static void +decode_LDST_0(DisasContext *dc, uint16_t iw0) +{ + /* LDST + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask); + int W = ((iw0 >> LDST_W_bits) & LDST_W_mask); + int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask); + int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask); + int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask); + int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask); + + TRACE_EXTRACT("sz:%i W:%i aop:%i Z:%i ptr:%i reg:%i", + sz, W, aop, Z, ptr, reg); + + if (aop == 3) { + illegal_instruction(dc); + } + + if (W == 0) { + if (sz == 0 && Z == 0) { + /* Dreg{reg} = [Preg{ptr}{aop}]; */ + gen_aligned_qemu_ld32u(dc, cpu_dreg[reg], cpu_preg[ptr]); + } else if (sz == 0 && Z == 1) { + /* Preg{reg} = [Preg{ptr}{aop}]; */ + gen_aligned_qemu_ld32u(dc, cpu_preg[reg], cpu_preg[ptr]); + } else if (sz == 1 && Z == 0) { + /* Dreg{reg} = W[Preg{ptr}{aop}] (Z); */ + gen_aligned_qemu_ld16u(dc, cpu_dreg[reg], cpu_preg[ptr]); + } else if (sz == 1 && Z == 1) { + /* Dreg{reg} = W[Preg{ptr}{aop}] (X); */ + gen_aligned_qemu_ld16s(dc, cpu_dreg[reg], cpu_preg[ptr]); + } else if (sz == 2 && Z == 0) { + /* Dreg{reg} = B[Preg{ptr}{aop}] (Z); */ + tcg_gen_qemu_ld8u(cpu_dreg[reg], cpu_preg[ptr], dc->mem_idx); + } else if (sz == 2 && Z == 1) { + /* Dreg{reg} = B[Preg{ptr}{aop}] (X); */ + tcg_gen_qemu_ld8s(cpu_dreg[reg], cpu_preg[ptr], dc->mem_idx); + } else { + illegal_instruction(dc); + } + } else { + if (sz == 0 && Z == 0) { + /* [Preg{ptr}{aop}] = Dreg{reg}; */ + gen_aligned_qemu_st32(dc, cpu_dreg[reg], cpu_preg[ptr]); + } else if (sz == 0 && Z == 1) { + /* [Preg{ptr}{aop}] = Preg{reg}; */ + gen_aligned_qemu_st32(dc, cpu_preg[reg], cpu_preg[ptr]); + } else if (sz == 1 && Z == 0) { + /* W[Preg{ptr}{aop}] = Dreg{reg}; */ + gen_aligned_qemu_st16(dc, cpu_dreg[reg], cpu_preg[ptr]); + } else if (sz == 2 && Z == 0) { + /* B[Preg{ptr}{aop}] = Dreg{reg}; */ + tcg_gen_qemu_st8(cpu_dreg[reg], cpu_preg[ptr], dc->mem_idx); + } else { + illegal_instruction(dc); + } + } + + if (aop == 0) { + tcg_gen_addi_tl(cpu_preg[ptr], cpu_preg[ptr], 1 << (2 - sz)); + } + if (aop == 1) { + tcg_gen_subi_tl(cpu_preg[ptr], cpu_preg[ptr], 1 << (2 - sz)); + } +} + +static void +decode_LDSTiiFP_0(DisasContext *dc, uint16_t iw0) +{ + /* LDSTiiFP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + /* This isn't exactly a grp:reg as this insn only supports Dregs & Pregs, + but for our usage, its functionality the same thing. */ + int grp = ((iw0 >> 3) & 0x1); + int reg = ((iw0 >> LDSTiiFP_reg_bits) & 0x7 /*LDSTiiFP_reg_mask*/); + int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask); + int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask); + uint32_t imm = negimm5s4(offset); + TCGv treg = get_allreg(dc, grp, reg); + TCGv ea; + + TRACE_EXTRACT("W:%i offset:%#x grp:%i reg:%i", + W, offset, grp, reg); + + ea = tcg_temp_local_new(); + tcg_gen_addi_tl(ea, cpu_fpreg, imm); + gen_align_check(dc, ea, 4, false); + if (W == 0) { + /* DPreg{reg} = [FP + imm{offset}]; */ + tcg_gen_qemu_ld32u(treg, ea, dc->mem_idx); + } else { + /* [FP + imm{offset}] = DPreg{reg}; */ + tcg_gen_qemu_st32(treg, ea, dc->mem_idx); + } + tcg_temp_free(ea); +} + +static void +decode_LDSTii_0(DisasContext *dc, uint16_t iw0) +{ + /* LDSTii + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask); + int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask); + int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask); + int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask); + int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask); + uint32_t imm; + TCGv ea; + + TRACE_EXTRACT("W:%i op:%i offset:%#x ptr:%i reg:%i", + W, op, offset, ptr, reg); + + if (op == 0 || op == 3) { + imm = uimm4s4(offset); + } else { + imm = uimm4s2(offset); + } + + ea = tcg_temp_local_new(); + tcg_gen_addi_tl(ea, cpu_preg[ptr], imm); + if (W == 0) { + if (op == 0) { + /* Dreg{reg} = [Preg{ptr} + imm{offset}]; */ + gen_aligned_qemu_ld32u(dc, cpu_dreg[reg], ea); + } else if (op == 1) { + /* Dreg{reg} = W[Preg{ptr} + imm{offset}] (Z); */ + gen_aligned_qemu_ld16u(dc, cpu_dreg[reg], ea); + } else if (op == 2) { + /* Dreg{reg} = W[Preg{ptr} + imm{offset}] (X); */ + gen_aligned_qemu_ld16s(dc, cpu_dreg[reg], ea); + } else if (op == 3) { + /* P%i = [Preg{ptr} + imm{offset}]; */ + gen_aligned_qemu_ld32u(dc, cpu_preg[reg], ea); + } + } else { + if (op == 0) { + /* [Preg{ptr} + imm{offset}] = Dreg{reg}; */ + gen_aligned_qemu_st32(dc, cpu_dreg[reg], ea); + } else if (op == 1) { + /* W[Preg{ptr} + imm{offset}] = Dreg{reg}; */ + gen_aligned_qemu_st16(dc, cpu_dreg[reg], ea); + } else if (op == 3) { + /* [Preg{ptr} + imm{offset}] = P%i; */ + gen_aligned_qemu_st32(dc, cpu_preg[reg], ea); + } else { + illegal_instruction(dc); + } + } + tcg_temp_free(ea); +} + +static void +decode_LoopSetup_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* LoopSetup + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......| + |.reg...........| - | - |.eoffset...............................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask); + int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask); + int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask); + int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & + LoopSetup_soffset_mask); + int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask); + int spcrel = pcrel4(soffset); + int epcrel = lppcrel10(eoffset); + + TRACE_EXTRACT("rop:%i c:%i soffset:%i reg:%i eoffset:%i", + rop, c, soffset, reg, eoffset); + + if (rop == 0) { + /* LSETUP (imm{soffset}, imm{eoffset}) LCreg{c}; */; + } else if (rop == 1 && reg <= 7) { + /* LSETUP (imm{soffset}, imm{eoffset}) LCreg{c} = Preg{reg}; */ + tcg_gen_mov_tl(cpu_lcreg[c], cpu_preg[reg]); + } else if (rop == 3 && reg <= 7) { + /* LSETUP (imm{soffset}, imm{eoffset}) LCreg{c} = Preg{reg} >> 1; */ + tcg_gen_shri_tl(cpu_lcreg[c], cpu_preg[reg], 1); + } else { + illegal_instruction(dc); + } + + tcg_gen_movi_tl(cpu_ltreg[c], dc->pc + spcrel); + tcg_gen_movi_tl(cpu_lbreg[c], dc->pc + epcrel); + gen_gotoi_tb(dc, 0, dc->pc + 4); +} + +static void +decode_LDIMMhalf_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* LDIMMhalf + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......| + |.hword.........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask); + int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask); + int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask); + int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask); + int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask); + int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask); + uint32_t val; + TCGv treg, tmp; + + TRACE_EXTRACT("Z:%i H:%i S:%i grp:%i reg:%i hword:%#x", + Z, H, S, grp, reg, hword); + + treg = get_allreg(dc, grp, reg); + if (S == 1) { + val = imm16(hword); + } else { + val = luimm16(hword); + } + + if (H == 0 && S == 1 && Z == 0) { + /* genreg{grp,reg} = imm{hword} (X); */ + /* Take care of immediate sign extension ourselves */ + tcg_gen_movi_tl(treg, (int16_t)val); + } else if (H == 0 && S == 0 && Z == 1) { + /* genreg{grp,reg} = imm{hword} (Z); */ + tcg_gen_movi_tl(treg, val); + } else if (H == 0 && S == 0 && Z == 0) { + /* genreg_lo{grp,reg} = imm{hword}; */ + tmp = tcg_temp_new(); + tcg_gen_movi_tl(tmp, val); + tcg_gen_deposit_tl(treg, treg, tmp, 0, 16); + tcg_temp_free(tmp); + } else if (H == 1 && S == 0 && Z == 0) { + /* genreg_hi{grp,reg} = imm{hword}; */ + tmp = tcg_temp_new(); + tcg_gen_movi_tl(tmp, val); + tcg_gen_deposit_tl(treg, treg, tmp, 16, 16); + tcg_temp_free(tmp); + } else { + illegal_instruction(dc); + } +} + +static void +decode_CALLa_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* CALLa + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................| + |.lsw...........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask); + int lsw = ((iw1 >> 0) & 0xffff); + int msw = ((iw0 >> 0) & 0xff); + int pcrel = pcrel24((msw << 16) | lsw); + + TRACE_EXTRACT("S:%i msw:%#x lsw:%#x", S, msw, lsw); + + if (S == 1) { + /* CALL imm{pcrel}; */ + dc->is_jmp = DISAS_CALL; + } else { + /* JUMP.L imm{pcrel}; */ + dc->is_jmp = DISAS_JUMP; + } + dc->hwloop_callback = gen_hwloop_br_pcrel_imm; + dc->hwloop_data = (void *)(unsigned long)pcrel; +} + +static void +decode_LDSTidxI_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* LDSTidxI + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......| + |.offset........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask); + int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask); + int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask); + int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask); + int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask); + int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask); + uint32_t imm_16s4 = imm16s4(offset); + uint32_t imm_16s2 = imm16s2(offset); + uint32_t imm_16 = imm16(offset); + TCGv ea; + + TRACE_EXTRACT("W:%i Z:%i sz:%i ptr:%i reg:%i offset:%#x", + W, Z, sz, ptr, reg, offset); + + ea = tcg_temp_local_new(); + if (sz == 0) { + tcg_gen_addi_tl(ea, cpu_preg[ptr], imm_16s4); + } else if (sz == 1) { + tcg_gen_addi_tl(ea, cpu_preg[ptr], imm_16s2); + } else if (sz == 2) { + tcg_gen_addi_tl(ea, cpu_preg[ptr], imm_16); + } else { + illegal_instruction(dc); + } + + if (W == 0) { + if (sz == 0 && Z == 0) { + /* Dreg{reg} = [Preg{ptr] + imm{offset}]; */ + gen_aligned_qemu_ld32u(dc, cpu_dreg[reg], ea); + } else if (sz == 0 && Z == 1) { + /* Preg{reg} = [Preg{ptr] + imm{offset}]; */ + gen_aligned_qemu_ld32u(dc, cpu_preg[reg], ea); + } else if (sz == 1 && Z == 0) { + /* Dreg{reg} = W[Preg{ptr] + imm{offset}] (Z); */ + gen_aligned_qemu_ld16u(dc, cpu_dreg[reg], ea); + } else if (sz == 1 && Z == 1) { + /* Dreg{reg} = W[Preg{ptr} imm{offset}] (X); */ + gen_aligned_qemu_ld16s(dc, cpu_dreg[reg], ea); + } else if (sz == 2 && Z == 0) { + /* Dreg{reg} = B[Preg{ptr} + imm{offset}] (Z); */ + tcg_gen_qemu_ld8u(cpu_dreg[reg], ea, dc->mem_idx); + } else if (sz == 2 && Z == 1) { + /* Dreg{reg} = B[Preg{ptr} + imm{offset}] (X); */ + tcg_gen_qemu_ld8s(cpu_dreg[reg], ea, dc->mem_idx); + } + } else { + if (sz == 0 && Z == 0) { + /* [Preg{ptr} + imm{offset}] = Dreg{reg}; */ + gen_aligned_qemu_st32(dc, cpu_dreg[reg], ea); + } else if (sz == 0 && Z == 1) { + /* [Preg{ptr} + imm{offset}] = Preg{reg}; */ + gen_aligned_qemu_st32(dc, cpu_preg[reg], ea); + } else if (sz == 1 && Z == 0) { + /* W[Preg{ptr} + imm{offset}] = Dreg{reg}; */ + gen_aligned_qemu_st16(dc, cpu_dreg[reg], ea); + } else if (sz == 2 && Z == 0) { + /* B[Preg{ptr} + imm{offset}] = Dreg{reg}; */ + tcg_gen_qemu_st8(cpu_dreg[reg], ea, dc->mem_idx); + } else { + illegal_instruction(dc); + } + } + + tcg_temp_free(ea); +} + +static void +decode_linkage_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* linkage + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.| + |.framesize.....................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask); + int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask); + TCGv tmp_sp; + + TRACE_EXTRACT("R:%i framesize:%#x", R, framesize); + + /* XXX: Should do alignment checks of fp/sp */ + + /* Delay the SP update till the end in case an exception occurs. */ + tmp_sp = tcg_temp_new(); + tcg_gen_mov_tl(tmp_sp, cpu_spreg); + if (R == 0) { + /* LINK imm{framesize}; */ + int size = uimm16s4(framesize); + tcg_gen_subi_tl(tmp_sp, tmp_sp, 4); + tcg_gen_qemu_st32(cpu_rets, tmp_sp, dc->mem_idx); + tcg_gen_subi_tl(tmp_sp, tmp_sp, 4); + tcg_gen_qemu_st32(cpu_fpreg, tmp_sp, dc->mem_idx); + tcg_gen_mov_tl(cpu_fpreg, tmp_sp); + tcg_gen_subi_tl(cpu_spreg, tmp_sp, size); + } else if (framesize == 0) { + /* UNLINK; */ + /* Restore SP from FP. */ + tcg_gen_mov_tl(tmp_sp, cpu_fpreg); + tcg_gen_qemu_ld32u(cpu_fpreg, tmp_sp, dc->mem_idx); + tcg_gen_addi_tl(tmp_sp, tmp_sp, 4); + tcg_gen_qemu_ld32u(cpu_rets, tmp_sp, dc->mem_idx); + tcg_gen_addi_tl(cpu_spreg, tmp_sp, 4); + } else { + illegal_instruction(dc); + } + tcg_temp_free(tmp_sp); +} + +static void +decode_dsp32mac_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* XXX: Very incomplete. */ + /* dsp32mac + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| + |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask); + int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); + int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); + int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask); + int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); + int M = ((iw0 >> (DSP32Mac_M_bits - 16)) & DSP32Mac_M_mask); + int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); + int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); + int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask); + int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); + int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); + int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask); + int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); + int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask); + int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask); + + int v_i = 0; + TCGv res; + + TRACE_EXTRACT("M:%i mmod:%i MM:%i P:%i w1:%i op1:%i h01:%i h11:%i " + "w0:%i op0:%i h00:%i h10:%i dst:%i src0:%i src1:%i", + M, mmod, MM, P, w1, op1, h01, h11, w0, op0, h00, h10, + dst, src0, src1); + + res = tcg_temp_local_new(); + tcg_gen_mov_tl(res, cpu_dreg[dst]); + if (w1 == 1 || op1 != 3) { + TCGv res1 = decode_macfunc(dc, 1, op1, h01, h11, src0, src1, mmod, MM, + P, &v_i); + if (w1) { + if (P) { + tcg_gen_mov_tl(cpu_dreg[dst + 1], res1); + } else { + gen_mov_h_tl(res, res1); + } + } + tcg_temp_free(res1); + } + if (w0 == 1 || op0 != 3) { + TCGv res0 = decode_macfunc(dc, 0, op0, h00, h10, src0, src1, mmod, 0, + P, &v_i); + if (w0) { + if (P) { + tcg_gen_mov_tl(cpu_dreg[dst], res0); + } else { + gen_mov_l_tl(res, res0); + } + } + tcg_temp_free(res0); + } + + if (!P && (w0 || w1)) { + tcg_gen_mov_tl(cpu_dreg[dst], res); + } + + tcg_temp_free(res); +} + +static void +decode_dsp32mult_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* XXX: Very incomplete. */ + + /* dsp32mult + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| + |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask); + int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); + int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); + int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask); + int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); + int M = ((iw0 >> (DSP32Mac_M_bits - 16)) & DSP32Mac_M_mask); + int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); + int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); + int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask); + int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); + int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); + int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask); + int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); + int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask); + int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask); + + TCGv res; + TCGv sat0, sat1; + + TRACE_EXTRACT("M:%i mmod:%i MM:%i P:%i w1:%i op1:%i h01:%i h11:%i " + "w0:%i op0:%i h00:%i h10:%i dst:%i src0:%i src1:%i", + M, mmod, MM, P, w1, op1, h01, h11, w0, op0, h00, h10, + dst, src0, src1); + + if (w1 == 0 && w0 == 0) { + illegal_instruction(dc); + } + if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0) { + illegal_instruction(dc); + } + if (P && ((dst & 1) || (op1 != 0) || (op0 != 0) || + !is_macmod_pmove(mmod))) { + illegal_instruction(dc); + } + if (!P && ((op1 != 0) || (op0 != 0) || !is_macmod_hmove(mmod))) { + illegal_instruction(dc); + } + + res = tcg_temp_local_new(); + tcg_gen_mov_tl(res, cpu_dreg[dst]); + + sat1 = tcg_temp_local_new(); + + if (w1) { + TCGv res1 = decode_multfunc_tl(dc, h01, h11, src0, src1, mmod, MM, + sat1); + if (P) { + tcg_gen_mov_tl(cpu_dreg[dst + 1], res1); + } else { + gen_mov_h_tl(res, res1); + } + tcg_temp_free(res1); + } + + sat0 = tcg_temp_local_new(); + + if (w0) { + TCGv res0 = decode_multfunc_tl(dc, h00, h10, src0, src1, mmod, 0, + sat0); + if (P) { + tcg_gen_mov_tl(cpu_dreg[dst], res0); + } else { + gen_mov_l_tl(res, res0); + } + tcg_temp_free(res0); + } + + if (!P && (w0 || w1)) { + tcg_gen_mov_tl(cpu_dreg[dst], res); + } + + tcg_temp_free(sat0); + tcg_temp_free(sat1); + tcg_temp_free(res); +} + +static void +decode_dsp32alu_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* dsp32alu + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| + |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask); + int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask); + int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask); + int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); + int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask); + int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask); + int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask); + int M = ((iw0 >> (DSP32Alu_M_bits - 16)) & DSP32Alu_M_mask); + int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask); + int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask); + TCGv tmp; + TCGv_i64 tmp64; + + TRACE_EXTRACT("M:%i HL:%i aopcde:%i aop:%i s:%i x:%i dst0:%i " + "dst1:%i src0:%i src1:%i", + M, HL, aopcde, aop, s, x, dst0, dst1, src0, src1); + + if ((aop == 0 || aop == 2) && aopcde == 9 && HL == 0 && s == 0) { + int a = aop >> 1; + /* Areg_lo{a} = Dreg_lo{src0}; */ + tmp64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(tmp64, cpu_dreg[src0]); + tcg_gen_deposit_i64(cpu_areg[a], cpu_areg[a], tmp64, 0, 16); + tcg_temp_free_i64(tmp64); + } else if ((aop == 0 || aop == 2) && aopcde == 9 && HL == 1 && s == 0) { + int a = aop >> 1; + /* Areg_hi{a} = Dreg_hi{src0}; */ + tcg_gen_andi_i64(cpu_areg[a], cpu_areg[a], 0xff0000ffff); + tmp64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(tmp64, cpu_dreg[src0]); + tcg_gen_andi_i64(tmp64, tmp64, 0xffff0000); + tcg_gen_or_i64(cpu_areg[a], cpu_areg[a], tmp64); + tcg_temp_free_i64(tmp64); + } else if ((aop == 1 || aop == 0) && aopcde == 5) { + /* Dreg{dst0}_hi{HL==0} = Dreg{src0} +{aop==0} Dreg{src1} (RND12); */ + /* Dreg{dst0}_lo{HL==1} = Dreg{src0} +{aop==0} Dreg{src1} (RND12); */ + /* Dreg{dst0}_hi{HL==0} = Dreg{src0} -{aop==1} Dreg{src1} (RND12); */ + /* Dreg{dst0}_lo{HL==1} = Dreg{src0} -{aop==1} Dreg{src1} (RND12); */ + unhandled_instruction(dc, "Dreg +/- RND12"); + } else if ((aop == 2 || aop == 3) && aopcde == 5) { + /* Dreg{dst0}_hi{HL==0} = Dreg{src0} +{aop==0} Dreg{src1} (RND20); */ + /* Dreg{dst0}_lo{HL==1} = Dreg{src0} +{aop==0} Dreg{src1} (RND20); */ + /* Dreg{dst0}_hi{HL==0} = Dreg{src0} -{aop==1} Dreg{src1} (RND20); */ + /* Dreg{dst0}_lo{HL==1} = Dreg{src0} -{aop==1} Dreg{src1} (RND20); */ + unhandled_instruction(dc, "Dreg +/- RND20"); + } else if (aopcde == 2 || aopcde == 3) { + /* Dreg{dst0}_lo{HL==0} = Dreg{src0}_lo{!aop&2} +{aopcde==2} + Dreg{src1}_lo{!aop&1} (amod1(s,x)); */ + /* Dreg{dst0}_hi{HL==1} = Dreg{src0}_hi{aop&2} -{aopcde==3} + Dreg{src1}_hi{aop&1} (amod1(s,x)); */ + TCGv s1, s2, d; + + s1 = tcg_temp_new(); + if (aop & 2) { + tcg_gen_shri_tl(s1, cpu_dreg[src0], 16); + } else { + tcg_gen_ext16u_tl(s1, cpu_dreg[src0]); + } + + s2 = tcg_temp_new(); + if (aop & 1) { + tcg_gen_shri_tl(s2, cpu_dreg[src1], 16); + } else { + tcg_gen_ext16u_tl(s2, cpu_dreg[src1]); + } + + d = tcg_temp_new(); + if (aopcde == 2) { + tcg_gen_add_tl(d, s1, s2); + } else { + tcg_gen_sub_tl(d, s1, s2); + } + tcg_gen_andi_tl(d, d, 0xffff); + + tcg_temp_free(s1); + tcg_temp_free(s2); + + if (HL) { + tcg_gen_andi_tl(cpu_dreg[dst0], cpu_dreg[dst0], 0xffff); + tcg_gen_shli_tl(d, d, 16); + tcg_gen_or_tl(cpu_dreg[dst0], cpu_dreg[dst0], d); + } else { + tcg_gen_andi_tl(cpu_dreg[dst0], cpu_dreg[dst0], 0xffff0000); + tcg_gen_or_tl(cpu_dreg[dst0], cpu_dreg[dst0], d); + } + tcg_temp_free(d); + } else if ((aop == 0 || aop == 2) && aopcde == 9 && s == 1) { + int a = aop >> 1; + /* Areg{a} = Dreg{src0}; */ + tcg_gen_ext_i32_i64(cpu_areg[a], cpu_dreg[src0]); + } else if ((aop == 1 || aop == 3) && aopcde == 9 && s == 0) { + int a = aop >> 1; + /* Areg_x{a} = Dreg_lo{src0}; */ + tmp64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(tmp64, cpu_dreg[src0]); + tcg_gen_deposit_i64(cpu_areg[a], cpu_areg[a], tmp64, 32, 8); + tcg_temp_free_i64(tmp64); + } else if (aop == 3 && aopcde == 11 && (s == 0 || s == 1)) { + /* A0 -= A0 (W32){s==1}; */ + tcg_gen_sub_i64(cpu_areg[0], cpu_areg[0], cpu_areg[1]); + + if (s == 1) { + unhandled_instruction(dc, "A0 -= A1 (W32)"); + } + } else if ((aop == 0 || aop == 1) && aopcde == 22) { + /* Dreg{dst0} = BYTEOP2P (Dreg{src0+1}:Dreg{src0}, + Dreg{src1+1}:Dreg{src1} (mode); */ + /* modes[HL + (aop << 1)] = { rndl, rndh, tl, th }; */ + /* (modes, r) s==1 */ + unhandled_instruction(dc, "BYTEOP2P"); + } else if ((aop == 0 || aop == 1) && s == 0 && aopcde == 8) { + /* Areg{aop} = 0; */ + tcg_gen_movi_i64(cpu_areg[0], 0); + } else if (aop == 2 && s == 0 && aopcde == 8) { + /* A1 = A0 = 0; */ + tcg_gen_movi_i64(cpu_areg[0], 0); + tcg_gen_mov_i64(cpu_areg[1], cpu_areg[0]); + } else if ((aop == 0 || aop == 1 || aop == 2) && s == 1 && aopcde == 8) { + /* A0 = A0 (S); {aop==0} */ + /* A1 = A1 (S); {aop==1} */ + /* A1 = A1 (S), A0 = A0 (S); {aop==2} */ + TCGv sat0, sat1; + + sat0 = tcg_temp_local_new(); + tcg_gen_movi_tl(sat0, 0); + if (aop == 0 || aop == 2) { + gen_extend_acc(cpu_areg[0]); + saturate_s32(cpu_areg[0], sat0); + tcg_gen_ext32s_i64(cpu_areg[0], cpu_areg[0]); + } + + sat1 = tcg_temp_local_new(); + tcg_gen_movi_tl(sat1, 0); + if (aop == 1 || aop == 2) { + gen_extend_acc(cpu_areg[1]); + saturate_s32(cpu_areg[1], sat1); + tcg_gen_ext32s_i64(cpu_areg[0], cpu_areg[0]); + } + + tcg_temp_free(sat1); + tcg_temp_free(sat0); + + /* XXX: missing ASTAT update */ + } else if (aop == 3 && (s == 0 || s == 1) && aopcde == 8) { + /* Areg{s} = Areg{!s}; */ + tcg_gen_mov_i64(cpu_areg[s], cpu_areg[!s]); + } else if (aop == 3 && HL == 0 && aopcde == 16) { + /* A1 = ABS A1 , A0 = ABS A0; */ + int i; + /* XXX: Missing ASTAT updates and saturation */ + for (i = 0; i < 2; ++i) { + gen_abs_i64(cpu_areg[i], cpu_areg[i]); + } + } else if (aop == 0 && aopcde == 23) { + unhandled_instruction(dc, "BYTEOP3P"); + } else if ((aop == 0 || aop == 1) && aopcde == 16) { + /* Areg{HL} = ABS Areg{aop}; */ + + /* XXX: Missing ASTAT updates */ + /* XXX: Missing saturation */ + gen_abs_i64(cpu_areg[aop], cpu_areg[aop]); + } else if (aop == 3 && aopcde == 12) { + /* Dreg{dst0}_lo{HL==0} = Dreg{src0} (RND); */ + /* Dreg{dst0}_hi{HL==1} = Dreg{src0} (RND); */ + unhandled_instruction(dc, "Dreg (RND)"); + } else if (aop == 3 && HL == 0 && aopcde == 15) { + /* Dreg{dst0} = -Dreg{src0} (V); */ + unhandled_instruction(dc, "Dreg = -Dreg (V)"); + } else if (aop == 3 && HL == 0 && aopcde == 14) { + /* A1 = -A1 , A0 = -A0; */ + tcg_gen_neg_i64(cpu_areg[1], cpu_areg[1]); + tcg_gen_neg_i64(cpu_areg[0], cpu_areg[0]); + /* XXX: what ASTAT flags need updating ? */ + } else if ((aop == 0 || aop == 1) && (HL == 0 || HL == 1) && + aopcde == 14) { + /* Areg{HL} = -Areg{aop}; */ + tcg_gen_neg_i64(cpu_areg[HL], cpu_areg[aop]); + /* XXX: Missing ASTAT updates */ + } else if (aop == 0 && aopcde == 12) { + /* Dreg_lo{dst0} = Dreg_hi{dst0} = + SIGN(Dreg_hi{src0} * Dreg_hi{src1} + + SIGN(Dreg_lo{src0} * Dreg_lo{src1} */ + TCGLabel *l; + TCGv tmp1_hi, tmp1_lo; + + tmp1_hi = tcg_temp_local_new(); + /* if ((src0_hi >> 15) & 1) tmp1_hi = -src1_hi; */ + tcg_gen_sari_tl(tmp1_hi, cpu_dreg[src1], 16); + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_GE, cpu_dreg[src0], 0, l); + tcg_gen_neg_tl(tmp1_hi, tmp1_hi); + gen_set_label(l); + + tmp = tcg_temp_local_new(); + tmp1_lo = tcg_temp_local_new(); + /* if ((src0_lo >> 15) & 1) tmp1_lo = -src1_lo; */ + tcg_gen_ext16s_tl(tmp, cpu_dreg[src0]); + tcg_gen_ext16s_tl(tmp1_lo, cpu_dreg[src1]); + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_GE, tmp, 0, l); + tcg_gen_neg_tl(tmp1_lo, tmp1_lo); + gen_set_label(l); + + tcg_temp_free(tmp); + + tcg_gen_add_tl(tmp1_hi, tmp1_hi, tmp1_lo); + tcg_gen_shli_tl(cpu_dreg[dst0], tmp1_hi, 16); + gen_mov_l_tl(cpu_dreg[dst0], tmp1_hi); + + tcg_temp_free(tmp1_lo); + tcg_temp_free(tmp1_hi); + } else if (aopcde == 0) { + /* Dreg{dst0} = Dreg{src0} -{aop&2}+{!aop&2}|-{aop&1}+{!aop&1} + Dreg{src1} (amod0); */ + TCGv s0, s1, t0, t1; + + if (s || x) { + unhandled_instruction(dc, "S/CO/SCO with +|+/-|-"); + } + + s0 = tcg_temp_local_new(); + s1 = tcg_temp_local_new(); + + t0 = tcg_temp_local_new(); + tcg_gen_shri_tl(s0, cpu_dreg[src0], 16); + tcg_gen_shri_tl(s1, cpu_dreg[src1], 16); + if (aop & 2) { + tcg_gen_sub_tl(t0, s0, s1); + } else { + tcg_gen_add_tl(t0, s0, s1); + } + + t1 = tcg_temp_local_new(); + tcg_gen_andi_tl(s0, cpu_dreg[src0], 0xffff); + tcg_gen_andi_tl(s1, cpu_dreg[src1], 0xffff); + if (aop & 1) { + tcg_gen_sub_tl(t1, s0, s1); + } else { + tcg_gen_add_tl(t1, s0, s1); + } + + tcg_temp_free(s1); + tcg_temp_free(s0); + + astat_queue_state2(dc, ASTAT_OP_VECTOR_ADD_ADD + aop, t0, t1); + + if (x) { + /* dst0.h = t1; dst0.l = t0 */ + tcg_gen_ext16u_tl(cpu_dreg[dst0], t0); + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_or_tl(cpu_dreg[dst0], cpu_dreg[dst0], t1); + } else { + /* dst0.h = t0; dst0.l = t1 */ + tcg_gen_ext16u_tl(cpu_dreg[dst0], t1); + tcg_gen_shli_tl(t0, t0, 16); + tcg_gen_or_tl(cpu_dreg[dst0], cpu_dreg[dst0], t0); + } + + tcg_temp_free(t0); + tcg_temp_free(t1); + /* XXX: missing ASTAT update */ + } else if (aop == 1 && aopcde == 12) { + /* Dreg{dst1} = A1.L + A1.H, Dreg{dst0} = A0.L + A0.H; */ + TCGv al, ah; + + al = tcg_temp_local_new(); + ah = tcg_temp_local_new(); + tcg_gen_extrl_i64_i32(ah, cpu_areg[0]); + tcg_gen_ext16u_tl(al, ah); + tcg_gen_shri_tl(ah, ah, 16); + tcg_gen_add_tl(cpu_dreg[dst0], al, ah); + tcg_temp_free(al); + tcg_temp_free(ah); + tcg_gen_ext16s_tl(cpu_dreg[dst0], cpu_dreg[dst0]); + + al = tcg_temp_local_new(); + ah = tcg_temp_local_new(); + tcg_gen_extrl_i64_i32(ah, cpu_areg[1]); + tcg_gen_ext16u_tl(al, ah); + tcg_gen_shri_tl(ah, ah, 16); + tcg_gen_add_tl(cpu_dreg[dst1], al, ah); + tcg_temp_free(al); + tcg_temp_free(ah); + tcg_gen_ext16s_tl(cpu_dreg[dst1], cpu_dreg[dst1]); + + /* XXX: ASTAT ? */ + } else if (aopcde == 1) { + /* XXX: missing ASTAT update */ + unhandled_instruction(dc, "Dreg +|+ Dreg, Dreg -|- Dreg"); + } else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 11) { + /* Dreg{dst0} = (A0 += A1); {aop==0} */ + /* Dreg{dst0}_lo{HL==0} = (A0 += A1); {aop==1} */ + /* Dreg{dst0}_hi{HL==1} = (A0 += A1); {aop==1} */ + /* (A0 += A1); {aop==2} */ + + tcg_gen_add_i64(cpu_areg[0], cpu_areg[0], cpu_areg[1]); + + if (aop == 2 && s == 1) { /* A0 += A1 (W32) */ + unhandled_instruction(dc, "A0 += A1 (W32)"); + } + + /* XXX: missing saturation support */ + if (aop == 0) { + /* Dregs = A0 += A1 */ + tcg_gen_extrl_i64_i32(cpu_dreg[dst0], cpu_areg[0]); + } else if (aop == 1) { + /* Dregs_lo = A0 += A1 */ + tmp = tcg_temp_new(); + tcg_gen_extrl_i64_i32(tmp, cpu_areg[0]); + gen_mov_l_tl(cpu_dreg[dst0], tmp); + tcg_temp_free(tmp); + } + } else if ((aop == 0 || aop == 1) && aopcde == 10) { + /* Dreg_lo{dst0} = Areg_x{aop}; */ + tmp = tcg_temp_new(); + tmp64 = tcg_temp_new_i64(); + tcg_gen_shri_i64(tmp64, cpu_areg[aop], 32); + tcg_gen_extrl_i64_i32(tmp, tmp64); + tcg_temp_free_i64(tmp64); + tcg_gen_ext8s_tl(tmp, tmp); + gen_mov_l_tl(cpu_dreg[dst0], tmp); + tcg_temp_free(tmp); + } else if (aop == 0 && aopcde == 4) { + /* Dreg{dst0} = Dreg{src0} + Dreg{src1} (amod1(s,x)); */ + tcg_gen_add_tl(cpu_dreg[dst0], cpu_dreg[src0], cpu_dreg[src1]); + astat_queue_state3(dc, ASTAT_OP_ADD32, cpu_dreg[dst0], cpu_dreg[src0], + cpu_dreg[src1]); + } else if (aop == 1 && aopcde == 4) { + /* Dreg{dst0} = Dreg{src0} - Dreg{src1} (amod1(s,x)); */ + tcg_gen_sub_tl(cpu_dreg[dst0], cpu_dreg[src0], cpu_dreg[src1]); + astat_queue_state3(dc, ASTAT_OP_SUB32, cpu_dreg[dst0], cpu_dreg[src0], + cpu_dreg[src1]); + } else if (aop == 2 && aopcde == 4) { + /* Dreg{dst1} = Dreg{src0} + Dreg{src1}, + Dreg{dst0} = Dreg{src0} - Dreg{src1} (amod1(s,x)); */ + if (dst1 == src0 || dst1 == src1) { + tmp = tcg_temp_new(); + } else { + tmp = cpu_dreg[dst1]; + } + tcg_gen_add_tl(tmp, cpu_dreg[src0], cpu_dreg[src1]); + tcg_gen_sub_tl(cpu_dreg[dst0], cpu_dreg[src0], cpu_dreg[src1]); + if (dst1 == src0 || dst1 == src1) { + tcg_gen_mov_tl(cpu_dreg[dst1], tmp); + tcg_temp_free(tmp); + } + /* XXX: Missing ASTAT updates */ + } else if ((aop == 0 || aop == 1) && aopcde == 17) { + unhandled_instruction(dc, "Dreg = Areg + Areg, Dreg = Areg - Areg"); + } else if (aop == 0 && aopcde == 18) { + unhandled_instruction(dc, "SAA"); + } else if (aop == 3 && aopcde == 18) { + dc->disalgnexcpt = true; + } else if ((aop == 0 || aop == 1) && aopcde == 20) { + unhandled_instruction(dc, "BYTEOP1P"); + } else if (aop == 0 && aopcde == 21) { + unhandled_instruction(dc, "BYTEOP16P"); + } else if (aop == 1 && aopcde == 21) { + unhandled_instruction(dc, "BYTEOP16M"); + } else if ((aop == 0 || aop == 1) && aopcde == 7) { + /* Dreg{dst0} = MIN{aop==1} (Dreg{src0}, Dreg{src1}); */ + /* Dreg{dst0} = MAX{aop==0} (Dreg{src0}, Dreg{src1}); */ + int _src0, _src1; + TCGCond cond; + + if (aop == 0) { + cond = TCG_COND_LT; + } else { + cond = TCG_COND_GE; + } + + /* src/dst regs might be the same, so we need to handle that */ + if (dst0 == src1) { + _src0 = src1, _src1 = src0; + } else { + _src0 = src0, _src1 = src1; + } + + tcg_gen_movcond_tl(cond, cpu_dreg[dst0], cpu_dreg[_src1], + cpu_dreg[_src0], cpu_dreg[_src0], cpu_dreg[_src1]); + + astat_queue_state1(dc, ASTAT_OP_MIN_MAX, cpu_dreg[dst0]); + } else if (aop == 2 && aopcde == 7) { + /* Dreg{dst0} = ABS Dreg{src0}; */ + + /* XXX: Missing saturation support (and ASTAT V/VS) */ + gen_abs_tl(cpu_dreg[dst0], cpu_dreg[src0]); + + astat_queue_state2(dc, ASTAT_OP_ABS, cpu_dreg[dst0], cpu_dreg[src0]); + } else if (aop == 3 && aopcde == 7) { + /* Dreg{dst0} = -Dreg{src0} (amod1(s,0)); */ + TCGLabel *l, *endl; + + l = gen_new_label(); + endl = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_dreg[src0], 0x80000000, l); + if (s) { + tcg_gen_movi_tl(cpu_dreg[dst0], 0x7fffffff); + tmp = tcg_const_tl(1); + _gen_astat_store(ASTAT_V, tmp); + _gen_astat_store(ASTAT_V_COPY, tmp); + _gen_astat_store(ASTAT_VS, tmp); + tcg_temp_free(tmp); + } else { + tcg_gen_movi_tl(cpu_dreg[dst0], 0x80000000); + } + + gen_set_label(l); + tcg_gen_neg_tl(cpu_dreg[dst0], cpu_dreg[src0]); + gen_set_label(endl); + astat_queue_state2(dc, ASTAT_OP_NEGATE, cpu_dreg[dst0], cpu_dreg[src0]); + } else if (aop == 2 && aopcde == 6) { + /* Dreg{dst0} = ABS Dreg{src0} (V); */ + TCGv tmp0; + + tmp = tcg_temp_local_new(); + tcg_gen_sari_tl(tmp, cpu_dreg[src0], 16); + gen_abs_tl(tmp, tmp); + + tmp0 = tcg_temp_local_new(); + tcg_gen_ext16s_tl(tmp0, cpu_dreg[src0]); + gen_abs_tl(tmp0, tmp0); + + astat_queue_state2(dc, ASTAT_OP_ABS_VECTOR, tmp0, tmp); + + tcg_gen_deposit_tl(cpu_dreg[dst0], tmp0, tmp, 16, 16); + + tcg_temp_free(tmp0); + tcg_temp_free(tmp); + } else if ((aop == 0 || aop == 1) && aopcde == 6) { + /* Dreg{dst0} = MAX{aop==0} (Dreg{src0}, Dreg{src1}) (V); */ + /* Dreg{dst0} = MIN{aop==1} (Dreg{src0}, Dreg{src1}) (V); */ + /* src/dst regs might be the same, so we need to handle that */ + TCGCond cond; + TCGv tmp0, tmp1; + + cond = aop == 1 ? TCG_COND_LE : TCG_COND_GE; + + tmp = tcg_temp_local_new(); + tmp0 = tcg_temp_local_new(); + tmp1 = tcg_temp_local_new(); + + /* First do top 16bit pair */ + tcg_gen_andi_tl(tmp0, cpu_dreg[src0], 0xffff0000); + tcg_gen_andi_tl(tmp1, cpu_dreg[src1], 0xffff0000); + tcg_gen_movcond_tl(cond, tmp0, tmp0, tmp1, tmp0, tmp1); + + /* Then bottom 16bit pair */ + tcg_gen_ext16s_tl(tmp, cpu_dreg[src0]); + tcg_gen_ext16s_tl(tmp1, cpu_dreg[src1]); + tcg_gen_movcond_tl(cond, tmp, tmp, tmp1, tmp, tmp1); + + astat_queue_state2(dc, ASTAT_OP_MIN_MAX_VECTOR, tmp0, tmp); + + /* Then combine them */ + tcg_gen_andi_tl(tmp, tmp, 0xffff); + tcg_gen_or_tl(cpu_dreg[dst0], tmp0, tmp); + + tcg_temp_free(tmp1); + tcg_temp_free(tmp0); + tcg_temp_free(tmp); + } else if (aop == 0 && aopcde == 24) { + TCGv dst; + /* Dreg{dst0} BYTEPACK (Dreg{src0}, Dreg{src1}); */ + + /* XXX: could optimize a little if dst0 is diff from src0 or src1 */ + /* dst |= (((src0 >> 0) & 0xff) << 0) */ + dst = tcg_temp_new(); + tcg_gen_andi_tl(dst, cpu_dreg[src0], 0xff); + tmp = tcg_temp_new(); + /* dst |= (((src0 >> 16) & 0xff) << 8) */ + tcg_gen_andi_tl(tmp, cpu_dreg[src0], 0xff0000); + tcg_gen_shri_tl(tmp, tmp, 8); + tcg_gen_or_tl(dst, dst, tmp); + /* dst |= (((src1 >> 0) & 0xff) << 16) */ + tcg_gen_andi_tl(tmp, cpu_dreg[src1], 0xff); + tcg_gen_shli_tl(tmp, tmp, 16); + tcg_gen_or_tl(dst, dst, tmp); + /* dst |= (((src1 >> 16) & 0xff) << 24) */ + tcg_gen_andi_tl(tmp, cpu_dreg[src1], 0xff0000); + tcg_gen_shli_tl(tmp, tmp, 8); + tcg_gen_or_tl(cpu_dreg[dst0], dst, tmp); + tcg_temp_free(tmp); + tcg_temp_free(dst); + } else if (aop == 1 && aopcde == 24) { + /* (Dreg{dst1}, Dreg{dst0} = BYTEUNPACK Dreg{src0+1}:{src0} (R){s}; */ + TCGv lo, hi; + TCGv_i64 tmp64_2; + + if (s) { + hi = cpu_dreg[src0], lo = cpu_dreg[src0 + 1]; + } else { + hi = cpu_dreg[src0 + 1], lo = cpu_dreg[src0]; + } + + /* Create one field of the two regs */ + tmp64 = tcg_temp_local_new_i64(); + tcg_gen_extu_i32_i64(tmp64, hi); + tcg_gen_shli_i64(tmp64, tmp64, 32); + tmp64_2 = tcg_temp_local_new_i64(); + tcg_gen_extu_i32_i64(tmp64_2, lo); + tcg_gen_or_i64(tmp64, tmp64, tmp64_2); + + /* Adjust the two regs field by the Ireg[0] order */ + tcg_gen_extu_i32_i64(tmp64_2, cpu_ireg[0]); + tcg_gen_andi_i64(tmp64_2, tmp64_2, 0x3); + tcg_gen_shli_i64(tmp64_2, tmp64_2, 3); /* multiply by 8 */ + tcg_gen_shr_i64(tmp64, tmp64, tmp64_2); + tcg_temp_free_i64(tmp64_2); + + /* Now that the 4 bytes we want are in the low 32bit, truncate */ + tmp = tcg_temp_local_new(); + tcg_gen_extrl_i64_i32(tmp, tmp64); + tcg_temp_free_i64(tmp64); + + /* Load bytea into dst0 */ + tcg_gen_andi_tl(cpu_dreg[dst0], tmp, 0xff); + /* Load byted into dst1 */ + tcg_gen_shri_tl(cpu_dreg[dst1], tmp, 8); + tcg_gen_andi_tl(cpu_dreg[dst1], cpu_dreg[dst1], 0xff0000); + /* Load byteb into dst0 */ + tcg_gen_shli_tl(tmp, tmp, 8); + tcg_gen_or_tl(cpu_dreg[dst0], cpu_dreg[dst0], tmp); + tcg_gen_andi_tl(cpu_dreg[dst0], cpu_dreg[dst0], 0xff00ff); + /* Load bytec into dst1 */ + tcg_gen_shri_tl(tmp, tmp, 24); + tcg_gen_or_tl(cpu_dreg[dst1], cpu_dreg[dst1], tmp); + tcg_gen_andi_tl(cpu_dreg[dst1], cpu_dreg[dst1], 0xff00ff); + tcg_temp_free(tmp); + } else if (aopcde == 13) { + TCGLabel *l; + TCGv a_lo; + TCGCond conds[] = { + /* GT */ TCG_COND_LE, + /* GE */ TCG_COND_LT, + /* LT */ TCG_COND_GE, + /* LE */ TCG_COND_GT, + }; + + /* (Dreg{dst1}, Dreg{dst0}) = SEARCH Dreg{src0} (mode{aop}); */ + + a_lo = tcg_temp_local_new(); + tmp = tcg_temp_local_new(); + + /* Compare A1 to Dreg_hi{src0} */ + tcg_gen_extrl_i64_i32(a_lo, cpu_areg[1]); + tcg_gen_ext16s_tl(a_lo, a_lo); + tcg_gen_sari_tl(tmp, cpu_dreg[src0], 16); + + l = gen_new_label(); + tcg_gen_brcond_tl(conds[aop], tmp, a_lo, l); + /* Move Dreg_hi{src0} into A0 */ + tcg_gen_ext_i32_i64(cpu_areg[1], tmp); + /* Move Preg{0} into Dreg{dst1} */ + tcg_gen_mov_tl(cpu_dreg[dst1], cpu_preg[0]); + gen_set_label(l); + + /* Compare A0 to Dreg_lo{src0} */ + tcg_gen_extrl_i64_i32(a_lo, cpu_areg[0]); + tcg_gen_ext16s_tl(a_lo, a_lo); + tcg_gen_ext16s_tl(tmp, cpu_dreg[src0]); + + l = gen_new_label(); + tcg_gen_brcond_tl(conds[aop], tmp, a_lo, l); + /* Move Dreg_lo{src0} into A0 */ + tcg_gen_ext_i32_i64(cpu_areg[0], tmp); + /* Move Preg{0} into Dreg{dst0} */ + tcg_gen_mov_tl(cpu_dreg[dst0], cpu_preg[0]); + gen_set_label(l); + + tcg_temp_free(a_lo); + tcg_temp_free(tmp); + } else { + illegal_instruction(dc); + } +} + +static void +decode_dsp32shift_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* dsp32shift + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| + |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask); + int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask); + int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); + int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask); + int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask); + int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & + DSP32Shift_sopcde_mask); + int M = ((iw0 >> (DSP32Shift_M_bits - 16)) & DSP32Shift_M_mask); + TCGv tmp; + TCGv_i64 tmp64; + + TRACE_EXTRACT("M:%i sopcde:%i sop:%i HLs:%i dst0:%i src0:%i src1:%i", + M, sopcde, sop, HLs, dst0, src0, src1); + + if ((sop == 0 || sop == 1) && sopcde == 0) { + TCGLabel *l, *endl; + TCGv val; + + /* Dreg{dst0}_hi{HLs&2} = ASHIFT Dreg{src1}_hi{HLs&1} BY + Dreg_lo{src0} (S){sop==1}; */ + /* Dreg{dst0}_lo{!HLs&2} = ASHIFT Dreg{src1}_lo{!HLs&1} BY + Dreg_lo{src0} (S){sop==1}; */ + + tmp = tcg_temp_local_new(); + gen_extNsi_tl(tmp, cpu_dreg[src0], 6); + + val = tcg_temp_local_new(); + if (HLs & 1) { + tcg_gen_sari_tl(val, cpu_dreg[src1], 16); + } else { + tcg_gen_ext16s_tl(val, cpu_dreg[src1]); + } + + /* Positive shift magnitudes produce Logical Left shifts. + * Negative shift magnitudes produce Arithmetic Right shifts. + */ + endl = gen_new_label(); + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_GE, tmp, 0, l); + tcg_gen_neg_tl(tmp, tmp); + tcg_gen_sar_tl(val, val, tmp); + astat_queue_state1(dc, ASTAT_OP_ASHIFT16, val); + tcg_gen_br(endl); + gen_set_label(l); + tcg_gen_shl_tl(val, val, tmp); + astat_queue_state1(dc, ASTAT_OP_LSHIFT16, val); + gen_set_label(endl); + + if (HLs & 2) { + gen_mov_h_tl(cpu_dreg[dst0], val); + } else { + gen_mov_l_tl(cpu_dreg[dst0], val); + } + + tcg_temp_free(val); + tcg_temp_free(tmp); + + /* XXX: Missing V updates */ + } else if (sop == 2 && sopcde == 0) { + TCGLabel *l, *endl; + TCGv val; + + /* Dreg{dst0}_hi{HLs&2} = LSHIFT Dreg{src1}_hi{HLs&1} BY + Dreg_lo{src0}; */ + /* Dreg{dst0}_lo{!HLs&2} = LSHIFT Dreg{src1}_lo{!HLs&1} BY + Dreg_lo{src0}; */ + + tmp = tcg_temp_local_new(); + gen_extNsi_tl(tmp, cpu_dreg[src0], 6); + + val = tcg_temp_local_new(); + if (HLs & 1) { + tcg_gen_shri_tl(val, cpu_dreg[src1], 16); + } else { + tcg_gen_ext16u_tl(val, cpu_dreg[src1]); + } + + /* Negative shift magnitudes means shift right */ + endl = gen_new_label(); + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_GE, tmp, 0, l); + tcg_gen_neg_tl(tmp, tmp); + tcg_gen_shr_tl(val, val, tmp); + tcg_gen_br(endl); + gen_set_label(l); + tcg_gen_shl_tl(val, val, tmp); + gen_set_label(endl); + astat_queue_state1(dc, ASTAT_OP_LSHIFT16, val); + + if (HLs & 2) { + gen_mov_h_tl(cpu_dreg[dst0], val); + } else { + gen_mov_l_tl(cpu_dreg[dst0], val); + } + + tcg_temp_free(val); + tcg_temp_free(tmp); + + /* XXX: Missing AZ/AN/V updates */ + } else if (sop == 2 && sopcde == 3 && (HLs == 1 || HLs == 0)) { + /* Areg{HLs} = ROT Areg{HLs} BY Dreg_lo{src0}; */ + tmp64 = tcg_temp_local_new_i64(); + tcg_gen_extu_i32_i64(tmp64, cpu_dreg[src0]); + tcg_gen_ext16s_i64(tmp64, tmp64); + gen_rot_i64(cpu_areg[HLs], cpu_areg[HLs], tmp64); + tcg_temp_free_i64(tmp64); + } else if (sop == 0 && sopcde == 3 && (HLs == 0 || HLs == 1)) { + /* Areg{HLs} = ASHIFT Areg{HLs} BY Dregs_lo{src0}; */ + unhandled_instruction(dc, "ASHIFT ACC"); + } else if (sop == 1 && sopcde == 3 && (HLs == 0 || HLs == 1)) { + /* Areg{HLs} = LSHIFT Areg{HLs} BY Dregs_lo{src0}; */ + unhandled_instruction(dc, "LSHIFT ACC"); + } else if ((sop == 0 || sop == 1) && sopcde == 1) { + /* Dreg{dst0} = ASHIFT Dreg{src1} BY Dreg{src0} (V){sop==0}; */ + /* Dreg{dst0} = ASHIFT Dreg{src1} BY Dreg{src0} (V,S){sop==1}; */ + unhandled_instruction(dc, "ASHIFT V"); + } else if ((sop == 0 || sop == 1 || sop == 2) && sopcde == 2) { + /* Dreg{dst0} = [LA]SHIFT Dreg{src1} BY Dreg_lo{src0} (opt_S); */ + /* sop == 1 : opt_S */ + TCGLabel *l, *endl; + + /* XXX: Missing V/VS update */ + if (sop == 1) { + unhandled_instruction(dc, "[AL]SHIFT with (S)"); + } + + tmp = tcg_temp_local_new(); + gen_extNsi_tl(tmp, cpu_dreg[src0], 6); + + /* Negative shift means logical or arith shift right */ + endl = gen_new_label(); + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_GE, tmp, 0, l); + tcg_gen_neg_tl(tmp, tmp); + if (sop == 2) { + tcg_gen_shr_tl(cpu_dreg[dst0], cpu_dreg[src1], tmp); + astat_queue_state1(dc, ASTAT_OP_LSHIFT_RT32, cpu_dreg[dst0]); + } else { + tcg_gen_sar_tl(cpu_dreg[dst0], cpu_dreg[src1], tmp); + astat_queue_state1(dc, ASTAT_OP_ASHIFT32, cpu_dreg[dst0]); + } + tcg_gen_br(endl); + + /* Positive shift is a logical left shift */ + gen_set_label(l); + tcg_gen_shl_tl(cpu_dreg[dst0], cpu_dreg[src1], tmp); + astat_queue_state1(dc, ASTAT_OP_LSHIFT32, cpu_dreg[dst0]); + gen_set_label(endl); + + tcg_temp_free(tmp); + } else if (sop == 3 && sopcde == 2) { + /* Dreg{dst0} = ROT Dreg{src1} BY Dreg_lo{src0}; */ + tmp = tcg_temp_local_new(); + tcg_gen_ext16s_tl(tmp, cpu_dreg[src0]); + gen_rot_tl(cpu_dreg[dst0], cpu_dreg[src1], tmp); + tcg_temp_free(tmp); + } else if (sop == 2 && sopcde == 1) { + /* Dreg{dst0} = LSHIFT Dreg{src1} BY Dreg_lo{src0} (V); */ + unhandled_instruction(dc, "LSHIFT (V)"); + } else if (sopcde == 4) { + /* Dreg{dst0} = PACK (Dreg{src1}_hi{sop&2}, Dreg{src0}_hi{sop&1}); */ + /* Dreg{dst0} = PACK (Dreg{src1}_lo{!sop&2}, Dreg{src0}_lo{!sop&1}); */ + TCGv tmph; + tmp = tcg_temp_new(); + if (sop & 1) { + tcg_gen_shri_tl(tmp, cpu_dreg[src0], 16); + } else { + tcg_gen_andi_tl(tmp, cpu_dreg[src0], 0xffff); + } + tmph = tcg_temp_new(); + if (sop & 2) { + tcg_gen_andi_tl(tmph, cpu_dreg[src1], 0xffff0000); + } else { + tcg_gen_shli_tl(tmph, cpu_dreg[src1], 16); + } + tcg_gen_or_tl(cpu_dreg[dst0], tmph, tmp); + tcg_temp_free(tmph); + tcg_temp_free(tmp); + } else if (sop == 0 && sopcde == 5) { + /* Dreg_lo{dst0} = SIGNBITS Dreg{src1}; */ + tmp = tcg_temp_new(); + gen_helper_signbits_32(tmp, cpu_dreg[src1]); + gen_mov_l_tl(cpu_dreg[dst0], tmp); + tcg_temp_free(tmp); + } else if (sop == 1 && sopcde == 5) { + /* Dreg_lo{dst0} = SIGNBITS Dreg_lo{src1}; */ + tmp = tcg_temp_new(); + gen_helper_signbits_16(tmp, cpu_dreg[src1]); + gen_mov_l_tl(cpu_dreg[dst0], tmp); + tcg_temp_free(tmp); + } else if (sop == 2 && sopcde == 5) { + /* Dreg_lo{dst0} = SIGNBITS Dreg_hi{src1}; */ + tmp = tcg_temp_new(); + tcg_gen_shri_tl(tmp, cpu_dreg[src1], 16); + gen_helper_signbits_16(tmp, tmp); + gen_mov_l_tl(cpu_dreg[dst0], tmp); + tcg_temp_free(tmp); + } else if ((sop == 0 || sop == 1) && sopcde == 6) { + /* Dreg_lo{dst0} = SIGNBITS Areg{sop}; */ + tmp = tcg_temp_new(); + gen_helper_signbits_40(tmp, cpu_areg[sop]); + gen_mov_l_tl(cpu_dreg[dst0], tmp); + tcg_temp_free(tmp); + } else if (sop == 3 && sopcde == 6) { + /* Dreg_lo{dst0} = ONES Dreg{src1}; */ + tmp = tcg_temp_new(); + gen_helper_ones(tmp, cpu_dreg[src1]); + gen_mov_l_tl(cpu_dreg[dst0], tmp); + tcg_temp_free(tmp); + } else if (sop == 0 && sopcde == 7) { + /* Dreg_lo{dst0} = EXPADJ( Dreg{src1}, Dreg_lo{src0}); */ + unhandled_instruction(dc, "EXPADJ"); + } else if (sop == 1 && sopcde == 7) { + /* Dreg_lo{dst0} = EXPADJ( Dreg{src1}, Dreg_lo{src0}) (V); */ + unhandled_instruction(dc, "EXPADJ (V)"); + } else if (sop == 2 && sopcde == 7) { + /* Dreg_lo{dst0} = EXPADJ( Dreg_lo{src1}, Dreg_lo{src0}) (V); */ + unhandled_instruction(dc, "EXPADJ"); + } else if (sop == 3 && sopcde == 7) { + /* Dreg_lo{dst0} = EXPADJ( Dreg_hi{src1}, Dreg_lo{src0}); */ + unhandled_instruction(dc, "EXPADJ"); + } else if (sop == 0 && sopcde == 8) { + /* BITMUX (Dreg{src0}, Dreg{src1}, A0) (ASR); */ + unhandled_instruction(dc, "BITMUX"); + } else if (sop == 1 && sopcde == 8) { + /* BITMUX (Dreg{src0}, Dreg{src1}, A0) (ASL); */ + unhandled_instruction(dc, "BITMUX"); + } else if ((sop == 0 || sop == 1) && sopcde == 9) { + /* Dreg_lo{dst0} = VIT_MAX (Dreg{src1}) (ASL){sop==0}; */ + /* Dreg_lo{dst0} = VIT_MAX (Dreg{src1}) (ASR){sop==1}; */ + TCGv sl, sh; + TCGLabel *l; + + gen_extend_acc(cpu_areg[0]); + if (sop & 1) { + tcg_gen_shri_i64(cpu_areg[0], cpu_areg[0], 1); + } else { + tcg_gen_shli_i64(cpu_areg[0], cpu_areg[0], 1); + } + + sl = tcg_temp_local_new(); + sh = tcg_temp_local_new(); + tmp = tcg_temp_local_new(); + + tcg_gen_ext16s_tl(sl, cpu_dreg[src1]); + tcg_gen_sari_tl(sh, cpu_dreg[src1], 16); + /* Hrm, can't this sub be inlined in the branch ? */ + tcg_gen_sub_tl(tmp, sh, sl); + tcg_gen_andi_tl(tmp, tmp, 0x8000); + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 0, l); + tcg_gen_mov_tl(sl, sh); + tcg_gen_ori_i64(cpu_areg[0], cpu_areg[0], (sop & 1) ? 0x80000000 : 1); + gen_set_label(l); + + gen_mov_l_tl(cpu_dreg[dst0], sl); + + tcg_temp_free(tmp); + tcg_temp_free(sh); + tcg_temp_free(sl); + } else if ((sop == 2 || sop == 3) && sopcde == 9) { + /* Dreg{dst0} = VIT_MAX (Dreg{src1}, Dreg{src0}) (ASL){sop==0}; */ + /* Dreg{dst0} = VIT_MAX (Dreg{src1}, Dreg{src0}) (ASR){sop==1}; */ + TCGv sl, sh, dst; + TCGLabel *l; + + gen_extend_acc(cpu_areg[0]); + if (sop & 1) { + tcg_gen_shri_i64(cpu_areg[0], cpu_areg[0], 2); + } else { + tcg_gen_shli_i64(cpu_areg[0], cpu_areg[0], 2); + } + + sl = tcg_temp_local_new(); + sh = tcg_temp_local_new(); + tmp = tcg_temp_local_new(); + + tcg_gen_ext16s_tl(sl, cpu_dreg[src1]); + tcg_gen_sari_tl(sh, cpu_dreg[src1], 16); + + /* Hrm, can't this sub be inlined in the branch ? */ + tcg_gen_sub_tl(tmp, sh, sl); + tcg_gen_andi_tl(tmp, tmp, 0x8000); + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 0, l); + tcg_gen_mov_tl(sl, sh); + tcg_gen_ori_i64(cpu_areg[0], cpu_areg[0], (sop & 1) ? 0x80000000 : 1); + gen_set_label(l); + + /* The dst might be a src reg */ + if (dst0 == src0) { + dst = tcg_temp_local_new(); + } else { + dst = cpu_dreg[dst0]; + } + + tcg_gen_shli_tl(dst, sl, 16); + + tcg_gen_ext16s_tl(sl, cpu_dreg[src0]); + tcg_gen_sari_tl(sh, cpu_dreg[src0], 16); + /* Hrm, can't this sub be inlined in the branch ? */ + tcg_gen_sub_tl(tmp, sh, sl); + tcg_gen_andi_tl(tmp, tmp, 0x8000); + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 0, l); + tcg_gen_mov_tl(sl, sh); + tcg_gen_ori_i64(cpu_areg[0], cpu_areg[0], (sop & 1) ? 0x40000000 : 2); + gen_set_label(l); + + gen_mov_l_tl(dst, sl); + + if (dst0 == src0) { + tcg_gen_mov_tl(cpu_dreg[dst0], dst); + tcg_temp_free(dst); + } + + tcg_temp_free(tmp); + tcg_temp_free(sh); + tcg_temp_free(sl); + } else if ((sop == 0 || sop == 1) && sopcde == 10) { + /* Dreg{dst0} = EXTRACT (Dreg{src1}, Dreg_lo{src0}) (X{sop==1}); */ + /* Dreg{dst0} = EXTRACT (Dreg{src1}, Dreg_lo{src0}) (Z{sop==0}); */ + TCGv mask, x, sgn; + + /* mask = 1 << (src0 & 0x1f) */ + tmp = tcg_temp_new(); + tcg_gen_andi_tl(tmp, cpu_dreg[src0], 0x1f); + mask = tcg_temp_local_new(); + tcg_gen_movi_tl(mask, 1); + tcg_gen_shl_tl(mask, mask, tmp); + tcg_temp_free(tmp); + if (sop) { + /* sgn = mask >> 1 */ + sgn = tcg_temp_local_new(); + tcg_gen_shri_tl(sgn, mask, 1); + } + /* mask -= 1 */ + tcg_gen_subi_tl(mask, mask, 1); + + /* x = src1 >> ((src0 >> 8) & 0x1f) */ + tmp = tcg_temp_new(); + x = tcg_temp_new(); + tcg_gen_shri_tl(tmp, cpu_dreg[src0], 8); + tcg_gen_andi_tl(tmp, tmp, 0x1f); + tcg_gen_shr_tl(x, cpu_dreg[src1], tmp); + tcg_temp_free(tmp); + /* dst0 = x & mask */ + tcg_gen_and_tl(cpu_dreg[dst0], x, mask); + tcg_temp_free(x); + + if (sop) { + /* if (dst0 & sgn) dst0 |= ~mask */ + TCGLabel *l; + l = gen_new_label(); + tmp = tcg_temp_new(); + tcg_gen_and_tl(tmp, cpu_dreg[dst0], sgn); + tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, l); + tcg_gen_not_tl(mask, mask); + tcg_gen_or_tl(cpu_dreg[dst0], cpu_dreg[dst0], mask); + gen_set_label(l); + tcg_temp_free(sgn); + tcg_temp_free(tmp); + } + + tcg_temp_free(mask); + + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst0]); + } else if ((sop == 2 || sop == 3) && sopcde == 10) { + /* The first dregs is the "background" while the second dregs is the + * "foreground". The fg reg is used to overlay the bg reg and is: + * | nnnn nnnn | nnnn nnnn | xxxp pppp | xxxL LLLL | + * n = the fg bit field + * p = bit position in bg reg to start LSB of fg field + * L = number of fg bits to extract + * Using (X) sign-extends the fg bit field. + */ + TCGv fg, bg, len, mask, fgnd, shft; + + /* Dreg{dst0} = DEPOSIT (Dreg{src1}, Dreg{src0}) (X){sop==3}; */ + fg = cpu_dreg[src0]; + bg = cpu_dreg[src1]; + + len = tcg_temp_new(); + tcg_gen_andi_tl(len, fg, 0x1f); + + mask = tcg_temp_new(); + tcg_gen_movi_tl(mask, 1); + tcg_gen_shl_tl(mask, mask, len); + tcg_gen_subi_tl(mask, mask, 1); + tcg_gen_andi_tl(mask, mask, 0xffff); + + fgnd = tcg_temp_new(); + tcg_gen_shri_tl(fgnd, fg, 16); + tcg_gen_and_tl(fgnd, fgnd, mask); + + shft = tcg_temp_new(); + tcg_gen_shri_tl(shft, fg, 8); + tcg_gen_andi_tl(shft, shft, 0x1f); + + if (sop == 3) { + /* Sign extend the fg bit field. */ + tcg_gen_movi_tl(mask, -1); + gen_extNs_tl(fgnd, fgnd, len); + } + tcg_gen_shl_tl(fgnd, fgnd, shft); + tcg_gen_shl_tl(mask, mask, shft); + tcg_gen_not_tl(mask, mask); + tcg_gen_and_tl(mask, bg, mask); + + tcg_gen_or_tl(cpu_dreg[dst0], mask, fgnd); + + tcg_temp_free(shft); + tcg_temp_free(fgnd); + tcg_temp_free(mask); + tcg_temp_free(len); + + astat_queue_state1(dc, ASTAT_OP_LOGICAL, cpu_dreg[dst0]); + } else if (sop == 0 && sopcde == 11) { + /* Dreg_lo{dst0} = CC = BXORSHIFT (A0, Dreg{src0}); */ + unhandled_instruction(dc, "BXORSHIFT"); + } else if (sop == 1 && sopcde == 11) { + /* Dreg_lo{dst0} = CC = BXOR (A0, Dreg{src0}); */ + unhandled_instruction(dc, "BXOR"); + } else if (sop == 0 && sopcde == 12) { + /* A0 = BXORSHIFT (A0, A1, CC); */ + unhandled_instruction(dc, "BXORSHIFT"); + } else if (sop == 1 && sopcde == 12) { + /* Dreg_lo{dst0} = CC = BXOR (A0, A1, CC); */ + unhandled_instruction(dc, "CC = BXOR"); + } else if ((sop == 0 || sop == 1 || sop == 2) && sopcde == 13) { + int shift = (sop + 1) * 8; + TCGv tmp2; + /* Dreg{dst0} = ALIGN{shift} (Dreg{src1}, Dreg{src0}); */ + /* XXX: could be optimized a bit if dst0 is not src1 or src0 */ + tmp = tcg_temp_new(); + tmp2 = tcg_temp_new(); + tcg_gen_shli_tl(tmp, cpu_dreg[src1], 32 - shift); + tcg_gen_shri_tl(tmp2, cpu_dreg[src0], shift); + tcg_gen_or_tl(cpu_dreg[dst0], tmp, tmp2); + tcg_temp_free(tmp2); + tcg_temp_free(tmp); + } else { + illegal_instruction(dc); + } +} + +static void +decode_dsp32shiftimm_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* dsp32shiftimm + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| + |.sop...|.HLs...|.dst0......|.immag.................|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask); + int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask); + int bit8 = ((iw1 >> 8) & 0x1); + int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & + DSP32ShiftImm_immag_mask); + int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & + DSP32ShiftImm_immag_mask); + int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & + DSP32ShiftImm_dst0_mask); + int M = ((iw0 >> (DSP32ShiftImm_M_bits - 16)) & + DSP32ShiftImm_M_mask); + int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & + DSP32ShiftImm_sopcde_mask); + int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask); + TCGv tmp; + + TRACE_EXTRACT("M:%i sopcde:%i sop:%i HLs:%i dst0:%i immag:%#x src1:%i", + M, sopcde, sop, HLs, dst0, immag, src1); + + if (sopcde == 0) { + tmp = tcg_temp_new(); + + if (HLs & 1) { + if (sop == 0) { + tcg_gen_sari_tl(tmp, cpu_dreg[src1], 16); + } else { + tcg_gen_shri_tl(tmp, cpu_dreg[src1], 16); + } + } else { + if (sop == 0) { + tcg_gen_ext16s_tl(tmp, cpu_dreg[src1]); + } else { + tcg_gen_ext16u_tl(tmp, cpu_dreg[src1]); + } + } + + if (sop == 0) { + /* dregs_hi/lo = dregs_hi/lo >>> imm4 */ + tcg_gen_sari_tl(tmp, tmp, newimmag); + astat_queue_state1(dc, ASTAT_OP_ASHIFT16, tmp); + } else if (sop == 1 && bit8 == 0) { + /* dregs_hi/lo = dregs_hi/lo << imm4 (S) */ + tcg_gen_shli_tl(tmp, tmp, immag); + astat_queue_state1(dc, ASTAT_OP_LSHIFT16, tmp); + } else if (sop == 1 && bit8) { + /* dregs_hi/lo = dregs_hi/lo >>> imm4 (S) */ + tcg_gen_shri_tl(tmp, tmp, immag); + astat_queue_state1(dc, ASTAT_OP_LSHIFT16, tmp); + } else if (sop == 2 && bit8) { + /* dregs_hi/lo = dregs_hi/lo >> imm4 */ + tcg_gen_shri_tl(tmp, tmp, newimmag); + astat_queue_state1(dc, ASTAT_OP_LSHIFT16, tmp); + } else if (sop == 2 && bit8 == 0) { + /* dregs_hi/lo = dregs_hi/lo << imm4 */ + tcg_gen_shli_tl(tmp, tmp, immag); + astat_queue_state1(dc, ASTAT_OP_LSHIFT16, tmp); + } else { + illegal_instruction(dc); + } + + if (HLs & 2) { + gen_mov_h_tl(cpu_dreg[dst0], tmp); + } else { + gen_mov_l_tl(cpu_dreg[dst0], tmp); + } + + tcg_temp_free(tmp); + } else if (sop == 2 && sopcde == 3 && (HLs == 1 || HLs == 0)) { + /* Areg{HLs} = ROT Areg{HLs} BY imm{immag}; */ + int shift = imm6(immag); + gen_roti_i64(cpu_areg[HLs], cpu_areg[HLs], shift); + } else if (sop == 0 && sopcde == 3 && bit8 == 1) { + /* Arithmetic shift, so shift in sign bit copies */ + int shift = uimm5(newimmag); + HLs = !!HLs; + + /* Areg{HLs} = Aregs{HLs} >>> imm{newimmag}; */ + tcg_gen_sari_i64(cpu_areg[HLs], cpu_areg[HLs], shift); + } else if ((sop == 0 && sopcde == 3 && bit8 == 0) || + (sop == 1 && sopcde == 3)) { + int shiftup = uimm5(immag); + int shiftdn = uimm5(newimmag); + HLs = !!HLs; + + if (sop == 0) { + /* Areg{HLs} = Aregs{HLs} <<{sop} imm{immag}; */ + tcg_gen_shli_i64(cpu_areg[HLs], cpu_areg[HLs], shiftup); + } else { + /* Areg{HLs} = Aregs{HLs} >>{sop} imm{newimmag}; */ + tcg_gen_shri_i64(cpu_areg[HLs], cpu_areg[HLs], shiftdn); + } + + /* XXX: Missing ASTAT update */ + } else if (sop == 1 && sopcde == 1 && bit8 == 0) { + /* Dreg{dst0} = Dreg{src1} << imm{immag} (V, S); */ + unhandled_instruction(dc, "Dreg = Dreg << imm (V,S)"); + } else if (sop == 2 && sopcde == 1 && bit8 == 1) { + /* Dreg{dst0} = Dreg{src1} >> imm{count} (V); */ + int count = imm5(newimmag); + + /* XXX: No ASTAT handling */ + if (count > 0 && count <= 15) { + tcg_gen_shri_tl(cpu_dreg[dst0], cpu_dreg[src1], count); + tcg_gen_andi_tl(cpu_dreg[dst0], cpu_dreg[dst0], + 0xffff0000 | ((1 << (16 - count)) - 1)); + } else if (count) { + tcg_gen_movi_tl(cpu_dreg[dst0], 0); + } + } else if (sop == 2 && sopcde == 1 && bit8 == 0) { + /* Dreg{dst0} = Dreg{src1} << imm{count} (V); */ + int count = imm5(immag); + + /* XXX: No ASTAT handling */ + if (count > 0 && count <= 15) { + tcg_gen_shli_tl(cpu_dreg[dst0], cpu_dreg[src1], count); + tcg_gen_andi_tl(cpu_dreg[dst0], cpu_dreg[dst0], + ~(((1 << count) - 1) << 16)); + } else if (count) { + tcg_gen_movi_tl(cpu_dreg[dst0], 0); + } + } else if (sopcde == 1 && (sop == 0 || (sop == 1 && bit8 == 1))) { + /* Dreg{dst0} = Dreg{src1} >>> imm{newimmag} (V){sop==0}; */ + /* Dreg{dst0} = Dreg{src1} >>> imm{newimmag} (V,S){sop==1}; */ + int count = uimm5(newimmag); + + if (sop == 1) { + unhandled_instruction(dc, "ashiftrt (S)"); + } + + /* XXX: No ASTAT handling */ + if (count > 0 && count <= 15) { + tmp = tcg_temp_new(); + tcg_gen_ext16s_tl(tmp, cpu_dreg[src1]); + tcg_gen_sari_tl(tmp, tmp, count); + tcg_gen_andi_tl(tmp, tmp, 0xffff); + tcg_gen_sari_tl(cpu_dreg[dst0], cpu_dreg[src1], count); + tcg_gen_andi_tl(cpu_dreg[dst0], cpu_dreg[dst0], 0xffff0000); + tcg_gen_or_tl(cpu_dreg[dst0], cpu_dreg[dst0], tmp); + tcg_temp_free(tmp); + } else if (count) { + unhandled_instruction(dc, "ashiftrt (S)"); + } + } else if (sop == 1 && sopcde == 2) { + /* Dreg{dst0} = Dreg{src1} << imm{count} (S); */ + int count = imm6(immag); + tcg_gen_shli_tl(cpu_dreg[dst0], cpu_dreg[src1], -count); + astat_queue_state1(dc, ASTAT_OP_LSHIFT32, cpu_dreg[dst0]); + } else if (sop == 2 && sopcde == 2) { + /* Dreg{dst0} = Dreg{src1} >> imm{count}; */ + int count = imm6(newimmag); + if (count < 0) { + tcg_gen_shli_tl(cpu_dreg[dst0], cpu_dreg[src1], -count); + astat_queue_state1(dc, ASTAT_OP_LSHIFT32, cpu_dreg[dst0]); + } else { + tcg_gen_shri_tl(cpu_dreg[dst0], cpu_dreg[src1], count); + astat_queue_state1(dc, ASTAT_OP_LSHIFT_RT32, cpu_dreg[dst0]); + } + } else if (sop == 3 && sopcde == 2) { + /* Dreg{dst0} = ROT Dreg{src1} BY imm{shift}; */ + int shift = imm6(immag); + gen_roti_tl(cpu_dreg[dst0], cpu_dreg[src1], shift); + } else if (sop == 0 && sopcde == 2) { + /* Dreg{dst0} = Dreg{src1} >>> imm{count}; */ + int count = imm6(newimmag); + + /* Negative shift magnitudes produce Logical Left shifts. + * Positive shift magnitudes produce Arithmetic Right shifts. + */ + if (count < 0) { + tcg_gen_shli_tl(cpu_dreg[dst0], cpu_dreg[src1], -count); + astat_queue_state1(dc, ASTAT_OP_LSHIFT32, cpu_dreg[dst0]); + } else { + tcg_gen_sari_tl(cpu_dreg[dst0], cpu_dreg[src1], count); + astat_queue_state1(dc, ASTAT_OP_ASHIFT32, cpu_dreg[dst0]); + } + } else { + illegal_instruction(dc); + } +} + +static void +decode_psedoDEBUG_0(DisasContext *dc, uint16_t iw0) +{ + /* psedoDEBUG + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask); + int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask); + int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask); + + TRACE_EXTRACT("fn:%i grp:%i reg:%i", fn, grp, reg); + + if ((reg == 0 || reg == 1) && fn == 3) { + /* DBG Areg{reg}; */ + TCGv tmp = tcg_const_tl(reg); + gen_helper_dbg_areg(cpu_areg[reg], tmp); + tcg_temp_free(tmp); + } else if (reg == 3 && fn == 3) { + /* ABORT; */ + cec_exception(dc, EXCP_ABORT); + } else if (reg == 4 && fn == 3) { + /* HLT; */ + cec_exception(dc, EXCP_HLT); + } else if (reg == 5 && fn == 3) { + unhandled_instruction(dc, "DBGHALT"); + } else if (reg == 6 && fn == 3) { + unhandled_instruction(dc, "DBGCMPLX (dregs)"); + } else if (reg == 7 && fn == 3) { + unhandled_instruction(dc, "DBG"); + } else if (grp == 0 && fn == 2) { + /* OUTC Dreg{reg}; */ + gen_helper_outc(cpu_dreg[reg]); + } else if (fn == 0) { + /* DBG allreg{grp,reg}; */ + bool istmp; + TCGv tmp; + TCGv tmp_grp = tcg_const_tl(grp); + TCGv tmp_reg = tcg_const_tl(reg); + + if (grp == 4 && reg == 6) { + /* ASTAT */ + tmp = tcg_temp_new(); + gen_astat_load(dc, tmp); + istmp = true; + } else { + tmp = get_allreg(dc, grp, reg); + istmp = false; + } + + gen_helper_dbg(tmp, tmp_grp, tmp_reg); + + if (istmp) { + tcg_temp_free(tmp); + } + tcg_temp_free(tmp_reg); + tcg_temp_free(tmp_grp); + } else if (fn == 1) { + unhandled_instruction(dc, "PRNT allregs"); + } else { + illegal_instruction(dc); + } +} + +static void +decode_psedoOChar_0(DisasContext *dc, uint16_t iw0) +{ + /* psedoOChar + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask); + TCGv tmp; + + TRACE_EXTRACT("ch:%#x", ch); + + /* OUTC imm{ch}; */ + tmp = tcg_temp_new(); + tcg_gen_movi_tl(tmp, ch); + gen_helper_outc(tmp); + tcg_temp_free(tmp); +} + +static void +decode_psedodbg_assert_0(DisasContext *dc, uint16_t iw0, uint16_t iw1) +{ + /* psedodbg_assert + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...| + |.expected......................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & + PseudoDbg_Assert_expected_mask); + int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & + PseudoDbg_Assert_dbgop_mask); + int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & + PseudoDbg_Assert_grp_mask); + int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & + PseudoDbg_Assert_regtest_mask); + TCGv reg, exp, pc; + bool istmp; + + TRACE_EXTRACT("dbgop:%i grp:%i regtest:%i expected:%#x", + dbgop, grp, regtest, expected); + + if (dbgop == 0 || dbgop == 2) { + /* DBGA (genreg_lo{grp,regtest}, imm{expected} */ + /* DBGAL (genreg{grp,regtest}, imm{expected} */ + } else if (dbgop == 1 || dbgop == 3) { + /* DBGA (genreg_hi{grp,regtest}, imm{expected} */ + /* DBGAH (genreg{grp,regtest}, imm{expected} */ + } else { + illegal_instruction(dc); + } + + if (grp == 4 && regtest == 6) { + /* ASTAT */ + reg = tcg_temp_new(); + gen_astat_load(dc, reg); + istmp = true; + } else if (grp == 4 && (regtest == 0 || regtest == 2)) { + /* A#.X */ + TCGv_i64 tmp64 = tcg_temp_new_i64(); + reg = tcg_temp_new(); + tcg_gen_shri_i64(tmp64, cpu_areg[regtest >> 1], 32); + tcg_gen_andi_i64(tmp64, tmp64, 0xff); + tcg_gen_extrl_i64_i32(reg, tmp64); + tcg_temp_free_i64(tmp64); + istmp = true; + } else if (grp == 4 && (regtest == 1 || regtest == 3)) { + /* A#.W */ + reg = tcg_temp_new(); + tcg_gen_extrl_i64_i32(reg, cpu_areg[regtest >> 1]); + istmp = true; + } else { + reg = get_allreg(dc, grp, regtest); + istmp = false; + } + + exp = tcg_const_tl(expected); + pc = tcg_const_tl(dc->pc); + if (dbgop & 1) { + gen_helper_dbga_h(cpu_env, pc, reg, exp); + } else { + gen_helper_dbga_l(cpu_env, pc, reg, exp); + } + + if (istmp) { + tcg_temp_free(reg); + } + tcg_temp_free(pc); + tcg_temp_free(exp); +} + +#include "linux-fixed-code.h" + +static uint32_t bfin_lduw_code(DisasContext *dc, target_ulong pc) +{ +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page */ + if (((dc->env->personality & 0xff/*PER_MASK*/) == 0/*PER_LINUX*/) && + (pc & 0xFFFFFF00) == 0x400) { + uint32_t off = pc - 0x400; + if (off < sizeof(bfin_linux_fixed_code)) { + return ((uint16_t)bfin_linux_fixed_code[off + 1] << 8) | + bfin_linux_fixed_code[off]; + } + } +#endif + + return cpu_lduw_code(dc->env, pc); +} + +/* Interpret a single 16bit/32bit insn; no parallel insn handling */ +static void +_interp_insn_bfin(DisasContext *dc, target_ulong pc) +{ + uint16_t iw0, iw1; + + iw0 = bfin_lduw_code(dc, pc); + if ((iw0 & 0xc000) != 0xc000) { + /* 16-bit opcode */ + dc->insn_len = 2; + + TRACE_EXTRACT("iw0:%#x", iw0); + if ((iw0 & 0xFF00) == 0x0000) { + decode_ProgCtrl_0(dc, iw0); + } else if ((iw0 & 0xFFC0) == 0x0240) { + decode_CaCTRL_0(dc, iw0); + } else if ((iw0 & 0xFF80) == 0x0100) { + decode_PushPopReg_0(dc, iw0); + } else if ((iw0 & 0xFE00) == 0x0400) { + decode_PushPopMultiple_0(dc, iw0); + } else if ((iw0 & 0xFE00) == 0x0600) { + decode_ccMV_0(dc, iw0); + } else if ((iw0 & 0xF800) == 0x0800) { + decode_CCflag_0(dc, iw0); + } else if ((iw0 & 0xFFE0) == 0x0200) { + decode_CC2dreg_0(dc, iw0); + } else if ((iw0 & 0xFF00) == 0x0300) { + decode_CC2stat_0(dc, iw0); + } else if ((iw0 & 0xF000) == 0x1000) { + decode_BRCC_0(dc, iw0); + } else if ((iw0 & 0xF000) == 0x2000) { + decode_UJUMP_0(dc, iw0); + } else if ((iw0 & 0xF000) == 0x3000) { + decode_REGMV_0(dc, iw0); + } else if ((iw0 & 0xFC00) == 0x4000) { + decode_ALU2op_0(dc, iw0); + } else if ((iw0 & 0xFE00) == 0x4400) { + decode_PTR2op_0(dc, iw0); + } else if ((iw0 & 0xF800) == 0x4800) { + decode_LOGI2op_0(dc, iw0); + } else if ((iw0 & 0xF000) == 0x5000) { + decode_COMP3op_0(dc, iw0); + } else if ((iw0 & 0xF800) == 0x6000) { + decode_COMPI2opD_0(dc, iw0); + } else if ((iw0 & 0xF800) == 0x6800) { + decode_COMPI2opP_0(dc, iw0); + } else if ((iw0 & 0xF000) == 0x8000) { + decode_LDSTpmod_0(dc, iw0); + } else if ((iw0 & 0xFF60) == 0x9E60) { + decode_dagMODim_0(dc, iw0); + } else if ((iw0 & 0xFFF0) == 0x9F60) { + decode_dagMODik_0(dc, iw0); + } else if ((iw0 & 0xFC00) == 0x9C00) { + decode_dspLDST_0(dc, iw0); + } else if ((iw0 & 0xF000) == 0x9000) { + decode_LDST_0(dc, iw0); + } else if ((iw0 & 0xFC00) == 0xB800) { + decode_LDSTiiFP_0(dc, iw0); + } else if ((iw0 & 0xE000) == 0xA000) { + decode_LDSTii_0(dc, iw0); + } else { + TRACE_EXTRACT("no matching 16-bit pattern"); + illegal_instruction(dc); + } + return; + } + + /* Grab the next 16 bits to determine if it's a 32-bit or 64-bit opcode */ + iw1 = bfin_lduw_code(dc, pc + 2); + if ((iw0 & BIT_MULTI_INS) && (iw0 & 0xe800) != 0xe800 /* not linkage */) { + dc->insn_len = 8; + } else { + dc->insn_len = 4; + } + + TRACE_EXTRACT("iw0:%#x iw1:%#x insn_len:%i", + iw0, iw1, dc->insn_len); + + if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800) { + /* MNOP; */; + } else if (((iw0 & 0xFF80) == 0xE080) && ((iw1 & 0x0C00) == 0x0000)) { + decode_LoopSetup_0(dc, iw0, iw1); + } else if (((iw0 & 0xFF00) == 0xE100) && ((iw1 & 0x0000) == 0x0000)) { + decode_LDIMMhalf_0(dc, iw0, iw1); + } else if (((iw0 & 0xFE00) == 0xE200) && ((iw1 & 0x0000) == 0x0000)) { + decode_CALLa_0(dc, iw0, iw1); + } else if (((iw0 & 0xFC00) == 0xE400) && ((iw1 & 0x0000) == 0x0000)) { + decode_LDSTidxI_0(dc, iw0, iw1); + } else if (((iw0 & 0xFFFE) == 0xE800) && ((iw1 & 0x0000) == 0x0000)) { + decode_linkage_0(dc, iw0, iw1); + } else if (((iw0 & 0xF600) == 0xC000) && ((iw1 & 0x0000) == 0x0000)) { + decode_dsp32mac_0(dc, iw0, iw1); + } else if (((iw0 & 0xF600) == 0xC200) && ((iw1 & 0x0000) == 0x0000)) { + decode_dsp32mult_0(dc, iw0, iw1); + } else if (((iw0 & 0xF7C0) == 0xC400) && ((iw1 & 0x0000) == 0x0000)) { + decode_dsp32alu_0(dc, iw0, iw1); + } else if (((iw0 & 0xF7E0) == 0xC600) && ((iw1 & 0x01C0) == 0x0000)) { + decode_dsp32shift_0(dc, iw0, iw1); + } else if (((iw0 & 0xF7E0) == 0xC680) && ((iw1 & 0x0000) == 0x0000)) { + decode_dsp32shiftimm_0(dc, iw0, iw1); + } else if ((iw0 & 0xFF00) == 0xF800) { + decode_psedoDEBUG_0(dc, iw0), dc->insn_len = 2; + } else if ((iw0 & 0xFF00) == 0xF900) { + decode_psedoOChar_0(dc, iw0), dc->insn_len = 2; + } else if (((iw0 & 0xFF00) == 0xF000) && ((iw1 & 0x0000) == 0x0000)) { + decode_psedodbg_assert_0(dc, iw0, iw1); + } else { + TRACE_EXTRACT("no matching 32-bit pattern"); + illegal_instruction(dc); + } +} + +/* Interpret a single Blackfin insn; breaks up parallel insns */ +static void +interp_insn_bfin(DisasContext *dc) +{ + _interp_insn_bfin(dc, dc->pc); + + /* Proper display of multiple issue instructions */ + if (dc->insn_len == 8) { + _interp_insn_bfin(dc, dc->pc + 4); + _interp_insn_bfin(dc, dc->pc + 6); + dc->disalgnexcpt = 0; + /* Reset back for higher levels to process branches */ + dc->insn_len = 8; + } +} diff --git a/target-bfin/bfin-tdep.h b/target-bfin/bfin-tdep.h new file mode 100644 index 0000000000000..ef6d3252ad3ee --- /dev/null +++ b/target-bfin/bfin-tdep.h @@ -0,0 +1,94 @@ +/* Target-dependent code for Analog Devices Blackfin processer, for GDB. + + Copyright (C) 2005 Free Software Foundation, Inc. + Contributed by Analog Devices. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, + Boston, MA 02110-1301, USA. */ + +enum gdb_regnum { + /* Core Registers */ + BFIN_R0_REGNUM = 0, + BFIN_R1_REGNUM, + BFIN_R2_REGNUM, + BFIN_R3_REGNUM, + BFIN_R4_REGNUM, + BFIN_R5_REGNUM, + BFIN_R6_REGNUM, + BFIN_R7_REGNUM, + BFIN_P0_REGNUM, + BFIN_P1_REGNUM, + BFIN_P2_REGNUM, + BFIN_P3_REGNUM, + BFIN_P4_REGNUM, + BFIN_P5_REGNUM, + BFIN_SP_REGNUM, + BFIN_FP_REGNUM, + BFIN_I0_REGNUM, + BFIN_I1_REGNUM, + BFIN_I2_REGNUM, + BFIN_I3_REGNUM, + BFIN_M0_REGNUM, + BFIN_M1_REGNUM, + BFIN_M2_REGNUM, + BFIN_M3_REGNUM, + BFIN_B0_REGNUM, + BFIN_B1_REGNUM, + BFIN_B2_REGNUM, + BFIN_B3_REGNUM, + BFIN_L0_REGNUM, + BFIN_L1_REGNUM, + BFIN_L2_REGNUM, + BFIN_L3_REGNUM, + BFIN_A0_DOT_X_REGNUM, + BFIN_A0_DOT_W_REGNUM, + BFIN_A1_DOT_X_REGNUM, + BFIN_A1_DOT_W_REGNUM, + BFIN_ASTAT_REGNUM, + BFIN_RETS_REGNUM, + BFIN_LC0_REGNUM, + BFIN_LT0_REGNUM, + BFIN_LB0_REGNUM, + BFIN_LC1_REGNUM, + BFIN_LT1_REGNUM, + BFIN_LB1_REGNUM, + BFIN_CYCLES_REGNUM, + BFIN_CYCLES2_REGNUM, + BFIN_USP_REGNUM, + BFIN_SEQSTAT_REGNUM, + BFIN_SYSCFG_REGNUM, + BFIN_RETI_REGNUM, + BFIN_RETX_REGNUM, + BFIN_RETN_REGNUM, + BFIN_RETE_REGNUM, + + /* Pseudo Registers */ + BFIN_PC_REGNUM, + BFIN_CC_REGNUM, + BFIN_TEXT_ADDR, /* Address of .text section. */ + BFIN_TEXT_END_ADDR, /* Address of the end of .text section. */ + BFIN_DATA_ADDR, /* Address of .data section. */ + + BFIN_FDPIC_EXEC_REGNUM, + BFIN_FDPIC_INTERP_REGNUM, + + /* MMRs */ + BFIN_IPEND_REGNUM, + + /* LAST ENTRY SHOULD NOT BE CHANGED. */ + BFIN_NUM_REGS /* The number of all registers. */ +}; diff --git a/target-bfin/cpu.c b/target-bfin/cpu.c new file mode 100644 index 0000000000000..6588eb9247058 --- /dev/null +++ b/target-bfin/cpu.c @@ -0,0 +1,193 @@ +/* + * QEMU Blackfin CPU + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "qemu-common.h" +#include "migration/vmstate.h" + +static void bfin_cpu_set_pc(CPUState *cs, vaddr value) +{ + BlackfinCPU *cpu = BFIN_CPU(cs); + + cpu->env.pc = value; +} + +static bool bfin_cpu_has_work(CPUState *cpu) +{ + return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); +} + +/* CPUClass::reset() */ +static void bfin_cpu_reset(CPUState *cs) +{ + BlackfinCPU *cpu = BFIN_CPU(cs); + BlackfinCPUClass *bcc = BFIN_CPU_GET_CLASS(cpu); + CPUArchState *env = &cpu->env; + + bcc->parent_reset(cs); + + tlb_flush(cs, 1); + + env->pc = 0xEF000000; +} + +static void bfin_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + info->mach = bfd_mach_bfin; + info->print_insn = print_insn_bfin; +} + +static void bfin_cpu_initfn(Object *obj) +{ + CPUState *cs = CPU(obj); + BlackfinCPU *cpu = BFIN_CPU(obj); + CPUArchState *env = &cpu->env; + + cs->env_ptr = env; + cpu_exec_init(cs, &error_abort); + + if (tcg_enabled()) { + bfin_translate_init(); + } +} + +static void bfin_cpu_realizefn(DeviceState *dev, Error **errp) +{ + CPUState *cs = CPU(dev); + BlackfinCPUClass *bcc = BFIN_CPU_GET_CLASS(dev); + + cpu_reset(cs); + qemu_init_vcpu(cs); + + bcc->parent_realize(dev, errp); +} + +static ObjectClass *bfin_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + + if (!cpu_model) { + return NULL; + } + + oc = object_class_by_name(cpu_model); + if (!oc || !object_class_dynamic_cast(oc, TYPE_BLACKFIN_CPU) || + object_class_is_abstract(oc)) { + return NULL; + } + return oc; +} + +static void bfin_cpu_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + BlackfinCPUClass *bcc = BFIN_CPU_CLASS(oc); + + bcc->parent_realize = dc->realize; + dc->realize = bfin_cpu_realizefn; + + bcc->parent_reset = cc->reset; + cc->reset = bfin_cpu_reset; + + cc->class_by_name = bfin_cpu_class_by_name; + cc->has_work = bfin_cpu_has_work; + cc->do_interrupt = bfin_cpu_do_interrupt; + cc->set_pc = bfin_cpu_set_pc; + cc->gdb_read_register = bfin_cpu_gdb_read_register; + cc->gdb_write_register = bfin_cpu_gdb_write_register; + cc->dump_state = bfin_cpu_dump_state; + cc->disas_set_info = bfin_cpu_disas_set_info; +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug = bfin_cpu_get_phys_page_debug; + dc->vmsd = &vmstate_bfin_cpu; +#endif +} + +static const TypeInfo bfin_cpu_type_info = { + .name = TYPE_BLACKFIN_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(BlackfinCPU), + .instance_init = bfin_cpu_initfn, + .abstract = true, + .class_size = sizeof(BlackfinCPUClass), + .class_init = bfin_cpu_class_init, +}; + +static void bf5xx_cpu_initfn(Object *obj) +{ +} + +typedef struct BlackfinCPUInfo { + const char *name; + void (*initfn)(Object *obj); + void (*class_init)(ObjectClass *oc, void *data); +} BlackfinCPUInfo; + +static const BlackfinCPUInfo bfin_cpus[] = { + { .name = "bf504", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf506", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf512", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf514", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf516", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf518", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf522", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf523", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf524", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf525", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf526", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf527", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf531", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf532", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf533", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf534", .initfn = bf5xx_cpu_initfn, }, + /*{ .name = "bf535", .initfn = bf5xx_cpu_initfn, },*/ + { .name = "bf536", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf537", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf538", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf539", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf542", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf544", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf547", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf548", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf549", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf561", .initfn = bf5xx_cpu_initfn, }, + { .name = "bf592", .initfn = bf5xx_cpu_initfn, }, +#ifdef CONFIG_USER_ONLY + { .name = "any", .initfn = bf5xx_cpu_initfn, }, +#endif +}; + +static void bfin_cpu_register(const BlackfinCPUInfo *info) +{ + TypeInfo type_info = { + .name = info->name, + .parent = TYPE_BLACKFIN_CPU, + .instance_size = sizeof(BlackfinCPU), + .instance_init = info->initfn, + .class_init = info->class_init, + .class_size = sizeof(BlackfinCPUClass), + }; + + type_register_static(&type_info); +} + +static void bfin_cpu_register_types(void) +{ + size_t i; + + type_register_static(&bfin_cpu_type_info); + for (i = 0; i < ARRAY_SIZE(bfin_cpus); i++) { + bfin_cpu_register(&bfin_cpus[i]); + } +} + +type_init(bfin_cpu_register_types) diff --git a/target-bfin/cpu.h b/target-bfin/cpu.h new file mode 100644 index 0000000000000..3372192caded0 --- /dev/null +++ b/target-bfin/cpu.h @@ -0,0 +1,273 @@ +/* + * Blackfin emulation + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#ifndef CPU_BFIN_H +#define CPU_BFIN_H + +struct DisasContext; + +#define TARGET_LONG_BITS 32 + +#define ELF_MACHINE EM_BLACKFIN + +#define CPUArchState struct CPUBfinState + +#include "qemu-common.h" +#include "exec/cpu-defs.h" + +#define TARGET_HAS_ICE 1 + +/* These exceptions correspond directly to hardware levels. */ +#define EXCP_SYSCALL 0 +#define EXCP_SOFT_BP 1 +#define EXCP_STACK_OVERFLOW 3 +#define EXCP_SINGLE_STEP 0x10 +#define EXCP_TRACE_FULL 0x11 +#define EXCP_UNDEF_INST 0x21 +#define EXCP_ILL_INST 0x22 +#define EXCP_DCPLB_VIOLATE 0x23 +#define EXCP_DATA_MISALGIN 0x24 +#define EXCP_UNRECOVERABLE 0x25 +#define EXCP_DCPLB_MISS 0x26 +#define EXCP_DCPLB_MULT 0x27 +#define EXCP_EMU_WATCH 0x28 +#define EXCP_MISALIG_INST 0x2a +#define EXCP_ICPLB_PROT 0x2b +#define EXCP_ICPLB_MISS 0x2c +#define EXCP_ICPLB_MULT 0x2d +#define EXCP_ILL_SUPV 0x2e +/* These are QEMU internal ones (must be larger than 0xFF). */ +#define EXCP_ABORT 0x100 +#define EXCP_DBGA 0x101 +#define EXCP_OUTC 0x102 +#define EXCP_FIXED_CODE 0x103 + +#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_1 + +#define BFIN_L1_CACHE_BYTES 32 + +/* Blackfin does 1K/4K/1M/4M, but for now only support 4k */ +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 2 + +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + +/* Indexes into astat array; matches bitpos in hardware too */ +enum { + ASTAT_AZ = 0, + ASTAT_AN, + ASTAT_AC0_COPY, + ASTAT_V_COPY, + ASTAT_CC = 5, + ASTAT_AQ, + ASTAT_RND_MOD = 8, + ASTAT_AC0 = 12, + ASTAT_AC1, + ASTAT_AV0 = 16, + ASTAT_AV0S, + ASTAT_AV1, + ASTAT_AV1S, + ASTAT_V = 24, + ASTAT_VS +}; + +typedef struct CPUBfinState { + int personality; + + uint32_t dreg[8]; + uint32_t preg[8]; + uint32_t ireg[4]; + uint32_t mreg[4]; + uint32_t breg[4]; + uint32_t lreg[4]; + uint64_t areg[2]; + uint32_t rets; + uint32_t lcreg[2], ltreg[2], lbreg[2]; + uint32_t cycles[2]; + uint32_t uspreg; + uint32_t seqstat; + uint32_t syscfg; + uint32_t reti; + uint32_t retx; + uint32_t retn; + uint32_t rete; + uint32_t emudat; + uint32_t pc; + + /* ASTAT bits; broken up for speeeeeeeed */ + uint32_t astat[32]; + /* ASTAT delayed helpers */ + uint32_t astat_op, astat_arg[3]; + + CPU_COMMON +} CPUBfinState; +#define spreg preg[6] +#define fpreg preg[7] + +#include "qom/cpu.h" + +#define TYPE_BLACKFIN_CPU "bfin-cpu" + +#define BFIN_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(BlackfinCPUClass, (klass), TYPE_BLACKFIN_CPU) +#define BFIN_CPU(obj) \ + OBJECT_CHECK(BlackfinCPU, (obj), TYPE_BLACKFIN_CPU) +#define BFIN_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(BlackfinCPUClass, (obj), TYPE_BLACKFIN_CPU) + +/** + * BlackfinCPUClass: + * @parent_reset: The parent class' reset handler. + * + * A Blackfin CPU model. + */ +typedef struct BlackfinCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + DeviceRealize parent_realize; + void (*parent_reset)(CPUState *cpu); + + const char *name; +} BlackfinCPUClass; + +/** + * BlackfinCPU: + * @env: #CPUArchState + * + * A Blackfin CPU. + */ +typedef struct BlackfinCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUArchState env; +} BlackfinCPU; + +static inline BlackfinCPU *bfin_env_get_cpu(CPUArchState *env) +{ + return container_of(env, BlackfinCPU, env); +} + +#define ENV_GET_CPU(e) CPU(bfin_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(BlackfinCPU, env) + +#ifndef CONFIG_USER_ONLY +extern const struct VMStateDescription vmstate_bfin_cpu; +#endif + +static inline BlackfinCPU *cpu_bfin_init(const char *cpu_model) +{ + return BFIN_CPU(cpu_generic_init(TYPE_BLACKFIN_CPU, cpu_model)); +} + +#define cpu_init(cpu_model) CPU(cpu_bfin_init(cpu_model)) + +#define cpu_list cpu_bfin_list +#define cpu_signal_handler cpu_bfin_signal_handler + +void bfin_cpu_do_interrupt(CPUState *cpu); + +void bfin_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, + int flags); +hwaddr bfin_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int bfin_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int bfin_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); + +static inline uint32_t bfin_astat_read(CPUArchState *env) +{ + unsigned int i, ret; + + ret = 0; + for (i = 0; i < 32; ++i) { + ret |= (env->astat[i] << i); + } + + return ret; +} + +static inline void bfin_astat_write(CPUArchState *env, uint32_t astat) +{ + unsigned int i; + for (i = 0; i < 32; ++i) { + env->astat[i] = (astat >> i) & 1; + } +} + +enum astat_ops { + ASTAT_OP_NONE, + ASTAT_OP_DYNAMIC, + ASTAT_OP_ABS, + ASTAT_OP_ABS_VECTOR, + ASTAT_OP_ADD16, + ASTAT_OP_ADD32, + ASTAT_OP_ASHIFT16, + ASTAT_OP_ASHIFT32, + ASTAT_OP_COMPARE_SIGNED, + ASTAT_OP_COMPARE_UNSIGNED, + ASTAT_OP_LOGICAL, + ASTAT_OP_LSHIFT16, + ASTAT_OP_LSHIFT32, + ASTAT_OP_LSHIFT_RT16, + ASTAT_OP_LSHIFT_RT32, + ASTAT_OP_MIN_MAX, + ASTAT_OP_MIN_MAX_VECTOR, + ASTAT_OP_NEGATE, + ASTAT_OP_SUB16, + ASTAT_OP_SUB32, + ASTAT_OP_VECTOR_ADD_ADD, /* +|+ */ + ASTAT_OP_VECTOR_ADD_SUB, /* +|- */ + ASTAT_OP_VECTOR_SUB_SUB, /* -|- */ + ASTAT_OP_VECTOR_SUB_ADD, /* -|+ */ +}; + +void cpu_list(FILE *f, fprintf_function cpu_fprintf); +int cpu_bfin_signal_handler(int host_signum, void *pinfo, void *puc); +void bfin_translate_init(void); + +extern const char * const greg_names[]; +extern const char *get_allreg_name(int grp, int reg); + +#include "dv-bfin_cec.h" + +/* */ +#define MMU_MODE0_SUFFIX _kernel +#define MMU_MODE1_SUFFIX _user +#define MMU_USER_IDX 1 +static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +{ + return !cec_is_supervisor_mode(env); +} + +int cpu_bfin_handle_mmu_fault(CPUState *cs, target_ulong address, + MMUAccessType access_type, int mmu_idx); +#define cpu_handle_mmu_fault cpu_bfin_handle_mmu_fault + +#include "exec/cpu-all.h" + +#include "exec/exec-all.h" + +static inline void cpu_pc_from_tb(CPUArchState *env, TranslationBlock *tb) +{ + env->pc = tb->pc; +} + +static inline void cpu_get_tb_cpu_state(CPUArchState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = env->astat[ASTAT_RND_MOD]; +} + +#endif diff --git a/target-bfin/dv-bfin_cec.h b/target-bfin/dv-bfin_cec.h new file mode 100644 index 0000000000000..3f4dbbb7635d8 --- /dev/null +++ b/target-bfin/dv-bfin_cec.h @@ -0,0 +1,5 @@ +#include +static inline bool cec_is_supervisor_mode(CPUBfinState *env) +{ + return true; +} diff --git a/target-bfin/gdbstub.c b/target-bfin/gdbstub.c new file mode 100644 index 0000000000000..0e07341463d5f --- /dev/null +++ b/target-bfin/gdbstub.c @@ -0,0 +1,206 @@ +/* + * QEMU Blackfin CPU + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" +#include "target-bfin/bfin-tdep.h" + +int bfin_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + BlackfinCPU *cpu = BFIN_CPU(cs); + CPUArchState *env = &cpu->env; + uint32_t val; + + switch (n) { + case BFIN_R0_REGNUM ... BFIN_R7_REGNUM: + val = env->dreg[n - BFIN_R0_REGNUM]; + break; + case BFIN_P0_REGNUM ... BFIN_FP_REGNUM: + val = env->preg[n - BFIN_P0_REGNUM]; + break; + case BFIN_I0_REGNUM ... BFIN_I3_REGNUM: + val = env->ireg[n - BFIN_I0_REGNUM]; + break; + case BFIN_M0_REGNUM ... BFIN_M3_REGNUM: + val = env->mreg[n - BFIN_M0_REGNUM]; + break; + case BFIN_B0_REGNUM ... BFIN_B3_REGNUM: + val = env->breg[n - BFIN_B0_REGNUM]; + break; + case BFIN_L0_REGNUM ... BFIN_L3_REGNUM: + val = env->lreg[n - BFIN_L0_REGNUM]; + break; + case BFIN_A0_DOT_X_REGNUM: + val = (env->areg[0] >> 32) & 0xff; + break; + case BFIN_A0_DOT_W_REGNUM: + val = env->areg[0]; + break; + case BFIN_A1_DOT_X_REGNUM: + val = (env->areg[1] >> 32) & 0xff; + break; + case BFIN_A1_DOT_W_REGNUM: + val = env->areg[1]; + break; + case BFIN_ASTAT_REGNUM: + val = bfin_astat_read(env); + break; + case BFIN_RETS_REGNUM: + val = env->rets; + break; + case BFIN_LC0_REGNUM: + val = env->lcreg[0]; + break; + case BFIN_LT0_REGNUM: + val = env->ltreg[0]; + break; + case BFIN_LB0_REGNUM: + val = env->lbreg[0]; + break; + case BFIN_LC1_REGNUM: + val = env->lcreg[1]; + break; + case BFIN_LT1_REGNUM: + val = env->ltreg[1]; + break; + case BFIN_LB1_REGNUM: + val = env->lbreg[1]; + break; + case BFIN_CYCLES_REGNUM ... BFIN_CYCLES2_REGNUM: + val = env->cycles[n - BFIN_CYCLES_REGNUM]; + break; + case BFIN_USP_REGNUM: + val = env->uspreg; + break; + case BFIN_SEQSTAT_REGNUM: + val = env->seqstat; + break; + case BFIN_SYSCFG_REGNUM: + val = env->syscfg; + break; + case BFIN_RETI_REGNUM: + val = env->reti; + break; + case BFIN_RETX_REGNUM: + val = env->retx; + break; + case BFIN_RETN_REGNUM: + val = env->retn; + break; + case BFIN_RETE_REGNUM: + val = env->rete; + break; + case BFIN_PC_REGNUM: + val = env->pc; + break; + default: + return 0; + } + + return gdb_get_regl(mem_buf, val); +} + +int bfin_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + BlackfinCPU *cpu = BFIN_CPU(cs); + CPUArchState *env = &cpu->env; + target_ulong tmpl; + int r = 4; + + tmpl = ldtul_p(mem_buf); + + switch (n) { + case BFIN_R0_REGNUM ... BFIN_R7_REGNUM: + env->dreg[n - BFIN_R0_REGNUM] = tmpl; + break; + case BFIN_P0_REGNUM ... BFIN_FP_REGNUM: + env->preg[n - BFIN_P0_REGNUM] = tmpl; + break; + case BFIN_I0_REGNUM ... BFIN_I3_REGNUM: + env->ireg[n - BFIN_I0_REGNUM] = tmpl; + break; + case BFIN_M0_REGNUM ... BFIN_M3_REGNUM: + env->mreg[n - BFIN_M0_REGNUM] = tmpl; + break; + case BFIN_B0_REGNUM ... BFIN_B3_REGNUM: + env->breg[n - BFIN_B0_REGNUM] = tmpl; + break; + case BFIN_L0_REGNUM ... BFIN_L3_REGNUM: + env->lreg[n - BFIN_L0_REGNUM] = tmpl; + break; + case BFIN_A0_DOT_X_REGNUM: + env->areg[0] = (env->areg[0] & 0xffffffff) | ((uint64_t)tmpl << 32); + break; + case BFIN_A0_DOT_W_REGNUM: + env->areg[0] = (env->areg[0] & ~0xffffffff) | tmpl; + break; + case BFIN_A1_DOT_X_REGNUM: + env->areg[1] = (env->areg[1] & 0xffffffff) | ((uint64_t)tmpl << 32); + break; + case BFIN_A1_DOT_W_REGNUM: + env->areg[1] = (env->areg[1] & ~0xffffffff) | tmpl; + break; + case BFIN_ASTAT_REGNUM: + bfin_astat_write(env, tmpl); + break; + case BFIN_RETS_REGNUM: + env->rets = tmpl; + break; + case BFIN_LC0_REGNUM: + env->lcreg[0] = tmpl; + break; + case BFIN_LT0_REGNUM: + env->ltreg[0] = tmpl; + break; + case BFIN_LB0_REGNUM: + env->lbreg[0] = tmpl; + break; + case BFIN_LC1_REGNUM: + env->lcreg[1] = tmpl; + break; + case BFIN_LT1_REGNUM: + env->ltreg[1] = tmpl; + break; + case BFIN_LB1_REGNUM: + env->lbreg[1] = tmpl; + break; + case BFIN_CYCLES_REGNUM ... BFIN_CYCLES2_REGNUM: + env->cycles[n - BFIN_CYCLES_REGNUM] = tmpl; + break; + case BFIN_USP_REGNUM: + env->uspreg = tmpl; + break; + case BFIN_SEQSTAT_REGNUM: + env->seqstat = tmpl; + break; + case BFIN_SYSCFG_REGNUM: + env->syscfg = tmpl; + break; + case BFIN_RETI_REGNUM: + env->reti = tmpl; + break; + case BFIN_RETX_REGNUM: + env->retx = tmpl; + break; + case BFIN_RETN_REGNUM: + env->retn = tmpl; + break; + case BFIN_RETE_REGNUM: + env->rete = tmpl; + break; + case BFIN_PC_REGNUM: + env->pc = tmpl; + break; + default: + return 0; + } + + return r; +} diff --git a/target-bfin/helper.c b/target-bfin/helper.c new file mode 100644 index 0000000000000..b7eb3769085f6 --- /dev/null +++ b/target-bfin/helper.c @@ -0,0 +1,115 @@ +/* + * Blackfin helpers + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" + +#include "cpu.h" +#include "exec/exec-all.h" +#include "qemu/host-utils.h" + +#if defined(CONFIG_USER_ONLY) + +void bfin_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index = -1; +} + +int cpu_handle_mmu_fault(CPUState *cs, target_ulong address, + MMUAccessType access_type, int mmu_idx) +{ + cs->exception_index = EXCP_DCPLB_VIOLATE; + return 1; +} + +#else + +void bfin_cpu_do_interrupt(CPUState *cs) +{ + BlackfinCPU *cpu = BFIN_CPU(cs); + CPUBfinState *env = &cpu->env; + + qemu_log_mask(CPU_LOG_INT, + "exception at pc=%x type=%x\n", env->pc, cs->exception_index); + + switch (cs->exception_index) { + default: + cpu_abort(cs, "unhandled exception type=%d\n", + cs->exception_index); + break; + } +} + +hwaddr bfin_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + return addr & TARGET_PAGE_MASK; +} + +int cpu_handle_mmu_fault(CPUState *cs, target_ulong address, + MMUAccessType access_type, int mmu_idx) +{ + int prot; + + /* XXX: walk the CPLB tables here */ +#if 0 + static const char * const rw_map[] = { "read", "write", "exec", }; + + printf("%s: %5s @ " TARGET_FMT_lx " (mmu_idx=%i)\n", + __func__, rw_map[access_type], address, mmu_idx); +#endif + + address &= TARGET_PAGE_MASK; + prot = PAGE_BITS; + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + + return 0; +} + +#endif + +/* Sort alphabetically by type name, except for "any". */ +static gint cpu_list_compare(gconstpointer a, gconstpointer b) +{ + ObjectClass *class_a = (ObjectClass *)a; + ObjectClass *class_b = (ObjectClass *)b; + const char *name_a, *name_b; + + name_a = object_class_get_name(class_a); + name_b = object_class_get_name(class_b); + if (strcmp(name_a, "any") == 0) { + return 1; + } else if (strcmp(name_b, "any") == 0) { + return -1; + } else { + return strcmp(name_a, name_b); + } +} + +static void cpu_list_entry(gpointer data, gpointer user_data) +{ + ObjectClass *oc = data; + CPUListState *s = user_data; + + (*s->cpu_fprintf)(s->file, " %s\n", + object_class_get_name(oc)); +} + +void cpu_bfin_list(FILE *f, fprintf_function cpu_fprintf) +{ + CPUListState s = { + .file = f, + .cpu_fprintf = cpu_fprintf, + }; + GSList *list; + + list = object_class_get_list(TYPE_BLACKFIN_CPU, false); + list = g_slist_sort(list, cpu_list_compare); + (*cpu_fprintf)(f, "Available CPUs:\n"); + g_slist_foreach(list, cpu_list_entry, &s); + g_slist_free(list); +} diff --git a/target-bfin/helper.h b/target-bfin/helper.h new file mode 100644 index 0000000000000..0c8b12bd037f1 --- /dev/null +++ b/target-bfin/helper.h @@ -0,0 +1,32 @@ +/* + * Blackfin helpers + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +DEF_HELPER_FLAGS_3(raise_exception, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_5(memalign, TCG_CALL_NO_WG, void, env, i32, i32, i32, i32) +DEF_HELPER_FLAGS_2(require_supervisor, TCG_CALL_NO_WG, void, env, i32) + +DEF_HELPER_FLAGS_4(dbga_l, TCG_CALL_NO_WG, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(dbga_h, TCG_CALL_NO_WG, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_1(outc, TCG_CALL_NO_RWG, void, i32) +DEF_HELPER_FLAGS_3(dbg, TCG_CALL_NO_RWG, void, i32, i32, i32) +DEF_HELPER_FLAGS_2(dbg_areg, TCG_CALL_NO_RWG, void, i64, i32) + +DEF_HELPER_FLAGS_1(astat_load, TCG_CALL_NO_WG_SE, i32, env) +DEF_HELPER_2(astat_store, void, env, i32) + +DEF_HELPER_FLAGS_1(cycles_read, TCG_CALL_NO_SE, i32, env) + +DEF_HELPER_FLAGS_1(ones, TCG_CALL_NO_RWG_SE, i32, i32) +DEF_HELPER_FLAGS_1(signbits_16, TCG_CALL_NO_RWG_SE, i32, i32) +DEF_HELPER_FLAGS_1(signbits_32, TCG_CALL_NO_RWG_SE, i32, i32) +DEF_HELPER_FLAGS_1(signbits_40, TCG_CALL_NO_RWG_SE, i32, i64) + +DEF_HELPER_FLAGS_4(dagadd, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32) +DEF_HELPER_FLAGS_4(dagsub, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32) +DEF_HELPER_FLAGS_2(add_brev, TCG_CALL_NO_RWG_SE, i32, i32, i32) diff --git a/target-bfin/linux-fixed-code.h b/target-bfin/linux-fixed-code.h new file mode 100644 index 0000000000000..a6dddc415c6db --- /dev/null +++ b/target-bfin/linux-fixed-code.h @@ -0,0 +1,23 @@ +/* DO NOT EDIT: Autogenerated. */ +/* Fixed code region of Linux userspace starting at 0x400. Last produced + from Linux-2.6.37 (not that the fixed code region changes often). */ +static const unsigned char bfin_linux_fixed_code[] = { +0x28, 0xe1, 0xad, 0x00, 0xa0, 0x00, 0x00, 0x20, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x91, 0x01, 0x93, 0x10, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x91, 0x08, 0x08, 0x02, 0x10, 0x02, 0x93, +0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x01, 0x91, 0x01, 0x50, 0x00, 0x93, 0x10, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x01, 0x91, 0x01, 0x52, 0x00, 0x93, 0x10, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x01, 0x91, 0x01, 0x56, 0x00, 0x93, 0x10, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x01, 0x91, 0x01, 0x54, 0x00, 0x93, 0x10, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x01, 0x91, 0x01, 0x58, 0x00, 0x93, 0x10, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; diff --git a/target-bfin/machine.c b/target-bfin/machine.c new file mode 100644 index 0000000000000..a204ee8a3f804 --- /dev/null +++ b/target-bfin/machine.c @@ -0,0 +1,53 @@ +/* + * Blackfin cpu save/load logic + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/boards.h" + +#define VMSTATE_AUTO32_ARRAY(member) \ + VMSTATE_UINT32_ARRAY(member, CPUArchState, ARRAY_SIZE(((CPUArchState *)NULL)->member)) +#define VMSTATE_AUTO64_ARRAY(member) \ + VMSTATE_UINT64_ARRAY(member, CPUArchState, ARRAY_SIZE(((CPUArchState *)NULL)->member)) +#define _VMSTATE_UINT32(member) \ + VMSTATE_UINT32(member, CPUArchState) +const VMStateDescription vmstate_bfin_cpu = { + .name = "cpu", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_AUTO32_ARRAY(dreg), + VMSTATE_AUTO32_ARRAY(preg), + VMSTATE_AUTO32_ARRAY(ireg), + VMSTATE_AUTO32_ARRAY(mreg), + VMSTATE_AUTO32_ARRAY(breg), + VMSTATE_AUTO32_ARRAY(lreg), + VMSTATE_AUTO64_ARRAY(areg), + _VMSTATE_UINT32(rets), + VMSTATE_AUTO32_ARRAY(lcreg), + VMSTATE_AUTO32_ARRAY(ltreg), + VMSTATE_AUTO32_ARRAY(lbreg), + VMSTATE_AUTO32_ARRAY(cycles), + _VMSTATE_UINT32(uspreg), + _VMSTATE_UINT32(seqstat), + _VMSTATE_UINT32(syscfg), + _VMSTATE_UINT32(reti), + _VMSTATE_UINT32(retx), + _VMSTATE_UINT32(retn), + _VMSTATE_UINT32(rete), + _VMSTATE_UINT32(emudat), + _VMSTATE_UINT32(pc), + VMSTATE_AUTO32_ARRAY(astat), + _VMSTATE_UINT32(astat_op), + VMSTATE_AUTO32_ARRAY(astat_arg), + VMSTATE_END_OF_LIST() + } +}; diff --git a/target-bfin/monitor.c b/target-bfin/monitor.c new file mode 100644 index 0000000000000..1cf80230aeddf --- /dev/null +++ b/target-bfin/monitor.c @@ -0,0 +1,80 @@ +/* + * QEMU Blackfin CPU + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "monitor/monitor.h" +#include "monitor/hmp-target.h" +#include "hmp.h" + +const MonitorDef monitor_defs[] = { +#define _REG(name, var) { name, offsetof(CPUArchState, var) } +#define REG(name) _REG(#name, name) +#define _REG_ARR(name, idx, arr) _REG(#name #idx, arr[idx]) +#define REG_ARR(name, idx) _REG_ARR(name, idx, name##reg) + _REG_ARR(r, 0, dreg), + _REG_ARR(r, 1, dreg), + _REG_ARR(r, 2, dreg), + _REG_ARR(r, 3, dreg), + _REG_ARR(r, 4, dreg), + _REG_ARR(r, 5, dreg), + _REG_ARR(r, 6, dreg), + _REG_ARR(r, 7, dreg), + REG_ARR(p, 0), + REG_ARR(p, 1), + REG_ARR(p, 2), + REG_ARR(p, 3), + REG_ARR(p, 4), + REG_ARR(p, 5), + REG_ARR(i, 0), + REG_ARR(i, 1), + REG_ARR(i, 2), + REG_ARR(i, 3), + REG_ARR(m, 0), + REG_ARR(m, 1), + REG_ARR(m, 2), + REG_ARR(m, 3), + REG_ARR(b, 0), + REG_ARR(b, 1), + REG_ARR(b, 2), + REG_ARR(b, 3), + REG_ARR(l, 0), + REG_ARR(l, 1), + REG_ARR(l, 2), + REG_ARR(l, 3), + REG(rets), + REG_ARR(lc, 0), + REG_ARR(lc, 1), + REG_ARR(lt, 0), + REG_ARR(lt, 1), + REG_ARR(lb, 0), + REG_ARR(lb, 1), + _REG_ARR(cycles, 0, cycles), + _REG_ARR(cycles, 1, cycles), + _REG("usp", uspreg), + _REG("fp", fpreg), + _REG("sp", spreg), + REG(seqstat), + REG(syscfg), + REG(reti), + REG(retx), + REG(retn), + REG(rete), + REG(emudat), + REG(pc), +#undef REG_ARR +#undef _REG_ARR +#undef REG +#undef _REG +}; + +const MonitorDef *target_monitor_defs(void) +{ + return monitor_defs; +} diff --git a/target-bfin/op_helper.c b/target-bfin/op_helper.c new file mode 100644 index 0000000000000..5b80aea23bc69 --- /dev/null +++ b/target-bfin/op_helper.c @@ -0,0 +1,294 @@ +/* + * Blackfin helpers + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "cpu.h" +#include "exec/helper-proto.h" + +#if !defined(CONFIG_USER_ONLY) + +/* Try to fill the TLB and return an exception if error. If retaddr is + NULL, it means that the function was called in C code (i.e. not + from generated code or from helper.c) */ +/* XXX: fix it to restore all registers */ +void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + int ret; + + ret = cpu_bfin_handle_mmu_fault(cs, addr, access_type, mmu_idx); + if (unlikely(ret)) { + if (retaddr) { + /* now we have a real cpu fault */ + if (cpu_restore_state(cs, retaddr)) { + /* XXX: something!? */ + } + } + cpu_loop_exit(cs); + } +} + +#endif + +void HELPER(raise_exception)(CPUArchState *env, uint32_t excp, uint32_t pc) +{ + BlackfinCPU *cpu = bfin_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; + if (pc != -1) { + env->pc = pc; + } + cpu_loop_exit(cs); +} + +void HELPER(memalign)(CPUArchState *env, uint32_t excp, uint32_t pc, + uint32_t addr, uint32_t len) +{ + if ((addr & (len - 1)) == 0) { + return; + } + + HELPER(raise_exception)(env, excp, pc); +} + +void HELPER(require_supervisor)(CPUArchState *env, uint32_t pc) +{ + if (!cec_is_supervisor_mode(env)) + HELPER(raise_exception)(env, EXCP_ILL_SUPV, pc); +} + +void HELPER(dbga_l)(CPUArchState *env, uint32_t pc, uint32_t actual, + uint32_t expected) +{ + if ((actual & 0xffff) != expected) { + HELPER(raise_exception)(env, EXCP_DBGA, pc); + } +} + +void HELPER(dbga_h)(CPUArchState *env, uint32_t pc, uint32_t actual, + uint32_t expected) +{ + if ((actual >> 16) != expected) { + HELPER(raise_exception)(env, EXCP_DBGA, pc); + } +} + +void HELPER(outc)(uint32_t ch) +{ + putc(ch, stdout); + if (ch == '\n') { + fflush(stdout); + } +} + +void HELPER(dbg)(uint32_t val, uint32_t grp, uint32_t reg) +{ + printf("DBG : %s = 0x%08x\n", get_allreg_name(grp, reg), val); +} + +void HELPER(dbg_areg)(uint64_t val, uint32_t areg) +{ + printf("DBG : A%u = 0x%010"PRIx64"\n", areg, (val << 24) >> 24); +} + +uint32_t HELPER(astat_load)(CPUArchState *env) +{ + return bfin_astat_read(env); +} + +void HELPER(astat_store)(CPUArchState *env, uint32_t astat) +{ + bfin_astat_write(env, astat); +} + +/* XXX: This isn't entirely accurate. A write to CYCLES should reset it to 0. + So this code really should be returning CYCLES + clock offset. */ +uint32_t HELPER(cycles_read)(CPUArchState *env) +{ + uint64_t cycles; + +#ifndef CONFIG_USER_ONLY + cycles = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); +#else + cycles = cpu_get_host_ticks(); +#endif + + env->cycles[1] = cycles >> 32; + env->cycles[0] = cycles; + return env->cycles[0]; +} + +/* Count the number of bits set to 1 in the 32bit value. */ +uint32_t HELPER(ones)(uint32_t val) +{ + return ctpopl(val); +} + +/* Count number of leading bits that match the sign bit. */ +uint32_t HELPER(signbits_16)(uint32_t val) +{ + uint32_t bit = val & (1 << 15); + return (bit ? clo16(val) : clz16(val)) - 1; +} + +/* Count number of leading bits that match the sign bit. */ +uint32_t HELPER(signbits_32)(uint32_t val) +{ + uint32_t bit = val & (1 << 31); + return (bit ? clo32(val) : clz32(val)) - 1; +} + +/* Count number of leading bits that match the sign bit. + This ignores the top 24 bits entirely, so it should always be safe. */ +uint32_t HELPER(signbits_40)(uint64_t val) +{ + uint64_t bit = val & (1ULL << 39); + uint32_t cnt = 0; + + if (bit) { + val = ~val; + } + + /* Binary search for the leading one bit. */ + if (!(val & 0xFFFFF00000ULL)) { + cnt += 20; + val <<= 20; + } + if (!(val & 0xFFC0000000ULL)) { + cnt += 10; + val <<= 10; + } + if (!(val & 0xF800000000ULL)) { + cnt += 5; + val <<= 5; + } + if (!(val & 0xE000000000ULL)) { + cnt += 3; + val <<= 3; + } + if (!(val & 0x8000000000ULL)) { + cnt++; + val <<= 1; + } + if (!(val & 0x8000000000ULL)) { + cnt++; + } + + return cnt - 9; +} + +/* This is a bit crazy, but we want to simulate the hardware behavior exactly + rather than worry about the circular buffers being used correctly. Which + isn't to say there isn't room for improvement here, just that we want to + be conservative. See also dagsub(). */ +uint32_t HELPER(dagadd)(uint32_t I, uint32_t L, uint32_t B, uint32_t M) +{ + uint64_t i = I; + uint64_t l = L; + uint64_t b = B; + uint64_t m = M; + + uint64_t LB, IM, IML; + uint32_t im32, iml32, lb32, res; + uint64_t msb, car; + + msb = (uint64_t)1 << 31; + car = (uint64_t)1 << 32; + + IM = i + m; + im32 = IM; + LB = l + b; + lb32 = LB; + + if ((int32_t)M < 0) { + IML = i + m + l; + iml32 = IML; + if ((i & msb) || (IM & car)) { + res = (im32 < b) ? iml32 : im32; + } else { + res = (im32 < b) ? im32 : iml32; + } + } else { + IML = i + m - l; + iml32 = IML; + if ((IM & car) == (LB & car)) { + res = (im32 < lb32) ? im32 : iml32; + } else { + res = (im32 < lb32) ? iml32 : im32; + } + } + + return res; +} + +/* See dagadd() notes above. */ +uint32_t HELPER(dagsub)(uint32_t I, uint32_t L, uint32_t B, uint32_t M) +{ + uint64_t i = I; + uint64_t l = L; + uint64_t b = B; + uint64_t m = M; + + uint64_t mbar = (uint32_t)(~m + 1); + uint64_t LB, IM, IML; + uint32_t b32, im32, iml32, lb32, res; + uint64_t msb, car; + + msb = (uint64_t)1 << 31; + car = (uint64_t)1 << 32; + + IM = i + mbar; + im32 = IM; + LB = l + b; + lb32 = LB; + + if ((int32_t)M < 0) { + IML = i + mbar - l; + iml32 = IML; + if (!!((i & msb) && (IM & car)) == !!(LB & car)) { + res = (im32 < lb32) ? im32 : iml32; + } else { + res = (im32 < lb32) ? iml32 : im32; + } + } else { + IML = i + mbar + l; + iml32 = IML; + b32 = b; + if (M == 0 || IM & car) { + res = (im32 < b32) ? iml32 : im32; + } else { + res = (im32 < b32) ? im32 : iml32; + } + } + + return res; +} + +uint32_t HELPER(add_brev)(uint32_t addend1, uint32_t addend2) +{ + uint32_t mask, b, r; + int i, cy; + + mask = 0x80000000; + r = 0; + cy = 0; + + for (i = 31; i >= 0; --i) { + b = ((addend1 & mask) >> i) + ((addend2 & mask) >> i); + b += cy; + cy = b >> 1; + b &= 1; + r |= b << i; + mask >>= 1; + } + + return r; +} diff --git a/target-bfin/opcode/bfin.h b/target-bfin/opcode/bfin.h new file mode 100644 index 0000000000000..21ddfab574518 --- /dev/null +++ b/target-bfin/opcode/bfin.h @@ -0,0 +1,1754 @@ +/* bfin.h -- Header file for ADI Blackfin opcode table + Copyright 2005 Free Software Foundation, Inc. + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef OPCODE_BFIN_H +#define OPCODE_BFIN_H + +/* Common to all DSP32 instructions. */ +#define BIT_MULTI_INS 0x0800 + +/* This just sets the multi instruction bit of a DSP32 instruction. */ +#define SET_MULTI_INSTRUCTION_BIT(x) x->value |= BIT_MULTI_INS; + + +/* DSP instructions (32 bit) */ + +/* mmod field. */ +#define M_S2RND 1 +#define M_T 2 +#define M_W32 3 +#define M_FU 4 +#define M_TFU 6 +#define M_IS 8 +#define M_ISS2 9 +#define M_IH 11 +#define M_IU 12 + +static inline int is_macmod_pmove(int x) +{ + return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_S2RND) + || (x == M_ISS2) || (x == M_IU); +} + +static inline int is_macmod_hmove(int x) +{ + return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_IU) || (x == M_T) + || (x == M_TFU) || (x == M_S2RND) || (x == M_ISS2) || (x == M_IH); +} + +/* dsp32mac ++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| +|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......| ++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_src1; + int mask_src1; + int bits_src0; + int mask_src0; + int bits_dst; + int mask_dst; + int bits_h10; + int mask_h10; + int bits_h00; + int mask_h00; + int bits_op0; + int mask_op0; + int bits_w0; + int mask_w0; + int bits_h11; + int mask_h11; + int bits_h01; + int mask_h01; + int bits_op1; + int mask_op1; + int bits_w1; + int mask_w1; + int bits_P; + int mask_P; + int bits_MM; + int mask_MM; + int bits_mmod; + int mask_mmod; + int bits_code2; + int mask_code2; + int bits_M; + int mask_M; + int bits_code; + int mask_code; +} DSP32Mac; + +#define DSP32Mac_opcode 0xc0000000 +#define DSP32Mac_src1_bits 0 +#define DSP32Mac_src1_mask 0x7 +#define DSP32Mac_src0_bits 3 +#define DSP32Mac_src0_mask 0x7 +#define DSP32Mac_dst_bits 6 +#define DSP32Mac_dst_mask 0x7 +#define DSP32Mac_h10_bits 9 +#define DSP32Mac_h10_mask 0x1 +#define DSP32Mac_h00_bits 10 +#define DSP32Mac_h00_mask 0x1 +#define DSP32Mac_op0_bits 11 +#define DSP32Mac_op0_mask 0x3 +#define DSP32Mac_w0_bits 13 +#define DSP32Mac_w0_mask 0x1 +#define DSP32Mac_h11_bits 14 +#define DSP32Mac_h11_mask 0x1 +#define DSP32Mac_h01_bits 15 +#define DSP32Mac_h01_mask 0x1 +#define DSP32Mac_op1_bits 16 +#define DSP32Mac_op1_mask 0x3 +#define DSP32Mac_w1_bits 18 +#define DSP32Mac_w1_mask 0x1 +#define DSP32Mac_p_bits 19 +#define DSP32Mac_p_mask 0x1 +#define DSP32Mac_MM_bits 20 +#define DSP32Mac_MM_mask 0x1 +#define DSP32Mac_mmod_bits 21 +#define DSP32Mac_mmod_mask 0xf +#define DSP32Mac_code2_bits 25 +#define DSP32Mac_code2_mask 0x3 +#define DSP32Mac_M_bits 27 +#define DSP32Mac_M_mask 0x1 +#define DSP32Mac_code_bits 28 +#define DSP32Mac_code_mask 0xf + +#define init_DSP32Mac \ +{ \ + DSP32Mac_opcode, \ + DSP32Mac_src1_bits, DSP32Mac_src1_mask, \ + DSP32Mac_src0_bits, DSP32Mac_src0_mask, \ + DSP32Mac_dst_bits, DSP32Mac_dst_mask, \ + DSP32Mac_h10_bits, DSP32Mac_h10_mask, \ + DSP32Mac_h00_bits, DSP32Mac_h00_mask, \ + DSP32Mac_op0_bits, DSP32Mac_op0_mask, \ + DSP32Mac_w0_bits, DSP32Mac_w0_mask, \ + DSP32Mac_h11_bits, DSP32Mac_h11_mask, \ + DSP32Mac_h01_bits, DSP32Mac_h01_mask, \ + DSP32Mac_op1_bits, DSP32Mac_op1_mask, \ + DSP32Mac_w1_bits, DSP32Mac_w1_mask, \ + DSP32Mac_p_bits, DSP32Mac_p_mask, \ + DSP32Mac_MM_bits, DSP32Mac_MM_mask, \ + DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \ + DSP32Mac_code2_bits, DSP32Mac_code2_mask, \ + DSP32Mac_M_bits, DSP32Mac_M_mask, \ + DSP32Mac_code_bits, DSP32Mac_code_mask \ +}; + +/* dsp32mult ++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| +|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......| ++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ +*/ + +typedef DSP32Mac DSP32Mult; +#define DSP32Mult_opcode 0xc2000000 + +#define init_DSP32Mult \ +{ \ + DSP32Mult_opcode, \ + DSP32Mac_src1_bits, DSP32Mac_src1_mask, \ + DSP32Mac_src0_bits, DSP32Mac_src0_mask, \ + DSP32Mac_dst_bits, DSP32Mac_dst_mask, \ + DSP32Mac_h10_bits, DSP32Mac_h10_mask, \ + DSP32Mac_h00_bits, DSP32Mac_h00_mask, \ + DSP32Mac_op0_bits, DSP32Mac_op0_mask, \ + DSP32Mac_w0_bits, DSP32Mac_w0_mask, \ + DSP32Mac_h11_bits, DSP32Mac_h11_mask, \ + DSP32Mac_h01_bits, DSP32Mac_h01_mask, \ + DSP32Mac_op1_bits, DSP32Mac_op1_mask, \ + DSP32Mac_w1_bits, DSP32Mac_w1_mask, \ + DSP32Mac_p_bits, DSP32Mac_p_mask, \ + DSP32Mac_MM_bits, DSP32Mac_MM_mask, \ + DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \ + DSP32Mac_code2_bits, DSP32Mac_code2_mask, \ + DSP32Mac_M_bits, DSP32Mac_M_mask, \ + DSP32Mac_code_bits, DSP32Mac_code_mask \ +}; + +/* dsp32alu ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| +|.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_src1; + int mask_src1; + int bits_src0; + int mask_src0; + int bits_dst1; + int mask_dst1; + int bits_dst0; + int mask_dst0; + int bits_x; + int mask_x; + int bits_s; + int mask_s; + int bits_aop; + int mask_aop; + int bits_aopcde; + int mask_aopcde; + int bits_HL; + int mask_HL; + int bits_dontcare; + int mask_dontcare; + int bits_code2; + int mask_code2; + int bits_M; + int mask_M; + int bits_code; + int mask_code; +} DSP32Alu; + +#define DSP32Alu_opcode 0xc4000000 +#define DSP32Alu_src1_bits 0 +#define DSP32Alu_src1_mask 0x7 +#define DSP32Alu_src0_bits 3 +#define DSP32Alu_src0_mask 0x7 +#define DSP32Alu_dst1_bits 6 +#define DSP32Alu_dst1_mask 0x7 +#define DSP32Alu_dst0_bits 9 +#define DSP32Alu_dst0_mask 0x7 +#define DSP32Alu_x_bits 12 +#define DSP32Alu_x_mask 0x1 +#define DSP32Alu_s_bits 13 +#define DSP32Alu_s_mask 0x1 +#define DSP32Alu_aop_bits 14 +#define DSP32Alu_aop_mask 0x3 +#define DSP32Alu_aopcde_bits 16 +#define DSP32Alu_aopcde_mask 0x1f +#define DSP32Alu_HL_bits 21 +#define DSP32Alu_HL_mask 0x1 +#define DSP32Alu_dontcare_bits 22 +#define DSP32Alu_dontcare_mask 0x7 +#define DSP32Alu_code2_bits 25 +#define DSP32Alu_code2_mask 0x3 +#define DSP32Alu_M_bits 27 +#define DSP32Alu_M_mask 0x1 +#define DSP32Alu_code_bits 28 +#define DSP32Alu_code_mask 0xf + +#define init_DSP32Alu \ +{ \ + DSP32Alu_opcode, \ + DSP32Alu_src1_bits, DSP32Alu_src1_mask, \ + DSP32Alu_src0_bits, DSP32Alu_src0_mask, \ + DSP32Alu_dst1_bits, DSP32Alu_dst1_mask, \ + DSP32Alu_dst0_bits, DSP32Alu_dst0_mask, \ + DSP32Alu_x_bits, DSP32Alu_x_mask, \ + DSP32Alu_s_bits, DSP32Alu_s_mask, \ + DSP32Alu_aop_bits, DSP32Alu_aop_mask, \ + DSP32Alu_aopcde_bits, DSP32Alu_aopcde_mask, \ + DSP32Alu_HL_bits, DSP32Alu_HL_mask, \ + DSP32Alu_dontcare_bits, DSP32Alu_dontcare_mask, \ + DSP32Alu_code2_bits, DSP32Alu_code2_mask, \ + DSP32Alu_M_bits, DSP32Alu_M_mask, \ + DSP32Alu_code_bits, DSP32Alu_code_mask \ +}; + +/* dsp32shift ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| +|.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_src1; + int mask_src1; + int bits_src0; + int mask_src0; + int bits_dst1; + int mask_dst1; + int bits_dst0; + int mask_dst0; + int bits_HLs; + int mask_HLs; + int bits_sop; + int mask_sop; + int bits_sopcde; + int mask_sopcde; + int bits_dontcare; + int mask_dontcare; + int bits_code2; + int mask_code2; + int bits_M; + int mask_M; + int bits_code; + int mask_code; +} DSP32Shift; + +#define DSP32Shift_opcode 0xc6000000 +#define DSP32Shift_src1_bits 0 +#define DSP32Shift_src1_mask 0x7 +#define DSP32Shift_src0_bits 3 +#define DSP32Shift_src0_mask 0x7 +#define DSP32Shift_dst1_bits 6 +#define DSP32Shift_dst1_mask 0x7 +#define DSP32Shift_dst0_bits 9 +#define DSP32Shift_dst0_mask 0x7 +#define DSP32Shift_HLs_bits 12 +#define DSP32Shift_HLs_mask 0x3 +#define DSP32Shift_sop_bits 14 +#define DSP32Shift_sop_mask 0x3 +#define DSP32Shift_sopcde_bits 16 +#define DSP32Shift_sopcde_mask 0x1f +#define DSP32Shift_dontcare_bits 21 +#define DSP32Shift_dontcare_mask 0x3 +#define DSP32Shift_code2_bits 23 +#define DSP32Shift_code2_mask 0xf +#define DSP32Shift_M_bits 27 +#define DSP32Shift_M_mask 0x1 +#define DSP32Shift_code_bits 28 +#define DSP32Shift_code_mask 0xf + +#define init_DSP32Shift \ +{ \ + DSP32Shift_opcode, \ + DSP32Shift_src1_bits, DSP32Shift_src1_mask, \ + DSP32Shift_src0_bits, DSP32Shift_src0_mask, \ + DSP32Shift_dst1_bits, DSP32Shift_dst1_mask, \ + DSP32Shift_dst0_bits, DSP32Shift_dst0_mask, \ + DSP32Shift_HLs_bits, DSP32Shift_HLs_mask, \ + DSP32Shift_sop_bits, DSP32Shift_sop_mask, \ + DSP32Shift_sopcde_bits, DSP32Shift_sopcde_mask, \ + DSP32Shift_dontcare_bits, DSP32Shift_dontcare_mask, \ + DSP32Shift_code2_bits, DSP32Shift_code2_mask, \ + DSP32Shift_M_bits, DSP32Shift_M_mask, \ + DSP32Shift_code_bits, DSP32Shift_code_mask \ +}; + +/* dsp32shiftimm ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| +|.sop...|.HLs...|.dst0......|.immag.................|.src1......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_src1; + int mask_src1; + int bits_immag; + int mask_immag; + int bits_dst0; + int mask_dst0; + int bits_HLs; + int mask_HLs; + int bits_sop; + int mask_sop; + int bits_sopcde; + int mask_sopcde; + int bits_dontcare; + int mask_dontcare; + int bits_code2; + int mask_code2; + int bits_M; + int mask_M; + int bits_code; + int mask_code; +} DSP32ShiftImm; + +#define DSP32ShiftImm_opcode 0xc6800000 +#define DSP32ShiftImm_src1_bits 0 +#define DSP32ShiftImm_src1_mask 0x7 +#define DSP32ShiftImm_immag_bits 3 +#define DSP32ShiftImm_immag_mask 0x3f +#define DSP32ShiftImm_dst0_bits 9 +#define DSP32ShiftImm_dst0_mask 0x7 +#define DSP32ShiftImm_HLs_bits 12 +#define DSP32ShiftImm_HLs_mask 0x3 +#define DSP32ShiftImm_sop_bits 14 +#define DSP32ShiftImm_sop_mask 0x3 +#define DSP32ShiftImm_sopcde_bits 16 +#define DSP32ShiftImm_sopcde_mask 0x1f +#define DSP32ShiftImm_dontcare_bits 21 +#define DSP32ShiftImm_dontcare_mask 0x3 +#define DSP32ShiftImm_code2_bits 23 +#define DSP32ShiftImm_code2_mask 0xf +#define DSP32ShiftImm_M_bits 27 +#define DSP32ShiftImm_M_mask 0x1 +#define DSP32ShiftImm_code_bits 28 +#define DSP32ShiftImm_code_mask 0xf + +#define init_DSP32ShiftImm \ +{ \ + DSP32ShiftImm_opcode, \ + DSP32ShiftImm_src1_bits, DSP32ShiftImm_src1_mask, \ + DSP32ShiftImm_immag_bits, DSP32ShiftImm_immag_mask, \ + DSP32ShiftImm_dst0_bits, DSP32ShiftImm_dst0_mask, \ + DSP32ShiftImm_HLs_bits, DSP32ShiftImm_HLs_mask, \ + DSP32ShiftImm_sop_bits, DSP32ShiftImm_sop_mask, \ + DSP32ShiftImm_sopcde_bits, DSP32ShiftImm_sopcde_mask, \ + DSP32ShiftImm_dontcare_bits, DSP32ShiftImm_dontcare_mask, \ + DSP32ShiftImm_code2_bits, DSP32ShiftImm_code2_mask, \ + DSP32ShiftImm_M_bits, DSP32ShiftImm_M_mask, \ + DSP32ShiftImm_code_bits, DSP32ShiftImm_code_mask \ +}; + +/* LOAD / STORE */ + +/* LDSTidxI ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......| +|.offset........................................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_offset; + int mask_offset; + int bits_reg; + int mask_reg; + int bits_ptr; + int mask_ptr; + int bits_sz; + int mask_sz; + int bits_Z; + int mask_Z; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} LDSTidxI; + +#define LDSTidxI_opcode 0xe4000000 +#define LDSTidxI_offset_bits 0 +#define LDSTidxI_offset_mask 0xffff +#define LDSTidxI_reg_bits 16 +#define LDSTidxI_reg_mask 0x7 +#define LDSTidxI_ptr_bits 19 +#define LDSTidxI_ptr_mask 0x7 +#define LDSTidxI_sz_bits 22 +#define LDSTidxI_sz_mask 0x3 +#define LDSTidxI_Z_bits 24 +#define LDSTidxI_Z_mask 0x1 +#define LDSTidxI_W_bits 25 +#define LDSTidxI_W_mask 0x1 +#define LDSTidxI_code_bits 26 +#define LDSTidxI_code_mask 0x3f + +#define init_LDSTidxI \ +{ \ + LDSTidxI_opcode, \ + LDSTidxI_offset_bits, LDSTidxI_offset_mask, \ + LDSTidxI_reg_bits, LDSTidxI_reg_mask, \ + LDSTidxI_ptr_bits, LDSTidxI_ptr_mask, \ + LDSTidxI_sz_bits, LDSTidxI_sz_mask, \ + LDSTidxI_Z_bits, LDSTidxI_Z_mask, \ + LDSTidxI_W_bits, LDSTidxI_W_mask, \ + LDSTidxI_code_bits, LDSTidxI_code_mask \ +}; + + +/* LDST ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_ptr; + int mask_ptr; + int bits_Z; + int mask_Z; + int bits_aop; + int mask_aop; + int bits_W; + int mask_W; + int bits_sz; + int mask_sz; + int bits_code; + int mask_code; +} LDST; + +#define LDST_opcode 0x9000 +#define LDST_reg_bits 0 +#define LDST_reg_mask 0x7 +#define LDST_ptr_bits 3 +#define LDST_ptr_mask 0x7 +#define LDST_Z_bits 6 +#define LDST_Z_mask 0x1 +#define LDST_aop_bits 7 +#define LDST_aop_mask 0x3 +#define LDST_W_bits 9 +#define LDST_W_mask 0x1 +#define LDST_sz_bits 10 +#define LDST_sz_mask 0x3 +#define LDST_code_bits 12 +#define LDST_code_mask 0xf + +#define init_LDST \ +{ \ + LDST_opcode, \ + LDST_reg_bits, LDST_reg_mask, \ + LDST_ptr_bits, LDST_ptr_mask, \ + LDST_Z_bits, LDST_Z_mask, \ + LDST_aop_bits, LDST_aop_mask, \ + LDST_W_bits, LDST_W_mask, \ + LDST_sz_bits, LDST_sz_mask, \ + LDST_code_bits, LDST_code_mask \ +}; + +/* LDSTii ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_ptr; + int mask_ptr; + int bits_offset; + int mask_offset; + int bits_op; + int mask_op; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} LDSTii; + +#define LDSTii_opcode 0xa000 +#define LDSTii_reg_bit 0 +#define LDSTii_reg_mask 0x7 +#define LDSTii_ptr_bit 3 +#define LDSTii_ptr_mask 0x7 +#define LDSTii_offset_bit 6 +#define LDSTii_offset_mask 0xf +#define LDSTii_op_bit 10 +#define LDSTii_op_mask 0x3 +#define LDSTii_W_bit 12 +#define LDSTii_W_mask 0x1 +#define LDSTii_code_bit 13 +#define LDSTii_code_mask 0x7 + +#define init_LDSTii \ +{ \ + LDSTii_opcode, \ + LDSTii_reg_bit, LDSTii_reg_mask, \ + LDSTii_ptr_bit, LDSTii_ptr_mask, \ + LDSTii_offset_bit, LDSTii_offset_mask, \ + LDSTii_op_bit, LDSTii_op_mask, \ + LDSTii_W_bit, LDSTii_W_mask, \ + LDSTii_code_bit, LDSTii_code_mask \ +}; + + +/* LDSTiiFP ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_offset; + int mask_offset; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} LDSTiiFP; + +#define LDSTiiFP_opcode 0xb800 +#define LDSTiiFP_reg_bits 0 +#define LDSTiiFP_reg_mask 0xf +#define LDSTiiFP_offset_bits 4 +#define LDSTiiFP_offset_mask 0x1f +#define LDSTiiFP_W_bits 9 +#define LDSTiiFP_W_mask 0x1 +#define LDSTiiFP_code_bits 10 +#define LDSTiiFP_code_mask 0x3f + +#define init_LDSTiiFP \ +{ \ + LDSTiiFP_opcode, \ + LDSTiiFP_reg_bits, LDSTiiFP_reg_mask, \ + LDSTiiFP_offset_bits, LDSTiiFP_offset_mask, \ + LDSTiiFP_W_bits, LDSTiiFP_W_mask, \ + LDSTiiFP_code_bits, LDSTiiFP_code_mask \ +}; + +/* dspLDST ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_i; + int mask_i; + int bits_m; + int mask_m; + int bits_aop; + int mask_aop; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} DspLDST; + +#define DspLDST_opcode 0x9c00 +#define DspLDST_reg_bits 0 +#define DspLDST_reg_mask 0x7 +#define DspLDST_i_bits 3 +#define DspLDST_i_mask 0x3 +#define DspLDST_m_bits 5 +#define DspLDST_m_mask 0x3 +#define DspLDST_aop_bits 7 +#define DspLDST_aop_mask 0x3 +#define DspLDST_W_bits 9 +#define DspLDST_W_mask 0x1 +#define DspLDST_code_bits 10 +#define DspLDST_code_mask 0x3f + +#define init_DspLDST \ +{ \ + DspLDST_opcode, \ + DspLDST_reg_bits, DspLDST_reg_mask, \ + DspLDST_i_bits, DspLDST_i_mask, \ + DspLDST_m_bits, DspLDST_m_mask, \ + DspLDST_aop_bits, DspLDST_aop_mask, \ + DspLDST_W_bits, DspLDST_W_mask, \ + DspLDST_code_bits, DspLDST_code_mask \ +}; + + +/* LDSTpmod ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_ptr; + int mask_ptr; + int bits_idx; + int mask_idx; + int bits_reg; + int mask_reg; + int bits_aop; + int mask_aop; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} LDSTpmod; + +#define LDSTpmod_opcode 0x8000 +#define LDSTpmod_ptr_bits 0 +#define LDSTpmod_ptr_mask 0x7 +#define LDSTpmod_idx_bits 3 +#define LDSTpmod_idx_mask 0x7 +#define LDSTpmod_reg_bits 6 +#define LDSTpmod_reg_mask 0x7 +#define LDSTpmod_aop_bits 9 +#define LDSTpmod_aop_mask 0x3 +#define LDSTpmod_W_bits 11 +#define LDSTpmod_W_mask 0x1 +#define LDSTpmod_code_bits 12 +#define LDSTpmod_code_mask 0xf + +#define init_LDSTpmod \ +{ \ + LDSTpmod_opcode, \ + LDSTpmod_ptr_bits, LDSTpmod_ptr_mask, \ + LDSTpmod_idx_bits, LDSTpmod_idx_mask, \ + LDSTpmod_reg_bits, LDSTpmod_reg_mask, \ + LDSTpmod_aop_bits, LDSTpmod_aop_mask, \ + LDSTpmod_W_bits, LDSTpmod_W_mask, \ + LDSTpmod_code_bits, LDSTpmod_code_mask \ +}; + + +/* LOGI2op ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_dst; + int mask_dst; + int bits_src; + int mask_src; + int bits_opc; + int mask_opc; + int bits_code; + int mask_code; +} LOGI2op; + +#define LOGI2op_opcode 0x4800 +#define LOGI2op_dst_bits 0 +#define LOGI2op_dst_mask 0x7 +#define LOGI2op_src_bits 3 +#define LOGI2op_src_mask 0x1f +#define LOGI2op_opc_bits 8 +#define LOGI2op_opc_mask 0x7 +#define LOGI2op_code_bits 11 +#define LOGI2op_code_mask 0x1f + +#define init_LOGI2op \ +{ \ + LOGI2op_opcode, \ + LOGI2op_dst_bits, LOGI2op_dst_mask, \ + LOGI2op_src_bits, LOGI2op_src_mask, \ + LOGI2op_opc_bits, LOGI2op_opc_mask, \ + LOGI2op_code_bits, LOGI2op_code_mask \ +}; + + +/* ALU2op ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_dst; + int mask_dst; + int bits_src; + int mask_src; + int bits_opc; + int mask_opc; + int bits_code; + int mask_code; +} ALU2op; + +#define ALU2op_opcode 0x4000 +#define ALU2op_dst_bits 0 +#define ALU2op_dst_mask 0x7 +#define ALU2op_src_bits 3 +#define ALU2op_src_mask 0x7 +#define ALU2op_opc_bits 6 +#define ALU2op_opc_mask 0xf +#define ALU2op_code_bits 10 +#define ALU2op_code_mask 0x3f + +#define init_ALU2op \ +{ \ + ALU2op_opcode, \ + ALU2op_dst_bits, ALU2op_dst_mask, \ + ALU2op_src_bits, ALU2op_src_mask, \ + ALU2op_opc_bits, ALU2op_opc_mask, \ + ALU2op_code_bits, ALU2op_code_mask \ +}; + + +/* BRCC ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 1 |.T.|.B.|.offset................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_offset; + int mask_offset; + int bits_B; + int mask_B; + int bits_T; + int mask_T; + int bits_code; + int mask_code; +} BRCC; + +#define BRCC_opcode 0x1000 +#define BRCC_offset_bits 0 +#define BRCC_offset_mask 0x3ff +#define BRCC_B_bits 10 +#define BRCC_B_mask 0x1 +#define BRCC_T_bits 11 +#define BRCC_T_mask 0x1 +#define BRCC_code_bits 12 +#define BRCC_code_mask 0xf + +#define init_BRCC \ +{ \ + BRCC_opcode, \ + BRCC_offset_bits, BRCC_offset_mask, \ + BRCC_B_bits, BRCC_B_mask, \ + BRCC_T_bits, BRCC_T_mask, \ + BRCC_code_bits, BRCC_code_mask \ +}; + + +/* UJUMP ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 1 | 0 |.offset........................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_offset; + int mask_offset; + int bits_code; + int mask_code; +} UJump; + +#define UJump_opcode 0x2000 +#define UJump_offset_bits 0 +#define UJump_offset_mask 0xfff +#define UJump_code_bits 12 +#define UJump_code_mask 0xf + +#define init_UJump \ +{ \ + UJump_opcode, \ + UJump_offset_bits, UJump_offset_mask, \ + UJump_code_bits, UJump_code_mask \ +}; + + +/* ProgCtrl ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_poprnd; + int mask_poprnd; + int bits_prgfunc; + int mask_prgfunc; + int bits_code; + int mask_code; +} ProgCtrl; + +#define ProgCtrl_opcode 0x0000 +#define ProgCtrl_poprnd_bits 0 +#define ProgCtrl_poprnd_mask 0xf +#define ProgCtrl_prgfunc_bits 4 +#define ProgCtrl_prgfunc_mask 0xf +#define ProgCtrl_code_bits 8 +#define ProgCtrl_code_mask 0xff + +#define init_ProgCtrl \ +{ \ + ProgCtrl_opcode, \ + ProgCtrl_poprnd_bits, ProgCtrl_poprnd_mask, \ + ProgCtrl_prgfunc_bits, ProgCtrl_prgfunc_mask, \ + ProgCtrl_code_bits, ProgCtrl_code_mask \ +}; + +/* CALLa ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................| +|.lsw...........................................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + + +typedef struct +{ + unsigned long opcode; + int bits_addr; + int mask_addr; + int bits_S; + int mask_S; + int bits_code; + int mask_code; +} CALLa; + +#define CALLa_opcode 0xe2000000 +#define CALLa_addr_bits 0 +#define CALLa_addr_mask 0xffffff +#define CALLa_S_bits 24 +#define CALLa_S_mask 0x1 +#define CALLa_code_bits 25 +#define CALLa_code_mask 0x7f + +#define init_CALLa \ +{ \ + CALLa_opcode, \ + CALLa_addr_bits, CALLa_addr_mask, \ + CALLa_S_bits, CALLa_S_mask, \ + CALLa_code_bits, CALLa_code_mask \ +}; + + +/* pseudoDEBUG ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_grp; + int mask_grp; + int bits_fn; + int mask_fn; + int bits_code; + int mask_code; +} PseudoDbg; + +#define PseudoDbg_opcode 0xf800 +#define PseudoDbg_reg_bits 0 +#define PseudoDbg_reg_mask 0x7 +#define PseudoDbg_grp_bits 3 +#define PseudoDbg_grp_mask 0x7 +#define PseudoDbg_fn_bits 6 +#define PseudoDbg_fn_mask 0x3 +#define PseudoDbg_code_bits 8 +#define PseudoDbg_code_mask 0xff + +#define init_PseudoDbg \ +{ \ + PseudoDbg_opcode, \ + PseudoDbg_reg_bits, PseudoDbg_reg_mask, \ + PseudoDbg_grp_bits, PseudoDbg_grp_mask, \ + PseudoDbg_fn_bits, PseudoDbg_fn_mask, \ + PseudoDbg_code_bits, PseudoDbg_code_mask \ +}; + +/* PseudoDbg_assert ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...| +|.expected......................................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_expected; + int mask_expected; + int bits_regtest; + int mask_regtest; + int bits_grp; + int mask_grp; + int bits_dbgop; + int mask_dbgop; + int bits_dontcare; + int mask_dontcare; + int bits_code; + int mask_code; +} PseudoDbg_Assert; + +#define PseudoDbg_Assert_opcode 0xf0000000 +#define PseudoDbg_Assert_expected_bits 0 +#define PseudoDbg_Assert_expected_mask 0xffff +#define PseudoDbg_Assert_regtest_bits 16 +#define PseudoDbg_Assert_regtest_mask 0x7 +#define PseudoDbg_Assert_grp_bits 19 +#define PseudoDbg_Assert_grp_mask 0x7 +#define PseudoDbg_Assert_dbgop_bits 22 +#define PseudoDbg_Assert_dbgop_mask 0x3 +#define PseudoDbg_Assert_dontcare_bits 24 +#define PseudoDbg_Assert_dontcare_mask 0x7 +#define PseudoDbg_Assert_code_bits 27 +#define PseudoDbg_Assert_code_mask 0x1f + +#define init_PseudoDbg_Assert \ +{ \ + PseudoDbg_Assert_opcode, \ + PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \ + PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \ + PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \ + PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \ + PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \ + PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \ +}; + +/* pseudoChr ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_ch; + int mask_ch; + int bits_code; + int mask_code; +} PseudoChr; + +#define PseudoChr_opcode 0xf900 +#define PseudoChr_ch_bits 0 +#define PseudoChr_ch_mask 0xff +#define PseudoChr_code_bits 8 +#define PseudoChr_code_mask 0xff + +#define init_PseudoChr \ +{ \ + PseudoChr_opcode, \ + PseudoChr_ch_bits, PseudoChr_ch_mask, \ + PseudoChr_code_bits, PseudoChr_code_mask \ +}; + +/* CaCTRL ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_op; + int mask_op; + int bits_a; + int mask_a; + int bits_code; + int mask_code; +} CaCTRL; + +#define CaCTRL_opcode 0x0240 +#define CaCTRL_reg_bits 0 +#define CaCTRL_reg_mask 0x7 +#define CaCTRL_op_bits 3 +#define CaCTRL_op_mask 0x3 +#define CaCTRL_a_bits 5 +#define CaCTRL_a_mask 0x1 +#define CaCTRL_code_bits 6 +#define CaCTRL_code_mask 0x3fff + +#define init_CaCTRL \ +{ \ + CaCTRL_opcode, \ + CaCTRL_reg_bits, CaCTRL_reg_mask, \ + CaCTRL_op_bits, CaCTRL_op_mask, \ + CaCTRL_a_bits, CaCTRL_a_mask, \ + CaCTRL_code_bits, CaCTRL_code_mask \ +}; + +/* PushPopMultiple ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_pr; + int mask_pr; + int bits_dr; + int mask_dr; + int bits_W; + int mask_W; + int bits_p; + int mask_p; + int bits_d; + int mask_d; + int bits_code; + int mask_code; +} PushPopMultiple; + +#define PushPopMultiple_opcode 0x0400 +#define PushPopMultiple_pr_bits 0 +#define PushPopMultiple_pr_mask 0x7 +#define PushPopMultiple_dr_bits 3 +#define PushPopMultiple_dr_mask 0x7 +#define PushPopMultiple_W_bits 6 +#define PushPopMultiple_W_mask 0x1 +#define PushPopMultiple_p_bits 7 +#define PushPopMultiple_p_mask 0x1 +#define PushPopMultiple_d_bits 8 +#define PushPopMultiple_d_mask 0x1 +#define PushPopMultiple_code_bits 8 +#define PushPopMultiple_code_mask 0x1 + +#define init_PushPopMultiple \ +{ \ + PushPopMultiple_opcode, \ + PushPopMultiple_pr_bits, PushPopMultiple_pr_mask, \ + PushPopMultiple_dr_bits, PushPopMultiple_dr_mask, \ + PushPopMultiple_W_bits, PushPopMultiple_W_mask, \ + PushPopMultiple_p_bits, PushPopMultiple_p_mask, \ + PushPopMultiple_d_bits, PushPopMultiple_d_mask, \ + PushPopMultiple_code_bits, PushPopMultiple_code_mask \ +}; + +/* PushPopReg ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_grp; + int mask_grp; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} PushPopReg; + +#define PushPopReg_opcode 0x0100 +#define PushPopReg_reg_bits 0 +#define PushPopReg_reg_mask 0x7 +#define PushPopReg_grp_bits 3 +#define PushPopReg_grp_mask 0x7 +#define PushPopReg_W_bits 6 +#define PushPopReg_W_mask 0x1 +#define PushPopReg_code_bits 7 +#define PushPopReg_code_mask 0x1ff + +#define init_PushPopReg \ +{ \ + PushPopReg_opcode, \ + PushPopReg_reg_bits, PushPopReg_reg_mask, \ + PushPopReg_grp_bits, PushPopReg_grp_mask, \ + PushPopReg_W_bits, PushPopReg_W_mask, \ + PushPopReg_code_bits, PushPopReg_code_mask, \ +}; + +/* linkage ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.| +|.framesize.....................................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_framesize; + int mask_framesize; + int bits_R; + int mask_R; + int bits_code; + int mask_code; +} Linkage; + +#define Linkage_opcode 0xe8000000 +#define Linkage_framesize_bits 0 +#define Linkage_framesize_mask 0xffff +#define Linkage_R_bits 16 +#define Linkage_R_mask 0x1 +#define Linkage_code_bits 17 +#define Linkage_code_mask 0x7fff + +#define init_Linkage \ +{ \ + Linkage_opcode, \ + Linkage_framesize_bits, Linkage_framesize_mask, \ + Linkage_R_bits, Linkage_R_mask, \ + Linkage_code_bits, Linkage_code_mask \ +}; + +/* LoopSetup ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......| +|.reg...........| - | - |.eoffset...............................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_eoffset; + int mask_eoffset; + int bits_dontcare; + int mask_dontcare; + int bits_reg; + int mask_reg; + int bits_soffset; + int mask_soffset; + int bits_c; + int mask_c; + int bits_rop; + int mask_rop; + int bits_code; + int mask_code; +} LoopSetup; + +#define LoopSetup_opcode 0xe0800000 +#define LoopSetup_eoffset_bits 0 +#define LoopSetup_eoffset_mask 0x3ff +#define LoopSetup_dontcare_bits 10 +#define LoopSetup_dontcare_mask 0x3 +#define LoopSetup_reg_bits 12 +#define LoopSetup_reg_mask 0xf +#define LoopSetup_soffset_bits 16 +#define LoopSetup_soffset_mask 0xf +#define LoopSetup_c_bits 20 +#define LoopSetup_c_mask 0x1 +#define LoopSetup_rop_bits 21 +#define LoopSetup_rop_mask 0x3 +#define LoopSetup_code_bits 23 +#define LoopSetup_code_mask 0x1ff + +#define init_LoopSetup \ +{ \ + LoopSetup_opcode, \ + LoopSetup_eoffset_bits, LoopSetup_eoffset_mask, \ + LoopSetup_dontcare_bits, LoopSetup_dontcare_mask, \ + LoopSetup_reg_bits, LoopSetup_reg_mask, \ + LoopSetup_soffset_bits, LoopSetup_soffset_mask, \ + LoopSetup_c_bits, LoopSetup_c_mask, \ + LoopSetup_rop_bits, LoopSetup_rop_mask, \ + LoopSetup_code_bits, LoopSetup_code_mask \ +}; + +/* LDIMMhalf ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......| +|.hword.........................................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_hword; + int mask_hword; + int bits_reg; + int mask_reg; + int bits_grp; + int mask_grp; + int bits_S; + int mask_S; + int bits_H; + int mask_H; + int bits_Z; + int mask_Z; + int bits_code; + int mask_code; +} LDIMMhalf; + +#define LDIMMhalf_opcode 0xe1000000 +#define LDIMMhalf_hword_bits 0 +#define LDIMMhalf_hword_mask 0xffff +#define LDIMMhalf_reg_bits 16 +#define LDIMMhalf_reg_mask 0x7 +#define LDIMMhalf_grp_bits 19 +#define LDIMMhalf_grp_mask 0x3 +#define LDIMMhalf_S_bits 21 +#define LDIMMhalf_S_mask 0x1 +#define LDIMMhalf_H_bits 22 +#define LDIMMhalf_H_mask 0x1 +#define LDIMMhalf_Z_bits 23 +#define LDIMMhalf_Z_mask 0x1 +#define LDIMMhalf_code_bits 24 +#define LDIMMhalf_code_mask 0xff + +#define init_LDIMMhalf \ +{ \ + LDIMMhalf_opcode, \ + LDIMMhalf_hword_bits, LDIMMhalf_hword_mask, \ + LDIMMhalf_reg_bits, LDIMMhalf_reg_mask, \ + LDIMMhalf_grp_bits, LDIMMhalf_grp_mask, \ + LDIMMhalf_S_bits, LDIMMhalf_S_mask, \ + LDIMMhalf_H_bits, LDIMMhalf_H_mask, \ + LDIMMhalf_Z_bits, LDIMMhalf_Z_mask, \ + LDIMMhalf_code_bits, LDIMMhalf_code_mask \ +}; + + +/* CC2dreg ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_op; + int mask_op; + int bits_code; + int mask_code; +} CC2dreg; + +#define CC2dreg_opcode 0x0200 +#define CC2dreg_reg_bits 0 +#define CC2dreg_reg_mask 0x7 +#define CC2dreg_op_bits 3 +#define CC2dreg_op_mask 0x3 +#define CC2dreg_code_bits 5 +#define CC2dreg_code_mask 0x7fff + +#define init_CC2dreg \ +{ \ + CC2dreg_opcode, \ + CC2dreg_reg_bits, CC2dreg_reg_mask, \ + CC2dreg_op_bits, CC2dreg_op_mask, \ + CC2dreg_code_bits, CC2dreg_code_mask \ +}; + + +/* PTR2op ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_dst; + int mask_dst; + int bits_src; + int mask_src; + int bits_opc; + int mask_opc; + int bits_code; + int mask_code; +} PTR2op; + +#define PTR2op_opcode 0x4400 +#define PTR2op_dst_bits 0 +#define PTR2op_dst_mask 0x7 +#define PTR2op_src_bits 3 +#define PTR2op_src_mask 0x7 +#define PTR2op_opc_bits 6 +#define PTR2op_opc_mask 0x7 +#define PTR2op_code_bits 9 +#define PTR2op_code_mask 0x7f + +#define init_PTR2op \ +{ \ + PTR2op_opcode, \ + PTR2op_dst_bits, PTR2op_dst_mask, \ + PTR2op_src_bits, PTR2op_src_mask, \ + PTR2op_opc_bits, PTR2op_opc_mask, \ + PTR2op_code_bits, PTR2op_code_mask \ +}; + + +/* COMP3op ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_src0; + int mask_src0; + int bits_src1; + int mask_src1; + int bits_dst; + int mask_dst; + int bits_opc; + int mask_opc; + int bits_code; + int mask_code; +} COMP3op; + +#define COMP3op_opcode 0x5000 +#define COMP3op_src0_bits 0 +#define COMP3op_src0_mask 0x7 +#define COMP3op_src1_bits 3 +#define COMP3op_src1_mask 0x7 +#define COMP3op_dst_bits 6 +#define COMP3op_dst_mask 0x7 +#define COMP3op_opc_bits 9 +#define COMP3op_opc_mask 0x7 +#define COMP3op_code_bits 12 +#define COMP3op_code_mask 0xf + +#define init_COMP3op \ +{ \ + COMP3op_opcode, \ + COMP3op_src0_bits, COMP3op_src0_mask, \ + COMP3op_src1_bits, COMP3op_src1_mask, \ + COMP3op_dst_bits, COMP3op_dst_mask, \ + COMP3op_opc_bits, COMP3op_opc_mask, \ + COMP3op_code_bits, COMP3op_code_mask \ +}; + +/* ccMV ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_src; + int mask_src; + int bits_dst; + int mask_dst; + int bits_s; + int mask_s; + int bits_d; + int mask_d; + int bits_T; + int mask_T; + int bits_code; + int mask_code; +} CCmv; + +#define CCmv_opcode 0x0600 +#define CCmv_src_bits 0 +#define CCmv_src_mask 0x7 +#define CCmv_dst_bits 3 +#define CCmv_dst_mask 0x7 +#define CCmv_s_bits 6 +#define CCmv_s_mask 0x1 +#define CCmv_d_bits 7 +#define CCmv_d_mask 0x1 +#define CCmv_T_bits 8 +#define CCmv_T_mask 0x1 +#define CCmv_code_bits 9 +#define CCmv_code_mask 0x7f + +#define init_CCmv \ +{ \ + CCmv_opcode, \ + CCmv_src_bits, CCmv_src_mask, \ + CCmv_dst_bits, CCmv_dst_mask, \ + CCmv_s_bits, CCmv_s_mask, \ + CCmv_d_bits, CCmv_d_mask, \ + CCmv_T_bits, CCmv_T_mask, \ + CCmv_code_bits, CCmv_code_mask \ +}; + + +/* CCflag ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_x; + int mask_x; + int bits_y; + int mask_y; + int bits_G; + int mask_G; + int bits_opc; + int mask_opc; + int bits_I; + int mask_I; + int bits_code; + int mask_code; +} CCflag; + +#define CCflag_opcode 0x0800 +#define CCflag_x_bits 0 +#define CCflag_x_mask 0x7 +#define CCflag_y_bits 3 +#define CCflag_y_mask 0x7 +#define CCflag_G_bits 6 +#define CCflag_G_mask 0x1 +#define CCflag_opc_bits 7 +#define CCflag_opc_mask 0x7 +#define CCflag_I_bits 10 +#define CCflag_I_mask 0x1 +#define CCflag_code_bits 11 +#define CCflag_code_mask 0x1f + +#define init_CCflag \ +{ \ + CCflag_opcode, \ + CCflag_x_bits, CCflag_x_mask, \ + CCflag_y_bits, CCflag_y_mask, \ + CCflag_G_bits, CCflag_G_mask, \ + CCflag_opc_bits, CCflag_opc_mask, \ + CCflag_I_bits, CCflag_I_mask, \ + CCflag_code_bits, CCflag_code_mask, \ +}; + + +/* CC2stat ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_cbit; + int mask_cbit; + int bits_op; + int mask_op; + int bits_D; + int mask_D; + int bits_code; + int mask_code; +} CC2stat; + +#define CC2stat_opcode 0x0300 +#define CC2stat_cbit_bits 0 +#define CC2stat_cbit_mask 0x1f +#define CC2stat_op_bits 5 +#define CC2stat_op_mask 0x3 +#define CC2stat_D_bits 7 +#define CC2stat_D_mask 0x1 +#define CC2stat_code_bits 8 +#define CC2stat_code_mask 0xff + +#define init_CC2stat \ +{ \ + CC2stat_opcode, \ + CC2stat_cbit_bits, CC2stat_cbit_mask, \ + CC2stat_op_bits, CC2stat_op_mask, \ + CC2stat_D_bits, CC2stat_D_mask, \ + CC2stat_code_bits, CC2stat_code_mask \ +}; + + +/* REGMV ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_src; + int mask_src; + int bits_dst; + int mask_dst; + int bits_gs; + int mask_gs; + int bits_gd; + int mask_gd; + int bits_code; + int mask_code; +} RegMv; + +#define RegMv_opcode 0x3000 +#define RegMv_src_bits 0 +#define RegMv_src_mask 0x7 +#define RegMv_dst_bits 3 +#define RegMv_dst_mask 0x7 +#define RegMv_gs_bits 6 +#define RegMv_gs_mask 0x7 +#define RegMv_gd_bits 9 +#define RegMv_gd_mask 0x7 +#define RegMv_code_bits 12 +#define RegMv_code_mask 0xf + +#define init_RegMv \ +{ \ + RegMv_opcode, \ + RegMv_src_bits, RegMv_src_mask, \ + RegMv_dst_bits, RegMv_dst_mask, \ + RegMv_gs_bits, RegMv_gs_mask, \ + RegMv_gd_bits, RegMv_gd_mask, \ + RegMv_code_bits, RegMv_code_mask \ +}; + + +/* COMPI2opD ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_dst; + int mask_dst; + int bits_src; + int mask_src; + int bits_op; + int mask_op; + int bits_code; + int mask_code; +} COMPI2opD; + +#define COMPI2opD_opcode 0x6000 +#define COMPI2opD_dst_bits 0 +#define COMPI2opD_dst_mask 0x7 +#define COMPI2opD_src_bits 3 +#define COMPI2opD_src_mask 0x7f +#define COMPI2opD_op_bits 10 +#define COMPI2opD_op_mask 0x1 +#define COMPI2opD_code_bits 11 +#define COMPI2opD_code_mask 0x1f + +#define init_COMPI2opD \ +{ \ + COMPI2opD_opcode, \ + COMPI2opD_dst_bits, COMPI2opD_dst_mask, \ + COMPI2opD_src_bits, COMPI2opD_src_mask, \ + COMPI2opD_op_bits, COMPI2opD_op_mask, \ + COMPI2opD_code_bits, COMPI2opD_code_mask \ +}; + +/* COMPI2opP ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef COMPI2opD COMPI2opP; + +#define COMPI2opP_opcode 0x6800 +#define COMPI2opP_dst_bits 0 +#define COMPI2opP_dst_mask 0x7 +#define COMPI2opP_src_bits 3 +#define COMPI2opP_src_mask 0x7f +#define COMPI2opP_op_bits 10 +#define COMPI2opP_op_mask 0x1 +#define COMPI2opP_code_bits 11 +#define COMPI2opP_code_mask 0x1f + +#define init_COMPI2opP \ +{ \ + COMPI2opP_opcode, \ + COMPI2opP_dst_bits, COMPI2opP_dst_mask, \ + COMPI2opP_src_bits, COMPI2opP_src_mask, \ + COMPI2opP_op_bits, COMPI2opP_op_mask, \ + COMPI2opP_code_bits, COMPI2opP_code_mask \ +}; + + +/* dagMODim ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_i; + int mask_i; + int bits_m; + int mask_m; + int bits_op; + int mask_op; + int bits_code2; + int mask_code2; + int bits_br; + int mask_br; + int bits_code; + int mask_code; +} DagMODim; + +#define DagMODim_opcode 0x9e60 +#define DagMODim_i_bits 0 +#define DagMODim_i_mask 0x3 +#define DagMODim_m_bits 2 +#define DagMODim_m_mask 0x3 +#define DagMODim_op_bits 4 +#define DagMODim_op_mask 0x1 +#define DagMODim_code2_bits 5 +#define DagMODim_code2_mask 0x3 +#define DagMODim_br_bits 7 +#define DagMODim_br_mask 0x1 +#define DagMODim_code_bits 8 +#define DagMODim_code_mask 0xff + +#define init_DagMODim \ +{ \ + DagMODim_opcode, \ + DagMODim_i_bits, DagMODim_i_mask, \ + DagMODim_m_bits, DagMODim_m_mask, \ + DagMODim_op_bits, DagMODim_op_mask, \ + DagMODim_code2_bits, DagMODim_code2_mask, \ + DagMODim_br_bits, DagMODim_br_mask, \ + DagMODim_code_bits, DagMODim_code_mask \ +}; + +/* dagMODik ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_i; + int mask_i; + int bits_op; + int mask_op; + int bits_code; + int mask_code; +} DagMODik; + +#define DagMODik_opcode 0x9f60 +#define DagMODik_i_bits 0 +#define DagMODik_i_mask 0x3 +#define DagMODik_op_bits 2 +#define DagMODik_op_mask 0x3 +#define DagMODik_code_bits 3 +#define DagMODik_code_mask 0xfff + +#define init_DagMODik \ +{ \ + DagMODik_opcode, \ + DagMODik_i_bits, DagMODik_i_mask, \ + DagMODik_op_bits, DagMODik_op_mask, \ + DagMODik_code_bits, DagMODik_code_mask \ +}; + +#endif diff --git a/target-bfin/translate.c b/target-bfin/translate.c new file mode 100644 index 0000000000000..008e1cdfca139 --- /dev/null +++ b/target-bfin/translate.c @@ -0,0 +1,1299 @@ +/* + * Blackfin translation + * + * Copyright 2007-2016 Mike Frysinger + * Copyright 2007-2011 Analog Devices, Inc. + * + * Licensed under the Lesser GPL 2 or later. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "disas/disas.h" +#include "exec/cpu_ldst.h" +#include "exec/exec-all.h" +#include "tcg-op.h" +#include "qemu-common.h" +#include "opcode/bfin.h" + +#include "exec/helper-proto.h" +#include "exec/helper-gen.h" + +#include "trace-tcg.h" +#include "exec/log.h" + +typedef void (*hwloop_callback)(struct DisasContext *dc, int loop); + +typedef struct DisasContext { + CPUArchState *env; + struct TranslationBlock *tb; + /* The current PC we're decoding (could be middle of parallel insn) */ + target_ulong pc; + /* Length of current insn (2/4/8) */ + target_ulong insn_len; + + /* For delayed ASTAT handling */ + enum astat_ops astat_op; + + /* For hardware loop processing */ + hwloop_callback hwloop_callback; + void *hwloop_data; + + /* Was a DISALGNEXCPT used in this parallel insn ? */ + int disalgnexcpt; + + int is_jmp; + int mem_idx; +} DisasContext; + +/* We're making a call (which means we need to update RTS) */ +#define DISAS_CALL 0xad0 + +static TCGv_ptr cpu_env; +static TCGv cpu_dreg[8]; +static TCGv cpu_preg[8]; +#define cpu_spreg cpu_preg[6] +#define cpu_fpreg cpu_preg[7] +static TCGv cpu_ireg[4]; +static TCGv cpu_mreg[4]; +static TCGv cpu_breg[4]; +static TCGv cpu_lreg[4]; +static TCGv_i64 cpu_areg[2]; +static TCGv cpu_rets; +static TCGv cpu_lcreg[2], cpu_ltreg[2], cpu_lbreg[2]; +static TCGv cpu_cycles[2]; +static TCGv cpu_uspreg; +static TCGv cpu_seqstat; +static TCGv cpu_syscfg; +static TCGv cpu_reti; +static TCGv cpu_retx; +static TCGv cpu_retn; +static TCGv cpu_rete; +static TCGv cpu_emudat; +static TCGv cpu_pc; +static TCGv cpu_cc; +static TCGv cpu_astat_arg[3]; + +#include "exec/gen-icount.h" + +static inline void +bfin_tcg_new_set3(TCGv *tcgv, unsigned int cnt, unsigned int offbase, + const char * const *names) +{ + unsigned int i; + for (i = 0; i < cnt; ++i) { + tcgv[i] = tcg_global_mem_new(cpu_env, offbase + (i * 4), names[i]); + } +} +#define bfin_tcg_new_set2(tcgv, cnt, reg, name_idx) \ + bfin_tcg_new_set3(tcgv, cnt, offsetof(CPUArchState, reg), \ + &greg_names[name_idx]) +#define bfin_tcg_new_set(reg, name_idx) \ + bfin_tcg_new_set2(cpu_##reg, ARRAY_SIZE(cpu_##reg), reg, name_idx) +#define bfin_tcg_new(reg, name_idx) \ + bfin_tcg_new_set2(&cpu_##reg, 1, reg, name_idx) + +void bfin_translate_init(void) +{ + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); + + cpu_pc = tcg_global_mem_new(cpu_env, + offsetof(CPUArchState, pc), "PC"); + cpu_cc = tcg_global_mem_new(cpu_env, + offsetof(CPUArchState, astat[ASTAT_CC]), "CC"); + + cpu_astat_arg[0] = tcg_global_mem_new(cpu_env, + offsetof(CPUArchState, astat_arg[0]), "astat_arg[0]"); + cpu_astat_arg[1] = tcg_global_mem_new(cpu_env, + offsetof(CPUArchState, astat_arg[1]), "astat_arg[1]"); + cpu_astat_arg[2] = tcg_global_mem_new(cpu_env, + offsetof(CPUArchState, astat_arg[2]), "astat_arg[2]"); + + cpu_areg[0] = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUArchState, areg[0]), "A0"); + cpu_areg[1] = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUArchState, areg[1]), "A1"); + + bfin_tcg_new_set(dreg, 0); + bfin_tcg_new_set(preg, 8); + bfin_tcg_new_set(ireg, 16); + bfin_tcg_new_set(mreg, 20); + bfin_tcg_new_set(breg, 24); + bfin_tcg_new_set(lreg, 28); + bfin_tcg_new(rets, 39); + bfin_tcg_new(lcreg[0], 48); + bfin_tcg_new(ltreg[0], 49); + bfin_tcg_new(lbreg[0], 50); + bfin_tcg_new(lcreg[1], 51); + bfin_tcg_new(ltreg[1], 52); + bfin_tcg_new(lbreg[1], 53); + bfin_tcg_new_set(cycles, 54); + bfin_tcg_new(uspreg, 56); + bfin_tcg_new(seqstat, 57); + bfin_tcg_new(syscfg, 58); + bfin_tcg_new(reti, 59); + bfin_tcg_new(retx, 60); + bfin_tcg_new(retn, 61); + bfin_tcg_new(rete, 62); + bfin_tcg_new(emudat, 63); +} + +#define _astat_printf(bit) cpu_fprintf(f, "%s" #bit " ", \ + (env->astat[ASTAT_##bit] ? "" : "~")) +void bfin_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, + int flags) +{ + BlackfinCPU *cpu = BFIN_CPU(cs); + CPUBfinState *env = &cpu->env; + + cpu_fprintf(f, " SYSCFG: %04x SEQSTAT: %08x\n", + env->syscfg, env->seqstat); + cpu_fprintf(f, "RETE: %08x RETN: %08x RETX: %08x\n", + env->rete, env->retn, env->retx); + cpu_fprintf(f, "RETI: %08x RETS: %08x PC : %08x\n", + env->reti, env->rets, env->pc); + cpu_fprintf(f, " R0 : %08x R4 : %08x P0 : %08x P4 : %08x\n", + env->dreg[0], env->dreg[4], env->preg[0], env->preg[4]); + cpu_fprintf(f, " R1 : %08x R5 : %08x P1 : %08x P5 : %08x\n", + env->dreg[1], env->dreg[5], env->preg[1], env->preg[5]); + cpu_fprintf(f, " R2 : %08x R6 : %08x P2 : %08x SP : %08x\n", + env->dreg[2], env->dreg[6], env->preg[2], env->spreg); + cpu_fprintf(f, " R3 : %08x R7 : %08x P3 : %08x FP : %08x\n", + env->dreg[3], env->dreg[7], env->preg[3], env->fpreg); + cpu_fprintf(f, " LB0: %08x LT0: %08x LC0: %08x\n", + env->lbreg[0], env->ltreg[0], env->lcreg[0]); + cpu_fprintf(f, " LB1: %08x LT1: %08x LC1: %08x\n", + env->lbreg[1], env->ltreg[1], env->lcreg[1]); + cpu_fprintf(f, " B0 : %08x L0 : %08x M0 : %08x I0 : %08x\n", + env->breg[0], env->lreg[0], env->mreg[0], env->ireg[0]); + cpu_fprintf(f, " B1 : %08x L1 : %08x M1 : %08x I1 : %08x\n", + env->breg[1], env->lreg[1], env->mreg[1], env->ireg[1]); + cpu_fprintf(f, " B2 : %08x L2 : %08x M2 : %08x I2 : %08x\n", + env->breg[2], env->lreg[2], env->mreg[2], env->ireg[2]); + cpu_fprintf(f, " B3 : %08x L3 : %08x M3 : %08x I3 : %08x\n", + env->breg[3], env->lreg[3], env->mreg[3], env->ireg[3]); + cpu_fprintf(f, " A0: %010"PRIx64" A1: %010"PRIx64"\n", + env->areg[0] & 0xffffffffff, env->areg[1] & 0xffffffffff); + cpu_fprintf(f, " USP: %08x ASTAT: %08x CC : %08x\n", + env->uspreg, bfin_astat_read(env), env->astat[ASTAT_CC]); + cpu_fprintf(f, "ASTAT BITS: "); + _astat_printf(VS); + _astat_printf(V); + _astat_printf(AV1S); + _astat_printf(AV1); + _astat_printf(AV0S); + _astat_printf(AV0); + _astat_printf(AC1); + _astat_printf(AC0); + _astat_printf(AQ); + _astat_printf(CC); + _astat_printf(V_COPY); + _astat_printf(AC0_COPY); + _astat_printf(AN); + _astat_printf(AZ); + cpu_fprintf(f, "\nASTAT CACHE: OP: %02u ARG: %08x %08x %08x\n", + env->astat_op, env->astat_arg[0], env->astat_arg[1], + env->astat_arg[2]); + cpu_fprintf(f, " CYCLES: %08x %08x\n", + env->cycles[0], env->cycles[1]); +} + +static void gen_astat_update(DisasContext *, bool); + +static void gen_goto_tb(DisasContext *dc, int tb_num, TCGv dest) +{ + gen_astat_update(dc, false); + tcg_gen_mov_tl(cpu_pc, dest); + tcg_gen_exit_tb(0); +} + +static void gen_gotoi_tb(DisasContext *dc, int tb_num, target_ulong dest) +{ + TCGv tmp = tcg_temp_local_new(); + tcg_gen_movi_tl(tmp, dest); + gen_goto_tb(dc, tb_num, tmp); + tcg_temp_free(tmp); +} + +static void cec_exception(DisasContext *dc, int excp) +{ + TCGv tmp = tcg_const_tl(excp); + TCGv pc = tcg_const_tl(dc->pc); + gen_helper_raise_exception(cpu_env, tmp, pc); + tcg_temp_free(tmp); + dc->is_jmp = DISAS_UPDATE; +} + +static void cec_require_supervisor(DisasContext *dc) +{ +#ifdef CONFIG_LINUX_USER + cec_exception(dc, EXCP_ILL_SUPV); +#else + TCGv pc = tcg_const_tl(dc->pc); + gen_helper_require_supervisor(cpu_env, pc); +#endif +} + +static void gen_align_check(DisasContext *dc, TCGv addr, uint32_t len, + bool inst) +{ + TCGv excp, pc, tmp; + + /* XXX: This should be made into a runtime option. It adds likes + 10% overhead to memory intensive apps (like mp3 decoding). */ + if (1) { + return; + } + + excp = tcg_const_tl(inst ? EXCP_MISALIG_INST : EXCP_DATA_MISALGIN); + pc = tcg_const_tl(dc->pc); + tmp = tcg_const_tl(len); + gen_helper_memalign(cpu_env, excp, pc, addr, tmp); + tcg_temp_free(tmp); + tcg_temp_free(pc); + tcg_temp_free(excp); +} + +static void gen_aligned_qemu_ld16u(DisasContext *dc, TCGv ret, TCGv addr) +{ + gen_align_check(dc, addr, 2, false); + tcg_gen_qemu_ld16u(ret, addr, dc->mem_idx); +} + +static void gen_aligned_qemu_ld16s(DisasContext *dc, TCGv ret, TCGv addr) +{ + gen_align_check(dc, addr, 2, false); + tcg_gen_qemu_ld16s(ret, addr, dc->mem_idx); +} + +static void gen_aligned_qemu_ld32u(DisasContext *dc, TCGv ret, TCGv addr) +{ + gen_align_check(dc, addr, 4, false); + tcg_gen_qemu_ld32u(ret, addr, dc->mem_idx); +} + +static void gen_aligned_qemu_st16(DisasContext *dc, TCGv val, TCGv addr) +{ + gen_align_check(dc, addr, 2, false); + tcg_gen_qemu_st16(val, addr, dc->mem_idx); +} + +static void gen_aligned_qemu_st32(DisasContext *dc, TCGv val, TCGv addr) +{ + gen_align_check(dc, addr, 4, false); + tcg_gen_qemu_st32(val, addr, dc->mem_idx); +} + +/* + * If a LB reg is written, we need to invalidate the two translation + * blocks that could be affected -- the TB's referenced by the old LB + * could have LC/LT handling which we no longer want, and the new LB + * is probably missing LC/LT handling which we want. In both cases, + * we need to regenerate the block. + */ +static void gen_maybe_lb_exit_tb(DisasContext *dc, TCGv reg) +{ + if (!TCGV_EQUAL(reg, cpu_lbreg[0]) && !TCGV_EQUAL(reg, cpu_lbreg[1])) { + return; + } + + /* tb_invalidate_phys_page_range */ + dc->is_jmp = DISAS_UPDATE; + /* XXX: Not entirely correct, but very few things load + * directly into LB ... */ + gen_gotoi_tb(dc, 0, dc->pc + dc->insn_len); +} + +static void gen_hwloop_default(DisasContext *dc, int loop) +{ + if (loop != -1) { + gen_goto_tb(dc, 0, cpu_ltreg[loop]); + } +} + +static void _gen_hwloop_call(DisasContext *dc, int loop) +{ + if (dc->is_jmp != DISAS_CALL) { + return; + } + + if (loop == -1) { + tcg_gen_movi_tl(cpu_rets, dc->pc + dc->insn_len); + } else { + tcg_gen_mov_tl(cpu_rets, cpu_ltreg[loop]); + } +} + +static void gen_hwloop_br_pcrel_cc(DisasContext *dc, int loop) +{ + TCGLabel *l; + int pcrel = (unsigned long)dc->hwloop_data; + int T = pcrel & 1; + pcrel &= ~1; + + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc, T, l); + gen_gotoi_tb(dc, 0, dc->pc + pcrel); + gen_set_label(l); + if (loop == -1) { + dc->hwloop_callback = gen_hwloop_default; + } else { + gen_hwloop_default(dc, loop); + } +} + +static void gen_hwloop_br_pcrel(DisasContext *dc, int loop) +{ + TCGv *reg = dc->hwloop_data; + _gen_hwloop_call(dc, loop); + tcg_gen_addi_tl(cpu_pc, *reg, dc->pc); + gen_goto_tb(dc, 0, cpu_pc); +} + +static void gen_hwloop_br_pcrel_imm(DisasContext *dc, int loop) +{ + int pcrel = (unsigned long)dc->hwloop_data; + TCGv tmp; + + _gen_hwloop_call(dc, loop); + tmp = tcg_const_tl(pcrel); + tcg_gen_addi_tl(cpu_pc, tmp, dc->pc); + tcg_temp_free(tmp); + gen_goto_tb(dc, 0, cpu_pc); +} + +static void gen_hwloop_br_direct(DisasContext *dc, int loop) +{ + TCGv *reg = dc->hwloop_data; + _gen_hwloop_call(dc, loop); + gen_goto_tb(dc, 0, *reg); +} + +static void _gen_hwloop_check(DisasContext *dc, int loop, TCGLabel *l) +{ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_lcreg[loop], 0, l); + tcg_gen_subi_tl(cpu_lcreg[loop], cpu_lcreg[loop], 1); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_lcreg[loop], 0, l); + dc->hwloop_callback(dc, loop); +} + +static void gen_hwloop_check(DisasContext *dc) +{ + bool loop1, loop0; + TCGLabel *endl; + + loop1 = (dc->pc == dc->env->lbreg[1]); + loop0 = (dc->pc == dc->env->lbreg[0]); + + if (loop1 || loop0) { + endl = gen_new_label(); + } + + if (loop1) { + TCGLabel *l; + if (loop0) { + l = gen_new_label(); + } else { + l = endl; + } + + _gen_hwloop_check(dc, 1, l); + + if (loop0) { + tcg_gen_br(endl); + gen_set_label(l); + } + } + + if (loop0) { + _gen_hwloop_check(dc, 0, endl); + } + + if (loop1 || loop0) { + gen_set_label(endl); + } + + dc->hwloop_callback(dc, -1); +} + +/* R#.L = reg; R#.H = reg; */ +/* XXX: This modifies the low source ... assumes it is a temp ... */ +/* +static void gen_mov_l_h_tl(TCGv dst, TCGv srcl, TCGv srch) +{ + tcg_gen_shli_tl(dst, srch, 16); + tcg_gen_andi_tl(srcl, srcl, 0xffff); + tcg_gen_or_tl(dst, dst, srcl); +} +*/ + +/* R#.L = reg */ +static void gen_mov_l_tl(TCGv dst, TCGv src) +{ + tcg_gen_deposit_tl(dst, dst, src, 0, 16); +} + +/* R#.L = imm32 */ +/* +static void gen_movi_l_tl(TCGv dst, uint32_t src) +{ + tcg_gen_andi_tl(dst, dst, 0xffff0000); + tcg_gen_ori_tl(dst, dst, src & 0xffff); +} +*/ + +/* R#.H = reg */ +static void gen_mov_h_tl(TCGv dst, TCGv src) +{ + tcg_gen_deposit_tl(dst, dst, src, 16, 16); +} + +/* R#.H = imm32 */ +/* +static void gen_movi_h_tl(TCGv dst, uint32_t src) +{ + tcg_gen_andi_tl(dst, dst, 0xffff); + tcg_gen_ori_tl(dst, dst, src << 16); +} +*/ + +static void gen_extNs_tl(TCGv dst, TCGv src, TCGv n) +{ + /* Shift the sign bit up, and then back down */ + TCGv tmp = tcg_temp_new(); + tcg_gen_subfi_tl(tmp, 32, n); + tcg_gen_shl_tl(dst, src, tmp); + tcg_gen_sar_tl(dst, dst, tmp); + tcg_temp_free(tmp); +} + +static void gen_extNsi_tl(TCGv dst, TCGv src, uint32_t n) +{ + /* Shift the sign bit up, and then back down */ + tcg_gen_shli_tl(dst, src, 32 - n); + tcg_gen_sari_tl(dst, dst, 32 - n); +} + +static void gen_extNsi_i64(TCGv_i64 dst, TCGv_i64 src, uint32_t n) +{ + /* Shift the sign bit up, and then back down */ + tcg_gen_shli_i64(dst, src, 64 - n); + tcg_gen_sari_i64(dst, dst, 64 - n); +} + +static void gen_abs_tl(TCGv ret, TCGv arg) +{ + TCGLabel *l = gen_new_label(); + tcg_gen_mov_tl(ret, arg); + tcg_gen_brcondi_tl(TCG_COND_GE, arg, 0, l); + tcg_gen_neg_tl(ret, ret); + gen_set_label(l); +} + +static void gen_abs_i64(TCGv_i64 ret, TCGv_i64 arg) +{ + TCGLabel *l = gen_new_label(); + tcg_gen_mov_i64(ret, arg); + tcg_gen_brcondi_i64(TCG_COND_GE, arg, 0, l); + tcg_gen_neg_i64(ret, ret); + gen_set_label(l); +} + +/* Common tail code for DIVQ/DIVS insns */ +static void _gen_divqs(TCGv pquo, TCGv r, TCGv aq, TCGv div) +{ + /* + * pquo <<= 1 + * pquo |= aq + * pquo = (pquo & 0x1FFFF) | (r << 17) + */ + tcg_gen_shli_tl(pquo, pquo, 1); + tcg_gen_or_tl(pquo, pquo, aq); + tcg_gen_andi_tl(pquo, pquo, 0x1FFFF); + tcg_gen_shli_tl(r, r, 17); + tcg_gen_or_tl(pquo, pquo, r); + + tcg_temp_free(r); + tcg_temp_free(aq); + tcg_temp_free(div); +} + +/* Common AQ ASTAT bit management for DIVQ/DIVS insns */ +static void _gen_divqs_st_aq(TCGv r, TCGv aq, TCGv div) +{ + /* aq = (r ^ div) >> 15 */ + tcg_gen_xor_tl(aq, r, div); + tcg_gen_shri_tl(aq, aq, 15); + tcg_gen_andi_tl(aq, aq, 1); + tcg_gen_st_tl(aq, cpu_env, offsetof(CPUArchState, astat[ASTAT_AQ])); +} + +/* DIVQ ( Dreg, Dreg ) ; + * Based on AQ status bit, either add or subtract the divisor from + * the dividend. Then set the AQ status bit based on the MSBs of the + * 32-bit dividend and the 16-bit divisor. Left shift the dividend one + * bit. Copy the logical inverse of AQ into the dividend LSB. + */ +static void gen_divq(TCGv pquo, TCGv src) +{ + TCGLabel *l; + TCGv af, r, aq, div; + + /* div = R#.L */ + div = tcg_temp_local_new(); + tcg_gen_ext16u_tl(div, src); + + /* af = pquo >> 16 */ + af = tcg_temp_local_new(); + tcg_gen_shri_tl(af, pquo, 16); + + /* + * we take this: + * if (ASTAT_AQ) + * r = div + af; + * else + * r = af - div; + * + * and turn it into: + * r = div; + * if (aq == 0) + * r = -r; + * r += af; + */ + aq = tcg_temp_local_new(); + tcg_gen_ld_tl(aq, cpu_env, offsetof(CPUArchState, astat[ASTAT_AQ])); + + l = gen_new_label(); + r = tcg_temp_local_new(); + tcg_gen_mov_tl(r, div); + tcg_gen_brcondi_tl(TCG_COND_NE, aq, 0, l); + tcg_gen_neg_tl(r, r); + gen_set_label(l); + tcg_gen_add_tl(r, r, af); + + tcg_temp_free(af); + + _gen_divqs_st_aq(r, aq, div); + + /* aq = !aq */ + tcg_gen_xori_tl(aq, aq, 1); + + _gen_divqs(pquo, r, aq, div); +} + +/* DIVS ( Dreg, Dreg ) ; + * Initialize for DIVQ. Set the AQ status bit based on the signs of + * the 32-bit dividend and the 16-bit divisor. Left shift the dividend + * one bit. Copy AQ into the dividend LSB. + */ +static void gen_divs(TCGv pquo, TCGv src) +{ + TCGv r, aq, div; + + /* div = R#.L */ + div = tcg_temp_local_new(); + tcg_gen_ext16u_tl(div, src); + + /* r = pquo >> 16 */ + r = tcg_temp_local_new(); + tcg_gen_shri_tl(r, pquo, 16); + + aq = tcg_temp_local_new(); + + _gen_divqs_st_aq(r, aq, div); + + _gen_divqs(pquo, r, aq, div); +} + +/* Reg = ROT reg BY reg/imm + * The Blackfin rotate is not like the TCG rotate. It shifts through the + * CC bit too giving it 33 bits to play with. So we have to reduce things + * to shifts ourself. + */ +static void gen_rot_tl(TCGv dst, TCGv src, TCGv orig_shift) +{ + uint32_t nbits = 32; + TCGv shift, ret, tmp, tmp_shift; + TCGLabel *l, *endl; + + /* shift = CLAMP (shift, -nbits, nbits); */ + + endl = gen_new_label(); + + /* if (shift == 0) */ + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, orig_shift, 0, l); + tcg_gen_mov_tl(dst, src); + tcg_gen_br(endl); + gen_set_label(l); + + /* Reduce everything to rotate left */ + shift = tcg_temp_local_new(); + tcg_gen_mov_tl(shift, orig_shift); + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_GE, shift, 0, l); + tcg_gen_addi_tl(shift, shift, nbits + 1); + gen_set_label(l); + + if (TCGV_EQUAL(dst, src)) { + ret = tcg_temp_local_new(); + } else { + ret = dst; + } + + /* ret = shift == nbits ? 0 : val << shift; */ + tcg_gen_movi_tl(ret, 0); + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, shift, nbits, l); + tcg_gen_shl_tl(ret, src, shift); + gen_set_label(l); + + /* ret |= shift == 1 ? 0 : val >> ((nbits + 1) - shift); */ + l = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, shift, 1, l); + tmp = tcg_temp_new(); + tmp_shift = tcg_temp_new(); + tcg_gen_subfi_tl(tmp_shift, nbits + 1, shift); + tcg_gen_shr_tl(tmp, src, tmp_shift); + tcg_gen_or_tl(ret, ret, tmp); + tcg_temp_free(tmp_shift); + tcg_temp_free(tmp); + gen_set_label(l); + + /* Then add in and output feedback via the CC register */ + tcg_gen_subi_tl(shift, shift, 1); + tcg_gen_shl_tl(cpu_cc, cpu_cc, shift); + tcg_gen_or_tl(ret, ret, cpu_cc); + tcg_gen_subfi_tl(shift, nbits - 1, shift); + tcg_gen_shr_tl(cpu_cc, src, shift); + tcg_gen_andi_tl(cpu_cc, cpu_cc, 1); + + if (TCGV_EQUAL(dst, src)) { + tcg_gen_mov_tl(dst, ret); + tcg_temp_free(ret); + } + + tcg_temp_free(shift); + gen_set_label(endl); +} + +static void gen_roti_tl(TCGv dst, TCGv src, int32_t shift) +{ + uint32_t nbits = 32; + TCGv ret; + + /* shift = CLAMP (shift, -nbits, nbits); */ + + if (shift == 0) { + tcg_gen_mov_tl(dst, src); + return; + } + + /* Reduce everything to rotate left */ + if (shift < 0) { + shift += nbits + 1; + } + + if (TCGV_EQUAL(dst, src)) { + ret = tcg_temp_new(); + } else { + ret = dst; + } + + /* First rotate the main register */ + if (shift == nbits) { + tcg_gen_movi_tl(ret, 0); + } else { + tcg_gen_shli_tl(ret, src, shift); + } + if (shift != 1) { + TCGv tmp = tcg_temp_new(); + tcg_gen_shri_tl(tmp, src, (nbits + 1) - shift); + tcg_gen_or_tl(ret, ret, tmp); + tcg_temp_free(tmp); + } + + /* Then add in and output feedback via the CC register */ + tcg_gen_shli_tl(cpu_cc, cpu_cc, shift - 1); + tcg_gen_or_tl(ret, ret, cpu_cc); + tcg_gen_shri_tl(cpu_cc, src, nbits - shift); + tcg_gen_andi_tl(cpu_cc, cpu_cc, 1); + + if (TCGV_EQUAL(dst, src)) { + tcg_gen_mov_tl(dst, ret); + tcg_temp_free(ret); + } +} + +static void gen_rot_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 orig_shift) +{ + uint32_t nbits = 40; + TCGv_i64 shift, ret, tmp, tmp_shift, cc64; + TCGLabel *l, *endl; + + /* shift = CLAMP (shift, -nbits, nbits); */ + + endl = gen_new_label(); + + /* if (shift == 0) */ + l = gen_new_label(); + tcg_gen_brcondi_i64(TCG_COND_NE, orig_shift, 0, l); + tcg_gen_mov_i64(dst, src); + tcg_gen_br(endl); + gen_set_label(l); + + /* Reduce everything to rotate left */ + shift = tcg_temp_local_new_i64(); + tcg_gen_mov_i64(shift, orig_shift); + l = gen_new_label(); + tcg_gen_brcondi_i64(TCG_COND_GE, shift, 0, l); + tcg_gen_addi_i64(shift, shift, nbits + 1); + gen_set_label(l); + + if (TCGV_EQUAL_I64(dst, src)) { + ret = tcg_temp_local_new_i64(); + } else { + ret = dst; + } + + /* ret = shift == nbits ? 0 : val << shift; */ + tcg_gen_movi_i64(ret, 0); + l = gen_new_label(); + tcg_gen_brcondi_i64(TCG_COND_EQ, shift, nbits, l); + tcg_gen_shl_i64(ret, src, shift); + gen_set_label(l); + + /* ret |= shift == 1 ? 0 : val >> ((nbits + 1) - shift); */ + l = gen_new_label(); + tcg_gen_brcondi_i64(TCG_COND_EQ, shift, 1, l); + tmp = tcg_temp_new_i64(); + tmp_shift = tcg_temp_new_i64(); + tcg_gen_subfi_i64(tmp_shift, nbits + 1, shift); + tcg_gen_shr_i64(tmp, src, tmp_shift); + tcg_gen_or_i64(ret, ret, tmp); + tcg_temp_free_i64(tmp_shift); + tcg_temp_free_i64(tmp); + gen_set_label(l); + + /* Then add in and output feedback via the CC register */ + cc64 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(cc64, cpu_cc); + tcg_gen_subi_i64(shift, shift, 1); + tcg_gen_shl_i64(cc64, cc64, shift); + tcg_gen_or_i64(ret, ret, cc64); + tcg_gen_subfi_i64(shift, nbits - 1, shift); + tcg_gen_shr_i64(cc64, src, shift); + tcg_gen_andi_i64(cc64, cc64, 1); + tcg_gen_extrl_i64_i32(cpu_cc, cc64); + tcg_temp_free_i64(cc64); + + if (TCGV_EQUAL_I64(dst, src)) { + tcg_gen_mov_i64(dst, ret); + tcg_temp_free_i64(ret); + } + + tcg_temp_free_i64(shift); + gen_set_label(endl); +} + +static void gen_roti_i64(TCGv_i64 dst, TCGv_i64 src, int32_t shift) +{ + uint32_t nbits = 40; + TCGv_i64 ret, cc64; + + /* shift = CLAMP (shift, -nbits, nbits); */ + + if (shift == 0) { + tcg_gen_mov_i64(dst, src); + return; + } + + /* Reduce everything to rotate left */ + if (shift < 0) { + shift += nbits + 1; + } + + if (TCGV_EQUAL_I64(dst, src)) { + ret = tcg_temp_new_i64(); + } else { + ret = dst; + } + + /* First rotate the main register */ + if (shift == nbits) { + tcg_gen_movi_i64(ret, 0); + } else { + tcg_gen_shli_i64(ret, src, shift); + } + if (shift != 1) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_shri_i64(tmp, src, (nbits + 1) - shift); + tcg_gen_or_i64(ret, ret, tmp); + tcg_temp_free_i64(tmp); + } + + /* Then add in and output feedback via the CC register */ + cc64 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(cc64, cpu_cc); + tcg_gen_shli_i64(cc64, cc64, shift - 1); + tcg_gen_or_i64(ret, ret, cc64); + tcg_gen_shri_i64(cc64, src, nbits - shift); + tcg_gen_andi_i64(cc64, cc64, 1); + tcg_gen_extrl_i64_i32(cpu_cc, cc64); + tcg_temp_free_i64(cc64); + + if (TCGV_EQUAL_I64(dst, src)) { + tcg_gen_mov_i64(dst, ret); + tcg_temp_free_i64(ret); + } +} + +/* This is a bit crazy, but we want to simulate the hardware behavior exactly + rather than worry about the circular buffers being used correctly. Which + isn't to say there isn't room for improvement here, just that we want to + be conservative. See also dagsub(). */ +static void gen_dagadd(DisasContext *dc, int dagno, TCGv M) +{ + TCGLabel *l, *endl; + + /* Optimize for when circ buffers are not used */ + l = gen_new_label(); + endl = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_lreg[dagno], 0, l); + tcg_gen_add_tl(cpu_ireg[dagno], cpu_ireg[dagno], M); + tcg_gen_br(endl); + gen_set_label(l); + + /* Fallback to the big guns */ + gen_helper_dagadd(cpu_ireg[dagno], cpu_ireg[dagno], + cpu_lreg[dagno], cpu_breg[dagno], M); + + gen_set_label(endl); +} + +static void gen_dagaddi(DisasContext *dc, int dagno, uint32_t M) +{ + TCGv m = tcg_temp_local_new(); + tcg_gen_movi_tl(m, M); + gen_dagadd(dc, dagno, m); + tcg_temp_free(m); +} + +/* See dagadd() notes above. */ +static void gen_dagsub(DisasContext *dc, int dagno, TCGv M) +{ + TCGLabel *l, *endl; + + /* Optimize for when circ buffers are not used */ + l = gen_new_label(); + endl = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_lreg[dagno], 0, l); + tcg_gen_sub_tl(cpu_ireg[dagno], cpu_ireg[dagno], M); + tcg_gen_br(endl); + gen_set_label(l); + + /* Fallback to the big guns */ + gen_helper_dagsub(cpu_ireg[dagno], cpu_ireg[dagno], + cpu_lreg[dagno], cpu_breg[dagno], M); + + gen_set_label(endl); +} + +static void gen_dagsubi(DisasContext *dc, int dagno, uint32_t M) +{ + TCGv m = tcg_temp_local_new(); + tcg_gen_movi_tl(m, M); + gen_dagsub(dc, dagno, m); + tcg_temp_free(m); +} + +#define _gen_astat_store(bit, reg) \ + tcg_gen_st_tl(reg, cpu_env, offsetof(CPUArchState, astat[bit])) + +static void _gen_astat_update_az(TCGv reg, TCGv tmp) +{ + tcg_gen_setcondi_tl(TCG_COND_EQ, tmp, reg, 0); + _gen_astat_store(ASTAT_AZ, tmp); +} + +static void _gen_astat_update_az2(TCGv reg, TCGv reg2, TCGv tmp) +{ + TCGv tmp2 = tcg_temp_new(); + tcg_gen_setcondi_tl(TCG_COND_EQ, tmp, reg, 0); + tcg_gen_setcondi_tl(TCG_COND_EQ, tmp2, reg2, 0); + tcg_gen_or_tl(tmp, tmp, tmp2); + tcg_temp_free(tmp2); + _gen_astat_store(ASTAT_AZ, tmp); +} + +static void _gen_astat_update_an(TCGv reg, TCGv tmp, uint32_t len) +{ + tcg_gen_setcondi_tl(TCG_COND_GEU, tmp, reg, 1 << (len - 1)); + _gen_astat_store(ASTAT_AN, tmp); +} + +static void _gen_astat_update_an2(TCGv reg, TCGv reg2, TCGv tmp, uint32_t len) +{ + TCGv tmp2 = tcg_temp_new(); + tcg_gen_setcondi_tl(TCG_COND_GEU, tmp, reg, 1 << (len - 1)); + tcg_gen_setcondi_tl(TCG_COND_GEU, tmp2, reg2, 1 << (len - 1)); + tcg_gen_or_tl(tmp, tmp, tmp2); + tcg_temp_free(tmp2); + _gen_astat_store(ASTAT_AN, tmp); +} + +static void _gen_astat_update_nz(TCGv reg, TCGv tmp, uint32_t len) +{ + _gen_astat_update_az(reg, tmp); + _gen_astat_update_an(reg, tmp, len); +} + +static void _gen_astat_update_nz2(TCGv reg, TCGv reg2, TCGv tmp, uint32_t len) +{ + _gen_astat_update_az2(reg, reg2, tmp); + _gen_astat_update_an2(reg, reg2, tmp, len); +} + +static void gen_astat_update(DisasContext *dc, bool clear) +{ + TCGv tmp = tcg_temp_local_new(); + uint32_t len = 16; + + switch (dc->astat_op) { + case ASTAT_OP_ABS: /* [0] = ABS( [1] ) */ + len = 32; + /* XXX: Missing V/VS updates */ + _gen_astat_update_nz(cpu_astat_arg[0], tmp, len); + break; + + case ASTAT_OP_ABS_VECTOR: /* [0][1] = ABS( [2] ) (V) */ + /* XXX: Missing V/VS updates */ + _gen_astat_update_nz2(cpu_astat_arg[0], cpu_astat_arg[1], tmp, len); + break; + + case ASTAT_OP_ADD32: /* [0] = [1] + [2] */ + /* XXX: Missing V/VS updates */ + len = 32; + tcg_gen_not_tl(tmp, cpu_astat_arg[1]); + tcg_gen_setcond_tl(TCG_COND_LTU, tmp, tmp, cpu_astat_arg[2]); + _gen_astat_store(ASTAT_AC0, tmp); + _gen_astat_store(ASTAT_AC0_COPY, tmp); + _gen_astat_update_nz(cpu_astat_arg[0], tmp, 32); + break; + + case ASTAT_OP_ASHIFT32: + len *= 2; + case ASTAT_OP_ASHIFT16: + tcg_gen_movi_tl(tmp, 0); + /* Need to update AC0 ? */ + _gen_astat_store(ASTAT_V, tmp); + _gen_astat_store(ASTAT_V_COPY, tmp); + _gen_astat_update_nz(cpu_astat_arg[0], tmp, len); + break; + + case ASTAT_OP_COMPARE_SIGNED: { + TCGv flgs, flgo, overflow, flgn, res = tcg_temp_new(); + tcg_gen_sub_tl(res, cpu_astat_arg[0], cpu_astat_arg[1]); + _gen_astat_update_az(res, tmp); + tcg_gen_setcond_tl(TCG_COND_LEU, tmp, cpu_astat_arg[1], + cpu_astat_arg[0]); + _gen_astat_store(ASTAT_AC0, tmp); + _gen_astat_store(ASTAT_AC0_COPY, tmp); + /* XXX: This has got to be simpler ... */ + /* int flgs = srcop >> 31; */ + flgs = tcg_temp_new(); + tcg_gen_shri_tl(flgs, cpu_astat_arg[0], 31); + /* int flgo = dstop >> 31; */ + flgo = tcg_temp_new(); + tcg_gen_shri_tl(flgo, cpu_astat_arg[1], 31); + /* int flgn = result >> 31; */ + flgn = tcg_temp_new(); + tcg_gen_shri_tl(flgn, res, 31); + /* int overflow = (flgs ^ flgo) & (flgn ^ flgs); */ + overflow = tcg_temp_new(); + tcg_gen_xor_tl(tmp, flgs, flgo); + tcg_gen_xor_tl(overflow, flgn, flgs); + tcg_gen_and_tl(overflow, tmp, overflow); + /* an = (flgn && !overflow) || (!flgn && overflow); */ + tcg_gen_not_tl(tmp, overflow); + tcg_gen_and_tl(tmp, flgn, tmp); + tcg_gen_not_tl(res, flgn); + tcg_gen_and_tl(res, res, overflow); + tcg_gen_or_tl(tmp, tmp, res); + tcg_temp_free(flgn); + tcg_temp_free(overflow); + tcg_temp_free(flgo); + tcg_temp_free(flgs); + tcg_temp_free(res); + _gen_astat_store(ASTAT_AN, tmp); + break; + } + + case ASTAT_OP_COMPARE_UNSIGNED: + tcg_gen_sub_tl(tmp, cpu_astat_arg[0], cpu_astat_arg[1]); + _gen_astat_update_az(tmp, tmp); + tcg_gen_setcond_tl(TCG_COND_LEU, tmp, cpu_astat_arg[1], + cpu_astat_arg[0]); + _gen_astat_store(ASTAT_AC0, tmp); + _gen_astat_store(ASTAT_AC0_COPY, tmp); + tcg_gen_setcond_tl(TCG_COND_GTU, tmp, cpu_astat_arg[1], + cpu_astat_arg[0]); + _gen_astat_store(ASTAT_AN, tmp); + break; + + case ASTAT_OP_LOGICAL: + len = 32; + tcg_gen_movi_tl(tmp, 0); + /* AC0 is correct ? */ + _gen_astat_store(ASTAT_AC0, tmp); + _gen_astat_store(ASTAT_AC0_COPY, tmp); + _gen_astat_store(ASTAT_V, tmp); + _gen_astat_store(ASTAT_V_COPY, tmp); + _gen_astat_update_nz(cpu_astat_arg[0], tmp, len); + break; + + case ASTAT_OP_LSHIFT32: + len *= 2; + case ASTAT_OP_LSHIFT16: + _gen_astat_update_az(cpu_astat_arg[0], tmp); + /* XXX: should be checking bit shifted */ + tcg_gen_setcondi_tl(TCG_COND_GEU, tmp, cpu_astat_arg[0], + 1 << (len - 1)); + _gen_astat_store(ASTAT_AN, tmp); + /* XXX: No saturation handling ... */ + tcg_gen_movi_tl(tmp, 0); + _gen_astat_store(ASTAT_V, tmp); + _gen_astat_store(ASTAT_V_COPY, tmp); + break; + + case ASTAT_OP_LSHIFT_RT32: + len *= 2; + case ASTAT_OP_LSHIFT_RT16: + _gen_astat_update_az(cpu_astat_arg[0], tmp); + /* XXX: should be checking bit shifted */ + tcg_gen_setcondi_tl(TCG_COND_GEU, tmp, cpu_astat_arg[0], + 1 << (len - 1)); + _gen_astat_store(ASTAT_AN, tmp); + tcg_gen_movi_tl(tmp, 0); + _gen_astat_store(ASTAT_V, tmp); + _gen_astat_store(ASTAT_V_COPY, tmp); + break; + + case ASTAT_OP_MIN_MAX: /* [0] = MAX/MIN( [1], [2] ) */ + tcg_gen_movi_tl(tmp, 0); + _gen_astat_store(ASTAT_V, tmp); + _gen_astat_store(ASTAT_V_COPY, tmp); + _gen_astat_update_nz(cpu_astat_arg[0], tmp, 32); + break; + + case ASTAT_OP_MIN_MAX_VECTOR: /* [0][1] = MAX/MIN( [2], [3] ) (V) */ + tcg_gen_movi_tl(tmp, 0); + _gen_astat_store(ASTAT_V, tmp); + _gen_astat_store(ASTAT_V_COPY, tmp); + tcg_gen_sari_tl(cpu_astat_arg[0], cpu_astat_arg[0], 16); + _gen_astat_update_nz2(cpu_astat_arg[0], cpu_astat_arg[1], tmp, 16); + break; + + case ASTAT_OP_NEGATE: /* [0] = -[1] */ + len = 32; + _gen_astat_update_nz(cpu_astat_arg[0], tmp, 32); + tcg_gen_setcondi_tl(TCG_COND_EQ, tmp, cpu_astat_arg[0], 1 << (len - 1)); + _gen_astat_store(ASTAT_V, tmp); + /* XXX: Should "VS |= V;" */ + tcg_gen_setcondi_tl(TCG_COND_EQ, tmp, cpu_astat_arg[0], 0); + _gen_astat_store(ASTAT_AC0, tmp); + break; + + case ASTAT_OP_SUB32: /* [0] = [1] - [2] */ + len = 32; + /* XXX: Missing V/VS updates */ + tcg_gen_setcond_tl(TCG_COND_LEU, tmp, cpu_astat_arg[2], + cpu_astat_arg[1]); + _gen_astat_store(ASTAT_AC0, tmp); + _gen_astat_store(ASTAT_AC0_COPY, tmp); + _gen_astat_update_nz(cpu_astat_arg[0], tmp, len); + break; + + case ASTAT_OP_VECTOR_ADD_ADD: /* [0][1] = [2] +|+ [3] */ + case ASTAT_OP_VECTOR_ADD_SUB: /* [0][1] = [2] +|- [3] */ + case ASTAT_OP_VECTOR_SUB_SUB: /* [0][1] = [2] -|- [3] */ + case ASTAT_OP_VECTOR_SUB_ADD: /* [0][1] = [2] -|+ [3] */ + _gen_astat_update_az2(cpu_astat_arg[0], cpu_astat_arg[1], tmp); + /* Need AN, AC0/AC1, V */ + break; + + default: + fprintf(stderr, "qemu: unhandled astat op %u\n", dc->astat_op); + abort(); + case ASTAT_OP_DYNAMIC: + case ASTAT_OP_NONE: + break; + } + + tcg_temp_free(tmp); + + if (clear) { + dc->astat_op = ASTAT_OP_NONE; + } +} + +static void +_astat_queue_state(DisasContext *dc, enum astat_ops op, unsigned int num, + TCGv arg0, TCGv arg1, TCGv arg2) +{ + dc->astat_op = op; + + tcg_gen_mov_tl(cpu_astat_arg[0], arg0); + if (num > 1) { + tcg_gen_mov_tl(cpu_astat_arg[1], arg1); + } else { + tcg_gen_discard_tl(cpu_astat_arg[1]); + } + if (num > 2) { + tcg_gen_mov_tl(cpu_astat_arg[2], arg2); + } else { + tcg_gen_discard_tl(cpu_astat_arg[2]); + } +} +#define astat_queue_state1(dc, op, arg0) \ + _astat_queue_state(dc, op, 1, arg0, arg0, arg0) +#define astat_queue_state2(dc, op, arg0, arg1) \ + _astat_queue_state(dc, op, 2, arg0, arg1, arg1) +#define astat_queue_state3(dc, op, arg0, arg1, arg2) \ + _astat_queue_state(dc, op, 3, arg0, arg1, arg2) + +static void gen_astat_load(DisasContext *dc, TCGv reg) +{ + gen_astat_update(dc, true); + gen_helper_astat_load(reg, cpu_env); +} + +static void gen_astat_store(DisasContext *dc, TCGv reg) +{ + unsigned int i; + + gen_helper_astat_store(cpu_env, reg); + + dc->astat_op = ASTAT_OP_NONE; + + for (i = 0; i < ARRAY_SIZE(cpu_astat_arg); ++i) { + tcg_gen_discard_tl(cpu_astat_arg[i]); + } +} + +static void interp_insn_bfin(DisasContext *dc); + +void gen_intermediate_code(CPUArchState *env, TranslationBlock *tb) +{ + BlackfinCPU *cpu = bfin_env_get_cpu(env); + CPUState *cs = CPU(cpu); + uint32_t pc_start; + struct DisasContext ctx; + struct DisasContext *dc = &ctx; + uint32_t next_page_start; + int num_insns; + int max_insns; + + pc_start = tb->pc; + dc->env = env; + dc->tb = tb; + /* XXX: handle super/user mode here. */ + dc->mem_idx = 0; + + dc->is_jmp = DISAS_NEXT; + dc->pc = pc_start; + dc->astat_op = ASTAT_OP_DYNAMIC; + dc->hwloop_callback = gen_hwloop_default; + dc->disalgnexcpt = 1; + + next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + num_insns = 0; + max_insns = tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) { + max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } + + gen_tb_start(tb); + do { +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. The personality check is a + * bit of a hack that let's us run standalone ELFs (which are all of the + * tests. This way only Linux ELFs get caught here. */ + if (((dc->env->personality & 0xff/*PER_MASK*/) == 0/*PER_LINUX*/) && + (dc->pc & 0xFFFFFF00) == 0x400) { + cec_exception(dc, EXCP_FIXED_CODE); + break; + } +#endif + + if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + cec_exception(dc, EXCP_DEBUG); + dc->is_jmp = DISAS_UPDATE; + } + tcg_gen_insn_start(dc->pc); + ++num_insns; + + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { + gen_io_start(); + } + + interp_insn_bfin(dc); + gen_hwloop_check(dc); + dc->pc += dc->insn_len; + } while (!dc->is_jmp && + !tcg_op_buf_full() && + !cs->singlestep_enabled && + !singlestep && + dc->pc < next_page_start && + num_insns < max_insns); + + if (tb->cflags & CF_LAST_IO) { + gen_io_end(); + } + + if (unlikely(cs->singlestep_enabled)) { + cec_exception(dc, EXCP_DEBUG); + } else { + switch (dc->is_jmp) { + case DISAS_NEXT: + gen_gotoi_tb(dc, 1, dc->pc); + break; + default: + case DISAS_UPDATE: + /* indicate that the hash table must be used + to find the next TB */ + tcg_gen_exit_tb(0); + break; + case DISAS_CALL: + case DISAS_JUMP: + case DISAS_TB_JUMP: + /* nothing more to generate */ + break; + } + } + + gen_tb_end(tb, num_insns); + + tb->size = dc->pc - pc_start; + tb->icount = num_insns; + +#ifdef DEBUG_DISAS + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { + qemu_log("----------------\n"); + qemu_log("IN: %s\n", lookup_symbol(pc_start)); + log_target_disas(cs, pc_start, dc->pc - pc_start, 0); + qemu_log("\n"); + } +#endif +} + +void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb, + target_ulong *data) +{ + env->pc = data[0]; +} + +#include "bfin-sim.c" diff --git a/tests/tcg/Makefile b/tests/tcg/Makefile index 89e3342f3db67..b9a71880a19af 100644 --- a/tests/tcg/Makefile +++ b/tests/tcg/Makefile @@ -151,6 +151,10 @@ test-cris: test-lm32: $(MAKE) -C lm32 check +# testsuite for the Blackfin port. +test-bfin: + $(MAKE) -C bfin check + clean: rm -f *~ *.o test-i386.out test-i386.ref \ test-x86_64.log test-x86_64.ref qruncom $(TESTS) diff --git a/tests/tcg/bfin/.gitignore b/tests/tcg/bfin/.gitignore new file mode 100644 index 0000000000000..788ebb9c92a1a --- /dev/null +++ b/tests/tcg/bfin/.gitignore @@ -0,0 +1,2 @@ +*.x +*.X diff --git a/tests/tcg/bfin/10272_small.s b/tests/tcg/bfin/10272_small.s new file mode 100644 index 0000000000000..b260f9cc9905c --- /dev/null +++ b/tests/tcg/bfin/10272_small.s @@ -0,0 +1,51 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym P5, tmp0; + + r6=0xFF (Z); + W[p5+0x6] = r6; + + r0.l=0x0808; + r0.h=0xffff; + + R1 = W[P5 + 0x6 ] (X); + R0 = DEPOSIT(R1, R0); + W[P5+0x6] = R0; + + R5=W[P5+0x6] (X); + DBGA(r5.l,0xffff); + + /* This instruction order fails to successfully write R0 back */ + r0.l=0x0808; + r0.h=0xffff; + + loadsym P5, tmp0; + + r6=0xFF (Z); + W[p5+0x6] = r6; + R1 = W[P5 + 0x6 ] (X); + R0 = DEPOSIT(R1, R0); + W[P5+0x6] = R0; + + R5=W[P5+0x6] (X); + DBGA(r5.l,0xffff); + + r4=1; + loadsym P5, tmp0; + r6=0xFF (Z); + W[p5+0x6] = r6; + R1 = W[P5 + 0x6 ] (X); + R0 = R1+R4; + W[P5+0x6] = R0; + + R5=W[P5+0x6] (X); + DBGA(r5.l,0x100); + + pass; + + .data +tmp0: + .space (0x10); diff --git a/tests/tcg/bfin/10436.s b/tests/tcg/bfin/10436.s new file mode 100644 index 0000000000000..9975436978494 --- /dev/null +++ b/tests/tcg/bfin/10436.s @@ -0,0 +1,39 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym i0, tmp0; + + r1 = i0; + b0=i0; + r3=4; + l0=0; + m0=0; + + r5.l=0xdead; + r5.h=0xbeef; + + l0=r3; + [i0++] = r5; + l0 = 0; + r0 = i0; + + CC = R0 == R1; + if !CC JUMP _fail; + + l0=r3; + r3=[i0--]; + r0=i0; + + CC = R0 == R1; + if !CC JUMP _fail; + + pass + +_fail: + fail + + .data +tmp0: + .space (0x100); diff --git a/tests/tcg/bfin/10622.s b/tests/tcg/bfin/10622.s new file mode 100644 index 0000000000000..67076afe6881f --- /dev/null +++ b/tests/tcg/bfin/10622.s @@ -0,0 +1,21 @@ +# mach: bfin + +.include "testutils.inc" + start + + r2.l = 0x1234; + r2.h = 0xff90; + + r4=8; + i2=r2; + m2 = 4; + a0 = 0; + r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; + + r0 = i2; + + dbga(r0.l, 0x1238); + dbga(r0.h, 0xff90); + +_halt0: + pass; diff --git a/tests/tcg/bfin/10742.s b/tests/tcg/bfin/10742.s new file mode 100644 index 0000000000000..67cb6c99a5acc --- /dev/null +++ b/tests/tcg/bfin/10742.s @@ -0,0 +1,17 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r5.h=0x1234; + r5.l=0x5678; + + p5 = r5; + p5.l = 0x1000; + + r0 = p5; + dbga(r0.h, 0x1234); + dbga(r0.l, 0x1000); + + pass diff --git a/tests/tcg/bfin/10799.s b/tests/tcg/bfin/10799.s new file mode 100644 index 0000000000000..76e1eb32b512a --- /dev/null +++ b/tests/tcg/bfin/10799.s @@ -0,0 +1,55 @@ +# mach: bfin + +.include "testutils.inc" + start + + fp = sp; + + [--SP]=RETS; + + loadsym R1, _b; + loadsym R2, _a; + R0 = R2; + + SP += -12; + R2 = 4; + + CALL _dot; + R1 = R0; + + R0 = 30; + dbga( r1.l, 0x1e); + + + pass + +_dot: + P0 = R1; + CC = R2 <= 0; + R3 = R0; + R0 = 0; + IF CC JUMP ._P1L1 (bp); + R0 = 1; + I0 = R3; + R0 = MAX (R0,R2) || R2 = [P0++] || NOP; + P1 = R0; + R0 = 0; + R1 = [I0++]; + LSETUP (._P1L4 , ._P1L5) LC0=P1; + +._P1L4: + R1 *= R2; +._P1L5: + R0= R0 + R1 (NS) || R2 = [P0++] || R1 = [I0++]; + +._P1L1: + RTS; + +.data; +_a: + .db 0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00; + .db 0x04,0x00,0x00,0x00; + +_b: + .db 0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00; + .db 0x04,0x00,0x00,0x00; diff --git a/tests/tcg/bfin/7641.s b/tests/tcg/bfin/7641.s new file mode 100644 index 0000000000000..864480ccba5ec --- /dev/null +++ b/tests/tcg/bfin/7641.s @@ -0,0 +1,38 @@ +# Blackfin testcase for playing with TESTSET +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, element1 + + loadsym P1, element2 + + R0 = B [P0]; // R0 should get 00 + R1 = B [P1]; // R1 should get 02 + + TESTSET(P0); // should set CC and MSB of memory byte + R0 = CC; + TESTSET(P1); // should clear CC and not change MSB of memory + R1 = CC; + + R2 = B [P0]; // R2 should get 80 + R3 = B [P1]; // R3 should get 02 + + dbga(R0.l,0x0001); + dbga(R0.h,0x0000); + dbga(R1.l,0x0000); + dbga(R1.h,0x0000); + dbga(R2.l,0x0080); + dbga(R2.h,0x0000); + dbga(R3.l,0x0082); + dbga(R3.h,0x0000); + + pass + +.data +.align 4; +element1: .long 0x0 +element2: .long 0x2 +element3: .long 0x4 diff --git a/tests/tcg/bfin/Makefile b/tests/tcg/bfin/Makefile new file mode 100644 index 0000000000000..7d3ba14fd8974 --- /dev/null +++ b/tests/tcg/bfin/Makefile @@ -0,0 +1,80 @@ +# Simple makefile for local tests + +QEMU_USER = ../../../bfin-linux-user/qemu-bfin +SRCS = $(wildcard *.[csS]) +SIM_SRCS = $(SRCS) +SIM = $(SIM_SRCS:=.x) +HOST_SRCS = $(shell grep -L -e sim:.*operating $(SRCS)) +HOST = $(HOST_SRCS:=.X) + +NORMAL =  +GREEN =  +RED =  +BLUE =  +PASS = $(GREEN)PASS$(NORMAL) +FAIL = $(RED)FAIL$(NORMAL) + +all: sim # host +check: all + +sim: $(SIM) + @fail=0 pass=0 ; \ + timeout=`which timeout 2>/dev/null` && timeout="$$timeout 10s" ; \ + if addr=`cat /proc/sys/vm/mmap_min_addr 2>/dev/null` ; then \ + if [ $$addr -ne 0 ] ; then \ + printf '\n$(RED)Please run: sudo sysctl vm.mmap_min_addr=0$(NORMAL)\n\n' ; \ + exit 1 ; \ + fi ; \ + fi ; \ + [ "$(PWD)" = "`pwd`" ] && pwd="" || pwd="`pwd`/" ; \ + rm -f $@.log ; \ + printf 'Logging to $(BLUE)%s$(NORMAL)\n' "$${pwd}$@.log" ; \ + for x in $^ ; do \ + xx="$$timeout $(QEMU_USER) $$x" ; \ + x=$${x%.x} ; \ + printf '%80s\n' | tr ' ' '#' >> $@.log ; \ + printf 'Running: %s\n' "$$xx" >> $@.log ; \ + if ! out="`$$xx 2>&1`" ; then \ + res=FAIL ; \ + cres='$(FAIL)' ; \ + : $$(( fail += 1 )) ; \ + elif [ "$$out" != "pass" ] ; then \ + res=FAIL ; \ + cres='$(FAIL)' ; \ + : $$(( fail += 1 )) ; \ + else \ + res=PASS ; \ + cres='$(PASS)' ; \ + : $$(( pass += 1 )) ; \ + fi ; \ + printf '%s\n%s: %s\n\n' "$$out" "$$res" $$x >> $@.log ; \ + echo "$$cres: $$x" ; \ + done ; \ + printf '$(BLUE)SUMMARY$(NORMAL): %i/%i tests passed (see %s for details)\n' \ + $$pass $$(( pass + fail )) "$${pwd}$@.log" ; \ + exit $$(( fail != 0 )) + +jtag: $(JTAG) +host: $(HOST) + +FLAGS = -g -o $@ $< + +DO_SIM = bfin-elf-gcc -msim $(FLAGS) -nostdlib +%.c.x: %.c ; $(DO_SIM) $(shell sed -n '/^\# cc:/s|.*cc:||p' $<) +%.s.x: %.s ; $(DO_SIM) +%.S.x: %.S ; $(DO_SIM) + +DO_JTAG = bfin-elf-gcc $(FLAGS) -nostdlib +%.c.j: %.c ; $(DO_JTAG) $(shell sed -n '/^\# cc:/s|.*cc:||p' $<) +%.s.j: %.s ; $(DO_JTAG) +%.S.j: %.S ; $(DO_JTAG) + +DO_HOST = bfin-linux-uclibc-gcc -Wa,--defsym,BFIN_HOST=1 $(FLAGS) -static +%.c.X: %.c ; $(DO_HOST) +%.s.X: %.s ; $(DO_HOST) +%.S.X: %.S ; $(DO_HOST) + +clean: + rm -f *.[xX] *.o + +.PHONY: all clean diff --git a/tests/tcg/bfin/a0.s b/tests/tcg/bfin/a0.s new file mode 100644 index 0000000000000..3bc78d62fa299 --- /dev/null +++ b/tests/tcg/bfin/a0.s @@ -0,0 +1,17 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R0 <<= 1; + DBGA ( R0.L , 2 ); + R0 <<= 1; + DBGA ( R0.L , 4 ); + R0 <<= 3; + DBGA ( R0.L , 32 ); + R0 += 5; + DBGA ( R0.L , 37 ); + R0 += -7; + DBGA ( R0.L , 30 ); + pass diff --git a/tests/tcg/bfin/a1.s b/tests/tcg/bfin/a1.s new file mode 100644 index 0000000000000..40f9d40b1ad8d --- /dev/null +++ b/tests/tcg/bfin/a1.s @@ -0,0 +1,29 @@ +// check the imm7 bit constants bounds +# mach: bfin + +.include "testutils.inc" + start + + R0 = 63; + DBGA ( R0.L , 63 ); + R0 = -64; + DBGA ( R0.L , 0xffc0 ); + P0 = 63; + R0 = P0; DBGA ( R0.L , 63 ); + P0 = -64; + R0 = P0; DBGA ( R0.L , 0xffc0 ); + +// check loading imm16 into h/l halves + R0.L = 0x1111; + DBGA ( R0.L , 0x1111 ); + + R0.H = 0x1111; + DBGA ( R0.H , 0x1111 ); + + P0.L = 0x2222; + R0 = P0; DBGA ( R0.L , 0x2222 ); + + P0.H = 0x2222; + R0 = P0; DBGA ( R0.H , 0x2222 ); + + pass diff --git a/tests/tcg/bfin/a10.s b/tests/tcg/bfin/a10.s new file mode 100644 index 0000000000000..7133a43ac5cde --- /dev/null +++ b/tests/tcg/bfin/a10.s @@ -0,0 +1,163 @@ +// ALU test program. +// Test dual 16 bit MAX, MIN, ABS instructions +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; +// MAX +// first operand is larger, so AN=0 + R0.L = 0x0001; + R0.H = 0x0002; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0002 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger + R0.L = 0x0000; + R0.H = 0x0000; + R1.L = 0x0001; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one operand larger, one smaller. + R0.L = 0x000a; + R0.H = 0x0000; + R1.L = 0x0001; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x000a ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x8001; + R0.H = 0xffff; + R1.L = 0x8000; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x8001 ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x8000; + R0.H = 0xffff; + R1.L = 0x8000; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// MIN +// second operand is smaller + R0.L = 0x0001; + R0.H = 0x0004; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is smaller + R0.L = 0xffff; + R0.H = 0x8001; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x8001 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one of each + R0.L = 0xffff; + R0.H = 0x0034; + R1.L = 0x0999; + R1.H = 0x0010; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0x0010; + R1.L = 0x0999; + R1.H = 0x0010; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// ABS + R0.L = 0x0001; + R0.H = 0x8001; + R7 = ABS R0 (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x7fff ); + _DBG ASTAT; + R6 = ASTAT; + _DBG R6; + + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = VS; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0xffff; + R7 = ABS R0 (V); + _DBG R7; + _DBG ASTAT; + R6 = ASTAT; + _DBG R6; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0001 ); + CC = AZ; R6 = CC; DBGA ( R6.L, 0x1 ); + + pass diff --git a/tests/tcg/bfin/a2.s b/tests/tcg/bfin/a2.s new file mode 100644 index 0000000000000..eb668dd3b8940 --- /dev/null +++ b/tests/tcg/bfin/a2.s @@ -0,0 +1,179 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym P0, middle; + + R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 ); + R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 ); + R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 ); + R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 ); + R0 = [ P0 + 16 ]; DBGA ( R0.L , 54 ); + R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 ); + R0 = [ P0 + 24 ]; DBGA ( R0.L , 56 ); + R0 = [ P0 + 28 ]; DBGA ( R0.L , 57 ); + + R0 = [ P0 + -4 ]; DBGA ( R0.L , 49 ); + R0 = [ P0 + -8 ]; DBGA ( R0.L , 48 ); + R0 = [ P0 + -12 ]; DBGA ( R0.L , 47 ); + R0 = [ P0 + -16 ]; DBGA ( R0.L , 46 ); + R0 = [ P0 + -20 ]; DBGA ( R0.L , 45 ); + R0 = [ P0 + -24 ]; DBGA ( R0.L , 44 ); + R0 = [ P0 + -28 ]; DBGA ( R0.L , 43 ); + R0 = [ P0 + -32 ]; DBGA ( R0.L , 42 ); + + FP = P0; + + R0 = [ FP + 0 ]; DBGA ( R0.L , 50 ); + R0 = [ FP + 4 ]; DBGA ( R0.L , 51 ); + R0 = [ FP + 8 ]; DBGA ( R0.L , 52 ); + R0 = [ FP + 12 ]; DBGA ( R0.L , 53 ); + R0 = [ FP + 16 ]; DBGA ( R0.L , 54 ); + R0 = [ FP + 20 ]; DBGA ( R0.L , 55 ); + R0 = [ FP + 24 ]; DBGA ( R0.L , 56 ); + R0 = [ FP + 28 ]; DBGA ( R0.L , 57 ); + R0 = [ FP + 32 ]; DBGA ( R0.L , 58 ); + R0 = [ FP + 36 ]; DBGA ( R0.L , 59 ); + R0 = [ FP + 40 ]; DBGA ( R0.L , 60 ); + R0 = [ FP + 44 ]; DBGA ( R0.L , 61 ); + R0 = [ FP + 48 ]; DBGA ( R0.L , 62 ); + R0 = [ FP + 52 ]; DBGA ( R0.L , 63 ); + R0 = [ FP + 56 ]; DBGA ( R0.L , 64 ); + R0 = [ FP + 60 ]; DBGA ( R0.L , 65 ); + + R0 = [ FP + -4 ]; DBGA ( R0.L , 49 ); + R0 = [ FP + -8 ]; DBGA ( R0.L , 48 ); + R0 = [ FP + -12 ]; DBGA ( R0.L , 47 ); + R0 = [ FP + -16 ]; DBGA ( R0.L , 46 ); + R0 = [ FP + -20 ]; DBGA ( R0.L , 45 ); + R0 = [ FP + -24 ]; DBGA ( R0.L , 44 ); + R0 = [ FP + -28 ]; DBGA ( R0.L , 43 ); + R0 = [ FP + -32 ]; DBGA ( R0.L , 42 ); + R0 = [ FP + -36 ]; DBGA ( R0.L , 41 ); + R0 = [ FP + -40 ]; DBGA ( R0.L , 40 ); + R0 = [ FP + -44 ]; DBGA ( R0.L , 39 ); + R0 = [ FP + -48 ]; DBGA ( R0.L , 38 ); + R0 = [ FP + -52 ]; DBGA ( R0.L , 37 ); + R0 = [ FP + -56 ]; DBGA ( R0.L , 36 ); + R0 = [ FP + -60 ]; DBGA ( R0.L , 35 ); + R0 = [ FP + -64 ]; DBGA ( R0.L , 34 ); + R0 = [ FP + -68 ]; DBGA ( R0.L , 33 ); + R0 = [ FP + -72 ]; DBGA ( R0.L , 32 ); + R0 = [ FP + -76 ]; DBGA ( R0.L , 31 ); + R0 = [ FP + -80 ]; DBGA ( R0.L , 30 ); + R0 = [ FP + -84 ]; DBGA ( R0.L , 29 ); + R0 = [ FP + -88 ]; DBGA ( R0.L , 28 ); + R0 = [ FP + -92 ]; DBGA ( R0.L , 27 ); + R0 = [ FP + -96 ]; DBGA ( R0.L , 26 ); + R0 = [ FP + -100 ]; DBGA ( R0.L , 25 ); + R0 = [ FP + -104 ]; DBGA ( R0.L , 24 ); + R0 = [ FP + -108 ]; DBGA ( R0.L , 23 ); + R0 = [ FP + -112 ]; DBGA ( R0.L , 22 ); + R0 = [ FP + -116 ]; DBGA ( R0.L , 21 ); + + pass + + .data +base: + .dd 0 + .dd 1 + .dd 2 + .dd 3 + .dd 4 + .dd 5 + .dd 6 + .dd 7 + .dd 8 + .dd 9 + .dd 10 + .dd 11 + .dd 12 + .dd 13 + .dd 14 + .dd 15 + .dd 16 + .dd 17 + .dd 18 + .dd 19 + .dd 20 + .dd 21 + .dd 22 + .dd 23 + .dd 24 + .dd 25 + .dd 26 + .dd 27 + .dd 28 + .dd 29 + .dd 30 + .dd 31 + .dd 32 + .dd 33 + .dd 34 + .dd 35 + .dd 36 + .dd 37 + .dd 38 + .dd 39 + .dd 40 + .dd 41 + .dd 42 + .dd 43 + .dd 44 + .dd 45 + .dd 46 + .dd 47 + .dd 48 + .dd 49 +middle: + .dd 50 + .dd 51 + .dd 52 + .dd 53 + .dd 54 + .dd 55 + .dd 56 + .dd 57 + .dd 58 + .dd 59 + .dd 60 + .dd 61 + .dd 62 + .dd 63 + .dd 64 + .dd 65 + .dd 66 + .dd 67 + .dd 68 + .dd 69 + .dd 70 + .dd 71 + .dd 72 + .dd 73 + .dd 74 + .dd 75 + .dd 76 + .dd 77 + .dd 78 + .dd 79 + .dd 80 + .dd 81 + .dd 82 + .dd 83 + .dd 84 + .dd 85 + .dd 86 + .dd 87 + .dd 88 + .dd 89 + .dd 90 + .dd 91 + .dd 92 + .dd 93 + .dd 94 + .dd 95 + .dd 96 + .dd 97 + .dd 98 + .dd 99 diff --git a/tests/tcg/bfin/a24.s b/tests/tcg/bfin/a24.s new file mode 100644 index 0000000000000..507350f3cf846 --- /dev/null +++ b/tests/tcg/bfin/a24.s @@ -0,0 +1,12 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0x1111 (X); + R0.H = 0x1111; + A0.x = R0; + R1 = A0.x; + DBGA ( R1.L , 0x11 ); + DBGA ( R1.H , 0x0 ); + pass diff --git a/tests/tcg/bfin/a25.s b/tests/tcg/bfin/a25.s new file mode 100644 index 0000000000000..b5d5d7bb2cd5d --- /dev/null +++ b/tests/tcg/bfin/a25.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + + A1 = A0 = 0; + R0.L = 0x01; + A0.x = R0; +//A0 = 0x0100000000 +//A1 = 0x0000000000 + + R4.L = 0x2d1a; + R4.H = 0x32e0; + + A1.x = R4; +//A1 = 0x1a00000000 + + A0.w = A1.x; + + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x001a ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0001 ); + + pass diff --git a/tests/tcg/bfin/a26.s b/tests/tcg/bfin/a26.s new file mode 100644 index 0000000000000..2e9a0b5737588 --- /dev/null +++ b/tests/tcg/bfin/a26.s @@ -0,0 +1,72 @@ +// Test ALU SEARCH instruction +# mach: bfin + +.include "testutils.inc" + start + + + init_r_regs 0; + ASTAT = R0; + + R0 = 4; + R1 = 5; + A1 = A0 = 0; + + R2.L = 0x0001; + R2.H = 0xffff; + + loadsym P0, foo; + + ( R1 , R0 ) = SEARCH R2 (GT); + + // R0 should be the pointer + R7 = P0; + CC = R0 == R7; + if !CC JUMP _fail; + + _DBG R1; // does not change + DBGA ( R1.H , 0 ); DBGA ( R1.L , 0x5 ); + + _DBG A0; // changes + R0 = A0.w; + DBGA ( R0.H , 0 ); DBGA ( R0.L , 0x1 ); + + _DBG A1; // does not change + R0 = A1.w; + DBGA ( R0.H , 0 ); DBGA ( R0.L , 0 ); + + R0 = 4; + R1 = 5; + A1 = A0 = 0; + + R2.L = 0x0000; + R2.H = 0xffff; + + loadsym p0, foo; + + ( R1 , R0 ) = SEARCH R2 (LT); + + _DBG R0; // no change + DBGA ( R0.H , 0 ); DBGA ( R0.L , 4 ); + + _DBG R1; // change + R7 = P0; + CC = R1 == R7; + if !CC JUMP _fail; + + _DBG A0; + R0 = A0.w; + DBGA ( R0.H , 0 ); DBGA ( R0.L , 0 ); + + _DBG A1; + R0 = A1.w; + DBGA ( R0.H , 0xffff ); DBGA ( R0.L , 0xffff ); + + pass + +_fail: + fail; + + .data +foo: + .space (0x100) diff --git a/tests/tcg/bfin/a3.s b/tests/tcg/bfin/a3.s new file mode 100644 index 0000000000000..c53300b1dbb68 --- /dev/null +++ b/tests/tcg/bfin/a3.s @@ -0,0 +1,313 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym P1, middle; + + R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 ); + R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 ); + R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 ); + R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 ); + R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 ); + R0 = W [ P1 + -12 ] (Z); DBGA ( R0.L , 44 ); + R0 = W [ P1 + -14 ] (Z); DBGA ( R0.L , 43 ); + R0 = W [ P1 + -16 ] (Z); DBGA ( R0.L , 42 ); + R0 = W [ P1 + -18 ] (Z); DBGA ( R0.L , 41 ); + R0 = W [ P1 + -20 ] (Z); DBGA ( R0.L , 40 ); + R0 = W [ P1 + -22 ] (Z); DBGA ( R0.L , 39 ); + R0 = W [ P1 + -24 ] (Z); DBGA ( R0.L , 38 ); + R0 = W [ P1 + -26 ] (Z); DBGA ( R0.L , 37 ); + R0 = W [ P1 + -28 ] (Z); DBGA ( R0.L , 36 ); + R0 = W [ P1 + -30 ] (Z); DBGA ( R0.L , 35 ); + R0 = W [ P1 + -32 ] (Z); DBGA ( R0.L , 34 ); + R0 = W [ P1 + -34 ] (Z); DBGA ( R0.L , 33 ); + R0 = W [ P1 + -36 ] (Z); DBGA ( R0.L , 32 ); + R0 = W [ P1 + -38 ] (Z); DBGA ( R0.L , 31 ); + R0 = W [ P1 + -40 ] (Z); DBGA ( R0.L , 30 ); + R0 = W [ P1 + -42 ] (Z); DBGA ( R0.L , 29 ); + R0 = W [ P1 + -44 ] (Z); DBGA ( R0.L , 28 ); + R0 = W [ P1 + -46 ] (Z); DBGA ( R0.L , 27 ); + R0 = W [ P1 + -48 ] (Z); DBGA ( R0.L , 26 ); + R0 = W [ P1 + -50 ] (Z); DBGA ( R0.L , 25 ); + R0 = W [ P1 + -52 ] (Z); DBGA ( R0.L , 24 ); + R0 = W [ P1 + -54 ] (Z); DBGA ( R0.L , 23 ); + R0 = W [ P1 + -56 ] (Z); DBGA ( R0.L , 22 ); + R0 = W [ P1 + -58 ] (Z); DBGA ( R0.L , 21 ); + R0 = W [ P1 + -60 ] (Z); DBGA ( R0.L , 20 ); + R0 = W [ P1 + -62 ] (Z); DBGA ( R0.L , 19 ); + R0 = W [ P1 + -64 ] (Z); DBGA ( R0.L , 18 ); + R0 = W [ P1 + -66 ] (Z); DBGA ( R0.L , 17 ); + R0 = W [ P1 + -68 ] (Z); DBGA ( R0.L , 16 ); + R0 = W [ P1 + -70 ] (Z); DBGA ( R0.L , 15 ); + R0 = W [ P1 + -72 ] (Z); DBGA ( R0.L , 14 ); + R0 = W [ P1 + -74 ] (Z); DBGA ( R0.L , 13 ); + R0 = W [ P1 + -76 ] (Z); DBGA ( R0.L , 12 ); + R0 = W [ P1 + -78 ] (Z); DBGA ( R0.L , 11 ); + R0 = W [ P1 + -80 ] (Z); DBGA ( R0.L , 10 ); + R0 = W [ P1 + -82 ] (Z); DBGA ( R0.L , 9 ); + R0 = W [ P1 + -84 ] (Z); DBGA ( R0.L , 8 ); + R0 = W [ P1 + -86 ] (Z); DBGA ( R0.L , 7 ); + R0 = W [ P1 + -88 ] (Z); DBGA ( R0.L , 6 ); + R0 = W [ P1 + -90 ] (Z); DBGA ( R0.L , 5 ); + R0 = W [ P1 + -92 ] (Z); DBGA ( R0.L , 4 ); + R0 = W [ P1 + -94 ] (Z); DBGA ( R0.L , 3 ); + R0 = W [ P1 + -96 ] (Z); DBGA ( R0.L , 2 ); + R0 = W [ P1 + -98 ] (Z); DBGA ( R0.L , 1 ); + R0 = W [ P1 + 0 ] (Z); DBGA ( R0.L , 50 ); + R0 = W [ P1 + 2 ] (Z); DBGA ( R0.L , 51 ); + R0 = W [ P1 + 4 ] (Z); DBGA ( R0.L , 52 ); + R0 = W [ P1 + 6 ] (Z); DBGA ( R0.L , 53 ); + R0 = W [ P1 + 8 ] (Z); DBGA ( R0.L , 54 ); + R0 = W [ P1 + 10 ] (Z); DBGA ( R0.L , 55 ); + R0 = W [ P1 + 12 ] (Z); DBGA ( R0.L , 56 ); + R0 = W [ P1 + 14 ] (Z); DBGA ( R0.L , 57 ); + R0 = W [ P1 + 16 ] (Z); DBGA ( R0.L , 58 ); + R0 = W [ P1 + 18 ] (Z); DBGA ( R0.L , 59 ); + R0 = W [ P1 + 20 ] (Z); DBGA ( R0.L , 60 ); + R0 = W [ P1 + 22 ] (Z); DBGA ( R0.L , 61 ); + R0 = W [ P1 + 24 ] (Z); DBGA ( R0.L , 62 ); + R0 = W [ P1 + 26 ] (Z); DBGA ( R0.L , 63 ); + R0 = W [ P1 + 28 ] (Z); DBGA ( R0.L , 64 ); + R0 = W [ P1 + 30 ] (Z); DBGA ( R0.L , 65 ); + R0 = W [ P1 + 32 ] (Z); DBGA ( R0.L , 66 ); + R0 = W [ P1 + 34 ] (Z); DBGA ( R0.L , 67 ); + R0 = W [ P1 + 36 ] (Z); DBGA ( R0.L , 68 ); + R0 = W [ P1 + 38 ] (Z); DBGA ( R0.L , 69 ); + R0 = W [ P1 + 40 ] (Z); DBGA ( R0.L , 70 ); + R0 = W [ P1 + 42 ] (Z); DBGA ( R0.L , 71 ); + R0 = W [ P1 + 44 ] (Z); DBGA ( R0.L , 72 ); + R0 = W [ P1 + 46 ] (Z); DBGA ( R0.L , 73 ); + R0 = W [ P1 + 48 ] (Z); DBGA ( R0.L , 74 ); + R0 = W [ P1 + 50 ] (Z); DBGA ( R0.L , 75 ); + R0 = W [ P1 + 52 ] (Z); DBGA ( R0.L , 76 ); + R0 = W [ P1 + 54 ] (Z); DBGA ( R0.L , 77 ); + R0 = W [ P1 + 56 ] (Z); DBGA ( R0.L , 78 ); + R0 = W [ P1 + 58 ] (Z); DBGA ( R0.L , 79 ); + R0 = W [ P1 + 60 ] (Z); DBGA ( R0.L , 80 ); + R0 = W [ P1 + 62 ] (Z); DBGA ( R0.L , 81 ); + R0 = W [ P1 + 64 ] (Z); DBGA ( R0.L , 82 ); + R0 = W [ P1 + 66 ] (Z); DBGA ( R0.L , 83 ); + R0 = W [ P1 + 68 ] (Z); DBGA ( R0.L , 84 ); + R0 = W [ P1 + 70 ] (Z); DBGA ( R0.L , 85 ); + R0 = W [ P1 + 72 ] (Z); DBGA ( R0.L , 86 ); + R0 = W [ P1 + 74 ] (Z); DBGA ( R0.L , 87 ); + R0 = W [ P1 + 76 ] (Z); DBGA ( R0.L , 88 ); + R0 = W [ P1 + 78 ] (Z); DBGA ( R0.L , 89 ); + R0 = W [ P1 + 80 ] (Z); DBGA ( R0.L , 90 ); + R0 = W [ P1 + 82 ] (Z); DBGA ( R0.L , 91 ); + R0 = W [ P1 + 84 ] (Z); DBGA ( R0.L , 92 ); + R0 = W [ P1 + 86 ] (Z); DBGA ( R0.L , 93 ); + R0 = W [ P1 + 88 ] (Z); DBGA ( R0.L , 94 ); + R0 = W [ P1 + 90 ] (Z); DBGA ( R0.L , 95 ); + R0 = W [ P1 + 92 ] (Z); DBGA ( R0.L , 96 ); + R0 = W [ P1 + 94 ] (Z); DBGA ( R0.L , 97 ); + R0 = W [ P1 + 96 ] (Z); DBGA ( R0.L , 98 ); + R0 = W [ P1 + 98 ] (Z); DBGA ( R0.L , 99 ); + + FP = P1; + + R0 = W [ FP + -2 ] (Z); DBGA ( R0.L , 49 ); + R0 = W [ FP + -4 ] (Z); DBGA ( R0.L , 48 ); + R0 = W [ FP + -6 ] (Z); DBGA ( R0.L , 47 ); + R0 = W [ FP + -8 ] (Z); DBGA ( R0.L , 46 ); + R0 = W [ FP + -10 ] (Z); DBGA ( R0.L , 45 ); + R0 = W [ FP + -12 ] (Z); DBGA ( R0.L , 44 ); + R0 = W [ FP + -14 ] (Z); DBGA ( R0.L , 43 ); + R0 = W [ FP + -16 ] (Z); DBGA ( R0.L , 42 ); + R0 = W [ FP + -18 ] (Z); DBGA ( R0.L , 41 ); + R0 = W [ FP + -20 ] (Z); DBGA ( R0.L , 40 ); + R0 = W [ FP + -22 ] (Z); DBGA ( R0.L , 39 ); + R0 = W [ FP + -24 ] (Z); DBGA ( R0.L , 38 ); + R0 = W [ FP + -26 ] (Z); DBGA ( R0.L , 37 ); + R0 = W [ FP + -28 ] (Z); DBGA ( R0.L , 36 ); + R0 = W [ FP + -30 ] (Z); DBGA ( R0.L , 35 ); + R0 = W [ FP + -32 ] (Z); DBGA ( R0.L , 34 ); + R0 = W [ FP + -34 ] (Z); DBGA ( R0.L , 33 ); + R0 = W [ FP + -36 ] (Z); DBGA ( R0.L , 32 ); + R0 = W [ FP + -38 ] (Z); DBGA ( R0.L , 31 ); + R0 = W [ FP + -40 ] (Z); DBGA ( R0.L , 30 ); + R0 = W [ FP + -42 ] (Z); DBGA ( R0.L , 29 ); + R0 = W [ FP + -44 ] (Z); DBGA ( R0.L , 28 ); + R0 = W [ FP + -46 ] (Z); DBGA ( R0.L , 27 ); + R0 = W [ FP + -48 ] (Z); DBGA ( R0.L , 26 ); + R0 = W [ FP + -50 ] (Z); DBGA ( R0.L , 25 ); + R0 = W [ FP + -52 ] (Z); DBGA ( R0.L , 24 ); + R0 = W [ FP + -54 ] (Z); DBGA ( R0.L , 23 ); + R0 = W [ FP + -56 ] (Z); DBGA ( R0.L , 22 ); + R0 = W [ FP + -58 ] (Z); DBGA ( R0.L , 21 ); + R0 = W [ FP + -60 ] (Z); DBGA ( R0.L , 20 ); + R0 = W [ FP + -62 ] (Z); DBGA ( R0.L , 19 ); + R0 = W [ FP + -64 ] (Z); DBGA ( R0.L , 18 ); + R0 = W [ FP + -66 ] (Z); DBGA ( R0.L , 17 ); + R0 = W [ FP + -68 ] (Z); DBGA ( R0.L , 16 ); + R0 = W [ FP + -70 ] (Z); DBGA ( R0.L , 15 ); + R0 = W [ FP + -72 ] (Z); DBGA ( R0.L , 14 ); + R0 = W [ FP + -74 ] (Z); DBGA ( R0.L , 13 ); + R0 = W [ FP + -76 ] (Z); DBGA ( R0.L , 12 ); + R0 = W [ FP + -78 ] (Z); DBGA ( R0.L , 11 ); + R0 = W [ FP + -80 ] (Z); DBGA ( R0.L , 10 ); + R0 = W [ FP + -82 ] (Z); DBGA ( R0.L , 9 ); + R0 = W [ FP + -84 ] (Z); DBGA ( R0.L , 8 ); + R0 = W [ FP + -86 ] (Z); DBGA ( R0.L , 7 ); + R0 = W [ FP + -88 ] (Z); DBGA ( R0.L , 6 ); + R0 = W [ FP + -90 ] (Z); DBGA ( R0.L , 5 ); + R0 = W [ FP + -92 ] (Z); DBGA ( R0.L , 4 ); + R0 = W [ FP + -94 ] (Z); DBGA ( R0.L , 3 ); + R0 = W [ FP + -96 ] (Z); DBGA ( R0.L , 2 ); + R0 = W [ FP + -98 ] (Z); DBGA ( R0.L , 1 ); + R0 = W [ FP + 0 ] (Z); DBGA ( R0.L , 50 ); + R0 = W [ FP + 2 ] (Z); DBGA ( R0.L , 51 ); + R0 = W [ FP + 4 ] (Z); DBGA ( R0.L , 52 ); + R0 = W [ FP + 6 ] (Z); DBGA ( R0.L , 53 ); + R0 = W [ FP + 8 ] (Z); DBGA ( R0.L , 54 ); + R0 = W [ FP + 10 ] (Z); DBGA ( R0.L , 55 ); + R0 = W [ FP + 12 ] (Z); DBGA ( R0.L , 56 ); + R0 = W [ FP + 14 ] (Z); DBGA ( R0.L , 57 ); + R0 = W [ FP + 16 ] (Z); DBGA ( R0.L , 58 ); + R0 = W [ FP + 18 ] (Z); DBGA ( R0.L , 59 ); + R0 = W [ FP + 20 ] (Z); DBGA ( R0.L , 60 ); + R0 = W [ FP + 22 ] (Z); DBGA ( R0.L , 61 ); + R0 = W [ FP + 24 ] (Z); DBGA ( R0.L , 62 ); + R0 = W [ FP + 26 ] (Z); DBGA ( R0.L , 63 ); + R0 = W [ FP + 28 ] (Z); DBGA ( R0.L , 64 ); + R0 = W [ FP + 30 ] (Z); DBGA ( R0.L , 65 ); + R0 = W [ FP + 32 ] (Z); DBGA ( R0.L , 66 ); + R0 = W [ FP + 34 ] (Z); DBGA ( R0.L , 67 ); + R0 = W [ FP + 36 ] (Z); DBGA ( R0.L , 68 ); + R0 = W [ FP + 38 ] (Z); DBGA ( R0.L , 69 ); + R0 = W [ FP + 40 ] (Z); DBGA ( R0.L , 70 ); + R0 = W [ FP + 42 ] (Z); DBGA ( R0.L , 71 ); + R0 = W [ FP + 44 ] (Z); DBGA ( R0.L , 72 ); + R0 = W [ FP + 46 ] (Z); DBGA ( R0.L , 73 ); + R0 = W [ FP + 48 ] (Z); DBGA ( R0.L , 74 ); + R0 = W [ FP + 50 ] (Z); DBGA ( R0.L , 75 ); + R0 = W [ FP + 52 ] (Z); DBGA ( R0.L , 76 ); + R0 = W [ FP + 54 ] (Z); DBGA ( R0.L , 77 ); + R0 = W [ FP + 56 ] (Z); DBGA ( R0.L , 78 ); + R0 = W [ FP + 58 ] (Z); DBGA ( R0.L , 79 ); + R0 = W [ FP + 60 ] (Z); DBGA ( R0.L , 80 ); + R0 = W [ FP + 62 ] (Z); DBGA ( R0.L , 81 ); + R0 = W [ FP + 64 ] (Z); DBGA ( R0.L , 82 ); + R0 = W [ FP + 66 ] (Z); DBGA ( R0.L , 83 ); + R0 = W [ FP + 68 ] (Z); DBGA ( R0.L , 84 ); + R0 = W [ FP + 70 ] (Z); DBGA ( R0.L , 85 ); + R0 = W [ FP + 72 ] (Z); DBGA ( R0.L , 86 ); + R0 = W [ FP + 74 ] (Z); DBGA ( R0.L , 87 ); + R0 = W [ FP + 76 ] (Z); DBGA ( R0.L , 88 ); + R0 = W [ FP + 78 ] (Z); DBGA ( R0.L , 89 ); + R0 = W [ FP + 80 ] (Z); DBGA ( R0.L , 90 ); + R0 = W [ FP + 82 ] (Z); DBGA ( R0.L , 91 ); + R0 = W [ FP + 84 ] (Z); DBGA ( R0.L , 92 ); + R0 = W [ FP + 86 ] (Z); DBGA ( R0.L , 93 ); + R0 = W [ FP + 88 ] (Z); DBGA ( R0.L , 94 ); + R0 = W [ FP + 90 ] (Z); DBGA ( R0.L , 95 ); + R0 = W [ FP + 92 ] (Z); DBGA ( R0.L , 96 ); + R0 = W [ FP + 94 ] (Z); DBGA ( R0.L , 97 ); + R0 = W [ FP + 96 ] (Z); DBGA ( R0.L , 98 ); + R0 = W [ FP + 98 ] (Z); DBGA ( R0.L , 99 ); + pass + + .data + + .dw 0 + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 10 + .dw 11 + .dw 12 + .dw 13 + .dw 14 + .dw 15 + .dw 16 + .dw 17 + .dw 18 + .dw 19 + .dw 20 + .dw 21 + .dw 22 + .dw 23 + .dw 24 + .dw 25 + .dw 26 + .dw 27 + .dw 28 + .dw 29 + .dw 30 + .dw 31 + .dw 32 + .dw 33 + .dw 34 + .dw 35 + .dw 36 + .dw 37 + .dw 38 + .dw 39 + .dw 40 + .dw 41 + .dw 42 + .dw 43 + .dw 44 + .dw 45 + .dw 46 + .dw 47 + .dw 48 + .dw 49 +middle: + .dw 50 + .dw 51 + .dw 52 + .dw 53 + .dw 54 + .dw 55 + .dw 56 + .dw 57 + .dw 58 + .dw 59 + .dw 60 + .dw 61 + .dw 62 + .dw 63 + .dw 64 + .dw 65 + .dw 66 + .dw 67 + .dw 68 + .dw 69 + .dw 70 + .dw 71 + .dw 72 + .dw 73 + .dw 74 + .dw 75 + .dw 76 + .dw 77 + .dw 78 + .dw 79 + .dw 80 + .dw 81 + .dw 82 + .dw 83 + .dw 84 + .dw 85 + .dw 86 + .dw 87 + .dw 88 + .dw 89 + .dw 90 + .dw 91 + .dw 92 + .dw 93 + .dw 94 + .dw 95 + .dw 96 + .dw 97 + .dw 98 + .dw 99 diff --git a/tests/tcg/bfin/a4.s b/tests/tcg/bfin/a4.s new file mode 100644 index 0000000000000..d0f5ef5f8e51d --- /dev/null +++ b/tests/tcg/bfin/a4.s @@ -0,0 +1,36 @@ +# Blackfin testcase for signbits +# mach: bfin + + .include "testutils.inc" + + start + +xx: + R0 = 1; + CALL red; + JUMP.L aa; + + .align 16 +aa: + R0 = 2; + CALL red; + JUMP.S bb; + + .align 16 +bb: + R0 = 3; + CALL red; + JUMP.S ccd; + + .align 16 +red: + RTS; + + .align 16 +ccd: + R1 = 3 (Z); + CC = R0 == R1 + if CC jump 1f; + fail +1: + pass diff --git a/tests/tcg/bfin/a7.s b/tests/tcg/bfin/a7.s new file mode 100644 index 0000000000000..4fbc5f6d4daaa --- /dev/null +++ b/tests/tcg/bfin/a7.s @@ -0,0 +1,179 @@ +# mach: bfin + +.include "testutils.inc" + start + + R1 = 0; + R0 = 0; + R0 = R1 ^ R0; + +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 1 ); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R0 = R1 | R0; +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 1 ); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R0 = 0; + R1 = 1; + CC = R0 == R1; + +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 2 ); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + CC = BITTST ( R1 , 1 ); + +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 2 ); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + CC = ! BITTST( R1 , 1 ); +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 0x22 ); + r7 = cc; + dbga( r7.l, 1); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R0.L = 0; + R0.H = 0x8000; + R0 >>>= 1; + _DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 0x22 ); + cc = az; + r6 = cc; + dbga( r6.l, 0); + cc = an; + r6 = cc; + dbga( r6.l, 1); + cc = av0; + r6 = cc; + dbga( r6.l, 0); + cc = av0s; + r6 = cc; + dbga( r6.l, 0); + cc = av1; + r6 = cc; + dbga( r6.l, 0); + cc = av1s; + r6 = cc; + dbga( r6.l, 0); + + R0.L = 17767; R0.H = 291; + R1.L = 52719; R1.H = -30293; + R2.L = 39612; R2.H = 22136; + R3.L = 4660; R3.H = -8464; + R4.L = 26777; R4.H = 9029; + R5.L = 9029; R5.H = 30865; + R6.L = 21554; R6.H = -26506; + R7.L = 22136; R7.H = 4660; + R0 = R0 + R0; + R1 = R0 - R1; + R2 = R0 & R2; + R3 = R0 | R3; + R4 = R0 & R4; + R5 = R0 & R5; + R6 = R0 | R6; + R7 = R0 & R7; + DBGA ( R0.l , 35534 ); DBGA( R0.h , 582 ); + DBGA( R1.l , 48351 ); DBGA ( R1.h , 30874 ); + DBGA ( R2.l , 35468 ); DBGA ( R2.h , 576 ); + DBGA ( R3.l , 39678 ); DBGA ( R3.h , 0xdef6); + DBGA ( R4.l , 2184 ); DBGA ( R4.h , 580 ); + DBGA ( R5.l , 580 ); DBGA( R5.h , 0 ); + DBGA ( R6.l, 57086 ); DBGA ( R6.h , 0x9a76 ); + DBGA ( R7.l , 584 ); DBGA ( R7.h , 516 ); + pass diff --git a/tests/tcg/bfin/a8.s b/tests/tcg/bfin/a8.s new file mode 100644 index 0000000000000..23f3464507072 --- /dev/null +++ b/tests/tcg/bfin/a8.s @@ -0,0 +1,41 @@ +# mach: bfin + +.include "testutils.inc" + start + +// xh, h, xb, b + R0.L = 32898; R0.H = 1; + R1.L = 49346; R1.H = 3; + R2.L = 6; R2.H = -1; + R3.L = 129; R3.H = 7; + R4.L = 4; R4.H = 0; + R5.L = 5; R5.H = 0; + R6.L = 6; R6.H = 0; + R7.L = 7; R7.H = 0; + R4 = R0.L (X); + +// _DBG ASTAT; R7 = ASTAT;DBGA ( R7.L , 2 ); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R5 = R0.L; + R6 = R1.B (X); + R7 = R1.B; + DBGA ( R4.l , 32898 ); DBGA ( R4.h , 0xffff); + pass diff --git a/tests/tcg/bfin/a9.s b/tests/tcg/bfin/a9.s new file mode 100644 index 0000000000000..5c851f1debd50 --- /dev/null +++ b/tests/tcg/bfin/a9.s @@ -0,0 +1,205 @@ +// ALU test program. +// Test 32 bit MAX, MIN, ABS instructions +# mach: bfin + +.include "testutils.inc" + start + + +// MAX +// first operand is larger, so AN=0 + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger, so AN=1 + R0.L = 0x0000; + R0.H = 0x0000; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is larger, check correct output with overflow + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0xffff; + R1.H = 0xffff; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger, no overflow here + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0xffff; + R1.H = 0x7fff; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger, overflow + R0.L = 0xffff; + R0.H = 0x800f; + R1.L = 0xffff; + R1.H = 0x7fff; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0S; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1S; R7 = CC; DBGA ( R7.L , 0x0 ); + +// both operands equal + R0.L = 0x0080; + R0.H = 0x8000; + R1.L = 0x0080; + R1.H = 0x8000; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0x0080 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// MIN +// second operand is smaller + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is smaller + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is smaller, overflow + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0000; + R1.H = 0x0ff0; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// equal operands + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0001; + R1.H = 0x8000; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// ABS + R0.L = 0x0001; + R0.H = 0x8000; + R7 = ABS R0; + _DBG R7; + _DBG ASTAT; + R6 = ASTAT; + + _DBG R6; + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); +//CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); +//CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); +//CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); +//CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); +//CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); +//CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0001; + R0.H = 0x0000; + R7 = ABS R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R7 = ABS R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0x0000; + R7 = ABS R0; + _DBG R7; + _DBG ASTAT; + R6 = ASTAT; + _DBG R6; + + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + + pass diff --git a/tests/tcg/bfin/abs-2.S b/tests/tcg/bfin/abs-2.S new file mode 100644 index 0000000000000..1e768b0a2f22b --- /dev/null +++ b/tests/tcg/bfin/abs-2.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8765; + R0.L = 0x4321; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x789a; + R2.L = 0xbcdf; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN|_V|_V_COPY); + R3.L = LO(_AZ|_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: */ + R3.H = HI(0); + R3.L = LO(0); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/tests/tcg/bfin/abs-3.S b/tests/tcg/bfin/abs-3.S new file mode 100644 index 0000000000000..44ba7656cadfe --- /dev/null +++ b/tests/tcg/bfin/abs-3.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x0; + R0.L = 0x0; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x0; + R2.L = 0x0; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN V V_COPY */ + R3.H = HI(_AN|_V|_V_COPY); + R3.L = LO(_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ */ + R3.H = HI(_AZ); + R3.L = LO(_AZ); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/tests/tcg/bfin/abs.S b/tests/tcg/bfin/abs.S new file mode 100644 index 0000000000000..1425d4281beaa --- /dev/null +++ b/tests/tcg/bfin/abs.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0x5678; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x1234; + R2.L = 0x5678; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN|_V|_V_COPY); + R3.L = LO(_AZ|_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: */ + R3.H = HI(0); + R3.L = LO(0); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/tests/tcg/bfin/acc-rot.s b/tests/tcg/bfin/acc-rot.s new file mode 100644 index 0000000000000..ccf307c0da687 --- /dev/null +++ b/tests/tcg/bfin/acc-rot.s @@ -0,0 +1,129 @@ +# Blackfin testcase for Accumulator Rotates (ROT) +# mach: bfin + + .include "testutils.inc" + + .macro atest_setup acc:req, val_x:req, val_w:req, cc:req, shift:req + imm32 R0, \val_w + imm32 R1, \val_x + R2 = \cc; + R3 = \shift + \acc\().W = R0; + \acc\().X = R1; + CC = R2; + .endm + + .macro atest_check acc:req, exp_x:req, exp_w:req, expcc:req + R7 = CC; + CHECKREG R7, \expcc; + + R2 = \acc\().W; + CHECKREG R2, \exp_w; + + R6 = \acc\().X; + R6 = R6.B (z); + CHECKREG R6, \exp_x; + .endm + + .macro _atest acc:req, val_x:req, val_w:req, cc:req, shift:req, exp_x:req, exp_w:req, expcc:req + atest_setup \acc, \val_x, \val_w, \cc, \shift + _DBG \acc; + \acc = ROT \acc BY \shift; + atest_check \acc, \exp_x, \exp_w, \expcc + + atest_setup \acc, \val_x, \val_w, \cc, \shift + \acc = ROT \acc BY R3.L; + atest_check \acc, \exp_x, \exp_w, \expcc + .endm + + .macro atest val_x:req, val_w:req, cc:req, shift:req, exp_x:req, exp_w:req, expcc:req + _atest A0, \val_x, \val_w, \cc, \shift, \exp_x, \exp_w, \expcc + _atest A1, \val_x, \val_w, \cc, \shift, \exp_x, \exp_w, \expcc + .endm + + start + + atest 0x00, 0x00000000, 0, 0, 0x00, 0x00000000, 0 + atest 0xa5, 0xa5a5a5a5, 0, 0, 0xa5, 0xa5a5a5a5, 0 + atest 0x00, 0x00000000, 1, 0, 0x00, 0x00000000, 1 + atest 0xa5, 0xa5a5a5a5, 1, 0, 0xa5, 0xa5a5a5a5, 1 + atest 0x00, 0x00000000, 0, 10, 0x00, 0x00000000, 0 + + atest 0x00, 0x0000000f, 0, 4, 0x00, 0x000000f0, 0 + atest 0x00, 0x0000000f, 1, 4, 0x00, 0x000000f8, 0 + atest 0x00, 0x0000000f, 0, 20, 0x00, 0x00f00000, 0 + atest 0x00, 0x0000000f, 1, 20, 0x00, 0x00f80000, 0 + atest 0x00, 0x0000000f, 0, -5, 0xf0, 0x00000000, 0 + atest 0x00, 0x0000000f, 1, -5, 0xf8, 0x00000000, 0 + atest 0x00, 0x0000000f, 0, -1, 0x00, 0x00000007, 1 + atest 0x00, 0x0000000f, 1, -1, 0x80, 0x00000007, 1 + + atest 0xff, 0xffffffff, 1, 10, 0xff, 0xffffffff, 1 + atest 0x11, 0x11111110, 0, -5, 0x00, 0x88888888, 1 + + atest 0x1f, 0x2e3d4c5b, 1, 0, 0x1f, 0x2e3d4c5b, 1 + atest 0x1f, 0x2e3d4c5b, 1, 1, 0x3e, 0x5c7a98b7, 0 + atest 0x1f, 0x2e3d4c5b, 1, 2, 0x7c, 0xb8f5316e, 0 + atest 0x1f, 0x2e3d4c5b, 1, 3, 0xf9, 0x71ea62dc, 0 + atest 0x1f, 0x2e3d4c5b, 1, 4, 0xf2, 0xe3d4c5b8, 1 + atest 0x1f, 0x2e3d4c5b, 1, 5, 0xe5, 0xc7a98b71, 1 + atest 0x1f, 0x2e3d4c5b, 1, 6, 0xcb, 0x8f5316e3, 1 + atest 0x1f, 0x2e3d4c5b, 1, 7, 0x97, 0x1ea62dc7, 1 + atest 0x1f, 0x2e3d4c5b, 1, 8, 0x2e, 0x3d4c5b8f, 1 + atest 0x1f, 0x2e3d4c5b, 1, 9, 0x5c, 0x7a98b71f, 0 + atest 0x1f, 0x2e3d4c5b, 1, 10, 0xb8, 0xf5316e3e, 0 + atest 0x1f, 0x2e3d4c5b, 1, 11, 0x71, 0xea62dc7c, 1 + atest 0x1f, 0x2e3d4c5b, 1, 12, 0xe3, 0xd4c5b8f9, 0 + atest 0x1f, 0x2e3d4c5b, 1, 13, 0xc7, 0xa98b71f2, 1 + atest 0x1f, 0x2e3d4c5b, 1, 14, 0x8f, 0x5316e3e5, 1 + atest 0x1f, 0x2e3d4c5b, 1, 15, 0x1e, 0xa62dc7cb, 1 + atest 0x1f, 0x2e3d4c5b, 1, 16, 0x3d, 0x4c5b8f97, 0 + atest 0x1f, 0x2e3d4c5b, 1, 17, 0x7a, 0x98b71f2e, 0 + atest 0x1f, 0x2e3d4c5b, 1, 18, 0xf5, 0x316e3e5c, 0 + atest 0x1f, 0x2e3d4c5b, 1, 19, 0xea, 0x62dc7cb8, 1 + atest 0x1f, 0x2e3d4c5b, 1, 20, 0xd4, 0xc5b8f971, 1 + atest 0x1f, 0x2e3d4c5b, 1, 21, 0xa9, 0x8b71f2e3, 1 + atest 0x1f, 0x2e3d4c5b, 1, 22, 0x53, 0x16e3e5c7, 1 + atest 0x1f, 0x2e3d4c5b, 1, 23, 0xa6, 0x2dc7cb8f, 0 + atest 0x1f, 0x2e3d4c5b, 1, 24, 0x4c, 0x5b8f971e, 1 + atest 0x1f, 0x2e3d4c5b, 1, 25, 0x98, 0xb71f2e3d, 0 + atest 0x1f, 0x2e3d4c5b, 1, 26, 0x31, 0x6e3e5c7a, 1 + atest 0x1f, 0x2e3d4c5b, 1, 27, 0x62, 0xdc7cb8f5, 0 + atest 0x1f, 0x2e3d4c5b, 1, 28, 0xc5, 0xb8f971ea, 0 + atest 0x1f, 0x2e3d4c5b, 1, 29, 0x8b, 0x71f2e3d4, 1 + atest 0x1f, 0x2e3d4c5b, 1, 30, 0x16, 0xe3e5c7a9, 1 + atest 0x1f, 0x2e3d4c5b, 1, 31, 0x2d, 0xc7cb8f53, 0 + atest 0x1f, 0x2e3d4c5b, 1, -1, 0x8f, 0x971ea62d, 1 + atest 0x1f, 0x2e3d4c5b, 1, -2, 0xc7, 0xcb8f5316, 1 + atest 0x1f, 0x2e3d4c5b, 1, -3, 0xe3, 0xe5c7a98b, 0 + atest 0x1f, 0x2e3d4c5b, 1, -4, 0x71, 0xf2e3d4c5, 1 + atest 0x1f, 0x2e3d4c5b, 1, -5, 0xb8, 0xf971ea62, 1 + atest 0x1f, 0x2e3d4c5b, 1, -6, 0xdc, 0x7cb8f531, 0 + atest 0x1f, 0x2e3d4c5b, 1, -7, 0x6e, 0x3e5c7a98, 1 + atest 0x1f, 0x2e3d4c5b, 1, -8, 0xb7, 0x1f2e3d4c, 0 + atest 0x1f, 0x2e3d4c5b, 1, -9, 0x5b, 0x8f971ea6, 0 + atest 0x1f, 0x2e3d4c5b, 1, -10, 0x2d, 0xc7cb8f53, 0 + atest 0x1f, 0x2e3d4c5b, 1, -11, 0x16, 0xe3e5c7a9, 1 + atest 0x1f, 0x2e3d4c5b, 1, -12, 0x8b, 0x71f2e3d4, 1 + atest 0x1f, 0x2e3d4c5b, 1, -13, 0xc5, 0xb8f971ea, 0 + atest 0x1f, 0x2e3d4c5b, 1, -14, 0x62, 0xdc7cb8f5, 0 + atest 0x1f, 0x2e3d4c5b, 1, -15, 0x31, 0x6e3e5c7a, 1 + atest 0x1f, 0x2e3d4c5b, 1, -16, 0x98, 0xb71f2e3d, 0 + atest 0x1f, 0x2e3d4c5b, 1, -17, 0x4c, 0x5b8f971e, 1 + atest 0x1f, 0x2e3d4c5b, 1, -18, 0xa6, 0x2dc7cb8f, 0 + atest 0x1f, 0x2e3d4c5b, 1, -19, 0x53, 0x16e3e5c7, 1 + atest 0x1f, 0x2e3d4c5b, 1, -20, 0xa9, 0x8b71f2e3, 1 + atest 0x1f, 0x2e3d4c5b, 1, -21, 0xd4, 0xc5b8f971, 1 + atest 0x1f, 0x2e3d4c5b, 1, -22, 0xea, 0x62dc7cb8, 1 + atest 0x1f, 0x2e3d4c5b, 1, -23, 0xf5, 0x316e3e5c, 0 + atest 0x1f, 0x2e3d4c5b, 1, -24, 0x7a, 0x98b71f2e, 0 + atest 0x1f, 0x2e3d4c5b, 1, -25, 0x3d, 0x4c5b8f97, 0 + atest 0x1f, 0x2e3d4c5b, 1, -26, 0x1e, 0xa62dc7cb, 1 + atest 0x1f, 0x2e3d4c5b, 1, -27, 0x8f, 0x5316e3e5, 1 + atest 0x1f, 0x2e3d4c5b, 1, -28, 0xc7, 0xa98b71f2, 1 + atest 0x1f, 0x2e3d4c5b, 1, -29, 0xe3, 0xd4c5b8f9, 0 + atest 0x1f, 0x2e3d4c5b, 1, -30, 0x71, 0xea62dc7c, 1 + atest 0x1f, 0x2e3d4c5b, 1, -31, 0xb8, 0xf5316e3e, 0 + atest 0x1f, 0x2e3d4c5b, 1, -32, 0x5c, 0x7a98b71f, 0 + + pass diff --git a/tests/tcg/bfin/acp5_19.s b/tests/tcg/bfin/acp5_19.s new file mode 100644 index 0000000000000..74e755202fad6 --- /dev/null +++ b/tests/tcg/bfin/acp5_19.s @@ -0,0 +1,12 @@ +# mach: bfin + +.include "testutils.inc" + start + + r0.h=0xa5a5; + r0.l=0xffff; + a0 = 0; + r0=a0.x; + dbga(r0.h, 0x0000); + dbga(r0.l, 0x0000); + pass; diff --git a/tests/tcg/bfin/add_imm7.s b/tests/tcg/bfin/add_imm7.s new file mode 100644 index 0000000000000..4709f1983ce3d --- /dev/null +++ b/tests/tcg/bfin/add_imm7.s @@ -0,0 +1,38 @@ +# mach: bfin + +.include "testutils.inc" + start + + r0 = 0 + ASTAT = r0; + + r2=-7; + r2+=-63; + _dbg r2; + _dbg astat; + r7=astat; + dbga ( r7.h, 0x0); + dbga ( r7.l, 0x1006); + + r7=0; + astat=r7; + r2=64; + r2+=-64; + _dbg r2; + _dbg astat; + r7=astat; + dbga ( r7.h, 0x0); + dbga ( r7.l, 0x1005); + + r7=0; + astat=r7; + r2=0; + r2.h=0x8000; + r2+=-63; + _dbg astat; + _dbg r2; + r7=astat; + dbga ( r7.h, 0x0000); + dbga ( r7.l, 0x1004); + + pass diff --git a/tests/tcg/bfin/algnbug1.s b/tests/tcg/bfin/algnbug1.s new file mode 100644 index 0000000000000..be0363bba0449 --- /dev/null +++ b/tests/tcg/bfin/algnbug1.s @@ -0,0 +1,38 @@ +# mach: bfin + +.include "testutils.inc" + start + + + loadsym P0, blocka; + I0 = P0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + I0 = P0; + M0 = 1 (X); + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + pass + + .data + .align 8 +blocka: + .dw 0xfeff + .dw 0xfcfd + .dw 0xfafb + .dw 0xf8f9 diff --git a/tests/tcg/bfin/algnbug2.s b/tests/tcg/bfin/algnbug2.s new file mode 100644 index 0000000000000..b06d5ad968c2b --- /dev/null +++ b/tests/tcg/bfin/algnbug2.s @@ -0,0 +1,69 @@ +# mach: bfin + +.include "testutils.inc" + start + + + M0 = 1 (X); + loadsym I0, blocka; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + pass + + .data; + .align 8 +blocka: + .dw 0xfeff + .dw 0xfcfd + .dw 0xfafb + .dw 0xf8f9 diff --git a/tests/tcg/bfin/b0.S b/tests/tcg/bfin/b0.S new file mode 100644 index 0000000000000..5a02092a15d61 --- /dev/null +++ b/tests/tcg/bfin/b0.S @@ -0,0 +1,51 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + CC = R0 == R0; + + AZ = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AC0|_AC0_COPY|_CC|_AZ); + R0 = R0 + R0; + R0 = ASTAT; CHECKREG R0, (_CC); + + AN = CC; + R0 = ASTAT; CHECKREG R0, (_CC|_AN); + R0 = - R0; + R0 = ASTAT; CHECKREG R0, (_CC|_AN); + + AC0 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AC0|_CC|_AN); + + AV0 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_CC|_AN); + + AV1 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_CC|_AN); + + AQ = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AQ|_CC|_AN); + + CC = R0 < R0; + _DBG ASTAT; + +// When AV0 is set, AV1 is unchanged + AQ = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AC0_COPY|_AZ); + + AV1 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_AC0_COPY|_AZ); + + pass diff --git a/tests/tcg/bfin/b1.s b/tests/tcg/bfin/b1.s new file mode 100644 index 0000000000000..c9eaeca58d48c --- /dev/null +++ b/tests/tcg/bfin/b1.s @@ -0,0 +1,12 @@ +# mach: bfin +.include "testutils.inc" + start + + R0 = 0; + CC = R0 == R0; + + IF CC JUMP 4; + JUMP.S LL1; + pass +LL1: + fail diff --git a/tests/tcg/bfin/b2.S b/tests/tcg/bfin/b2.S new file mode 100644 index 0000000000000..731f874460460 --- /dev/null +++ b/tests/tcg/bfin/b2.S @@ -0,0 +1,26 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + CC = BITTST ( R0 , 0x0 ); + BITSET( R0 , 0x0 ); + CC = BITTST ( R0 , 0x0 ); + CC = ! BITTST( R0 , 0x0 ); + R1.L = 1; + R1.H = 0; + CC = R0 == R1; + CC = BITTST ( R0 , 0x1 ); + R5 = ASTAT; + CHECKREG R5, (_AC0|_AC0_COPY|_AZ) + + BITSET( R0 , 0x1 ); + R5 = ASTAT; + CHECKREG R5, 0 + CC = BITTST ( R0 , 0x1 ); + CC = ! BITTST( R0 , 0x1 ); + pass diff --git a/tests/tcg/bfin/brcc.s b/tests/tcg/bfin/brcc.s new file mode 100644 index 0000000000000..479bf50aa16db --- /dev/null +++ b/tests/tcg/bfin/brcc.s @@ -0,0 +1,164 @@ +# mach: bfin + +.include "testutils.inc" + start + + + /* Stall tests */ + + r0 = 0; + r1 = 1; + loadsym p0, foo; + p1 = p0; + +pass_1: + cc = r0; + nop; + nop; + + if cc jump _fail_1; + [p0++] = p0; + [p0++] = p0; + r7 = p0; + r5 = CC; + P1 += 8; + r6 = p1; + CC = R6 == R7; + if !CC jump _failure; + + cc = R5; + if !cc jump over; + +_fail_1: + [p0++] = p0; + [p0++] = p0; + +back: + if !cc jump skip(bp); + +_fail_2: + [p0++] = p0; + [p0++] = p0; + +over: + if cc jump _fail_3(bp); + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5=cc; + P1 += 8; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + + CC = R5; + if !cc jump back(bp); + +_fail_3: + [p0++] = p0; + [p0++] = p0; + +skip: + [p0++] = p0; + [p0++] = p0; + [p0++] = p0; + r7=p0; + + P1 += 0xc; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + +next: + [p0++] = p0; + r7=p0; + P1 += 4; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + +pass_2: + cc = r1; + nop; + nop; + + if !cc jump _fail_4; + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5 = cc; + P1 += 8; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + + cc = R5; + if cc jump over_2; + +_fail_4: + [p0++] = p0; + [p0++] = p0; + P1 += 8; + +back_2: + if cc jump skip_2 (bp); + +_fail_5: + [p0++] = p0; + [p0++] = p0; + P1 += 8; + +over_2: + if !cc jump _fail_6 (bp); + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5 = cc; + P1 += 8; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + cc = R5; + + if cc jump back_2 (bp); + +_fail_6: + [p0++] = p0; + [p0++] = p0; + +skip_2: + [p0++] = p0; + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5 = cc; + P1 += 0xc; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + cc = r5; + + if cc jump next_2 (bp); + +next_2: + [p0++] = p0; + [p0++] = p0; + P1 += 8; + r7=p0; + r6 = P1; + CC = R6 == R7; + if !CC jump _failure; + + cc = r0; +_halt: + pass; + +_fail_7: + [p0++] = p0; + +_failure: + fail; + + .data +foo: + .space (0x100) diff --git a/tests/tcg/bfin/brevadd.s b/tests/tcg/bfin/brevadd.s new file mode 100644 index 0000000000000..56e112291c361 --- /dev/null +++ b/tests/tcg/bfin/brevadd.s @@ -0,0 +1,20 @@ +# Blackfin testcase for signbits +# mach: bfin + + .include "testutils.inc" + + start + + L2 = 0; + M2 = -4 (X); + I2.H = 0x9000; + I2.L = 0; + I2 += M2 (BREV); + R2 = I2; + imm32 r0, 0x10000002 + CC = R2 == R0 + if CC jump 1f; + + fail +1: + pass diff --git a/tests/tcg/bfin/byteunpack.s b/tests/tcg/bfin/byteunpack.s new file mode 100644 index 0000000000000..883c07172372a --- /dev/null +++ b/tests/tcg/bfin/byteunpack.s @@ -0,0 +1,45 @@ +# Blackfin testcase for playing with BYTEUNPACK +# mach: bfin + + .include "testutils.inc" + + start + + .macro _bu_pre_test i0:req, src0:req, src1:req + dmm32 I0, \i0 + imm32 R0, \src0 + imm32 R1, \src1 + .endm + .macro _bu_chk_test dst0:req, dst1:req + imm32 R2, \dst0 + imm32 R3, \dst1 + CC = R5 == R2; + IF !CC jump 1f; + CC = R6 == R3; + IF !CC jump 1f; + .endm + .macro bu_test i0:req, dst0:req, dst1:req, src0:req, src1:req + _bu_pre_test \i0, \src0, \src1 + (R6, R5) = BYTEUNPACK R1:0; + _bu_chk_test \dst0, \dst1 + .endm + .macro bu_r_test i0:req, dst0:req, dst1:req, src0:req, src1:req + _bu_pre_test \i0, \src0, \src1 + (R6, R5) = BYTEUNPACK R1:0 (R); + _bu_chk_test \dst0, \dst1 + .endm + + # Taken from PRM + bu_test 0, 0x00BA00DD, 0x00BE00EF, 0xBEEFBADD, 0xFEEDFACE + bu_test 1, 0x00EF00BA, 0x00CE00BE, 0xBEEFBADD, 0xFEEDFACE + bu_test 2, 0x00BE00EF, 0x00FA00CE, 0xBEEFBADD, 0xFEEDFACE + bu_test 3, 0x00CE00BE, 0x00ED00FA, 0xBEEFBADD, 0xFEEDFACE + + # Taken from PRM + bu_r_test 0, 0x00FA00CE, 0x00FE00ED, 0xBEEFBADD, 0xFEEDFACE + bu_r_test 1, 0x00ED00FA, 0x00DD00FE, 0xBEEFBADD, 0xFEEDFACE + bu_r_test 2, 0x00FE00ED, 0x00BA00DD, 0xBEEFBADD, 0xFEEDFACE + bu_r_test 3, 0x00DD00FE, 0x00EF00BA, 0xBEEFBADD, 0xFEEDFACE + + pass +1: fail diff --git a/tests/tcg/bfin/c_alu2op_arith_r_sft.s b/tests/tcg/bfin/c_alu2op_arith_r_sft.s new file mode 100644 index 0000000000000..7ce9d4edc5cd5 --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_arith_r_sft.s @@ -0,0 +1,226 @@ +//Original:/testcases/core/c_alu2op_arith_r_sft/c_alu2op_arith_r_sft.dsp +// Spec Reference: alu2op arith right +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R1.L = 1; +R1 >>>= R0; +R2 >>>= R0; +R3 >>>= R0; +R4 >>>= R0; +R5 >>>= R0; +R6 >>>= R0; +R7 >>>= R0; +R4 >>>= R0; +R0 >>>= R0; +CHECKREG r1, 0x12340001; +CHECKREG r2, 0x23456789; +CHECKREG r3, 0x3456789A; +CHECKREG r4, 0x856789AB; +CHECKREG r5, 0x96789ABC; +CHECKREG r6, 0xA789ABCD; +CHECKREG r7, 0xB89ABCDE; +CHECKREG r0, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R1.L = -1; +R0 >>>= R1; +R2 >>>= R1; +R3 >>>= R1; +R4 >>>= R1; +R5 >>>= R1; +R6 >>>= R1; +R7 >>>= R1; +R1 >>>= R1; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 31; +R0 >>>= R2; +R1 >>>= R2; +R3 >>>= R2; +R4 >>>= R2; +R5 >>>= R2; +R6 >>>= R2; +R7 >>>= R2; +R2 >>>= R2; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R3.L = -31; +R0 >>>= R3; +R1 >>>= R3; +R2 >>>= R3; +R4 >>>= R3; +R5 >>>= R3; +R6 >>>= R3; +R7 >>>= R3; +R3 >>>= R3; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x00000001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R4.L = 15; +R1 >>>= R4; +R2 >>>= R4; +R3 >>>= R4; +R0 >>>= R4; +R5 >>>= R4; +R6 >>>= R4; +R7 >>>= R4; +R4 >>>= R4; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00002468; +CHECKREG r2, 0x0000468A; +CHECKREG r3, 0x000068AC; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0xFFFF2CF1; +CHECKREG r6, 0xFFFF4F13; +CHECKREG r7, 0xFFFF7135; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x00000000; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R5.L = -15; +R0 >>>= R5; +R1 >>>= R5; +R2 >>>= R5; +R3 >>>= R5; +R4 >>>= R5; +R6 >>>= R5; +R7 >>>= R5; +R5 >>>= R5; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0xb1256790; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R6.L = 24; +R0 >>>= R6; +R1 >>>= R6; +R2 >>>= R6; +R3 >>>= R6; +R4 >>>= R6; +R5 >>>= R6; +R7 >>>= R6; +R6 >>>= R6; +CHECKREG r0, 0x00000051; +CHECKREG r1, 0x00000012; +CHECKREG r2, 0xFFFFFFB1; +CHECKREG r3, 0x00000034; +CHECKREG r4, 0xFFFFFF95; +CHECKREG r5, 0xFFFFFF86; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000078; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0x00000000; +R7.L = -24; +R0 >>>= R7; +R1 >>>= R7; +R2 >>>= R7; +R3 >>>= R7; +R4 >>>= R7; +R5 >>>= R7; +R6 >>>= R7; +R7 >>>= R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0x00000000; + +// special case +R2.L = -1; +R2.H = 32767; +R0 = 0; +R2 >>>= R0; +CHECKREG r2, 0x7FFFFFFF; + +pass diff --git a/tests/tcg/bfin/c_alu2op_conv_b.s b/tests/tcg/bfin/c_alu2op_conv_b.s new file mode 100644 index 0000000000000..0de3b520ee5bb --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_conv_b.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_b/c_alu2op_conv_b.dsp +// Spec Reference: alu2op convert b +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.B (Z); +R1 = R0.B (Z); +R2 = R0.B (Z); +R3 = R0.B (Z); +R4 = R0.B (Z); +R5 = R0.B (Z); +R6 = R0.B (Z); +R7 = R0.B (Z); +CHECKREG r0, 0x000000BC; +CHECKREG r1, 0x000000BC; +CHECKREG r2, 0x000000BC; +CHECKREG r3, 0x000000BC; +CHECKREG r4, 0x000000BC; +CHECKREG r5, 0x000000BC; +CHECKREG r6, 0x000000BC; +CHECKREG r7, 0x000000BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.B (Z); +R2 = R1.B (Z); +R3 = R1.B (Z); +R4 = R1.B (Z); +R5 = R1.B (Z); +R6 = R1.B (Z); +R7 = R1.B (Z); +R1 = R1.B (Z); +CHECKREG r0, 0x00000059; +CHECKREG r1, 0x00000059; +CHECKREG r2, 0x00000059; +CHECKREG r3, 0x00000059; +CHECKREG r4, 0x00000059; +CHECKREG r5, 0x00000059; +CHECKREG r6, 0x00000059; +CHECKREG r7, 0x00000059; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.B (Z); +R1 = R2.B (Z); +R3 = R2.B (Z); +R4 = R2.B (Z); +R5 = R2.B (Z); +R6 = R2.B (Z); +R7 = R2.B (Z); +R2 = R2.B (Z); +CHECKREG r0, 0x00000089; +CHECKREG r1, 0x00000089; +CHECKREG r2, 0x00000089; +CHECKREG r3, 0x00000089; +CHECKREG r4, 0x00000089; +CHECKREG r5, 0x00000089; +CHECKREG r6, 0x00000089; +CHECKREG r7, 0x00000089; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.B (Z); +R1 = R3.B (Z); +R2 = R3.B (Z); +R4 = R3.B (Z); +R5 = R3.B (Z); +R6 = R3.B (Z); +R7 = R3.B (Z); +R3 = R3.B (Z); +CHECKREG r0, 0x0000009A; +CHECKREG r1, 0x0000009A; +CHECKREG r2, 0x0000009A; +CHECKREG r3, 0x0000009A; +CHECKREG r4, 0x0000009A; +CHECKREG r5, 0x0000009A; +CHECKREG r6, 0x0000009A; +CHECKREG r7, 0x0000009A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.B (Z); +R1 = R4.B (Z); +R2 = R4.B (Z); +R3 = R4.B (Z); +R4 = R4.B (Z); +R5 = R4.B (Z); +R6 = R4.B (Z); +R7 = R4.B (Z); +CHECKREG r0, 0x000000AB; +CHECKREG r1, 0x000000AB; +CHECKREG r2, 0x000000AB; +CHECKREG r3, 0x000000AB; +CHECKREG r4, 0x000000AB; +CHECKREG r5, 0x000000AB; +CHECKREG r6, 0x000000AB; +CHECKREG r7, 0x000000AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.B (Z); +R1 = R5.B (Z); +R2 = R5.B (Z); +R3 = R5.B (Z); +R4 = R5.B (Z); +R6 = R5.B (Z); +R7 = R5.B (Z); +R5 = R5.B (Z); +CHECKREG r0, 0x000000BC; +CHECKREG r1, 0x000000BC; +CHECKREG r2, 0x000000BC; +CHECKREG r3, 0x000000BC; +CHECKREG r4, 0x000000BC; +CHECKREG r5, 0x000000BC; +CHECKREG r6, 0x000000BC; +CHECKREG r7, 0x000000BC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.B (Z); +R1 = R6.B (Z); +R2 = R6.B (Z); +R3 = R6.B (Z); +R4 = R6.B (Z); +R5 = R6.B (Z); +R7 = R6.B (Z); +R6 = R6.B (Z); +CHECKREG r0, 0x000000CD; +CHECKREG r1, 0x000000CD; +CHECKREG r2, 0x000000CD; +CHECKREG r3, 0x000000CD; +CHECKREG r4, 0x000000CD; +CHECKREG r5, 0x000000CD; +CHECKREG r6, 0x000000CD; +CHECKREG r7, 0x000000CD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.B (Z); +R1 = R7.B (Z); +R2 = R7.B (Z); +R3 = R7.B (Z); +R4 = R7.B (Z); +R5 = R7.B (Z); +R6 = R7.B (Z); +R7 = R7.B (Z); +CHECKREG r0, 0x00000088; +CHECKREG r1, 0x00000088; +CHECKREG r2, 0x00000088; +CHECKREG r3, 0x00000088; +CHECKREG r4, 0x00000088; +CHECKREG r5, 0x00000088; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x00000088; + + +pass diff --git a/tests/tcg/bfin/c_alu2op_conv_h.s b/tests/tcg/bfin/c_alu2op_conv_h.s new file mode 100644 index 0000000000000..70468a647be2b --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_conv_h.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_h/c_alu2op_conv_h.dsp +// Spec Reference: alu2op convert h +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.L (Z); +R1 = R0.L (Z); +R2 = R0.L (Z); +R3 = R0.L (Z); +R4 = R0.L (Z); +R5 = R0.L (Z); +R6 = R0.L (Z); +R7 = R0.L (Z); +CHECKREG r0, 0x00009ABC; +CHECKREG r1, 0x00009ABC; +CHECKREG r2, 0x00009ABC; +CHECKREG r3, 0x00009ABC; +CHECKREG r4, 0x00009ABC; +CHECKREG r5, 0x00009ABC; +CHECKREG r6, 0x00009ABC; +CHECKREG r7, 0x00009ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.L (Z); +R2 = R1.L (Z); +R3 = R1.L (Z); +R4 = R1.L (Z); +R5 = R1.L (Z); +R6 = R1.L (Z); +R7 = R1.L (Z); +R1 = R1.L (Z); +CHECKREG r0, 0x00004659; +CHECKREG r1, 0x00004659; +CHECKREG r2, 0x00004659; +CHECKREG r3, 0x00004659; +CHECKREG r4, 0x00004659; +CHECKREG r5, 0x00004659; +CHECKREG r6, 0x00004659; +CHECKREG r7, 0x00004659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.L (Z); +R1 = R2.L (Z); +R3 = R2.L (Z); +R4 = R2.L (Z); +R5 = R2.L (Z); +R6 = R2.L (Z); +R7 = R2.L (Z); +R2 = R2.L (Z); +CHECKREG r0, 0x00006789; +CHECKREG r1, 0x00006789; +CHECKREG r2, 0x00006789; +CHECKREG r3, 0x00006789; +CHECKREG r4, 0x00006789; +CHECKREG r5, 0x00006789; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x00006789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.L (Z); +R1 = R3.L (Z); +R2 = R3.L (Z); +R4 = R3.L (Z); +R5 = R3.L (Z); +R6 = R3.L (Z); +R7 = R3.L (Z); +R3 = R3.L (Z); +CHECKREG r0, 0x0000789A; +CHECKREG r1, 0x0000789A; +CHECKREG r2, 0x0000789A; +CHECKREG r3, 0x0000789A; +CHECKREG r4, 0x0000789A; +CHECKREG r5, 0x0000789A; +CHECKREG r6, 0x0000789A; +CHECKREG r7, 0x0000789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.L (Z); +R1 = R4.L (Z); +R2 = R4.L (Z); +R3 = R4.L (Z); +R4 = R4.L (Z); +R5 = R4.L (Z); +R6 = R4.L (Z); +R7 = R4.L (Z); +CHECKREG r0, 0x0000A9AB; +CHECKREG r1, 0x0000A9AB; +CHECKREG r2, 0x0000A9AB; +CHECKREG r3, 0x0000A9AB; +CHECKREG r4, 0x0000A9AB; +CHECKREG r5, 0x0000A9AB; +CHECKREG r6, 0x0000A9AB; +CHECKREG r7, 0x0000A9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.L (Z); +R1 = R5.L (Z); +R2 = R5.L (Z); +R3 = R5.L (Z); +R4 = R5.L (Z); +R6 = R5.L (Z); +R7 = R5.L (Z); +R5 = R5.L (Z); +CHECKREG r0, 0x00009FBC; +CHECKREG r1, 0x00009FBC; +CHECKREG r2, 0x00009FBC; +CHECKREG r3, 0x00009FBC; +CHECKREG r4, 0x00009FBC; +CHECKREG r5, 0x00009FBC; +CHECKREG r6, 0x00009FBC; +CHECKREG r7, 0x00009FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.L (Z); +R1 = R6.L (Z); +R2 = R6.L (Z); +R3 = R6.L (Z); +R4 = R6.L (Z); +R5 = R6.L (Z); +R7 = R6.L (Z); +R6 = R6.L (Z); +CHECKREG r0, 0x0000AECD; +CHECKREG r1, 0x0000AECD; +CHECKREG r2, 0x0000AECD; +CHECKREG r3, 0x0000AECD; +CHECKREG r4, 0x0000AECD; +CHECKREG r5, 0x0000AECD; +CHECKREG r6, 0x0000AECD; +CHECKREG r7, 0x0000AECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.L (Z); +R1 = R7.L (Z); +R2 = R7.L (Z); +R3 = R7.L (Z); +R4 = R7.L (Z); +R5 = R7.L (Z); +R6 = R7.L (Z); +R7 = R7.L (Z); +CHECKREG r0, 0x0000BC88; +CHECKREG r1, 0x0000BC88; +CHECKREG r2, 0x0000BC88; +CHECKREG r3, 0x0000BC88; +CHECKREG r4, 0x0000BC88; +CHECKREG r5, 0x0000BC88; +CHECKREG r6, 0x0000BC88; +CHECKREG r7, 0x0000BC88; + + +pass diff --git a/tests/tcg/bfin/c_alu2op_conv_mix.s b/tests/tcg/bfin/c_alu2op_conv_mix.s new file mode 100644 index 0000000000000..7c33c13096e4b --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_conv_mix.s @@ -0,0 +1,186 @@ +//Original:/testcases/core/c_alu2op_conv_mix/c_alu2op_conv_mix.dsp +// Spec Reference: alu2op convert mix +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.B (X); +R1 = R1.L (X); +R2 = R2.L (Z); +R3 = R3.B (X); +R4 = R4.B (Z); +R5 = - R5; +R6 = ~ R6; +R7 = R7.L (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0x00005678; +CHECKREG r2, 0x00006789; +CHECKREG r3, 0xFFFFFF9A; +CHECKREG r4, 0x000000AB; +CHECKREG r5, 0x69876544; +CHECKREG r6, 0x58765432; +CHECKREG r7, 0xFFFFBCDE; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R6 = R0.B (X); +R7 = R1.L (X); +R0 = R2.L (Z); +R1 = R3.B (X); +R2 = R4.B (Z); +R3 = - R5; +R4 = ~ R6; +R5 = R7.L (X); +CHECKREG r0, 0x00006789; +CHECKREG r1, 0xFFFFFF9A; +CHECKREG r2, 0x000000AB; +CHECKREG r3, 0x39876544; +CHECKREG r4, 0xFFFFFFFD; +CHECKREG r5, 0x00004659; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0x00004659; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x91203450; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0x789abcde; +R5 = R0.B (X); +R6 = R1.L (X); +R7 = R2.L (Z); +R0 = R3.B (X); +R1 = R4.B (Z); +R2 = - R5; +R3 = ~ R6; +R4 = R7.L (X); +CHECKREG r0, 0xFFFFFF9A; +CHECKREG r1, 0x000000AB; +CHECKREG r2, 0xFFFFFFFE; +CHECKREG r3, 0xFFFFA987; +CHECKREG r4, 0x00003450; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00005678; +CHECKREG r7, 0x00003450; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R4 = R0.B (X); +R5 = R1.L (X); +R6 = R2.L (Z); +R7 = R3.B (X); +R0 = R4.B (Z); +R1 = - R5; +R2 = ~ R6; +R3 = R7.L (X); +CHECKREG r0, 0x00000002; +CHECKREG r1, 0xFFFFA988; +CHECKREG r2, 0xFFFF9876; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00005678; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xadf00001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R3 = R0.B (X); +R4 = R1.L (X); +R5 = R2.L (Z); +R6 = R3.B (X); +R7 = R4.B (Z); +R0 = - R5; +R1 = ~ R6; +R2 = R7.L (X); +CHECKREG r0, 0xFFFF9877; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000078; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00005678; +CHECKREG r5, 0x00006789; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000078; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x54238900; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R2 = R0.B (X); +R3 = R1.L (X); +R4 = R2.L (Z); +R5 = R3.B (X); +R6 = R4.B (Z); +R7 = - R5; +R0 = ~ R6; +R1 = R7.L (X); +CHECKREG r0, 0xFFFFFFFD; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R1 = R0.B (X); +R2 = R1.L (X); +R3 = R2.L (Z); +R4 = R3.B (X); +R5 = R4.B (Z); +R6 = - R5; +R0 = ~ R6; +R7 = R7.L (X); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000002; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0xFFFFFFFE; +CHECKREG r7, 0xFFFFBCDE; + + +pass diff --git a/tests/tcg/bfin/c_alu2op_conv_neg.s b/tests/tcg/bfin/c_alu2op_conv_neg.s new file mode 100644 index 0000000000000..85314a81c4a2d --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_conv_neg.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_neg/c_alu2op_conv_neg.dsp +// Spec Reference: alu2op (-) negative +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = - R0; +R1 = - R0; +R2 = - R0; +R3 = - R0; +R4 = - R0; +R5 = - R0; +R6 = - R0; +R7 = - R0; +CHECKREG r0, 0xFF876544; +CHECKREG r1, 0x00789ABC; +CHECKREG r2, 0x00789ABC; +CHECKREG r3, 0x00789ABC; +CHECKREG r4, 0x00789ABC; +CHECKREG r5, 0x00789ABC; +CHECKREG r6, 0x00789ABC; +CHECKREG r7, 0x00789ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = - R1; +R1 = - R1; +R2 = - R1; +R3 = - R1; +R4 = - R1; +R5 = - R1; +R6 = - R1; +R7 = - R1; +CHECKREG r0, 0xFFC8B9A7; +CHECKREG r1, 0xFFC8B9A7; +CHECKREG r2, 0x00374659; +CHECKREG r3, 0x00374659; +CHECKREG r4, 0x00374659; +CHECKREG r5, 0x00374659; +CHECKREG r6, 0x00374659; +CHECKREG r7, 0x00374659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = - R2; +R1 = - R2; +R2 = - R2; +R3 = - R2; +R4 = - R2; +R5 = - R2; +R6 = - R2; +R7 = - R2; +CHECKREG r0, 0x6CEA9877; +CHECKREG r1, 0x6CEA9877; +CHECKREG r2, 0x6CEA9877; +CHECKREG r3, 0x93156789; +CHECKREG r4, 0x93156789; +CHECKREG r5, 0x93156789; +CHECKREG r6, 0x93156789; +CHECKREG r7, 0x93156789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = - R3; +R1 = - R3; +R2 = - R3; +R3 = - R3; +R4 = - R3; +R5 = - R3; +R6 = - R3; +R7 = - R3; +CHECKREG r0, 0x56AD8766; +CHECKREG r1, 0x56AD8766; +CHECKREG r2, 0x56AD8766; +CHECKREG r3, 0x56AD8766; +CHECKREG r4, 0xA952789A; +CHECKREG r5, 0xA952789A; +CHECKREG r6, 0xA952789A; +CHECKREG r7, 0xA952789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = - R4; +R1 = - R4; +R2 = - R4; +R3 = - R4; +R4 = - R4; +R5 = - R4; +R6 = - R4; +R7 = - R4; +CHECKREG r0, 0x79985655; +CHECKREG r1, 0x79985655; +CHECKREG r2, 0x79985655; +CHECKREG r3, 0x79985655; +CHECKREG r4, 0x79985655; +CHECKREG r5, 0x8667A9AB; +CHECKREG r6, 0x8667A9AB; +CHECKREG r7, 0x8667A9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = - R5; +R1 = - R5; +R2 = - R5; +R3 = - R5; +R4 = - R5; +R5 = - R5; +R6 = - R5; +R7 = - R5; +CHECKREG r0, 0x39876044; +CHECKREG r1, 0x39876044; +CHECKREG r2, 0x39876044; +CHECKREG r3, 0x39876044; +CHECKREG r4, 0x39876044; +CHECKREG r5, 0x39876044; +CHECKREG r6, 0xC6789FBC; +CHECKREG r7, 0xC6789FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = - R6; +R1 = - R6; +R2 = - R6; +R3 = - R6; +R4 = - R6; +R5 = - R6; +R6 = - R6; +R7 = - R6; +CHECKREG r0, 0x58765133; +CHECKREG r1, 0x58765133; +CHECKREG r2, 0x58765133; +CHECKREG r3, 0x58765133; +CHECKREG r4, 0x58765133; +CHECKREG r5, 0x58765133; +CHECKREG r6, 0x58765133; +CHECKREG r7, 0xA789AECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = - R7; +R1 = - R7; +R2 = - R7; +R3 = - R7; +R4 = - R7; +R5 = - R7; +R7 = - R7; +R6 = - R7; +CHECKREG r0, 0xA7654378; +CHECKREG r1, 0xA7654378; +CHECKREG r2, 0xA7654378; +CHECKREG r3, 0xA7654378; +CHECKREG r4, 0xA7654378; +CHECKREG r5, 0xA7654378; +CHECKREG r6, 0x589ABC88; +CHECKREG r7, 0xA7654378; + + +pass diff --git a/tests/tcg/bfin/c_alu2op_conv_toggle.s b/tests/tcg/bfin/c_alu2op_conv_toggle.s new file mode 100644 index 0000000000000..791d7a941beb1 --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_conv_toggle.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_toggle/c_alu2op_conv_toggle.dsp +// Spec Reference: alu2op (~) toggle +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = ~ R0; +R1 = ~ R0; +R2 = ~ R0; +R3 = ~ R0; +R4 = ~ R0; +R5 = ~ R0; +R6 = ~ R0; +R7 = ~ R0; +CHECKREG r0, 0xFF876543; +CHECKREG r1, 0x00789ABC; +CHECKREG r2, 0x00789ABC; +CHECKREG r3, 0x00789ABC; +CHECKREG r4, 0x00789ABC; +CHECKREG r5, 0x00789ABC; +CHECKREG r6, 0x00789ABC; +CHECKREG r7, 0x00789ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = ~ R1; +R1 = ~ R1; +R2 = ~ R1; +R3 = ~ R1; +R4 = ~ R1; +R5 = ~ R1; +R6 = ~ R1; +R7 = ~ R1; +CHECKREG r0, 0xFFC8B9A6; +CHECKREG r1, 0xFFC8B9A6; +CHECKREG r2, 0x00374659; +CHECKREG r3, 0x00374659; +CHECKREG r4, 0x00374659; +CHECKREG r5, 0x00374659; +CHECKREG r6, 0x00374659; +CHECKREG r7, 0x00374659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = ~ R2; +R1 = ~ R2; +R2 = ~ R2; +R3 = ~ R2; +R4 = ~ R2; +R5 = ~ R2; +R6 = ~ R2; +R7 = ~ R2; +CHECKREG r0, 0x6CEA9876; +CHECKREG r1, 0x6CEA9876; +CHECKREG r2, 0x6CEA9876; +CHECKREG r3, 0x93156789; +CHECKREG r4, 0x93156789; +CHECKREG r5, 0x93156789; +CHECKREG r6, 0x93156789; +CHECKREG r7, 0x93156789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = ~ R3; +R1 = ~ R3; +R2 = ~ R3; +R3 = ~ R3; +R4 = ~ R3; +R5 = ~ R3; +R6 = ~ R3; +R7 = ~ R3; +CHECKREG r0, 0x56AD8765; +CHECKREG r1, 0x56AD8765; +CHECKREG r2, 0x56AD8765; +CHECKREG r3, 0x56AD8765; +CHECKREG r4, 0xA952789A; +CHECKREG r5, 0xA952789A; +CHECKREG r6, 0xA952789A; +CHECKREG r7, 0xA952789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = ~ R4; +R1 = ~ R4; +R2 = ~ R4; +R3 = ~ R4; +R4 = ~ R4; +R5 = ~ R4; +R6 = ~ R4; +R7 = ~ R4; +CHECKREG r0, 0x79985654; +CHECKREG r1, 0x79985654; +CHECKREG r2, 0x79985654; +CHECKREG r3, 0x79985654; +CHECKREG r4, 0x79985654; +CHECKREG r5, 0x8667A9AB; +CHECKREG r6, 0x8667A9AB; +CHECKREG r7, 0x8667A9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = ~ R5; +R1 = ~ R5; +R2 = ~ R5; +R3 = ~ R5; +R4 = ~ R5; +R5 = ~ R5; +R6 = ~ R5; +R7 = ~ R5; +CHECKREG r0, 0x39876043; +CHECKREG r1, 0x39876043; +CHECKREG r2, 0x39876043; +CHECKREG r3, 0x39876043; +CHECKREG r4, 0x39876043; +CHECKREG r5, 0x39876043; +CHECKREG r6, 0xC6789FBC; +CHECKREG r7, 0xC6789FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = ~ R6; +R1 = ~ R6; +R2 = ~ R6; +R3 = ~ R6; +R4 = ~ R6; +R5 = ~ R6; +R6 = ~ R6; +R7 = ~ R6; +CHECKREG r0, 0x58765132; +CHECKREG r1, 0x58765132; +CHECKREG r2, 0x58765132; +CHECKREG r3, 0x58765132; +CHECKREG r4, 0x58765132; +CHECKREG r5, 0x58765132; +CHECKREG r6, 0x58765132; +CHECKREG r7, 0xA789AECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = ~ R7; +R1 = ~ R7; +R2 = ~ R7; +R3 = ~ R7; +R4 = ~ R7; +R5 = ~ R7; +R7 = ~ R7; +R6 = ~ R7; +CHECKREG r0, 0xA7654377; +CHECKREG r1, 0xA7654377; +CHECKREG r2, 0xA7654377; +CHECKREG r3, 0xA7654377; +CHECKREG r4, 0xA7654377; +CHECKREG r5, 0xA7654377; +CHECKREG r6, 0x589ABC88; +CHECKREG r7, 0xA7654377; + + +pass diff --git a/tests/tcg/bfin/c_alu2op_conv_xb.s b/tests/tcg/bfin/c_alu2op_conv_xb.s new file mode 100644 index 0000000000000..779a790dbee61 --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_conv_xb.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_xb/c_alu2op_conv_xb.dsp +// Spec Reference: alu2op convert xb +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.B (X); +R1 = R0.B (X); +R2 = R0.B (X); +R3 = R0.B (X); +R4 = R0.B (X); +R5 = R0.B (X); +R6 = R0.B (X); +R7 = R0.B (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0xFFFFFFBC; +CHECKREG r2, 0xFFFFFFBC; +CHECKREG r3, 0xFFFFFFBC; +CHECKREG r4, 0xFFFFFFBC; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFBC; +CHECKREG r7, 0xFFFFFFBC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.B (X); +R2 = R1.B (X); +R3 = R1.B (X); +R4 = R1.B (X); +R5 = R1.B (X); +R6 = R1.B (X); +R7 = R1.B (X); +R1 = R1.B (X); +CHECKREG r0, 0x00000059; +CHECKREG r1, 0x00000059; +CHECKREG r2, 0x00000059; +CHECKREG r3, 0x00000059; +CHECKREG r4, 0x00000059; +CHECKREG r5, 0x00000059; +CHECKREG r6, 0x00000059; +CHECKREG r7, 0x00000059; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.B (X); +R1 = R2.B (X); +R3 = R2.B (X); +R4 = R2.B (X); +R5 = R2.B (X); +R6 = R2.B (X); +R7 = R2.B (X); +R2 = R2.B (X); +CHECKREG r0, 0xFFFFFF89; +CHECKREG r1, 0xFFFFFF89; +CHECKREG r2, 0xFFFFFF89; +CHECKREG r3, 0xFFFFFF89; +CHECKREG r4, 0xFFFFFF89; +CHECKREG r5, 0xFFFFFF89; +CHECKREG r6, 0xFFFFFF89; +CHECKREG r7, 0xFFFFFF89; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.B (X); +R1 = R3.B (X); +R2 = R3.B (X); +R4 = R3.B (X); +R5 = R3.B (X); +R6 = R3.B (X); +R7 = R3.B (X); +R3 = R3.B (X); +CHECKREG r0, 0xFFFFFF9A; +CHECKREG r1, 0xFFFFFF9A; +CHECKREG r2, 0xFFFFFF9A; +CHECKREG r3, 0xFFFFFF9A; +CHECKREG r4, 0xFFFFFF9A; +CHECKREG r5, 0xFFFFFF9A; +CHECKREG r6, 0xFFFFFF9A; +CHECKREG r7, 0xFFFFFF9A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.B (X); +R1 = R4.B (X); +R2 = R4.B (X); +R3 = R4.B (X); +R4 = R4.B (X); +R5 = R4.B (X); +R6 = R4.B (X); +R7 = R4.B (X); +CHECKREG r0, 0xFFFFFFAB; +CHECKREG r1, 0xFFFFFFAB; +CHECKREG r2, 0xFFFFFFAB; +CHECKREG r3, 0xFFFFFFAB; +CHECKREG r4, 0xFFFFFFAB; +CHECKREG r5, 0xFFFFFFAB; +CHECKREG r6, 0xFFFFFFAB; +CHECKREG r7, 0xFFFFFFAB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.B (X); +R1 = R5.B (X); +R2 = R5.B (X); +R3 = R5.B (X); +R4 = R5.B (X); +R6 = R5.B (X); +R7 = R5.B (X); +R5 = R5.B (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0xFFFFFFBC; +CHECKREG r2, 0xFFFFFFBC; +CHECKREG r3, 0xFFFFFFBC; +CHECKREG r4, 0xFFFFFFBC; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFBC; +CHECKREG r7, 0xFFFFFFBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.B (X); +R1 = R6.B (X); +R2 = R6.B (X); +R3 = R6.B (X); +R4 = R6.B (X); +R5 = R6.B (X); +R7 = R6.B (X); +R6 = R6.B (X); +CHECKREG r0, 0xFFFFFFCD; +CHECKREG r1, 0xFFFFFFCD; +CHECKREG r2, 0xFFFFFFCD; +CHECKREG r3, 0xFFFFFFCD; +CHECKREG r4, 0xFFFFFFCD; +CHECKREG r5, 0xFFFFFFCD; +CHECKREG r6, 0xFFFFFFCD; +CHECKREG r7, 0xFFFFFFCD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.B (X); +R1 = R7.B (X); +R2 = R7.B (X); +R3 = R7.B (X); +R4 = R7.B (X); +R5 = R7.B (X); +R6 = R7.B (X); +R7 = R7.B (X); +CHECKREG r0, 0xFFFFFF88; +CHECKREG r1, 0xFFFFFF88; +CHECKREG r2, 0xFFFFFF88; +CHECKREG r3, 0xFFFFFF88; +CHECKREG r4, 0xFFFFFF88; +CHECKREG r5, 0xFFFFFF88; +CHECKREG r6, 0xFFFFFF88; +CHECKREG r7, 0xFFFFFF88; + + +pass diff --git a/tests/tcg/bfin/c_alu2op_conv_xh.s b/tests/tcg/bfin/c_alu2op_conv_xh.s new file mode 100644 index 0000000000000..75b06c0b8d9bf --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_conv_xh.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_alu2op_conv_xh/c_alu2op_conv_xh.dsp +// Spec Reference: alu2op convert xh +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.L (X); +R1 = R0.L (X); +R2 = R0.L (X); +R3 = R0.L (X); +R4 = R0.L (X); +R5 = R0.L (X); +R6 = R0.L (X); +R7 = R0.L (X); +CHECKREG r0, 0xFFFF9ABC; +CHECKREG r1, 0xFFFF9ABC; +CHECKREG r2, 0xFFFF9ABC; +CHECKREG r3, 0xFFFF9ABC; +CHECKREG r4, 0xFFFF9ABC; +CHECKREG r5, 0xFFFF9ABC; +CHECKREG r6, 0xFFFF9ABC; +CHECKREG r7, 0xFFFF9ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.L (X); +R2 = R1.L (X); +R3 = R1.L (X); +R4 = R1.L (X); +R5 = R1.L (X); +R6 = R1.L (X); +R7 = R1.L (X); +R1 = R1.L (X); +CHECKREG r0, 0x00004659; +CHECKREG r1, 0x00004659; +CHECKREG r2, 0x00004659; +CHECKREG r3, 0x00004659; +CHECKREG r4, 0x00004659; +CHECKREG r5, 0x00004659; +CHECKREG r6, 0x00004659; +CHECKREG r7, 0x00004659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.L (X); +R1 = R2.L (X); +R3 = R2.L (X); +R4 = R2.L (X); +R5 = R2.L (X); +R6 = R2.L (X); +R7 = R2.L (X); +R2 = R2.L (X); +CHECKREG r0, 0x00006789; +CHECKREG r1, 0x00006789; +CHECKREG r2, 0x00006789; +CHECKREG r3, 0x00006789; +CHECKREG r4, 0x00006789; +CHECKREG r5, 0x00006789; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x00006789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.L (X); +R1 = R3.L (X); +R2 = R3.L (X); +R4 = R3.L (X); +R5 = R3.L (X); +R6 = R3.L (X); +R7 = R3.L (X); +R3 = R3.L (X); +CHECKREG r0, 0x0000789A; +CHECKREG r1, 0x0000789A; +CHECKREG r2, 0x0000789A; +CHECKREG r3, 0x0000789A; +CHECKREG r4, 0x0000789A; +CHECKREG r5, 0x0000789A; +CHECKREG r6, 0x0000789A; +CHECKREG r7, 0x0000789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.L (X); +R1 = R4.L (X); +R2 = R4.L (X); +R3 = R4.L (X); +R4 = R4.L (X); +R5 = R4.L (X); +R6 = R4.L (X); +R7 = R4.L (X); +CHECKREG r0, 0xFFFFA9AB; +CHECKREG r1, 0xFFFFA9AB; +CHECKREG r2, 0xFFFFA9AB; +CHECKREG r3, 0xFFFFA9AB; +CHECKREG r4, 0xFFFFA9AB; +CHECKREG r5, 0xFFFFA9AB; +CHECKREG r6, 0xFFFFA9AB; +CHECKREG r7, 0xFFFFA9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.L (X); +R1 = R5.L (X); +R2 = R5.L (X); +R3 = R5.L (X); +R4 = R5.L (X); +R6 = R5.L (X); +R7 = R5.L (X); +R5 = R5.L (X); +CHECKREG r0, 0xFFFF9FBC; +CHECKREG r1, 0xFFFF9FBC; +CHECKREG r2, 0xFFFF9FBC; +CHECKREG r3, 0xFFFF9FBC; +CHECKREG r4, 0xFFFF9FBC; +CHECKREG r5, 0xFFFF9FBC; +CHECKREG r6, 0xFFFF9FBC; +CHECKREG r7, 0xFFFF9FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.L (X); +R1 = R6.L (X); +R2 = R6.L (X); +R3 = R6.L (X); +R4 = R6.L (X); +R5 = R6.L (X); +R7 = R6.L (X); +R6 = R6.L (X); +CHECKREG r0, 0xFFFFAECD; +CHECKREG r1, 0xFFFFAECD; +CHECKREG r2, 0xFFFFAECD; +CHECKREG r3, 0xFFFFAECD; +CHECKREG r4, 0xFFFFAECD; +CHECKREG r5, 0xFFFFAECD; +CHECKREG r6, 0xFFFFAECD; +CHECKREG r7, 0xFFFFAECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.L (X); +R1 = R7.L (X); +R2 = R7.L (X); +R3 = R7.L (X); +R4 = R7.L (X); +R5 = R7.L (X); +R6 = R7.L (X); +R7 = R7.L (X); +CHECKREG r0, 0xFFFFBC88; +CHECKREG r1, 0xFFFFBC88; +CHECKREG r2, 0xFFFFBC88; +CHECKREG r3, 0xFFFFBC88; +CHECKREG r4, 0xFFFFBC88; +CHECKREG r5, 0xFFFFBC88; +CHECKREG r6, 0xFFFFBC88; +CHECKREG r7, 0xFFFFBC88; + + +pass diff --git a/tests/tcg/bfin/c_alu2op_divq.s b/tests/tcg/bfin/c_alu2op_divq.s new file mode 100644 index 0000000000000..2a03227b67111 --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_divq.s @@ -0,0 +1,220 @@ +//Original:/testcases/core/c_alu2op_divq/c_alu2op_divq.dsp +// Spec Reference: alu2op divide q +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0.L = 1; +DIVQ ( R1 , R0 ); +DIVQ ( R2 , R0 ); +DIVQ ( R3 , R0 ); +DIVQ ( R4 , R0 ); +DIVQ ( R5 , R0 ); +DIVQ ( R6 , R0 ); +DIVQ ( R7 , R0 ); +DIVQ ( R4 , R0 ); +DIVQ ( R0 , R0 ); +CHECKREG r1, 0x2466ACF1; +CHECKREG r2, 0x4688CF13; +CHECKREG r3, 0x68AAF135; +CHECKREG r4, 0x159C26AD; +CHECKREG r5, 0x2CF33578; +CHECKREG r6, 0x4F15579A; +CHECKREG r7, 0x713779BC; +CHECKREG r0, 0xFFFE0002; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R1.L = -1; +DIVQ ( R0 , R1 ); +DIVQ ( R2 , R1 ); +DIVQ ( R3 , R1 ); +DIVQ ( R4 , R1 ); +DIVQ ( R5 , R1 ); +DIVQ ( R6 , R1 ); +DIVQ ( R7 , R1 ); +DIVQ ( R1 , R1 ); +CHECKREG r0, 0x02440004; +CHECKREG r1, 0x0003FFFE; +CHECKREG r2, 0x2688CF13; +CHECKREG r3, 0x48AEF135; +CHECKREG r4, 0x6AD11357; +CHECKREG r5, 0x8CF33579; +CHECKREG r6, 0xAF15579B; +CHECKREG r7, 0xD13779BD; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 31; +DIVQ ( R0 , R2 ); +DIVQ ( R1 , R2 ); +DIVQ ( R3 , R2 ); +DIVQ ( R4 , R2 ); +DIVQ ( R5 , R2 ); +DIVQ ( R6 , R2 ); +DIVQ ( R7 , R2 ); +DIVQ ( R2 , R2 ); +CHECKREG r0, 0xA2840005; +CHECKREG r1, 0x242AACF1; +CHECKREG r2, 0xFFC2003E; +CHECKREG r3, 0x686EF135; +CHECKREG r4, 0x2A911356; +CHECKREG r5, 0x0D2F3578; +CHECKREG r6, 0xCF51579B; +CHECKREG r7, 0xF0F779BD; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R3.L = -31; +DIVQ ( R0 , R3 ); +DIVQ ( R1 , R3 ); +DIVQ ( R2 , R3 ); +DIVQ ( R4 , R3 ); +DIVQ ( R5 , R3 ); +DIVQ ( R6 , R3 ); +DIVQ ( R7 , R3 ); +DIVQ ( R3 , R3 ); +CHECKREG r0, 0x02080004; +CHECKREG r1, 0x042AACF1; +CHECKREG r2, 0x26C8CF13; +CHECKREG r3, 0x003FFFC2; +CHECKREG r4, 0x6B0D1357; +CHECKREG r5, 0x8D2F3579; +CHECKREG r6, 0xAF51579B; +CHECKREG r7, 0xD17379BD; + +imm32 r0, 0x00000001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R4.L = 15; +DIVQ ( R1 , R4 ); +DIVQ ( R2 , R4 ); +DIVQ ( R3 , R4 ); +DIVQ ( R0 , R4 ); +DIVQ ( R5 , R4 ); +DIVQ ( R6 , R4 ); +DIVQ ( R7 , R4 ); +DIVQ ( R4 , R4 ); +CHECKREG r0, 0xFFE20002; +CHECKREG r1, 0x2486ACF1; +CHECKREG r2, 0x466CCF13; +CHECKREG r3, 0x688EF135; +CHECKREG r4, 0x001E001F; +CHECKREG r5, 0x2D0F3578; +CHECKREG r6, 0x4F31579A; +CHECKREG r7, 0x715379BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x00000000; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R5.L = -15; +DIVQ ( R0 , R5 ); +DIVQ ( R1 , R5 ); +DIVQ ( R2 , R5 ); +DIVQ ( R3 , R5 ); +DIVQ ( R4 , R5 ); +DIVQ ( R6 , R5 ); +DIVQ ( R7 , R5 ); +DIVQ ( R5 , R5 ); +CHECKREG r0, 0x02640004; +CHECKREG r1, 0xFFE20001; +CHECKREG r2, 0x26A8CF13; +CHECKREG r3, 0x48CAF135; +CHECKREG r4, 0x6AED1357; +CHECKREG r5, 0x001FFFE2; +CHECKREG r6, 0xAF31579B; +CHECKREG r7, 0xD15379BD; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0xb1256790; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R6.L = 24; +DIVQ ( R0 , R6 ); +DIVQ ( R1 , R6 ); +DIVQ ( R2 , R6 ); +DIVQ ( R3 , R6 ); +DIVQ ( R4 , R6 ); +DIVQ ( R5 , R6 ); +DIVQ ( R7 , R6 ); +DIVQ ( R6 , R6 ); +CHECKREG r0, 0xA2760005; +CHECKREG r1, 0x2438ACF1; +CHECKREG r2, 0x621ACF20; +CHECKREG r3, 0x68DCF135; +CHECKREG r4, 0x2A9F1356; +CHECKREG r5, 0x0D213578; +CHECKREG r6, 0xFFD00030; +CHECKREG r7, 0xF16579BD; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0x00000000; +R7.L = -24; +DIVQ ( R0 , R7 ); +DIVQ ( R1 , R7 ); +DIVQ ( R2 , R7 ); +DIVQ ( R3 , R7 ); +DIVQ ( R4 , R7 ); +DIVQ ( R5 , R7 ); +DIVQ ( R6 , R7 ); +DIVQ ( R7 , R7 ); +CHECKREG r0, 0x02160004; +CHECKREG r1, 0x0438ACF1; +CHECKREG r2, 0x26BACF13; +CHECKREG r3, 0x48DCF135; +CHECKREG r4, 0x6AFF1357; +CHECKREG r5, 0x8D213579; +CHECKREG r6, 0xAF43579B; +CHECKREG r7, 0x0031FFD0; + + +pass diff --git a/tests/tcg/bfin/c_alu2op_divs.s b/tests/tcg/bfin/c_alu2op_divs.s new file mode 100644 index 0000000000000..f0fc09155644c --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_divs.s @@ -0,0 +1,220 @@ +//Original:/testcases/core/c_alu2op_divs/c_alu2op_divs.dsp +// Spec Reference: alu2op divide s +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0.L = 1; +DIVS ( R1 , R0 ); +DIVS ( R2 , R0 ); +DIVS ( R3 , R0 ); +DIVS ( R4 , R0 ); +DIVS ( R5 , R0 ); +DIVS ( R6 , R0 ); +DIVS ( R7 , R0 ); +DIVS ( R4 , R0 ); +DIVS ( R0 , R0 ); +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x468ACF12; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x159E26AE; +CHECKREG r5, 0x2CF13579; +CHECKREG r6, 0x4F13579B; +CHECKREG r7, 0x713579BD; +CHECKREG r0, 0x00000002; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R1.L = -1; +DIVS ( R0 , R1 ); +DIVS ( R2 , R1 ); +DIVS ( R3 , R1 ); +DIVS ( R4 , R1 ); +DIVS ( R5 , R1 ); +DIVS ( R6 , R1 ); +DIVS ( R7 , R1 ); +DIVS ( R1 , R1 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x0001FFFF; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x48ACF134; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x8CF13578; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0xD13579BC; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 31; +DIVS ( R0 , R2 ); +DIVS ( R1 , R2 ); +DIVS ( R3 , R2 ); +DIVS ( R4 , R2 ); +DIVS ( R5 , R2 ); +DIVS ( R6 , R2 ); +DIVS ( R7 , R2 ); +DIVS ( R2 , R2 ); +CHECKREG r0, 0xA2460004; +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x0000003E; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x2ACF1357; +CHECKREG r5, 0x0CF13579; +CHECKREG r6, 0xCF13579A; +CHECKREG r7, 0xF13579BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R3.L = -31; +DIVS ( R0 , R3 ); +DIVS ( R1 , R3 ); +DIVS ( R2 , R3 ); +DIVS ( R4 , R3 ); +DIVS ( R5 , R3 ); +DIVS ( R6 , R3 ); +DIVS ( R7 , R3 ); +DIVS ( R3 , R3 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x0468ACF0; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x0001FFC3; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x8CF13578; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0xD13579BC; + +imm32 r0, 0x00000001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R4.L = 15; +DIVS ( R1 , R4 ); +DIVS ( R2 , R4 ); +DIVS ( R3 , R4 ); +DIVS ( R0 , R4 ); +DIVS ( R5 , R4 ); +DIVS ( R6 , R4 ); +DIVS ( R7 , R4 ); +DIVS ( R4 , R4 ); +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x468ACF12; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x0000001E; +CHECKREG r5, 0x2CF13579; +CHECKREG r6, 0x4F13579B; +CHECKREG r7, 0x713579BD; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x00000000; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R5.L = -15; +DIVS ( R0 , R5 ); +DIVS ( R1 , R5 ); +DIVS ( R2 , R5 ); +DIVS ( R3 , R5 ); +DIVS ( R4 , R5 ); +DIVS ( R6 , R5 ); +DIVS ( R7 , R5 ); +DIVS ( R5 , R5 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x48ACF134; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x0001FFE3; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0xD13579BC; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0xb1256790; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R6.L = 24; +DIVS ( R0 , R6 ); +DIVS ( R1 , R6 ); +DIVS ( R2 , R6 ); +DIVS ( R3 , R6 ); +DIVS ( R4 , R6 ); +DIVS ( R5 , R6 ); +DIVS ( R7 , R6 ); +DIVS ( R6 , R6 ); +CHECKREG r0, 0xA2460004; +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x624ACF21; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x2ACF1357; +CHECKREG r5, 0x0CF13579; +CHECKREG r6, 0x00000030; +CHECKREG r7, 0xF13579BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0x00000000; +R7.L = -24; +DIVS ( R0 , R7 ); +DIVS ( R1 , R7 ); +DIVS ( R2 , R7 ); +DIVS ( R3 , R7 ); +DIVS ( R4 , R7 ); +DIVS ( R5 , R7 ); +DIVS ( R6 , R7 ); +DIVS ( R7 , R7 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x0468ACF0; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x48ACF134; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x8CF13578; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0x0001FFD1; + + +pass diff --git a/tests/tcg/bfin/c_alu2op_log_l_sft.s b/tests/tcg/bfin/c_alu2op_log_l_sft.s new file mode 100644 index 0000000000000..06489efb3afa0 --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_log_l_sft.s @@ -0,0 +1,220 @@ +//Original:/proj/frio/dv/testcases/core/c_alu2op_log_l_sft/c_alu2op_log_l_sft.dsp +// Spec Reference: alu2op logical left +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x00000000; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R0.L = 1; + R1 <<= R0; + R2 <<= R0; + R3 <<= R0; + R4 <<= R0; + R5 <<= R0; + R6 <<= R0; + R7 <<= R0; + R4 <<= R0; + R0 <<= R0; + CHECKREG r1, 0x2468ACF0; + CHECKREG r2, 0x468ACF12; + CHECKREG r3, 0x68ACF134; + CHECKREG r4, 0x159E26AC; + CHECKREG r5, 0x2CF13578; + CHECKREG r6, 0x4F13579A; + CHECKREG r7, 0x713579BC; + CHECKREG r0, 0x00000002; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R1.L = -1; + R0 <<= R1; + R2 <<= R1; + R3 <<= R1; + R4 <<= R1; + R5 <<= R1; + R6 <<= R1; + R7 <<= R1; + R1 <<= R1; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0x00000000; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 31; + R0 <<= R2; + R1 <<= R2; + R3 <<= R2; + R4 <<= R2; + R5 <<= R2; + R6 <<= R2; + R7 <<= R2; + R2 <<= R2; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x80000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x80000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x80000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0x00000000; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R3.L = -31; + R0 <<= R3; + R1 <<= R3; + R2 <<= R3; + R4 <<= R3; + R5 <<= R3; + R6 <<= R3; + R7 <<= R3; + R3 <<= R3; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x00000001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x00000000; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4.L = 15; + R1 <<= R4; + R2 <<= R4; + R3 <<= R4; + R0 <<= R4; + R5 <<= R4; + R6 <<= R4; + R7 <<= R4; + R4 <<= R4; + CHECKREG r0, 0x00008000; + CHECKREG r1, 0x2B3C0000; + CHECKREG r2, 0xB3C48000; + CHECKREG r3, 0x3C4D0000; + CHECKREG r4, 0x00078000; + CHECKREG r5, 0x4D5E0000; + CHECKREG r6, 0xD5E68000; + CHECKREG r7, 0x5E6F0000; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0x00000000; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -15; + R0 <<= R5; + R1 <<= R5; + R2 <<= R5; + R3 <<= R5; + R4 <<= R5; + R6 <<= R5; + R7 <<= R5; + R5 <<= R5; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0xb1256790; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x00000000; + imm32 r7, 0x789abcde; + R6.L = 24; + R0 <<= R6; + R1 <<= R6; + R2 <<= R6; + R3 <<= R6; + R4 <<= R6; + R5 <<= R6; + R7 <<= R6; + R6 <<= R6; + CHECKREG r0, 0x02000000; + CHECKREG r1, 0x78000000; + CHECKREG r2, 0x90000000; + CHECKREG r3, 0x9A000000; + CHECKREG r4, 0xAB000000; + CHECKREG r5, 0xBC000000; + CHECKREG r6, 0x18000000; + CHECKREG r7, 0xDE000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0x00000000; + R7.L = -24; + R0 <<= R7; + R1 <<= R7; + R2 <<= R7; + R3 <<= R7; + R4 <<= R7; + R5 <<= R7; + R6 <<= R7; + R7 <<= R7; + CHECKREG r0, 0x00; + CHECKREG r1, 0x00; + CHECKREG r2, 0x00; + CHECKREG r3, 0x00; + CHECKREG r4, 0x00; + CHECKREG r5, 0x00; + CHECKREG r6, 0x00; + CHECKREG r7, 0x00; + + pass diff --git a/tests/tcg/bfin/c_alu2op_log_r_sft.s b/tests/tcg/bfin/c_alu2op_log_r_sft.s new file mode 100644 index 0000000000000..fdb14fc74ff04 --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_log_r_sft.s @@ -0,0 +1,217 @@ +//Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp +// Spec Reference: alu2op logical right +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R0.L = 1; + R1 >>= R0; + R2 >>= R0; + R3 >>= R0; + R4 >>= R0; + R5 >>= R0; + R6 >>= R0; + R7 >>= R0; + R4 >>= R0; + R0 >>= R0; + CHECKREG r1, 0x091A2B3C; + CHECKREG r2, 0x11A2B3C4; + CHECKREG r3, 0x1A2B3C4D; + CHECKREG r4, 0x2159E26A; + CHECKREG r5, 0x4B3C4D5E; + CHECKREG r6, 0x53C4D5E6; + CHECKREG r7, 0x5C4D5E6F; + CHECKREG r0, 0x00000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R1.L = -1; + R0 >>= R1; + R2 >>= R1; + R3 >>= R1; + R4 >>= R1; + R5 >>= R1; + R6 >>= R1; + R7 >>= R1; + R1 >>= R1; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0x00000000; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 31; + R0 >>= R2; + R1 >>= R2; + R3 >>= R2; + R4 >>= R2; + R5 >>= R2; + R6 >>= R2; + R7 >>= R2; + R2 >>= R2; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0x00000001; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0x00000000; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R3.L = -31; + R0 >>= R3; + R1 >>= R3; + R2 >>= R3; + R4 >>= R3; + R5 >>= R3; + R6 >>= R3; + R7 >>= R3; + R3 >>= R3; + CHECKREG r0, 0x00; + CHECKREG r1, 0x0; + CHECKREG r2, 0x0; + CHECKREG r3, 0x0; + CHECKREG r4, 0x0; + CHECKREG r5, 0x0; + CHECKREG r6, 0x0; + CHECKREG r7, 0x0; + + imm32 r0, 0x00000001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x00000000; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4.L = 15; + R1 >>= R4; + R2 >>= R4; + R3 >>= R4; + R0 >>= R4; + R5 >>= R4; + R6 >>= R4; + R7 >>= R4; + R4 >>= R4; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00002468; + CHECKREG r2, 0x0000468A; + CHECKREG r3, 0x000068AC; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00012CF1; + CHECKREG r6, 0x00014F13; + CHECKREG r7, 0x00017135; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0x00000000; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -15; + R0 >>= R5; + R1 >>= R5; + R2 >>= R5; + R3 >>= R5; + R4 >>= R5; + R6 >>= R5; + R7 >>= R5; + R5 >>= R5; + CHECKREG r0, 0x000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x0000; + CHECKREG r3, 0x0000; + CHECKREG r4, 0x0000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x0000; + CHECKREG r7, 0x0000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0xb1256790; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x00000000; + imm32 r7, 0x789abcde; + R6.L = 24; + R0 >>= R6; + R1 >>= R6; + R2 >>= R6; + R3 >>= R6; + R4 >>= R6; + R5 >>= R6; + R7 >>= R6; + R6 >>= R6; + CHECKREG r0, 0x00000051; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x000000B1; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000095; + CHECKREG r5, 0x00000086; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000078; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0x00000000; + R7.L = -24; + R0 >>= R7; + R1 >>= R7; + R2 >>= R7; + R3 >>= R7; + R4 >>= R7; + R5 >>= R7; + R6 >>= R7; + R7 >>= R7; + CHECKREG r0, 0x00; + CHECKREG r1, 0x00; + CHECKREG r2, 0x00; + CHECKREG r3, 0x00; + CHECKREG r4, 0x00; + CHECKREG r5, 0x00; + CHECKREG r6, 0x00; + CHECKREG r7, 0x00; + + pass diff --git a/tests/tcg/bfin/c_alu2op_shadd_1.s b/tests/tcg/bfin/c_alu2op_shadd_1.s new file mode 100644 index 0000000000000..73e39ec16661a --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_shadd_1.s @@ -0,0 +1,209 @@ +//Original:/testcases/core/c_alu2op_shadd_1/c_alu2op_shadd_1.dsp +// Spec Reference: alu2op shadd 1 +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R1 = ( R1 + R0 ) << 1; +R2 = ( R2 + R0 ) << 1; +R3 = ( R3 + R0 ) << 1; +R4 = ( R4 + R0 ) << 1; +R5 = ( R5 + R0 ) << 1; +R6 = ( R6 + R0 ) << 1; +R7 = ( R7 + R0 ) << 1; +R0 = ( R0 + R0 ) << 1; +CHECKREG r0, 0x0D05E640; +CHECKREG r1, 0x2AE5A010; +CHECKREG r2, 0x4D05C232; +CHECKREG r3, 0x6F25E454; +CHECKREG r4, 0x11460676; +CHECKREG r5, 0x33662898; +CHECKREG r6, 0x55864ABA; +CHECKREG r7, 0x77A66CDC; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R1 ) << 1; +R2 = ( R2 + R1 ) << 1; +R3 = ( R3 + R1 ) << 1; +R4 = ( R4 + R1 ) << 1; +R5 = ( R5 + R1 ) << 1; +R6 = ( R6 + R1 ) << 1; +R7 = ( R7 + R1 ) << 1; +R1 = ( R1 + R1 ) << 1; +CHECKREG r0, 0x2AF38A10; +CHECKREG r1, 0x48D149E0; +CHECKREG r2, 0x6AF36A02; +CHECKREG r3, 0x8D158A24; +CHECKREG r4, 0x2F37AA46; +CHECKREG r5, 0x5159CA68; +CHECKREG r6, 0x737BEA8A; +CHECKREG r7, 0x959E0AAC; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R2 ) << 1; +R1 = ( R1 + R2 ) << 1; +R3 = ( R3 + R2 ) << 1; +R4 = ( R4 + R2 ) << 1; +R5 = ( R5 + R2 ) << 1; +R6 = ( R6 + R2 ) << 1; +R7 = ( R7 + R2 ) << 1; +R2 = ( R2 + R2 ) << 1; +CHECKREG r0, 0x4D15C0D2; +CHECKREG r1, 0x6AF37AE2; +CHECKREG r2, 0x8D159CE4; +CHECKREG r3, 0xAF37BEE6; +CHECKREG r4, 0x5159E0E8; +CHECKREG r5, 0x737C02EA; +CHECKREG r6, 0x959E24EC; +CHECKREG r7, 0xB7C046EE; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R3 ) << 1; +R1 = ( R1 + R3 ) << 1; +R2 = ( R2 + R3 ) << 1; +R4 = ( R4 + R3 ) << 1; +R5 = ( R5 + R3 ) << 1; +R6 = ( R6 + R3 ) << 1; +R7 = ( R7 + R3 ) << 1; +R3 = ( R3 + R3 ) << 1; +CHECKREG r0, 0x7137E454; +CHECKREG r1, 0x91159E24; +CHECKREG r2, 0xB137C046; +CHECKREG r3, 0xD159E268; +CHECKREG r4, 0x717C048A; +CHECKREG r5, 0x919E26AC; +CHECKREG r6, 0xB1C048CE; +CHECKREG r7, 0xD1E26AF0; + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R0 = ( R0 + R4 ) << 1; +R1 = ( R1 + R4 ) << 1; +R2 = ( R2 + R4 ) << 1; +R3 = ( R3 + R4 ) << 1; +R5 = ( R5 + R4 ) << 1; +R6 = ( R6 + R4 ) << 1; +R7 = ( R7 + R4 ) << 1; +R4 = ( R4 + R4 ) << 1; +CHECKREG r0, 0x11460676; +CHECKREG r1, 0x2F25C046; +CHECKREG r2, 0x5145E268; +CHECKREG r3, 0x7366048A; +CHECKREG r4, 0x158626AC; +CHECKREG r5, 0x37A648CE; +CHECKREG r6, 0x59C66AF0; +CHECKREG r7, 0x7BE68D12; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R5 ) << 1; +R1 = ( R1 + R5 ) << 1; +R2 = ( R2 + R5 ) << 1; +R3 = ( R3 + R5 ) << 1; +R4 = ( R4 + R5 ) << 1; +R6 = ( R6 + R5 ) << 1; +R7 = ( R7 + R5 ) << 1; +R5 = ( R5 + R5 ) << 1; +CHECKREG r0, 0x337C0A98; +CHECKREG r1, 0x5159CA68; +CHECKREG r2, 0x737BEA8A; +CHECKREG r3, 0x959E0AAC; +CHECKREG r4, 0x37C02ACE; +CHECKREG r5, 0x59E24AF0; +CHECKREG r6, 0x7C046B12; +CHECKREG r7, 0x9E268B34; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R6 ) << 1; +R1 = ( R1 + R6 ) << 1; +R2 = ( R2 + R6 ) << 1; +R3 = ( R3 + R6 ) << 1; +R4 = ( R4 + R6 ) << 1; +R5 = ( R5 + R6 ) << 1; +R7 = ( R7 + R6 ) << 1; +R6 = ( R6 + R6 ) << 1; +CHECKREG r0, 0x559E48DA; +CHECKREG r1, 0x737C02EA; +CHECKREG r2, 0x959E24EC; +CHECKREG r3, 0xB7C046EE; +CHECKREG r4, 0x59E268F0; +CHECKREG r5, 0x7C048AF2; +CHECKREG r6, 0x9E26ACF4; +CHECKREG r7, 0xC048CEF6; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R7 ) << 1; +R1 = ( R1 + R7 ) << 1; +R2 = ( R2 + R7 ) << 1; +R3 = ( R3 + R7 ) << 1; +R4 = ( R4 + R7 ) << 1; +R5 = ( R5 + R7 ) << 1; +R6 = ( R6 + R7 ) << 1; +R7 = ( R7 + R7 ) << 1; +CHECKREG r0, 0x71C06CDC; +CHECKREG r1, 0x919E26AC; +CHECKREG r2, 0xB1C048CE; +CHECKREG r3, 0xD1E26AF0; +CHECKREG r4, 0x72048D12; +CHECKREG r5, 0x9226AF34; +CHECKREG r6, 0xB248D156; +CHECKREG r7, 0xD26AF378; +pass diff --git a/tests/tcg/bfin/c_alu2op_shadd_2.s b/tests/tcg/bfin/c_alu2op_shadd_2.s new file mode 100644 index 0000000000000..b9812f43e6980 --- /dev/null +++ b/tests/tcg/bfin/c_alu2op_shadd_2.s @@ -0,0 +1,209 @@ +//Original:/testcases/core/c_alu2op_shadd_2/c_alu2op_shadd_2.dsp +// Spec Reference: alu2op shadd 2 +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R1 = ( R1 + R0 ) << 2; +R2 = ( R2 + R0 ) << 2; +R3 = ( R3 + R0 ) << 2; +R4 = ( R4 + R0 ) << 2; +R5 = ( R5 + R0 ) << 2; +R6 = ( R6 + R0 ) << 2; +R7 = ( R7 + R0 ) << 2; +R0 = ( R0 + R0 ) << 2; +CHECKREG r0, 0x1A0BCC80; +CHECKREG r1, 0x55CB4020; +CHECKREG r2, 0x9A0B8464; +CHECKREG r3, 0xDE4BC8A8; +CHECKREG r4, 0x228C0CEC; +CHECKREG r5, 0x66CC5130; +CHECKREG r6, 0xAB0C9574; +CHECKREG r7, 0xEF4CD9B8; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R1 ) << 2; +R2 = ( R2 + R1 ) << 2; +R3 = ( R3 + R1 ) << 2; +R4 = ( R4 + R1 ) << 2; +R5 = ( R5 + R1 ) << 2; +R6 = ( R6 + R1 ) << 2; +R7 = ( R7 + R1 ) << 2; +R1 = ( R1 + R1 ) << 2; +CHECKREG r0, 0x55E71420; +CHECKREG r1, 0x91A293C0; +CHECKREG r2, 0xD5E6D404; +CHECKREG r3, 0x1A2B1448; +CHECKREG r4, 0x5E6F548C; +CHECKREG r5, 0xA2B394D0; +CHECKREG r6, 0xE6F7D514; +CHECKREG r7, 0x2B3C1558; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R2 ) << 2; +R1 = ( R1 + R2 ) << 2; +R3 = ( R3 + R2 ) << 2; +R4 = ( R4 + R2 ) << 2; +R5 = ( R5 + R2 ) << 2; +R6 = ( R6 + R2 ) << 2; +R7 = ( R7 + R2 ) << 2; +R2 = ( R2 + R2 ) << 2; +CHECKREG r0, 0x9A2B81A4; +CHECKREG r1, 0xD5E6F5C4; +CHECKREG r2, 0x1A2B39C8; +CHECKREG r3, 0x5E6F7DCC; +CHECKREG r4, 0xA2B3C1D0; +CHECKREG r5, 0xE6F805D4; +CHECKREG r6, 0x2B3C49D8; +CHECKREG r7, 0x6F808DDC; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R3 ) << 2; +R1 = ( R1 + R3 ) << 2; +R2 = ( R2 + R3 ) << 2; +R4 = ( R4 + R3 ) << 2; +R5 = ( R5 + R3 ) << 2; +R6 = ( R6 + R3 ) << 2; +R7 = ( R7 + R3 ) << 2; +R3 = ( R3 + R3 ) << 2; +CHECKREG r0, 0xE26FC8A8; +CHECKREG r1, 0x222B3C48; +CHECKREG r2, 0x626F808C; +CHECKREG r3, 0xA2B3C4D0; +CHECKREG r4, 0xE2F80914; +CHECKREG r5, 0x233C4D58; +CHECKREG r6, 0x6380919C; +CHECKREG r7, 0xA3C4D5E0; + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R0 = ( R0 + R4 ) << 2; +R1 = ( R1 + R4 ) << 2; +R2 = ( R2 + R4 ) << 2; +R3 = ( R3 + R4 ) << 2; +R5 = ( R5 + R4 ) << 2; +R6 = ( R6 + R4 ) << 2; +R7 = ( R7 + R4 ) << 2; +R4 = ( R4 + R4 ) << 2; +CHECKREG r0, 0x228C0CEC; +CHECKREG r1, 0x5E4B808C; +CHECKREG r2, 0xA28BC4D0; +CHECKREG r3, 0xE6CC0914; +CHECKREG r4, 0x2B0C4D58; +CHECKREG r5, 0x6F4C919C; +CHECKREG r6, 0xB38CD5E0; +CHECKREG r7, 0xF7CD1A24; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R5 ) << 2; +R1 = ( R1 + R5 ) << 2; +R2 = ( R2 + R5 ) << 2; +R3 = ( R3 + R5 ) << 2; +R4 = ( R4 + R5 ) << 2; +R6 = ( R6 + R5 ) << 2; +R7 = ( R7 + R5 ) << 2; +R5 = ( R5 + R5 ) << 2; +CHECKREG r0, 0x66F81530; +CHECKREG r1, 0xA2B394D0; +CHECKREG r2, 0xE6F7D514; +CHECKREG r3, 0x2B3C1558; +CHECKREG r4, 0x6F80559C; +CHECKREG r5, 0xB3C495E0; +CHECKREG r6, 0xF808D624; +CHECKREG r7, 0x3C4D1668; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R6 ) << 2; +R1 = ( R1 + R6 ) << 2; +R2 = ( R2 + R6 ) << 2; +R3 = ( R3 + R6 ) << 2; +R4 = ( R4 + R6 ) << 2; +R5 = ( R5 + R6 ) << 2; +R7 = ( R7 + R6 ) << 2; +R6 = ( R6 + R6 ) << 2; +CHECKREG r0, 0xAB3C91B4; +CHECKREG r1, 0xE6F805D4; +CHECKREG r2, 0x2B3C49D8; +CHECKREG r3, 0x6F808DDC; +CHECKREG r4, 0xB3C4D1E0; +CHECKREG r5, 0xF80915E4; +CHECKREG r6, 0x3C4D59E8; +CHECKREG r7, 0x80919DEC; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R7 ) << 2; +R1 = ( R1 + R7 ) << 2; +R2 = ( R2 + R7 ) << 2; +R3 = ( R3 + R7 ) << 2; +R4 = ( R4 + R7 ) << 2; +R5 = ( R5 + R7 ) << 2; +R6 = ( R6 + R7 ) << 2; +R7 = ( R7 + R7 ) << 2; +CHECKREG r0, 0xE380D9B8; +CHECKREG r1, 0x233C4D58; +CHECKREG r2, 0x6380919C; +CHECKREG r3, 0xA3C4D5E0; +CHECKREG r4, 0xE4091A24; +CHECKREG r5, 0x244D5E68; +CHECKREG r6, 0x6491A2AC; +CHECKREG r7, 0xA4D5E6F0; +pass diff --git a/tests/tcg/bfin/c_br_preg_killed_ac.s b/tests/tcg/bfin/c_br_preg_killed_ac.s new file mode 100644 index 0000000000000..67a5bdc87c5b5 --- /dev/null +++ b/tests/tcg/bfin/c_br_preg_killed_ac.s @@ -0,0 +1,82 @@ +//Original:/testcases/seq/c_br_preg_killed_ac/c_br_preg_killed_ac.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; + + P4 = 4; + P2 = 2; + loadsym P5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + IF !CC JUMP LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + JUMP ( PC + P4 ); //brf LABEL2; // (bp); + CC = ! CC; +LABEL2: + JUMP ( PC + P4 ); //brf LABEL3; // (bp); + R2 = - R2; // ALU2op killed +LABEL3: + JUMP ( PC + P4 ); //brf LABEL4; + R3 <<= 2; // LOGI2op killed +LABEL4: + JUMP ( PC + P4 ); //brf LABEL5; + R0 = R1 + R2; // COMP3op killed +LABEL5: + JUMP ( PC + P4 ); //brf LABEL6; + R4 += 3; // COMPI2opD killed +LABEL6: + JUMP ( PC + P4 ); //brf LABEL7; // (bp); + R5 = 25; // LDIMMHALF killed +LABEL7: + JUMP ( PC + P4 ); //brf LABEL8; + R6 = CC; // CC2REG killed +LABEL8: + JUMP ( PC + P4 ); //brf LABEL9; + JUMP ( PC + P2 ); //BAD1; // UJUMP killed +LABEL9: + JUMP ( PC + P4 ); //brf LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/tests/tcg/bfin/c_br_preg_killed_ex1.s b/tests/tcg/bfin/c_br_preg_killed_ex1.s new file mode 100644 index 0000000000000..7a18f53dd7129 --- /dev/null +++ b/tests/tcg/bfin/c_br_preg_killed_ex1.s @@ -0,0 +1,85 @@ +//Original:/testcases/seq/c_br_preg_killed_ex1/c_br_preg_killed_ex1.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + P2 = 4; + loadsym p5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + IF !CC JUMP LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + JUMP ( PC + P2 ); //brf LABEL2; // (bp); + CC = ! CC; +LABEL2: + IF !CC JUMP LABEL3; // (bp); + R2 = - R2; // ALU2op killed +LABEL3: + IF !CC JUMP LABEL4; + R3 <<= 2; // LOGI2op killed +LABEL4: + IF !CC JUMP LABEL5; + R0 = R1 + R2; // COMP3op killed +LABEL5: + IF !CC JUMP LABEL6; + R4 += 3; // COMPI2opD killed +LABEL6: + IF !CC JUMP LABEL7; // (bp); + R5 = 25; // LDIMMHALF killed +LABEL7: + IF !CC JUMP LABEL8; + R6 = CC; // CC2REG killed +LABEL8: + IF !CC JUMP LABEL9; + JUMP.S BAD1; // UJUMP killed +LABEL9: + IF !CC JUMP LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/tests/tcg/bfin/c_br_preg_stall_ac.s b/tests/tcg/bfin/c_br_preg_stall_ac.s new file mode 100644 index 0000000000000..7ac29e64554d5 --- /dev/null +++ b/tests/tcg/bfin/c_br_preg_stall_ac.s @@ -0,0 +1,75 @@ +//Original:/testcases/seq/c_br_preg_stall_ac/c_br_preg_stall_ac.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + /* This test likes to assume the current [SP] is valid */ + SP += -12; + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST; + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + P1 = 4; + P2 = 6; + loadsym P5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + R0 = CC; + IF CC R1 = R0; + [ SP ] = P2; + P2 = [ SP ]; + JUMP ( PC + P2 ); //brf LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1' + CC = ! CC; +LABEL2: + JUMP ( PC + P1 ); //brf LABEL3; + JUMP ( PC + P2 ); //BAD1; // UJUMP killed +LABEL3: + JUMP ( PC + P1 ); //brf LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/tests/tcg/bfin/c_br_preg_stall_ex1.s b/tests/tcg/bfin/c_br_preg_stall_ex1.s new file mode 100644 index 0000000000000..5310edf0e6b0c --- /dev/null +++ b/tests/tcg/bfin/c_br_preg_stall_ex1.s @@ -0,0 +1,70 @@ +//Original:/testcases/seq/c_br_preg_stall_ex1/c_br_preg_stall_ex1.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + P1 = 4; + P2 = 6; + loadsym p5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + R0 = CC; + IF CC R1 = R0; + IF !CC JUMP LABEL1; + R0 = LC0; + R2 = R1 + R0; +LABEL1: + JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1' + CC = ! CC; +LABEL2: + JUMP ( PC + P1 ); //brf LABEL3; + JUMP ( PC + P2 ); //BAD1; // UJUMP killed +LABEL3: + JUMP ( PC + P1 ); //brf LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/tests/tcg/bfin/c_brcc_bp1.s b/tests/tcg/bfin/c_brcc_bp1.s new file mode 100644 index 0000000000000..012d1a5db6806 --- /dev/null +++ b/tests/tcg/bfin/c_brcc_bp1.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_bp1/c_brcc_bp1.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1; // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_brcc_bp2.s b/tests/tcg/bfin/c_brcc_bp2.s new file mode 100644 index 0000000000000..1fc7278f719bc --- /dev/null +++ b/tests/tcg/bfin/c_brcc_bp2.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_bp2/c_brcc_bp2.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_brcc_bp3.s b/tests/tcg/bfin/c_brcc_bp3.s new file mode 100644 index 0000000000000..0a21994505e4d --- /dev/null +++ b/tests/tcg/bfin/c_brcc_bp3.s @@ -0,0 +1,47 @@ +//Original:/testcases/core/c_brcc_bp3/c_brcc_bp3.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_brcc_bp4.s b/tests/tcg/bfin/c_brcc_bp4.s new file mode 100644 index 0000000000000..39f64b141d554 --- /dev/null +++ b/tests/tcg/bfin/c_brcc_bp4.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_bp4/c_brcc_bp4.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2 (BP); // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_brcc_brf_bp.s b/tests/tcg/bfin/c_brcc_brf_bp.s new file mode 100644 index 0000000000000..7ca29c51326f7 --- /dev/null +++ b/tests/tcg/bfin/c_brcc_brf_bp.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brf_bp/c_brcc_brf_bp.dsp +// Spec Reference: brcc brf bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + IF !CC JUMP good1 (BP); // branch on false (should branch) + CC = ! CC; // set cc=1 + R1 = 1; // if go here, error +good1: IF !CC JUMP good2 (BP); // branch on false (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF !CC JUMP bad2 (BP); // branch on false (should not branch) + CC = ! CC; + IF !CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF !CC JUMP end; // branch on true (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_brcc_brf_brt_bp.s b/tests/tcg/bfin/c_brcc_brf_brt_bp.s new file mode 100644 index 0000000000000..c9f2945171673 --- /dev/null +++ b/tests/tcg/bfin/c_brcc_brf_brt_bp.s @@ -0,0 +1,47 @@ +//Original:/testcases/core/c_brcc_brf_brt_bp/c_brcc_brf_brt_bp.dsp +// Spec Reference: brcc brfbrt +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000444; +imm32 r5, 0x00000555; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = R4 < R5; + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + CC = ! CC; + IF !CC JUMP good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF !CC JUMP bad2 (BP); // branch on true (should not branch) + IF CC JUMP end; // we're done +bad2: R0 = 8; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000444; +CHECKREG r5, 0x00000555; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_brcc_brf_brt_nbp.s b/tests/tcg/bfin/c_brcc_brf_brt_nbp.s new file mode 100644 index 0000000000000..32b3bd045370a --- /dev/null +++ b/tests/tcg/bfin/c_brcc_brf_brt_nbp.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brf_brt_nbp/c_brcc_brf_brt_nbp.dsp +// Spec Reference: brcc brf brt no bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1; // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1; // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_brcc_brf_fbkwd.s b/tests/tcg/bfin/c_brcc_brf_fbkwd.s new file mode 100644 index 0000000000000..371238c61cbce --- /dev/null +++ b/tests/tcg/bfin/c_brcc_brf_fbkwd.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brf_fbkwd/c_brcc_brf_fbkwd.dsp +// Spec Reference: brcc brf forward/backward +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +ASTAT = R0; + +IF !CC JUMP SUBR; + R1.L = 0xeeee; + R2.L = 0x2222; + R3.L = 0x3333; +JBACK: + R4.L = 0x4444; + + + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass + +//.code 0x448 +SUBR: + R1.L = 0x1111; +IF !CC JUMP JBACK; diff --git a/tests/tcg/bfin/c_brcc_brf_nbp.s b/tests/tcg/bfin/c_brcc_brf_nbp.s new file mode 100644 index 0000000000000..52eb0f3c39428 --- /dev/null +++ b/tests/tcg/bfin/c_brcc_brf_nbp.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_brf_nbp/c_brcc_brf_nbp.dsp +// Spec Reference: brcc brf no bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + IF !CC JUMP good1; // branch on false (should branch) + CC = ! CC; // set cc=1 + R1 = 1; // if go here, error +good1: IF !CC JUMP good2; // branch on false (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF !CC JUMP bad2; // branch on false (should not branch) + CC = ! CC; + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF !CC JUMP end; // branch on true (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_brcc_brt_bp.s b/tests/tcg/bfin/c_brcc_brt_bp.s new file mode 100644 index 0000000000000..d3ad0fc5ac905 --- /dev/null +++ b/tests/tcg/bfin/c_brcc_brt_bp.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brt_bp/c_brcc_brt_bp.dsp +// Spec Reference: brcc brt bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // (should branch) + R1 = 1; // if go here, error +good1: IF CC JUMP good2 (BP); // (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF CC JUMP bad2 (BP); // (should not branch) + CC = ! CC; + IF CC JUMP good3 (BP); // (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP end (BP); // (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_brcc_brt_nbp.s b/tests/tcg/bfin/c_brcc_brt_nbp.s new file mode 100644 index 0000000000000..a1c5e6bce7fc1 --- /dev/null +++ b/tests/tcg/bfin/c_brcc_brt_nbp.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_brt_nbp/c_brcc_brt_nbp.dsp +// Spec Reference: brcc brt no bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1; // (should branch) + R1 = 1; // if go here, error +good1: IF CC JUMP good2; // (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF CC JUMP bad2; // (should not branch) + CC = ! CC; + IF CC JUMP good3; // (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP end; // (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_calla_ljump.s b/tests/tcg/bfin/c_calla_ljump.s new file mode 100644 index 0000000000000..be1e94f9c69d1 --- /dev/null +++ b/tests/tcg/bfin/c_calla_ljump.s @@ -0,0 +1,31 @@ +//Original:/testcases/core/c_calla_ljump/c_calla_ljump.dsp +// Spec Reference: progctrl calla ljump +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +JUMP.L SUBR; + +JBACK: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass + +SUBR: // should jump here + R1.L = 0x1111; + JUMP.L JBACK; + R2.L = 0x2222; // should not go here + JUMP.L JBACK; +RTS; diff --git a/tests/tcg/bfin/c_calla_subr.s b/tests/tcg/bfin/c_calla_subr.s new file mode 100644 index 0000000000000..8c651da6a3989 --- /dev/null +++ b/tests/tcg/bfin/c_calla_subr.s @@ -0,0 +1,28 @@ +//Original:/testcases/core/c_calla_subr/c_calla_subr.dsp +// Spec Reference: progctrl calla subr +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +CALL SUBR; + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass + +SUBR: // should jump here + R1.L = 0x1111; + RTS; + R2.L = 0x2222; // should not go here + RTS; diff --git a/tests/tcg/bfin/c_cc2dreg.s b/tests/tcg/bfin/c_cc2dreg.s new file mode 100644 index 0000000000000..38aab854e5c12 --- /dev/null +++ b/tests/tcg/bfin/c_cc2dreg.s @@ -0,0 +1,56 @@ +//Original:/testcases/core/c_cc2dreg/c_cc2dreg.dsp +// Spec Reference: cc2dreg +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00120000; +imm32 r2, 0x00000003; +imm32 r3, 0x00000004; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R0; + +CC = R1; +R1 = CC; +CC = R1; +CC = ! CC; +R2 = CC; +CC = R2; +CC = ! CC; +R3 = CC; +CC = R3; +CC = ! CC; +R4 = CC; +CC = R5; +R5 = CC; +CC = R6; +R6 = CC; +CC = ! CC; +R7 = CC; +R0 = CC; + + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + + + +pass diff --git a/tests/tcg/bfin/c_cc2stat_cc_ac.S b/tests/tcg/bfin/c_cc2stat_cc_ac.S new file mode 100644 index 0000000000000..964f82ae4396e --- /dev/null +++ b/tests/tcg/bfin/c_cc2stat_cc_ac.S @@ -0,0 +1,240 @@ +//Original:/testcases/core/c_cc2stat_cc_ac/c_cc2stat_cc_ac.dsp +// Spec Reference: cc2stat cc ac +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + imm32 r0, _UNSET; + imm32 r1, _UNSET; + imm32 r2, _UNSET; + imm32 r3, _UNSET; + imm32 r4, _UNSET; + imm32 r5, _UNSET; + imm32 r6, _UNSET; + imm32 r7, _UNSET; + +// test CC = AC 0-0, 0-1, 1-0, 1-1 + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC = AC0; // + R0 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC = AC0; // + R1 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + CC = AC0; // + R2 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC = AC0; // + R3 = CC; // + +// test cc |= AC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC |= AC0; // + R4 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC |= AC0; // + R5 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 0 + CC |= AC0; // + R6 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC |= AC0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _SET; + +// test CC &= AC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC &= AC0; // + R4 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC &= AC0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + CC &= AC0; // + R6 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC &= AC0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _SET; + +// test CC ^= AC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC ^= AC0; // + R4 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC ^= AC0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + CC ^= AC0; // + R6 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC ^= AC0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _UNSET; + +// test AC0 = CC 0-0, 0-1, 1-0, 1-1 + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 = CC; // + R0 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 = CC; // + R1 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 = CC; // + R2 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 = CC; // + R3 = ASTAT; // + +// test AC0 |= CC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 |= CC; // + R4 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 |= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 |= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 |= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_AC0|_CC); + CHECKREG r3, (_CC|_AC0); + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0); + CHECKREG r6, (_AC0|_CC); + CHECKREG r7, (_CC|_AC0); + +// test AC0 &= CC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 &= CC; // + R4 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 &= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 &= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 &= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AC0); + CHECKREG r3, (_CC|_AC0); + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _CC; + CHECKREG r7, (_CC|_AC0); + +// test AC0 ^= CC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 ^= CC; // + R4 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 ^= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 ^= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 ^= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AC0); + CHECKREG r3, (_CC|_AC0); + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0); + CHECKREG r6, (_CC|_AC0); + CHECKREG r7, _CC; + + pass diff --git a/tests/tcg/bfin/c_cc2stat_cc_an.s b/tests/tcg/bfin/c_cc2stat_cc_an.s new file mode 100644 index 0000000000000..d93024f9d0843 --- /dev/null +++ b/tests/tcg/bfin/c_cc2stat_cc_an.s @@ -0,0 +1,243 @@ +//Original:/testcases/core/c_cc2stat_cc_an/c_cc2stat_cc_an.dsp +// Spec Reference: cc2stat cc an +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// test CC = AN 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC = AN; // +R0 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC = AN; // +R1 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +CC = AN; // +R2 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC = AN; // +R3 = CC; // + +// test cc |= AN (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC |= AN; // +R4 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC |= AN; // +R5 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 0 +CC |= AN; // +R6 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC |= AN; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +// test CC &= AN (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC &= AN; // +R4 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC &= AN; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +CC &= AN; // +R6 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC &= AN; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +// test CC ^= AN (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC ^= AN; // +R4 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC ^= AN; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +CC ^= AN; // +R6 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC ^= AN; // +R7 = CC; // + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// test AN = CC 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN = CC; // +R0 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN = CC; // +R1 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN = CC; // +R2 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN = CC; // +R3 = ASTAT; // + +// test AN |= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN |= CC; // +R4 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN |= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN |= CC; // +R6 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN |= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// test AN &= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN &= CC; // +R4 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN &= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN &= CC; // +R6 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN &= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000022; + +// test AN ^= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN ^= CC; // +R4 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN ^= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN ^= CC; // +R6 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN ^= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000020; + + +pass diff --git a/tests/tcg/bfin/c_cc2stat_cc_aq.s b/tests/tcg/bfin/c_cc2stat_cc_aq.s new file mode 100644 index 0000000000000..e8b877ebe0602 --- /dev/null +++ b/tests/tcg/bfin/c_cc2stat_cc_aq.s @@ -0,0 +1,243 @@ +//Original:/testcases/core/c_cc2stat_cc_aq/c_cc2stat_cc_aq.dsp +// Spec Reference: cc2stat cc aq +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// test CC = AQ 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC = AQ; // +R0 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC = AQ; // +R1 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC = AQ; // +R2 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC = AQ; // +R3 = CC; // + +// test cc |= AQ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC |= AQ; // +R4 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC |= AQ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC |= AQ; // +R6 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC |= AQ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +// test CC &= AQ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC &= AQ; // +R4 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC &= AQ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC &= AQ; // +R6 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC &= AQ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +// test CC ^= AQ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC ^= AQ; // +R4 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC ^= AQ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC ^= AQ; // +R6 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC ^= AQ; // +R7 = CC; // + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// test AQ = CC 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ = CC; // +R0 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ = CC; // +R1 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ = CC; // +R2 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ = CC; // +R3 = ASTAT; // + +// test AQ |= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ |= CC; // +R4 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ |= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ |= CC; // +R6 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ |= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000040; +CHECKREG r6, 0x00000060; +CHECKREG r7, 0x00000060; + +// test AQ &= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ &= CC; // +R4 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ &= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ &= CC; // +R6 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ &= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000060; + +// test AQ ^= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ ^= CC; // +R4 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ ^= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ ^= CC; // +R6 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ ^= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000040; +CHECKREG r6, 0x00000060; +CHECKREG r7, 0x00000020; + + +pass diff --git a/tests/tcg/bfin/c_cc2stat_cc_av0.S b/tests/tcg/bfin/c_cc2stat_cc_av0.S new file mode 100644 index 0000000000000..c600902f5d31b --- /dev/null +++ b/tests/tcg/bfin/c_cc2stat_cc_av0.S @@ -0,0 +1,241 @@ +//Original:/testcases/core/c_cc2stat_cc_av0/c_cc2stat_cc_av0.dsp +// Spec Reference: cc2stat cc av0 +# mach: bfin + +#include "test.h" + .include "testutils.inc" + + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000000; + imm32 r2, 0x00000000; + imm32 r3, 0x00000000; + imm32 r4, 0x00000000; + imm32 r5, 0x00000000; + imm32 r6, 0x00000000; + imm32 r7, 0x00000000; + +// test CC = AV0 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC = AV0; // + R0 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC = AV0; // + R1 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + CC = AV0; // + R2 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC = AV0; // + R3 = CC; // + +// test cc |= AV0 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC |= AV0; // + R4 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC |= AV0; // + R5 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 0 + CC |= AV0; // + R6 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC |= AV0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _SET; + +// test CC &= AV0 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC &= AV0; // + R4 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC &= AV0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + CC &= AV0; // + R6 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC &= AV0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _SET; + +// test CC ^= AV0 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC ^= AV0; // + R4 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC ^= AV0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + CC ^= AV0; // + R6 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC ^= AV0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _UNSET; + +// test AV0 = CC 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 = CC; // + R0 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 = CC; // + R1 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 = CC; // + R2 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 = CC; // + R3 = ASTAT; // + +// test AV0 |= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 |= CC; // + R4 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 |= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 |= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 |= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV0); + CHECKREG r3, (_CC|_AV0); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV0; + CHECKREG r6, (_CC|_AV0); + CHECKREG r7, (_CC|_AV0); + +// test AV0 &= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 &= CC; // + R4 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 &= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 &= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 &= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV0); + CHECKREG r3, (_CC|_AV0); + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, (_CC); + CHECKREG r7, (_CC|_AV0); + +// test AV0 ^= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 ^= CC; // + R4 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 ^= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 ^= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 ^= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV0); + CHECKREG r3, (_CC|_AV0); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV0; + CHECKREG r6, (_CC|_AV0); + CHECKREG r7, _CC; + + pass diff --git a/tests/tcg/bfin/c_cc2stat_cc_av1.S b/tests/tcg/bfin/c_cc2stat_cc_av1.S new file mode 100644 index 0000000000000..28550856cf5fa --- /dev/null +++ b/tests/tcg/bfin/c_cc2stat_cc_av1.S @@ -0,0 +1,240 @@ +//Original:/testcases/core/c_cc2stat_cc_av1/c_cc2stat_cc_av1.dsp +// Spec Reference: cc2stat cc av1 +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000000; + imm32 r2, 0x00000000; + imm32 r3, 0x00000000; + imm32 r4, 0x00000000; + imm32 r5, 0x00000000; + imm32 r6, 0x00000000; + imm32 r7, 0x00000000; + +// test CC = AV1 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC = AV1; // + R0 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC = AV1; // + R1 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC = AV1; // + R2 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC = AV1; // + R3 = CC; // + +// test cc |= AV1 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC |= AV1; // + R4 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC |= AV1; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC |= AV1; // + R6 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC |= AV1; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _SET; + +// test CC &= AV1 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC &= AV1; // + R4 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC &= AV1; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC &= AV1; // + R6 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC &= AV1; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _SET; + +// test CC ^= AV1 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC ^= AV1; // + R4 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC ^= AV1; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC ^= AV1; // + R6 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC ^= AV1; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _UNSET; + +// test AV1 = CC 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 = CC; // + R0 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 = CC; // + R1 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 = CC; // + R2 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 = CC; // + R3 = ASTAT; // + +// test AV1 |= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 |= CC; // + R4 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 |= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 |= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 |= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV1); + CHECKREG r3, (_CC|_AV1); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV1; + CHECKREG r6, (_CC|_AV1); + CHECKREG r7, (_CC|_AV1); + +// test AV1 &= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 &= CC; // + R4 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 &= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 &= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 &= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV1); + CHECKREG r3, (_CC|_AV1); + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _CC; + CHECKREG r7, (_CC|_AV1); + +// test AV1 ^= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 ^= CC; // + R4 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 ^= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 ^= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 ^= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV1); + CHECKREG r3, (_CC|_AV1); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV1; + CHECKREG r6, (_CC|_AV1); + CHECKREG r7, _CC; + + pass diff --git a/tests/tcg/bfin/c_cc2stat_cc_az.s b/tests/tcg/bfin/c_cc2stat_cc_az.s new file mode 100644 index 0000000000000..0d8b05bc57e28 --- /dev/null +++ b/tests/tcg/bfin/c_cc2stat_cc_az.s @@ -0,0 +1,243 @@ +//Original:/testcases/core/c_cc2stat_cc_az/c_cc2stat_cc_az.dsp +// Spec Reference: cc2stat cc az +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// test CC = AZ 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC = AZ; // +R0 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC = AZ; // +R1 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC = AZ; // +R2 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC = AZ; // +R3 = CC; // + +// test cc |= AZ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC |= AZ; // +R4 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC |= AZ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC |= AZ; // +R6 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC |= AZ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +// test CC &= AZ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC &= AZ; // +R4 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC &= AZ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC &= AZ; // +R6 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC &= AZ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +// test CC ^= AZ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC ^= AZ; // +R4 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC ^= AZ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC ^= AZ; // +R6 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC ^= AZ; // +R7 = CC; // + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// test AZ = CC 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ = CC; // +R0 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ = CC; // +R1 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ = CC; // +R2 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ = CC; // +R3 = ASTAT; // + +// test AZ |= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ |= CC; // +R4 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ |= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ |= CC; // +R6 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ |= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000021; +CHECKREG r7, 0x00000021; + +// test AZ &= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ &= CC; // +R4 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ &= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ &= CC; // +R6 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ &= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000021; + +// test AZ ^= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ ^= CC; // +R4 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ ^= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ ^= CC; // +R6 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ ^= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000021; +CHECKREG r7, 0x00000020; + + +pass diff --git a/tests/tcg/bfin/c_cc_flag_ccmv_depend.S b/tests/tcg/bfin/c_cc_flag_ccmv_depend.S new file mode 100644 index 0000000000000..bacedfc7ebea7 --- /dev/null +++ b/tests/tcg/bfin/c_cc_flag_ccmv_depend.S @@ -0,0 +1,82 @@ +//Original:/proj/frio/dv/testcases/core/c_cc_flag_ccmv_depend/c_cc_flag_ccmv_depend.dsp +// Spec Reference: ccflag followed by ccmv (# stalls) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + imm32 r0, 0xa08d2311; + imm32 r1, 0x10120040; + imm32 r2, 0x62b61557; + imm32 r3, 0x07300007; + imm32 r4, 0x00740088; + imm32 r5, 0x609950aa; + imm32 r6, 0x20bb06cc; + imm32 r7, 0xd90e108f; + + imm32 p1, 0x1401101f; + imm32 p2, 0x3204108e; + imm32 fp, 0xd93f1084; + imm32 p4, 0xeb04106f; + imm32 p5, 0xa90e5089; + + CC = R7; // cc2dreg + IF CC R0 = R3; // ccmov + R6 = R0 + R4; + + CC = ! CC; // cc2dreg + IF CC R1 = P1; // ccmov + + CC = R5 < R1; // ccflag + R1 = ASTAT; + IF !CC R2 = R5; // ccmov + + CC = R2 == R3; // ccflag + IF CC P1 = R4; // ccmov + + CC = ! CC; + CC = R7 < R5; + IF CC P2 = P5; // ccmov + + CC = P5 == 3; + IF CC FP = R2; // ccmov + +pass + + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair + + CC = A0 == A1; + IF !CC R3 = R6; // ccmov + R7 = R3 + R2; + + A0 += A1 (W32); // dsp32alu a0 + a1 + CC = A0 < A1; + IF CC R4 = P4; // ccmov + R6 = R4; + + R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac + CC = A0 <= A1; + IF CC R5 = P5; // ccmov + + A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + CC = A0 <= A1; + IF CC P5 = R6; // ccmov + + CHECKREG r0, 0x07300007; + CHECKREG r1, (_AC0|_AC0_COPY); + CHECKREG r2, 0x00766960; + CHECKREG r3, 0x07A4008F; + CHECKREG r4, 0xEB04106F; + CHECKREG r5, 0xA90E5089; + CHECKREG r6, 0xEB04106F; + CHECKREG r7, 0x075D69EF; + CHECKREG p1, 0x1401101F; + CHECKREG p2, 0xA90E5089; + CHECKREG fp, 0xD93F1084; + CHECKREG p4, 0xEB04106F; + CHECKREG p5, 0xA90E5089; + + pass diff --git a/tests/tcg/bfin/c_cc_flagdreg_mvbrsft.s b/tests/tcg/bfin/c_cc_flagdreg_mvbrsft.s new file mode 100644 index 0000000000000..a36f31ac27ef5 --- /dev/null +++ b/tests/tcg/bfin/c_cc_flagdreg_mvbrsft.s @@ -0,0 +1,87 @@ +//Original:/testcases/core/c_cc_flagdreg_mvbrsft/c_cc_flagdreg_mvbrsft.dsp +// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xa08d2311; +imm32 r1, 0x10120040; +imm32 r2, 0x62b61557; +imm32 r3, 0x07300007; +imm32 r4, 0x00740088; +imm32 r5, 0x609950aa; +imm32 r6, 0x20bb06cc; +imm32 r7, 0xd90e108f; + + ASTAT = R0; + + CC = R1; // cc2dreg + IF CC R1 = R3; // ccmov + CC = ! CC; // cc2dreg + IF CC R3 = R2; // ccmov + CC = R0 < R1; // ccflag + IF CC R4 = R5; // ccmov + CC = R2 == R3; + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + IF !CC JUMP LABEL1; // branch on + CC = ! CC; + IF !CC JUMP LABEL2 (BP); // branch on +LABEL1: + R6 = R0 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R3; + CC = R0 < R1; // ccflag + IF CC JUMP END (BP); // branch on + R4 = R5 + R7; + +END: + +CHECKREG r0, 0xA08D2311; +CHECKREG r1, 0x07300007; +CHECKREG r2, 0x62B61557; +CHECKREG r3, 0x07300007; +CHECKREG r4, 0x609950AA; +CHECKREG r5, 0x609950AA; +CHECKREG r6, 0x20BB06CC; +CHECKREG r7, 0x596950A3; + +imm32 r0, 0x408d2711; +imm32 r1, 0x15124040; +imm32 r2, 0x62661557; +imm32 r3, 0x073b0007; +imm32 r4, 0x01f49088; +imm32 r5, 0x6e2959aa; +imm32 r6, 0xa0b506cc; +imm32 r7, 0x00000002; + + + CC = R1; // cc2dreg + R2 = ROT R2 BY 1; // dsp32shiftim_rot + CC = ! CC; // cc2dreg + R3 = ROT R0 BY -3; // dsp32shiftim_rot + CC = R0 < R1; // ccflag + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = R2 == R3; + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + R7 = ROT R6 BY R7.L; + +CHECKREG r0, 0x408D2711; +CHECKREG r1, 0x15124040; +CHECKREG r2, 0xC4CC2AAF; +CHECKREG r3, 0x6811A4E2; +CHECKREG r4, 0x01F49088; +CHECKREG r5, 0x6E2959AA; +CHECKREG r6, 0x3E921100; +CHECKREG r7, 0xFA484402; + + + + +pass diff --git a/tests/tcg/bfin/c_cc_regmvlogi_mvbrsft.s b/tests/tcg/bfin/c_cc_regmvlogi_mvbrsft.s new file mode 100644 index 0000000000000..7ad1823fabb10 --- /dev/null +++ b/tests/tcg/bfin/c_cc_regmvlogi_mvbrsft.s @@ -0,0 +1,83 @@ +//Original:/testcases/core/c_cc_regmvlogi_mvbrsft/c_cc_regmvlogi_mvbrsft.dsp +// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000020; // cc=1 +imm32 r1, 0x00000000; // cc=0 +imm32 r2, 0x62b61557; +imm32 r3, 0x07300007; +imm32 r4, 0x00740088; +imm32 r5, 0x609950aa; +imm32 r6, 0x20bb06cc; +imm32 r7, 0xd90e108f; + + + ASTAT = R0; // cc=1 REGMV + IF CC R1 = R3; // ccmov + ASTAT = R1; // cc=0 REGMV + IF CC R3 = R2; // ccmv + CC = R0 < R1; // ccflag + IF CC R4 = R5; // ccmv + CC = ! BITTST( R0 , 4 ); // cc = 0 + IF CC R4 = R5; // ccmv + CC = BITTST ( R1 , 4 ); // cc = 0 + IF !CC JUMP LABEL1; // branch + CC = ! CC; + IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R6 = R0 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R3; + CC = R0 < R1; // ccflag + IF CC JUMP END (BP); // branch on + R4 = R5 + R7; + +END: + +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x07300007; +CHECKREG r2, 0x62B61557; +CHECKREG r3, 0x07300007; +CHECKREG r4, 0x609950AA; +CHECKREG r5, 0x609950AA; +CHECKREG r6, 0x62B61577; +CHECKREG r7, 0xD90E108F; + +imm32 r0, 0x00000020; +imm32 r1, 0x00000000; +imm32 r2, 0x62661557; +imm32 r3, 0x073b0007; +imm32 r4, 0x01f49088; +imm32 r5, 0x6e2959aa; +imm32 r6, 0xa0b506cc; +imm32 r7, 0x00000002; + + + ASTAT = R0; // cc=1 REGMV + R2 = ROT R2 BY 1; // dsp32shiftim_rot + ASTAT = R1; // cc=0 REGMV + R3 = ROT R3 BY 1; // dsp32shiftim_rot + CC = ! BITTST( R0 , 4 ); // cc = 0 + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = BITTST ( R1 , 4 ); // cc = 0 + IF CC R4 = R5; // ccmov + CC = BITTST ( R0 , 4 ); // cc = 1 + R7 = ROT R6 BY R7.L; + +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xC4CC2AAF; +CHECKREG r3, 0x0E76000E; +CHECKREG r4, 0x01F49088; +CHECKREG r5, 0x6E2959AA; +CHECKREG r6, 0x3E921110; +CHECKREG r7, 0xFA484440; + +pass diff --git a/tests/tcg/bfin/c_ccflag_dr_dr.s b/tests/tcg/bfin/c_ccflag_dr_dr.s new file mode 100644 index 0000000000000..a72cb0ccb34b8 --- /dev/null +++ b/tests/tcg/bfin/c_ccflag_dr_dr.s @@ -0,0 +1,299 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr/c_ccflag_dr_dr.dsp +// Spec Reference: ccflags dr-dr +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00110022; +imm32 r1, 0x00110022; +imm32 r2, 0x00330044; +imm32 r3, 0x00550066; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1; +R6 = ASTAT; +CC = R0 <= R1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; +CC = R0 < R1; +R4 = ASTAT; +CC = R0 <= R1 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001025; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2; +R6 = ASTAT; +CC = R3 <= R2; +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; +CC = R3 < R2 (IU); +R4 = ASTAT; +CC = R3 <= R2 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3; +R6 = ASTAT; +CC = R2 <= R3; +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; +CC = R2 < R3; +R4 = ASTAT; +CC = R2 <= R3; +R5 = ASTAT; +CHECKREG r4, 0x00000022; +CHECKREG r5, 0x00000022; + +imm32 r0, 0x01230123; +imm32 r1, 0x81230123; +imm32 r2, 0x04560456; +imm32 r3, 0x87890789; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1; +R6 = ASTAT; +CC = R0 <= R1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2; +R6 = ASTAT; +CC = R3 <= R2; +R7 = ASTAT; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001026; +CHECKREG r7, 0x00001026; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R1 == R3; +R5 = ASTAT; +CC = R1 < R3; +R6 = ASTAT; +CC = R1 <= R3; +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R3 == R1; +R5 = ASTAT; +CC = R3 < R1; +R6 = ASTAT; +CC = R3 <= R1; +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + + +imm32 r0, 0x80230123; +imm32 r1, 0x00230123; +imm32 r2, 0x80560056; +imm32 r3, 0x00890089; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3; +R6 = ASTAT; +CC = R2 <= R3; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; // overflow and carry but not negative +CHECKREG r6, 0x00001026; // cc overflow, carry and negative +CHECKREG r7, 0x00001026; + + +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; + +imm32 r0, 0x00000000; +imm32 r1, 0x11111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +NOP; +CHECKREG r3, 0x00000000; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R4 == R5; +R0 = ASTAT; +CC = R4 < R5; +R1 = ASTAT; +CC = R4 <= R5; +R2 = ASTAT; +CC = R4 < R5; +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R4 <= R5; +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6; +R1 = ASTAT; +CC = R7 <= R6; +R2 = ASTAT; +CC = R7 < R6; +R3 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; +CC = R7 <= R6 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R6 == R7; +R0 = ASTAT; +CC = R6 < R7; +R1 = ASTAT; +CC = R6 <= R7; +R2 = ASTAT; +CC = R6 < R7; +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R6 <= R7; +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +imm32 r4, 0x01230123; +imm32 r5, 0x81230123; +imm32 r6, 0x04560456; +imm32 r7, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R4 == R5; +R1 = ASTAT; +CC = R4 < R5; +R2 = ASTAT; +CC = R4 <= R5; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6; +R1 = ASTAT; +CC = R7 <= R6; +R2 = ASTAT; +CHECKREG r0, 0x00001006; +CHECKREG r1, 0x00001026; +CHECKREG r2, 0x00001026; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R5 == R7; +R0 = ASTAT; +CC = R5 < R7; +R1 = ASTAT; +CC = R5 <= R7; +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R7 == R5; +R1 = ASTAT; +CC = R7 < R5; +R2 = ASTAT; +CC = R7 <= R5; +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + + +imm32 r4, 0x80230123; +imm32 r5, 0x00230123; +imm32 r6, 0x80560056; +imm32 r7, 0x00890089; +// operate on negative number +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R6 == R7; +R1 = ASTAT; +CC = R6 < R7; +R2 = ASTAT; +CC = R6 <= R7; +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; // overflow and carry but not negative +CHECKREG r2, 0x00001026; // cc overflow, carry and negative +CHECKREG r3, 0x00001026; + + +pass; diff --git a/tests/tcg/bfin/c_ccflag_dr_dr_uu.s b/tests/tcg/bfin/c_ccflag_dr_dr_uu.s new file mode 100644 index 0000000000000..2709c89fba877 --- /dev/null +++ b/tests/tcg/bfin/c_ccflag_dr_dr_uu.s @@ -0,0 +1,299 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr_uu/c_ccflag_dr_dr_uu.dsp +// Spec Reference: ccflags dr-dr_uu +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00110022; +imm32 r1, 0x00110022; +imm32 r2, 0x00330044; +imm32 r3, 0x00550066; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1 (IU); +R6 = ASTAT; +CC = R0 <= R1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; +CC = R0 < R1 (IU); +R4 = ASTAT; +CC = R0 <= R1 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001025; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2 (IU); +R6 = ASTAT; +CC = R3 <= R2 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; +CC = R3 < R2 (IU); +R4 = ASTAT; +CC = R3 <= R2 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3 (IU); +R6 = ASTAT; +CC = R2 <= R3 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; +CC = R2 < R3 (IU); +R4 = ASTAT; +CC = R2 <= R3 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00000022; +CHECKREG r5, 0x00000022; + +imm32 r0, 0x01230123; +imm32 r1, 0x81230123; +imm32 r2, 0x04560456; +imm32 r3, 0x87890789; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1 (IU); +R6 = ASTAT; +CC = R0 <= R1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2 (IU); +R6 = ASTAT; +CC = R3 <= R2 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R1 == R3; +R5 = ASTAT; +CC = R1 < R3 (IU); +R6 = ASTAT; +CC = R1 <= R3 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R3 == R1; +R5 = ASTAT; +CC = R3 < R1 (IU); +R6 = ASTAT; +CC = R3 <= R1 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + + +imm32 r0, 0x80230123; +imm32 r1, 0x00230123; +imm32 r2, 0x80560056; +imm32 r3, 0x00890089; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3 (IU); +R6 = ASTAT; +CC = R2 <= R3 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; // overflow and carry but not negative +CHECKREG r6, 0x00001004; // cc overflow, carry and negative +CHECKREG r7, 0x00001004; + + +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; + +imm32 r0, 0x00000000; +imm32 r1, 0x11111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +NOP; +CHECKREG r3, 0x00000000; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R4 == R5; +R0 = ASTAT; +CC = R4 < R5 (IU); +R1 = ASTAT; +CC = R4 <= R5 (IU); +R2 = ASTAT; +CC = R4 < R5 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R4 <= R5 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6 (IU); +R1 = ASTAT; +CC = R7 <= R6 (IU); +R2 = ASTAT; +CC = R7 < R6 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; +CC = R7 <= R6 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R6 == R7; +R0 = ASTAT; +CC = R6 < R7 (IU); +R1 = ASTAT; +CC = R6 <= R7 (IU); +R2 = ASTAT; +CC = R6 < R7 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R6 <= R7 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +imm32 r4, 0x01230123; +imm32 r5, 0x81230123; +imm32 r6, 0x04560456; +imm32 r7, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R4 == R5; +R1 = ASTAT; +CC = R4 < R5 (IU); +R2 = ASTAT; +CC = R4 <= R5 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6 (IU); +R1 = ASTAT; +CC = R7 <= R6 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00001006; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R5 == R7; +R0 = ASTAT; +CC = R5 < R7 (IU); +R1 = ASTAT; +CC = R5 <= R7 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R7 == R5; +R1 = ASTAT; +CC = R7 < R5 (IU); +R2 = ASTAT; +CC = R7 <= R5 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + + +imm32 r4, 0x80230123; +imm32 r5, 0x00230123; +imm32 r6, 0x80560056; +imm32 r7, 0x00890089; +// operate on negative number +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R6 == R7; +R1 = ASTAT; +CC = R6 < R7 (IU); +R2 = ASTAT; +CC = R6 <= R7 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; // overflow and carry but not negative +CHECKREG r2, 0x00001004; // cc overflow, carry and negative +CHECKREG r3, 0x00001004; + + +pass; diff --git a/tests/tcg/bfin/c_ccflag_dr_imm3.s b/tests/tcg/bfin/c_ccflag_dr_imm3.s new file mode 100644 index 0000000000000..e584b80b115a9 --- /dev/null +++ b/tests/tcg/bfin/c_ccflag_dr_imm3.s @@ -0,0 +1,224 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3/c_ccflag_dr_imm3.dsp +// Spec Reference: ccflag dr-imm3 +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000002; +imm32 r2, 0x00000003; +imm32 r3, 0x00000004; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R0 == 1; +R5 = ASTAT; +CC = R0 < 1; +R6 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CC = R0 <= 1; +R5 = ASTAT; +CC = R0 < 1; +R6 = ASTAT; +CC = R0 <= 1; +R7 = ASTAT; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R1 == 1; +R5 = ASTAT; +CC = R1 < 1; +R6 = ASTAT; +CC = R1 <= 1; +R7 = ASTAT; +CHECKREG r5, 0x00001004; // carry +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R0 == 2; +R5 = ASTAT; +CC = R0 < 2; +R6 = ASTAT; +CC = R0 <= 2; +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// positive dreg GREATER than to neg imm3 +CC = R2 == -4; +R5 = ASTAT; +CC = R2 < -4; +R6 = ASTAT; +CC = R2 <= -4; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, -1; +imm32 r1, -2; +imm32 r2, -3; +imm32 r3, -4; +// negative dreg and positive imm3 +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +CC = R3 == 1; +R5 = ASTAT; +CC = R3 < 1; +R6 = ASTAT; +CC = R3 <= 1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001026; +CHECKREG r7, 0x00001026; + +// negative dreg LESS than neg imm3 +CC = R2 == -1; +R4 = ASTAT; +CC = R2 < -1; +R5 = ASTAT; +CC = R2 <= -1; +R6 = ASTAT; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000022; +CHECKREG r6, 0x00000022; + +// negative dreg GREATER neg imm3 +CC = R0 == -4; +R4 = ASTAT; +CC = R0 < -4; +R5 = ASTAT; +CC = R0 <= -4; +R6 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; + +imm32 r4, 0x00000001; +imm32 r5, 0x00000002; +imm32 r6, 0x00000003; +imm32 r7, 0x00000004; + +ASTAT = R0; +R3 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R4 == 1; +R1 = ASTAT; +CC = R4 < 1; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001025; +CHECKREG r2, 0x00001005; +CC = R4 <= 1; +R1 = ASTAT; +CC = R4 < 1; +R2 = ASTAT; +CC = R4 <= 1; +R3 = ASTAT; +CHECKREG r1, 0x00001025; +CHECKREG r2, 0x00001005; +CHECKREG r3, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R5 == 1; +R1 = ASTAT; +CC = R5 < 1; +R2 = ASTAT; +CC = R5 <= 1; +R3 = ASTAT; +CHECKREG r1, 0x00001004; // carry +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R6 == 2; +R1 = ASTAT; +CC = R6 < 2; +R2 = ASTAT; +CC = R6 <= 2; +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg GREATER than to neg imm3 +CC = R6 == -4; +R1 = ASTAT; +CC = R6 < -4; +R2 = ASTAT; +CC = R6 <= -4; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + +imm32 r4, -1; +imm32 r5, -2; +imm32 r6, -3; +imm32 r7, -4; +// negative dreg and positive imm3 +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +CC = R7 == 1; +R1 = ASTAT; +CC = R7 < 1; +R2 = ASTAT; +CC = R7 <= 1; +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; +CHECKREG r2, 0x00001026; +CHECKREG r3, 0x00001026; + +// negative dreg LESS than neg imm3 +CC = R6 == -1; +R0 = ASTAT; +CC = R6 < -1; +R1 = ASTAT; +CC = R6 <= -1; +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; + +// negative dreg GREATER neg imm3 +CC = R4 == -4; +R0 = ASTAT; +CC = R4 < -4; +R1 = ASTAT; +CC = R4 <= -4; +R2 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + + + +pass; diff --git a/tests/tcg/bfin/c_ccflag_dr_imm3_uu.s b/tests/tcg/bfin/c_ccflag_dr_imm3_uu.s new file mode 100644 index 0000000000000..d4a6a480ffdbc --- /dev/null +++ b/tests/tcg/bfin/c_ccflag_dr_imm3_uu.s @@ -0,0 +1,221 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3_uu/c_ccflag_dr_imm3_uu.dsp +// Spec Reference: ccflag dr-imm3 (uu) +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000002; +imm32 r2, 0x00000003; +imm32 r3, 0x00000004; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R0 == 1; +R5 = ASTAT; +CC = R0 < 1; +R6 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CC = R0 <= 1; +R5 = ASTAT; +CC = R0 < 1 (IU); +R6 = ASTAT; +CC = R0 <= 1 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R1 == 1; +R5 = ASTAT; +CC = R1 < 1 (IU); +R6 = ASTAT; +CC = R1 <= 1 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001004; // carry +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R0 == 2; +R5 = ASTAT; +CC = R0 < 2 (IU); +R6 = ASTAT; +CC = R0 <= 2 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// positive dreg GREATER than to neg imm3 +CC = R2 == -4; +R5 = ASTAT; +CC = R2 < 4 (IU); +R6 = ASTAT; +CC = R2 <= 4 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +imm32 r0, -1; +imm32 r1, -2; +imm32 r2, -3; +imm32 r3, -4; +// negative dreg and positive imm3 +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +CC = R3 == 1; +R5 = ASTAT; +CC = R3 < 1 (IU); +R6 = ASTAT; +CC = R3 <= 1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// negative dreg LESS than neg imm3 +CC = R2 == -1; +R4 = ASTAT; +CC = R2 < 1 (IU); +R5 = ASTAT; +CC = R2 <= 1 (IU); +R6 = ASTAT; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; + +// negative dreg GREATER neg imm3 +CC = R0 == -2; +R4 = ASTAT; +CC = R0 < 4 (IU); +R5 = ASTAT; +CC = R0 <= 4 (IU); +R6 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; + +imm32 r4, 0x00000001; +imm32 r5, 0x00000002; +imm32 r6, 0x00000003; +imm32 r7, 0x00000004; + +ASTAT = R0; +R3 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R4 == 1; +R1 = ASTAT; +CC = R4 < 1 (IU); +R2 = ASTAT; +CC = R4 <= 1 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001025; +CHECKREG r2, 0x00001005; +CHECKREG r3, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R5 == 1; +R1 = ASTAT; +CC = R5 < 1 (IU); +R2 = ASTAT; +CC = R5 <= 1 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00001004; // carry +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R6 == 2; +R1 = ASTAT; +CC = R6 < 2 (IU); +R2 = ASTAT; +CC = R6 <= 2 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg GREATER than to neg imm3 +CC = R6 == -4; +R1 = ASTAT; +CC = R6 < 4 (IU); +R2 = ASTAT; +CC = R6 <= 4 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; + +imm32 r4, -1; +imm32 r5, -2; +imm32 r6, -3; +imm32 r7, -4; +// negative dreg and positive imm3 +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +CC = R7 == 1; +R1 = ASTAT; +CC = R7 < 1 (IU); +R2 = ASTAT; +CC = R7 <= 1 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// negative dreg LESS than neg imm3 +CC = R6 == -1; +R0 = ASTAT; +CC = R6 < 1 (IU); +R1 = ASTAT; +CC = R6 <= 1 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + +// negative dreg GREATER neg imm3 +CC = R4 == -4; +R0 = ASTAT; +CC = R4 < 4 (IU); +R1 = ASTAT; +CC = R4 <= 4 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + + + + + + +pass; diff --git a/tests/tcg/bfin/c_ccflag_pr_imm3.s b/tests/tcg/bfin/c_ccflag_pr_imm3.s new file mode 100644 index 0000000000000..aa6a0eb6abd0b --- /dev/null +++ b/tests/tcg/bfin/c_ccflag_pr_imm3.s @@ -0,0 +1,539 @@ +//Original:/testcases/core/c_ccflag_pr_imm3/c_ccflag_pr_imm3.dsp +// Spec Reference: ccflag pr-imm3 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +//imm32 p0, 0x00000001; +imm32 p1, 0x00000001; +imm32 p2, 0x00000002; +imm32 p3, 0x00000003; +imm32 p4, 0x00000001; +imm32 p5, 0x00000002; +imm32 sp, 0x00000003; +imm32 fp, 0x00000003; + +R0 = 0; +ASTAT = R0; +// positive dreg EQUAL to positive imm3 +CC = P1 == 1; +R0 = ASTAT; +CC = P1 < 1; +R1 = ASTAT; +CC = P1 <= 1; +R2 = ASTAT; +CC = P2 == 2; +R3 = ASTAT; +CC = P2 < 2; +R4 = ASTAT; +CC = P2 <= 2; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 3; +R1 = ASTAT; +CC = P3 <= 3; +R2 = ASTAT; +CC = P4 == 1; +R3 = ASTAT; +CC = P4 < 1; +R4 = ASTAT; +CC = P4 <= 1; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P5 == 2; +R0 = ASTAT; +CC = P5 < 2; +R1 = ASTAT; +CC = P5 <= 2; +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 3; +R4 = ASTAT; +CC = SP <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 3; +R6 = ASTAT; +CC = FP <= 3; +R7 = ASTAT; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000020; + +// positive dreg GREATER than positive imm3 +imm32 p1, 0x00000002; +imm32 p2, 0x00000002; +imm32 p3, 0x00000003; +imm32 p4, 0x00000002; +imm32 p5, 0x00000002; +imm32 sp, 0x00000003; +imm32 fp, 0x00000003; +CC = P1 == 0; +R0 = ASTAT; +CC = P1 < 0; +R1 = ASTAT; +CC = P1 <= 0; +R2 = ASTAT; +CC = P2 == 1; +R3 = ASTAT; +CC = P2 < 1; +R4 = ASTAT; +CC = P2 <= 1; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == 2; +R0 = ASTAT; +CC = P3 < 2; +R1 = ASTAT; +CC = P3 <= 2; +R2 = ASTAT; +CC = P4 == 0; +R3 = ASTAT; +CC = P4 < 0; +R4 = ASTAT; +CC = P4 <= 0; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == 1; +R0 = ASTAT; +CC = P5 < 1; +R1 = ASTAT; +CC = P5 <= 1; +R2 = ASTAT; +CC = SP == 2; +R3 = ASTAT; +CC = SP < 2; +R4 = ASTAT; +CC = SP <= 2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == 2; +R5 = ASTAT; +CC = FP < 2; +R6 = ASTAT; +CC = FP <= 2; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive dreg LESS than positive imm3 +imm32 p1, 0x00000001; +imm32 p2, 0x00000002; +imm32 p3, 0x00000002; +imm32 p4, 0x00000001; +imm32 p5, 0x00000001; +imm32 sp, 0x00000002; +imm32 fp, 0x00000002; +CC = P1 == 2; +R0 = ASTAT; +CC = P1 < 2; +R1 = ASTAT; +CC = P1 <= 2; +R2 = ASTAT; +CC = P2 == 3; +R3 = ASTAT; +CC = P2 < 3; +R4 = ASTAT; +CC = P2 <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 3; +R1 = ASTAT; +CC = P3 <= 3; +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 3; +R4 = ASTAT; +CC = P4 <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 3; +R1 = ASTAT; +CC = P5 <= 3; +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 3; +R4 = ASTAT; +CC = SP <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 3; +R6 = ASTAT; +CC = FP <= 3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + + +// positive dreg GREATER than neg imm3 +CC = P1 == -1; +R0 = ASTAT; +CC = P1 < -1; +R1 = ASTAT; +CC = P1 <= -1; +R2 = ASTAT; +CC = P2 == -2; +R3 = ASTAT; +CC = P2 < -2; +R4 = ASTAT; +CC = P2 <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == -3; +R0 = ASTAT; +CC = P3 < -3; +R1 = ASTAT; +CC = P3 <= -3; +R2 = ASTAT; +CC = P4 == -4; +R3 = ASTAT; +CC = P4 < -4; +R4 = ASTAT; +CC = P4 <= -4; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == -1; +R0 = ASTAT; +CC = P5 < -1; +R1 = ASTAT; +CC = P5 <= -1; +R2 = ASTAT; +CC = SP == -2; +R3 = ASTAT; +CC = SP < -2; +R4 = ASTAT; +CC = SP <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == -4; +R5 = ASTAT; +CC = FP < -4; +R6 = ASTAT; +CC = FP <= -4; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + + +imm32 p1, -1; +imm32 p2, -2; +imm32 p3, -3; +imm32 p4, -4; +imm32 p5, -1; +imm32 sp, -2; +imm32 fp, -3; +// negative dreg equal negative imm3 +CC = P1 == -1; +R0 = ASTAT; +CC = P1 < -1; +R1 = ASTAT; +CC = P1 <= -1; +R2 = ASTAT; +CC = P2 == -2; +R3 = ASTAT; +CC = P2 < -2; +R4 = ASTAT; +CC = P2 <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P3 == -3; +R0 = ASTAT; +CC = P3 < -3; +R1 = ASTAT; +CC = P3 <= -3; +R2 = ASTAT; +CC = P4 == -4; +R3 = ASTAT; +CC = P4 < -4; +R4 = ASTAT; +CC = P4 <= -4; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P5 == -1; +R0 = ASTAT; +CC = P5 < -1; +R1 = ASTAT; +CC = P5 <= -1; +R2 = ASTAT; +CC = SP == -2; +R3 = ASTAT; +CC = SP < -2; +R4 = ASTAT; +CC = SP <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = FP == -3; +R5 = ASTAT; +CC = FP < -3; +R6 = ASTAT; +CC = FP <= -3; +R7 = ASTAT; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000020; + + +// negative dreg GREATER neg imm3 +imm32 p1, -1; +imm32 p2, -1; +imm32 p3, -2; +imm32 p4, -3; +imm32 p5, -1; +imm32 sp, -2; +imm32 fp, -3; +CC = P1 == -2; +R0 = ASTAT; +CC = P1 < -2; +R1 = ASTAT; +CC = P1 <= -2; +R2 = ASTAT; +CC = P2 == -3; +R3 = ASTAT; +CC = P2 < -3; +R4 = ASTAT; +CC = P2 <= -3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == -4; +R0 = ASTAT; +CC = P3 < -4; +R1 = ASTAT; +CC = P3 <= -4; +R2 = ASTAT; +CC = P4 == -4; +R3 = ASTAT; +CC = P4 < -4; +R4 = ASTAT; +CC = P4 <= -4; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == -2; +R0 = ASTAT; +CC = P5 < -2; +R1 = ASTAT; +CC = P5 <= -2; +R2 = ASTAT; +CC = SP == -3; +R3 = ASTAT; +CC = SP < -3; +R4 = ASTAT; +CC = SP <= -3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == -4; +R5 = ASTAT; +CC = FP < -4; +R6 = ASTAT; +CC = FP <= -4; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative dreg LESS than neg imm3 +imm32 p1, -2; +imm32 p2, -2; +imm32 p3, -3; +imm32 p4, -3; +imm32 p5, -4; +imm32 sp, -4; +imm32 fp, -4; +imm32 p4, -4; +CC = P1 == -1; +R0 = ASTAT; +CC = P1 < -1; +R1 = ASTAT; +CC = P1 <= -1; +R2 = ASTAT; +CC = P2 == -1; +R3 = ASTAT; +CC = P2 < -1; +R4 = ASTAT; +CC = P2 <= -1; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P3 == -2; +R0 = ASTAT; +CC = P3 < -2; +R1 = ASTAT; +CC = P3 <= -2; +R2 = ASTAT; +CC = P4 == -2; +R3 = ASTAT; +CC = P4 < -2; +R4 = ASTAT; +CC = P4 <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P5 == -3; +R0 = ASTAT; +CC = P5 < -3; +R1 = ASTAT; +CC = P5 <= -3; +R2 = ASTAT; +CC = SP == -3; +R3 = ASTAT; +CC = SP < -3; +R4 = ASTAT; +CC = SP <= -3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = FP == -3; +R5 = ASTAT; +CC = FP < -3; +R6 = ASTAT; +CC = FP <= -3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + + +pass diff --git a/tests/tcg/bfin/c_ccflag_pr_imm3_uu.s b/tests/tcg/bfin/c_ccflag_pr_imm3_uu.s new file mode 100644 index 0000000000000..6b1870248c110 --- /dev/null +++ b/tests/tcg/bfin/c_ccflag_pr_imm3_uu.s @@ -0,0 +1,238 @@ +//Original:/testcases/core/c_ccflag_pr_imm3_uu/c_ccflag_pr_imm3_uu.dsp +// Spec Reference: ccflag pr-imm3 (uu) +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS 0; + + +//imm32 p0, 0x00000001; +imm32 p1, 0x00000001; +imm32 p2, 0x00000002; +imm32 p3, 0x00000003; +imm32 p4, 0x00000004; +imm32 p5, 0x00000005; +imm32 sp, 0x00000006; +imm32 fp, 0x00000007; + +R0 = 0; +ASTAT = R0; +// positive preg EQUAL to positive imm3 +CC = P1 == 1; +R0 = ASTAT; +CC = P1 < 1 (IU); +R1 = ASTAT; +CC = P1 <= 1 (IU); +R2 = ASTAT; +CC = P2 == 2; +R3 = ASTAT; +CC = P2 < 2 (IU); +R4 = ASTAT; +CC = P2 <= 2 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 3 (IU); +R1 = ASTAT; +CC = P3 <= 3 (IU); +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 4 (IU); +R4 = ASTAT; +CC = P4 <= 4 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 5 (IU); +R1 = ASTAT; +CC = P5 <= 5 (IU); +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 6 (IU); +R4 = ASTAT; +CC = SP <= 6 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 7 (IU); +R6 = ASTAT; +CC = FP <= 7 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000020; + +// positive preg GREATER than positive imm3 +CC = P1 == 0; +R0 = ASTAT; +CC = P1 < 0 (IU); +R1 = ASTAT; +CC = P1 <= 0 (IU); +R2 = ASTAT; +CC = P2 == 1; +R3 = ASTAT; +CC = P2 < 1 (IU); +R4 = ASTAT; +CC = P2 <= 1 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == 2; +R0 = ASTAT; +CC = P3 < 2 (IU); +R1 = ASTAT; +CC = P3 <= 2 (IU); +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 3 (IU); +R4 = ASTAT; +CC = P4 <= 3 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 4 (IU); +R1 = ASTAT; +CC = P5 <= 4 (IU); +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 5 (IU); +R4 = ASTAT; +CC = SP <= 5 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 6 (IU); +R6 = ASTAT; +CC = FP <= 6 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive preg LESS than positive imm3 +imm32 p1, 0x00000000; +imm32 p2, 0x00000001; +imm32 p3, 0x00000002; +imm32 p4, 0x00000003; +imm32 p5, 0x00000004; +imm32 sp, 0x00000005; +imm32 fp, 0x00000006; +CC = P1 == 2; +R0 = ASTAT; +CC = P1 < 2 (IU); +R1 = ASTAT; +CC = P1 <= 2 (IU); +R2 = ASTAT; +CC = P2 == 3; +R3 = ASTAT; +CC = P2 < 3 (IU); +R4 = ASTAT; +CC = P2 <= 3 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 4 (IU); +R1 = ASTAT; +CC = P3 <= 4 (IU); +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 5 (IU); +R4 = ASTAT; +CC = P4 <= 5 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 6 (IU); +R1 = ASTAT; +CC = P5 <= 6 (IU); +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 7 (IU); +R4 = ASTAT; +CC = SP <= 7 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 7 (IU); +R6 = ASTAT; +CC = FP <= 7 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + + + + +pass diff --git a/tests/tcg/bfin/c_ccflag_pr_pr.s b/tests/tcg/bfin/c_ccflag_pr_pr.s new file mode 100644 index 0000000000000..ef9db524c4c33 --- /dev/null +++ b/tests/tcg/bfin/c_ccflag_pr_pr.s @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr/c_ccflag_pr_pr.dsp +// Spec Reference: ccflag pr-pr +# mach: bfin + +.include "testutils.inc" + start + +INIT_P_REGS 0; +INIT_R_REGS 0; + + +//imm32 p0, 0x00110022; +imm32 p1, 0x00110022; +imm32 p2, 0x00330044; +imm32 p3, 0x00550066; + +imm32 p4, 0x00770088; +imm32 p5, 0x009900aa; +imm32 fp, 0x00bb00cc; +imm32 sp, 0x00000000; + +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 EQUAL to positive preg-2 +CC = P2 == P1; +R5 = ASTAT; +P5 = R5; +CC = P2 < P1; +R6 = ASTAT; +CC = P2 <= P1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive preg-1 GREATER than positive preg-2 +CC = P3 == P2; +R5 = ASTAT; +CC = P3 < P2; +R6 = ASTAT; +CC = P3 <= P2; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +// positive preg-1 LESS than positive preg-2 +CC = P2 == P3; +R5 = ASTAT; +CC = P2 < P3; +R6 = ASTAT; +CC = P2 <= P3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +//imm32 p0, 0x01230123; +imm32 p1, 0x81230123; +imm32 p2, 0x04560456; +imm32 p3, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 GREATER than negative preg-2 +CC = P2 == P1; +R5 = ASTAT; +CC = P2 < P1; +R6 = ASTAT; +CC = P2 <= P1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = P3 == P2; +R5 = ASTAT; +CC = P3 < P2; +R6 = ASTAT; +CC = P3 <= P2; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 GREATER than negative preg-2 +CC = P1 == P3; +R5 = ASTAT; +CC = P1 < P3; +R6 = ASTAT; +CC = P1 <= P3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = P3 == P1; +R5 = ASTAT; +CC = P3 < P1; +R6 = ASTAT; +CC = P3 <= P1; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +//imm32 p0, 0x80230123; +imm32 p1, 0x00230123; +imm32 p2, 0x80560056; +imm32 p3, 0x00890089; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = P2 == P3; +R5 = ASTAT; +CC = P2 < P3; +R6 = ASTAT; +CC = P2 <= P3; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; // overflow and carry but not negative +CHECKREG r6, 0x00000020; // cc overflow, carry and negative +CHECKREG r7, 0x00000020; + + +imm32 p4, 0x44444444; +imm32 p5, 0x55555555; +imm32 fp, 0x66666666; +imm32 sp, 0x77777777; + +//imm32 p0, 0x00000000; +imm32 p1, 0x11111111; +imm32 p2, 0x00000000; +imm32 p3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive preg-1 EQUAL to positive preg-2 +CC = P4 == P5; +R0 = ASTAT; +CC = P4 < P5; +R1 = ASTAT; +CC = P4 <= P5; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// positive preg-1 GREATER than positive preg-2 +CC = SP == FP; +R0 = ASTAT; +CC = SP < FP; +R1 = ASTAT; +CC = SP <= FP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; + + +// positive preg-1 LESS than positive preg-2 +CC = FP == SP; +R0 = ASTAT; +CC = FP < SP; +R1 = ASTAT; +CC = FP <= SP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +imm32 p4, 0x01230123; +imm32 p5, 0x81230123; +imm32 fp, 0x04560456; +imm32 sp, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; // nop; +CHECKREG r3, 0x00000000; + +// positive preg-1 GREATER than negative preg-2 +CC = P4 == P5; +R1 = ASTAT; +CC = P4 < P5; +R2 = ASTAT; +CC = P4 <= P5; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = SP == FP; +R0 = ASTAT; +CC = SP < FP; +R1 = ASTAT; +CC = SP <= FP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// negative preg-1 GREATER than negative preg-2 +CC = P5 == SP; +R0 = ASTAT; +CC = P5 < SP; +R1 = ASTAT; +CC = P5 <= SP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = SP == P5; +R1 = ASTAT; +CC = SP < P5; +R2 = ASTAT; +CC = SP <= P5; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + + +imm32 p4, 0x80230123; +imm32 p5, 0x00230123; +imm32 fp, 0x80560056; +imm32 sp, 0x00890089; +// operate on negative number +P3 = 0; +ASTAT = P3; +R0 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = R6 == R7; +R1 = ASTAT; +CC = R6 < R7; +R2 = ASTAT; +CC = R6 <= R7; +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001025; // overflow and carry but not negative +CHECKREG r2, 0x00001005; // cc overflow, carry and negative +CHECKREG r3, 0x00001025; + + +pass; diff --git a/tests/tcg/bfin/c_ccflag_pr_pr_uu.s b/tests/tcg/bfin/c_ccflag_pr_pr_uu.s new file mode 100644 index 0000000000000..0cde8c23c4098 --- /dev/null +++ b/tests/tcg/bfin/c_ccflag_pr_pr_uu.s @@ -0,0 +1,212 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr_uu/c_ccflag_pr_pr_uu.dsp +// Spec Reference: ccflag pr-pr (uu) +# mach: bfin + +.include "testutils.inc" + start + +INIT_R_REGS 0; + +//imm32 p0, 0x00110022; +imm32 p1, 0x00110022; +imm32 p2, 0x00330044; +imm32 p3, 0x00550066; + +imm32 p4, 0x00770088; +imm32 p5, 0x009900aa; +imm32 fp, 0x00bb00cc; +imm32 sp, 0x00000000; + +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 EQUAL to positive preg-2 +CC = P2 < P1 (IU); +R6 = ASTAT; +CC = P2 <= P1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive preg-1 GREATER than positive preg-2 +CC = P3 < P2 (IU); +R6 = ASTAT; +CC = P3 <= P2 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +// positive preg-1 LESS than positive preg-2 +CC = P2 < P3 (IU); +R6 = ASTAT; +CC = P2 <= P3 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +//imm32 p0, 0x01230123; +imm32 p1, 0x81230123; +imm32 p2, 0x04560456; +imm32 p3, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 GREATER than negative preg-2 +CC = P2 < P1 (IU); +R6 = ASTAT; +CC = P2 <= P1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = P3 < P2 (IU); +R6 = ASTAT; +CC = P3 <= P2 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative preg-1 GREATER than negative preg-2 +CC = P1 < P3 (IU); +R6 = ASTAT; +CC = P1 <= P3 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = P3 < P1 (IU); +R6 = ASTAT; +CC = P3 <= P1 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +//imm32 p0, 0x80230123; +imm32 p1, 0x00230123; +imm32 p2, 0x80560056; +imm32 p3, 0x00890089; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = P2 < P3 (IU); +R6 = ASTAT; +CC = P2 <= P3 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; // overflow and carry but not negative +CHECKREG r6, 0x00000000; // cc overflow, carry and negative +CHECKREG r7, 0x00000000; + + +imm32 p4, 0x44444444; +imm32 p5, 0x55555555; +imm32 fp, 0x66666666; +imm32 sp, 0x77777777; + +//imm32 p0, 0x00000000; +imm32 p1, 0x11111111; +imm32 p2, 0x00000000; +imm32 p3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive preg-1 EQUAL to positive preg-2 +CC = P4 < P5; +R1 = ASTAT; +CC = P4 <= P5; +R2 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// positive preg-1 GREATER than positive preg-2 +CC = SP < FP (IU); +R1 = ASTAT; +CC = SP <= FP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; + + +// positive preg-1 LESS than positive preg-2 +CC = FP < SP (IU); +R1 = ASTAT; +CC = FP <= SP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +imm32 p4, 0x01230123; +imm32 p5, 0x81230123; +imm32 fp, 0x04560456; +imm32 sp, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; // nop; +CHECKREG r3, 0x00000000; + +// positive preg-1 GREATER than negative preg-2 +CC = P4 < P5 (IU); +R2 = ASTAT; +CC = P4 <= P5 (IU); +R3 = ASTAT; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = SP < FP (IU); +R1 = ASTAT; +CC = SP <= FP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; + +// negative preg-1 GREATER than negative preg-2 +CC = P5 < SP (IU); +R1 = ASTAT; +CC = P5 <= SP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = SP < P5 (IU); +R2 = ASTAT; +CC = SP <= P5 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + + +imm32 p4, 0x80230123; +imm32 p5, 0x00230123; +imm32 fp, 0x80560056; +imm32 sp, 0x00890089; +// operate on negative number +R0 = 0; +ASTAT = R0; +R0 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = R6 < R7 (IU); +R2 = ASTAT; +CC = R6 <= R7 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; // overflow and carry but not negative +CHECKREG r2, 0x00001005; // cc overflow, carry and negative +CHECKREG r3, 0x00001025; + + +pass; diff --git a/tests/tcg/bfin/c_ccmv_cc_dr_dr.s b/tests/tcg/bfin/c_ccmv_cc_dr_dr.s new file mode 100644 index 0000000000000..b9e4fa6c5ae28 --- /dev/null +++ b/tests/tcg/bfin/c_ccmv_cc_dr_dr.s @@ -0,0 +1,124 @@ +//Original:/testcases/core/c_ccmv_cc_dr_dr/c_ccmv_cc_dr_dr.dsp +// Spec Reference: ccmv cc dreg = dreg +# mach: bfin + +.include "testutils.inc" + start + +R0 = 0; +ASTAT = R0; + + +imm32 r0, 0xa08d2301; +imm32 r1, 0xd0021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x60b61507; +imm32 r4, 0x50487609; +imm32 r5, 0x3005900b; +imm32 r6, 0x2a0c660d; +imm32 r7, 0xd90e108f; +IF CC R0 = R0; +IF CC R1 = R3; +IF CC R2 = R5; +IF CC R3 = R2; +CC = ! CC; +IF CC R4 = R6; +IF CC R5 = R1; +IF CC R6 = R7; +CC = ! CC; +IF CC R7 = R4; +CHECKREG r0, 0xA08D2301; +CHECKREG r1, 0xD0021053; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x60B61507; +CHECKREG r4, 0x2A0C660D; +CHECKREG r5, 0xD0021053; +CHECKREG r6, 0xD90E108F; +CHECKREG r7, 0xD90E108F; + + +imm32 r0, 0x308d2301; +imm32 r1, 0xd4023053; +imm32 r2, 0x2f041405; +imm32 r3, 0x60f61507; +imm32 r4, 0xd0487f09; +imm32 r5, 0x300b900b; +imm32 r6, 0x2a0cd60d; +imm32 r7, 0xd90e189f; +IF CC R4 = R3; +IF CC R5 = R7; +IF CC R6 = R1; +IF CC R7 = R2; +CC = ! CC; +IF CC R0 = R6; +IF CC R1 = R5; +IF CC R2 = R4; +CC = ! CC; +IF CC R3 = R0; +CHECKREG r0, 0x2A0CD60D; +CHECKREG r1, 0x300B900B; +CHECKREG r2, 0xD0487F09; +CHECKREG r3, 0x60F61507; +CHECKREG r4, 0xD0487F09; +CHECKREG r5, 0x300B900B; +CHECKREG r6, 0x2A0CD60D; +CHECKREG r7, 0xD90E189F; + + +imm32 r0, 0x708d2301; +imm32 r1, 0xd8021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x65b61507; +imm32 r4, 0x59487609; +imm32 r5, 0x3005900b; +imm32 r6, 0x2abc660d; +imm32 r7, 0xd90e108f; +IF CC R0 = R2; +IF CC R1 = R3; +CC = ! CC; +IF CC R2 = R5; +IF CC R3 = R7; +CC = ! CC; +IF CC R4 = R1; +IF CC R5 = R4; +IF CC R6 = R7; +IF CC R7 = R6; +CHECKREG r0, 0x708D2301; +CHECKREG r1, 0xD8021053; +CHECKREG r2, 0x3005900B; +CHECKREG r3, 0xD90E108F; +CHECKREG r4, 0x59487609; +CHECKREG r5, 0x3005900B; +CHECKREG r6, 0x2ABC660D; +CHECKREG r7, 0xD90E108F; + + +imm32 r0, 0xc08d2301; +imm32 r1, 0xdb021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x64b61507; +imm32 r4, 0x50487609; +imm32 r5, 0x30f5900b; +imm32 r6, 0x2a4c660d; +imm32 r7, 0x895e108f; +IF CC R4 = R3; +IF CC R5 = R7; +CC = ! CC; +IF CC R6 = R2; +IF CC R7 = R6; +CC = ! CC; +IF CC R0 = R1; +IF CC R1 = R2; +IF CC R2 = R0; +IF CC R3 = R4; +CHECKREG r0, 0xC08D2301; +CHECKREG r1, 0xDB021053; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x64B61507; +CHECKREG r4, 0x50487609; +CHECKREG r5, 0x30F5900B; +CHECKREG r6, 0x2F041405; +CHECKREG r7, 0x2F041405; + + +pass diff --git a/tests/tcg/bfin/c_ccmv_cc_dr_pr.s b/tests/tcg/bfin/c_ccmv_cc_dr_pr.s new file mode 100644 index 0000000000000..186a199a1de1d --- /dev/null +++ b/tests/tcg/bfin/c_ccmv_cc_dr_pr.s @@ -0,0 +1,61 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_cc_dr_pr/c_ccmv_cc_dr_pr.dsp +// Spec Reference: ccmv cc dpreg = dpreg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x138d2301; + imm32 r1, 0x20421053; + imm32 r2, 0x3f051405; + imm32 r3, 0x40b66507; + imm32 r4, 0x50487709; + imm32 r5, 0x6005908b; + imm32 r6, 0x7a0c6609; + imm32 r7, 0x890e108f; + imm32 p1, 0x9d021053; + imm32 p2, 0xafb41405; + imm32 p3, 0xb0bf1507; + imm32 p4, 0xd0483609; + imm32 p5, 0xe005d00b; + imm32 sp, 0xfa0c667d; + imm32 fp, 0xc90e108f; + IF CC R0 = P0; + IF CC P1 = R3; + IF CC R2 = P5; + IF CC P2 = R2; + CC = ! CC; + IF CC P3 = R6; + IF CC R5 = P1; + IF CC P4 = R7; + CC = ! CC; + IF CC R7 = P4; + IF CC P5 = R3; + IF CC R6 = SP; + IF CC R3 = P2; + CC = ! CC; + IF CC SP = R6; + IF CC R1 = P5; + IF CC FP = R4; + CC = ! CC; + IF CC R3 = P3; + CHECKREG r0, 0x138D2301; + CHECKREG r1, 0xE005D00B; + CHECKREG r2, 0x3F051405; + CHECKREG r3, 0x40B66507; + CHECKREG r4, 0x50487709; + CHECKREG r5, 0x9D021053; + CHECKREG r6, 0x7A0C6609; + CHECKREG r7, 0x890E108F; + CHECKREG p1, 0x9D021053; + CHECKREG p2, 0xAFB41405; + CHECKREG p3, 0x7A0C6609; + CHECKREG p4, 0x890E108F; + CHECKREG p5, 0xE005D00B; + CHECKREG sp, 0x7A0C6609; + CHECKREG fp, 0x50487709; + + pass diff --git a/tests/tcg/bfin/c_ccmv_cc_pr_pr.s b/tests/tcg/bfin/c_ccmv_cc_pr_pr.s new file mode 100644 index 0000000000000..df93ccb11a082 --- /dev/null +++ b/tests/tcg/bfin/c_ccmv_cc_pr_pr.s @@ -0,0 +1,111 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_cc_pr_pr/c_ccmv_cc_pr_pr.dsp +// Spec Reference: ccmv cc preg = preg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 p1, 0xd0021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2a0c660d; + imm32 fp, 0xd90e108f; + IF CC P3 = P3; + IF CC P1 = P3; + IF CC P2 = P5; + IF CC P3 = P2; + CC = ! CC; + IF CC P4 = SP; + IF CC P5 = P1; + IF CC SP = FP; + CC = ! CC; + IF CC FP = P4; + CHECKREG p1, 0xD0021053; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x60B61507; + CHECKREG p4, 0x2A0C660D; + CHECKREG p5, 0xD0021053; + CHECKREG sp, 0xD90E108F; + CHECKREG fp, 0xD90E108F; + + imm32 p1, 0xd4023053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60f61507; + imm32 p4, 0xd0487f09; + imm32 p5, 0x300b900b; + imm32 sp, 0x2a0cd60d; + imm32 fp, 0xd90e189f; + IF CC P4 = P3; + IF CC P5 = FP; + IF CC SP = P1; + IF CC FP = P2; + CC = ! CC; + IF CC P3 = SP; + IF CC P1 = P5; + IF CC P2 = P4; + CC = ! CC; + IF CC P3 = P2; + CHECKREG p1, 0x300B900B; + CHECKREG p2, 0xD0487F09; + CHECKREG p3, 0x2A0CD60D; + CHECKREG p4, 0xD0487F09; + CHECKREG p5, 0x300B900B; + CHECKREG sp, 0x2A0CD60D; + CHECKREG fp, 0xD90E189F; + + imm32 p1, 0xd8021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x65b61507; + imm32 p4, 0x59487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2abc660d; + imm32 fp, 0xd90e108f; + IF CC P3 = P2; + IF CC P1 = P3; + CC = ! CC; + IF CC P2 = P5; + IF CC P3 = FP; + CC = ! CC; + IF CC P4 = P1; + IF CC P5 = P4; + IF CC SP = FP; + IF CC FP = SP; + CHECKREG p1, 0xD8021053; + CHECKREG p2, 0x3005900B; + CHECKREG p3, 0xD90E108F; + CHECKREG p4, 0x59487609; + CHECKREG p5, 0x3005900B; + CHECKREG sp, 0x2ABC660D; + CHECKREG fp, 0xD90E108F; + + imm32 p1, 0xdb021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x64b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x30f5900b; + imm32 sp, 0x2a4c660d; + imm32 fp, 0x895e108f; + IF CC P4 = P3; + IF CC P5 = FP; + CC = ! CC; + IF CC SP = P2; + IF CC FP = SP; + CC = ! CC; + IF CC P3 = P1; + IF CC P1 = P2; + IF CC P2 = P3; + IF CC P3 = P4; + CHECKREG p1, 0xDB021053; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x64B61507; + CHECKREG p4, 0x50487609; + CHECKREG p5, 0x30F5900B; + CHECKREG sp, 0x2F041405; + CHECKREG fp, 0x2F041405; + + pass diff --git a/tests/tcg/bfin/c_ccmv_ncc_dr_dr.s b/tests/tcg/bfin/c_ccmv_ncc_dr_dr.s new file mode 100644 index 0000000000000..94a6e32dac227 --- /dev/null +++ b/tests/tcg/bfin/c_ccmv_ncc_dr_dr.s @@ -0,0 +1,123 @@ +//Original:/testcases/core/c_ccmv_ncc_dr_dr/c_ccmv_ncc_dr_dr.dsp +// Spec Reference: ccmv !cc dreg = dreg +# mach: bfin + +.include "testutils.inc" + start +R0 = 0; +ASTAT = R0; + + +imm32 r0, 0x808d2301; +imm32 r1, 0x90021053; +imm32 r2, 0x21041405; +imm32 r3, 0x60261507; +imm32 r4, 0x50447609; +imm32 r5, 0xdfe5500b; +imm32 r6, 0x2a0c660d; +imm32 r7, 0xd90e1b8f; +IF !CC R0 = R0; +IF !CC R1 = R3; +IF !CC R2 = R5; +IF !CC R3 = R2; +CC = ! CC; +IF !CC R4 = R6; +IF !CC R5 = R1; +IF !CC R6 = R7; +CC = ! CC; +IF !CC R7 = R4; +CHECKREG r0, 0x808D2301; +CHECKREG r1, 0x60261507; +CHECKREG r2, 0xDFE5500B; +CHECKREG r3, 0xDFE5500B; +CHECKREG r4, 0x50447609; +CHECKREG r5, 0xDFE5500B; +CHECKREG r6, 0x2A0C660D; +CHECKREG r7, 0x50447609; + + +imm32 r0, 0x308d2301; +imm32 r1, 0xd4023053; +imm32 r2, 0x2f041405; +imm32 r3, 0x60f61507; +imm32 r4, 0xd0487f09; +imm32 r5, 0x300b900b; +imm32 r6, 0x2a0cd60d; +imm32 r7, 0xd90e189f; +IF !CC R4 = R3; +IF !CC R5 = R7; +IF !CC R6 = R1; +IF !CC R7 = R2; +CC = ! CC; +IF !CC R0 = R6; +IF !CC R1 = R5; +IF !CC R2 = R4; +CC = ! CC; +IF !CC R3 = R0; +CHECKREG r0, 0x308D2301; +CHECKREG r1, 0xD4023053; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x308D2301; +CHECKREG r4, 0x60F61507; +CHECKREG r5, 0xD90E189F; +CHECKREG r6, 0xD4023053; +CHECKREG r7, 0x2F041405; + + +imm32 r0, 0x708d2301; +imm32 r1, 0xd8021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x65b61507; +imm32 r4, 0x59487609; +imm32 r5, 0x3005900b; +imm32 r6, 0x2abc660d; +imm32 r7, 0xd90e108f; +IF !CC R0 = R2; +IF !CC R1 = R3; +CC = ! CC; +IF !CC R2 = R5; +IF !CC R3 = R7; +CC = ! CC; +IF !CC R4 = R1; +IF !CC R5 = R4; +IF !CC R6 = R7; +IF !CC R7 = R6; +CHECKREG r0, 0x2F041405; +CHECKREG r1, 0x65B61507; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x65B61507; +CHECKREG r4, 0x65B61507; +CHECKREG r5, 0x65B61507; +CHECKREG r6, 0xD90E108F; +CHECKREG r7, 0xD90E108F; + + +imm32 r0, 0xc08d2301; +imm32 r1, 0xdb021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x64b61507; +imm32 r4, 0x50487609; +imm32 r5, 0x30f5900b; +imm32 r6, 0x2a4c660d; +imm32 r7, 0x895e108f; +IF !CC R4 = R3; +IF !CC R5 = R7; +CC = ! CC; +IF !CC R6 = R2; +IF !CC R7 = R6; +CC = ! CC; +IF !CC R0 = R1; +IF !CC R1 = R2; +IF !CC R2 = R0; +IF !CC R3 = R4; +CHECKREG r0, 0xDB021053; +CHECKREG r1, 0x2F041405; +CHECKREG r2, 0xDB021053; +CHECKREG r3, 0x64B61507; +CHECKREG r4, 0x64B61507; +CHECKREG r5, 0x895E108F; +CHECKREG r6, 0x2A4C660D; +CHECKREG r7, 0x895E108F; + + +pass diff --git a/tests/tcg/bfin/c_ccmv_ncc_dr_pr.s b/tests/tcg/bfin/c_ccmv_ncc_dr_pr.s new file mode 100644 index 0000000000000..1b981ac8ec6d7 --- /dev/null +++ b/tests/tcg/bfin/c_ccmv_ncc_dr_pr.s @@ -0,0 +1,60 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_dr_pr/c_ccmv_ncc_dr_pr.dsp +// Spec Reference: ccmv !cc dpreg = dpreg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x138d2301; + imm32 r1, 0x20421053; + imm32 r2, 0x3f051405; + imm32 r3, 0x40b66507; + imm32 r4, 0x50487709; + imm32 r5, 0x6005908b; + imm32 r6, 0x7a0c6609; + imm32 r7, 0x890e108f; + imm32 p1, 0x9d021053; + imm32 p2, 0xafb41405; + imm32 p3, 0xb0bf1507; + imm32 p4, 0xd0483609; + imm32 p5, 0xe005d00b; + imm32 sp, 0xfa0c667d; + imm32 fp, 0xc90e108f; + IF !CC R0 = P0; + CC = ! CC; + IF !CC P1 = R3; + IF !CC R2 = P5; + IF !CC P2 = R2; + IF !CC P3 = R6; + IF !CC R5 = P1; + CC = ! CC; + IF !CC P4 = R7; + IF !CC R7 = P4; + IF !CC P5 = R3; + IF !CC R6 = SP; + CC = ! CC; + IF !CC R3 = P2; + IF !CC SP = R6; + IF !CC R1 = P5; + CC = ! CC; + IF !CC FP = R4; + IF !CC R3 = P3; + CHECKREG r1, 0x20421053; + CHECKREG r2, 0x3F051405; + CHECKREG r3, 0xB0BF1507; + CHECKREG r4, 0x50487709; + CHECKREG r5, 0x6005908B; + CHECKREG r6, 0xFA0C667D; + CHECKREG r7, 0x890E108F; + CHECKREG p1, 0x9D021053; + CHECKREG p2, 0xAFB41405; + CHECKREG p3, 0xB0BF1507; + CHECKREG p4, 0x890E108F; + CHECKREG p5, 0x40B66507; + CHECKREG sp, 0xFA0C667D; + CHECKREG fp, 0x50487709; + + pass diff --git a/tests/tcg/bfin/c_ccmv_ncc_pr_pr.s b/tests/tcg/bfin/c_ccmv_ncc_pr_pr.s new file mode 100644 index 0000000000000..58c38edd537d3 --- /dev/null +++ b/tests/tcg/bfin/c_ccmv_ncc_pr_pr.s @@ -0,0 +1,111 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_pr_pr/c_ccmv_ncc_pr_pr.dsp +// Spec Reference: ccmv !cc preg = preg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 p1, 0xd0021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2a0c660d; + imm32 fp, 0xd90e108f; + IF !CC P3 = P3; + IF !CC P1 = P3; + CC = ! CC; + IF !CC P2 = P5; + IF !CC P3 = P2; + IF !CC P4 = SP; + IF !CC P5 = P1; + IF !CC SP = FP; + CC = ! CC; + IF !CC FP = P4; + CHECKREG p1, 0x60B61507; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x60B61507; + CHECKREG p4, 0x50487609; + CHECKREG p5, 0x3005900B; + CHECKREG sp, 0x2A0C660D; + CHECKREG fp, 0x50487609; + + imm32 p1, 0xd4023053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60f61507; + imm32 p4, 0xd0487f09; + imm32 p5, 0x300b900b; + imm32 sp, 0x2a0cd60d; + imm32 fp, 0xd90e189f; + IF !CC P4 = P3; + IF !CC P5 = FP; + CC = ! CC; + IF !CC SP = P1; + IF !CC FP = P2; + IF !CC P3 = SP; + IF !CC P1 = P5; + IF !CC P2 = P4; + CC = ! CC; + IF !CC P3 = P2; + CHECKREG p1, 0xD4023053; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x2F041405; + CHECKREG p4, 0x60F61507; + CHECKREG p5, 0xD90E189F; + CHECKREG sp, 0x2A0CD60D; + CHECKREG fp, 0xD90E189F; + + imm32 p1, 0xd8021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x65b61507; + imm32 p4, 0x59487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2abc660d; + imm32 fp, 0xd90e108f; + IF !CC P3 = P2; + IF !CC P1 = P3; + CC = ! CC; + IF !CC P2 = P5; + IF !CC P3 = FP; + IF !CC P4 = P1; + IF !CC P5 = P4; + IF !CC SP = FP; + CC = ! CC; + IF !CC FP = SP; + CHECKREG p1, 0x2F041405; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x2F041405; + CHECKREG p4, 0x59487609; + CHECKREG p5, 0x3005900B; + CHECKREG sp, 0x2ABC660D; + CHECKREG fp, 0x2ABC660D; + + imm32 p1, 0xdb021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x64b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x30f5900b; + imm32 sp, 0x2a4c660d; + imm32 fp, 0x895e108f; + IF !CC P4 = P3; + IF !CC P5 = FP; + IF !CC SP = P2; + IF !CC FP = SP; + CC = ! CC; + IF !CC P3 = P1; + IF !CC P1 = P2; + CC = ! CC; + IF !CC P2 = P3; + IF !CC P3 = P4; + CHECKREG p1, 0xDB021053; + CHECKREG p2, 0x64B61507; + CHECKREG p3, 0x64B61507; + CHECKREG p4, 0x64B61507; + CHECKREG p5, 0x895E108F; + CHECKREG sp, 0x2F041405; + CHECKREG fp, 0x2F041405; + + pass diff --git a/tests/tcg/bfin/c_comp3op_dr_and_dr.s b/tests/tcg/bfin/c_comp3op_dr_and_dr.s new file mode 100644 index 0000000000000..567187b53a560 --- /dev/null +++ b/tests/tcg/bfin/c_comp3op_dr_and_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_and_dr/c_comp3op_dr_and_dr.dsp +// Spec Reference: comp3op dregs & dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 & R0; +R1 = R0 & R1; +R2 = R0 & R2; +R3 = R0 & R3; +R4 = R0 & R4; +R5 = R0 & R5; +R6 = R0 & R6; +R7 = R0 & R7; +CHECKREG r0, 0x01234567; +CHECKREG r1, 0x01234567; +CHECKREG r2, 0x00200024; +CHECKREG r3, 0x00200024; +CHECKREG r4, 0x01014001; +CHECKREG r5, 0x00010145; +CHECKREG r6, 0x00224422; +CHECKREG r7, 0x00204460; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 & R0; +R1 = R1 & R1; +R2 = R1 & R2; +R3 = R1 & R3; +R4 = R1 & R4; +R5 = R1 & R5; +R6 = R1 & R6; +R7 = R1 & R7; +CHECKREG r0, 0x01231567; +CHECKREG r1, 0x89AB1DEF; +CHECKREG r2, 0x002818AC; +CHECKREG r3, 0x88A01024; +CHECKREG r4, 0x01011889; +CHECKREG r5, 0x08811145; +CHECKREG r6, 0x88221422; +CHECKREG r7, 0x00201468; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 & R0; +R1 = R2 & R1; +R2 = R2 & R2; +R3 = R2 & R3; +R4 = R2 & R4; +R5 = R2 & R5; +R6 = R2 & R6; +R7 = R2 & R7; +CHECKREG r0, 0x00200024; +CHECKREG r1, 0x0028882C; +CHECKREG r2, 0x56789A2C; +CHECKREG r3, 0x56701224; +CHECKREG r4, 0x02400828; +CHECKREG r5, 0x50100224; +CHECKREG r6, 0x10701020; +CHECKREG r7, 0x12301228; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 & R0; +R1 = R3 & R1; +R2 = R3 & R2; +R3 = R3 & R3; +R4 = R3 & R4; +R5 = R3 & R5; +R6 = R3 & R6; +R7 = R3 & R7; +CHECKREG r0, 0x00200023; +CHECKREG r1, 0x88A00023; +CHECKREG r2, 0x56701233; +CHECKREG r3, 0xDEF01233; +CHECKREG r4, 0x02400013; +CHECKREG r5, 0x58900203; +CHECKREG r6, 0x98701033; +CHECKREG r7, 0x12301233; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 & R0; +R1 = R4 & R1; +R2 = R4 & R2; +R3 = R4 & R3; +R4 = R4 & R4; +R5 = R4 & R5; +R6 = R4 & R6; +R7 = R4 & R7; +CHECKREG r0, 0x41014001; +CHECKREG r1, 0x41014889; +CHECKREG r2, 0x42400898; +CHECKREG r3, 0x42400010; +CHECKREG r4, 0x43456899; +CHECKREG r5, 0x40012001; +CHECKREG r6, 0x40444010; +CHECKREG r7, 0x42044018; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 & R0; +R1 = R5 & R1; +R2 = R5 & R2; +R3 = R5 & R3; +R4 = R5 & R4; +R5 = R5 & R5; +R6 = R5 & R6; +R7 = R5 & R7; +CHECKREG r0, 0x05010145; +CHECKREG r1, 0x05810145; +CHECKREG r2, 0x55100204; +CHECKREG r3, 0x55900204; +CHECKREG r4, 0x25012001; +CHECKREG r5, 0x75912345; +CHECKREG r6, 0x15100000; +CHECKREG r7, 0x15100240; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 & R0; +R1 = R6 & R1; +R2 = R6 & R2; +R3 = R6 & R3; +R4 = R6 & R4; +R5 = R6 & R5; +R6 = R6 & R6; +R7 = R6 & R7; +CHECKREG r0, 0x00264422; +CHECKREG r1, 0x88264422; +CHECKREG r2, 0x10761030; +CHECKREG r3, 0x98761030; +CHECKREG r4, 0x00464010; +CHECKREG r5, 0x18160000; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x10365430; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 & R0; +R1 = R7 & R1; +R2 = R7 & R2; +R3 = R7 & R3; +R4 = R7 & R4; +R5 = R7 & R5; +R6 = R7 & R6; +R7 = R7 & R7; +CHECKREG r0, 0x00205460; +CHECKREG r1, 0x00205468; +CHECKREG r2, 0x12305238; +CHECKREG r3, 0x12305230; +CHECKREG r4, 0x02045018; +CHECKREG r5, 0x10105240; +CHECKREG r6, 0x10345430; +CHECKREG r7, 0x12345678; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 & R0; +R1 = R2 & R0; +R2 = R3 & R0; +R3 = R4 & R0; +R4 = R5 & R0; +R5 = R6 & R0; +R6 = R7 & R0; +R7 = R0 & R0; +CHECKREG r0, 0x01234567; +CHECKREG r1, 0x00000024; +CHECKREG r2, 0x00210024; +CHECKREG r3, 0x01010001; +CHECKREG r4, 0x00010145; +CHECKREG r5, 0x00224402; +CHECKREG r6, 0x00204461; +CHECKREG r7, 0x01234567; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 & R1; +R1 = R3 & R1; +R2 = R4 & R1; +R3 = R5 & R1; +R4 = R6 & R1; +R5 = R7 & R1; +R6 = R0 & R1; +R7 = R1 & R1; +CHECKREG r0, 0x002818AC; +CHECKREG r1, 0x08201024; +CHECKREG r2, 0x00001000; +CHECKREG r3, 0x08000004; +CHECKREG r4, 0x08201020; +CHECKREG r5, 0x00201020; +CHECKREG r6, 0x00201024; +CHECKREG r7, 0x08201024; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 & R2; +R1 = R5 & R2; +R2 = R6 & R2; +R3 = R7 & R2; +R4 = R0 & R2; +R5 = R1 & R2; +R6 = R2 & R2; +R7 = R3 & R2; +CHECKREG r0, 0x02410228; +CHECKREG r1, 0x50310224; +CHECKREG r2, 0x10731020; +CHECKREG r3, 0x10301020; +CHECKREG r4, 0x00410020; +CHECKREG r5, 0x10310020; +CHECKREG r6, 0x10731020; +CHECKREG r7, 0x10301020; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 & R3; +R1 = R6 & R3; +R2 = R7 & R3; +R3 = R0 & R3; +R4 = R1 & R3; +R5 = R2 & R3; +R6 = R3 & R3; +R7 = R4 & R3; +CHECKREG r0, 0x48400200; +CHECKREG r1, 0x08704030; +CHECKREG r2, 0x02304233; +CHECKREG r3, 0x48400200; +CHECKREG r4, 0x08400000; +CHECKREG r5, 0x00000200; +CHECKREG r6, 0x48400200; +CHECKREG r7, 0x08400000; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 & R4; +R1 = R7 & R4; +R2 = R0 & R4; +R3 = R1 & R4; +R4 = R2 & R4; +R5 = R3 & R4; +R6 = R4 & R4; +R7 = R5 & R4; +CHECKREG r0, 0x40444010; +CHECKREG r1, 0x42054018; +CHECKREG r2, 0x40444010; +CHECKREG r3, 0x42054018; +CHECKREG r4, 0x40444010; +CHECKREG r5, 0x40044010; +CHECKREG r6, 0x40444010; +CHECKREG r7, 0x40044010; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 & R5; +R1 = R0 & R5; +R2 = R1 & R5; +R3 = R2 & R5; +R4 = R3 & R5; +R5 = R4 & R5; +R6 = R5 & R5; +R7 = R6 & R5; +CHECKREG r0, 0x15140240; +CHECKREG r1, 0x15140240; +CHECKREG r2, 0x15140240; +CHECKREG r3, 0x15140240; +CHECKREG r4, 0x15140240; +CHECKREG r5, 0x15140240; +CHECKREG r6, 0x15140240; +CHECKREG r7, 0x15140240; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 & R6; +R1 = R0 & R6; +R2 = R1 & R6; +R3 = R2 & R6; +R4 = R3 & R6; +R5 = R4 & R6; +R6 = R5 & R6; +R7 = R6 & R6; +CHECKREG r0, 0x10365430; +CHECKREG r1, 0x10365430; +CHECKREG r2, 0x10365430; +CHECKREG r3, 0x10365430; +CHECKREG r4, 0x10365430; +CHECKREG r5, 0x10365430; +CHECKREG r6, 0x10365430; +CHECKREG r7, 0x10365430; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 & R7; +R1 = R2 & R7; +R2 = R3 & R7; +R3 = R4 & R7; +R4 = R5 & R7; +R5 = R6 & R7; +R6 = R7 & R7; +R7 = R0 & R7; +CHECKREG r0, 0x00200068; +CHECKREG r1, 0x12000208; +CHECKREG r2, 0x02300238; +CHECKREG r3, 0x00048018; +CHECKREG r4, 0x10000040; +CHECKREG r5, 0x10300400; +CHECKREG r6, 0x12348678; +CHECKREG r7, 0x00200068; + + +pass diff --git a/tests/tcg/bfin/c_comp3op_dr_minus_dr.s b/tests/tcg/bfin/c_comp3op_dr_minus_dr.s new file mode 100644 index 0000000000000..ebf2b0bd937fb --- /dev/null +++ b/tests/tcg/bfin/c_comp3op_dr_minus_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_minus_dr/c_comp3op_dr_minus_dr.dsp +// Spec Reference: comp3op dregs - dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 - R0; +R1 = R0 - R1; +R2 = R0 - R2; +R3 = R0 - R3; +R4 = R0 - R4; +R5 = R0 - R5; +R6 = R0 - R6; +R7 = R0 - R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x76543211; +CHECKREG r2, 0xA9876544; +CHECKREG r3, 0x210FEDCC; +CHECKREG r4, 0xDCBA9767; +CHECKREG r5, 0x876EDCBB; +CHECKREG r6, 0x6789ABCE; +CHECKREG r7, 0xEDCBA988; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 - R0; +R1 = R1 - R1; +R2 = R1 - R2; +R3 = R1 - R3; +R4 = R1 - R4; +R5 = R1 - R5; +R6 = R1 - R6; +R7 = R1 - R7; +CHECKREG r0, 0x88880888; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xA987E544; +CHECKREG r3, 0x210FEDCC; +CHECKREG r4, 0xDCBAE767; +CHECKREG r5, 0x876EECBB; +CHECKREG r6, 0x6789EBCE; +CHECKREG r7, 0xEDCBE988; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 - R0; +R1 = R2 - R1; +R2 = R2 - R2; +R3 = R2 - R3; +R4 = R2 - R4; +R5 = R2 - R5; +R6 = R2 - R6; +R7 = R2 - R7; +CHECKREG r0, 0x55555505; +CHECKREG r1, 0xCCCCCCFD; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x210FEDDC; +CHECKREG r4, 0xDCBA97D7; +CHECKREG r5, 0x876EDCDB; +CHECKREG r6, 0x6789ABDE; +CHECKREG r7, 0xEDCBA9D8; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 - R0; +R1 = R3 - R1; +R2 = R3 - R2; +R3 = R3 - R3; +R4 = R3 - R4; +R5 = R3 - R5; +R6 = R3 - R6; +R7 = R3 - R7; +CHECKREG r0, 0xDDCCCCD0; +CHECKREG r1, 0x55444450; +CHECKREG r2, 0x88777780; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xDCBA976D; +CHECKREG r5, 0x876EDCBD; +CHECKREG r6, 0x6789ABCD; +CHECKREG r7, 0xEDCBA98D; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 - R0; +R1 = R4 - R1; +R2 = R4 - R2; +R3 = R4 - R3; +R4 = R4 - R4; +R5 = R4 - R5; +R6 = R4 - R6; +R7 = R4 - R7; +CHECKREG r0, 0x02222332; +CHECKREG r1, 0xF9999AAA; +CHECKREG r2, 0xFCCCCDDD; +CHECKREG r3, 0xF4555665; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0xB76EDCBB; +CHECKREG r6, 0xB789ABCE; +CHECKREG r7, 0xBDCBA988; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 - R0; +R1 = R5 - R1; +R2 = R5 - R2; +R3 = R5 - R3; +R4 = R5 - R4; +R5 = R5 - R5; +R6 = R5 - R6; +R7 = R5 - R7; +CHECKREG r0, 0x706DDDDE; +CHECKREG r1, 0xEFE55556; +CHECKREG r2, 0x20188889; +CHECKREG r3, 0x9FA11111; +CHECKREG r4, 0x504BBAAC; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x6A89ABCE; +CHECKREG r7, 0xEACBA988; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 - R0; +R1 = R6 - R1; +R2 = R6 - R2; +R3 = R6 - R3; +R4 = R6 - R4; +R5 = R6 - R5; +R6 = R6 - R6; +R7 = R6 - R7; +CHECKREG r0, 0x97500ECB; +CHECKREG r1, 0x0ECF8643; +CHECKREG r2, 0x41FFB976; +CHECKREG r3, 0xB98041FE; +CHECKREG r4, 0x752FEB99; +CHECKREG r5, 0x1FE030ED; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xEDC9A988; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 - R0; +R1 = R7 - R1; +R2 = R7 - R2; +R3 = R7 - R3; +R4 = R7 - R4; +R5 = R7 - R5; +R6 = R7 - R6; +R7 = R7 - R7; +CHECKREG r0, 0x1110E111; +CHECKREG r1, 0x8888D889; +CHECKREG r2, 0xBBBBDBBC; +CHECKREG r3, 0x3343E444; +CHECKREG r4, 0xEEEEDDDF; +CHECKREG r5, 0x99A2E333; +CHECKREG r6, 0x79BDE246; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 - R0; +R1 = R2 - R0; +R2 = R3 - R0; +R3 = R4 - R0; +R4 = R5 - R0; +R5 = R6 - R0; +R6 = R7 - R0; +R7 = R0 - R0; +CHECKREG r0, 0x70888888; +CHECKREG r1, 0xE5901234; +CHECKREG r2, 0x6E6889AC; +CHECKREG r3, 0xB2BC9011; +CHECKREG r4, 0x080898BD; +CHECKREG r5, 0x27EDCB8A; +CHECKREG r6, 0xA1ABCDE9; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 - R1; +R1 = R3 - R1; +R2 = R4 - R1; +R3 = R5 - R1; +R4 = R6 - R1; +R5 = R7 - R1; +R6 = R0 - R1; +R7 = R1 - R1; +CHECKREG r0, 0x28CCFCCD; +CHECKREG r1, 0xB474F445; +CHECKREG r2, 0x6ECD2454; +CHECKREG r3, 0xC41C2F00; +CHECKREG r4, 0xE4011DED; +CHECKREG r5, 0x5DBF21E3; +CHECKREG r6, 0x74580888; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 - R2; +R1 = R5 - R2; +R2 = R6 - R2; +R3 = R7 - R2; +R4 = R0 - R2; +R5 = R1 - R2; +R6 = R2 - R2; +R7 = R3 - R2; +CHECKREG r0, 0xCCD1C8FD; +CHECKREG r1, 0x21BD8909; +CHECKREG r2, 0x41FFB9F7; +CHECKREG r3, 0xD0347C31; +CHECKREG r4, 0x8AD20F06; +CHECKREG r5, 0xDFBDCF12; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x8E34C23A; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 - R3; +R1 = R6 - R3; +R2 = R7 - R3; +R3 = R0 - R3; +R4 = R1 - R3; +R5 = R2 - R3; +R6 = R3 - R3; +R7 = R4 - R3; +CHECKREG r0, 0x2950E111; +CHECKREG r1, 0x49841201; +CHECKREG r2, 0xC3440440; +CHECKREG r3, 0xDA609EDE; +CHECKREG r4, 0x6F237323; +CHECKREG r5, 0xE8E36562; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x94C2D445; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 - R4; +R1 = R7 - R4; +R2 = R0 - R4; +R3 = R1 - R4; +R4 = R2 - R4; +R5 = R3 - R4; +R6 = R4 - R4; +R7 = R5 - R4; +CHECKREG r0, 0xF510EB99; +CHECKREG r1, 0xEEEFEDDF; +CHECKREG r2, 0xA1CB8300; +CHECKREG r3, 0x9BAA8546; +CHECKREG r4, 0x4E861A67; +CHECKREG r5, 0x4D246ADF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFE9E5078; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 - R5; +R1 = R0 - R5; +R2 = R1 - R5; +R3 = R2 - R5; +R4 = R3 - R5; +R5 = R4 - R5; +R6 = R5 - R5; +R7 = R6 - R5; +CHECKREG r0, 0x9F9E3333; +CHECKREG r1, 0x2A080FEE; +CHECKREG r2, 0xB471ECA9; +CHECKREG r3, 0x3EDBC964; +CHECKREG r4, 0xC945A61F; +CHECKREG r5, 0x53AF82DA; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xAC507D26; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 - R6; +R1 = R0 - R6; +R2 = R1 - R6; +R3 = R2 - R6; +R4 = R3 - R6; +R5 = R4 - R6; +R6 = R5 - R6; +R7 = R6 - R6; +CHECKREG r0, 0x79C10246; +CHECKREG r1, 0xE14AAE14; +CHECKREG r2, 0x48D459E2; +CHECKREG r3, 0xB05E05B0; +CHECKREG r4, 0x17E7B17E; +CHECKREG r5, 0x7F715D4C; +CHECKREG r6, 0xE6FB091A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 - R7; +R1 = R2 - R7; +R2 = R3 - R7; +R3 = R4 - R7; +R4 = R5 - R7; +R5 = R6 - R7; +R6 = R7 - R7; +R7 = R0 - R7; +CHECKREG r0, 0x7676F277; +CHECKREG r1, 0x4453F414; +CHECKREG r2, 0x7CC3EBC0; +CHECKREG r3, 0x16110221; +CHECKREG r4, 0x664CF1CD; +CHECKREG r5, 0x8643EE0A; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x64426BFF; + + +pass diff --git a/tests/tcg/bfin/c_comp3op_dr_mix.s b/tests/tcg/bfin/c_comp3op_dr_mix.s new file mode 100644 index 0000000000000..492091866f50a --- /dev/null +++ b/tests/tcg/bfin/c_comp3op_dr_mix.s @@ -0,0 +1,237 @@ +//Original:/testcases/core/c_comp3op_dr_mix/c_comp3op_dr_mix.dsp +// Spec Reference: comp3op dregs mix +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 + R0; +R1 = R0 - R1; +R2 = R0 & R2; +R3 = R0 | R3; +R4 = R0 & R4; +R5 = R0 & R5; +R6 = R0 | R6; +R7 = R0 & R7; +CHECKREG r0, 0x02468ACE; +CHECKREG r1, 0x789ABCDF; +CHECKREG r2, 0x02408A8C; +CHECKREG r3, 0xDEF69AFE; +CHECKREG r4, 0x02440888; +CHECKREG r5, 0x00000244; +CHECKREG r6, 0x9A76DEFE; +CHECKREG r7, 0x02040248; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 + R0; +R1 = R1 - R1; +R2 = R1 & R2; +R3 = R1 | R3; +R4 = R1 & R4; +R5 = R1 & R5; +R6 = R1 | R6; +R7 = R1 & R7; +CHECKREG r0, 0x8ACE3356; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xDEF01234; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x98761432; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 + R0; +R1 = R2 - R1; +R2 = R2 & R2; +R3 = R2 | R3; +R4 = R2 & R4; +R5 = R2 & R5; +R6 = R2 | R6; +R7 = R2 & R7; +CHECKREG r0, 0x579BDF53; +CHECKREG r1, 0xCCCCCCFD; +CHECKREG r2, 0x56789A2C; +CHECKREG r3, 0xDEF89A2C; +CHECKREG r4, 0x02400828; +CHECKREG r5, 0x50100224; +CHECKREG r6, 0xDE7EDE2E; +CHECKREG r7, 0x12301228; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 + R0; +R1 = R3 - R1; +R2 = R3 & R2; +R3 = R3 | R3; +R4 = R3 & R4; +R5 = R3 - R5; +R6 = R3 | R6; +R7 = R3 & R7; +CHECKREG r0, 0xE0135796; +CHECKREG r1, 0x55444450; +CHECKREG r2, 0x56701233; +CHECKREG r3, 0xDEF01233; +CHECKREG r4, 0x02400013; +CHECKREG r5, 0x665EEEF0; +CHECKREG r6, 0xDEF65633; +CHECKREG r7, 0x12301233; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 + R0; +R1 = R4 - R1; +R2 = R4 & R2; +R3 = R4 | R3; +R4 = R4 & R4; +R5 = R4 & R5; +R6 = R4 | R6; +R7 = R4 & R7; +CHECKREG r0, 0x8468AE00; +CHECKREG r1, 0xF9999AAA; +CHECKREG r2, 0x42400898; +CHECKREG r3, 0x4FF57ABD; +CHECKREG r4, 0x43456899; +CHECKREG r5, 0x40012001; +CHECKREG r6, 0x4B777CBB; +CHECKREG r7, 0x42044018; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 + R0; +R1 = R5 - R1; +R2 = R5 & R2; +R3 = R5 | R3; +R4 = R5 & R4; +R5 = R5 & R5; +R6 = R5 | R6; +R7 = R5 & R7; +CHECKREG r0, 0x7AB468AC; +CHECKREG r1, 0xEFE55556; +CHECKREG r2, 0x55100204; +CHECKREG r3, 0xF5F13375; +CHECKREG r4, 0x25012001; +CHECKREG r5, 0x75912345; +CHECKREG r6, 0xF5F77777; +CHECKREG r7, 0x15100240; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 + R0; +R1 = R6 - R1; +R2 = R6 & R2; +R3 = R6 | R3; +R4 = R6 & R4; +R5 = R6 & R5; +R6 = R6 | R6; +R7 = R6 & R7; +CHECKREG r0, 0x999C9999; +CHECKREG r1, 0x0ECF8643; +CHECKREG r2, 0x10761030; +CHECKREG r3, 0xDEF65636; +CHECKREG r4, 0x00464010; +CHECKREG r5, 0x18160000; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x10365430; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 + R0; +R1 = R7 - R1; +R2 = R7 & R2; +R3 = R7 | R3; +R4 = R7 & R4; +R5 = R7 - R5; +R6 = R7 | R6; +R7 = R7 & R7; +CHECKREG r0, 0x1357CBDF; +CHECKREG r1, 0x8888D889; +CHECKREG r2, 0x12305238; +CHECKREG r3, 0xDEF4767C; +CHECKREG r4, 0x02045018; +CHECKREG r5, 0x99A2E333; +CHECKREG r6, 0x9A76767A; +CHECKREG r7, 0x12345678; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; + + +R0 = R1 + R2; +R1 = R3 - R2; +R2 = R4 & R3; +R3 = R5 | R4; +R4 = R6 & R7; +CHECKREG r0, 0x00060008; +CHECKREG r1, 0x00020002; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x000A000B; +CHECKREG r4, 0x000C000D; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000e000f; + + +pass diff --git a/tests/tcg/bfin/c_comp3op_dr_or_dr.s b/tests/tcg/bfin/c_comp3op_dr_or_dr.s new file mode 100644 index 0000000000000..36e6401f67838 --- /dev/null +++ b/tests/tcg/bfin/c_comp3op_dr_or_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_or_dr/c_comp3op_dr_or_dr.dsp +// Spec Reference: comp3op dregs | dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 | R0; +R1 = R0 | R1; +R2 = R0 | R2; +R3 = R0 | R3; +R4 = R0 | R4; +R5 = R0 | R5; +R6 = R0 | R6; +R7 = R0 | R7; +CHECKREG r0, 0x01234567; +CHECKREG r1, 0x89ABCDEF; +CHECKREG r2, 0x577BDFFF; +CHECKREG r3, 0xDFF35777; +CHECKREG r4, 0x23676DFF; +CHECKREG r5, 0x79B36767; +CHECKREG r6, 0x99775577; +CHECKREG r7, 0x1337577F; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 | R0; +R1 = R1 | R1; +R2 = R1 | R2; +R3 = R1 | R3; +R4 = R1 | R4; +R5 = R1 | R5; +R6 = R1 | R6; +R7 = R1 | R7; +CHECKREG r0, 0x89AB1DEF; +CHECKREG r1, 0x89AB1DEF; +CHECKREG r2, 0xDFFB1FFF; +CHECKREG r3, 0xDFFB1FFF; +CHECKREG r4, 0xABEF1DFF; +CHECKREG r5, 0xF9BB1FEF; +CHECKREG r6, 0x99FF1DFF; +CHECKREG r7, 0x9BBF1FFF; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 | R0; +R1 = R2 | R1; +R2 = R2 | R2; +R3 = R2 | R3; +R4 = R2 | R4; +R5 = R2 | R5; +R6 = R2 | R6; +R7 = R2 | R7; +CHECKREG r0, 0x577BDF2F; +CHECKREG r1, 0xDFFBDF2F; +CHECKREG r2, 0x56789A2C; +CHECKREG r3, 0xDEF89A2C; +CHECKREG r4, 0x777DFA2D; +CHECKREG r5, 0x7EF9BB2D; +CHECKREG r6, 0xDE7EDE2E; +CHECKREG r7, 0x567CDE2C; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 | R0; +R1 = R3 | R1; +R2 = R3 | R2; +R3 = R3 | R3; +R4 = R3 | R4; +R5 = R3 | R5; +R6 = R3 | R6; +R7 = R3 | R7; +CHECKREG r0, 0xDFF35773; +CHECKREG r1, 0xDFFBDFF3; +CHECKREG r2, 0xDEF89AB3; +CHECKREG r3, 0xDEF01233; +CHECKREG r4, 0xFFF57AB3; +CHECKREG r5, 0xFEF13373; +CHECKREG r6, 0xDEF65633; +CHECKREG r7, 0xDEF45673; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 | R0; +R1 = R4 | R1; +R2 = R4 | R2; +R3 = R4 | R3; +R4 = R4 | R4; +R5 = R4 | R5; +R6 = R4 | R6; +R7 = R4 | R7; +CHECKREG r0, 0x43676DFF; +CHECKREG r1, 0x4BEFEDFF; +CHECKREG r2, 0x477DFABD; +CHECKREG r3, 0x4FF57ABD; +CHECKREG r4, 0x43456899; +CHECKREG r5, 0x4BD56BDD; +CHECKREG r6, 0x4B777CBB; +CHECKREG r7, 0x43757EF9; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 | R0; +R1 = R5 | R1; +R2 = R5 | R2; +R3 = R5 | R3; +R4 = R5 | R4; +R5 = R5 | R5; +R6 = R5 | R6; +R7 = R5 | R7; +CHECKREG r0, 0x75B36767; +CHECKREG r1, 0xF5BBEFEF; +CHECKREG r2, 0x75F9BBFD; +CHECKREG r3, 0xF5F13375; +CHECKREG r4, 0x75D56BDD; +CHECKREG r5, 0x75912345; +CHECKREG r6, 0xF5F77777; +CHECKREG r7, 0x75B5777D; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 | R0; +R1 = R6 | R1; +R2 = R6 | R2; +R3 = R6 | R3; +R4 = R6 | R4; +R5 = R6 | R5; +R6 = R6 | R6; +R7 = R6 | R7; +CHECKREG r0, 0x99765577; +CHECKREG r1, 0x99F6DDFF; +CHECKREG r2, 0xDE76DEBE; +CHECKREG r3, 0xDEF65636; +CHECKREG r4, 0xBB767CBB; +CHECKREG r5, 0xF8F67777; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x9A76567A; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 | R0; +R1 = R7 | R1; +R2 = R7 | R2; +R3 = R7 | R3; +R4 = R7 | R4; +R5 = R7 | R5; +R6 = R7 | R6; +R7 = R7 | R7; +CHECKREG r0, 0x1337777F; +CHECKREG r1, 0x9BBF7FFF; +CHECKREG r2, 0x567C7EFC; +CHECKREG r3, 0xDEF4767C; +CHECKREG r4, 0x33757EF9; +CHECKREG r5, 0x7AB5777D; +CHECKREG r6, 0x9A76767A; +CHECKREG r7, 0x12345678; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 | R0; +R1 = R2 | R0; +R2 = R3 | R0; +R3 = R4 | R0; +R4 = R5 | R0; +R5 = R6 | R0; +R6 = R7 | R0; +R7 = R0 | R0; +CHECKREG r0, 0x91ABCDEF; +CHECKREG r1, 0xD7BBDFFF; +CHECKREG r2, 0xDFFBDFFF; +CHECKREG r3, 0xB3EFDDFF; +CHECKREG r4, 0xF9BBEDEF; +CHECKREG r5, 0x99FFDDFF; +CHECKREG r6, 0x93BFDFFF; +CHECKREG r7, 0x91ABCDEF; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 | R1; +R1 = R3 | R1; +R2 = R4 | R1; +R3 = R5 | R1; +R4 = R6 | R1; +R5 = R7 | R1; +R6 = R0 | R1; +R7 = R1 | R1; +CHECKREG r0, 0x7BFB1FFF; +CHECKREG r1, 0xFFAB1FFF; +CHECKREG r2, 0xFFEB1FFF; +CHECKREG r3, 0xFFBB3FFF; +CHECKREG r4, 0xFFFF1FFF; +CHECKREG r5, 0xFFBF1FFF; +CHECKREG r6, 0xFFFB1FFF; +CHECKREG r7, 0xFFAB1FFF; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 | R2; +R1 = R5 | R2; +R2 = R6 | R2; +R3 = R7 | R2; +R4 = R0 | R2; +R5 = R1 | R2; +R6 = R2 | R2; +R7 = R3 | R2; +CHECKREG r0, 0x7777FB2D; +CHECKREG r1, 0x7E73BB3D; +CHECKREG r2, 0xDE73DE2F; +CHECKREG r3, 0xDE77FE2F; +CHECKREG r4, 0xFF77FF2F; +CHECKREG r5, 0xFE73FF3F; +CHECKREG r6, 0xDE73DE2F; +CHECKREG r7, 0xDE77FE2F; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 | R3; +R1 = R6 | R3; +R2 = R7 | R3; +R3 = R0 | R3; +R4 = R1 | R3; +R5 = R2 | R3; +R6 = R3 | R3; +R7 = R4 | R3; +CHECKREG r0, 0x7EF16377; +CHECKREG r1, 0xDEF45637; +CHECKREG r2, 0x5EF44673; +CHECKREG r3, 0x7EF16377; +CHECKREG r4, 0xFEF57777; +CHECKREG r5, 0x7EF56777; +CHECKREG r6, 0x7EF16377; +CHECKREG r7, 0xFEF57777; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 | R4; +R1 = R7 | R4; +R2 = R0 | R4; +R3 = R1 | R4; +R4 = R2 | R4; +R5 = R3 | R4; +R6 = R4 | R4; +R7 = R5 | R4; +CHECKREG r0, 0x5B577CBB; +CHECKREG r1, 0x53757EF9; +CHECKREG r2, 0x5B577CBB; +CHECKREG r3, 0x53757EF9; +CHECKREG r4, 0x5B577CBB; +CHECKREG r5, 0x5B777EFB; +CHECKREG r6, 0x5B577CBB; +CHECKREG r7, 0x5B777EFB; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 | R5; +R1 = R0 | R5; +R2 = R1 | R5; +R3 = R2 | R5; +R4 = R3 | R5; +R5 = R4 | R5; +R6 = R5 | R5; +R7 = R6 | R5; +CHECKREG r0, 0x75B6777D; +CHECKREG r1, 0x75B6777D; +CHECKREG r2, 0x75B6777D; +CHECKREG r3, 0x75B6777D; +CHECKREG r4, 0x75B6777D; +CHECKREG r5, 0x75B6777D; +CHECKREG r6, 0x75B6777D; +CHECKREG r7, 0x75B6777D; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 | R6; +R1 = R0 | R6; +R2 = R1 | R6; +R3 = R2 | R6; +R4 = R3 | R6; +R5 = R4 | R6; +R6 = R5 | R6; +R7 = R6 | R6; +CHECKREG r0, 0x9A77567A; +CHECKREG r1, 0x9A77567A; +CHECKREG r2, 0x9A77567A; +CHECKREG r3, 0x9A77567A; +CHECKREG r4, 0x9A77567A; +CHECKREG r5, 0x9A77567A; +CHECKREG r6, 0x9A77567A; +CHECKREG r7, 0x9A77567A; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 | R7; +R1 = R2 | R7; +R2 = R3 | R7; +R3 = R4 | R7; +R4 = R5 | R7; +R5 = R6 | R7; +R6 = R7 | R7; +R7 = R0 | R7; +CHECKREG r0, 0x9ABFFEFF; +CHECKREG r1, 0x56BCFEFC; +CHECKREG r2, 0x9EFCF678; +CHECKREG r3, 0x3A758EF9; +CHECKREG r4, 0x7AB5FE7D; +CHECKREG r5, 0x9A7CF6FA; +CHECKREG r6, 0x12348678; +CHECKREG r7, 0x9ABFFEFF; + + +pass diff --git a/tests/tcg/bfin/c_comp3op_dr_plus_dr.s b/tests/tcg/bfin/c_comp3op_dr_plus_dr.s new file mode 100644 index 0000000000000..fff4cb71b6292 --- /dev/null +++ b/tests/tcg/bfin/c_comp3op_dr_plus_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_plus_dr/c_comp3op_dr_plus_dr.dsp +// Spec Reference: comp3op dregs + dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 + R0; +R1 = R0 + R1; +R2 = R0 + R2; +R3 = R0 + R3; +R4 = R0 + R4; +R5 = R0 + R5; +R6 = R0 + R6; +R7 = R0 + R7; +CHECKREG r0, 0x02468ACE; +CHECKREG r1, 0x8BF258BD; +CHECKREG r2, 0x58BF258A; +CHECKREG r3, 0xE1369D02; +CHECKREG r4, 0x258BF367; +CHECKREG r5, 0x7AD7AE13; +CHECKREG r6, 0x9ABCDF00; +CHECKREG r7, 0x147AE146; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 + R0; +R1 = R1 + R1; +R2 = R1 + R2; +R3 = R1 + R3; +R4 = R1 + R4; +R5 = R1 + R5; +R6 = R1 + R6; +R7 = R1 + R7; +CHECKREG r0, 0x8ACE3356; +CHECKREG r1, 0x13563BDE; +CHECKREG r2, 0x69CE569A; +CHECKREG r3, 0xF2464E12; +CHECKREG r4, 0x369B5477; +CHECKREG r5, 0x8BE74F23; +CHECKREG r6, 0xABCC5010; +CHECKREG r7, 0x258A5256; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 + R0; +R1 = R2 + R1; +R2 = R2 + R2; +R3 = R2 + R3; +R4 = R2 + R4; +R5 = R2 + R5; +R6 = R2 + R6; +R7 = R2 + R7; +CHECKREG r0, 0x579BDF53; +CHECKREG r1, 0xE024675B; +CHECKREG r2, 0xACF13458; +CHECKREG r3, 0x8BE1467C; +CHECKREG r4, 0xD0369C81; +CHECKREG r5, 0x2582577D; +CHECKREG r6, 0x4567887A; +CHECKREG r7, 0xBF258A80; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 + R0; +R1 = R3 + R1; +R2 = R3 + R2; +R3 = R3 + R3; +R4 = R3 + R4; +R5 = R3 + R5; +R6 = R3 + R6; +R7 = R3 + R7; +CHECKREG r0, 0xE0135796; +CHECKREG r1, 0x689BE016; +CHECKREG r2, 0x3568ACE6; +CHECKREG r3, 0xBDE02466; +CHECKREG r4, 0xE1258CF9; +CHECKREG r5, 0x367147A9; +CHECKREG r6, 0x56567899; +CHECKREG r7, 0xD0147AD9; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 + R0; +R1 = R4 + R1; +R2 = R4 + R2; +R3 = R4 + R3; +R4 = R4 + R4; +R5 = R4 + R5; +R6 = R4 + R6; +R7 = R4 + R7; +CHECKREG r0, 0x8468AE00; +CHECKREG r1, 0x8CF13688; +CHECKREG r2, 0x89BE0355; +CHECKREG r3, 0x92357ACD; +CHECKREG r4, 0x868AD132; +CHECKREG r5, 0xCF1BF477; +CHECKREG r6, 0xCF012564; +CHECKREG r7, 0xC8BF27AA; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 + R0; +R1 = R5 + R1; +R2 = R5 + R2; +R3 = R5 + R3; +R4 = R5 + R4; +R5 = R5 + R5; +R6 = R5 + R6; +R7 = R5 + R7; +CHECKREG r0, 0x7AB468AC; +CHECKREG r1, 0xFB3CF134; +CHECKREG r2, 0xCB09BE01; +CHECKREG r3, 0x4B813579; +CHECKREG r4, 0x9AD68BDE; +CHECKREG r5, 0xEB22468A; +CHECKREG r6, 0x80989ABC; +CHECKREG r7, 0x00569D02; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 + R0; +R1 = R6 + R1; +R2 = R6 + R2; +R3 = R6 + R3; +R4 = R6 + R4; +R5 = R6 + R5; +R6 = R6 + R6; +R7 = R6 + R7; +CHECKREG r0, 0x999C9999; +CHECKREG r1, 0x221D2221; +CHECKREG r2, 0xEEECEEEE; +CHECKREG r3, 0x776C6666; +CHECKREG r4, 0xBBBCBCCB; +CHECKREG r5, 0x110C7777; +CHECKREG r6, 0x30ECA864; +CHECKREG r7, 0x4322FEDC; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 + R0; +R1 = R7 + R1; +R2 = R7 + R2; +R3 = R7 + R3; +R4 = R7 + R4; +R5 = R7 + R5; +R6 = R7 + R6; +R7 = R7 + R7; +CHECKREG r0, 0x1357CBDF; +CHECKREG r1, 0x9BDFD467; +CHECKREG r2, 0x68ACD134; +CHECKREG r3, 0xF124C8AC; +CHECKREG r4, 0x3579CF11; +CHECKREG r5, 0x8AC5C9BD; +CHECKREG r6, 0xAAAACAAA; +CHECKREG r7, 0x2468ACF0; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 + R0; +R1 = R2 + R0; +R2 = R3 + R0; +R3 = R4 + R0; +R4 = R5 + R0; +R5 = R6 + R0; +R6 = R7 + R0; +R7 = R0 + R0; +CHECKREG r0, 0x92CF1356; +CHECKREG r1, 0xE8E7AE12; +CHECKREG r2, 0x71C0258A; +CHECKREG r3, 0xB6142BEF; +CHECKREG r4, 0x0B60349B; +CHECKREG r5, 0x2B456768; +CHECKREG r6, 0xA50369C7; +CHECKREG r7, 0x259E26AC; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 + R1; +R1 = R3 + R1; +R2 = R4 + R1; +R3 = R5 + R1; +R4 = R6 + R1; +R5 = R7 + R1; +R6 = R0 + R1; +R7 = R1 + R1; +CHECKREG r0, 0x7C2338AB; +CHECKREG r1, 0x07CB3023; +CHECKREG r2, 0x2B0D48BC; +CHECKREG r3, 0x805C5368; +CHECKREG r4, 0xA0414255; +CHECKREG r5, 0x19FF464B; +CHECKREG r6, 0x83EE68CE; +CHECKREG r7, 0x0F966046; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R3 + R2; +R1 = R4 + R2; +R2 = R5 + R2; +R3 = R6 + R2; +R4 = R7 + R2; +R5 = R0 + R2; +R6 = R1 + R2; +R7 = R2 + R2; +CHECKREG r0, 0x9563CC50; +CHECKREG r1, 0x79B8FD55; +CHECKREG r2, 0xCEA4BD61; +CHECKREG r3, 0x67181184; +CHECKREG r4, 0xE0D8F389; +CHECKREG r5, 0x640889B1; +CHECKREG r6, 0x485DBAB6; +CHECKREG r7, 0x9D497AC2; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R4 + R3; +R1 = R5 + R3; +R2 = R6 + R3; +R3 = R7 + R3; +R4 = R0 + R3; +R5 = R1 + R3; +R6 = R2 + R3; +R7 = R3 + R3; +CHECKREG r0, 0x7335A6C6; +CHECKREG r1, 0xC7316577; +CHECKREG r2, 0xE7649667; +CHECKREG r3, 0x612488A6; +CHECKREG r4, 0xD45A2F6C; +CHECKREG r5, 0x2855EE1D; +CHECKREG r6, 0x48891F0D; +CHECKREG r7, 0xC249114C; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R5 + R4; +R1 = R6 + R4; +R2 = R7 + R4; +R3 = R0 + R4; +R4 = R1 + R4; +R5 = R2 + R4; +R6 = R3 + R4; +R7 = R4 + R4; +CHECKREG r0, 0x98D68BDE; +CHECKREG r1, 0x9B9BBCCB; +CHECKREG r2, 0x957ABF11; +CHECKREG r3, 0xEC1BF477; +CHECKREG r4, 0xEEE12564; +CHECKREG r5, 0x845BE475; +CHECKREG r6, 0xDAFD19DB; +CHECKREG r7, 0xDDC24AC8; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R6 + R5; +R1 = R7 + R5; +R2 = R0 + R5; +R3 = R1 + R5; +R4 = R2 + R5; +R5 = R3 + R5; +R6 = R4 + R5; +R7 = R5 + R5; +CHECKREG r0, 0x0B0C8777; +CHECKREG r1, 0x8ACA79BD; +CHECKREG r2, 0x80A2AABC; +CHECKREG r3, 0x00609D02; +CHECKREG r4, 0xF638CE01; +CHECKREG r5, 0x75F6C047; +CHECKREG r6, 0x6C2F8E48; +CHECKREG r7, 0xEBED808E; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 + R6; +R1 = R0 + R6; +R2 = R1 + R6; +R3 = R2 + R6; +R4 = R3 + R6; +R5 = R4 + R6; +R6 = R5 + R6; +R7 = R6 + R6; +CHECKREG r0, 0xAAADAAAA; +CHECKREG r1, 0x4323FEDC; +CHECKREG r2, 0xDB9A530E; +CHECKREG r3, 0x7410A740; +CHECKREG r4, 0x0C86FB72; +CHECKREG r5, 0xA4FD4FA4; +CHECKREG r6, 0x3D73A3D6; +CHECKREG r7, 0x7AE747AC; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 + R7; +R1 = R2 + R7; +R2 = R3 + R7; +R3 = R4 + R7; +R4 = R5 + R7; +R5 = R6 + R7; +R6 = R7 + R7; +R7 = R0 + R7; +CHECKREG r0, 0x9ADFFF67; +CHECKREG r1, 0x68BD0104; +CHECKREG r2, 0xA12CF8B0; +CHECKREG r3, 0x3A7A0F11; +CHECKREG r4, 0x8AB5FEBD; +CHECKREG r5, 0xAAACFAFA; +CHECKREG r6, 0x24690CF0; +CHECKREG r7, 0xAD1485DF; + + +pass diff --git a/tests/tcg/bfin/c_comp3op_dr_xor_dr.s b/tests/tcg/bfin/c_comp3op_dr_xor_dr.s new file mode 100644 index 0000000000000..fa0db63ed567b --- /dev/null +++ b/tests/tcg/bfin/c_comp3op_dr_xor_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_xor_dr/c_comp3op_dr_xor_dr.dsp +// Spec Reference: comp3op dregs xor dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 ^ R0; +R1 = R0 ^ R1; +R2 = R0 ^ R2; +R3 = R0 ^ R3; +R4 = R0 ^ R4; +R5 = R0 ^ R5; +R6 = R0 ^ R6; +R7 = R0 ^ R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x89ABCDEF; +CHECKREG r2, 0x56789ABC; +CHECKREG r3, 0xDEF01234; +CHECKREG r4, 0x23456899; +CHECKREG r5, 0x78912345; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x12345678; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 ^ R0; +R1 = R1 ^ R1; +R2 = R1 ^ R2; +R3 = R1 ^ R3; +R4 = R1 ^ R4; +R5 = R1 ^ R5; +R6 = R1 ^ R6; +R7 = R1 ^ R7; +CHECKREG r0, 0x88880888; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x56781ABC; +CHECKREG r3, 0xDEF01234; +CHECKREG r4, 0x23451899; +CHECKREG r5, 0x78911345; +CHECKREG r6, 0x98761432; +CHECKREG r7, 0x12341678; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 ^ R0; +R1 = R2 ^ R1; +R2 = R2 ^ R2; +R3 = R2 ^ R3; +R4 = R2 ^ R4; +R5 = R2 ^ R5; +R6 = R2 ^ R6; +R7 = R2 ^ R7; +CHECKREG r0, 0x575BDF0B; +CHECKREG r1, 0xDFD35703; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xDEF01224; +CHECKREG r4, 0x23456829; +CHECKREG r5, 0x78912325; +CHECKREG r6, 0x98765422; +CHECKREG r7, 0x12345628; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 ^ R0; +R1 = R3 ^ R1; +R2 = R3 ^ R2; +R3 = R3 ^ R3; +R4 = R3 ^ R4; +R5 = R3 ^ R5; +R6 = R3 ^ R6; +R7 = R3 ^ R7; +CHECKREG r0, 0xDFD35750; +CHECKREG r1, 0x575BDFD0; +CHECKREG r2, 0x88888880; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x23456893; +CHECKREG r5, 0x78912343; +CHECKREG r6, 0x98765433; +CHECKREG r7, 0x12345673; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 ^ R0; +R1 = R4 ^ R1; +R2 = R4 ^ R2; +R3 = R4 ^ R3; +R4 = R4 ^ R4; +R5 = R4 ^ R5; +R6 = R4 ^ R6; +R7 = R4 ^ R7; +CHECKREG r0, 0x02662DFE; +CHECKREG r1, 0x0AEEA576; +CHECKREG r2, 0x053DF225; +CHECKREG r3, 0x0DB57AAD; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x48912345; +CHECKREG r6, 0x48765432; +CHECKREG r7, 0x42345678; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 ^ R0; +R1 = R5 ^ R1; +R2 = R5 ^ R2; +R3 = R5 ^ R3; +R4 = R5 ^ R4; +R5 = R5 ^ R5; +R6 = R5 ^ R6; +R7 = R5 ^ R7; +CHECKREG r0, 0x70B26622; +CHECKREG r1, 0xF03AEEAA; +CHECKREG r2, 0x20E9B9F9; +CHECKREG r3, 0xA0613171; +CHECKREG r4, 0x50D44BDC; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x95765432; +CHECKREG r7, 0x15345678; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 ^ R0; +R1 = R6 ^ R1; +R2 = R6 ^ R2; +R3 = R6 ^ R3; +R4 = R6 ^ R4; +R5 = R6 ^ R5; +R6 = R6 ^ R6; +R7 = R6 ^ R7; +CHECKREG r0, 0x99501155; +CHECKREG r1, 0x11D099DD; +CHECKREG r2, 0xCE00CE8E; +CHECKREG r3, 0x46804606; +CHECKREG r4, 0xBB303CAB; +CHECKREG r5, 0xE0E07777; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x12365678; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 ^ R0; +R1 = R7 ^ R1; +R2 = R7 ^ R2; +R3 = R7 ^ R3; +R4 = R7 ^ R4; +R5 = R7 ^ R5; +R6 = R7 ^ R6; +R7 = R7 ^ R7; +CHECKREG r0, 0x1317231F; +CHECKREG r1, 0x9B9F2B97; +CHECKREG r2, 0x444C2CC4; +CHECKREG r3, 0xCCC4244C; +CHECKREG r4, 0x31712EE1; +CHECKREG r5, 0x6AA5253D; +CHECKREG r6, 0x8A42224A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 ^ R0; +R1 = R2 ^ R0; +R2 = R3 ^ R0; +R3 = R4 ^ R0; +R4 = R5 ^ R0; +R5 = R6 ^ R0; +R6 = R7 ^ R0; +R7 = R0 ^ R0; +CHECKREG r0, 0x90888888; +CHECKREG r1, 0xC6901234; +CHECKREG r2, 0x4E799ABC; +CHECKREG r3, 0xB3CD9011; +CHECKREG r4, 0xE819A9CD; +CHECKREG r5, 0x08FEDC9A; +CHECKREG r6, 0x82BCDEF9; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 ^ R1; +R1 = R3 ^ R1; +R2 = R4 ^ R1; +R3 = R5 ^ R1; +R4 = R6 ^ R1; +R5 = R7 ^ R1; +R6 = R0 ^ R1; +R7 = R1 ^ R1; +CHECKREG r0, 0x7BD30753; +CHECKREG r1, 0xF78B0FDB; +CHECKREG r2, 0xD4C91742; +CHECKREG r3, 0x8F1A2C9E; +CHECKREG r4, 0x6FFD1DE9; +CHECKREG r5, 0xE5BF19F3; +CHECKREG r6, 0x8C580888; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 ^ R2; +R1 = R5 ^ R2; +R2 = R6 ^ R2; +R3 = R7 ^ R2; +R4 = R0 ^ R2; +R5 = R1 ^ R2; +R6 = R2 ^ R2; +R7 = R3 ^ R2; +CHECKREG r0, 0x7536F905; +CHECKREG r1, 0x2E42B919; +CHECKREG r2, 0xCE00CE0F; +CHECKREG r3, 0xDC34F827; +CHECKREG r4, 0xBB36370A; +CHECKREG r5, 0xE0427716; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x12343628; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 ^ R3; +R1 = R6 ^ R3; +R2 = R7 ^ R3; +R3 = R0 ^ R3; +R4 = R1 ^ R3; +R5 = R2 ^ R3; +R6 = R3 ^ R3; +R7 = R4 ^ R3; +CHECKREG r0, 0x36B16177; +CHECKREG r1, 0xD6841607; +CHECKREG r2, 0x5CC40440; +CHECKREG r3, 0x78412344; +CHECKREG r4, 0xAEC53543; +CHECKREG r5, 0x24852704; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xD6841607; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 ^ R4; +R1 = R7 ^ R4; +R2 = R0 ^ R4; +R3 = R1 ^ R4; +R4 = R2 ^ R4; +R5 = R3 ^ R4; +R6 = R4 ^ R4; +R7 = R5 ^ R4; +CHECKREG r0, 0x1B133CAB; +CHECKREG r1, 0x11703EE1; +CHECKREG r2, 0x48565432; +CHECKREG r3, 0x42355678; +CHECKREG r4, 0x1B133CAB; +CHECKREG r5, 0x59266AD3; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x42355678; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 ^ R5; +R1 = R0 ^ R5; +R2 = R1 ^ R5; +R3 = R2 ^ R5; +R4 = R3 ^ R5; +R5 = R4 ^ R5; +R6 = R5 ^ R5; +R7 = R6 ^ R5; +CHECKREG r0, 0x60A2753D; +CHECKREG r1, 0x15345678; +CHECKREG r2, 0x60A2753D; +CHECKREG r3, 0x15345678; +CHECKREG r4, 0x60A2753D; +CHECKREG r5, 0x15345678; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x15345678; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 ^ R6; +R1 = R0 ^ R6; +R2 = R1 ^ R6; +R3 = R2 ^ R6; +R4 = R3 ^ R6; +R5 = R4 ^ R6; +R6 = R5 ^ R6; +R7 = R6 ^ R6; +CHECKREG r0, 0x8A41024A; +CHECKREG r1, 0x12375678; +CHECKREG r2, 0x8A41024A; +CHECKREG r3, 0x12375678; +CHECKREG r4, 0x8A41024A; +CHECKREG r5, 0x12375678; +CHECKREG r6, 0x8A41024A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 ^ R7; +R1 = R2 ^ R7; +R2 = R3 ^ R7; +R3 = R4 ^ R7; +R4 = R5 ^ R7; +R5 = R6 ^ R7; +R6 = R7 ^ R7; +R7 = R0 ^ R7; +CHECKREG r0, 0x9A9FFE97; +CHECKREG r1, 0x44BCFCF4; +CHECKREG r2, 0x9CCCF440; +CHECKREG r3, 0x3A710EE1; +CHECKREG r4, 0x6AB5FE3D; +CHECKREG r5, 0x8A4CF2FA; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x88AB78EF; + + +pass diff --git a/tests/tcg/bfin/c_comp3op_pr_plus_pr_sh1.s b/tests/tcg/bfin/c_comp3op_pr_plus_pr_sh1.s new file mode 100644 index 0000000000000..f570a5f1fb6da --- /dev/null +++ b/tests/tcg/bfin/c_comp3op_pr_plus_pr_sh1.s @@ -0,0 +1,302 @@ +//Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh1/c_comp3op_pr_plus_pr_sh1.dsp +// Spec Reference: comp3op pregs + pregs << 1 +# mach: bfin + +.include "testutils.inc" + start + + imm32 p1, 0x89ab1def; + imm32 p2, 0x56781abc; + imm32 p3, 0xdef01234; + imm32 p4, 0x23451899; + imm32 p5, 0x78911345; + imm32 sp, 0x98761432; + imm32 fp, 0x12341678; + P1 = P1 + ( P1 << 1 ); + P2 = P1 + ( P2 << 1 ); + P3 = P1 + ( P3 << 1 ); + P4 = P1 + ( P4 << 1 ); + P5 = P1 + ( P5 << 1 ); + SP = P1 + ( SP << 1 ); + FP = P1 + FP; + CHECKREG p1, 0x9D0159CD; + CHECKREG p2, 0x49F18F45; + CHECKREG p3, 0x5AE17E35; + CHECKREG p4, 0xE38B8AFF; + CHECKREG p5, 0x8E238057; + CHECKREG sp, 0xCDED8231; + CHECKREG fp, 0xAF357045; + + imm32 p1, 0x89abcd2f; + imm32 p2, 0x56789a2c; + imm32 p3, 0xdef01224; + imm32 p4, 0x23456829; + imm32 p5, 0x78912325; + imm32 sp, 0x98765422; + imm32 fp, 0x12345628; + P1 = P2 + ( P1 << 1 ); + P2 = P2 + ( P2 << 1 ); + P3 = P2 + ( P3 << 1 ); + P4 = P2 + ( P4 << 1 ); + P5 = P2 + ( P5 << 1 ); + SP = P2 + ( SP << 1 ); + FP = P2 + ( FP << 1 ); + CHECKREG p1, 0x69D0348A; + CHECKREG p2, 0x0369CE84; + CHECKREG p3, 0xC149F2CC; + CHECKREG p4, 0x49F49ED6; + CHECKREG p5, 0xF48C14CE; + CHECKREG sp, 0x345676C8; + CHECKREG fp, 0x27D27AD4; + + imm32 p1, 0x89abcde3; + imm32 p2, 0x56789ab3; + imm32 p3, 0xdef01233; + imm32 p4, 0x23456893; + imm32 p5, 0x78912343; + imm32 sp, 0x98765433; + imm32 fp, 0x12345673; + P1 = P3 + ( P1 << 1 ); + P2 = P3 + ( P2 << 1 ); + P3 = P3 + ( P3 << 1 ); + P4 = P3 + ( P4 << 1 ); + P5 = P3 + ( P5 << 1 ); + SP = P3 + ( SP << 1 ); + FP = P3 + ( FP << 1 ); + CHECKREG p1, 0xF247ADF9; + CHECKREG p2, 0x8BE14799; + CHECKREG p3, 0x9CD03699; + CHECKREG p4, 0xE35B07BF; + CHECKREG p5, 0x8DF27D1F; + CHECKREG sp, 0xCDBCDEFF; + CHECKREG fp, 0xC138E37F; + + imm32 p1, 0x49abcdef; + imm32 p2, 0x46789abc; + imm32 p3, 0x4ef01234; + imm32 p4, 0x43456899; + imm32 p5, 0x48912345; + imm32 sp, 0x48765432; + imm32 fp, 0x42345678; + P1 = P4 + ( P1 << 1 ); + P2 = P4 + ( P2 << 1 ); + P3 = P4 + ( P3 << 1 ); + P4 = P4 + ( P4 << 1 ); + P5 = P4 + ( P5 << 1 ); + SP = P4 + ( SP << 1 ); + FP = P4 + ( FP << 1 ); + CHECKREG p1, 0xD69D0477; + CHECKREG p2, 0xD0369E11; + CHECKREG p3, 0xE1258D01; + CHECKREG p4, 0xC9D039CB; + CHECKREG p5, 0x5AF28055; + CHECKREG sp, 0x5ABCE22F; + CHECKREG fp, 0x4E38E6BB; + + imm32 p1, 0x85abcdef; + imm32 p2, 0x55789abc; + imm32 p3, 0xd5f01234; + imm32 p4, 0x25456899; + imm32 p5, 0x75912345; + imm32 sp, 0x95765432; + imm32 fp, 0x15345678; + P1 = P5 + ( P1 << 1 ); + P2 = P5 + ( P2 << 1 ); + P3 = P5 + ( P3 << 1 ); + P4 = P5 + ( P4 << 1 ); + P5 = P5 + ( P5 << 1 ); + SP = P5 + ( SP << 1 ); + FP = P5 + ( FP << 1 ); + CHECKREG p1, 0x80E8BF23; + CHECKREG p2, 0x208258BD; + CHECKREG p3, 0x217147AD; + CHECKREG p4, 0xC01BF477; + CHECKREG p5, 0x60B369CF; + CHECKREG sp, 0x8BA01233; + CHECKREG fp, 0x8B1C16BF; + + imm32 p1, 0x89a6cdef; + imm32 p2, 0x56769abc; + imm32 p3, 0xdef61234; + imm32 p4, 0x23466899; + imm32 p5, 0x78962345; + imm32 sp, 0x98765432; + imm32 fp, 0x12365678; + P1 = SP + ( P1 << 1 ); + P2 = SP + ( P2 << 1 ); + P3 = SP + ( P3 << 1 ); + P4 = SP + ( P4 << 1 ); + P5 = SP + ( P5 << 1 ); + SP = SP + ( SP << 1 ); + FP = SP + ( FP << 1 ); + CHECKREG p1, 0xABC3F010; + CHECKREG p2, 0x456389AA; + CHECKREG p3, 0x5662789A; + CHECKREG p4, 0xDF032564; + CHECKREG p5, 0x89A29ABC; + CHECKREG sp, 0xC962FC96; + CHECKREG fp, 0xEDCFA986; + + imm32 p1, 0x89ab7def; + imm32 p2, 0x56787abc; + imm32 p3, 0xdef07234; + imm32 p4, 0x23457899; + imm32 p5, 0x78917345; + imm32 sp, 0x98767432; + imm32 fp, 0x12345678; + P1 = FP + ( P1 << 1 ); + P2 = FP + ( P2 << 1 ); + P3 = FP + ( P3 << 1 ); + P4 = FP + ( P4 << 1 ); + P5 = FP + ( P5 << 1 ); + SP = FP + ( SP << 1 ); + FP = FP + ( FP << 1 ); + CHECKREG p1, 0x258B5256; + CHECKREG p2, 0xBF254BF0; + CHECKREG p3, 0xD0153AE0; + CHECKREG p4, 0x58BF47AA; + CHECKREG p5, 0x03573D02; + CHECKREG sp, 0x43213EDC; + CHECKREG fp, 0x369D0368; + + imm32 p1, 0x29ab1def; + imm32 p2, 0x52781abc; + imm32 p3, 0xde201234; + imm32 p4, 0x23421899; + imm32 p5, 0x78912345; + imm32 sp, 0x98761232; + imm32 fp, 0x12341628; + P1 = P3 + ( P1 << 1 ); + P2 = P4 + ( P1 << 1 ); + P3 = P5 + ( P1 << 1 ); + P4 = SP + ( P1 << 1 ); + P5 = FP + ( P1 << 1 ); + FP = P1 + ( P1 << 1 ); + CHECKREG p1, 0x31764E12; + CHECKREG p2, 0x862EB4BD; + CHECKREG p3, 0xDB7DBF69; + CHECKREG p4, 0xFB62AE56; + CHECKREG p5, 0x7520B24C; + CHECKREG fp, 0x9462EA36; + + imm32 p1, 0x893bcd2f; + imm32 p2, 0x56739a2c; + imm32 p3, 0x3ef03224; + imm32 p4, 0x23456329; + imm32 p5, 0x78312335; + imm32 sp, 0x98735423; + imm32 fp, 0x12343628; + P1 = P4 + ( P2 << 1 ); + P2 = P5 + ( P2 << 1 ); + P3 = SP + ( P2 << 1 ); + P4 = FP + ( P2 << 1 ); + SP = P1 + ( P2 << 1 ); + FP = P2 + ( P2 << 1 ); + CHECKREG p1, 0xD02C9781; + CHECKREG p2, 0x2518578D; + CHECKREG p3, 0xE2A4033D; + CHECKREG p4, 0x5C64E542; + CHECKREG sp, 0x1A5D469B; + CHECKREG fp, 0x6F4906A7; + + imm32 p1, 0x894bcde3; + imm32 p2, 0x56749ab3; + imm32 p3, 0x4ef04233; + imm32 p4, 0x24456493; + imm32 p5, 0x78412344; + imm32 sp, 0x98745434; + imm32 fp, 0x12344673; + P1 = P5 + ( P3 << 1 ); + P2 = SP + ( P3 << 1 ); + P3 = FP + ( P3 << 1 ); + P5 = P1 + ( P3 << 1 ); + SP = P2 + ( P3 << 1 ); + FP = P3 + ( P3 << 1 ); + CHECKREG p1, 0x1621A7AA; + CHECKREG p2, 0x3654D89A; + CHECKREG p3, 0xB014CAD9; + CHECKREG p5, 0x764B3D5C; + CHECKREG sp, 0x967E6E4C; + CHECKREG fp, 0x103E608B; + + imm32 p1, 0x49abc5ef; + imm32 p2, 0x46789a5c; + imm32 p3, 0x4ef01235; + imm32 p4, 0x53456899; + imm32 p5, 0x45912345; + imm32 sp, 0x48565432; + imm32 fp, 0x42355678; + P1 = SP + ( P4 << 1 ); + P2 = FP + ( P4 << 1 ); + P4 = P1 + ( P4 << 1 ); + P5 = P2 + ( P4 << 1 ); + SP = P3 + ( P4 << 1 ); + FP = P4 + ( P4 << 1 ); + CHECKREG p1, 0xEEE12564; + CHECKREG p2, 0xE8C027AA; + CHECKREG p4, 0x956BF696; + CHECKREG p5, 0x139814D6; + CHECKREG sp, 0x79C7FF61; + CHECKREG fp, 0xC043E3C2; + + imm32 p1, 0x85ab6def; + imm32 p2, 0x657896bc; + imm32 p3, 0xd6f01264; + imm32 p4, 0x25656896; + imm32 p5, 0x75962345; + imm32 sp, 0x95766432; + imm32 fp, 0x15345678; + P1 = FP + ( P5 << 1 ); + P3 = P1 + ( P5 << 1 ); + P4 = P2 + ( P5 << 1 ); + P5 = P3 + ( P5 << 1 ); + SP = P4 + ( P5 << 1 ); + FP = P5 + ( P5 << 1 ); + CHECKREG p1, 0x00609D02; + CHECKREG p3, 0xEB8CE38C; + CHECKREG p4, 0x50A4DD46; + CHECKREG p5, 0xD6B92A16; + CHECKREG sp, 0xFE173172; + CHECKREG fp, 0x842B7E42; + + imm32 p1, 0x89a7cdef; + imm32 p2, 0x56767abc; + imm32 p3, 0xdef61734; + imm32 p4, 0x73466879; + imm32 p5, 0x77962347; + imm32 sp, 0x98765432; + imm32 fp, 0x12375678; + P2 = P1 + ( SP << 1 ); + P3 = P2 + ( SP << 1 ); + P4 = P3 + ( SP << 1 ); + P5 = P4 + ( SP << 1 ); + SP = P5 + ( SP << 1 ); + FP = SP + ( SP << 1 ); + CHECKREG p2, 0xBA947653; + CHECKREG p3, 0xEB811EB7; + CHECKREG p4, 0x1C6DC71B; + CHECKREG p5, 0x4D5A6F7F; + CHECKREG sp, 0x7E4717E3; + CHECKREG fp, 0x7AD547A9; + + imm32 p1, 0x88ab78ef; + imm32 p2, 0x56887a8c; + imm32 p3, 0x8ef87238; + imm32 p4, 0x28458899; + imm32 p5, 0x78817845; + imm32 sp, 0x98787482; + imm32 fp, 0x12348678; + P1 = P2 + ( FP << 1 ); + P2 = P3 + ( FP << 1 ); + P3 = P4 + ( FP << 1 ); + P4 = P5 + ( FP << 1 ); + P5 = SP + ( FP << 1 ); + SP = FP + ( FP << 1 ); + CHECKREG p1, 0x7AF1877C; + CHECKREG p2, 0xB3617F28; + CHECKREG p3, 0x4CAE9589; + CHECKREG p4, 0x9CEA8535; + CHECKREG p5, 0xBCE18172; + CHECKREG sp, 0x369D9368; + + pass diff --git a/tests/tcg/bfin/c_comp3op_pr_plus_pr_sh2.s b/tests/tcg/bfin/c_comp3op_pr_plus_pr_sh2.s new file mode 100644 index 0000000000000..dd86726dfccd4 --- /dev/null +++ b/tests/tcg/bfin/c_comp3op_pr_plus_pr_sh2.s @@ -0,0 +1,302 @@ +//Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh2/c_comp3op_pr_plus_pr_sh2.dsp +// Spec Reference: comp3op pregs + pregs << 2 +# mach: bfin + +.include "testutils.inc" + start + + imm32 p1, 0x89ab1def; + imm32 p2, 0x56781abc; + imm32 p3, 0xdef01234; + imm32 p4, 0x23451899; + imm32 p5, 0x78911345; + imm32 sp, 0x98761432; + imm32 fp, 0x12341678; + P1 = P1 + ( P1 << 2 ); + P2 = P1 + ( P2 << 2 ); + P3 = P1 + ( P3 << 2 ); + P4 = P1 + ( P4 << 2 ); + P5 = P1 + ( P5 << 2 ); + SP = P1 + ( SP << 2 ); + FP = P1 + FP; + CHECKREG p1, 0xB05795AB; + CHECKREG p2, 0x0A38009B; + CHECKREG p3, 0x2C17DE7B; + CHECKREG p4, 0x3D6BF80F; + CHECKREG p5, 0x929BE2BF; + CHECKREG sp, 0x122FE673; + CHECKREG fp, 0xC28BAC23; + + imm32 p1, 0x89abcd2f; + imm32 p2, 0x56789a2c; + imm32 p3, 0xdef01224; + imm32 p4, 0x23456829; + imm32 p5, 0x78912325; + imm32 sp, 0x98765422; + imm32 fp, 0x12345628; + P1 = P2 + ( P1 << 2 ); + P2 = P2 + ( P2 << 2 ); + P3 = P2 + ( P3 << 2 ); + P4 = P2 + ( P4 << 2 ); + P5 = P2 + ( P5 << 2 ); + SP = P2 + ( SP << 2 ); + FP = P2 + ( FP << 2 ); + CHECKREG p1, 0x7D27CEE8; + CHECKREG p2, 0xB05B02DC; + CHECKREG p3, 0x2C1B4B6C; + CHECKREG p4, 0x3D70A380; + CHECKREG p5, 0x929F8F70; + CHECKREG sp, 0x12345364; + CHECKREG fp, 0xF92C5B7C; + + imm32 p1, 0x89abcde3; + imm32 p2, 0x56789ab3; + imm32 p3, 0xdef01233; + imm32 p4, 0x23456893; + imm32 p5, 0x78912343; + imm32 sp, 0x98765433; + imm32 fp, 0x12345673; + P1 = P3 + ( P1 << 2 ); + P2 = P3 + ( P2 << 2 ); + P3 = P3 + ( P3 << 2 ); + P4 = P3 + ( P4 << 2 ); + P5 = P3 + ( P5 << 2 ); + SP = P3 + ( SP << 2 ); + FP = P3 + ( FP << 2 ); + CHECKREG p1, 0x059F49BF; + CHECKREG p2, 0x38D27CFF; + CHECKREG p3, 0x5AB05AFF; + CHECKREG p4, 0xE7C5FD4B; + CHECKREG p5, 0x3CF4E80B; + CHECKREG sp, 0xBC89ABCB; + CHECKREG fp, 0xA381B4CB; + + imm32 p1, 0x49abcdef; + imm32 p2, 0x46789abc; + imm32 p3, 0x4ef01234; + imm32 p4, 0x43456899; + imm32 p5, 0x48912345; + imm32 sp, 0x48765432; + imm32 fp, 0x42345678; + P1 = P4 + ( P1 << 2 ); + P2 = P4 + ( P2 << 2 ); + P3 = P4 + ( P3 << 2 ); + P4 = P4 + ( P4 << 2 ); + P5 = P4 + ( P5 << 2 ); + SP = P4 + ( SP << 2 ); + FP = P4 + ( FP << 2 ); + CHECKREG p1, 0x69F4A055; + CHECKREG p2, 0x5D27D389; + CHECKREG p3, 0x7F05B169; + CHECKREG p4, 0x505B0AFD; + CHECKREG p5, 0x729F9811; + CHECKREG sp, 0x72345BC5; + CHECKREG fp, 0x592C64DD; + + imm32 p1, 0x85abcdef; + imm32 p2, 0x55789abc; + imm32 p3, 0xd5f01234; + imm32 p4, 0x25456899; + imm32 p5, 0x75912345; + imm32 sp, 0x95765432; + imm32 fp, 0x15345678; + P1 = P5 + ( P1 << 2 ); + P2 = P5 + ( P2 << 2 ); + P3 = P5 + ( P3 << 2 ); + P4 = P5 + ( P4 << 2 ); + P5 = P5 + ( P5 << 2 ); + SP = P5 + ( SP << 2 ); + FP = P5 + ( FP << 2 ); + CHECKREG p1, 0x8C405B01; + CHECKREG p2, 0xCB738E35; + CHECKREG p3, 0xCD516C15; + CHECKREG p4, 0x0AA6C5A9; + CHECKREG p5, 0x4BD5B059; + CHECKREG sp, 0xA1AF0121; + CHECKREG fp, 0xA0A70A39; + + imm32 p1, 0x89a6cdef; + imm32 p2, 0x56769abc; + imm32 p3, 0xdef61234; + imm32 p4, 0x23466899; + imm32 p5, 0x78962345; + imm32 sp, 0x98765432; + imm32 fp, 0x12365678; + P1 = SP + ( P1 << 2 ); + P2 = SP + ( P2 << 2 ); + P3 = SP + ( P3 << 2 ); + P4 = SP + ( P4 << 2 ); + P5 = SP + ( P5 << 2 ); + SP = SP + ( SP << 2 ); + FP = SP + ( FP << 2 ); + CHECKREG p1, 0xBF118BEE; + CHECKREG p2, 0xF250BF22; + CHECKREG p3, 0x144E9D02; + CHECKREG p4, 0x258FF696; + CHECKREG p5, 0x7ACEE146; + CHECKREG sp, 0xFA4FA4FA; + CHECKREG fp, 0x4328FEDA; + + imm32 p1, 0x89ab7def; + imm32 p2, 0x56787abc; + imm32 p3, 0xdef07234; + imm32 p4, 0x23457899; + imm32 p5, 0x78917345; + imm32 sp, 0x98767432; + imm32 fp, 0x12345678; + P1 = FP + ( P1 << 2 ); + P2 = FP + ( P2 << 2 ); + P3 = FP + ( P3 << 2 ); + P4 = FP + ( P4 << 2 ); + P5 = FP + ( P5 << 2 ); + SP = FP + ( SP << 2 ); + FP = FP + ( FP << 2 ); + CHECKREG p1, 0x38E24E34; + CHECKREG p2, 0x6C164168; + CHECKREG p3, 0x8DF61F48; + CHECKREG p4, 0x9F4A38DC; + CHECKREG p5, 0xF47A238C; + CHECKREG sp, 0x740E2740; + CHECKREG fp, 0x5B05B058; + + imm32 p1, 0x29ab1def; + imm32 p2, 0x52781abc; + imm32 p3, 0xde201234; + imm32 p4, 0x23421899; + imm32 p5, 0x78912345; + imm32 sp, 0x98761232; + imm32 fp, 0x12341628; + P1 = P3 + ( P1 << 2 ); + P2 = P4 + ( P1 << 2 ); + P3 = P5 + ( P1 << 2 ); + P4 = SP + ( P1 << 2 ); + P5 = FP + ( P1 << 2 ); + FP = P1 + ( P1 << 2 ); + CHECKREG p1, 0x84CC89F0; + CHECKREG p2, 0x36744059; + CHECKREG p3, 0x8BC34B05; + CHECKREG p4, 0xABA839F2; + CHECKREG p5, 0x25663DE8; + CHECKREG fp, 0x97FEB1B0; + + imm32 p1, 0x893bcd2f; + imm32 p2, 0x56739a2c; + imm32 p3, 0x3ef03224; + imm32 p4, 0x23456329; + imm32 p5, 0x78312335; + imm32 sp, 0x98735423; + imm32 fp, 0x12343628; + P1 = P4 + ( P2 << 2 ); + P2 = P5 + ( P2 << 2 ); + P3 = SP + ( P2 << 2 ); + P4 = FP + ( P2 << 2 ); + SP = P1 + ( P2 << 2 ); + FP = P2 + ( P2 << 2 ); + CHECKREG p1, 0x7D13CBD9; + CHECKREG p2, 0xD1FF8BE5; + CHECKREG p3, 0xE07183B7; + CHECKREG p4, 0x5A3265BC; + CHECKREG sp, 0xC511FB6D; + CHECKREG fp, 0x19FDBB79; + + imm32 p1, 0x894bcde3; + imm32 p2, 0x56749ab3; + imm32 p3, 0x4ef04233; + imm32 p4, 0x24456493; + imm32 p5, 0x78412344; + imm32 sp, 0x98745434; + imm32 fp, 0x12344673; + P1 = P5 + ( P3 << 2 ); + P2 = SP + ( P3 << 2 ); + P3 = FP + ( P3 << 2 ); + P5 = P1 + ( P3 << 2 ); + SP = P2 + ( P3 << 2 ); + FP = P3 + ( P3 << 2 ); + CHECKREG p1, 0xB4022C10; + CHECKREG p2, 0xD4355D00; + CHECKREG p3, 0x4DF54F3F; + CHECKREG p5, 0xEBD7690C; + CHECKREG sp, 0x0C0A99FC; + CHECKREG fp, 0x85CA8C3B; + + imm32 p1, 0x49abc5ef; + imm32 p2, 0x46789a5c; + imm32 p3, 0x4ef01235; + imm32 p4, 0x53456899; + imm32 p5, 0x45912345; + imm32 sp, 0x48565432; + imm32 fp, 0x42355678; + P1 = SP + ( P4 << 2 ); + P2 = FP + ( P4 << 2 ); + P4 = P1 + ( P4 << 2 ); + P5 = P2 + ( P4 << 2 ); + SP = P3 + ( P4 << 2 ); + FP = P4 + ( P4 << 2 ); + CHECKREG p1, 0x956BF696; + CHECKREG p2, 0x8F4AF8DC; + CHECKREG p4, 0xE28198FA; + CHECKREG p5, 0x19515CC4; + CHECKREG sp, 0xD8F6761D; + CHECKREG fp, 0x6C87FCE2; + + imm32 p1, 0x85ab6def; + imm32 p2, 0x657896bc; + imm32 p3, 0xd6f01264; + imm32 p4, 0x25656896; + imm32 p5, 0x75962345; + imm32 sp, 0x95766432; + imm32 fp, 0x15345678; + P1 = FP + ( P5 << 2 ); + P3 = P1 + ( P5 << 2 ); + P4 = P2 + ( P5 << 2 ); + P5 = P3 + ( P5 << 2 ); + SP = P4 + ( P5 << 2 ); + FP = P5 + ( P5 << 2 ); + CHECKREG p1, 0xEB8CE38C; + CHECKREG p3, 0xC1E570A0; + CHECKREG p4, 0x3BD123D0; + CHECKREG p5, 0x983DFDB4; + CHECKREG sp, 0x9CC91AA0; + CHECKREG fp, 0xF935F484; + + imm32 p1, 0x89a7cdef; + imm32 p2, 0x56767abc; + imm32 p3, 0xdef61734; + imm32 p4, 0x73466879; + imm32 p5, 0x77962347; + imm32 sp, 0x98765432; + imm32 fp, 0x12375678; + P2 = P1 + ( SP << 2 ); + P3 = P2 + ( SP << 2 ); + P4 = P3 + ( SP << 2 ); + P5 = P4 + ( SP << 2 ); + SP = P5 + ( SP << 2 ); + FP = SP + ( SP << 2 ); + CHECKREG p2, 0xEB811EB7; + CHECKREG p3, 0x4D5A6F7F; + CHECKREG p4, 0xAF33C047; + CHECKREG p5, 0x110D110F; + CHECKREG sp, 0x72E661D7; + CHECKREG fp, 0x3E7FE933; + + imm32 p1, 0x88ab78ef; + imm32 p2, 0x56887a8c; + imm32 p3, 0x8ef87238; + imm32 p4, 0x28458899; + imm32 p5, 0x78817845; + imm32 sp, 0x98787482; + imm32 fp, 0x12348678; + P1 = P2 + ( FP << 2 ); + P2 = P3 + ( FP << 2 ); + P3 = P4 + ( FP << 2 ); + P4 = P5 + ( FP << 2 ); + P5 = SP + ( FP << 2 ); + SP = FP + ( FP << 2 ); + CHECKREG p1, 0x9F5A946C; + CHECKREG p2, 0xD7CA8C18; + CHECKREG p3, 0x7117A279; + CHECKREG p4, 0xC1539225; + CHECKREG p5, 0xE14A8E62; + CHECKREG sp, 0x5B06A058; + + pass diff --git a/tests/tcg/bfin/c_compi2opd_dr_add_i7_n.s b/tests/tcg/bfin/c_compi2opd_dr_add_i7_n.s new file mode 100644 index 0000000000000..af3406b0ae2a4 --- /dev/null +++ b/tests/tcg/bfin/c_compi2opd_dr_add_i7_n.s @@ -0,0 +1,164 @@ +//Original:/testcases/core/c_compi2opd_dr_add_i7_n/c_compi2opd_dr_add_i7_n.dsp +// Spec Reference: compi2opd dregs += imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +R0 += 0; +R1 += -1; +R2 += -2; +R3 += -3; +R4 += -4; +R5 += -5; +R6 += -6; +R7 += -7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFE; +CHECKREG r3, 0xFFFFFFFD; +CHECKREG r4, 0xFFFFFFFC; +CHECKREG r5, 0xFFFFFFFB; +CHECKREG r6, 0xFFFFFFFA; +CHECKREG r7, 0xFFFFFFF9; + +R0 += -8; +R1 += -9; +R2 += -10; +R3 += -11; +R4 += -12; +R5 += -13; +R6 += -14; +R7 += -15; +CHECKREG r0, 0xFFFFFFF8; +CHECKREG r1, 0xFFFFFFF6; +CHECKREG r2, 0xFFFFFFF4; +CHECKREG r3, 0xFFFFFFF2; +CHECKREG r4, 0xFFFFFFF0; +CHECKREG r5, 0xFFFFFFEE; +CHECKREG r6, 0xFFFFFFEC; +CHECKREG r7, 0xFFFFFFEA; + +R0 += -16; +R1 += -17; +R2 += -18; +R3 += -19; +R4 += -20; +R5 += -21; +R6 += -22; +R7 += -23; +CHECKREG r0, 0xFFFFFFE8; +CHECKREG r1, 0xFFFFFFE5; +CHECKREG r2, 0xFFFFFFE2; +CHECKREG r3, 0xFFFFFFDF; +CHECKREG r4, 0xFFFFFFDC; +CHECKREG r5, 0xFFFFFFD9; +CHECKREG r6, 0xFFFFFFD6; +CHECKREG r7, 0xFFFFFFD3; + +R0 += -24; +R1 += -25; +R2 += -26; +R3 += -27; +R4 += -28; +R5 += -29; +R6 += -30; +R7 += -31; +CHECKREG r0, 0xFFFFFFD0; +CHECKREG r1, 0xFFFFFFCC; +CHECKREG r2, 0xFFFFFFC8; +CHECKREG r3, 0xFFFFFFC4; +CHECKREG r4, 0xFFFFFFC0; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFB8; +CHECKREG r7, 0xFFFFFFB4; + +R0 += -32; +R1 += -33; +R2 += -34; +R3 += -35; +R4 += -36; +R5 += -37; +R6 += -38; +R7 += -39; +CHECKREG r0, 0xFFFFFFB0; +CHECKREG r1, 0xFFFFFFAB; +CHECKREG r2, 0xFFFFFFA6; +CHECKREG r3, 0xFFFFFFA1; +CHECKREG r4, 0xFFFFFF9C; +CHECKREG r5, 0xFFFFFF97; +CHECKREG r6, 0xFFFFFF92; +CHECKREG r7, 0xFFFFFF8D; + +R0 += -40; +R1 += -41; +R2 += -42; +R3 += -43; +R4 += -44; +R5 += -45; +R6 += -46; +R7 += -47; +CHECKREG r0, 0xFFFFFF88; +CHECKREG r1, 0xFFFFFF82; +CHECKREG r2, 0xFFFFFF7C; +CHECKREG r3, 0xFFFFFF76; +CHECKREG r4, 0xFFFFFF70; +CHECKREG r5, 0xFFFFFF6A; +CHECKREG r6, 0xFFFFFF64; +CHECKREG r7, 0xFFFFFF5E; + +R0 += -48; +R1 += -49; +R2 += -50; +R3 += -51; +R4 += -52; +R5 += -53; +R6 += -54; +R7 += -55; +CHECKREG r0, 0xFFFFFF58; +CHECKREG r1, 0xFFFFFF51; +CHECKREG r2, 0xFFFFFF4A; +CHECKREG r3, 0xFFFFFF43; +CHECKREG r4, 0xFFFFFF3C; +CHECKREG r5, 0xFFFFFF35; +CHECKREG r6, 0xFFFFFF2E; +CHECKREG r7, 0xFFFFFF27; + +R0 += -56; +R1 += -57; +R2 += -58; +R3 += -59; +R4 += -60; +R5 += -61; +R6 += -62; +R7 += -63; +CHECKREG r0, 0xFFFFFF20; +CHECKREG r1, 0xFFFFFF18; +CHECKREG r2, 0xFFFFFF10; +CHECKREG r3, 0xFFFFFF08; +CHECKREG r4, 0xFFFFFF00; +CHECKREG r5, 0xFFFFFEF8; +CHECKREG r6, 0xFFFFFEF0; +CHECKREG r7, 0xFFFFFEE8; + +R0 += -64; +R1 += -64; +R2 += -64; +R3 += -64; +R4 += -64; +R5 += -64; +R6 += -64; +R7 += -64; +CHECKREG r0, 0xFFFFFEE0; +CHECKREG r1, 0xFFFFFED8; +CHECKREG r2, 0xFFFFFED0; +CHECKREG r3, 0xFFFFFEC8; +CHECKREG r4, 0xFFFFFEC0; +CHECKREG r5, 0xFFFFFEB8; +CHECKREG r6, 0xFFFFFEB0; +CHECKREG r7, 0xFFFFFEA8; + +pass diff --git a/tests/tcg/bfin/c_compi2opd_dr_add_i7_p.s b/tests/tcg/bfin/c_compi2opd_dr_add_i7_p.s new file mode 100644 index 0000000000000..66b453791c81f --- /dev/null +++ b/tests/tcg/bfin/c_compi2opd_dr_add_i7_p.s @@ -0,0 +1,147 @@ +//Original:/testcases/core/c_compi2opd_dr_add_i7_p/c_compi2opd_dr_add_i7_p.dsp +// Spec Reference: compi2opd dregs += imm7 positive +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +R0 += 0; +R1 += 1; +R2 += 2; +R3 += 3; +R4 += 4; +R5 += 5; +R6 += 6; +R7 += 7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +R0 += 8; +R1 += 9; +R2 += 10; +R3 += 11; +R4 += 12; +R5 += 13; +R6 += 14; +R7 += 15; +CHECKREG r0, 0x00000008; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x0000000C; +CHECKREG r3, 0x0000000E; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000012; +CHECKREG r6, 0x00000014; +CHECKREG r7, 0x00000016; + +R0 += 16; +R1 += 17; +R2 += 18; +R3 += 19; +R4 += 20; +R5 += 21; +R6 += 22; +R7 += 23; +CHECKREG r0, 0x00000018; +CHECKREG r1, 0x0000001B; +CHECKREG r2, 0x0000001E; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000024; +CHECKREG r5, 0x00000027; +CHECKREG r6, 0x0000002A; +CHECKREG r7, 0x0000002D; + +R0 += 24; +R1 += 25; +R2 += 26; +R3 += 27; +R4 += 28; +R5 += 29; +R6 += 30; +R7 += 31; +CHECKREG r0, 0x00000030; +CHECKREG r1, 0x00000034; +CHECKREG r2, 0x00000038; +CHECKREG r3, 0x0000003C; +CHECKREG r4, 0x00000040; +CHECKREG r5, 0x00000044; +CHECKREG r6, 0x00000048; +CHECKREG r7, 0x0000004C; + +R0 += 32; +R1 += 33; +R2 += 34; +R3 += 35; +R4 += 36; +R5 += 37; +R6 += 38; +R7 += 39; +CHECKREG r0, 0x00000050; +CHECKREG r1, 0x00000055; +CHECKREG r2, 0x0000005A; +CHECKREG r3, 0x0000005F; +CHECKREG r4, 0x00000064; +CHECKREG r5, 0x00000069; +CHECKREG r6, 0x0000006E; +CHECKREG r7, 0x00000073; + +R0 += 40; +R1 += 41; +R2 += 42; +R3 += 43; +R4 += 44; +R5 += 45; +R6 += 46; +R7 += 47; +CHECKREG r0, 0x00000078; +CHECKREG r1, 0x0000007E; +CHECKREG r2, 0x00000084; +CHECKREG r3, 0x0000008A; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x00000096; +CHECKREG r6, 0x0000009C; +CHECKREG r7, 0x000000A2; + +R0 += 48; +R1 += 49; +R2 += 50; +R3 += 51; +R4 += 52; +R5 += 53; +R6 += 54; +R7 += 55; +CHECKREG r0, 0x000000A8; +CHECKREG r1, 0x000000AF; +CHECKREG r2, 0x000000B6; +CHECKREG r3, 0x000000BD; +CHECKREG r4, 0x000000C4; +CHECKREG r5, 0x000000CB; +CHECKREG r6, 0x000000D2; +CHECKREG r7, 0x000000D9; + +R0 += 56; +R1 += 57; +R2 += 58; +R3 += 59; +R4 += 60; +R5 += 61; +R6 += 62; +R7 += 63; +CHECKREG r0, 0x000000E0; +CHECKREG r1, 0x000000E8; +CHECKREG r2, 0x000000F0; +CHECKREG r3, 0x000000F8; +CHECKREG r4, 0x00000100; +CHECKREG r5, 0x00000108; +CHECKREG r6, 0x00000110; +CHECKREG r7, 0x00000118; + +pass diff --git a/tests/tcg/bfin/c_compi2opd_dr_eq_i7_n.s b/tests/tcg/bfin/c_compi2opd_dr_eq_i7_n.s new file mode 100644 index 0000000000000..509929de275f7 --- /dev/null +++ b/tests/tcg/bfin/c_compi2opd_dr_eq_i7_n.s @@ -0,0 +1,166 @@ +//Original:/testcases/core/c_compi2opd_dr_eq_i7_n/c_compi2opd_dr_eq_i7_n.dsp +// Spec Reference: compi2opd dregs = imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + + +R0 = -0; +R1 = -1; +R2 = -2; +R3 = -3; +R4 = -4; +R5 = -5; +R6 = -6; +R7 = -7; +CHECKREG r0, -0; +CHECKREG r1, -1; +CHECKREG r2, -2; +CHECKREG r3, -3; +CHECKREG r4, -4; +CHECKREG r5, -5; +CHECKREG r6, -6; +CHECKREG r7, -7; + +R0 = -8; +R1 = -9; +R2 = -10; +R3 = -11; +R4 = -12; +R5 = -13; +R6 = -14; +R7 = -15; +CHECKREG r0, -8; +CHECKREG r1, -9; +CHECKREG r2, -10; +CHECKREG r3, -11; +CHECKREG r4, -12; +CHECKREG r5, -13; +CHECKREG r6, -14; +CHECKREG r7, -15; + +R0 = -16; +R1 = -17; +R2 = -18; +R3 = -19; +R4 = -20; +R5 = -21; +R6 = -22; +R7 = -23; +CHECKREG r0, -16; +CHECKREG r1, -17; +CHECKREG r2, -18; +CHECKREG r3, -19; +CHECKREG r4, -20; +CHECKREG r5, -21; +CHECKREG r6, -22; +CHECKREG r7, -23; + +R0 = -24; +R1 = -25; +R2 = -26; +R3 = -27; +R4 = -28; +R5 = -29; +R6 = -30; +R7 = -31; +CHECKREG r0, -24; +CHECKREG r1, -25; +CHECKREG r2, -26; +CHECKREG r3, -27; +CHECKREG r4, -28; +CHECKREG r5, -29; +CHECKREG r6, -30; +CHECKREG r7, -31; + +R0 = -32; +R1 = -33; +R2 = -34; +R3 = -35; +R4 = -36; +R5 = -37; +R6 = -38; +R7 = -39; +CHECKREG r0, -32; +CHECKREG r1, -33; +CHECKREG r2, -34; +CHECKREG r3, -35; +CHECKREG r4, -36; +CHECKREG r5, -37; +CHECKREG r6, -38; +CHECKREG r7, -39; + +R0 = -40; +R1 = -41; +R2 = -42; +R3 = -43; +R4 = -44; +R5 = -45; +R6 = -46; +R7 = -47; +CHECKREG r0, -40; +CHECKREG r1, -41; +CHECKREG r2, -42; +CHECKREG r3, -43; +CHECKREG r4, -44; +CHECKREG r5, -45; +CHECKREG r6, -46; +CHECKREG r7, -47; + +R0 = -48; +R1 = -49; +R2 = -50; +R3 = -51; +R4 = -52; +R5 = -53; +R6 = -54; +R7 = -55; +CHECKREG r0, -48; +CHECKREG r1, -49; +CHECKREG r2, -50; +CHECKREG r3, -51; +CHECKREG r4, -52; +CHECKREG r5, -53; +CHECKREG r6, -54; +CHECKREG r7, -55; + +R0 = -56; +R1 = -57; +R2 = -58; +R3 = -59; +R4 = -60; +R5 = -61; +R6 = -62; +R7 = -63; +CHECKREG r0, -56; +CHECKREG r1, -57; +CHECKREG r2, -58; +CHECKREG r3, -59; +CHECKREG r4, -60; +CHECKREG r5, -61; +CHECKREG r6, -62; +CHECKREG r7, -63; + +R0 = -64; +R1 = -64; +R2 = -64; +R3 = -64; +R4 = -64; +R5 = -64; +R6 = -64; +R7 = -64; +CHECKREG r0, -64; +CHECKREG r1, -64; +CHECKREG r2, -64; +CHECKREG r3, -64; +CHECKREG r4, -64; +CHECKREG r5, -64; +CHECKREG r6, -64; +CHECKREG r7, -64; + + +pass diff --git a/tests/tcg/bfin/c_compi2opd_dr_eq_i7_p.s b/tests/tcg/bfin/c_compi2opd_dr_eq_i7_p.s new file mode 100644 index 0000000000000..5e792cc4ff112 --- /dev/null +++ b/tests/tcg/bfin/c_compi2opd_dr_eq_i7_p.s @@ -0,0 +1,147 @@ +//Original:/testcases/core/c_compi2opd_dr_eq_i7_p/c_compi2opd_dr_eq_i7_p.dsp +// Spec Reference: compi2opd dregs = imm7 positive +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +R0 = 0; +R1 = 1; +R2 = 2; +R3 = 3; +R4 = 4; +R5 = 5; +R6 = 6; +R7 = 7; +CHECKREG r0, 0; +CHECKREG r1, 1; +CHECKREG r2, 2; +CHECKREG r3, 3; +CHECKREG r4, 4; +CHECKREG r5, 5; +CHECKREG r6, 6; +CHECKREG r7, 7; + +R0 = 8; +R1 = 9; +R2 = 10; +R3 = 11; +R4 = 12; +R5 = 13; +R6 = 14; +R7 = 15; +CHECKREG r0, 8; +CHECKREG r1, 9; +CHECKREG r2, 10; +CHECKREG r3, 11; +CHECKREG r4, 12; +CHECKREG r5, 13; +CHECKREG r6, 14; +CHECKREG r7, 15; + +R0 = 16; +R1 = 17; +R2 = 18; +R3 = 19; +R4 = 20; +R5 = 21; +R6 = 22; +R7 = 23; +CHECKREG r0, 16; +CHECKREG r1, 17; +CHECKREG r2, 18; +CHECKREG r3, 19; +CHECKREG r4, 20; +CHECKREG r5, 21; +CHECKREG r6, 22; +CHECKREG r7, 23; + +R0 = 24; +R1 = 25; +R2 = 26; +R3 = 27; +R4 = 28; +R5 = 29; +R6 = 30; +R7 = 31; +CHECKREG r0, 24; +CHECKREG r1, 25; +CHECKREG r2, 26; +CHECKREG r3, 27; +CHECKREG r4, 28; +CHECKREG r5, 29; +CHECKREG r6, 30; +CHECKREG r7, 31; + +R0 = 32; +R1 = 33; +R2 = 34; +R3 = 35; +R4 = 36; +R5 = 37; +R6 = 38; +R7 = 39; +CHECKREG r0, 32; +CHECKREG r1, 33; +CHECKREG r2, 34; +CHECKREG r3, 35; +CHECKREG r4, 36; +CHECKREG r5, 37; +CHECKREG r6, 38; +CHECKREG r7, 39; + +R0 = 40; +R1 = 41; +R2 = 42; +R3 = 43; +R4 = 44; +R5 = 45; +R6 = 46; +R7 = 47; +CHECKREG r0, 40; +CHECKREG r1, 41; +CHECKREG r2, 42; +CHECKREG r3, 43; +CHECKREG r4, 44; +CHECKREG r5, 45; +CHECKREG r6, 46; +CHECKREG r7, 47; + +R0 = 48; +R1 = 49; +R2 = 50; +R3 = 51; +R4 = 52; +R5 = 53; +R6 = 54; +R7 = 55; +CHECKREG r0, 48; +CHECKREG r1, 49; +CHECKREG r2, 50; +CHECKREG r3, 51; +CHECKREG r4, 52; +CHECKREG r5, 53; +CHECKREG r6, 54; +CHECKREG r7, 55; + +R0 = 56; +R1 = 57; +R2 = 58; +R3 = 59; +R4 = 60; +R5 = 61; +R6 = 62; +R7 = 63; +CHECKREG r0, 56; +CHECKREG r1, 57; +CHECKREG r2, 58; +CHECKREG r3, 59; +CHECKREG r4, 60; +CHECKREG r5, 61; +CHECKREG r6, 62; +CHECKREG r7, 63; + +pass diff --git a/tests/tcg/bfin/c_compi2opd_flags.S b/tests/tcg/bfin/c_compi2opd_flags.S new file mode 100644 index 0000000000000..41864c517911f --- /dev/null +++ b/tests/tcg/bfin/c_compi2opd_flags.S @@ -0,0 +1,600 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opd_flags/c_compi2opd_flags.dsp +// Spec Reference: compi2opd dregs += imm7 flags (az, an, ac, av0) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + INIT_R_REGS 0; + ASTAT = R0; // initialize astat + +// AZ for R0 + imm32 r0, 0x00000000; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R0 + imm32 r0, 0xffffffff; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R0; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R0 + imm32 r0, 0x7fffffff; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFE; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); //C + CHECKREG r7, (_AN); // A + +// AZ, AN, AC, AV0 for R0 + R0 = 0; + ASTAT = R0; + imm32 r0, 0x80000000; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000001; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R0 + R1 = 0; + ASTAT = R1; + imm32 r1, 0x00000000; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R1 + imm32 r1, 0xffffffff; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R1; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R1 + imm32 r1, 0x7fffffff; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFE; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R1 + R1 = 0; + ASTAT = R1; + imm32 r1, 0x80000000; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000001; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R2 + imm32 r2, 0x00000000; + ASTAT = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R2 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R2; + R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R2 + imm32 r2, 0xffffffff; + R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r2, 0xFFFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R2 + imm32 r2, 0x7fffffff; + R2 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x7FFFFFFE; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R2 + R2 = 0; + ASTAT = R2; + imm32 r2, 0x80000000; + R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x80000001; + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R3 + imm32 r3, 0x00000000; + ASTAT = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R3 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R3; + R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, 0x00000000; + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R3 + imm32 r3, 0xffffffff; + R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R3 + imm32 r3, 0x7fffffff; + R3 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r3, 0x7FFFFFFE; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R3 + R3 = 0; + ASTAT = R3; + imm32 r3, 0x80000000; + R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r3, 0x80000001; + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R4 + imm32 r4, 0x00000000; + ASTAT = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R4 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R4; + R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R3 = ASTAT; + R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AN); + CHECKREG r4, 0x00000000; + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R4 + imm32 r4, 0xffffffff; + R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R4 + imm32 r4, 0x7fffffff; + R4 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, 0x7FFFFFFE; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R4 + R4 = 0; + ASTAT = R4; + imm32 r4, 0x80000000; + R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r4, 0x80000001; + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R5 + imm32 r5, 0x00000000; + ASTAT = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R5 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + R0 = R5; + R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R5 + imm32 r5, 0xffffffff; + R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r4, (_AN); + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R5 + imm32 r5, 0x7fffffff; + R5 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, (_AC0|_AC0_COPY); + CHECKREG r5, 0x7FFFFFFE; + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R5 + R5 = 0; + ASTAT = R5; + imm32 r5, 0x80000000; + R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r4, (_AN); + CHECKREG r5, 0x80000001; + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R6 + imm32 r6, 0x00000000; + ASTAT = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R6 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R0 = ASTAT; + R6 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R6; + R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R6 + imm32 r6, 0xffffffff; + R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r4, (_AZ); + CHECKREG r5, (_AN); + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R6 + R6 = 0; + ASTAT = R6; + imm32 r6, 0x7fffffff; + R6 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_AC0|_AC0_COPY); + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, 0x7FFFFFFE; + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R6 + R6 = 0; + ASTAT = R6; + imm32 r6, 0x80000000; + R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_AN); + CHECKREG r5, (_AN); + CHECKREG r6, 0x80000001; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R7 + imm32 r7, 0x00000000; + ASTAT = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R1 = ASTAT; + R7 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R7; + R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, (_AZ); + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + +// AN, AC for R7 + imm32 r7, 0xffffffff; + R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + R0 = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r4, (_AC0|_AC0_COPY|_AZ); + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, 0xFFFFFFFF; + +// AC, AV0 for R7 + R7 = 0; + ASTAT = R7; + imm32 r7, 0x7fffffff; + R7 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, 0x7FFFFFFE; + +// AZ, AN, AC, AV0 for R7 + R7 = 0; + ASTAT = R7; + imm32 r7, 0x80000000; + R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_AC0|_AC0_COPY); + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, 0x80000001; + + pass diff --git a/tests/tcg/bfin/c_compi2opd_flags_2.S b/tests/tcg/bfin/c_compi2opd_flags_2.S new file mode 100644 index 0000000000000..94a8ef00885da --- /dev/null +++ b/tests/tcg/bfin/c_compi2opd_flags_2.S @@ -0,0 +1,600 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opd_flags_2/c_compi2opd_flags_2.dsp +// Spec Reference: compi2opd dregs += imm7 flags_2 (az, an, ac, av0) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = R0; // initialize astat + +// AZ for R0 + imm32 r0, 0x00000000; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R0 + imm32 r0, 0xffffffff; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R0; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R0 + imm32 r0, 0x7fffffff; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFE; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R0 + R0 = 0; + ASTAT = R0; + imm32 r0, 0x80000000; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000001; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R0 + imm32 r1, 0x00000000; + ASTAT = R1; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R1 + r1 = 0; + ASTAT = r1; + imm32 r1, 0xffffffff; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R1; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R1 + imm32 r1, 0x7fffffff; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFE; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R1 + R1 = 0; + ASTAT = R1; + imm32 r1, 0x80000000; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000001; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R2 + imm32 r2, 0x00000000; + ASTAT = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R2 += 2; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -2; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R2; + R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R2 + R2 = 0; + ASTAT = R2; + imm32 r2, 0xffffffff; + R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r2, 0xFFFFFFFF; + CHECKREG r1, (_AZ); + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R2 + imm32 r2, 0x7fffffff; + R2 += 2; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += -2; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000001; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x7FFFFFFD; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R2 + R2 = 0; + ASTAT = R2; + imm32 r2, 0x80000000; + R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += 2; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += 2; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFE; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x80000002; + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R3 + imm32 r3, 0x00000000; + ASTAT = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R3 += 3; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -3; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R3; + R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, 0x00000000; + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R3 + imm32 r3, 0xffffffff; + R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000002; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R3 + imm32 r3, 0x7fffffff; + R3 += 3; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += -3; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000002; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r3, 0x7FFFFFFC; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R3 + R3 = 0; + ASTAT = R3; + imm32 r3, 0x80000000; + R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += 3; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += 3; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFD; + CHECKREG r1, 0x80000000; + CHECKREG r3, 0x80000003; + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R4 + imm32 r4, 0x00000000; + ASTAT = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R4 += 4; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -4; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R4; + R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0 + R3 = ASTAT; + R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AN); + CHECKREG r4, 0x00000000; + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R4 + imm32 r4, 0xffffffff; + R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000003; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R4 + imm32 r4, 0x7fffffff; + R4 += 4; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += -4; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x80000003; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, 0x7FFFFFFB; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R4 + R4 = 0; + ASTAT = R4; + imm32 r4, 0x80000000; + R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += 4; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += 4; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x7FFFFFFC; + CHECKREG r2, 0x80000000; + CHECKREG r4, 0x80000004; + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R5 + imm32 r5, 0x00000000; + ASTAT = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R5 += 5; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -5; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + R0 = R5; + R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R5 + imm32 r5, 0xffffffff; + R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x00000004; + CHECKREG r4, (_AN); + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R5 + imm32 r5, 0x7fffffff; + R5 += 5; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += -5; // az = 0 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x80000004; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, (_AC0|_AC0_COPY); + CHECKREG r5, 0x7FFFFFFA; + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R5 + R5 = 0; + ASTAT = R5; + imm32 r5, 0x80000000; + R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += 5; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += 5; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x7FFFFFFB; + CHECKREG r2, 0x80000000; + CHECKREG r4, (_AN); + CHECKREG r5, 0x80000005; + CHECKREG r6, (_AN); + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R6 + imm32 r6, 0x00000000; + ASTAT = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R6 += 6; // az = 0 an = 0 ac = 0 av0 = 0 + R0 = ASTAT; + R6 += -6; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R6; + R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R6 + imm32 r6, 0xffffffff; + R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000005; + CHECKREG r4, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R6 + imm32 r6, 0x7fffffff; + R6 += 6; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += -6; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000005; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_AC0|_AC0_COPY); + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, 0x7FFFFFF9; + CHECKREG r7, (_AN); + +// AZ, AN, AC, AV0 for R6 + R6 = 0; + ASTAT = R6; + imm32 r6, 0x80000000; + R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += 6; // az = 1 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += 6; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFA; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_AN); + CHECKREG r5, (_AN); + CHECKREG r6, 0x80000006; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AZ for R7 + imm32 r7, 0x00000000; + ASTAT = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R1 = ASTAT; + R7 += 7; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -7; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R7; + R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, (_AZ); + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + +// AN, AC for R7 + imm32 r7, 0xffffffff; + R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + R0 = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000006; + CHECKREG r4, (_AC0|_AC0_COPY); + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, 0xFFFFFFFF; + +// AC, AV0 for R7 + imm32 r7, 0x7fffffff; + R7 += 7; // az = 0 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += -7; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000006; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, 0x7FFFFFF8; + +// AZ, AN, AC, AV0 for R7 + R7 = 0; + ASTAT = R7; + imm32 r7, 0x80000000; + R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += 7; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += 7; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFF9; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_AC0|_AC0_COPY); + CHECKREG r5, (_AN); + CHECKREG r6, (_AN); + CHECKREG r7, 0x80000007; + + pass diff --git a/tests/tcg/bfin/c_compi2opp_pr_add_i7_n.s b/tests/tcg/bfin/c_compi2opp_pr_add_i7_n.s new file mode 100644 index 0000000000000..b63cb86a05237 --- /dev/null +++ b/tests/tcg/bfin/c_compi2opp_pr_add_i7_n.s @@ -0,0 +1,149 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_n/c_compi2opp_pr_add_i7_n.dsp +// Spec Reference: compi2opp pregs += imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + INIT_P_REGS 0; + + imm32 sp, 0x00000000; + imm32 fp, 0x00000000; + + P1 += -1; + P2 += -2; + P3 += -3; + P4 += -4; + P5 += -5; + SP += -6; + FP += -7; + CHECKREG p1, 0xFFFFFFFF; + CHECKREG p2, 0xFFFFFFFE; + CHECKREG p3, 0xFFFFFFFD; + CHECKREG p4, 0xFFFFFFFC; + CHECKREG p5, 0xFFFFFFFB; + CHECKREG sp, 0xFFFFFFFA; + CHECKREG fp, 0xFFFFFFF9; + + P1 += -9; + P2 += -10; + P3 += -11; + P4 += -12; + P5 += -13; + SP += -14; + FP += -15; + CHECKREG p1, 0xFFFFFFF6; + CHECKREG p2, 0xFFFFFFF4; + CHECKREG p3, 0xFFFFFFF2; + CHECKREG p4, 0xFFFFFFF0; + CHECKREG p5, 0xFFFFFFEE; + CHECKREG sp, 0xFFFFFFEC; + CHECKREG fp, 0xFFFFFFEA; + + P1 += -17; + P2 += -18; + P3 += -19; + P4 += -20; + P5 += -21; + SP += -22; + FP += -23; + CHECKREG p1, 0xFFFFFFE5; + CHECKREG p2, 0xFFFFFFE2; + CHECKREG p3, 0xFFFFFFDF; + CHECKREG p4, 0xFFFFFFDC; + CHECKREG p5, 0xFFFFFFD9; + CHECKREG sp, 0xFFFFFFD6; + CHECKREG fp, 0xFFFFFFD3; + + P1 += -25; + P2 += -26; + P3 += -27; + P4 += -28; + P5 += -29; + SP += -30; + FP += -31; + CHECKREG p1, 0xFFFFFFCC; + CHECKREG p2, 0xFFFFFFC8; + CHECKREG p3, 0xFFFFFFC4; + CHECKREG p4, 0xFFFFFFC0; + CHECKREG p5, 0xFFFFFFBC; + CHECKREG sp, 0xFFFFFFB8; + CHECKREG fp, 0xFFFFFFB4; + + P1 += -33; + P2 += -34; + P3 += -35; + P4 += -36; + P5 += -37; + SP += -38; + FP += -39; + CHECKREG p1, 0xFFFFFFAB; + CHECKREG p2, 0xFFFFFFA6; + CHECKREG p3, 0xFFFFFFA1; + CHECKREG p4, 0xFFFFFF9C; + CHECKREG p5, 0xFFFFFF97; + CHECKREG sp, 0xFFFFFF92; + CHECKREG fp, 0xFFFFFF8D; + + P1 += -41; + P2 += -42; + P3 += -43; + P4 += -44; + P5 += -45; + SP += -46; + FP += -47; + CHECKREG p1, 0xFFFFFF82; + CHECKREG p2, 0xFFFFFF7C; + CHECKREG p3, 0xFFFFFF76; + CHECKREG p4, 0xFFFFFF70; + CHECKREG p5, 0xFFFFFF6A; + CHECKREG sp, 0xFFFFFF64; + CHECKREG fp, 0xFFFFFF5E; + + P1 += -49; + P2 += -50; + P3 += -51; + P4 += -52; + P5 += -53; + SP += -54; + FP += -55; + CHECKREG p1, 0xFFFFFF51; + CHECKREG p2, 0xFFFFFF4A; + CHECKREG p3, 0xFFFFFF43; + CHECKREG p4, 0xFFFFFF3C; + CHECKREG p5, 0xFFFFFF35; + CHECKREG sp, 0xFFFFFF2E; + CHECKREG fp, 0xFFFFFF27; + + P1 += -57; + P2 += -58; + P3 += -59; + P4 += -60; + P5 += -61; + SP += -62; + FP += -63; + CHECKREG p1, 0xFFFFFF18; + CHECKREG p2, 0xFFFFFF10; + CHECKREG p3, 0xFFFFFF08; + CHECKREG p4, 0xFFFFFF00; + CHECKREG p5, 0xFFFFFEF8; + CHECKREG sp, 0xFFFFFEF0; + CHECKREG fp, 0xFFFFFEE8; + + P1 += -64; + P2 += -64; + P3 += -64; + P4 += -64; + P5 += -64; + SP += -64; + FP += -64; + CHECKREG p1, 0xFFFFFED8; + CHECKREG p2, 0xFFFFFED0; + CHECKREG p3, 0xFFFFFEC8; + CHECKREG p4, 0xFFFFFEC0; + CHECKREG p5, 0xFFFFFEB8; + CHECKREG sp, 0xFFFFFEB0; + CHECKREG fp, 0xFFFFFEA8; + + pass diff --git a/tests/tcg/bfin/c_compi2opp_pr_add_i7_p.s b/tests/tcg/bfin/c_compi2opp_pr_add_i7_p.s new file mode 100644 index 0000000000000..75336a8449e89 --- /dev/null +++ b/tests/tcg/bfin/c_compi2opp_pr_add_i7_p.s @@ -0,0 +1,116 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_p/c_compi2opp_pr_add_i7_p.dsp +// Spec Reference: compi2opp pregs += imm7 positive +# mach: bfin + +.include "testutils.inc" + start + + INIT_P_REGS 0; + + imm32 fp, 0x00000000; + + P1 += 1; + P2 += 2; + P3 += 3; + P4 += 4; + P5 += 5; + FP += 7; + CHECKREG p1, 0x00000001; + CHECKREG p2, 0x00000002; + CHECKREG p3, 0x00000003; + CHECKREG p4, 0x00000004; + CHECKREG p5, 0x00000005; + CHECKREG fp, 0x00000007; + + P1 += 9; + P2 += 10; + P3 += 11; + P4 += 12; + P5 += 13; + FP += 15; + CHECKREG p1, 0x0000000A; + CHECKREG p2, 0x0000000C; + CHECKREG p3, 0x0000000E; + CHECKREG p4, 0x00000010; + CHECKREG p5, 0x00000012; + CHECKREG fp, 0x00000016; + + P1 += 17; + P2 += 18; + P3 += 19; + P4 += 20; + P5 += 21; + FP += 23; + CHECKREG p1, 0x0000001B; + CHECKREG p2, 0x0000001E; + CHECKREG p3, 0x00000021; + CHECKREG p4, 0x00000024; + CHECKREG p5, 0x00000027; + CHECKREG fp, 0x0000002D; + + P1 += 25; + P2 += 26; + P3 += 27; + P4 += 28; + P5 += 29; + FP += 31; + CHECKREG p1, 0x00000034; + CHECKREG p2, 0x00000038; + CHECKREG p3, 0x0000003C; + CHECKREG p4, 0x00000040; + CHECKREG p5, 0x00000044; + CHECKREG fp, 0x0000004C; + + P1 += 33; + P2 += 34; + P3 += 35; + P4 += 36; + P5 += 37; + FP += 39; + CHECKREG p1, 0x00000055; + CHECKREG p2, 0x0000005A; + CHECKREG p3, 0x0000005F; + CHECKREG p4, 0x00000064; + CHECKREG p5, 0x00000069; + CHECKREG fp, 0x00000073; + + P1 += 41; + P2 += 42; + P3 += 43; + P4 += 44; + P5 += 45; + FP += 47; + CHECKREG p1, 0x0000007E; + CHECKREG p2, 0x00000084; + CHECKREG p3, 0x0000008A; + CHECKREG p4, 0x00000090; + CHECKREG p5, 0x00000096; + CHECKREG fp, 0x000000A2; + + P1 += 49; + P2 += 50; + P3 += 51; + P4 += 52; + P5 += 53; + FP += 55; + CHECKREG p1, 0x000000AF; + CHECKREG p2, 0x000000B6; + CHECKREG p3, 0x000000BD; + CHECKREG p4, 0x000000C4; + CHECKREG p5, 0x000000CB; + CHECKREG fp, 0x000000D9; + + P1 += 57; + P2 += 58; + P3 += 59; + P4 += 60; + P5 += 61; + FP += 63; + CHECKREG p1, 0x000000E8; + CHECKREG p2, 0x000000F0; + CHECKREG p3, 0x000000F8; + CHECKREG p4, 0x00000100; + CHECKREG p5, 0x00000108; + CHECKREG fp, 0x00000118; + + pass diff --git a/tests/tcg/bfin/c_compi2opp_pr_eq_i7_n.s b/tests/tcg/bfin/c_compi2opp_pr_eq_i7_n.s new file mode 100644 index 0000000000000..efeeb692de075 --- /dev/null +++ b/tests/tcg/bfin/c_compi2opp_pr_eq_i7_n.s @@ -0,0 +1,161 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_n/c_compi2opp_pr_eq_i7_n.dsp +// Spec Reference: compi2opp pregs = imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + R0 = -0; + P1 = -1; + P2 = -2; + P3 = -3; + P4 = -4; + P5 = -5; + SP = -6; + FP = -7; + CHECKREG r0, -0; + CHECKREG p1, -1; + CHECKREG p2, -2; + CHECKREG p3, -3; + CHECKREG p4, -4; + CHECKREG p5, -5; + CHECKREG sp, -6; + CHECKREG fp, -7; + + R0 = -8; + P1 = -9; + P2 = -10; + P3 = -11; + P4 = -12; + P5 = -13; + SP = -14; + FP = -15; + CHECKREG r0, -8; + CHECKREG p1, -9; + CHECKREG p2, -10; + CHECKREG p3, -11; + CHECKREG p4, -12; + CHECKREG p5, -13; + CHECKREG sp, -14; + CHECKREG fp, -15; + + R0 = -16; + P1 = -17; + P2 = -18; + P3 = -19; + P4 = -20; + P5 = -21; + SP = -22; + FP = -23; + CHECKREG r0, -16; + CHECKREG p1, -17; + CHECKREG p2, -18; + CHECKREG p3, -19; + CHECKREG p4, -20; + CHECKREG p5, -21; + CHECKREG sp, -22; + CHECKREG fp, -23; + + R0 = -24; + P1 = -25; + P2 = -26; + P3 = -27; + P4 = -28; + P5 = -29; + SP = -30; + FP = -31; + CHECKREG r0, -24; + CHECKREG p1, -25; + CHECKREG p2, -26; + CHECKREG p3, -27; + CHECKREG p4, -28; + CHECKREG p5, -29; + CHECKREG sp, -30; + CHECKREG fp, -31; + + R0 = -32; + P1 = -33; + P2 = -34; + P3 = -35; + P4 = -36; + P5 = -37; + SP = -38; + FP = -39; + CHECKREG r0, -32; + CHECKREG p1, -33; + CHECKREG p2, -34; + CHECKREG p3, -35; + CHECKREG p4, -36; + CHECKREG p5, -37; + CHECKREG sp, -38; + CHECKREG fp, -39; + + R0 = -40; + P1 = -41; + P2 = -42; + P3 = -43; + P4 = -44; + P5 = -45; + SP = -46; + FP = -47; + CHECKREG r0, -40; + CHECKREG p1, -41; + CHECKREG p2, -42; + CHECKREG p3, -43; + CHECKREG p4, -44; + CHECKREG p5, -45; + CHECKREG sp, -46; + CHECKREG fp, -47; + + R0 = -48; + P1 = -49; + P2 = -50; + P3 = -51; + P4 = -52; + P5 = -53; + SP = -54; + FP = -55; + CHECKREG r0, -48; + CHECKREG p1, -49; + CHECKREG p2, -50; + CHECKREG p3, -51; + CHECKREG p4, -52; + CHECKREG p5, -53; + CHECKREG sp, -54; + CHECKREG fp, -55; + + R0 = -56; + P1 = -57; + P2 = -58; + P3 = -59; + P4 = -60; + P5 = -61; + SP = -62; + FP = -63; + CHECKREG r0, -56; + CHECKREG p1, -57; + CHECKREG p2, -58; + CHECKREG p3, -59; + CHECKREG p4, -60; + CHECKREG p5, -61; + CHECKREG sp, -62; + CHECKREG fp, -63; + + R0 = -64; + P1 = -64; + P2 = -64; + P3 = -64; + P4 = -64; + P5 = -64; + SP = -64; + FP = -64; + CHECKREG r0, -64; + CHECKREG p1, -64; + CHECKREG p2, -64; + CHECKREG p3, -64; + CHECKREG p4, -64; + CHECKREG p5, -64; + CHECKREG sp, -64; + CHECKREG fp, -64; + + pass diff --git a/tests/tcg/bfin/c_compi2opp_pr_eq_i7_p.s b/tests/tcg/bfin/c_compi2opp_pr_eq_i7_p.s new file mode 100644 index 0000000000000..75433bcb18e2d --- /dev/null +++ b/tests/tcg/bfin/c_compi2opp_pr_eq_i7_p.s @@ -0,0 +1,131 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_p/c_compi2opp_pr_eq_i7_p.dsp +// Spec Reference: compi2opd pregs = imm7 positive +# mach: bfin + +.include "testutils.inc" + start + +//R0 = 0; + P1 = 1; + P2 = 2; + P3 = 3; + P4 = 4; + P5 = 5; + SP = 6; + FP = 7; + CHECKREG p1, 1; + CHECKREG p2, 2; + CHECKREG p3, 3; + CHECKREG p4, 4; + CHECKREG p5, 5; + CHECKREG sp, 6; + CHECKREG fp, 7; + + P1 = 9; + P2 = 10; + P3 = 11; + P4 = 12; + P5 = 13; + SP = 14; + FP = 15; + CHECKREG p1, 9; + CHECKREG p2, 10; + CHECKREG p3, 11; + CHECKREG p4, 12; + CHECKREG p5, 13; + CHECKREG sp, 14; + CHECKREG fp, 15; + + P1 = 17; + P2 = 18; + P3 = 19; + P4 = 20; + P5 = 21; + SP = 22; + FP = 23; + CHECKREG p1, 17; + CHECKREG p2, 18; + CHECKREG p3, 19; + CHECKREG p4, 20; + CHECKREG p5, 21; + CHECKREG sp, 22; + CHECKREG fp, 23; + + P1 = 25; + P2 = 26; + P3 = 27; + P4 = 28; + P5 = 29; + SP = 30; + FP = 31; + CHECKREG p1, 25; + CHECKREG p2, 26; + CHECKREG p3, 27; + CHECKREG p4, 28; + CHECKREG p5, 29; + CHECKREG sp, 30; + CHECKREG fp, 31; + + R0 = 32; + P1 = 33; + P2 = 34; + P3 = 35; + P4 = 36; + P5 = 37; + SP = 38; + FP = 39; + CHECKREG r0, 32; + CHECKREG p1, 33; + CHECKREG p2, 34; + CHECKREG p3, 35; + CHECKREG p4, 36; + CHECKREG p5, 37; + CHECKREG sp, 38; + CHECKREG fp, 39; + + P1 = 41; + P2 = 42; + P3 = 43; + P4 = 44; + P5 = 45; + SP = 46; + FP = 47; + CHECKREG p1, 41; + CHECKREG p2, 42; + CHECKREG p3, 43; + CHECKREG p4, 44; + CHECKREG p5, 45; + CHECKREG sp, 46; + CHECKREG fp, 47; + + P1 = 49; + P2 = 50; + P3 = 51; + P4 = 52; + P5 = 53; + SP = 54; + FP = 55; + CHECKREG p1, 49; + CHECKREG p2, 50; + CHECKREG p3, 51; + CHECKREG p4, 52; + CHECKREG p5, 53; + CHECKREG sp, 54; + CHECKREG fp, 55; + + P1 = 57; + P2 = 58; + P3 = 59; + P4 = 60; + P5 = 61; + SP = 62; + FP = 63; + CHECKREG p1, 57; + CHECKREG p2, 58; + CHECKREG p3, 59; + CHECKREG p4, 60; + CHECKREG p5, 61; + CHECKREG sp, 62; + CHECKREG fp, 63; + + pass diff --git a/tests/tcg/bfin/c_dagmodik_lnz_imgebl.s b/tests/tcg/bfin/c_dagmodik_lnz_imgebl.s new file mode 100644 index 0000000000000..cea97ad4fac2b --- /dev/null +++ b/tests/tcg/bfin/c_dagmodik_lnz_imgebl.s @@ -0,0 +1,290 @@ +//Original:/testcases/core/c_dagmodik_lnz_imgebl/c_dagmodik_lnz_imgebl.dsp +// Spec Reference: dagmodik l not zero & i+m >= b+l +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x00001000; +imm32 b1, 0x00001000; +imm32 b2, 0x00001000; +imm32 b3, 0x00001000; + +imm32 l0, 0x00000001; +imm32 l1, 0x00000002; +imm32 l2, 0x00000003; +imm32 l3, 0x00000004; + +imm32 m0, 0x00000015; +imm32 m1, 0x00000016; +imm32 m2, 0x00000017; +imm32 m3, 0x00000018; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x0000100F; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001002; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x0000100E; +CHECKREG r7, 0x00001001; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x000010FE; +CHECKREG r2, 0x0000100C; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00000FFF; +CHECKREG r5, 0x000010FC; +CHECKREG r6, 0x0000100A; +CHECKREG r7, 0x00001001; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x000010FE; +CHECKREG r2, 0x0000100B; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x0000100C; +CHECKREG r7, 0x00001001; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00000FFE; +CHECKREG r1, 0x000010F8; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x0000100C; +CHECKREG r7, 0x00001001; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00000FFE; +CHECKREG r1, 0x000010F8; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00000FF8; +CHECKREG r5, 0x000010F0; +CHECKREG r6, 0x00000FFF; +CHECKREG r7, 0x00001001; + +// i+m = b+l +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x00001000; +imm32 b1, 0x00001100; +imm32 b2, 0x00001010; +imm32 b3, 0x00001001; + +imm32 l0, 0x00000015; +imm32 l1, 0x00000016; +imm32 l2, 0x00000017; +imm32 l3, 0x00000018; + +imm32 m0, 0x00000015; +imm32 m1, 0x00000016; +imm32 m2, 0x00000017; +imm32 m3, 0x00000018; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001014; +CHECKREG r7, 0x00001005; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x00001010; +CHECKREG r7, 0x00001001; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001104; +CHECKREG r2, 0x00001014; +CHECKREG r3, 0x00001005; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001018; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001010; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001018; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001010; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x0000100D; +CHECKREG r5, 0x0000110E; +CHECKREG r6, 0x0000101F; +CHECKREG r7, 0x00001011; + + + +pass diff --git a/tests/tcg/bfin/c_dagmodik_lnz_imltbl.s b/tests/tcg/bfin/c_dagmodik_lnz_imltbl.s new file mode 100644 index 0000000000000..7142682863dc1 --- /dev/null +++ b/tests/tcg/bfin/c_dagmodik_lnz_imltbl.s @@ -0,0 +1,289 @@ +//Original:/testcases/core/c_dagmodik_lnz_imltbl/c_dagmodik_lnz_imltbl.dsp +// Spec Reference: dagmodik l not zero & i+m < b +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x0000100e; +imm32 b1, 0x0000110c; +imm32 b2, 0x0000101a; +imm32 b3, 0x00001008; + +imm32 l0, 0x000000a1; +imm32 l1, 0x000000b2; +imm32 l2, 0x000000c3; +imm32 l3, 0x000000d4; + +imm32 m0, 0x00000005; +imm32 m1, 0x00000004; +imm32 m2, 0x00000003; +imm32 m3, 0x00000002; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001014; +CHECKREG r7, 0x00001005; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A3; +CHECKREG r1, 0x000011B4; +CHECKREG r2, 0x000010D5; +CHECKREG r3, 0x000010D7; +CHECKREG r4, 0x000010A1; +CHECKREG r5, 0x000011B2; +CHECKREG r6, 0x000010D3; +CHECKREG r7, 0x000010D5; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A5; +CHECKREG r1, 0x000011B6; +CHECKREG r2, 0x000010D7; +CHECKREG r3, 0x000010D9; +CHECKREG r4, 0x000010A9; +CHECKREG r5, 0x000011BA; +CHECKREG r6, 0x000010DB; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x000010A1; +CHECKREG r1, 0x000011B2; +CHECKREG r2, 0x000010D3; +CHECKREG r3, 0x000010D5; +CHECKREG r4, 0x000010A9; +CHECKREG r5, 0x000011BA; +CHECKREG r6, 0x000010DB; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A1; +CHECKREG r1, 0x000011B2; +CHECKREG r2, 0x000010D3; +CHECKREG r3, 0x000010D5; +CHECKREG r4, 0x00001099; +CHECKREG r5, 0x000011AA; +CHECKREG r6, 0x000010CB; +CHECKREG r7, 0x000010CD; + +// i+m = b+l +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x0000100e; +imm32 b1, 0x0000110c; +imm32 b2, 0x0000101a; +imm32 b3, 0x00001008; + +imm32 l0, 0x00000011; +imm32 l1, 0x00000012; +imm32 l2, 0x00000013; +imm32 l3, 0x00000014; + +imm32 m0, 0x00000002; +imm32 m1, 0x00000003; +imm32 m2, 0x00000004; +imm32 m3, 0x00000005; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001014; +CHECKREG r7, 0x00001005; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001013; +CHECKREG r1, 0x00001114; +CHECKREG r2, 0x00001025; +CHECKREG r3, 0x00001017; +CHECKREG r4, 0x00001011; +CHECKREG r5, 0x00001112; +CHECKREG r6, 0x00001023; +CHECKREG r7, 0x00001015; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001015; +CHECKREG r1, 0x00001116; +CHECKREG r2, 0x00001027; +CHECKREG r3, 0x00001019; +CHECKREG r4, 0x00001019; +CHECKREG r5, 0x0000111A; +CHECKREG r6, 0x0000102B; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00001011; +CHECKREG r1, 0x00001112; +CHECKREG r2, 0x00001023; +CHECKREG r3, 0x00001015; +CHECKREG r4, 0x00001019; +CHECKREG r5, 0x0000111A; +CHECKREG r6, 0x0000102B; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001011; +CHECKREG r1, 0x00001112; +CHECKREG r2, 0x00001023; +CHECKREG r3, 0x00001015; +CHECKREG r4, 0x0000101A; +CHECKREG r5, 0x0000111C; +CHECKREG r6, 0x0000101B; +CHECKREG r7, 0x0000100D; + + + +pass diff --git a/tests/tcg/bfin/c_dagmodik_lz_inc_dec.s b/tests/tcg/bfin/c_dagmodik_lz_inc_dec.s new file mode 100644 index 0000000000000..64ac94664634e --- /dev/null +++ b/tests/tcg/bfin/c_dagmodik_lz_inc_dec.s @@ -0,0 +1,140 @@ +//Original:/testcases/core/c_dagmodik_lz_inc_dec/c_dagmodik_lz_inc_dec.dsp +// Spec Reference: dagmodik L=0, I incremented & decremented +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001200; +imm32 i3, 0x00001300; +imm32 m0, 0x00000000; +imm32 m1, 0x00000110; +imm32 m2, 0x00000210; +imm32 m3, 0x00000310; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001202; +CHECKREG r3, 0x00001302; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001204; +CHECKREG r7, 0x00001304; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001202; +CHECKREG r3, 0x00001302; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x00001200; +CHECKREG r7, 0x00001300; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001104; +CHECKREG r2, 0x00001204; +CHECKREG r3, 0x00001304; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001208; +CHECKREG r7, 0x00001308; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001200; +CHECKREG r3, 0x00001300; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001208; +CHECKREG r7, 0x00001308; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001200; +CHECKREG r3, 0x00001300; +CHECKREG r4, 0x00000FF8; +CHECKREG r5, 0x000010F8; +CHECKREG r6, 0x000011F8; +CHECKREG r7, 0x000012F8; + + + +pass diff --git a/tests/tcg/bfin/c_dagmodim_lnz_imgebl.s b/tests/tcg/bfin/c_dagmodim_lnz_imgebl.s new file mode 100644 index 0000000000000..4189c054716e5 --- /dev/null +++ b/tests/tcg/bfin/c_dagmodim_lnz_imgebl.s @@ -0,0 +1,108 @@ +//Original:/testcases/core/c_dagmodim_lnz_imgebl/c_dagmodim_lnz_imgebl.dsp +// Spec Reference: dagmodim l not zero & i+m >= b+l +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x00001000; +imm32 b1, 0x00001000; +imm32 b2, 0x00001000; +imm32 b3, 0x00001000; + +imm32 l0, 0x00000001; +imm32 l1, 0x00000002; +imm32 l2, 0x00000003; +imm32 l3, 0x00000004; + +imm32 m0, 0x00000015; +imm32 m1, 0x00000016; +imm32 m2, 0x00000017; +imm32 m3, 0x00000018; + + I0 += M0; + I1 += M1; + I2 += M2; + I3 += M3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M1; + I1 += M2; + I2 += M3; + I3 += M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; + +CHECKREG r0, 0x00001014; +CHECKREG r1, 0x00001114; +CHECKREG r2, 0x00001024; +CHECKREG r3, 0x00001015; +CHECKREG r4, 0x00001029; +CHECKREG r5, 0x00001129; +CHECKREG r6, 0x00001039; +CHECKREG r7, 0x00001026; + + I0 -= M2; + I1 -= M3; + I2 -= M0; + I3 -= M1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= M3; + I1 -= M2; + I2 -= M1; + I3 -= M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001012; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00001024; +CHECKREG r3, 0x00001010; +CHECKREG r4, 0x00000FFB; +CHECKREG r5, 0x000010FA; +CHECKREG r6, 0x0000100E; +CHECKREG r7, 0x00000FFF; + + I0 += M3 (BREV); + I1 += M0 (BREV); + I2 += M1 (BREV); + I3 += M2 (BREV); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M2 (BREV); + I1 += M3 (BREV); + I2 += M0 (BREV); + I3 += M1 (BREV); +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00000FEF; +CHECKREG r1, 0x000010E0; +CHECKREG r2, 0x0000101B; +CHECKREG r3, 0x00000FE7; +CHECKREG r4, 0x00000FFB; +CHECKREG r5, 0x000010F8; +CHECKREG r6, 0x00001001; +CHECKREG r7, 0x00000FF2; + + +pass diff --git a/tests/tcg/bfin/c_dagmodim_lnz_imltbl.s b/tests/tcg/bfin/c_dagmodim_lnz_imltbl.s new file mode 100644 index 0000000000000..152c94b15fa91 --- /dev/null +++ b/tests/tcg/bfin/c_dagmodim_lnz_imltbl.s @@ -0,0 +1,109 @@ +//Original:/testcases/core/c_dagmodim_lnz_imltbl/c_dagmodim_lnz_imltbl.dsp +// Spec Reference: dagmodim l not zero & i+m < b +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x0000110e; +imm32 b1, 0x0000110c; +imm32 b2, 0x0000110a; +imm32 b3, 0x00001108; + +imm32 l0, 0x000000a1; +imm32 l1, 0x000000b2; +imm32 l2, 0x000000c3; +imm32 l3, 0x000000d4; + +imm32 m0, 0x00000005; +imm32 m1, 0x00000004; +imm32 m2, 0x00000003; +imm32 m3, 0x00000002; + + I0 += M0; + I1 += M1; + I2 += M2; + I3 += M3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M1; + I1 += M2; + I2 += M3; + I3 += M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001005; +CHECKREG r1, 0x00001104; +CHECKREG r2, 0x00001013; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001009; +CHECKREG r5, 0x00001107; +CHECKREG r6, 0x00001015; +CHECKREG r7, 0x00001008; + + + I0 -= M2; + I1 -= M3; + I2 -= M0; + I3 -= M1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= M3; + I1 -= M2; + I2 -= M1; + I3 -= M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A7; +CHECKREG r1, 0x000011B7; +CHECKREG r2, 0x000010D3; +CHECKREG r3, 0x000010D8; +CHECKREG r4, 0x00001146; +CHECKREG r5, 0x000011B4; +CHECKREG r6, 0x00001192; +CHECKREG r7, 0x000011A7; + + I0 += M3 (BREV); + I1 += M0 (BREV); + I2 += M1 (BREV); + I3 += M2 (BREV); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M2 (BREV); + I1 += M3 (BREV); + I2 += M0 (BREV); + I3 += M1 (BREV); +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001145; +CHECKREG r1, 0x000011B3; +CHECKREG r2, 0x00001196; +CHECKREG r3, 0x000011A5; +CHECKREG r4, 0x00001146; +CHECKREG r5, 0x000011B0; +CHECKREG r6, 0x00001190; +CHECKREG r7, 0x000011A3; + + + +pass diff --git a/tests/tcg/bfin/c_dagmodim_lz_inc_dec.s b/tests/tcg/bfin/c_dagmodim_lz_inc_dec.s new file mode 100644 index 0000000000000..094a7d82d6df8 --- /dev/null +++ b/tests/tcg/bfin/c_dagmodim_lz_inc_dec.s @@ -0,0 +1,98 @@ +//Original:/testcases/core/c_dagmodim_lz_inc_dec/c_dagmodim_lz_inc_dec.dsp +// Spec Reference: dagmodim L=0, I incremented & decremented (by M) +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x10001000; +imm32 i1, 0x02001100; +imm32 i2, 0x00301010; +imm32 i3, 0x00041001; + +imm32 m0, 0x00000005; +imm32 m1, 0x00000006; +imm32 m2, 0x00000007; +imm32 m3, 0x00000008; + + I0 += M0; + I1 += M1; + I2 += M2; + I3 += M3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M1; + I1 += M2; + I2 += M3; + I3 += M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; + +CHECKREG r0, 0x10001005; +CHECKREG r1, 0x02001106; +CHECKREG r2, 0x00301017; +CHECKREG r3, 0x00041009; +CHECKREG r4, 0x1000100B; +CHECKREG r5, 0x0200110D; +CHECKREG r6, 0x0030101F; +CHECKREG r7, 0x0004100E; + + I0 -= M2; + I1 -= M3; + I2 -= M0; + I3 -= M1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= M3; + I1 -= M2; + I2 -= M1; + I3 -= M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x10001004; +CHECKREG r1, 0x02001105; +CHECKREG r2, 0x0030101A; +CHECKREG r3, 0x00041008; +CHECKREG r4, 0x10000FFC; +CHECKREG r5, 0x020010FE; +CHECKREG r6, 0x00301014; +CHECKREG r7, 0x00041003; + + I0 += M3 (BREV); + I1 += M0 (BREV); + I2 += M1 (BREV); + I3 += M2 (BREV); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M2 (BREV); + I1 += M3 (BREV); + I2 += M0 (BREV); + I3 += M1 (BREV); +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x10000FF2; +CHECKREG r1, 0x020010F8; +CHECKREG r2, 0x00301011; +CHECKREG r3, 0x00041005; +CHECKREG r4, 0x10000FF4; +CHECKREG r5, 0x020010F4; +CHECKREG r6, 0x00301014; +CHECKREG r7, 0x00041000; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_a_neg_a.s b/tests/tcg/bfin/c_dsp32alu_a_neg_a.s new file mode 100644 index 0000000000000..263e900dc6d53 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_a_neg_a.s @@ -0,0 +1,34 @@ +//Original:/testcases/core/c_dsp32alu_a_neg_a/c_dsp32alu_a_neg_a.dsp +// Spec Reference: dsp32alu a = neg a +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A1 = A0 = 0; +A0 = R0; + +A0 = - A0; +A1 = - A0; +A1 = - A1; +A0 = - A1; +R1 = A0.w; +R2 = A1.w; +CHECKREG r0, 0xA5678911; +CHECKREG r1, 0xA5678911; +CHECKREG r2, 0x5A9876EF; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_aa_absabs.s b/tests/tcg/bfin/c_dsp32alu_aa_absabs.s new file mode 100644 index 0000000000000..fd505f0c6c08e --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_aa_absabs.s @@ -0,0 +1,35 @@ +//Original:/testcases/core/c_dsp32alu_aa_absabs/c_dsp32alu_aa_absabs.dsp +// Spec Reference: dsp32alu a1, a0 = abs / abs a1, a0 +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A0 = R0; +A1 = R1; + +A1 = ABS A1, A0 = ABS A0; +R2 = A0.w; +R3 = A1.w; +A1 = ABS A1, A0 = ABS A0; +R4 = A0.w; +R5 = A1.w; +CHECKREG r2, 0x5A9876EF; +CHECKREG r3, 0x2789AB1D; +CHECKREG r4, 0x5A9876EF; +CHECKREG r5, 0x2789AB1D; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_aa_negneg.s b/tests/tcg/bfin/c_dsp32alu_aa_negneg.s new file mode 100644 index 0000000000000..4d6f4bf8e0ada --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_aa_negneg.s @@ -0,0 +1,35 @@ +//Original:/testcases/core/c_dsp32alu_aa_negneg/c_dsp32alu_aa_negneg.dsp +// Spec Reference: dsp32alu a1, a0 = neg / neg a1, a0 +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A0 = R0; +A1 = R1; + +A1 = - A1, A0 = - A0; +R2 = A0.w; +R3 = A1.w; +A1 = - A1, A0 = - A0; +R4 = A0.w; +R5 = A1.w; +CHECKREG r2, 0x5A9876EF; +CHECKREG r3, 0xD87654E3; +CHECKREG r4, 0xA5678911; +CHECKREG r5, 0x2789AB1D; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_abs.s b/tests/tcg/bfin/c_dsp32alu_abs.s new file mode 100644 index 0000000000000..0504a7b337275 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_abs.s @@ -0,0 +1,62 @@ +//Original:/testcases/core/c_dsp32alu_abs/c_dsp32alu_abs.dsp +// Spec Reference: dsp32alu dregs = abs ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = ABS R0; +R1 = ABS R1; +R2 = ABS R2; +R3 = ABS R3; +R4 = ABS R4; +R5 = ABS R5; +R6 = ABS R6; +R7 = ABS R7; +CHECKREG r0, 0x15678911; +CHECKREG r1, 0x2789AB1D; +CHECKREG r2, 0x34445515; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0x5567891B; +CHECKREG r5, 0x6789AB1D; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x79998889; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = ABS R7; +R1 = ABS R6; +R2 = ABS R5; +R3 = ABS R4; +R4 = ABS R3; +R5 = ABS R2; +R6 = ABS R1; +R7 = ABS R0; +CHECKREG r0, 0x0EEEFFFF; +CHECKREG r1, 0x033322D3; +CHECKREG r2, 0x155544D5; +CHECKREG r3, 0x277766D7; +CHECKREG r4, 0x277766D7; +CHECKREG r5, 0x155544D5; +CHECKREG r6, 0x033322D3; +CHECKREG r7, 0x0EEEFFFF; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_absabs.s b/tests/tcg/bfin/c_dsp32alu_absabs.s new file mode 100644 index 0000000000000..bb1cafc29c3d6 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_absabs.s @@ -0,0 +1,62 @@ +//Original:/testcases/core/c_dsp32alu_absabs/c_dsp32alu_absabs.dsp +// Spec Reference: dsp32alu dregs = abs / abs ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = ABS R0 (V); +R1 = ABS R1 (V); +R2 = ABS R2 (V); +R3 = ABS R3 (V); +R4 = ABS R4 (V); +R5 = ABS R5 (V); +R6 = ABS R6 (V); +R7 = ABS R7 (V); +CHECKREG r0, 0x156776EF; +CHECKREG r1, 0x278954E3; +CHECKREG r2, 0x34445515; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0x556776E5; +CHECKREG r5, 0x678954E3; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x799A7777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = ABS R7 (V); +R1 = ABS R6 (V); +R2 = ABS R5 (V); +R3 = ABS R4 (V); +R4 = ABS R3 (V); +R5 = ABS R2 (V); +R6 = ABS R1 (V); +R7 = ABS R0 (V); +CHECKREG r0, 0x0EEE0001; +CHECKREG r1, 0x033422D3; +CHECKREG r2, 0x155644D5; +CHECKREG r3, 0x277866D7; +CHECKREG r4, 0x277866D7; +CHECKREG r5, 0x155644D5; +CHECKREG r6, 0x033422D3; +CHECKREG r7, 0x0EEE0001; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_awx.s b/tests/tcg/bfin/c_dsp32alu_awx.s new file mode 100644 index 0000000000000..d0603ac81014b --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_awx.s @@ -0,0 +1,54 @@ +//Original:/testcases/core/c_dsp32alu_awx/c_dsp32alu_awx.dsp +// Spec Reference: dsp32alu awx +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +// A0 & A1 types +A0 = 0; +A1 = 0; + +A0.L = R0.L; +A0.H = R0.H; +A0.x = R2.L; +R3 = A0.w; +R4 = A1.w; +R5.L = A0.x; +//rl6 = a1x; +CHECKREG r3, 0x15678911; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x67890015; +//CHECKREG r6, 0x74440000; + +A0 += A1; +R0 = A0.w; +CHECKREG r0, 0x15678911; + +A0 -= A1; +R1 = A0.w; +CHECKREG r1, 0x15678911; + +R2 = A1.L + A1.H, R3 = A0.L + A0.H; /* 0x */ +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xFFFF9E78; + +A0 = A1; +R4 = A0.w; +R5 = A1.w; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_bytepack.s b/tests/tcg/bfin/c_dsp32alu_bytepack.s new file mode 100644 index 0000000000000..731a692d909c8 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_bytepack.s @@ -0,0 +1,77 @@ +//Original:/testcases/core/c_dsp32alu_bytepack/c_dsp32alu_bytepack.dsp +// Spec Reference: dsp32alu bytepack +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R4 = BYTEPACK ( R0 , R0 ); +R5 = BYTEPACK ( R0 , R1 ); +R6 = BYTEPACK ( R0 , R2 ); +R7 = BYTEPACK ( R0 , R3 ); +CHECKREG r4, 0x67116711; +CHECKREG r5, 0x891D6711; +CHECKREG r6, 0x44156711; +CHECKREG r7, 0x66176711; + +imm32 r0, 0x1567892b; +imm32 r1, 0x2789ab2d; +imm32 r2, 0x34445525; +imm32 r3, 0x46667727; +imm32 r4, 0x58889929; +imm32 r5, 0x6aaabb2b; +imm32 r6, 0x7cccdd2d; +imm32 r7, 0x8eeeffff; +R4 = BYTEPACK ( R1 , R4 ); +R5 = BYTEPACK ( R1 , R5 ); +R6 = BYTEPACK ( R1 , R6 ); +R7 = BYTEPACK ( R1 , R7 ); +CHECKREG r4, 0x8829892D; +CHECKREG r5, 0xAA2B892D; +CHECKREG r6, 0xCC2D892D; +CHECKREG r7, 0xEEFF892D; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r0, 0x456789ab; +imm32 r1, 0x6689abcd; +imm32 r2, 0x47445555; +imm32 r3, 0x68667777; +R4 = BYTEPACK ( R2 , R0 ); +R5 = BYTEPACK ( R2 , R1 ); +R6 = BYTEPACK ( R2 , R2 ); +R7 = BYTEPACK ( R2 , R3 ); +CHECKREG r4, 0x67AB4455; +CHECKREG r5, 0x89CD4455; +CHECKREG r6, 0x44554455; +CHECKREG r7, 0x66774455; + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0xaeaa4bbb; +imm32 r6, 0xcfccd44d; +imm32 r7, 0xe1eefff4; +R4 = BYTEPACK ( R3 , R4 ); +R5 = BYTEPACK ( R3 , R5 ); +R6 = BYTEPACK ( R3 , R6 ); +R7 = BYTEPACK ( R3 , R7 ); +CHECKREG r4, 0x88996477; +CHECKREG r5, 0xAABB6477; +CHECKREG r6, 0xCC4D6477; +CHECKREG r7, 0xEEF46477; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_byteunpack.s b/tests/tcg/bfin/c_dsp32alu_byteunpack.s new file mode 100644 index 0000000000000..95fa30a9c4bef --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_byteunpack.s @@ -0,0 +1,113 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteunpack/c_dsp32alu_byteunpack.dsp +// Spec Reference: dsp32alu byteunpack +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + ( R4 , R5 ) = BYTEUNPACK R1:0; + ( R1 , R3 ) = BYTEUNPACK R1:0; + ( R0 , R7 ) = BYTEUNPACK R1:0; + ( R6 , R2 ) = BYTEUNPACK R1:0; + CHECKREG r0, 0x00150067; + CHECKREG r1, 0x00150067; + CHECKREG r2, 0x00000067; + CHECKREG r3, 0x00890011; + CHECKREG r4, 0x00150067; + CHECKREG r5, 0x00890011; + CHECKREG r6, 0x00000015; + CHECKREG r7, 0x00890011; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x58889929; + imm32 r5, 0x6aaabb2b; + imm32 r6, 0x7cccdd2d; + imm32 r7, 0x8eeeffff; + ( R1 , R0 ) = BYTEUNPACK R3:2; + ( R3 , R4 ) = BYTEUNPACK R3:2; + ( R5 , R2 ) = BYTEUNPACK R3:2; + ( R7 , R6 ) = BYTEUNPACK R3:2; + CHECKREG r0, 0x00550025; + CHECKREG r1, 0x00340044; + CHECKREG r2, 0x00550025; + CHECKREG r3, 0x00340044; + CHECKREG r4, 0x00550025; + CHECKREG r5, 0x00340044; + CHECKREG r6, 0x00000025; + CHECKREG r7, 0x00000055; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r0, 0x456789ab; + imm32 r1, 0x6689abcd; + imm32 r2, 0x47445555; + imm32 r3, 0x68667777; + ( R1 , R2 ) = BYTEUNPACK R1:0 (R); + ( R3 , R6 ) = BYTEUNPACK R1:0 (R); + ( R4 , R0 ) = BYTEUNPACK R1:0 (R); + ( R5 , R7 ) = BYTEUNPACK R1:0 (R); + CHECKREG r0, 0x00000089; + CHECKREG r1, 0x00660089; + CHECKREG r2, 0x00AB00CD; + CHECKREG r3, 0x00000066; + CHECKREG r4, 0x00000066; + CHECKREG r5, 0x00000066; + CHECKREG r6, 0x00000089; + CHECKREG r7, 0x00000089; + + imm32 r0, 0x496789ab; + imm32 r1, 0x6489abcd; + imm32 r2, 0x4b445555; + imm32 r3, 0x6c647777; + imm32 r4, 0x8d889999; + imm32 r5, 0xaeaa4bbb; + imm32 r6, 0xcfccd44d; + imm32 r7, 0xe1eefff4; + ( R0 , R1 ) = BYTEUNPACK R3:2 (R); + ( R2 , R3 ) = BYTEUNPACK R3:2 (R); + ( R4 , R5 ) = BYTEUNPACK R3:2 (R); + ( R6 , R7 ) = BYTEUNPACK R3:2 (R); + CHECKREG r0, 0x006C0064; + CHECKREG r1, 0x00770077; + CHECKREG r2, 0x006C0064; + CHECKREG r3, 0x00770077; + CHECKREG r4, 0x00000077; + CHECKREG r5, 0x00000077; + CHECKREG r6, 0x00000077; + CHECKREG r7, 0x00000077; + + imm32 r0, 0x4537891b; + imm32 r1, 0x6759ab2d; + imm32 r2, 0x44555535; + imm32 r3, 0x66665747; + imm32 r4, 0x88789565; + imm32 r5, 0xaa8abb5b; + imm32 r6, 0xcc9cdd85; + imm32 r7, 0xeeaeff9f; + ( R0 , R1 ) = BYTEUNPACK R1:0; + ( R2 , R3 ) = BYTEUNPACK R3:2 (R); + ( R4 , R5 ) = BYTEUNPACK R1:0 (R); + ( R6 , R7 ) = BYTEUNPACK R3:2; + CHECKREG r0, 0x00450037; + CHECKREG r1, 0x0089001B; + CHECKREG r2, 0x00660066; + CHECKREG r3, 0x00570047; + CHECKREG r4, 0x00000089; + CHECKREG r5, 0x0000001B; + CHECKREG r6, 0x00000066; + CHECKREG r7, 0x00000066; + + pass diff --git a/tests/tcg/bfin/c_dsp32alu_disalnexcpt.s b/tests/tcg/bfin/c_dsp32alu_disalnexcpt.s new file mode 100644 index 0000000000000..ef5d916f5191b --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_disalnexcpt.s @@ -0,0 +1,255 @@ +//Original:/testcases/core/c_dsp32alu_disalnexcpt/c_dsp32alu_disalnexcpt.dsp +// Spec Reference: c_dsp32alu_disalgnexcpt +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym P0, DATA1; + P0 += 1; I0 = P0; + loadsym P0, DATA2; + P0 += 1; I1 = P0; + loadsym P0, DATA3; + P0 += 1; I2 = P0; + loadsym P0, DATA4; + P0 += 1; I3 = P0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I1 ++ ]; + DISALGNEXCPT || NOP || R2 = [ I2 ++ ]; + DISALGNEXCPT || NOP || R3 = [ I3 ++ ]; + DISALGNEXCPT || NOP || R4 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R5 = [ I1 ++ ]; + DISALGNEXCPT || NOP || R6 = [ I2 ++ ]; + DISALGNEXCPT || NOP || R7 = [ I3 ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x44454647; + CHECKREG r7, 0x64656667; + +// reverse to minus mninus i-- + DISALGNEXCPT || NOP || R0 = [ I0 -- ]; + DISALGNEXCPT || NOP || R1 = [ I1 -- ]; + DISALGNEXCPT || NOP || R2 = [ I2 -- ]; + DISALGNEXCPT || NOP || R3 = [ I3 -- ]; + DISALGNEXCPT || NOP || R4 = [ I0 -- ]; + DISALGNEXCPT || NOP || R5 = [ I1 -- ]; + DISALGNEXCPT || NOP || R6 = [ I2 -- ]; + DISALGNEXCPT || NOP || R7 = [ I3 -- ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x44454647; + CHECKREG r7, 0x64656667; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dsp32alu_max.s b/tests/tcg/bfin/c_dsp32alu_max.s new file mode 100644 index 0000000000000..74d36f97673c8 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_max.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_max/c_dsp32alu_max.dsp +// Spec Reference: dsp32alu dregs = max ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x85678911; +imm32 r1, 0x9789ab1d; +imm32 r2, 0xa4445b15; +imm32 r3, 0x46667717; +imm32 r4, 0xd567f91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = MAX ( R0 , R0 ); +R1 = MAX ( R0 , R1 ); +R2 = MAX ( R0 , R2 ); +R3 = MAX ( R0 , R3 ); +R4 = MAX ( R0 , R4 ); +R5 = MAX ( R0 , R5 ); +R6 = MAX ( R0 , R6 ); +R7 = MAX ( R0 , R7 ); +CHECKREG r0, 0x85678911; +CHECKREG r1, 0x9789AB1D; +CHECKREG r2, 0xA4445B15; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0xD567F91B; +CHECKREG r5, 0x6789AB1D; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x86667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MAX ( R1 , R0 ); +R1 = MAX ( R1 , R1 ); +R2 = MAX ( R1 , R2 ); +R3 = MAX ( R1 , R3 ); +R4 = MAX ( R1 , R4 ); +R5 = MAX ( R1 , R5 ); +R6 = MAX ( R1 , R6 ); +R7 = MAX ( R1 , R7 ); +CHECKREG r0, 0xA789AB2D; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0xD8889929; +CHECKREG r5, 0xEAAABB2B; +CHECKREG r6, 0xFCCCDD2D; +CHECKREG r7, 0x0EEEFFFF; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = MAX ( R2 , R0 ); +R1 = MAX ( R2 , R1 ); +R2 = MAX ( R2 , R2 ); +R3 = MAX ( R2 , R3 ); +R4 = MAX ( R2 , R4 ); +R5 = MAX ( R2 , R5 ); +R6 = MAX ( R2 , R6 ); +R7 = MAX ( R2 , R7 ); +CHECKREG r0, 0x43445555; +CHECKREG r1, 0x6289ABCD; +CHECKREG r2, 0x43445555; +CHECKREG r3, 0x64667777; +CHECKREG r4, 0x456789AB; +CHECKREG r5, 0x6689ABCD; +CHECKREG r6, 0x47445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MAX ( R3 , R0 ); +R1 = MAX ( R3 , R1 ); +R2 = MAX ( R3 , R2 ); +R3 = MAX ( R3 , R3 ); +R4 = MAX ( R3 , R4 ); +R5 = MAX ( R3 , R5 ); +R6 = MAX ( R3 , R6 ); +R7 = MAX ( R3 , R7 ); +CHECKREG r0, 0xC6667727; +CHECKREG r1, 0xC6667727; +CHECKREG r2, 0xC6667727; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0x456789AB; +CHECKREG r5, 0x6689ABCD; +CHECKREG r6, 0x47445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x5537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x74555535; +imm32 r3, 0x86665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MAX ( R4 , R0 ); +R1 = MAX ( R4 , R1 ); +R2 = MAX ( R4 , R2 ); +R3 = MAX ( R4 , R3 ); +R4 = MAX ( R4 , R4 ); +R5 = MAX ( R4 , R5 ); +R6 = MAX ( R4 , R6 ); +R7 = MAX ( R4 , R7 ); +CHECKREG r0, 0x5537891B; +CHECKREG r1, 0x6759AB2D; +CHECKREG r2, 0x74555535; +CHECKREG r3, 0x88789565; +CHECKREG r4, 0x88789565; +CHECKREG r5, 0xAA8ABB5B; +CHECKREG r6, 0xCC9CDD85; +CHECKREG r7, 0xEEAEFF9F; + +imm32 r0, 0x556b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x79736564; +imm32 r3, 0x81278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = MAX ( R5 , R0 ); +R1 = MAX ( R5 , R1 ); +R2 = MAX ( R5 , R2 ); +R3 = MAX ( R5 , R3 ); +R4 = MAX ( R5 , R4 ); +R5 = MAX ( R5 , R5 ); +R6 = MAX ( R5 , R6 ); +R7 = MAX ( R5 , R7 ); +CHECKREG r0, 0x556B89AB; +CHECKREG r1, 0x69764BCD; +CHECKREG r2, 0x79736564; +CHECKREG r3, 0xAAAA0BBB; +CHECKREG r4, 0xAAAA0BBB; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xCCCC1DDD; +CHECKREG r7, 0x12346FFF; + +imm32 r0, 0xe56739ab; +imm32 r1, 0xf7694bcd; +imm32 r2, 0xa3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x42345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MAX ( R6 , R0 ); +R1 = MAX ( R6 , R1 ); +R2 = MAX ( R6 , R2 ); +R3 = MAX ( R6 , R3 ); +R4 = MAX ( R6 , R4 ); +R5 = MAX ( R6 , R5 ); +R6 = MAX ( R6 , R6 ); +R7 = MAX ( R6 , R7 ); +CHECKREG r0, 0x043290D6; +CHECKREG r1, 0x043290D6; +CHECKREG r2, 0x043290D6; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x42345699; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0x576789ab; +imm32 r1, 0xd779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xf9ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MAX ( R7 , R0 ); +R1 = MAX ( R7 , R1 ); +R2 = MAX ( R7 , R2 ); +R3 = MAX ( R7 , R3 ); +R4 = MAX ( R7 , R4 ); +R5 = MAX ( R7 , R5 ); +R6 = MAX ( R7 , R6 ); +R7 = MAX ( R7 , R7 ); +CHECKREG r0, 0x576789AB; +CHECKREG r1, 0xD779ABCD; +CHECKREG r2, 0x23456755; +CHECKREG r3, 0x56789007; +CHECKREG r4, 0x789AB799; +CHECKREG r5, 0xABCD2FF7; +CHECKREG r6, 0xF9AB1D7D; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0xe56739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = MAX ( R4 , R7 ); +R5 = MAX ( R5 , R5 ); +R2 = MAX ( R6 , R3 ); +R6 = MAX ( R0 , R4 ); +R0 = MAX ( R1 , R6 ); +R2 = MAX ( R2 , R1 ); +R1 = MAX ( R3 , R0 ); +R7 = MAX ( R7 , R4 ); +CHECKREG r0, 0x67694BCD; +CHECKREG r1, 0x67694BCD; +CHECKREG r2, 0x67694BCD; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x12345699; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x12345699; +CHECKREG r7, 0x12345699; + +imm32 r0, 0xd76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xe3456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MAX ( R4 , R0 ); +R5 = MAX ( R5 , R1 ); +R2 = MAX ( R2 , R2 ); +R7 = MAX ( R7 , R3 ); +R4 = MAX ( R3 , R4 ); +R0 = MAX ( R1 , R5 ); +R1 = MAX ( R0 , R6 ); +R6 = MAX ( R6 , R7 ); +CHECKREG r0, 0x6779ABCD; +CHECKREG r1, 0x6779ABCD; +CHECKREG r2, 0xE3456755; +CHECKREG r3, 0x789AB799; +CHECKREG r4, 0x789AB799; +CHECKREG r5, 0x6779ABCD; +CHECKREG r6, 0x789AB799; +CHECKREG r7, 0x789AB799; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_maxmax.s b/tests/tcg/bfin/c_dsp32alu_maxmax.s new file mode 100644 index 0000000000000..8e39d22a8f447 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_maxmax.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_maxmax/c_dsp32alu_maxmax.dsp +// Spec Reference: dsp32alu dregs = max / max ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x25678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0xe6657717; +imm32 r4, 0x5a67891b; +imm32 r5, 0x67b9ab1d; +imm32 r6, 0x744d5515; +imm32 r7, 0x8666c777; +R0 = MAX ( R0 , R0 ) (V); +R1 = MAX ( R0 , R1 ) (V); +R2 = MAX ( R0 , R2 ) (V); +R3 = MAX ( R0 , R3 ) (V); +R4 = MAX ( R0 , R4 ) (V); +R5 = MAX ( R0 , R5 ) (V); +R6 = MAX ( R0 , R6 ) (V); +R7 = MAX ( R0 , R7 ) (V); +CHECKREG r0, 0x25678911; +CHECKREG r1, 0x2567AB1D; +CHECKREG r2, 0x34445515; +CHECKREG r3, 0x25677717; +CHECKREG r4, 0x5A67891B; +CHECKREG r5, 0x67B9AB1D; +CHECKREG r6, 0x744D5515; +CHECKREG r7, 0x2567C777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MAX ( R1 , R0 ) (V); +R1 = MAX ( R1 , R1 ) (V); +R2 = MAX ( R1 , R2 ) (V); +R3 = MAX ( R1 , R3 ) (V); +R4 = MAX ( R1 , R4 ) (V); +R5 = MAX ( R1 , R5 ) (V); +R6 = MAX ( R1 , R6 ) (V); +R7 = MAX ( R1 , R7 ) (V); +CHECKREG r0, 0xA789AB2D; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0xD888AB2D; +CHECKREG r5, 0xEAAABB2B; +CHECKREG r6, 0xFCCCDD2D; +CHECKREG r7, 0x0EEEFFFF; + +imm32 r0, 0x416789ab; +imm32 r1, 0x5289abcd; +imm32 r2, 0x63445555; +imm32 r3, 0xa7669777; +imm32 r4, 0x456789ab; +imm32 r5, 0xb689abcd; +imm32 r6, 0xd7445555; +imm32 r7, 0x68667777; +R0 = MAX ( R2 , R0 ) (V); +R1 = MAX ( R2 , R1 ) (V); +R2 = MAX ( R2 , R2 ) (V); +R3 = MAX ( R2 , R3 ) (V); +R4 = MAX ( R2 , R4 ) (V); +R5 = MAX ( R2 , R5 ) (V); +R6 = MAX ( R2 , R6 ) (V); +R7 = MAX ( R2 , R7 ) (V); +CHECKREG r0, 0x63445555; +CHECKREG r1, 0x63445555; +CHECKREG r2, 0x63445555; +CHECKREG r3, 0x63445555; +CHECKREG r4, 0x63445555; +CHECKREG r5, 0x63445555; +CHECKREG r6, 0x63445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MAX ( R3 , R0 ) (V); +R1 = MAX ( R3 , R1 ) (V); +R2 = MAX ( R3 , R2 ) (V); +R3 = MAX ( R3 , R3 ) (V); +R4 = MAX ( R3 , R4 ) (V); +R5 = MAX ( R3 , R5 ) (V); +R6 = MAX ( R3 , R6 ) (V); +R7 = MAX ( R3 , R7 ) (V); +CHECKREG r0, 0xC6667727; +CHECKREG r1, 0xC6667727; +CHECKREG r2, 0xC6667727; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0x63447727; +CHECKREG r5, 0x63447727; +CHECKREG r6, 0x63447727; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MAX ( R4 , R0 ) (V); +R1 = MAX ( R4 , R1 ) (V); +R2 = MAX ( R4 , R2 ) (V); +R3 = MAX ( R4 , R3 ) (V); +R4 = MAX ( R4 , R4 ) (V); +R5 = MAX ( R4 , R5 ) (V); +R6 = MAX ( R4 , R6 ) (V); +R7 = MAX ( R4 , R7 ) (V); +CHECKREG r0, 0x45379565; +CHECKREG r1, 0x6759AB2D; +CHECKREG r2, 0x44555535; +CHECKREG r3, 0x66665747; +CHECKREG r4, 0x88789565; +CHECKREG r5, 0xAA8ABB5B; +CHECKREG r6, 0xCC9CDD85; +CHECKREG r7, 0xEEAEFF9F; + +imm32 r0, 0xa56b89ab; +imm32 r1, 0x659b4bcd; +imm32 r2, 0xd9736564; +imm32 r3, 0x61278394; +imm32 r4, 0xb8876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = MAX ( R5 , R0 ) (V); +R1 = MAX ( R5 , R1 ) (V); +R2 = MAX ( R5 , R2 ) (V); +R3 = MAX ( R5 , R3 ) (V); +R4 = MAX ( R5 , R4 ) (V); +R5 = MAX ( R5 , R5 ) (V); +R6 = MAX ( R5 , R6 ) (V); +R7 = MAX ( R5 , R7 ) (V); +CHECKREG r0, 0xAAAA0BBB; +CHECKREG r1, 0x659B4BCD; +CHECKREG r2, 0xD9736564; +CHECKREG r3, 0x61270BBB; +CHECKREG r4, 0xB8876439; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xCCCC1DDD; +CHECKREG r7, 0x12346FFF; + +imm32 r0, 0x956739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MAX ( R6 , R0 ) (V); +R1 = MAX ( R6 , R1 ) (V); +R2 = MAX ( R6 , R2 ) (V); +R3 = MAX ( R6 , R3 ) (V); +R4 = MAX ( R6 , R4 ) (V); +R5 = MAX ( R6 , R5 ) (V); +R6 = MAX ( R6 , R6 ) (V); +R7 = MAX ( R6 , R7 ) (V); +CHECKREG r0, 0x043239AB; +CHECKREG r1, 0x67694BCD; +CHECKREG r2, 0x04326755; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x12345699; +CHECKREG r5, 0x456790D6; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0x876789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MAX ( R7 , R0 ) (V); +R1 = MAX ( R7 , R1 ) (V); +R2 = MAX ( R7 , R2 ) (V); +R3 = MAX ( R7 , R3 ) (V); +R4 = MAX ( R7 , R4 ) (V); +R5 = MAX ( R7 , R5 ) (V); +R6 = MAX ( R7 , R6 ) (V); +R7 = MAX ( R7 , R7 ) (V); +CHECKREG r0, 0xABCD2FF7; +CHECKREG r1, 0x67792FF7; +CHECKREG r2, 0xD3456755; +CHECKREG r3, 0x56782FF7; +CHECKREG r4, 0x789A2FF7; +CHECKREG r5, 0xABCD2FF7; +CHECKREG r6, 0xABCD2FF7; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = MAX ( R4 , R7 ) (V); +R5 = MAX ( R5 , R5 ) (V); +R2 = MAX ( R6 , R3 ) (V); +R6 = MAX ( R0 , R4 ) (V); +R0 = MAX ( R1 , R6 ) (V); +R2 = MAX ( R2 , R1 ) (V); +R1 = MAX ( R3 , R0 ) (V); +R7 = MAX ( R7 , R4 ) (V); +CHECKREG r0, 0x67695699; +CHECKREG r1, 0x67696777; +CHECKREG r2, 0x67696777; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x12345699; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x45675699; +CHECKREG r7, 0x12345699; + +imm32 r0, 0x876789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x2345d755; +imm32 r3, 0x5678b007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MAX ( R4 , R0 ) (V); +R5 = MAX ( R5 , R1 ) (V); +R2 = MAX ( R2 , R2 ) (V); +R7 = MAX ( R7 , R3 ) (V); +R4 = MAX ( R3 , R4 ) (V); +R0 = MAX ( R1 , R5 ) (V); +R1 = MAX ( R0 , R6 ) (V); +R6 = MAX ( R6 , R7 ) (V); +CHECKREG r0, 0x67790BBB; +CHECKREG r1, 0x67791D7D; +CHECKREG r2, 0x2345D755; +CHECKREG r3, 0x789AB799; +CHECKREG r4, 0x789AB799; +CHECKREG r5, 0x67790BBB; +CHECKREG r6, 0x789A2FF7; +CHECKREG r7, 0x789A2FF7; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_min.s b/tests/tcg/bfin/c_dsp32alu_min.s new file mode 100644 index 0000000000000..b36eaac84e29d --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_min.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_min/c_dsp32alu_min.dsp +// Spec Reference: dsp32alu dregs = min ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x35678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0xf6667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = MIN ( R0 , R0 ); +R1 = MIN ( R0 , R1 ); +R2 = MIN ( R0 , R2 ); +R3 = MIN ( R0 , R3 ); +R4 = MIN ( R0 , R4 ); +R5 = MIN ( R0 , R5 ); +R6 = MIN ( R0 , R6 ); +R7 = MIN ( R0 , R7 ); +CHECKREG r0, 0x35678911; +CHECKREG r1, 0x2789AB1D; +CHECKREG r2, 0x35678911; +CHECKREG r3, 0xF6667717; +CHECKREG r4, 0x35678911; +CHECKREG r5, 0x35678911; +CHECKREG r6, 0x35678911; +CHECKREG r7, 0x86667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MIN ( R1 , R0 ); +R1 = MIN ( R1 , R1 ); +R2 = MIN ( R1 , R2 ); +R3 = MIN ( R1 , R3 ); +R4 = MIN ( R1 , R4 ); +R5 = MIN ( R1 , R5 ); +R6 = MIN ( R1 , R6 ); +R7 = MIN ( R1 , R7 ); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xA789AB2D; +CHECKREG r3, 0xA789AB2D; +CHECKREG r4, 0xA789AB2D; +CHECKREG r5, 0xA789AB2D; +CHECKREG r6, 0xA789AB2D; +CHECKREG r7, 0xA789AB2D; + +imm32 r0, 0x716789ab; +imm32 r1, 0x8289abcd; +imm32 r2, 0x93445555; +imm32 r3, 0xa4667777; +imm32 r4, 0x456789ab; +imm32 r5, 0xb689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = MIN ( R2 , R0 ); +R1 = MIN ( R2 , R1 ); +R2 = MIN ( R2 , R2 ); +R3 = MIN ( R2 , R3 ); +R4 = MIN ( R2 , R4 ); +R5 = MIN ( R2 , R5 ); +R6 = MIN ( R2 , R6 ); +R7 = MIN ( R2 , R7 ); +CHECKREG r0, 0x93445555; +CHECKREG r1, 0x8289ABCD; +CHECKREG r2, 0x93445555; +CHECKREG r3, 0x93445555; +CHECKREG r4, 0x93445555; +CHECKREG r5, 0x93445555; +CHECKREG r6, 0x93445555; +CHECKREG r7, 0x93445555; + +imm32 r0, 0x2567892b; +imm32 r1, 0x5789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MIN ( R3 , R0 ); +R1 = MIN ( R3 , R1 ); +R2 = MIN ( R3 , R2 ); +R3 = MIN ( R3 , R3 ); +R4 = MIN ( R3 , R4 ); +R5 = MIN ( R3 , R5 ); +R6 = MIN ( R3 , R6 ); +R7 = MIN ( R3 , R7 ); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0x93445555; +CHECKREG r5, 0x93445555; +CHECKREG r6, 0x93445555; +CHECKREG r7, 0x93445555; + +imm32 r0, 0xd537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0xf455b535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MIN ( R4 , R0 ); +R1 = MIN ( R4 , R1 ); +R2 = MIN ( R4 , R2 ); +R3 = MIN ( R4 , R3 ); +R4 = MIN ( R4 , R4 ); +R5 = MIN ( R4 , R5 ); +R6 = MIN ( R4 , R6 ); +R7 = MIN ( R4 , R7 ); +CHECKREG r0, 0x88789565; +CHECKREG r1, 0x88789565; +CHECKREG r2, 0x88789565; +CHECKREG r3, 0x88789565; +CHECKREG r4, 0x88789565; +CHECKREG r5, 0x88789565; +CHECKREG r6, 0x88789565; +CHECKREG r7, 0x88789565; + +imm32 r0, 0xa56b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = MIN ( R5 , R0 ); +R1 = MIN ( R5 , R1 ); +R2 = MIN ( R5 , R2 ); +R3 = MIN ( R5 , R3 ); +R4 = MIN ( R5 , R4 ); +R5 = MIN ( R5 , R5 ); +R6 = MIN ( R5 , R6 ); +R7 = MIN ( R5 , R7 ); +CHECKREG r0, 0xA56B89AB; +CHECKREG r1, 0xAAAA0BBB; +CHECKREG r2, 0xAAAA0BBB; +CHECKREG r3, 0xAAAA0BBB; +CHECKREG r4, 0x98876439; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xAAAA0BBB; +CHECKREG r7, 0xAAAA0BBB; + +imm32 r0, 0xe56739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0xd2345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MIN ( R6 , R0 ); +R1 = MIN ( R6 , R1 ); +R2 = MIN ( R6 , R2 ); +R3 = MIN ( R6 , R3 ); +R4 = MIN ( R6 , R4 ); +R5 = MIN ( R6 , R5 ); +R6 = MIN ( R6 , R6 ); +R7 = MIN ( R6 , R7 ); +CHECKREG r0, 0xE56739AB; +CHECKREG r1, 0x043290D6; +CHECKREG r2, 0x03456755; +CHECKREG r3, 0x043290D6; +CHECKREG r4, 0xD2345699; +CHECKREG r5, 0x043290D6; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x043290D6; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MIN ( R7 , R0 ); +R1 = MIN ( R7 , R1 ); +R2 = MIN ( R7 , R2 ); +R3 = MIN ( R7 , R3 ); +R4 = MIN ( R7 , R4 ); +R5 = MIN ( R7 , R5 ); +R6 = MIN ( R7 , R6 ); +R7 = MIN ( R7 , R7 ); +CHECKREG r0, 0xABCD2FF7; +CHECKREG r1, 0xABCD2FF7; +CHECKREG r2, 0xABCD2FF7; +CHECKREG r3, 0xABCD2FF7; +CHECKREG r4, 0xABCD2FF7; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0x89AB1D7D; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0xb43290d6; +imm32 r7, 0x1234567f; +R4 = MIN ( R4 , R7 ); +R5 = MIN ( R5 , R5 ); +R2 = MIN ( R6 , R3 ); +R6 = MIN ( R0 , R4 ); +R0 = MIN ( R1 , R6 ); +R2 = MIN ( R2 , R1 ); +R1 = MIN ( R3 , R0 ); +R7 = MIN ( R7 , R4 ); +CHECKREG r0, 0x1234567F; +CHECKREG r1, 0x1234567F; +CHECKREG r2, 0xB43290D6; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x1234567F; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x1234567F; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0xa76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xf3456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MIN ( R4 , R0 ); +R5 = MIN ( R5 , R1 ); +R2 = MIN ( R2 , R2 ); +R7 = MIN ( R7 , R3 ); +R4 = MIN ( R3 , R4 ); +R0 = MIN ( R1 , R5 ); +R1 = MIN ( R0 , R6 ); +R6 = MIN ( R6 , R7 ); +CHECKREG r0, 0xAAAA0BBB; +CHECKREG r1, 0x89AB1D7D; +CHECKREG r2, 0xF3456755; +CHECKREG r3, 0xA76789AB; +CHECKREG r4, 0xA76789AB; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0x89AB1D7D; +CHECKREG r7, 0xA76789AB; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_minmin.s b/tests/tcg/bfin/c_dsp32alu_minmin.s new file mode 100644 index 0000000000000..4106245bddc39 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_minmin.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_minmin/c_dsp32alu_minmin.dsp +// Spec Reference: dsp32alu dregs = min / min ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x25678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x2a445345; +imm32 r3, 0x46657717; +imm32 r4, 0xd567e91b; +imm32 r5, 0x6789af1d; +imm32 r6, 0x74445d85; +imm32 r7, 0x8666a779; +R0 = MIN ( R0 , R0 ) (V); +R1 = MIN ( R0 , R1 ) (V); +R2 = MIN ( R0 , R2 ) (V); +R3 = MIN ( R0 , R3 ) (V); +R4 = MIN ( R0 , R4 ) (V); +R5 = MIN ( R0 , R5 ) (V); +R6 = MIN ( R0 , R6 ) (V); +R7 = MIN ( R0 , R7 ) (V); +CHECKREG r0, 0x25678911; +CHECKREG r1, 0x23898911; +CHECKREG r2, 0x25678911; +CHECKREG r3, 0x25678911; +CHECKREG r4, 0xD5678911; +CHECKREG r5, 0x25678911; +CHECKREG r6, 0x25678911; +CHECKREG r7, 0x86668911; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MIN ( R1 , R0 ) (V); +R1 = MIN ( R1 , R1 ) (V); +R2 = MIN ( R1 , R2 ) (V); +R3 = MIN ( R1 , R3 ) (V); +R4 = MIN ( R1 , R4 ) (V); +R5 = MIN ( R1 , R5 ) (V); +R6 = MIN ( R1 , R6 ) (V); +R7 = MIN ( R1 , R7 ) (V); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xA789AB2D; +CHECKREG r3, 0xA789AB2D; +CHECKREG r4, 0xA7899929; +CHECKREG r5, 0xA789AB2D; +CHECKREG r6, 0xA789AB2D; +CHECKREG r7, 0xA789AB2D; + +imm32 r0, 0x416789ab; +imm32 r1, 0x5289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0xa466a777; +imm32 r4, 0x45678dab; +imm32 r5, 0xf689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = MIN ( R2 , R0 ) (V); +R1 = MIN ( R2 , R1 ) (V); +R2 = MIN ( R2 , R2 ) (V); +R3 = MIN ( R2 , R3 ) (V); +R4 = MIN ( R2 , R4 ) (V); +R5 = MIN ( R2 , R5 ) (V); +R6 = MIN ( R2 , R6 ) (V); +R7 = MIN ( R2 , R7 ) (V); +CHECKREG r0, 0x416789AB; +CHECKREG r1, 0x4344ABCD; +CHECKREG r2, 0x43445555; +CHECKREG r3, 0xA466A777; +CHECKREG r4, 0x43448DAB; +CHECKREG r5, 0xF689ABCD; +CHECKREG r6, 0x43445555; +CHECKREG r7, 0x43445555; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MIN ( R3 , R0 ) (V); +R1 = MIN ( R3 , R1 ) (V); +R2 = MIN ( R3 , R2 ) (V); +R3 = MIN ( R3 , R3 ) (V); +R4 = MIN ( R3 , R4 ) (V); +R5 = MIN ( R3 , R5 ) (V); +R6 = MIN ( R3 , R6 ) (V); +R7 = MIN ( R3 , R7 ) (V); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0xC6668DAB; +CHECKREG r5, 0xC666ABCD; +CHECKREG r6, 0xC6665555; +CHECKREG r7, 0xC6665555; + +imm32 r0, 0x5537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x74555535; +imm32 r3, 0x86665747; +imm32 r4, 0x98789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MIN ( R4 , R0 ) (V); +R1 = MIN ( R4 , R1 ) (V); +R2 = MIN ( R4 , R2 ) (V); +R3 = MIN ( R4 , R3 ) (V); +R4 = MIN ( R4 , R4 ) (V); +R5 = MIN ( R4 , R5 ) (V); +R6 = MIN ( R4 , R6 ) (V); +R7 = MIN ( R4 , R7 ) (V); +CHECKREG r0, 0x9878891B; +CHECKREG r1, 0x98789565; +CHECKREG r2, 0x98789565; +CHECKREG r3, 0x86669565; +CHECKREG r4, 0x98789565; +CHECKREG r5, 0x98789565; +CHECKREG r6, 0x98789565; +CHECKREG r7, 0x98789565; + +imm32 r0, 0x256b89ab; +imm32 r1, 0x64764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x43346fff; +R0 = MIN ( R5 , R0 ) (V); +R1 = MIN ( R5 , R1 ) (V); +R2 = MIN ( R5 , R2 ) (V); +R3 = MIN ( R5 , R3 ) (V); +R4 = MIN ( R5 , R4 ) (V); +R5 = MIN ( R5 , R5 ) (V); +R6 = MIN ( R5 , R6 ) (V); +R7 = MIN ( R5 , R7 ) (V); +CHECKREG r0, 0xAAAA89AB; +CHECKREG r1, 0xAAAA0BBB; +CHECKREG r2, 0xAAAA0BBB; +CHECKREG r3, 0xAAAA8394; +CHECKREG r4, 0x98870BBB; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xAAAA0BBB; +CHECKREG r7, 0xAAAA0BBB; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MIN ( R6 , R0 ) (V); +R1 = MIN ( R6 , R1 ) (V); +R2 = MIN ( R6 , R2 ) (V); +R3 = MIN ( R6 , R3 ) (V); +R4 = MIN ( R6 , R4 ) (V); +R5 = MIN ( R6 , R5 ) (V); +R6 = MIN ( R6 , R6 ) (V); +R7 = MIN ( R6 , R7 ) (V); +CHECKREG r0, 0x043290D6; +CHECKREG r1, 0x043290D6; +CHECKREG r2, 0x034590D6; +CHECKREG r3, 0x043290D6; +CHECKREG r4, 0x043290D6; +CHECKREG r5, 0x04328B6B; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x043290D6; + +imm32 r0, 0x976789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x8345a755; +imm32 r3, 0x5678b007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MIN ( R7 , R0 ) (V); +R1 = MIN ( R7 , R1 ) (V); +R2 = MIN ( R7 , R2 ) (V); +R3 = MIN ( R7 , R3 ) (V); +R4 = MIN ( R7 , R4 ) (V); +R5 = MIN ( R7 , R5 ) (V); +R6 = MIN ( R7 , R6 ) (V); +R7 = MIN ( R7 , R7 ) (V); +CHECKREG r0, 0x976789AB; +CHECKREG r1, 0xABCDABCD; +CHECKREG r2, 0x8345A755; +CHECKREG r3, 0xABCDB007; +CHECKREG r4, 0xABCDB799; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0x89AB1D7D; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = MIN ( R4 , R7 ) (V); +R5 = MIN ( R5 , R5 ) (V); +R2 = MIN ( R6 , R3 ) (V); +R6 = MIN ( R0 , R4 ) (V); +R0 = MIN ( R1 , R6 ) (V); +R2 = MIN ( R2 , R1 ) (V); +R1 = MIN ( R3 , R0 ) (V); +R7 = MIN ( R7 , R4 ) (V); +CHECKREG r0, 0x123439AB; +CHECKREG r1, 0x123439AB; +CHECKREG r2, 0x043290D6; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x1234567F; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x123439AB; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0xa76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xb3456755; +imm32 r3, 0x5678d007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MIN ( R4 , R0 ) (V); +R5 = MIN ( R5 , R1 ) (V); +R2 = MIN ( R2 , R2 ) (V); +R7 = MIN ( R7 , R3 ) (V); +R4 = MIN ( R3 , R4 ) (V); +R0 = MIN ( R1 , R5 ) (V); +R1 = MIN ( R0 , R6 ) (V); +R6 = MIN ( R6 , R7 ) (V); +CHECKREG r0, 0xAAAAABCD; +CHECKREG r1, 0x89ABABCD; +CHECKREG r2, 0xB3456755; +CHECKREG r3, 0xA76789AB; +CHECKREG r4, 0xA76789AB; +CHECKREG r5, 0xAAAAABCD; +CHECKREG r6, 0x89AB89AB; +CHECKREG r7, 0xA76789AB; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_rr_lph_a1a0.s b/tests/tcg/bfin/c_dsp32alu_rr_lph_a1a0.s new file mode 100644 index 0000000000000..5ce3598f7ba92 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_rr_lph_a1a0.s @@ -0,0 +1,33 @@ +//Original:/testcases/core/c_dsp32alu_rr_lph_a1a0/c_dsp32alu_rr_lph_a1a0.dsp +// Spec Reference: dsp32alu (dregs, dregs) = L + H, L + H (a1, a0) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x25678911; +imm32 r1, 0x0029ab2d; +imm32 r2, 0x00145535; +imm32 r3, 0xf6567747; +imm32 r4, 0xe566895b; +imm32 r5, 0x67897b6d; +imm32 r6, 0xb4445875; +imm32 r7, 0x86667797; +A1 = R1; +A0 = R0; + +R2 = A1.L + A1.H, R3 = A0.L + A0.H; +R4 = A1.L + A1.H, R5 = A0.L + A0.H; +R6 = A1.L + A1.H, R7 = A0.L + A0.H; +CHECKREG r2, 0xFFFFAB56; +CHECKREG r3, 0xFFFFAE78; +CHECKREG r4, 0xFFFFAB56; +CHECKREG r5, 0xFFFFAE78; +CHECKREG r6, 0xFFFFAB56; +CHECKREG r7, 0xFFFFAE78; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_search.s b/tests/tcg/bfin/c_dsp32alu_search.s new file mode 100644 index 0000000000000..68b3d324c97a5 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_search.s @@ -0,0 +1,74 @@ +//Original:/testcases/core/c_dsp32alu_search/c_dsp32alu_search.dsp +// Spec Reference: dsp32alu search +# mach: bfin + +.include "testutils.inc" + start + +imm32 p0, 0x11234556; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +( R0 , R1 ) = SEARCH R2 (GE); +( R2 , R3 ) = SEARCH R4 (GT); +( R4 , R5 ) = SEARCH R0 (LE); +( R7 , R6 ) = SEARCH R1 (LT); +CHECKREG r0, 0x11234556; +CHECKREG r1, 0x11234556; +CHECKREG r2, 0x11234556; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0x11234556; +CHECKREG r5, 0x11234556; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x86667777; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r0, 0x456789ab; +imm32 r1, 0x6689abcd; +imm32 r2, 0x47445555; +imm32 r3, 0x68667777; +( R2 , R1 ) = SEARCH R3 (LE); +( R6 , R3 ) = SEARCH R5 (GT); +( R4 , R7 ) = SEARCH R2 (GE); +( R0 , R5 ) = SEARCH R4 (LT); +CHECKREG r0, 0x11234556; +CHECKREG r1, 0x6689ABCD; +CHECKREG r2, 0x47445555; +CHECKREG r3, 0x68667777; +CHECKREG r4, 0x11234556; +CHECKREG r5, 0x11234556; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x11234556; + +imm32 r0, 0x516789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x73445555; +imm32 r3, 0x84667777; +imm32 r0, 0x956789ab; +imm32 r1, 0xa689abcd; +imm32 r2, 0xb7445555; +imm32 r3, 0xc86def77; +( R3 , R4 ) = SEARCH R5 (GT); +( R0 , R7 ) = SEARCH R6 (GE); +( R6 , R1 ) = SEARCH R2 (LT); +( R2 , R5 ) = SEARCH R4 (LE); +CHECKREG r0, 0x11234556; +CHECKREG r1, 0xA689ABCD; +CHECKREG r2, 0xB7445555; +CHECKREG r3, 0xC86DEF77; +CHECKREG r4, 0x11234556; +CHECKREG r5, 0x11234556; +CHECKREG r6, 0x11234556; +CHECKREG r7, 0x11234556; + + +pass diff --git a/tests/tcg/bfin/c_dsp32alu_sgn.s b/tests/tcg/bfin/c_dsp32alu_sgn.s new file mode 100644 index 0000000000000..de36c20217c15 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32alu_sgn.s @@ -0,0 +1,39 @@ +//Original:/testcases/core/c_dsp32alu_sgn/c_dsp32alu_sgn.dsp +// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x456789ab; +imm32 r1, 0x6689abcd; +imm32 r2, 0x47445555; +imm32 r3, 0x68667777; +R4.H = R4.L = SIGN(R2.H) * R0.H + SIGN(R2.L) * R0.L; +R5.H = R5.L = SIGN(R2.H) * R1.H + SIGN(R2.L) * R1.L; +R6.H = R6.L = SIGN(R2.H) * R2.H + SIGN(R2.L) * R2.L; +R7.H = R7.L = SIGN(R2.H) * R3.H + SIGN(R2.L) * R3.L; +CHECKREG r4, 0xCF12CF12; +CHECKREG r5, 0x12561256; +CHECKREG r6, 0x9C999C99; +CHECKREG r7, 0xDFDDDFDD; + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0xaeaa4bbb; +imm32 r6, 0xcfccd44d; +imm32 r7, 0xe1eefff4; +R0.H = R0.L = SIGN(R3.H) * R4.H + SIGN(R3.L) * R4.L; +R1.H = R1.L = SIGN(R3.H) * R5.H + SIGN(R3.L) * R5.L; +R2.H = R2.L = SIGN(R3.H) * R6.H + SIGN(R3.L) * R6.L; +R3.H = R3.L = SIGN(R3.H) * R7.H + SIGN(R3.L) * R7.L; +CHECKREG r0, 0x27212721; +CHECKREG r1, 0xFA65FA65; +CHECKREG r2, 0xA419A419; +CHECKREG r3, 0xE1E2E1E2; + + +pass diff --git a/tests/tcg/bfin/c_dsp32mac_a1a0.s b/tests/tcg/bfin/c_dsp32mac_a1a0.s new file mode 100644 index 0000000000000..25c2a2d4eac18 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32mac_a1a0.s @@ -0,0 +1,255 @@ +//Original:/testcases/core/c_dsp32mac_a1a0/c_dsp32mac_a1a0.dsp +// Spec Reference: dsp32mac a1 a0 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 r0, 0x00000000; +A0 = 0; +A1 = 0; +ASTAT = r0; + + +// test the default (signed fraction : left ) +imm32 r0, 0x12345678; +imm32 r1, 0x33456789; +imm32 r2, 0x5556789a; +imm32 r3, 0x75678912; +imm32 r4, 0x86789123; +imm32 r5, 0xa7891234; +imm32 r6, 0xc1234567; +imm32 r7, 0xf1234567; +A1 = R0.L * R1.L, A0 = R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.L, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 += R4.L * R5.L, A0 = R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.L * R7.L, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x45F11C70; +CHECKREG r1, 0x45F11C70; +CHECKREG r2, 0xB48EEC5C; +CHECKREG r3, 0x8FF1C9A8; +CHECKREG r4, 0xEEB780C0; +CHECKREG r5, 0x802DABE0; +CHECKREG r6, 0xF6043652; +CHECKREG r7, 0xA5CF0AC2; + +imm32 r0, 0x12245618; +imm32 r1, 0x23256719; +imm32 r2, 0x3426781a; +imm32 r3, 0x45278912; +imm32 r4, 0x56289113; +imm32 r5, 0x67291214; +imm32 r6, 0xa1234517; +imm32 r7, 0xc1234517; +A1 = R0.L * R1.H, A0 += R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.H, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 = R4.L * R5.H, A0 += R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 = R6.L * R7.H, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x3B5C5702; +CHECKREG r1, 0x17A372F0; +CHECKREG r2, 0x7C3EF2EE; +CHECKREG r3, 0x40E29BEC; +CHECKREG r4, 0x886A092E; +CHECKREG r5, 0xA699C216; +CHECKREG r6, 0xB700DEC0; +CHECKREG r7, 0xDE11924A; + +imm32 r0, 0x15245648; +imm32 r1, 0x25256749; +imm32 r2, 0x3526784a; +imm32 r3, 0x45278942; +imm32 r4, 0x55389143; +imm32 r5, 0x65391244; +imm32 r6, 0xa5334547; +imm32 r7, 0xc5334547; +A1 += R0.H * R1.H, A0 = R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 += R2.H * R3.H, A0 = R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 += R4.H * R5.H, A0 = R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.H * R7.H, A0 = R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x459F2510; +CHECKREG r1, 0xE43416B2; +CHECKREG r2, 0x40FC8A8C; +CHECKREG r3, 0x00EAC446; +CHECKREG r4, 0x0C2925C0; +CHECKREG r5, 0x444EE736; +CHECKREG r6, 0x29B65052; +CHECKREG r7, 0x6E053788; + + +imm32 r0, 0x13245628; +imm32 r1, 0x23256729; +imm32 r2, 0x3326782a; +imm32 r3, 0x43278922; +imm32 r4, 0x56389123; +imm32 r5, 0x67391224; +imm32 r6, 0xa1334527; +imm32 r7, 0xc1334527; +A1 += R0.H * R1.L, A0 += R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.H * R3.L, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 = R4.H * R5.L, A0 += R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 = R6.H * R7.L, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x6F261922; +CHECKREG r1, 0x7D725110; +CHECKREG r2, 0xAE30B1EE; +CHECKREG r3, 0xD0804218; +CHECKREG r4, 0xBA68D1AE; +CHECKREG r5, 0x0C381FC0; +CHECKREG r6, 0xE8EBF200; +CHECKREG r7, 0xCCC89B8A; + + +imm32 r0, 0x01340678; +imm32 r1, 0x02450789; +imm32 r2, 0x0356089a; +imm32 r3, 0x04670912; +imm32 r4, 0x05780123; +imm32 r5, 0x06890234; +imm32 r6, 0x07230567; +imm32 r7, 0x00230567; +A1 -= R0.L * R1.L, A0 = R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.L, A0 -= R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.L * R5.L, A0 -= R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 -= R6.L * R7.L, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x00617C70; +CHECKREG r1, 0xCC671F1A; +CHECKREG r2, 0x0015C084; +CHECKREG r3, 0x009C09A8; +CHECKREG r4, 0xFFFDA7C4; +CHECKREG r5, 0x00970770; +CHECKREG r6, 0xFFFF9B56; +CHECKREG r7, 0x005CA88E; + +imm32 r0, 0x00245618; +imm32 r1, 0x01256719; +imm32 r2, 0x0226781a; +imm32 r3, 0x03278912; +imm32 r4, 0x06489113; +imm32 r5, 0x05291214; +imm32 r6, 0x01634517; +imm32 r7, 0x02234517; +A1 += R0.L * R1.H, A0 -= R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 -= R2.L * R3.H, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.L * R5.H, A0 -= R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.L * R7.H, A0 -= R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0xBAA77AA6; +CHECKREG r1, 0x0121BB7E; +CHECKREG r2, 0xBD9CAE92; +CHECKREG r3, 0xFE2C8792; +CHECKREG r4, 0xBCB99352; +CHECKREG r5, 0x02A5517C; +CHECKREG r6, 0xBCB3A640; +CHECKREG r7, 0x03CC91C6; + +imm32 r0, 0x10240648; +imm32 r1, 0x25156749; +imm32 r2, 0x3526084a; +imm32 r3, 0x45238942; +imm32 r4, 0x51381143; +imm32 r5, 0x62392244; +imm32 r6, 0xa3333547; +imm32 r7, 0xc4334547; +A1 += R0.H * R1.H, A0 -= R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 -= R2.H * R3.H, A0 -= R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.H * R5.H, A0 += R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.H * R7.H, A0 -= R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0xB7A22130; +CHECKREG r1, 0x08799FAE; +CHECKREG r2, 0xB327F8F4; +CHECKREG r3, 0xEBC49B4A; +CHECKREG r4, 0xC8E5FEB4; +CHECKREG r5, 0xAD71905A; +CHECKREG r6, 0x9D8AE062; +CHECKREG r7, 0xD8CCAEAC; + + +imm32 r0, 0x10245628; +imm32 r1, 0x23056729; +imm32 r2, 0x3320782a; +imm32 r3, 0x43270922; +imm32 r4, 0x56389023; +imm32 r5, 0x67391024; +imm32 r6, 0x21334507; +imm32 r7, 0x11334520; +A1 += R0.H * R1.L, A0 -= R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 -= R2.H * R3.L, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.H * R5.L, A0 -= R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.H * R7.L, A0 -= R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x581B1792; +CHECKREG r1, 0xE5CED234; +CHECKREG r2, 0x9725B05E; +CHECKREG r3, 0xE228FDB4; +CHECKREG r4, 0x8C46709E; +CHECKREG r5, 0xD749BDF4; +CHECKREG r6, 0x87D0704C; +CHECKREG r7, 0xE93788B4; + + + +pass diff --git a/tests/tcg/bfin/c_dsp32mac_pair_a0.s b/tests/tcg/bfin/c_dsp32mac_pair_a0.s new file mode 100644 index 0000000000000..e47600e31218f --- /dev/null +++ b/tests/tcg/bfin/c_dsp32mac_pair_a0.s @@ -0,0 +1,129 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0/c_dsp32mac_pair_a0.dsp +// Spec Reference: dsp32mac pair a0 +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 = R1.L * R0.L ); + P1 = A1.w; + P5 = A0.w; + A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ); + P2 = A1.w; + A1 -= R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ); + P3 = A0.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ); + P4 = A0.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF2CF3598; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF70DA834; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFF221DD6; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0x0004BA9E; + CHECKREG p3, 0xF2CF3598; + CHECKREG p4, 0xF70DA834; + CHECKREG p5, 0xFF221DD6; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 -= R1.L * R0.L ); + P1 = A0.w; + A1 = R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xFFBC8F22; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFFA518F6; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFD9B2E5E; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFD9B2E5E; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0xFFA518F6; + CHECKREG p4, 0xFFBC8F22; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ); + P1 = A0.w; + A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + A1 -= R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xF8876658; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x1EA0F4F8; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x00062F18; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xCB200616; + CHECKREG p2, 0x00062F18; + CHECKREG p3, 0xF8876658; + CHECKREG p4, 0x1EA0F4F8; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ); + P1 = A0.w; + A1 -= R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ); + P2 = A0.w; + A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ); + P3 = A0.w; + A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ); + P4 = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xFF256182; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xFF1FB35E; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xF750102E; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFF9EE9A; + CHECKREG p2, 0xFF256182; + CHECKREG p3, 0xFF1FB35E; + CHECKREG p4, 0xF750102E; + + pass diff --git a/tests/tcg/bfin/c_dsp32mac_pair_a0_i.s b/tests/tcg/bfin/c_dsp32mac_pair_a0_i.s new file mode 100644 index 0000000000000..75782f8b4f50a --- /dev/null +++ b/tests/tcg/bfin/c_dsp32mac_pair_a0_i.s @@ -0,0 +1,247 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_i/c_dsp32mac_pair_a0_i.dsp +// Spec Reference: dsp32mac pair a0 I +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (IS); + P1 = A0.w; + A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (IS); + P5 = A1.w; + P2 = A0.w; + A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (IS); + P3 = A0.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFD9ABC; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF9679ACC; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF857FE25; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x006EF115; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0x006EF115; + CHECKREG p2, 0xFFFD9ABC; + CHECKREG p3, 0xF9679ACC; + CHECKREG p4, 0xF857FE25; + CHECKREG p5, 0x00025D4F; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A0.w; + A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (IS); + P2 = A0.w; + A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFC8B26EA; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFC7F6BD4; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFCB93CEB; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFCB93CEB; + CHECKREG p2, 0xFCBB1787; + CHECKREG p3, 0xFC7F6BD4; + CHECKREG p4, 0xFC8B26EA; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (IS); + P1 = A0.w; + A1 -= R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (IS); + P2 = A0.w; + A1 = R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + A1 -= R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0x01A40FD3; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x0B2A737B; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0x16FB23DF; + CHECKREG p2, 0x0003178C; + CHECKREG p3, 0x01A40FD3; + CHECKREG p4, 0x0B2A737B; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (IS); + P1 = A0.w; + A1 = R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ) (IS); + P2 = A0.w; + A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (IS); + P3 = A0.w; + A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFCF74D; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xFF92B0C1; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xFF911149; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x007295B5; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFFCF74D; + CHECKREG p2, 0xFF92B0C1; + CHECKREG p3, 0xFF911149; + CHECKREG p4, 0x007295B5; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (IS); + P5 = A1.w; + P1 = A0.w; + A1 -= R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (IS); + P2 = A0.w; + A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (IS); + P3 = A0.w; + A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFD9ABC; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF9679ACC; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xFA773773; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFF910EEB; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF910EEB; + CHECKREG p2, 0xFFFD9ABC; + CHECKREG p3, 0xF9679ACC; + CHECKREG p4, 0xFA773773; + CHECKREG p5, 0xFF89C73F; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 -= R1.L * R0.L ) (IS); + P1 = A0.w; + R0 = ( A0 = R2.H * R3.L ) (IS); + P2 = A0.w; + R2 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + R0 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFE0B29B; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFFD4F785; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFDBDFA88; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFDBDFA88; + CHECKREG p2, 0xFFFE2564; + CHECKREG p3, 0xFFD4F785; + CHECKREG p4, 0xFFE0B29B; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A0.w; + R6 = ( A0 -= R2.H * R3.L ) (IS); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xE3AD394F; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xDB61F2C1; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0xE58CEB7F; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xE590030B; + CHECKREG p2, 0xE58CEB7F; + CHECKREG p3, 0xE3AD394F; + CHECKREG p4, 0xDB61F2C1; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 = R5.L * R3.L ) (IS); + P1 = A0.w; + A1 -= R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (IS); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 += R7.H * R0.H ) (IS); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFCF74D; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x006A468C; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x0068A714; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xFBE08004; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFFCF74D; + CHECKREG p2, 0x006A468C; + CHECKREG p3, 0x0068A714; + CHECKREG p4, 0xFBE08004; + + pass diff --git a/tests/tcg/bfin/c_dsp32mac_pair_a0_m.s b/tests/tcg/bfin/c_dsp32mac_pair_a0_m.s new file mode 100644 index 0000000000000..075704f659571 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32mac_pair_a0_m.s @@ -0,0 +1,129 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_m/c_dsp32mac_pair_a0_m.dsp +// Spec Reference: dsp32mac pair a0 m (M, MNOP) +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ); + P5 = A1.w; + P1 = A0.w; + A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ); + P3 = A0.w; + A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ); + P4 = A0.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF2CF3598; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF70DA834; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFF221DD6; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0xFFFB3578; + CHECKREG p3, 0xF2CF3598; + CHECKREG p4, 0xF70DA834; + CHECKREG p5, 0xFF910EEB; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 -= R1.L * R0.L ); + P1 = A0.w; + R0 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + R2 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + R0 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xFFBC8F22; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFFA518F6; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFD9B2E5E; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFD9B2E5E; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0xFFA518F6; + CHECKREG p4, 0xFFBC8F22; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ); + P1 = A0.w; + R6 = ( A0 -= R2.H * R3.L ); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xC39B0E3E; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xA26DF406; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0xCB19D6FE; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xCB200616; + CHECKREG p2, 0xCB19D6FE; + CHECKREG p3, 0xC39B0E3E; + CHECKREG p4, 0xA26DF406; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 = R5.L * R3.L ); + P1 = A0.w; + A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ); + P4 = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x00D48D18; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x00DA3B3C; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x06E3E0DC; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFF9EE9A; + CHECKREG p2, 0x00D48D18; + CHECKREG p3, 0x00DA3B3C; + CHECKREG p4, 0x06E3E0DC; + + pass diff --git a/tests/tcg/bfin/c_dsp32mac_pair_a1.s b/tests/tcg/bfin/c_dsp32mac_pair_a1.s new file mode 100644 index 0000000000000..36d8e2a0c6ed1 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32mac_pair_a1.s @@ -0,0 +1,127 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1/c_dsp32mac_pair_a1.dsp +// Spec Reference: dsp32mac pair a1 +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; + P1 = A1.w; + R1 = ( A1 = R2.L * R3.L ), A0 += R2.H * R3.L; + P2 = A1.w; + R3 = ( A1 -= R7.L * R4.L ), A0 += R7.H * R4.H; + P3 = A1.w; + R5 = ( A1 -= R6.L * R5.L ), A0 -= R6.L * R5.H; + P4 = A1.w; + CHECKREG r0, 0x63545ABD; + CHECKREG r1, 0x0004BA9E; + CHECKREG r2, 0xA8645679; + CHECKREG r3, 0xE8616512; + CHECKREG r4, 0xEFB86569; + CHECKREG r5, 0xF0688FB4; + CHECKREG r6, 0x000C086D; + CHECKREG r7, 0xFF221DD6; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0x0004BA9E; + CHECKREG p3, 0xE8616512; + CHECKREG p4, 0xF0688FB4; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ), A0 -= R1.L * R0.L; + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L; + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ), A0 += R4.H * R5.H; + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x98764ABD; + CHECKREG r1, 0x012F2306; + CHECKREG r2, 0xA1145649; + CHECKREG r3, 0x0117ACDA; + CHECKREG r4, 0xEFBC1569; + CHECKREG r5, 0xF97C8728; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xF97C8728; + CHECKREG p2, 0x0000AC92; + CHECKREG p3, 0x0117ACDA; + CHECKREG p4, 0x012F2306; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), A0 = R1.L * R0.L; + P1 = A1.w; + R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L; + P2 = A1.w; + R1 = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H; + P3 = A1.w; + R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x7136459D; + CHECKREG r1, 0xCABE16DA; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xEF9C1569; + CHECKREG r5, 0xCABE9156; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0xD363146A; + CHECKREG p1, 0xD3694382; + CHECKREG p2, 0xD363146A; + CHECKREG p3, 0xCABE16DA; + CHECKREG p4, 0xCABE9156; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L; + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L; + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H; + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H; + P4 = A1.w; + CHECKREG r0, 0x123489BD; + CHECKREG r1, 0xDBB6D160; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0x18A4A070; + CHECKREG r4, 0xEDB91569; + CHECKREG r5, 0x09DF3640; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0x08024998; + CHECKREG p1, 0xDBB6D160; + CHECKREG p2, 0x18A4A070; + CHECKREG p3, 0x09DF3640; + CHECKREG p4, 0x08024998; + + pass diff --git a/tests/tcg/bfin/c_dsp32mac_pair_a1_i.s b/tests/tcg/bfin/c_dsp32mac_pair_a1_i.s new file mode 100644 index 0000000000000..8ac571dcf8dc5 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32mac_pair_a1_i.s @@ -0,0 +1,243 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_i/c_dsp32mac_pair_a1_i.dsp +// Spec Reference: dsp32mac pair a1 I +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x93545abd; + imm32 r1, 0x89bcfec7; + imm32 r2, 0xa8945679; + imm32 r3, 0x00890007; + imm32 r4, 0xefb89569; + imm32 r5, 0x1235890b; + imm32 r6, 0x000c089d; + imm32 r7, 0x678e0089; + R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (IS); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.L ), A0 -= R2.H * R3.L (IS); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (IS); + P3 = A1.w; + R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (IS); + P4 = A1.w; + CHECKREG r0, 0x93545ABD; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0xA8945679; + CHECKREG r3, 0xF9C9E563; + CHECKREG r4, 0xEFB89569; + CHECKREG r5, 0xF5C94922; + CHECKREG r6, 0x000C089D; + CHECKREG r7, 0xFF910EEB; + CHECKREG p1, 0xFF910EEB; + CHECKREG p2, 0x00025D4F; + CHECKREG p3, 0xF9C9E563; + CHECKREG p4, 0xF5C94922; + + imm32 r0, 0x98464abd; + imm32 r1, 0xa1b5f4c7; + imm32 r2, 0xa1146649; + imm32 r3, 0x00010805; + imm32 r4, 0xefbc1599; + imm32 r5, 0x12350100; + imm32 r6, 0x200c001d; + imm32 r7, 0x628e0001; + R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (IS); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS); + P2 = A1.w; + R3 = ( A1 = R4.L * R5.H ), A0 -= R4.H * R5.H (IS); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0x98464ABD; + CHECKREG r1, 0xFF90BFE3; + CHECKREG r2, 0xA1146649; + CHECKREG r3, 0xFF8595CD; + CHECKREG r4, 0xEFBC1599; + CHECKREG r5, 0xFA555F8C; + CHECKREG r6, 0x200C001D; + CHECKREG r7, 0x628E0001; + CHECKREG p1, 0xFA555F8C; + CHECKREG p2, 0x00006649; + CHECKREG p3, 0xFF8595CD; + CHECKREG p4, 0xFF90BFE3; + + imm32 r0, 0x713a459d; + imm32 r1, 0xabd6aec7; + imm32 r2, 0x7a145a79; + imm32 r3, 0x08a100a7; + imm32 r4, 0xef9a156a; + imm32 r5, 0x1225a10b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0a61; + R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (IS); + P1 = A1.w; + R7 = ( A1 -= R2.H * R3.L ), A0 = R2.H * R3.L (IS); + P2 = A1.w; + R1 = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IS); + P3 = A1.w; + R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0x713A459D; + CHECKREG r1, 0xE54D2A3B; + CHECKREG r2, 0x7A145A79; + CHECKREG r3, 0x08A100A7; + CHECKREG r4, 0xEF9A156A; + CHECKREG r5, 0xE54DB17A; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0xE85E2D15; + CHECKREG p1, 0xE8ADD021; + CHECKREG p2, 0xE85E2D15; + CHECKREG p3, 0xE54D2A3B; + CHECKREG p4, 0xE54DB17A; + + imm32 r0, 0x773489bd; + imm32 r1, 0x917cfec7; + imm32 r2, 0xa9177679; + imm32 r3, 0xd0910777; + imm32 r4, 0xedb91579; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d077999; + imm32 r7, 0x677e0709; + R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (IS); + P1 = A1.w; + R3 = ( A1 -= R2.H * R1.H ), A0 = R2.H * R1.L (IS); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H (IS); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 -= R4.L * R6.H (IS); + P4 = A1.w; + CHECKREG r0, 0x773489BD; + CHECKREG r1, 0xEDC9D17F; + CHECKREG r2, 0xA9177679; + CHECKREG r3, 0xE79AC370; + CHECKREG r4, 0xEDB91579; + CHECKREG r5, 0xB76A2BD8; + CHECKREG r6, 0x0D077999; + CHECKREG r7, 0xB67C10E7; + CHECKREG p1, 0xEDC9D17F; + CHECKREG p2, 0xE79AC370; + CHECKREG p3, 0xB76A2BD8; + CHECKREG p4, 0xB67C10E7; + + imm32 r0, 0x83547abd; + imm32 r1, 0x88bc8ec7; + imm32 r2, 0xa8895679; + imm32 r3, 0x00080007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c896d; + imm32 r7, 0x67Be0096; + R7 = ( A1 += R1.L * R0.L ) (IS); + P1 = A1.w; + R1 = ( A1 = R2.H * R3.L ) (IS); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.H ) (IS); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ) (IS); + P4 = A1.w; + CHECKREG r0, 0x83547ABD; + CHECKREG r1, 0xFFFD9BBF; + CHECKREG r2, 0xA8895679; + CHECKREG r3, 0xF81E0AF0; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0xF81F456C; + CHECKREG r6, 0x000C896D; + CHECKREG r7, 0x80334FD2; + CHECKREG p1, 0x80334FD2; + CHECKREG p2, 0xFFFD9BBF; + CHECKREG p3, 0xF81E0AF0; + CHECKREG p4, 0xF81F456C; + + imm32 r0, 0x9aa64abd; + imm32 r1, 0xa1baf4c7; + imm32 r2, 0xb114a649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcdb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c0d1b; + imm32 r7, 0x678e0d01; + R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (IS); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ) (M), A0 -= R2.H * R3.L (IS); + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H (IS); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0x9AA64ABD; + CHECKREG r1, 0x23F08194; + CHECKREG r2, 0xB114A649; + CHECKREG r3, 0x1EA35F9A; + CHECKREG r4, 0xEFBCDB69; + CHECKREG r5, 0xF157B476; + CHECKREG r6, 0x000C0D1B; + CHECKREG r7, 0x678E0D01; + CHECKREG p1, 0xF157B476; + CHECKREG p2, 0xFC24C949; + CHECKREG p3, 0x1EA35F9A; + CHECKREG p4, 0x23F08194; + + imm32 r0, 0xd136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xdd010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x00e3d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 -= R1.L * R0.L (IS); + P1 = A1.w; + R7 = A1 , A0 = R2.H * R3.L (IS); + P2 = A1.w; + R1 = A1 , A0 += R4.H * R5.H (IS); + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0xD136459D; + CHECKREG r1, 0x23F08194; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xDD010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0x23F08194; + CHECKREG r6, 0x00E3D01D; + CHECKREG r7, 0x23F08194; + CHECKREG p1, 0x23F08194; + CHECKREG p2, 0x23F08194; + CHECKREG p3, 0x23F08194; + CHECKREG p4, 0x23F08194; + + imm32 r0, 0x125489bd; + imm32 r1, 0x91b5fec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910507; + imm32 r4, 0x34567859; + imm32 r5, 0xd2359105; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M,IS); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ) (M,IS); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ) (M,IS); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M,IS); + P4 = A1.w; + CHECKREG r0, 0x125489BD; + CHECKREG r1, 0xFEA1A199; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0xA98B2D94; + CHECKREG r4, 0x34567859; + CHECKREG r5, 0xA21B7CBC; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0xA4C64EC4; + CHECKREG p1, 0xFEA1A199; + CHECKREG p2, 0xA98B2D94; + CHECKREG p3, 0xA21B7CBC; + CHECKREG p4, 0xA4C64EC4; + + pass diff --git a/tests/tcg/bfin/c_dsp32mac_pair_a1_m.s b/tests/tcg/bfin/c_dsp32mac_pair_a1_m.s new file mode 100644 index 0000000000000..f93e7a535ffd2 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32mac_pair_a1_m.s @@ -0,0 +1,127 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_m/c_dsp32mac_pair_a1_m.dsp +// Spec Reference: dsp32mac pair a1 M MNOP +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x63547abd; + imm32 r1, 0x86bc8ec7; + imm32 r2, 0xa8695679; + imm32 r3, 0x00060007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x67Be0086; + R7 = ( A1 += R1.L * R0.L ); + P1 = A1.w; + R1 = ( A1 -= R2.H * R3.L ); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.H ); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ); + P4 = A1.w; + CHECKREG r0, 0x63547ABD; + CHECKREG r1, 0x93734818; + CHECKREG r2, 0xA8695679; + CHECKREG r3, 0xE7256BA0; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0xE727E098; + CHECKREG r6, 0x000C086D; + CHECKREG r7, 0x936E7DD6; + CHECKREG p1, 0x936E7DD6; + CHECKREG p2, 0x93734818; + CHECKREG p3, 0xE7256BA0; + CHECKREG p4, 0xE727E098; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xb1145649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcbb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c001b; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L; + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ) (M), A0 = R2.H * R3.L; + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H; + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x98764ABD; + CHECKREG r1, 0x3FE4AC0B; + CHECKREG r2, 0xB1145649; + CHECKREG r3, 0x3FD9C011; + CHECKREG r4, 0xEFBCBB69; + CHECKREG r5, 0xE078DC52; + CHECKREG r6, 0x000C001B; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xE078DC52; + CHECKREG p2, 0x03B57949; + CHECKREG p3, 0x3FD9C011; + CHECKREG p4, 0x3FE4AC0B; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xd8010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x0003d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 = R1.L * R0.L; + P1 = A1.w; + R7 = A1 , A0 -= R2.H * R3.L; + P2 = A1.w; + R1 = A1 , A0 += R4.H * R5.H; + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x7136459D; + CHECKREG r1, 0x3FE4AC0B; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xD8010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0x3FE4AC0B; + CHECKREG r6, 0x0003D01D; + CHECKREG r7, 0x3FE4AC0B; + CHECKREG p1, 0x3FE4AC0B; + CHECKREG p2, 0x3FE4AC0B; + CHECKREG p3, 0x3FE4AC0B; + CHECKREG p4, 0x3FE4AC0B; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0x34567899; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ) (M); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ) (M); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M); + P4 = A1.w; + CHECKREG r0, 0x123489BD; + CHECKREG r1, 0x1A95CC10; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0xF6F970A4; + CHECKREG r4, 0x34567899; + CHECKREG r5, 0xEF96BB8C; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0xF2418D94; + CHECKREG p1, 0x1A95CC10; + CHECKREG p2, 0xF6F970A4; + CHECKREG p3, 0xEF96BB8C; + CHECKREG p4, 0xF2418D94; + + pass diff --git a/tests/tcg/bfin/c_dsp32mult_pair_m.s b/tests/tcg/bfin/c_dsp32mult_pair_m.s new file mode 100644 index 0000000000000..73ab875560f4e --- /dev/null +++ b/tests/tcg/bfin/c_dsp32mult_pair_m.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m/c_dsp32mult_pair_m.dsp +// Spec Reference: dsp32mult pair MUNOP +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L; +R2 = R0.L * R1.H; +R4 = R1.H * R1.H; +R6 = R0.L * R0.L; +CHECKREG r0, 0x39F9C2B2; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x2E3AADA8; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x48C98C48; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0x1D5C8788; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L; +R2 = R2.L * R3.H; +R4 = R3.H * R2.H; +R6 = R2.L * R3.L; +CHECKREG r0, 0x2965A1F2; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x3FAE367C; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0xC84ABC28; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x00176948; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L; +R2 = R4.L * R5.H; +R4 = R5.H * R5.H; +R6 = R4.L * R5.L; +CHECKREG r0, 0x1B29B4A2; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0xF85431BE; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x022A99E2; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0x0D4762AC; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L; +R2 = R6.L * R7.H; +R4 = R7.H * R7.H; +R6 = R6.L * R7.L; +CHECKREG r0, 0x31781CD2; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0xF4A3CF9C; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x029BD648; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0xBA1A5E86; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L; +R2 = R1.L * R6.H; +R4 = R3.H * R4.H; +R6 = R4.L * R3.L; +CHECKREG r0, 0x0B26E1B6; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x00079BA8; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0xFFFAC804; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0xFFFCF038; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H; +R3 = R6.H * R1.H; +R5 = R5.H * R2.L; +R7 = R4.L * R3.H; +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xF3E28324; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0xFFFEDD30; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x0DADBEB8; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x0000CBDC; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L; +R3 = R5.L * R3.H; +R5 = R3.H * R1.L; +R7 = R1.H * R2.H; +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0xFFF6B8D8; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0xFFFE7166; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0x00011CA0; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0xFFFE7870; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H; +R3 = R6.H * R1.H; +R5 = R1.L * R2.L; +R7 = R4.H * R2.L; +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0x03175676; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x00004A28; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0x4596549C; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0xA66540AE; + + +pass diff --git a/tests/tcg/bfin/c_dsp32mult_pair_m_i.s b/tests/tcg/bfin/c_dsp32mult_pair_m_i.s new file mode 100644 index 0000000000000..b865be0c5e889 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32mult_pair_m_i.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m_i/c_dsp32mult_pair_m_i.dsp +// Spec Reference: dsp32mult pair MUNOP i +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L (IS); +R2 = R0.L * R1.H (IS); +R4 = R1.H * R1.H (IS); +R6 = R0.L * R0.L (IS); +CHECKREG r0, 0x1CFCE159; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x0B8EAB6A; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x2464C624; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0x03AB90F1; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L (IS); +R2 = R2.L * R3.H (IS); +R4 = R3.H * R2.H (IS); +R6 = R2.L * R3.L (IS); +CHECKREG r0, 0x14B2D0F9; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x1FD71B3E; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0xF212AF0A; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x0005DA52; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L (IS); +R2 = R4.L * R5.H (IS); +R4 = R5.H * R5.H (IS); +R6 = R4.L * R5.L (IS); +CHECKREG r0, 0x0D94DA51; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0xFC2A18DF; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x01154CF1; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0xFAFF58AB; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L (IS); +R2 = R6.L * R7.H (IS); +R4 = R7.H * R7.H (IS); +R6 = R6.L * R7.L (IS); +CHECKREG r0, 0x18BC0E69; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0xFA51E7CE; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x014DEB24; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0xDD0D2F43; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L (IS); +R2 = R1.L * R6.H (IS); +R4 = R3.H * R4.H (IS); +R6 = R4.L * R3.L (IS); +CHECKREG r0, 0x059370DB; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x0003CDD4; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0xFFFD6402; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0x0002BC0E; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H (IS); +R3 = R6.H * R1.H (IS); +R5 = R5.H * R2.L (IS); +R7 = R4.L * R3.H (IS); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xF9F14192; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0xFFFFB74C; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x06D6DF5C; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x000032F7; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L (IS); +R3 = R5.L * R3.H (IS); +R5 = R3.H * R1.L (IS); +R7 = R1.H * R2.H (IS); +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0xFFFB5C6C; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0xFFFF38B3; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0xFFFFA394; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0xFFFF9E1C; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H (IS); +R3 = R6.H * R1.H (IS); +R5 = R1.L * R2.L (IS); +R7 = R4.H * R2.L (IS); +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0x018BAB3B; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x00001284; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0xDDE31527; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0xD332A057; + + +pass diff --git a/tests/tcg/bfin/c_dsp32mult_pair_m_u.s b/tests/tcg/bfin/c_dsp32mult_pair_m_u.s new file mode 100644 index 0000000000000..d7f66331c735c --- /dev/null +++ b/tests/tcg/bfin/c_dsp32mult_pair_m_u.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m_u/c_dsp32mult_pair_m_u.dsp +// Spec Reference: dsp32mult pair MUNOP u +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L (FU); +R2 = R0.L * R1.H (FU); +R4 = R1.H * R1.H (FU); +R6 = R0.L * R0.L (FU); +CHECKREG r0, 0x1CFCE159; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x8C61AB6A; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x6358C624; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0xC65D90F1; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L (FU); +R2 = R2.L * R3.H (FU); +R4 = R3.H * R2.H (FU); +R6 = R2.L * R3.L (FU); +CHECKREG r0, 0x831CD0F9; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x67121B3E; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0x39FC8A6C; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x0005DA52; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L (FU); +R2 = R4.L * R5.H (FU); +R4 = R5.H * R5.H (FU); +R6 = R4.L * R5.L (FU); +CHECKREG r0, 0x97A6DA51; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0x0CD118DF; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x01154CF1; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0x47F058AB; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L (FU); +R2 = R6.L * R7.H (FU); +R4 = R7.H * R7.H (FU); +R6 = R6.L * R7.L (FU); +CHECKREG r0, 0x79960E69; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0x0C97E7CE; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x014DEB24; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0x4D7C2F43; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L (FU); +R2 = R1.L * R6.H (FU); +R4 = R3.H * R4.H (FU); +R6 = R4.L * R3.L (FU); +CHECKREG r0, 0x9C1770DB; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x0003CDD4; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00036402; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0x0002BC0E; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H (FU); +R3 = R6.H * R1.H (FU); +R5 = R5.H * R2.L (FU); +R7 = R4.L * R3.H (FU); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0x0C374192; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0x00009294; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x06D6DF5C; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L (FU); +R3 = R5.L * R3.H (FU); +R5 = R3.H * R1.L (FU); +R7 = R1.H * R2.H (FU); +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0x00075C6C; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0x000838B3; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0x0002E360; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0x0000890C; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H (FU); +R3 = R6.H * R1.H (FU); +R5 = R1.L * R2.L (FU); +R7 = R4.H * R2.L (FU); +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0xD9B7AB3B; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x000A3494; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0x44E81527; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0x3A37A057; + + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_a0alr.s b/tests/tcg/bfin/c_dsp32shift_a0alr.s new file mode 100644 index 0000000000000..d66b5c4acad6d --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_a0alr.s @@ -0,0 +1,77 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_a0alr/c_dsp32shift_a0alr.dsp +// Spec Reference: dsp32shift a0 ashift, lshift, rot +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x13340000; + imm32 r1, 0x038C003E; + imm32 r2, 0x83159E24; + imm32 r3, 0x83159E24; + imm32 r4, 0xD359E268; + imm32 r5, 0x53E26AF2; + imm32 r6, 0x9326AF36; + imm32 r7, 0xE36BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = ROT A0 BY R0.L; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x038C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = ROT A0 BY R1.L; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0x0718007C; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = ROT A0 BY R2.L; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x003E0001; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = ROT A0 BY R3.L; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0xE3000F80; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = ROT A0 BY R4.L; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x718007C0; + + R5.L = -16; + A0.L = R6.L; + A0.H = R6.H; + A0 = ROT A0 BY R5.L; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x80007180; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = ROT A0 BY R6.L; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x01C6001F; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + A0 = ROT A0 BY R7.L; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x8C003E00; + + pass diff --git a/tests/tcg/bfin/c_dsp32shift_af.s b/tests/tcg/bfin/c_dsp32shift_af.s new file mode 100644 index 0000000000000..c93587b7c5139 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_af.s @@ -0,0 +1,186 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_af/c_dsp32shift_af.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + +// ashift : mix data, count (+)= (half reg) +// d_reg = ashift (d BY d_lo) +// Rx by RLx + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4 = ASHIFT R0 BY R0.L; + R5 = ASHIFT R1 BY R0.L; + R6 = ASHIFT R2 BY R0.L; + R7 = ASHIFT R3 BY R0.L; + CHECKREG r4, 0x02460002; + CHECKREG r5, 0x2468ACF0; + CHECKREG r6, 0x468ACF12; + CHECKREG r7, 0x68ACF134; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0xa6789abc; + imm32 r6, 0xb789abcd; + imm32 r7, 0xc89abcde; + R1.L = 5; + R5 = ASHIFT R0 BY R1.L; + R6 = ASHIFT R1 BY R1.L; + R7 = ASHIFT R2 BY R1.L; + R4 = ASHIFT R3 BY R1.L; + CHECKREG r4, 0x8ACF1340; + CHECKREG r5, 0x24600040; + CHECKREG r6, 0x468000A0; + CHECKREG r7, 0x68ACF120; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2 = 15; + R6 = ASHIFT R0 BY R2.L; + R7 = ASHIFT R1 BY R2.L; + R4 = ASHIFT R2 BY R2.L; + R5 = ASHIFT R3 BY R2.L; + CHECKREG r4, 0x00078000; + CHECKREG r5, 0x3C4D0000; + CHECKREG r6, 0x80010000; + CHECKREG r7, 0x2B3C0000; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0xa56789ab; + imm32 r5, 0xb6789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0xd89abcde; + R3.L = 16; + R7 = ASHIFT R0 BY R3.L; + R6 = ASHIFT R1 BY R3.L; + R5 = ASHIFT R2 BY R3.L; + R4 = ASHIFT R3 BY R3.L; + CHECKREG r4, 0x00100000; + CHECKREG r5, 0x67890000; + CHECKREG r6, 0x56780000; + CHECKREG r7, 0x00020000; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R7 = ASHIFT R0 BY R4.L; + R0 = ASHIFT R1 BY R4.L; + R1 = ASHIFT R2 BY R4.L; + R2 = ASHIFT R3 BY R4.L; + R3 = ASHIFT R4 BY R4.L; + R4 = ASHIFT R5 BY R4.L; + R5 = ASHIFT R6 BY R4.L; + R6 = ASHIFT R7 BY R4.L; + CHECKREG r0, 0x091A2B3C; + CHECKREG r1, 0x11A2B3C4; + CHECKREG r2, 0x1A2B3C4D; + CHECKREG r3, 0x22B3FFFF; + CHECKREG r4, 0x2B3C4D5E; + CHECKREG r5, 0x40000000; + CHECKREG r6, 0x40000000; + CHECKREG r7, 0x00918001; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -6; + R6 = ASHIFT R0 BY R5.L; + R7 = ASHIFT R1 BY R5.L; + R0 = ASHIFT R2 BY R5.L; + R1 = ASHIFT R3 BY R5.L; + R2 = ASHIFT R4 BY R5.L; + R3 = ASHIFT R5 BY R5.L; + R4 = ASHIFT R6 BY R5.L; + R5 = ASHIFT R7 BY R5.L; + CHECKREG r0, 0xFE4D159E; + CHECKREG r1, 0xFE9159E2; + CHECKREG r2, 0xFED59E26; + CHECKREG r3, 0xFF19E3FF; + CHECKREG r4, 0x00001230; + CHECKREG r5, 0xFFF82345; + CHECKREG r6, 0x00048C00; + CHECKREG r7, 0xFE08D159; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -15; + R5 = ASHIFT R0 BY R6.L; + R0 = ASHIFT R1 BY R6.L; + R7 = ASHIFT R2 BY R6.L; + R0 = ASHIFT R3 BY R6.L; + R1 = ASHIFT R4 BY R6.L; + R2 = ASHIFT R5 BY R6.L; + R3 = ASHIFT R6 BY R6.L; + R6 = ASHIFT R7 BY R6.L; + CHECKREG r0, 0x000068AC; + CHECKREG r1, 0x00008ACF; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x0000CF13; + CHECKREG r4, 0x456789AB; + CHECKREG r5, 0x00000246; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x0000468A; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R7.L = -14; + R0 = ASHIFT R0 BY R7.L; + R1 = ASHIFT R1 BY R7.L; + R2 = ASHIFT R2 BY R7.L; + R3 = ASHIFT R3 BY R7.L; + R4 = ASHIFT R4 BY R7.L; + R5 = ASHIFT R5 BY R7.L; + R6 = ASHIFT R6 BY R7.L; + R7 = ASHIFT R7 BY R7.L; + CHECKREG r0, 0x0000048C; + CHECKREG r1, 0xFFFE08D1; + CHECKREG r2, 0xFFFE4D15; + CHECKREG r3, 0xFFFE9159; + CHECKREG r4, 0xFFFED59E; + CHECKREG r5, 0xFFFF19E2; + CHECKREG r6, 0xFFFF5E26; + CHECKREG r7, 0xFFFFA26B; + + pass diff --git a/tests/tcg/bfin/c_dsp32shift_ahalf_ln.s b/tests/tcg/bfin/c_dsp32shift_ahalf_ln.s new file mode 100644 index 0000000000000..9a37aef16a3b4 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_ahalf_ln.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_ln/c_dsp32shift_ahalf_ln.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + + +// Ashift : neg data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = ASHIFT R0.L BY R0.L; +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c001; +CHECKREG r2, 0x0000c002; +CHECKREG r3, 0x0000c003; +CHECKREG r4, 0x0000c004; +CHECKREG r5, 0x0000c005; +CHECKREG r6, 0x0000c006; +CHECKREG r7, 0x0000c007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000a004; +CHECKREG r3, 0x0000c006; +CHECKREG r4, 0x0000e008; +CHECKREG r5, 0x0000800a; +CHECKREG r6, 0x0000a00c; +CHECKREG r7, 0x0000c00e; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x90012002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x90022004; +CHECKREG r3, 0x90032006; +CHECKREG r4, 0x90042008; +CHECKREG r5, 0x9005200a; +CHECKREG r6, 0x9006200c; +CHECKREG r7, 0x9007200e; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0xa0018000; +CHECKREG r1, 0xa0018000; +CHECKREG r2, 0xa002000f; +CHECKREG r3, 0xa0038000; +CHECKREG r4, 0xa0040000; +CHECKREG r5, 0xa0058000; +CHECKREG r6, 0xa0060000; +CHECKREG r7, 0xa0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0xc0010000; +CHECKREG r1, 0xc0010000; +CHECKREG r2, 0xc0020000; +CHECKREG r3, 0xc0030010; +CHECKREG r4, 0xc0040000; +CHECKREG r5, 0xc0050000; +CHECKREG r6, 0xc0060000; +CHECKREG r7, 0xc0070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R0.L; +R1.H = ASHIFT R1.L BY R0.L; +R2.H = ASHIFT R2.L BY R0.L; +R3.H = ASHIFT R3.L BY R0.L; +R4.H = ASHIFT R4.L BY R0.L; +R5.H = ASHIFT R5.L BY R0.L; +R6.H = ASHIFT R6.L BY R0.L; +R7.H = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.H = ASHIFT R0.L BY R1.L; +R1.H = ASHIFT R1.L BY R1.L; +R2.H = ASHIFT R2.L BY R1.L; +R3.H = ASHIFT R3.L BY R1.L; +R4.H = ASHIFT R4.L BY R1.L; +R5.H = ASHIFT R5.L BY R1.L; +R6.H = ASHIFT R6.L BY R1.L; +R7.H = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0xa002d001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0xa004d002; +CHECKREG r3, 0xa006d003; +CHECKREG r4, 0xa008d004; +CHECKREG r5, 0xa00ad005; +CHECKREG r6, 0xa00cd006; +CHECKREG r7, 0xa00ed007; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = ASHIFT R0.L BY R2.L; +R1.H = ASHIFT R1.L BY R2.L; +//rh2 = ashift (rl2 by rl2); +R3.H = ASHIFT R3.L BY R2.L; +R4.H = ASHIFT R4.L BY R2.L; +R5.H = ASHIFT R5.L BY R2.L; +R6.H = ASHIFT R6.L BY R2.L; +R7.H = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x8000e001; +CHECKREG r1, 0x8000e001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x8000e003; +CHECKREG r4, 0x0000e004; +CHECKREG r5, 0x8000e005; +CHECKREG r6, 0x0000e006; +CHECKREG r7, 0x8000e007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.H = ASHIFT R0.L BY R3.L; +R1.H = ASHIFT R1.L BY R3.L; +R2.H = ASHIFT R2.L BY R3.L; +R3.H = ASHIFT R3.L BY R3.L; +R4.H = ASHIFT R4.L BY R3.L; +R5.H = ASHIFT R5.L BY R3.L; +R6.H = ASHIFT R6.L BY R3.L; +R7.H = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x0000f001; +CHECKREG r1, 0x0000f001; +CHECKREG r2, 0x0000f002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000f004; +CHECKREG r5, 0x0000f005; +CHECKREG r6, 0x0000f006; +CHECKREG r7, 0x0000f007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R0.L; +R1.H = ASHIFT R1.H BY R0.L; +R2.H = ASHIFT R2.H BY R0.L; +R3.H = ASHIFT R3.H BY R0.L; +R4.H = ASHIFT R4.H BY R0.L; +R5.H = ASHIFT R5.H BY R0.L; +R6.H = ASHIFT R6.H BY R0.L; +R7.H = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.H = ASHIFT R0.H BY R1.L; +R1.H = ASHIFT R1.H BY R1.L; +R2.H = ASHIFT R2.H BY R1.L; +R3.H = ASHIFT R3.H BY R1.L; +R4.H = ASHIFT R4.H BY R1.L; +R5.H = ASHIFT R5.H BY R1.L; +R6.H = ASHIFT R6.H BY R1.L; +R7.H = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x40020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x40040000; +CHECKREG r3, 0x40060000; +CHECKREG r4, 0x40080000; +CHECKREG r5, 0x400a0000; +CHECKREG r6, 0x400c0000; +CHECKREG r7, 0x400e0000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0xb0018000; +CHECKREG r1, 0xb0018000; +CHECKREG r2, 0xb002000f; +CHECKREG r3, 0xb0038000; +CHECKREG r4, 0xb0040000; +CHECKREG r5, 0xb0058000; +CHECKREG r6, 0xb0060000; +CHECKREG r7, 0xb0078000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R0.H = ASHIFT R0.H BY R3.L; +R1.H = ASHIFT R1.H BY R3.L; +R2.H = ASHIFT R2.H BY R3.L; +R3.H = ASHIFT R3.H BY R3.L; +R4.H = ASHIFT R4.H BY R3.L; +R5.H = ASHIFT R5.H BY R3.L; +R6.H = ASHIFT R6.H BY R3.L; +R7.H = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +pass diff --git a/tests/tcg/bfin/c_dsp32shift_ahalf_lp.s b/tests/tcg/bfin/c_dsp32shift_ahalf_lp.s new file mode 100644 index 0000000000000..ecfa5f61d28ba --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_ahalf_lp.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_lp/c_dsp32shift_ahalf_lp.dsp +// Spec Reference: dsp32shift ashift half reg left positive +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R0.L; +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000006; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x0000000c; +CHECKREG r7, 0x0000000e; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x00010002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020004; +CHECKREG r3, 0x00030006; +CHECKREG r4, 0x00040008; +CHECKREG r5, 0x0005000a; +CHECKREG r6, 0x0006000c; +CHECKREG r7, 0x0007000e; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010001; +imm32 r1, 0x00010001; +imm32 r2, 0x00020002; +imm32 r3, 0x00030010; +imm32 r4, 0x00040004; +imm32 r5, 0x00050005; +imm32 r6, 0x00060006; +imm32 r7, 0x00070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030010; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R0.L; +R1.H = ASHIFT R1.L BY R0.L; +R2.H = ASHIFT R2.L BY R0.L; +R3.H = ASHIFT R3.L BY R0.L; +R4.H = ASHIFT R4.L BY R0.L; +R5.H = ASHIFT R5.L BY R0.L; +R6.H = ASHIFT R6.L BY R0.L; +R7.H = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R1.L; +R1.H = ASHIFT R1.L BY R1.L; +R2.H = ASHIFT R2.L BY R1.L; +R3.H = ASHIFT R3.L BY R1.L; +R4.H = ASHIFT R4.L BY R1.L; +R5.H = ASHIFT R5.L BY R1.L; +R6.H = ASHIFT R6.L BY R1.L; +R7.H = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x00020001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040002; +CHECKREG r3, 0x00060003; +CHECKREG r4, 0x00080004; +CHECKREG r5, 0x000a0005; +CHECKREG r6, 0x000c0006; +CHECKREG r7, 0x000e0007; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R2.L; +R1.H = ASHIFT R1.L BY R2.L; +//rh2 = ashift (rl2 by rl2); +R3.H = ASHIFT R3.L BY R2.L; +R4.H = ASHIFT R4.L BY R2.L; +R5.H = ASHIFT R5.L BY R2.L; +R6.H = ASHIFT R6.L BY R2.L; +R7.H = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x80000001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x80000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x80000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x80000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R3.L; +R1.H = ASHIFT R1.L BY R3.L; +R2.H = ASHIFT R2.L BY R3.L; +R3.H = ASHIFT R3.L BY R3.L; +R4.H = ASHIFT R4.L BY R3.L; +R5.H = ASHIFT R5.L BY R3.L; +R6.H = ASHIFT R6.L BY R3.L; +R7.H = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R0.L; +R1.H = ASHIFT R1.H BY R0.L; +R2.H = ASHIFT R2.H BY R0.L; +R3.H = ASHIFT R3.H BY R0.L; +R4.H = ASHIFT R4.H BY R0.L; +R5.H = ASHIFT R5.H BY R0.L; +R6.H = ASHIFT R6.H BY R0.L; +R7.H = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R1.L; +R1.H = ASHIFT R1.H BY R1.L; +R2.H = ASHIFT R2.H BY R1.L; +R3.H = ASHIFT R3.H BY R1.L; +R4.H = ASHIFT R4.H BY R1.L; +R5.H = ASHIFT R5.H BY R1.L; +R6.H = ASHIFT R6.H BY R1.L; +R7.H = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00060000; +CHECKREG r4, 0x00080000; +CHECKREG r5, 0x000a0000; +CHECKREG r6, 0x000c0000; +CHECKREG r7, 0x000e0000; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030010; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R3.L; +R1.H = ASHIFT R1.H BY R3.L; +R2.H = ASHIFT R2.H BY R3.L; +R3.H = ASHIFT R3.H BY R3.L; +R4.H = ASHIFT R4.H BY R3.L; +R5.H = ASHIFT R5.H BY R3.L; +R6.H = ASHIFT R6.H BY R3.L; +R7.H = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_ahalf_rn.s b/tests/tcg/bfin/c_dsp32shift_ahalf_rn.s new file mode 100644 index 0000000000000..aaa282c845a3e --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_ahalf_rn.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rn/c_dsp32shift_ahalf_rn.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c000; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x0000c000; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +R2.L = -15; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x0000ffff; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +CHECKREG r2, 0x0000ffff; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80018001; +CHECKREG r2, 0x80028002; +CHECKREG r3, 0x80038003; +CHECKREG r4, 0x80048004; +CHECKREG r5, 0x80058005; +CHECKREG r6, 0x80068006; +CHECKREG r7, 0x80078007; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x8001c000; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x8002c001; +CHECKREG r3, 0x8003c001; +CHECKREG r4, 0x8004c002; +CHECKREG r5, 0x8005c002; +CHECKREG r6, 0x8006c003; +CHECKREG r7, 0x8007c003; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0xa001ffff; +CHECKREG r1, 0xa001ffff; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0xa003ffff; +CHECKREG r4, 0xa004ffff; +CHECKREG r5, 0xa005ffff; +CHECKREG r6, 0xa006ffff; +CHECKREG r7, 0xa007ffff; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0xb001ffff; +CHECKREG r1, 0xb001ffff; +CHECKREG r2, 0xb002ffff; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0xb004ffff; +CHECKREG r5, 0xb005ffff; +CHECKREG r6, 0xb006ffff; +CHECKREG r7, 0xb007ffff; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L; +R1.H = ASHIFT R1.L BY R4.L; +R2.H = ASHIFT R2.L BY R4.L; +R3.H = ASHIFT R3.L BY R4.L; +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L; +R6.H = ASHIFT R6.L BY R4.L; +R7.H = ASHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = ASHIFT R0.L BY R5.L; +R1.H = ASHIFT R1.L BY R5.L; +R2.H = ASHIFT R2.L BY R5.L; +R3.H = ASHIFT R3.L BY R5.L; +R4.H = ASHIFT R4.L BY R5.L; +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L; +R7.H = ASHIFT R7.L BY R5.L; +CHECKREG r0, 0xc0008001; +CHECKREG r1, 0xc0008001; +CHECKREG r2, 0xc0018002; +CHECKREG r3, 0xc0018003; +CHECKREG r4, 0xc0028004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0xc0038006; +CHECKREG r7, 0xc0038007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = ASHIFT R0.L BY R6.L; +R1.H = ASHIFT R1.L BY R6.L; +R2.H = ASHIFT R2.L BY R6.L; +R3.H = ASHIFT R3.L BY R6.L; +R4.H = ASHIFT R4.L BY R6.L; +R5.H = ASHIFT R5.L BY R6.L; +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0xffff9001; +CHECKREG r1, 0xffff9001; +CHECKREG r2, 0xffff9002; +CHECKREG r3, 0xffff9003; +CHECKREG r4, 0xffff9004; +CHECKREG r5, 0xffff9005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0xffff9007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L; +R1.H = ASHIFT R1.L BY R7.L; +R2.H = ASHIFT R2.L BY R7.L; +R3.H = ASHIFT R3.L BY R7.L; +R4.H = ASHIFT R4.L BY R7.L; +R5.H = ASHIFT R5.L BY R7.L; +R6.H = ASHIFT R6.L BY R7.L; +R7.H = ASHIFT R7.L BY R7.L; +CHECKREG r0, 0xffffa001; +CHECKREG r1, 0xffffa001; +CHECKREG r2, 0xffffa002; +CHECKREG r3, 0xffffa003; +CHECKREG r4, 0xffffa004; +CHECKREG r5, 0xffffa005; +CHECKREG r6, 0xffffa006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R4.L; +R1.H = ASHIFT R1.H BY R4.L; +R2.H = ASHIFT R2.H BY R4.L; +R3.H = ASHIFT R3.H BY R4.L; +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L; +R6.H = ASHIFT R6.H BY R4.L; +R7.H = ASHIFT R7.H BY R4.L; +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0xc0020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R5.L; +R1.H = ASHIFT R1.H BY R5.L; +R2.H = ASHIFT R2.H BY R5.L; +R3.H = ASHIFT R3.H BY R5.L; +R4.H = ASHIFT R4.H BY R5.L; +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L; +R7.H = ASHIFT R7.H BY R5.L; +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +CHECKREG r4, 0xc0020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = ASHIFT R0.H BY R6.L; +R1.L = ASHIFT R1.H BY R6.L; +R2.L = ASHIFT R2.H BY R6.L; +R3.L = ASHIFT R3.H BY R6.L; +R4.L = ASHIFT R4.H BY R6.L; +R5.L = ASHIFT R5.H BY R6.L; +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0xd001ffff; +CHECKREG r1, 0xd001ffff; +CHECKREG r2, 0xd002ffff; +CHECKREG r3, 0xd003ffff; +CHECKREG r4, 0xd004ffff; +CHECKREG r5, 0xd005ffff; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0xd007ffff; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L; +R1.H = ASHIFT R1.H BY R7.L; +R2.H = ASHIFT R2.H BY R7.L; +R3.H = ASHIFT R3.H BY R7.L; +R4.H = ASHIFT R4.H BY R7.L; +R5.H = ASHIFT R5.H BY R7.L; +R6.H = ASHIFT R6.H BY R7.L; +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0xffff0000; +CHECKREG r1, 0xffff0000; +CHECKREG r2, 0xffff0000; +CHECKREG r3, 0xffff0000; +CHECKREG r4, 0xffff0000; +CHECKREG r5, 0xffff0000; +CHECKREG r6, 0xffff0000; +//CHECKREG r7, -16; +pass diff --git a/tests/tcg/bfin/c_dsp32shift_ahalf_rn_s.s b/tests/tcg/bfin/c_dsp32shift_ahalf_rn_s.s new file mode 100644 index 0000000000000..503671e2de288 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_ahalf_rn_s.s @@ -0,0 +1,424 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rn_s/c_dsp32shift_ahalf_rn_s.dsp +// Spec Reference: dsp32shift ashift s +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L (S); +R2.L = ASHIFT R2.L BY R0.L (S); +R3.L = ASHIFT R3.L BY R0.L (S); +R4.L = ASHIFT R4.L BY R0.L (S); +R5.L = ASHIFT R5.L BY R0.L (S); +R6.L = ASHIFT R6.L BY R0.L (S); +R7.L = ASHIFT R7.L BY R0.L (S); +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c000; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R1.L (S); +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L (S); +R3.L = ASHIFT R3.L BY R1.L (S); +R4.L = ASHIFT R4.L BY R1.L (S); +R5.L = ASHIFT R5.L BY R1.L (S); +R6.L = ASHIFT R6.L BY R1.L (S); +R7.L = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0x0000c000; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +R2.L = -15; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R2.L (S); +R1.L = ASHIFT R1.L BY R2.L (S); +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L (S); +R4.L = ASHIFT R4.L BY R2.L (S); +R5.L = ASHIFT R5.L BY R2.L (S); +R6.L = ASHIFT R6.L BY R2.L (S); +R7.L = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x0000ffff; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R3.L (S); +R1.L = ASHIFT R1.L BY R3.L (S); +R2.L = ASHIFT R2.L BY R3.L (S); +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L (S); +R5.L = ASHIFT R5.L BY R3.L (S); +R6.L = ASHIFT R6.L BY R3.L (S); +R7.L = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +CHECKREG r2, 0x0000ffff; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R0.L (S); +R1.L = ASHIFT R1.H BY R0.L (S); +R2.L = ASHIFT R2.H BY R0.L (S); +R3.L = ASHIFT R3.H BY R0.L (S); +R4.L = ASHIFT R4.H BY R0.L (S); +R5.L = ASHIFT R5.H BY R0.L (S); +R6.L = ASHIFT R6.H BY R0.L (S); +R7.L = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80018001; +CHECKREG r2, 0x80028002; +CHECKREG r3, 0x80038003; +CHECKREG r4, 0x80048004; +CHECKREG r5, 0x80058005; +CHECKREG r6, 0x80068006; +CHECKREG r7, 0x80078007; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R1.L (S); +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L (S); +R3.L = ASHIFT R3.H BY R1.L (S); +R4.L = ASHIFT R4.H BY R1.L (S); +R5.L = ASHIFT R5.H BY R1.L (S); +R6.L = ASHIFT R6.H BY R1.L (S); +R7.L = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x8001c000; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x8002c001; +CHECKREG r3, 0x8003c001; +CHECKREG r4, 0x8004c002; +CHECKREG r5, 0x8005c002; +CHECKREG r6, 0x8006c003; +CHECKREG r7, 0x8007c003; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0xa001ffff; +CHECKREG r1, 0xa001ffff; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0xa003ffff; +CHECKREG r4, 0xa004ffff; +CHECKREG r5, 0xa005ffff; +CHECKREG r6, 0xa006ffff; +CHECKREG r7, 0xa007ffff; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R0.L = ASHIFT R0.H BY R3.L (S); +R1.L = ASHIFT R1.H BY R3.L (S); +R2.L = ASHIFT R2.H BY R3.L (S); +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L (S); +R5.L = ASHIFT R5.H BY R3.L (S); +R6.L = ASHIFT R6.H BY R3.L (S); +R7.L = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0xb001ffff; +CHECKREG r1, 0xb001ffff; +CHECKREG r2, 0xb002ffff; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0xb004ffff; +CHECKREG r5, 0xb005ffff; +CHECKREG r6, 0xb006ffff; +CHECKREG r7, 0xb007ffff; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L (S); +R1.H = ASHIFT R1.L BY R4.L (S); +R2.H = ASHIFT R2.L BY R4.L (S); +R3.H = ASHIFT R3.L BY R4.L (S); +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L (S); +R6.H = ASHIFT R6.L BY R4.L (S); +R7.H = ASHIFT R7.L BY R4.L (S); +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = ASHIFT R0.L BY R5.L (S); +R1.H = ASHIFT R1.L BY R5.L (S); +R2.H = ASHIFT R2.L BY R5.L (S); +R3.H = ASHIFT R3.L BY R5.L (S); +R4.H = ASHIFT R4.L BY R5.L (S); +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L (S); +R7.H = ASHIFT R7.L BY R5.L (S); +CHECKREG r0, 0xc0008001; +CHECKREG r1, 0xc0008001; +CHECKREG r2, 0xc0018002; +CHECKREG r3, 0xc0018003; +CHECKREG r4, 0xc0028004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0xc0038006; +CHECKREG r7, 0xc0038007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = ASHIFT R0.L BY R6.L (S); +R1.H = ASHIFT R1.L BY R6.L (S); +R2.H = ASHIFT R2.L BY R6.L (S); +R3.H = ASHIFT R3.L BY R6.L (S); +R4.H = ASHIFT R4.L BY R6.L (S); +R5.H = ASHIFT R5.L BY R6.L (S); +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0xffff9001; +CHECKREG r1, 0xffff9001; +CHECKREG r2, 0xffff9002; +CHECKREG r3, 0xffff9003; +CHECKREG r4, 0xffff9004; +CHECKREG r5, 0xffff9005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0xffff9007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L (S); +R1.H = ASHIFT R1.L BY R7.L (S); +R2.H = ASHIFT R2.L BY R7.L (S); +R3.H = ASHIFT R3.L BY R7.L (S); +R4.H = ASHIFT R4.L BY R7.L (S); +R5.H = ASHIFT R5.L BY R7.L (S); +R6.H = ASHIFT R6.L BY R7.L (S); +R7.H = ASHIFT R7.L BY R7.L (S); +CHECKREG r0, 0xffffa001; +CHECKREG r1, 0xffffa001; +CHECKREG r2, 0xffffa002; +CHECKREG r3, 0xffffa003; +CHECKREG r4, 0xffffa004; +CHECKREG r5, 0xffffa005; +CHECKREG r6, 0xffffa006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R4.L (S); +R1.H = ASHIFT R1.H BY R4.L (S); +R2.H = ASHIFT R2.H BY R4.L (S); +R3.H = ASHIFT R3.H BY R4.L (S); +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L (S); +R6.H = ASHIFT R6.H BY R4.L (S); +R7.H = ASHIFT R7.H BY R4.L (S); +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0xc0020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R5.L (S); +R1.H = ASHIFT R1.H BY R5.L (S); +R2.H = ASHIFT R2.H BY R5.L (S); +R3.H = ASHIFT R3.H BY R5.L (S); +R4.H = ASHIFT R4.H BY R5.L (S); +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L (S); +R7.H = ASHIFT R7.H BY R5.L (S); +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +CHECKREG r4, 0xc0020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = ASHIFT R0.H BY R6.L (S); +R1.L = ASHIFT R1.H BY R6.L (S); +R2.L = ASHIFT R2.H BY R6.L (S); +R3.L = ASHIFT R3.H BY R6.L (S); +R4.L = ASHIFT R4.H BY R6.L (S); +R5.L = ASHIFT R5.H BY R6.L (S); +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0xd001ffff; +CHECKREG r1, 0xd001ffff; +CHECKREG r2, 0xd002ffff; +CHECKREG r3, 0xd003ffff; +CHECKREG r4, 0xd004ffff; +CHECKREG r5, 0xd005ffff; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0xd007ffff; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L (S); +R1.H = ASHIFT R1.H BY R7.L (S); +R2.H = ASHIFT R2.H BY R7.L (S); +R3.H = ASHIFT R3.H BY R7.L (S); +R4.H = ASHIFT R4.H BY R7.L (S); +R5.H = ASHIFT R5.H BY R7.L (S); +R6.H = ASHIFT R6.H BY R7.L (S); +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0xffff0000; +CHECKREG r1, 0xffff0000; +CHECKREG r2, 0xffff0000; +CHECKREG r3, 0xffff0000; +CHECKREG r4, 0xffff0000; +CHECKREG r5, 0xffff0000; +CHECKREG r6, 0xffff0000; +//CHECKREG r7, -16; + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_ahalf_rp.s b/tests/tcg/bfin/c_dsp32shift_ahalf_rp.s new file mode 100644 index 0000000000000..e3480d5aa8854 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_ahalf_rp.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rp/c_dsp32shift_ahalf_rp.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000800; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00001001; +CHECKREG r3, 0x00001801; +CHECKREG r4, 0x00002002; +CHECKREG r5, 0x00002802; +CHECKREG r6, 0x00003003; +CHECKREG r7, 0x00003803; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +R2.L = -15; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00002002; +R3.L = -16; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x10010800; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +R2.L = -15; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010001; +imm32 r1, 0x10010001; +imm32 r2, 0x20020002; +R3.L = -16; +imm32 r4, 0x40040004; +imm32 r5, 0x50050005; +imm32 r6, 0x60060006; +imm32 r7, 0x70070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L; +R1.H = ASHIFT R1.L BY R4.L; +R2.H = ASHIFT R2.L BY R4.L; +R3.H = ASHIFT R3.L BY R4.L; +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L; +R6.H = ASHIFT R6.L BY R4.L; +R7.H = ASHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R5.L; +R1.H = ASHIFT R1.L BY R5.L; +R2.H = ASHIFT R2.L BY R5.L; +R3.H = ASHIFT R3.L BY R5.L; +R4.H = ASHIFT R4.L BY R5.L; +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L; +R7.H = ASHIFT R7.L BY R5.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00010002; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x00030006; +CHECKREG r7, 0x00030007; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r1, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = ASHIFT R0.L BY R6.L; +R1.H = ASHIFT R1.L BY R6.L; +R2.H = ASHIFT R2.L BY R6.L; +R3.H = ASHIFT R3.L BY R6.L; +R4.H = ASHIFT R4.L BY R6.L; +R5.H = ASHIFT R5.L BY R6.L; +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x00001001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L; +R1.H = ASHIFT R1.L BY R7.L; +R2.H = ASHIFT R2.L BY R7.L; +R3.H = ASHIFT R3.L BY R7.L; +R4.H = ASHIFT R4.L BY R7.L; +R5.H = ASHIFT R5.L BY R7.L; +R6.H = ASHIFT R6.L BY R7.L; +R7.H = ASHIFT R7.L BY R7.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002001; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x00006006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +R4.L = -1; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R4.L; +R1.H = ASHIFT R1.H BY R4.L; +R2.H = ASHIFT R2.H BY R4.L; +R3.H = ASHIFT R3.H BY R4.L; +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L; +R6.H = ASHIFT R6.H BY R4.L; +R7.H = ASHIFT R7.H BY R4.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x00020000; +CHECKREG r6, 0x00030000; +CHECKREG r7, 0x00030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = ASHIFT R0.H BY R5.L; +R1.H = ASHIFT R1.H BY R5.L; +R2.H = ASHIFT R2.H BY R5.L; +R3.H = ASHIFT R3.H BY R5.L; +R4.H = ASHIFT R4.H BY R5.L; +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L; +R7.H = ASHIFT R7.H BY R5.L; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x10010000; +CHECKREG r3, 0x18010000; +CHECKREG r4, 0x20020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x30030000; +CHECKREG r7, 0x38030000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R6.L; +R1.L = ASHIFT R1.H BY R6.L; +R2.L = ASHIFT R2.H BY R6.L; +R3.L = ASHIFT R3.H BY R6.L; +R4.L = ASHIFT R4.H BY R6.L; +R5.L = ASHIFT R5.H BY R6.L; +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L; +R1.H = ASHIFT R1.H BY R7.L; +R2.H = ASHIFT R2.H BY R7.L; +R3.H = ASHIFT R3.H BY R7.L; +R4.H = ASHIFT R4.H BY R7.L; +R5.H = ASHIFT R5.H BY R7.L; +R6.H = ASHIFT R6.H BY R7.L; +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; +pass diff --git a/tests/tcg/bfin/c_dsp32shift_ahalf_rp_s.s b/tests/tcg/bfin/c_dsp32shift_ahalf_rp_s.s new file mode 100644 index 0000000000000..3e467f228ac67 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_ahalf_rp_s.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rp_s/c_dsp32shift_ahalf_rp_s.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L (S); +R2.L = ASHIFT R2.L BY R0.L (S); +R3.L = ASHIFT R3.L BY R0.L (S); +R4.L = ASHIFT R4.L BY R0.L (S); +R5.L = ASHIFT R5.L BY R0.L (S); +R6.L = ASHIFT R6.L BY R0.L (S); +R7.L = ASHIFT R7.L BY R0.L (S); +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R1.L (S); +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L (S); +R3.L = ASHIFT R3.L BY R1.L (S); +R4.L = ASHIFT R4.L BY R1.L (S); +R5.L = ASHIFT R5.L BY R1.L (S); +R6.L = ASHIFT R6.L BY R1.L (S); +R7.L = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0x00000800; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00001001; +CHECKREG r3, 0x00001801; +CHECKREG r4, 0x00002002; +CHECKREG r5, 0x00002802; +CHECKREG r6, 0x00003003; +CHECKREG r7, 0x00003803; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +R2.L = -15; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R2.L (S); +R1.L = ASHIFT R1.L BY R2.L (S); +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L (S); +R4.L = ASHIFT R4.L BY R2.L (S); +R5.L = ASHIFT R5.L BY R2.L (S); +R6.L = ASHIFT R6.L BY R2.L (S); +R7.L = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00002002; +R3.L = -16; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R3.L (S); +R1.L = ASHIFT R1.L BY R3.L (S); +R2.L = ASHIFT R2.L BY R3.L (S); +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L (S); +R5.L = ASHIFT R5.L BY R3.L (S); +R6.L = ASHIFT R6.L BY R3.L (S); +R7.L = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L (S); +R1.L = ASHIFT R1.H BY R0.L (S); +R2.L = ASHIFT R2.H BY R0.L (S); +R3.L = ASHIFT R3.H BY R0.L (S); +R4.L = ASHIFT R4.H BY R0.L (S); +R5.L = ASHIFT R5.H BY R0.L (S); +R6.L = ASHIFT R6.H BY R0.L (S); +R7.L = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R1.L (S); +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L (S); +R3.L = ASHIFT R3.H BY R1.L (S); +R4.L = ASHIFT R4.H BY R1.L (S); +R5.L = ASHIFT R5.H BY R1.L (S); +R6.L = ASHIFT R6.H BY R1.L (S); +R7.L = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x10010800; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +R2.L = -15; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010001; +imm32 r1, 0x10010001; +imm32 r2, 0x20020002; +R3.L = -16; +imm32 r4, 0x40040004; +imm32 r5, 0x50050005; +imm32 r6, 0x60060006; +imm32 r7, 0x70070007; +R0.L = ASHIFT R0.H BY R3.L (S); +R1.L = ASHIFT R1.H BY R3.L (S); +R2.L = ASHIFT R2.H BY R3.L (S); +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L (S); +R5.L = ASHIFT R5.H BY R3.L (S); +R6.L = ASHIFT R6.H BY R3.L (S); +R7.L = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +// d_hi = ashift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L (S); +R1.H = ASHIFT R1.L BY R4.L (S); +R2.H = ASHIFT R2.L BY R4.L (S); +R3.H = ASHIFT R3.L BY R4.L (S); +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L (S); +R6.H = ASHIFT R6.L BY R4.L (S); +R7.H = ASHIFT R7.L BY R4.L (S); +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R5.L (S); +R1.H = ASHIFT R1.L BY R5.L (S); +R2.H = ASHIFT R2.L BY R5.L (S); +R3.H = ASHIFT R3.L BY R5.L (S); +R4.H = ASHIFT R4.L BY R5.L (S); +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L (S); +R7.H = ASHIFT R7.L BY R5.L (S); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00010002; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x00030006; +CHECKREG r7, 0x00030007; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r1, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = ASHIFT R0.L BY R6.L (S); +R1.H = ASHIFT R1.L BY R6.L (S); +R2.H = ASHIFT R2.L BY R6.L (S); +R3.H = ASHIFT R3.L BY R6.L (S); +R4.H = ASHIFT R4.L BY R6.L (S); +R5.H = ASHIFT R5.L BY R6.L (S); +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x00001001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L (S); +R1.H = ASHIFT R1.L BY R7.L (S); +R2.H = ASHIFT R2.L BY R7.L (S); +R3.H = ASHIFT R3.L BY R7.L (S); +R4.H = ASHIFT R4.L BY R7.L (S); +R5.H = ASHIFT R5.L BY R7.L (S); +R6.H = ASHIFT R6.L BY R7.L (S); +R7.H = ASHIFT R7.L BY R7.L (S); +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002001; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x00006006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +R4.L = -1; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R4.L (S); +R1.H = ASHIFT R1.H BY R4.L (S); +R2.H = ASHIFT R2.H BY R4.L (S); +R3.H = ASHIFT R3.H BY R4.L (S); +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L (S); +R6.H = ASHIFT R6.H BY R4.L (S); +R7.H = ASHIFT R7.H BY R4.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x00020000; +CHECKREG r6, 0x00030000; +CHECKREG r7, 0x00030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = ASHIFT R0.H BY R5.L (S); +R1.H = ASHIFT R1.H BY R5.L (S); +R2.H = ASHIFT R2.H BY R5.L (S); +R3.H = ASHIFT R3.H BY R5.L (S); +R4.H = ASHIFT R4.H BY R5.L (S); +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L (S); +R7.H = ASHIFT R7.H BY R5.L (S); +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x10010000; +CHECKREG r3, 0x18010000; +CHECKREG r4, 0x20020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x30030000; +CHECKREG r7, 0x38030000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R6.L (S); +R1.L = ASHIFT R1.H BY R6.L (S); +R2.L = ASHIFT R2.H BY R6.L (S); +R3.L = ASHIFT R3.H BY R6.L (S); +R4.L = ASHIFT R4.H BY R6.L (S); +R5.L = ASHIFT R5.H BY R6.L (S); +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L (S); +R1.H = ASHIFT R1.H BY R7.L (S); +R2.H = ASHIFT R2.H BY R7.L (S); +R3.H = ASHIFT R3.H BY R7.L (S); +R4.H = ASHIFT R4.H BY R7.L (S); +R5.H = ASHIFT R5.H BY R7.L (S); +R6.H = ASHIFT R6.H BY R7.L (S); +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; +pass diff --git a/tests/tcg/bfin/c_dsp32shift_align16.s b/tests/tcg/bfin/c_dsp32shift_align16.s new file mode 100644 index 0000000000000..a6fd2841036a3 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_align16.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_align16/c_dsp32shift_align16.dsp +// Spec Reference: dsp32shift align16 +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = ALIGN16 ( R1 , R0 ); +R2 = ALIGN16 ( R2 , R0 ); +R3 = ALIGN16 ( R3 , R0 ); +R4 = ALIGN16 ( R4 , R0 ); +R5 = ALIGN16 ( R5 , R0 ); +R6 = ALIGN16 ( R6 , R0 ); +R7 = ALIGN16 ( R7 , R0 ); +R0 = ALIGN16 ( R0 , R0 ); +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x08010000; +CHECKREG r2, 0x08020000; +CHECKREG r3, 0x08030000; +CHECKREG r4, 0x48040000; +CHECKREG r5, 0x05050000; +CHECKREG r6, 0x08660000; +CHECKREG r7, 0x08070000; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09400002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = ALIGN16 ( R0 , R1 ); +R2 = ALIGN16 ( R2 , R1 ); +R3 = ALIGN16 ( R3 , R1 ); +R4 = ALIGN16 ( R4 , R1 ); +R5 = ALIGN16 ( R5 , R1 ); +R6 = ALIGN16 ( R6 , R1 ); +R7 = ALIGN16 ( R7 , R1 ); +R1 = ALIGN16 ( R1 , R1 ); +CHECKREG r0, 0xD0010900; +CHECKREG r1, 0x00020900; +CHECKREG r2, 0x00020900; +CHECKREG r3, 0x00030900; +CHECKREG r4, 0x00040900; +CHECKREG r5, 0x30050900; +CHECKREG r6, 0x04060900; +CHECKREG r7, 0x00570900; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a400010; +imm32 r4, 0x0a05e004; +imm32 r5, 0x0a006005; +imm32 r6, 0x0a00e706; +imm32 r7, 0x0a00e087; +R0 = ALIGN16 ( R0 , R2 ); +R1 = ALIGN16 ( R1 , R2 ); +R3 = ALIGN16 ( R3 , R2 ); +R4 = ALIGN16 ( R4 , R2 ); +R5 = ALIGN16 ( R5 , R2 ); +R6 = ALIGN16 ( R6 , R2 ); +R7 = ALIGN16 ( R7 , R2 ); +R2 = ALIGN16 ( R2 , R2 ); +CHECKREG r0, 0xE0010A00; +CHECKREG r1, 0xE0010A00; +CHECKREG r2, 0x000F0A00; +CHECKREG r3, 0x00100A00; +CHECKREG r4, 0xE0040A00; +CHECKREG r5, 0x60050A00; +CHECKREG r6, 0xE7060A00; +CHECKREG r7, 0xE0870A00; + +imm32 r0, 0x2b00f001; +imm32 r1, 0x0300f001; +imm32 r2, 0x0b40f002; +imm32 r3, 0x0b050010; +imm32 r4, 0x0b006004; +imm32 r5, 0x0b00f705; +imm32 r6, 0x0b00f086; +imm32 r7, 0x0b00f009; +R0 = ALIGN16 ( R0 , R3 ); +R1 = ALIGN16 ( R1 , R3 ); +R2 = ALIGN16 ( R2 , R3 ); +R4 = ALIGN16 ( R4 , R3 ); +R5 = ALIGN16 ( R5 , R3 ); +R6 = ALIGN16 ( R6 , R3 ); +R7 = ALIGN16 ( R7 , R3 ); +R3 = ALIGN16 ( R3 , R3 ); +CHECKREG r0, 0xF0010B05; +CHECKREG r1, 0xF0010B05; +CHECKREG r2, 0xF0020B05; +CHECKREG r3, 0x00100B05; +CHECKREG r4, 0x60040B05; +CHECKREG r5, 0xF7050B05; +CHECKREG r6, 0xF0860B05; +CHECKREG r7, 0xF0090B05; + +imm32 r0, 0x4c0000c0; +imm32 r1, 0x050100c0; +imm32 r2, 0x0c6200c0; +imm32 r3, 0x0c0700c0; +imm32 r4, 0x0c04800c; +imm32 r5, 0x0c0509c0; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c0700ca; +R0 = ALIGN16 ( R0 , R4 ); +R1 = ALIGN16 ( R1 , R4 ); +R2 = ALIGN16 ( R2 , R4 ); +R3 = ALIGN16 ( R3 , R4 ); +R5 = ALIGN16 ( R5 , R4 ); +R6 = ALIGN16 ( R6 , R4 ); +R7 = ALIGN16 ( R7 , R4 ); +R4 = ALIGN16 ( R4 , R4 ); +CHECKREG r0, 0x00C00C04; +CHECKREG r1, 0x00C00C04; +CHECKREG r2, 0x00C00C04; +CHECKREG r3, 0x00C00C04; +CHECKREG r4, 0x800C0C04; +CHECKREG r5, 0x09C00C04; +CHECKREG r6, 0x00000C04; +CHECKREG r7, 0x00CA0C04; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = ALIGN16 ( R0 , R5 ); +R1 = ALIGN16 ( R1 , R5 ); +R2 = ALIGN16 ( R2 , R5 ); +R3 = ALIGN16 ( R3 , R5 ); +R4 = ALIGN16 ( R4 , R5 ); +R6 = ALIGN16 ( R6 , R5 ); +R7 = ALIGN16 ( R7 , R5 ); +R5 = ALIGN16 ( R5 , R5 ); +CHECKREG r0, 0x00D0A005; +CHECKREG r1, 0x00D1A005; +CHECKREG r2, 0x00D0A005; +CHECKREG r3, 0x00D0A005; +CHECKREG r4, 0x00D0A005; +CHECKREG r5, 0x0007A005; +CHECKREG r6, 0x00D0A005; +CHECKREG r7, 0x00D0A005; + +imm32 r0, 0xb2010000; +imm32 r1, 0xb0310000; +imm32 r2, 0xb042000f; +imm32 r3, 0xbf030000; +imm32 r4, 0xba040000; +imm32 r5, 0xbb050000; +imm32 r6, 0xbc060009; +imm32 r7, 0xb0e70000; +R0 = ALIGN16 ( R0 , R6 ); +R1 = ALIGN16 ( R1 , R6 ); +R2 = ALIGN16 ( R2 , R6 ); +R3 = ALIGN16 ( R3 , R6 ); +R4 = ALIGN16 ( R4 , R6 ); +R5 = ALIGN16 ( R5 , R6 ); +R6 = ALIGN16 ( R6 , R6 ); +R7 = ALIGN16 ( R7 , R6 ); +CHECKREG r0, 0x0000BC06; +CHECKREG r1, 0x0000BC06; +CHECKREG r2, 0x000FBC06; +CHECKREG r3, 0x0000BC06; +CHECKREG r4, 0x0000BC06; +CHECKREG r5, 0x0000BC06; +CHECKREG r6, 0x0009BC06; +CHECKREG r7, 0x00000009; + +imm32 r0, 0xd23100e0; +imm32 r1, 0xd04500e0; +imm32 r2, 0xde32f0e0; +imm32 r3, 0xd90300e0; +imm32 r4, 0xd07400e0; +imm32 r5, 0xdef500e0; +imm32 r6, 0xd06600e0; +imm32 r7, 0xd0080023; +R1 = ALIGN16 ( R0 , R7 ); +R2 = ALIGN16 ( R1 , R7 ); +R3 = ALIGN16 ( R2 , R7 ); +R4 = ALIGN16 ( R3 , R7 ); +R5 = ALIGN16 ( R4 , R7 ); +R6 = ALIGN16 ( R5 , R7 ); +R7 = ALIGN16 ( R6 , R7 ); +R0 = ALIGN16 ( R7 , R7 ); +CHECKREG r0, 0xD008D008; +CHECKREG r1, 0x00E0D008; +CHECKREG r2, 0xD008D008; +CHECKREG r3, 0xD008D008; +CHECKREG r4, 0xD008D008; +CHECKREG r5, 0xD008D008; +CHECKREG r6, 0xD008D008; +CHECKREG r7, 0xD008D008; + + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_align24.s b/tests/tcg/bfin/c_dsp32shift_align24.s new file mode 100644 index 0000000000000..bc33c581d42e4 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_align24.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp +// Spec Reference: dsp32shift align24 +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = ALIGN24 ( R1 , R0 ); +R2 = ALIGN24 ( R2 , R0 ); +R3 = ALIGN24 ( R3 , R0 ); +R4 = ALIGN24 ( R4 , R0 ); +R5 = ALIGN24 ( R5 , R0 ); +R6 = ALIGN24 ( R6 , R0 ); +R7 = ALIGN24 ( R7 , R0 ); +R0 = ALIGN24 ( R0 , R0 ); +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x00080100; +CHECKREG r2, 0x20080200; +CHECKREG r3, 0x03080300; +CHECKREG r4, 0x00480400; +CHECKREG r5, 0x00050500; +CHECKREG r6, 0x00086600; +CHECKREG r7, 0x00080700; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09400002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = ALIGN24 ( R0 , R1 ); +R2 = ALIGN24 ( R2 , R1 ); +R3 = ALIGN24 ( R3 , R1 ); +R4 = ALIGN24 ( R4 , R1 ); +R5 = ALIGN24 ( R5 , R1 ); +R6 = ALIGN24 ( R6 , R1 ); +R7 = ALIGN24 ( R7 , R1 ); +R1 = ALIGN24 ( R1 , R1 ); +CHECKREG r0, 0x00D00109; +CHECKREG r1, 0x00000209; +CHECKREG r2, 0x40000209; +CHECKREG r3, 0x10000309; +CHECKREG r4, 0x02000409; +CHECKREG r5, 0x00300509; +CHECKREG r6, 0x00040609; +CHECKREG r7, 0x00005709; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a400010; +imm32 r4, 0x0a05e004; +imm32 r5, 0x0a006005; +imm32 r6, 0x0a00e706; +imm32 r7, 0x0a00e087; +R0 = ALIGN24 ( R0 , R2 ); +R1 = ALIGN24 ( R1 , R2 ); +R3 = ALIGN24 ( R3 , R2 ); +R4 = ALIGN24 ( R4 , R2 ); +R5 = ALIGN24 ( R5 , R2 ); +R6 = ALIGN24 ( R6 , R2 ); +R7 = ALIGN24 ( R7 , R2 ); +R2 = ALIGN24 ( R2 , R2 ); +CHECKREG r0, 0x00E0010A; +CHECKREG r1, 0x00E0010A; +CHECKREG r2, 0x00000F0A; +CHECKREG r3, 0x4000100A; +CHECKREG r4, 0x05E0040A; +CHECKREG r5, 0x0060050A; +CHECKREG r6, 0x00E7060A; +CHECKREG r7, 0x00E0870A; + +imm32 r0, 0x2b00f001; +imm32 r1, 0x0300f001; +imm32 r2, 0x0b40f002; +imm32 r3, 0x0b050010; +imm32 r4, 0x0b006004; +imm32 r5, 0x0b00f705; +imm32 r6, 0x0b00f086; +imm32 r7, 0x0b00f009; +R0 = ALIGN24 ( R0 , R3 ); +R1 = ALIGN24 ( R1 , R3 ); +R2 = ALIGN24 ( R2 , R3 ); +R4 = ALIGN24 ( R4 , R3 ); +R5 = ALIGN24 ( R5 , R3 ); +R6 = ALIGN24 ( R6 , R3 ); +R7 = ALIGN24 ( R7 , R3 ); +R3 = ALIGN24 ( R3 , R3 ); +CHECKREG r0, 0x00F0010B; +CHECKREG r1, 0x00F0010B; +CHECKREG r2, 0x40F0020B; +CHECKREG r3, 0x0500100B; +CHECKREG r4, 0x0060040B; +CHECKREG r5, 0x00F7050B; +CHECKREG r6, 0x00F0860B; +CHECKREG r7, 0x00F0090B; + +imm32 r0, 0x4c0000c0; +imm32 r1, 0x050100c0; +imm32 r2, 0x0c6200c0; +imm32 r3, 0x0c0700c0; +imm32 r4, 0x0c04800c; +imm32 r5, 0x0c0509c0; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c0700ca; +R0 = ALIGN24 ( R0 , R4 ); +R1 = ALIGN24 ( R1 , R4 ); +R2 = ALIGN24 ( R2 , R4 ); +R3 = ALIGN24 ( R3 , R4 ); +R5 = ALIGN24 ( R5 , R4 ); +R6 = ALIGN24 ( R6 , R4 ); +R7 = ALIGN24 ( R7 , R4 ); +R4 = ALIGN24 ( R4 , R4 ); +CHECKREG r0, 0x0000C00C; +CHECKREG r1, 0x0100C00C; +CHECKREG r2, 0x6200C00C; +CHECKREG r3, 0x0700C00C; +CHECKREG r4, 0x04800C0C; +CHECKREG r5, 0x0509C00C; +CHECKREG r6, 0x0600000C; +CHECKREG r7, 0x0700CA0C; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = ALIGN24 ( R0 , R5 ); +R1 = ALIGN24 ( R1 , R5 ); +R2 = ALIGN24 ( R2 , R5 ); +R3 = ALIGN24 ( R3 , R5 ); +R4 = ALIGN24 ( R4 , R5 ); +R6 = ALIGN24 ( R6 , R5 ); +R7 = ALIGN24 ( R7 , R5 ); +R5 = ALIGN24 ( R5 , R5 ); +CHECKREG r0, 0x0100D0A0; +CHECKREG r1, 0x0100D1A0; +CHECKREG r2, 0x0200D0A0; +CHECKREG r3, 0x0300D0A0; +CHECKREG r4, 0x0400D0A0; +CHECKREG r5, 0x050007A0; +CHECKREG r6, 0x0600D0A0; +CHECKREG r7, 0x0700D0A0; + +imm32 r0, 0xb2010000; +imm32 r1, 0xb0310000; +imm32 r2, 0xb042000f; +imm32 r3, 0xbf030000; +imm32 r4, 0xba040000; +imm32 r5, 0xbb050000; +imm32 r6, 0xbc060009; +imm32 r7, 0xb0e70000; +R0 = ALIGN24 ( R0 , R6 ); +R1 = ALIGN24 ( R1 , R6 ); +R2 = ALIGN24 ( R2 , R6 ); +R3 = ALIGN24 ( R3 , R6 ); +R4 = ALIGN24 ( R4 , R6 ); +R5 = ALIGN24 ( R5 , R6 ); +R6 = ALIGN24 ( R6 , R6 ); +R7 = ALIGN24 ( R7 , R6 ); +CHECKREG r0, 0x010000BC; +CHECKREG r1, 0x310000BC; +CHECKREG r2, 0x42000FBC; +CHECKREG r3, 0x030000BC; +CHECKREG r4, 0x040000BC; +CHECKREG r5, 0x050000BC; +CHECKREG r6, 0x060009BC; +CHECKREG r7, 0xE7000006; + +imm32 r0, 0xd23100e0; +imm32 r1, 0xd04500e0; +imm32 r2, 0xde32f0e0; +imm32 r3, 0xd90300e0; +imm32 r4, 0xd07400e0; +imm32 r5, 0xdef500e0; +imm32 r6, 0xd06600e0; +imm32 r7, 0xd0080023; +R1 = ALIGN24 ( R0 , R7 ); +R2 = ALIGN24 ( R1 , R7 ); +R3 = ALIGN24 ( R2 , R7 ); +R4 = ALIGN24 ( R3 , R7 ); +R5 = ALIGN24 ( R4 , R7 ); +R6 = ALIGN24 ( R5 , R7 ); +R7 = ALIGN24 ( R6 , R7 ); +R0 = ALIGN24 ( R7 , R7 ); +CHECKREG r0, 0xD0D0D0D0; +CHECKREG r1, 0x3100E0D0; +CHECKREG r2, 0x00E0D0D0; +CHECKREG r3, 0xE0D0D0D0; +CHECKREG r4, 0xD0D0D0D0; +CHECKREG r5, 0xD0D0D0D0; +CHECKREG r6, 0xD0D0D0D0; +CHECKREG r7, 0xD0D0D0D0; + + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_align8.s b/tests/tcg/bfin/c_dsp32shift_align8.s new file mode 100644 index 0000000000000..ce1f82bee248d --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_align8.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_align8/c_dsp32shift_align8.dsp +// Spec Reference: dsp32shift align8 +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = ALIGN8 ( R1 , R0 ); +R2 = ALIGN8 ( R2 , R0 ); +R3 = ALIGN8 ( R3 , R0 ); +R4 = ALIGN8 ( R4 , R0 ); +R5 = ALIGN8 ( R5 , R0 ); +R6 = ALIGN8 ( R6 , R0 ); +R7 = ALIGN8 ( R7 , R0 ); +R0 = ALIGN8 ( R0 , R0 ); +CHECKREG r0, 0x01000000; +CHECKREG r1, 0x01000000; +CHECKREG r2, 0x02000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x04000000; +CHECKREG r5, 0x05000000; +CHECKREG r6, 0x66000000; +CHECKREG r7, 0x07000000; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09400002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = ALIGN8 ( R0 , R1 ); +R2 = ALIGN8 ( R2 , R1 ); +R3 = ALIGN8 ( R3 , R1 ); +R4 = ALIGN8 ( R4 , R1 ); +R5 = ALIGN8 ( R5 , R1 ); +R6 = ALIGN8 ( R6 , R1 ); +R7 = ALIGN8 ( R7 , R1 ); +R1 = ALIGN8 ( R1 , R1 ); +CHECKREG r0, 0x01090000; +CHECKREG r1, 0x02090000; +CHECKREG r2, 0x02090000; +CHECKREG r3, 0x03090000; +CHECKREG r4, 0x04090000; +CHECKREG r5, 0x05090000; +CHECKREG r6, 0x06090000; +CHECKREG r7, 0x57090000; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a400010; +imm32 r4, 0x0a05e004; +imm32 r5, 0x0a006005; +imm32 r6, 0x0a00e706; +imm32 r7, 0x0a00e087; +R0 = ALIGN8 ( R0 , R2 ); +R1 = ALIGN8 ( R1 , R2 ); +R3 = ALIGN8 ( R3 , R2 ); +R4 = ALIGN8 ( R4 , R2 ); +R5 = ALIGN8 ( R5 , R2 ); +R6 = ALIGN8 ( R6 , R2 ); +R7 = ALIGN8 ( R7 , R2 ); +R2 = ALIGN8 ( R2 , R2 ); +CHECKREG r0, 0x010A0000; +CHECKREG r1, 0x010A0000; +CHECKREG r2, 0x0F0A0000; +CHECKREG r3, 0x100A0000; +CHECKREG r4, 0x040A0000; +CHECKREG r5, 0x050A0000; +CHECKREG r6, 0x060A0000; +CHECKREG r7, 0x870A0000; + +imm32 r0, 0x2b00f001; +imm32 r1, 0x0300f001; +imm32 r2, 0x0b40f002; +imm32 r3, 0x0b050010; +imm32 r4, 0x0b006004; +imm32 r5, 0x0b00f705; +imm32 r6, 0x0b00f086; +imm32 r7, 0x0b00f009; +R0 = ALIGN8 ( R0 , R3 ); +R1 = ALIGN8 ( R1 , R3 ); +R2 = ALIGN8 ( R2 , R3 ); +R4 = ALIGN8 ( R4 , R3 ); +R5 = ALIGN8 ( R5 , R3 ); +R6 = ALIGN8 ( R6 , R3 ); +R7 = ALIGN8 ( R7 , R3 ); +R3 = ALIGN8 ( R3 , R3 ); +CHECKREG r0, 0x010B0500; +CHECKREG r1, 0x010B0500; +CHECKREG r2, 0x020B0500; +CHECKREG r3, 0x100B0500; +CHECKREG r4, 0x040B0500; +CHECKREG r5, 0x050B0500; +CHECKREG r6, 0x860B0500; +CHECKREG r7, 0x090B0500; + +imm32 r0, 0x4c0000c0; +imm32 r1, 0x050100c0; +imm32 r2, 0x0c6200c0; +imm32 r3, 0x0c0700c0; +imm32 r4, 0x0c04800c; +imm32 r5, 0x0c0509c0; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c0700ca; +R0 = ALIGN8 ( R0 , R4 ); +R1 = ALIGN8 ( R1 , R4 ); +R2 = ALIGN8 ( R2 , R4 ); +R3 = ALIGN8 ( R3 , R4 ); +R5 = ALIGN8 ( R5 , R4 ); +R6 = ALIGN8 ( R6 , R4 ); +R7 = ALIGN8 ( R7 , R4 ); +R4 = ALIGN8 ( R4 , R4 ); +CHECKREG r0, 0xC00C0480; +CHECKREG r1, 0xC00C0480; +CHECKREG r2, 0xC00C0480; +CHECKREG r3, 0xC00C0480; +CHECKREG r4, 0x0C0C0480; +CHECKREG r5, 0xC00C0480; +CHECKREG r6, 0x000C0480; +CHECKREG r7, 0xCA0C0480; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = ALIGN8 ( R0 , R5 ); +R1 = ALIGN8 ( R1 , R5 ); +R2 = ALIGN8 ( R2 , R5 ); +R3 = ALIGN8 ( R3 , R5 ); +R4 = ALIGN8 ( R4 , R5 ); +R6 = ALIGN8 ( R6 , R5 ); +R7 = ALIGN8 ( R7 , R5 ); +R5 = ALIGN8 ( R5 , R5 ); +CHECKREG r0, 0xD0A00500; +CHECKREG r1, 0xD1A00500; +CHECKREG r2, 0xD0A00500; +CHECKREG r3, 0xD0A00500; +CHECKREG r4, 0xD0A00500; +CHECKREG r5, 0x07A00500; +CHECKREG r6, 0xD0A00500; +CHECKREG r7, 0xD0A00500; + +imm32 r0, 0xb2010000; +imm32 r1, 0xb0310000; +imm32 r2, 0xb042000f; +imm32 r3, 0xbf030000; +imm32 r4, 0xba040000; +imm32 r5, 0xbb050000; +imm32 r6, 0xbc060009; +imm32 r7, 0xb0e70000; +R0 = ALIGN8 ( R0 , R6 ); +R1 = ALIGN8 ( R1 , R6 ); +R2 = ALIGN8 ( R2 , R6 ); +R3 = ALIGN8 ( R3 , R6 ); +R4 = ALIGN8 ( R4 , R6 ); +R5 = ALIGN8 ( R5 , R6 ); +R6 = ALIGN8 ( R6 , R6 ); +R7 = ALIGN8 ( R7 , R6 ); +CHECKREG r0, 0x00BC0600; +CHECKREG r1, 0x00BC0600; +CHECKREG r2, 0x0FBC0600; +CHECKREG r3, 0x00BC0600; +CHECKREG r4, 0x00BC0600; +CHECKREG r5, 0x00BC0600; +CHECKREG r6, 0x09BC0600; +CHECKREG r7, 0x0009BC06; + +imm32 r0, 0xd23100e0; +imm32 r1, 0xd04500e0; +imm32 r2, 0xde32f0e0; +imm32 r3, 0xd90300e0; +imm32 r4, 0xd07400e0; +imm32 r5, 0xdef500e0; +imm32 r6, 0xd06600e0; +imm32 r7, 0xd0080023; +R1 = ALIGN8 ( R0 , R7 ); +R2 = ALIGN8 ( R1 , R7 ); +R3 = ALIGN8 ( R2 , R7 ); +R4 = ALIGN8 ( R3 , R7 ); +R5 = ALIGN8 ( R4 , R7 ); +R6 = ALIGN8 ( R5 , R7 ); +R7 = ALIGN8 ( R6 , R7 ); +R0 = ALIGN8 ( R7 , R7 ); +CHECKREG r0, 0x0000D008; +CHECKREG r1, 0xE0D00800; +CHECKREG r2, 0x00D00800; +CHECKREG r3, 0x00D00800; +CHECKREG r4, 0x00D00800; +CHECKREG r5, 0x00D00800; +CHECKREG r6, 0x00D00800; +CHECKREG r7, 0x00D00800; + + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_fdepx.s b/tests/tcg/bfin/c_dsp32shift_fdepx.s new file mode 100644 index 0000000000000..5e843fe550b55 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_fdepx.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp +// Spec Reference: dsp32shift fdep x +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = DEPOSIT( R1, R0 ); +R2 = DEPOSIT( R2, R0 ); +R3 = DEPOSIT( R3, R0 ); +R4 = DEPOSIT( R4, R0 ) (X); +R5 = DEPOSIT( R5, R0 ); +R6 = DEPOSIT( R6, R0 ); +R7 = DEPOSIT( R7, R0 ) (X); +R0 = DEPOSIT( R0, R0 ); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x01000800; +CHECKREG r2, 0x08200802; +CHECKREG r3, 0x08030802; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x08000504; +CHECKREG r6, 0x08000866; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09000002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = DEPOSIT( R0, R1 ); +R2 = DEPOSIT( R2, R1 ); +R3 = DEPOSIT( R3, R1 ); +R4 = DEPOSIT( R4, R1 ); +R5 = DEPOSIT( R5, R1 ) (X); +R6 = DEPOSIT( R6, R1 ); +R7 = DEPOSIT( R7, R1 ) (X); +R1 = DEPOSIT( R1, R1 ); +CHECKREG r0, 0x0900D000; +CHECKREG r1, 0x09000000; +CHECKREG r2, 0x09000000; +CHECKREG r3, 0x09100000; +CHECKREG r4, 0x09020004; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x09000404; +CHECKREG r7, 0x00000000; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a000010; +imm32 r4, 0x0a00e004; +imm32 r5, 0x0a00e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0a00e007; +R0 = DEPOSIT( R0, R2 ); +R1 = DEPOSIT( R1, R2 ); +R3 = DEPOSIT( R3, R2 ); +R4 = DEPOSIT( R4, R2 ); +R5 = DEPOSIT( R5, R2 ); +R6 = DEPOSIT( R6, R2 ); +R7 = DEPOSIT( R7, R2 ); +R2 = DEPOSIT( R2, R2 ); +CHECKREG r0, 0x0A008A00; +CHECKREG r1, 0x0A008A00; +CHECKREG r2, 0x0A000A00; +CHECKREG r3, 0x0A000A00; +CHECKREG r4, 0x0A008A00; +CHECKREG r5, 0x0A008A00; +CHECKREG r6, 0x0A008A00; +CHECKREG r7, 0x0A008A00; + +imm32 r0, 0x4b00f001; +imm32 r1, 0x5b00f001; +imm32 r2, 0x6b00f002; +imm32 r3, 0x9f000010; +imm32 r4, 0x8b00f004; +imm32 r5, 0x0900f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x0b0af007; +R0 = DEPOSIT( R0, R3 ); +R1 = DEPOSIT( R1, R3 ); +R2 = DEPOSIT( R2, R3 ) (X); +R4 = DEPOSIT( R4, R3 ); +R5 = DEPOSIT( R5, R3 ); +R6 = DEPOSIT( R6, R3 ) (X); +R7 = DEPOSIT( R7, R3 ); +R3 = DEPOSIT( R3, R3 ); +CHECKREG r0, 0x4B009F00; +CHECKREG r1, 0x5B009F00; +CHECKREG r2, 0xFFFF9F00; +CHECKREG r3, 0x9F009F00; +CHECKREG r4, 0x8B009F00; +CHECKREG r5, 0x09009F00; +CHECKREG r6, 0xFFFF9F00; +CHECKREG r7, 0x0B0A9F00; + +imm32 r0, 0x0c0000c0; +imm32 r1, 0x0c0100c0; +imm32 r2, 0x0c0200c0; +imm32 r3, 0x0c0300c0; +imm32 r4, 0x0c04000c; +imm32 r5, 0x0c0500c0; +imm32 r6, 0x0c0600c0; +imm32 r7, 0x0c0700c0; +R0 = DEPOSIT( R0, R4 ); +R1 = DEPOSIT( R1, R4 ); +R2 = DEPOSIT( R2, R4 ); +R3 = DEPOSIT( R3, R4 ); +R5 = DEPOSIT( R5, R4 ) (X); +R6 = DEPOSIT( R6, R4 ); +R7 = DEPOSIT( R7, R4 ); +R4 = DEPOSIT( R4, R4 ); +CHECKREG r0, 0x0C000C04; +CHECKREG r1, 0x0C010C04; +CHECKREG r2, 0x0C020C04; +CHECKREG r3, 0x0C030C04; +CHECKREG r4, 0x0C040C04; +CHECKREG r5, 0xFFFFFC04; +CHECKREG r6, 0x0C060C04; +CHECKREG r7, 0x0C070C04; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R5 = DEPOSIT( R0, R5 ); +R6 = DEPOSIT( R1, R5 ) (X); +R7 = DEPOSIT( R2, R5 ); +R0 = DEPOSIT( R3, R5 ); +R1 = DEPOSIT( R4, R5 ) (X); +R2 = DEPOSIT( R6, R5 ); +R3 = DEPOSIT( R7, R5 ); +R4 = DEPOSIT( R5, R5 ); +CHECKREG r0, 0xA00300C1; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0xA00200C1; +CHECKREG r4, 0xA0010081; +CHECKREG r5, 0xA0010085; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0xA00200C1; + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0x00237809; +imm32 r7, 0xb0070000; +R0 = DEPOSIT( R0, R6 ); +R1 = DEPOSIT( R1, R6 ); +R2 = DEPOSIT( R2, R6 ); +R3 = DEPOSIT( R3, R6 ) (X); +R4 = DEPOSIT( R4, R6 ); +R5 = DEPOSIT( R5, R6 ); +R6 = DEPOSIT( R6, R6 ); +R7 = DEPOSIT( R7, R6 ); +CHECKREG r0, 0x23010000; +CHECKREG r1, 0x23010000; +CHECKREG r2, 0x2302000F; +CHECKREG r3, 0x23030000; +CHECKREG r4, 0x23040000; +CHECKREG r5, 0x23050000; +CHECKREG r6, 0x23237809; +CHECKREG r7, 0x23070000; + +imm32 r0, 0xd00100e0; +imm32 r1, 0xd00100e0; +imm32 r2, 0xd00200e0; +imm32 r3, 0xd00300e0; +imm32 r4, 0xd00400e0; +imm32 r5, 0xd00500e0; +imm32 r6, 0xd00600e0; +imm32 r7, 0x00012345; +R1 = DEPOSIT( R0, R7 ); +R2 = DEPOSIT( R1, R7 ); +R3 = DEPOSIT( R2, R7 ); +R4 = DEPOSIT( R3, R7 ); +R5 = DEPOSIT( R4, R7 ) (X); +R6 = DEPOSIT( R5, R7 ); +R7 = DEPOSIT( R6, R7 ) (X); +R0 = DEPOSIT( R7, R7 ); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xD0010008; +CHECKREG r2, 0xD0010008; +CHECKREG r3, 0xD0010008; +CHECKREG r4, 0xD0010008; +CHECKREG r5, 0x00000008; +CHECKREG r6, 0x00000008; +CHECKREG r7, 0x00000008; + + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_fextx.s b/tests/tcg/bfin/c_dsp32shift_fextx.s new file mode 100644 index 0000000000000..13ba90c136bb4 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_fextx.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_fextx/c_dsp32shift_fextx.dsp +// Spec Reference: dsp32shift fext x +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = EXTRACT( R1, R0.L ) (Z); +R2 = EXTRACT( R2, R0.L ) (Z); +R3 = EXTRACT( R3, R0.L ) (Z); +R4 = EXTRACT( R4, R0.L ) (X); +R5 = EXTRACT( R5, R0.L ) (Z); +R6 = EXTRACT( R6, R0.L ) (Z); +R7 = EXTRACT( R7, R0.L ) (X); +R0 = EXTRACT( R0, R0.L ) (Z); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09000002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = EXTRACT( R0, R1.L ) (Z); +R2 = EXTRACT( R2, R1.L ) (Z); +R3 = EXTRACT( R3, R1.L ) (Z); +R4 = EXTRACT( R4, R1.L ) (Z); +R5 = EXTRACT( R5, R1.L ) (X); +R6 = EXTRACT( R6, R1.L ) (Z); +R7 = EXTRACT( R7, R1.L ) (X); +R1 = EXTRACT( R1, R1.L ) (Z); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0xFFFFFFFF; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a000010; +imm32 r4, 0x0a00e004; +imm32 r5, 0x0a00e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0a00e007; +R0 = EXTRACT( R0, R2.L ) (Z); +R1 = EXTRACT( R1, R2.L ) (Z); +R3 = EXTRACT( R3, R2.L ) (Z); +R4 = EXTRACT( R4, R2.L ) (Z); +R5 = EXTRACT( R5, R2.L ) (Z); +R6 = EXTRACT( R6, R2.L ) (Z); +R7 = EXTRACT( R7, R2.L ) (Z); +R2 = EXTRACT( R2, R2.L ) (Z); +CHECKREG r0, 0x00006001; +CHECKREG r1, 0x00006001; +CHECKREG r2, 0x0000000F; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00006004; +CHECKREG r5, 0x00006005; +CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00006007; + +imm32 r0, 0x0b00f001; +imm32 r1, 0x0b00f001; +imm32 r2, 0x0b00f002; +imm32 r3, 0x0b000010; +imm32 r4, 0x0b00f004; +imm32 r5, 0x0b00f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x0b00f007; +R0 = EXTRACT( R0, R3.L ) (Z); +R1 = EXTRACT( R1, R3.L ) (Z); +R2 = EXTRACT( R2, R3.L ) (X); +R4 = EXTRACT( R4, R3.L ) (Z); +R5 = EXTRACT( R5, R3.L ) (Z); +R6 = EXTRACT( R6, R3.L ) (X); +R7 = EXTRACT( R7, R3.L ) (Z); +R3 = EXTRACT( R3, R3.L ) (Z); +CHECKREG r0, 0x0000F001; +CHECKREG r1, 0x0000F001; +CHECKREG r2, 0xFFFFF002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000F004; +CHECKREG r5, 0x0000F005; +CHECKREG r6, 0xFFFFF006; +CHECKREG r7, 0x0000F007; + +imm32 r0, 0x0c0000c0; +imm32 r1, 0x0c0100c0; +imm32 r2, 0x0c0200c0; +imm32 r3, 0x0c0300c0; +imm32 r4, 0x0c04000c; +imm32 r5, 0x0c0500c0; +imm32 r6, 0x0c0600c0; +imm32 r7, 0x0c0700c0; +R0 = EXTRACT( R0, R4.L ) (Z); +R1 = EXTRACT( R1, R4.L ) (Z); +R2 = EXTRACT( R2, R4.L ) (Z); +R3 = EXTRACT( R3, R4.L ) (Z); +R5 = EXTRACT( R5, R4.L ) (X); +R6 = EXTRACT( R6, R4.L ) (Z); +R7 = EXTRACT( R7, R4.L ) (Z); +R4 = EXTRACT( R4, R4.L ) (Z); +CHECKREG r0, 0x000000C0; +CHECKREG r1, 0x000000C0; +CHECKREG r2, 0x000000C0; +CHECKREG r3, 0x000000C0; +CHECKREG r4, 0x0000000C; +CHECKREG r5, 0x000000C0; +CHECKREG r6, 0x000000C0; +CHECKREG r7, 0x000000C0; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = EXTRACT( R0, R5.L ) (Z); +R1 = EXTRACT( R1, R5.L ) (X); +R2 = EXTRACT( R2, R5.L ) (Z); +R3 = EXTRACT( R3, R5.L ) (Z); +R4 = EXTRACT( R4, R5.L ) (X); +R6 = EXTRACT( R6, R5.L ) (Z); +R7 = EXTRACT( R7, R5.L ) (Z); +R5 = EXTRACT( R5, R5.L ) (Z); +CHECKREG r0, 0x00000050; +CHECKREG r1, 0xFFFFFFD1; +CHECKREG r2, 0x00000050; +CHECKREG r3, 0x00000050; +CHECKREG r4, 0xFFFFFFD0; +CHECKREG r5, 0x00000007; +CHECKREG r6, 0x00000050; +CHECKREG r7, 0x00000050; + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060009; +imm32 r7, 0xb0070000; +R0 = EXTRACT( R0, R6.L ) (Z); +R1 = EXTRACT( R1, R6.L ) (Z); +R2 = EXTRACT( R2, R6.L ) (Z); +R3 = EXTRACT( R3, R6.L ) (X); +R4 = EXTRACT( R4, R6.L ) (Z); +R5 = EXTRACT( R5, R6.L ) (Z); +R6 = EXTRACT( R6, R6.L ) (Z); +R7 = EXTRACT( R7, R6.L ) (Z); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x0000000F; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000009; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xd00100e0; +imm32 r1, 0xd00100e0; +imm32 r2, 0xd00200e0; +imm32 r3, 0xd00300e0; +imm32 r4, 0xd00400e0; +imm32 r5, 0xd00500e0; +imm32 r6, 0xd00600e0; +imm32 r7, 0xd0070023; +R1 = EXTRACT( R0, R7.L ) (Z); +R2 = EXTRACT( R1, R7.L ) (Z); +R3 = EXTRACT( R2, R7.L ) (Z); +R4 = EXTRACT( R3, R7.L ) (Z); +R5 = EXTRACT( R4, R7.L ) (X); +R6 = EXTRACT( R5, R7.L ) (Z); +R7 = EXTRACT( R6, R7.L ) (X); +R0 = EXTRACT( R7, R7.L ) (Z); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_lf.s b/tests/tcg/bfin/c_dsp32shift_lf.s new file mode 100644 index 0000000000000..88ee774ed4984 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_lf.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shift_lf/c_dsp32shift_lf.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : mix data, count (+)= (half reg) +// d_reg = lshift (d BY d_lo) +// Rx by RLx +imm32 r0, 0x01210001; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R7 = LSHIFT R0 BY R0.L; +R6 = LSHIFT R1 BY R0.L; +R0 = LSHIFT R2 BY R0.L; +R1 = LSHIFT R3 BY R0.L; +R2 = LSHIFT R4 BY R0.L; +R3 = LSHIFT R5 BY R0.L; +R4 = LSHIFT R6 BY R0.L; +R5 = LSHIFT R7 BY R0.L; +CHECKREG r0, 0x4682CF12; +CHECKREG r1, 0xE2680000; +CHECKREG r2, 0x26AC0000; +CHECKREG r3, 0x6AF00000; +CHECKREG r4, 0xB3C00000; +CHECKREG r5, 0x00080000; +CHECKREG r6, 0x2462ACF0; +CHECKREG r7, 0x02420002; + +imm32 r0, 0x01220002; +imm32 r1, 0x12325678; +imm32 r2, 0x23426789; +imm32 r3, 0x3452789a; +imm32 r4, 0x956289ab; +imm32 r5, 0xa6729abc; +imm32 r6, 0xb782abcd; +imm32 r7, 0xc892bcde; +R1.L = 2; +R3 = LSHIFT R0 BY R1.L; +R4 = LSHIFT R1 BY R1.L; +R5 = LSHIFT R2 BY R1.L; +R6 = LSHIFT R3 BY R1.L; +R7 = LSHIFT R4 BY R1.L; +R0 = LSHIFT R5 BY R1.L; +R1 = LSHIFT R6 BY R1.L; +R2 = LSHIFT R7 BY R1.L; +CHECKREG r0, 0x34267890; +CHECKREG r1, 0x48800080; +CHECKREG r2, 0x23200020; +CHECKREG r3, 0x04880008; +CHECKREG r4, 0x48C80008; +CHECKREG r5, 0x8D099E24; +CHECKREG r6, 0x12200020; +CHECKREG r7, 0x23200020; + +imm32 r0, 0x01230002; +imm32 r1, 0x12335678; +imm32 r2, 0x23436789; +imm32 r3, 0x3453789a; +imm32 r4, 0x456389ab; +imm32 r5, 0x56739abc; +imm32 r6, 0x6783abcd; +imm32 r7, 0x789abcde; +R2 = 14; +R0 = LSHIFT R4 BY R2.L; +R1 = LSHIFT R5 BY R2.L; +R2 = LSHIFT R6 BY R2.L; +R3 = LSHIFT R7 BY R2.L; +CHECKREG r0, 0xE26AC000; +CHECKREG r1, 0xE6AF0000; +CHECKREG r2, 0xEAF34000; +CHECKREG r3, 0x789ABCDE; + +imm32 r0, 0x01240002; +imm32 r1, 0x12345678; +imm32 r2, 0x23446789; +imm32 r3, 0x3454789a; +imm32 r4, 0xa56489ab; +imm32 r5, 0xb6749abc; +imm32 r6, 0xc784abcd; +imm32 r7, 0xd894bcde; +R3.L = 15; +R4 = LSHIFT R0 BY R3.L; +R5 = LSHIFT R1 BY R3.L; +R6 = LSHIFT R2 BY R3.L; +R7 = LSHIFT R3 BY R3.L; +R0 = LSHIFT R4 BY R3.L; +R1 = LSHIFT R5 BY R3.L; +R2 = LSHIFT R6 BY R3.L; +R3 = LSHIFT R7 BY R3.L; +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0xC0000000; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x2B3C0000; +CHECKREG r6, 0x33C48000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x01250002; +imm32 r1, 0x12355678; +imm32 r2, 0x23456789; +imm32 r3, 0x3455789a; +imm32 r4, 0x456589ab; +imm32 r5, 0x56759abc; +imm32 r6, 0x6785abcd; +imm32 r7, 0x7895bcde; +R4.L = -1; +R7 = LSHIFT R0 BY R4.L; +R6 = LSHIFT R1 BY R4.L; +R5 = LSHIFT R2 BY R4.L; +R3 = LSHIFT R4 BY R4.L; +R2 = LSHIFT R5 BY R4.L; +R1 = LSHIFT R6 BY R4.L; +R0 = LSHIFT R7 BY R4.L; +R4 = LSHIFT R3 BY R4.L; +CHECKREG r0, 0x00494000; +CHECKREG r1, 0x048D559E; +CHECKREG r2, 0x08D159E2; +CHECKREG r3, 0x22B2FFFF; +CHECKREG r4, 0x11597FFF; +CHECKREG r5, 0x11A2B3C4; +CHECKREG r6, 0x091AAB3C; +CHECKREG r7, 0x00928001; + +imm32 r0, 0x01260002; +imm32 r1, 0x82365678; +imm32 r2, 0x93466789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56689ab; +imm32 r5, 0xc6769abc; +imm32 r6, 0xd786abcd; +imm32 r7, 0xe896bcde; +R5.L = -8; +R6 = LSHIFT R0 BY R5.L; +R7 = LSHIFT R1 BY R5.L; +R0 = LSHIFT R2 BY R5.L; +R1 = LSHIFT R3 BY R5.L; +R2 = LSHIFT R4 BY R5.L; +R3 = LSHIFT R5 BY R5.L; +R4 = LSHIFT R6 BY R5.L; +R5 = LSHIFT R7 BY R5.L; +CHECKREG r0, 0x00934667; +CHECKREG r1, 0x00A45678; +CHECKREG r2, 0x00B56689; +CHECKREG r3, 0x00C676FF; +CHECKREG r4, 0x00000126; +CHECKREG r5, 0x00008236; +CHECKREG r6, 0x00012600; +CHECKREG r7, 0x00823656; + +imm32 r0, 0x01270002; +imm32 r1, 0x12375678; +imm32 r2, 0x23476789; +imm32 r3, 0x3457789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56779abc; +imm32 r6, 0x6787abcd; +imm32 r7, 0x7897bcde; +R6.L = -15; +R7 = LSHIFT R0 BY R6.L; +R0 = LSHIFT R1 BY R6.L; +R1 = LSHIFT R2 BY R6.L; +R2 = LSHIFT R3 BY R6.L; +R3 = LSHIFT R4 BY R6.L; +R4 = LSHIFT R5 BY R6.L; +R5 = LSHIFT R6 BY R6.L; +R6 = LSHIFT R7 BY R6.L; +CHECKREG r0, 0x0000246E; +CHECKREG r1, 0x0000468E; +CHECKREG r2, 0x000068AE; +CHECKREG r3, 0x00008ACF; +CHECKREG r4, 0x0000ACEF; +CHECKREG r5, 0x0000CF0F; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x0000024E; + +imm32 r0, 0x01280002; +imm32 r1, 0x82385678; +imm32 r2, 0x93486789; +imm32 r3, 0xa458789a; +imm32 r4, 0xb56889ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd788abcd; +imm32 r7, 0xe898bcde; +R7.L = -16; +R0 = LSHIFT R0 BY R7.L; +R1 = LSHIFT R1 BY R7.L; +R2 = LSHIFT R2 BY R7.L; +R3 = LSHIFT R3 BY R7.L; +R4 = LSHIFT R4 BY R7.L; +R5 = LSHIFT R5 BY R7.L; +R6 = LSHIFT R6 BY R7.L; +R7 = LSHIFT R7 BY R7.L; +CHECKREG r0, 0x00000128; +CHECKREG r1, 0x00008238; +CHECKREG r2, 0x00009348; +CHECKREG r3, 0x0000A458; +CHECKREG r4, 0x0000B568; +CHECKREG r5, 0x0000C678; +CHECKREG r6, 0x0000D788; +CHECKREG r7, 0x0000E898; + +imm32 r0, 0x81290002; +imm32 r1, 0x92395678; +imm32 r2, 0xa3496789; +imm32 r3, 0xb459789a; +imm32 r4, 0xc56989ab; +imm32 r5, 0xd6799abc; +imm32 r6, 0xe789abcd; +imm32 r7, 0xf899bcde; +R0.L = 4; +//r0 = lshift (r0 by rl0); +R1 = LSHIFT R1 BY R0.L; +R2 = LSHIFT R2 BY R0.L; +R3 = LSHIFT R3 BY R0.L; +R4 = LSHIFT R4 BY R0.L; +R5 = LSHIFT R5 BY R0.L; +R6 = LSHIFT R6 BY R0.L; +R7 = LSHIFT R7 BY R0.L; +CHECKREG r1, 0x23956780; +CHECKREG r2, 0x34967890; +CHECKREG r3, 0x459789A0; +CHECKREG r4, 0x56989AB0; +CHECKREG r5, 0x6799ABC0; +CHECKREG r6, 0x789ABCD0; +CHECKREG r7, 0x899BCDE0; + +imm32 r0, 0x012a0002; +imm32 r1, 0x123a5678; +imm32 r2, 0x234a6789; +imm32 r3, 0x345a789a; +imm32 r4, 0x456a89ab; +imm32 r5, 0x567a9abc; +imm32 r6, 0x678aabcd; +imm32 r7, 0xf89abcde; +R1.L = 2; +R7 = LSHIFT R0 BY R1.L; +R6 = LSHIFT R1 BY R1.L; +R5 = LSHIFT R2 BY R1.L; +R4 = LSHIFT R3 BY R1.L; +R3 = LSHIFT R4 BY R1.L; +R2 = LSHIFT R5 BY R1.L; +R0 = LSHIFT R6 BY R1.L; +R1 = LSHIFT R7 BY R1.L; +CHECKREG r0, 0x23A00020; +CHECKREG r1, 0x12A00020; +CHECKREG r2, 0x34A67890; +CHECKREG r3, 0x45A789A0; +CHECKREG r4, 0xD169E268; +CHECKREG r5, 0x8D299E24; +CHECKREG r6, 0x48E80008; +CHECKREG r7, 0x04A80008; + + +imm32 r0, 0x012b0002; +imm32 r1, 0x123b5678; +imm32 r2, 0x234b6789; +imm32 r3, 0x345b789a; +imm32 r4, 0x456b89ab; +imm32 r5, 0x567b9abc; +imm32 r6, 0x678babcd; +imm32 r7, 0x789bbcde; +R2.L = 15; +R0 = LSHIFT R0 BY R2.L; +R1 = LSHIFT R1 BY R2.L; +R3 = LSHIFT R3 BY R2.L; +R4 = LSHIFT R4 BY R2.L; +R5 = LSHIFT R5 BY R2.L; +R6 = LSHIFT R6 BY R2.L; +R7 = LSHIFT R7 BY R2.L; +R2 = LSHIFT R2 BY R2.L; +CHECKREG r0, 0x80010000; +CHECKREG r1, 0xAB3C0000; +CHECKREG r2, 0x80078000; +CHECKREG r3, 0xBC4D0000; +CHECKREG r4, 0xC4D58000; +CHECKREG r5, 0xCD5E0000; +CHECKREG r6, 0xD5E68000; +CHECKREG r7, 0xDE6F0000; + +imm32 r0, 0x012c0002; +imm32 r1, 0x123c5678; +imm32 r2, 0x234c6789; +imm32 r3, 0x345c789a; +imm32 r4, 0x456c89ab; +imm32 r5, 0x567c9abc; +imm32 r6, 0x678cabcd; +imm32 r7, 0x789cbcde; +R3.L = 16; +R0 = LSHIFT R0 BY R3.L; +R1 = LSHIFT R1 BY R3.L; +R2 = LSHIFT R2 BY R3.L; +R4 = LSHIFT R4 BY R3.L; +R5 = LSHIFT R5 BY R3.L; +R6 = LSHIFT R6 BY R3.L; +R7 = LSHIFT R7 BY R3.L; +R3 = LSHIFT R3 BY R3.L; +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x56780000; +CHECKREG r2, 0x67890000; +CHECKREG r3, 0x00100000; +CHECKREG r4, 0x89AB0000; +CHECKREG r5, 0x9ABC0000; +CHECKREG r6, 0xABCD0000; +CHECKREG r7, 0xBCDE0000; + +imm32 r0, 0x012d0002; +imm32 r1, 0x123d5678; +imm32 r2, 0x234d6789; +imm32 r3, 0x345d789a; +imm32 r4, 0x456d89ab; +imm32 r5, 0x567d9abc; +imm32 r6, 0x678dabcd; +imm32 r7, 0x789dbcde; +R4.L = -9; +R7 = LSHIFT R0 BY R4.L; +R0 = LSHIFT R1 BY R4.L; +R1 = LSHIFT R2 BY R4.L; +R2 = LSHIFT R3 BY R4.L; +//r4 = lshift (r4 by rl4); +R3 = LSHIFT R5 BY R4.L; +R5 = LSHIFT R6 BY R4.L; +R6 = LSHIFT R7 BY R4.L; +CHECKREG r0, 0x00091EAB; +CHECKREG r1, 0x0011A6B3; +CHECKREG r2, 0x001A2EBC; +CHECKREG r3, 0x002B3ECD; +CHECKREG r4, 0x456DFFF7; +CHECKREG r5, 0x0033C6D5; +CHECKREG r6, 0x0000004B; +CHECKREG r7, 0x00009680; + +imm32 r0, 0x012e0002; +imm32 r1, 0x123e5678; +imm32 r2, 0x234e6789; +imm32 r3, 0x345e789a; +imm32 r4, 0x456e89ab; +imm32 r5, 0x567e9abc; +imm32 r6, 0x678eabcd; +imm32 r7, 0x789ebcde; +R5.L = -14; +R0 = LSHIFT R0 BY R5.L; +R1 = LSHIFT R1 BY R5.L; +R2 = LSHIFT R2 BY R5.L; +R3 = LSHIFT R3 BY R5.L; +R4 = LSHIFT R4 BY R5.L; +//r5 = lshift (r5 by rl5); +R6 = LSHIFT R6 BY R5.L; +R7 = LSHIFT R7 BY R5.L; +CHECKREG r0, 0x000004B8; +CHECKREG r1, 0x000048F9; +CHECKREG r2, 0x00008D39; +CHECKREG r3, 0x0000D179; +CHECKREG r4, 0x000115BA; +CHECKREG r5, 0x567EFFF2; +CHECKREG r6, 0x00019E3A; +CHECKREG r7, 0x0001E27A; + + +imm32 r0, 0x012f0002; +imm32 r1, 0x623f5678; +imm32 r2, 0x734f6789; +imm32 r3, 0x845f789a; +imm32 r4, 0x956f89ab; +imm32 r5, 0xa67f9abc; +imm32 r6, 0xc78fabcd; +imm32 r7, 0xd89fbcde; +R6.L = -15; +R0 = LSHIFT R0 BY R6.L; +R1 = LSHIFT R1 BY R6.L; +R2 = LSHIFT R2 BY R6.L; +R3 = LSHIFT R3 BY R6.L; +R4 = LSHIFT R4 BY R6.L; +R5 = LSHIFT R5 BY R6.L; +//r6 = lshift (r6 by rl6); +R7 = LSHIFT R7 BY R6.L; +CHECKREG r0, 0x0000025E; +CHECKREG r1, 0x0000C47E; +CHECKREG r2, 0x0000E69E; +CHECKREG r3, 0x000108BE; +CHECKREG r4, 0x00012ADF; +CHECKREG r5, 0x00014CFF; +CHECKREG r6, 0xC78FFFF1; +CHECKREG r7, 0x0001B13F; + +imm32 r0, 0x71230072; +imm32 r1, 0x82345678; +imm32 r2, 0x93456779; +imm32 r3, 0xa456787a; +imm32 r4, 0xb567897b; +imm32 r5, 0xc6789a7c; +imm32 r6, 0x6789ab7d; +imm32 r7, 0x789abc7e; +R7.L = -16; +R0 = LSHIFT R0 BY R7.L; +R1 = LSHIFT R1 BY R7.L; +R2 = LSHIFT R2 BY R7.L; +R3 = LSHIFT R3 BY R7.L; +R4 = LSHIFT R4 BY R7.L; +R5 = LSHIFT R5 BY R7.L; +R6 = LSHIFT R6 BY R7.L; +R7 = LSHIFT R7 BY R7.L; +CHECKREG r0, 0x00007123; +CHECKREG r1, 0x00008234; +CHECKREG r2, 0x00009345; +CHECKREG r3, 0x0000A456; +CHECKREG r4, 0x0000B567; +CHECKREG r5, 0x0000C678; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x0000789A; + + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_lhalf_ln.s b/tests/tcg/bfin/c_dsp32shift_lhalf_ln.s new file mode 100644 index 0000000000000..df47e33f7beb7 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_lhalf_ln.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_ln/c_dsp32shift_lhalf_ln.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : neg data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = LSHIFT R0.L BY R0.L; +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c001; +CHECKREG r2, 0x0000c002; +CHECKREG r3, 0x0000c003; +CHECKREG r4, 0x0000c004; +CHECKREG r5, 0x0000c005; +CHECKREG r6, 0x0000c006; +CHECKREG r7, 0x0000c007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000a004; +CHECKREG r3, 0x0000c006; +CHECKREG r4, 0x0000e008; +CHECKREG r5, 0x0000800a; +CHECKREG r6, 0x0000a00c; +CHECKREG r7, 0x0000c00e; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = lshft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x90012002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x90022004; +CHECKREG r3, 0x90032006; +CHECKREG r4, 0x90042008; +CHECKREG r5, 0x9005200a; +CHECKREG r6, 0x9006200c; +CHECKREG r7, 0x9007200e; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0xa0018000; +CHECKREG r1, 0xa0018000; +CHECKREG r2, 0xa002000f; +CHECKREG r3, 0xa0038000; +CHECKREG r4, 0xa0040000; +CHECKREG r5, 0xa0058000; +CHECKREG r6, 0xa0060000; +CHECKREG r7, 0xa0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0xc0010000; +CHECKREG r1, 0xc0010000; +CHECKREG r2, 0xc0020000; +CHECKREG r3, 0xc0030010; +CHECKREG r4, 0xc0040000; +CHECKREG r5, 0xc0050000; +CHECKREG r6, 0xc0060000; +CHECKREG r7, 0xc0070000; + +// d_hi = lshft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R0.L; +R1.H = LSHIFT R1.L BY R0.L; +R2.H = LSHIFT R2.L BY R0.L; +R3.H = LSHIFT R3.L BY R0.L; +R4.H = LSHIFT R4.L BY R0.L; +R5.H = LSHIFT R5.L BY R0.L; +R6.H = LSHIFT R6.L BY R0.L; +R7.H = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.H = LSHIFT R0.L BY R1.L; +R1.H = LSHIFT R1.L BY R1.L; +R2.H = LSHIFT R2.L BY R1.L; +R3.H = LSHIFT R3.L BY R1.L; +R4.H = LSHIFT R4.L BY R1.L; +R5.H = LSHIFT R5.L BY R1.L; +R6.H = LSHIFT R6.L BY R1.L; +R7.H = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0xa002d001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0xa004d002; +CHECKREG r3, 0xa006d003; +CHECKREG r4, 0xa008d004; +CHECKREG r5, 0xa00ad005; +CHECKREG r6, 0xa00cd006; +CHECKREG r7, 0xa00ed007; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = LSHIFT R0.L BY R2.L; +R1.H = LSHIFT R1.L BY R2.L; +//rh2 = lshift (rl2 by rl2); +R3.H = LSHIFT R3.L BY R2.L; +R4.H = LSHIFT R4.L BY R2.L; +R5.H = LSHIFT R5.L BY R2.L; +R6.H = LSHIFT R6.L BY R2.L; +R7.H = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x8000e001; +CHECKREG r1, 0x8000e001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x8000e003; +CHECKREG r4, 0x0000e004; +CHECKREG r5, 0x8000e005; +CHECKREG r6, 0x0000e006; +CHECKREG r7, 0x8000e007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.H = LSHIFT R0.L BY R3.L; +R1.H = LSHIFT R1.L BY R3.L; +R2.H = LSHIFT R2.L BY R3.L; +R3.H = LSHIFT R3.L BY R3.L; +R4.H = LSHIFT R4.L BY R3.L; +R5.H = LSHIFT R5.L BY R3.L; +R6.H = LSHIFT R6.L BY R3.L; +R7.H = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x0000f001; +CHECKREG r1, 0x0000f001; +CHECKREG r2, 0x0000f002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000f004; +CHECKREG r5, 0x0000f005; +CHECKREG r6, 0x0000f006; +CHECKREG r7, 0x0000f007; + +// d_lo = lshft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R0.L; +R1.H = LSHIFT R1.H BY R0.L; +R2.H = LSHIFT R2.H BY R0.L; +R3.H = LSHIFT R3.H BY R0.L; +R4.H = LSHIFT R4.H BY R0.L; +R5.H = LSHIFT R5.H BY R0.L; +R6.H = LSHIFT R6.H BY R0.L; +R7.H = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.H = LSHIFT R0.H BY R1.L; +R1.H = LSHIFT R1.H BY R1.L; +R2.H = LSHIFT R2.H BY R1.L; +R3.H = LSHIFT R3.H BY R1.L; +R4.H = LSHIFT R4.H BY R1.L; +R5.H = LSHIFT R5.H BY R1.L; +R6.H = LSHIFT R6.H BY R1.L; +R7.H = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x40020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x40040000; +CHECKREG r3, 0x40060000; +CHECKREG r4, 0x40080000; +CHECKREG r5, 0x400a0000; +CHECKREG r6, 0x400c0000; +CHECKREG r7, 0x400e0000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0xb0018000; +CHECKREG r1, 0xb0018000; +CHECKREG r2, 0xb002000f; +CHECKREG r3, 0xb0038000; +CHECKREG r4, 0xb0040000; +CHECKREG r5, 0xb0058000; +CHECKREG r6, 0xb0060000; +CHECKREG r7, 0xb0078000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R0.H = LSHIFT R0.H BY R3.L; +R1.H = LSHIFT R1.H BY R3.L; +R2.H = LSHIFT R2.H BY R3.L; +R3.H = LSHIFT R3.H BY R3.L; +R4.H = LSHIFT R4.H BY R3.L; +R5.H = LSHIFT R5.H BY R3.L; +R6.H = LSHIFT R6.H BY R3.L; +R7.H = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +pass diff --git a/tests/tcg/bfin/c_dsp32shift_lhalf_lp.s b/tests/tcg/bfin/c_dsp32shift_lhalf_lp.s new file mode 100644 index 0000000000000..6000715ae7a99 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_lhalf_lp.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_lp/c_dsp32shift_lhalf_lp.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R0.L; +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000006; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x0000000c; +CHECKREG r7, 0x0000000e; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x00010002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020004; +CHECKREG r3, 0x00030006; +CHECKREG r4, 0x00040008; +CHECKREG r5, 0x0005000a; +CHECKREG r6, 0x0006000c; +CHECKREG r7, 0x0007000e; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010001; +imm32 r1, 0x00010001; +imm32 r2, 0x00020002; +imm32 r3, 0x00030010; +imm32 r4, 0x00040004; +imm32 r5, 0x00050005; +imm32 r6, 0x00060006; +imm32 r7, 0x00070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030010; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R0.L; +R1.H = LSHIFT R1.L BY R0.L; +R2.H = LSHIFT R2.L BY R0.L; +R3.H = LSHIFT R3.L BY R0.L; +R4.H = LSHIFT R4.L BY R0.L; +R5.H = LSHIFT R5.L BY R0.L; +R6.H = LSHIFT R6.L BY R0.L; +R7.H = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R1.L; +R1.H = LSHIFT R1.L BY R1.L; +R2.H = LSHIFT R2.L BY R1.L; +R3.H = LSHIFT R3.L BY R1.L; +R4.H = LSHIFT R4.L BY R1.L; +R5.H = LSHIFT R5.L BY R1.L; +R6.H = LSHIFT R6.L BY R1.L; +R7.H = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00020001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040002; +CHECKREG r3, 0x00060003; +CHECKREG r4, 0x00080004; +CHECKREG r5, 0x000a0005; +CHECKREG r6, 0x000c0006; +CHECKREG r7, 0x000e0007; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R2.L; +R1.H = LSHIFT R1.L BY R2.L; +//rh2 = lshift (rl2 by rl2); +R3.H = LSHIFT R3.L BY R2.L; +R4.H = LSHIFT R4.L BY R2.L; +R5.H = LSHIFT R5.L BY R2.L; +R6.H = LSHIFT R6.L BY R2.L; +R7.H = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x80000001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x80000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x80000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x80000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R3.L; +R1.H = LSHIFT R1.L BY R3.L; +R2.H = LSHIFT R2.L BY R3.L; +R3.H = LSHIFT R3.L BY R3.L; +R4.H = LSHIFT R4.L BY R3.L; +R5.H = LSHIFT R5.L BY R3.L; +R6.H = LSHIFT R6.L BY R3.L; +R7.H = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R0.L; +R1.H = LSHIFT R1.H BY R0.L; +R2.H = LSHIFT R2.H BY R0.L; +R3.H = LSHIFT R3.H BY R0.L; +R4.H = LSHIFT R4.H BY R0.L; +R5.H = LSHIFT R5.H BY R0.L; +R6.H = LSHIFT R6.H BY R0.L; +R7.H = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R1.L; +R1.H = LSHIFT R1.H BY R1.L; +R2.H = LSHIFT R2.H BY R1.L; +R3.H = LSHIFT R3.H BY R1.L; +R4.H = LSHIFT R4.H BY R1.L; +R5.H = LSHIFT R5.H BY R1.L; +R6.H = LSHIFT R6.H BY R1.L; +R7.H = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00060000; +CHECKREG r4, 0x00080000; +CHECKREG r5, 0x000a0000; +CHECKREG r6, 0x000c0000; +CHECKREG r7, 0x000e0000; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030010; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R3.L; +R1.H = LSHIFT R1.H BY R3.L; +R2.H = LSHIFT R2.H BY R3.L; +R3.H = LSHIFT R3.H BY R3.L; +R4.H = LSHIFT R4.H BY R3.L; +R5.H = LSHIFT R5.H BY R3.L; +R6.H = LSHIFT R6.H BY R3.L; +R7.H = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +pass diff --git a/tests/tcg/bfin/c_dsp32shift_lhalf_rn.s b/tests/tcg/bfin/c_dsp32shift_lhalf_rn.s new file mode 100644 index 0000000000000..a5b6563674c78 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_lhalf_rn.s @@ -0,0 +1,425 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_rn/c_dsp32shift_lhalf_rn.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +//rl0 = lshift (rl0 by rl0); +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00004000; +CHECKREG r2, 0x00004001; +CHECKREG r3, 0x00004001; +CHECKREG r4, 0x00004002; +CHECKREG r5, 0x00004002; +CHECKREG r6, 0x00004003; +CHECKREG r7, 0x00004003; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00004000; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00004001; +CHECKREG r3, 0x00004001; +CHECKREG r4, 0x00004002; +CHECKREG r5, 0x00004002; +CHECKREG r6, 0x00004003; +CHECKREG r7, 0x00004003; + + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +R2.L = -15; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80018001; +CHECKREG r2, 0x80028002; +CHECKREG r3, 0x80038003; +CHECKREG r4, 0x80048004; +CHECKREG r5, 0x80058005; +CHECKREG r6, 0x80068006; +CHECKREG r7, 0x80078007; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x80014000; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x80024001; +CHECKREG r3, 0x80034001; +CHECKREG r4, 0x80044002; +CHECKREG r5, 0x80054002; +CHECKREG r6, 0x80064003; +CHECKREG r7, 0x80074003; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0xa0010001; +CHECKREG r1, 0xa0010001; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0xa0030001; +CHECKREG r4, 0xa0040001; +CHECKREG r5, 0xa0050001; +CHECKREG r6, 0xa0060001; +CHECKREG r7, 0xa0070001; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0xb0010000; +CHECKREG r1, 0xb0010000; +CHECKREG r2, 0xb0020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0xb0040000; +CHECKREG r5, 0xb0050000; +CHECKREG r6, 0xb0060000; +CHECKREG r7, 0xb0070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R4.L; +R1.H = LSHIFT R1.L BY R4.L; +R2.H = LSHIFT R2.L BY R4.L; +R3.H = LSHIFT R3.L BY R4.L; +//rh4 = lshift (rl4 by rl4); +R5.H = LSHIFT R5.L BY R4.L; +R6.H = LSHIFT R6.L BY R4.L; +R7.H = LSHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = LSHIFT R0.L BY R5.L; +R1.H = LSHIFT R1.L BY R5.L; +R2.H = LSHIFT R2.L BY R5.L; +R3.H = LSHIFT R3.L BY R5.L; +R4.H = LSHIFT R4.L BY R5.L; +//rh5 = lshift (rl5 by rl5); +R6.H = LSHIFT R6.L BY R5.L; +R7.H = LSHIFT R7.L BY R5.L; +CHECKREG r0, 0x40008001; +CHECKREG r1, 0x40008001; +CHECKREG r2, 0x40018002; +CHECKREG r3, 0x40018003; +CHECKREG r4, 0x40028004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x40038006; +CHECKREG r7, 0x40038007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = LSHIFT R0.L BY R6.L; +R1.H = LSHIFT R1.L BY R6.L; +R2.H = LSHIFT R2.L BY R6.L; +R3.H = LSHIFT R3.L BY R6.L; +R4.H = LSHIFT R4.L BY R6.L; +R5.H = LSHIFT R5.L BY R6.L; +//rh6 = lshift (rl6 by rl6); +R7.H = LSHIFT R7.L BY R6.L; +CHECKREG r0, 0x00019001; +CHECKREG r1, 0x00019001; +CHECKREG r2, 0x00019002; +CHECKREG r3, 0x00019003; +CHECKREG r4, 0x00019004; +CHECKREG r5, 0x00019005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00019007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R0.H = LSHIFT R0.L BY R7.L; +R1.H = LSHIFT R1.L BY R7.L; +R2.H = LSHIFT R2.L BY R7.L; +R3.H = LSHIFT R3.L BY R7.L; +R4.H = LSHIFT R4.L BY R7.L; +R5.H = LSHIFT R5.L BY R7.L; +R6.H = LSHIFT R6.L BY R7.L; +R7.H = LSHIFT R7.L BY R7.L; +CHECKREG r0, 0x0000a001; +CHECKREG r1, 0x0000a001; +CHECKREG r2, 0x0000a002; +CHECKREG r3, 0x0000a003; +CHECKREG r4, 0x0000a004; +CHECKREG r5, 0x0000a005; +CHECKREG r6, 0x0000a006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = LSHIFT R0.H BY R4.L; +R1.H = LSHIFT R1.H BY R4.L; +R2.H = LSHIFT R2.H BY R4.L; +R3.H = LSHIFT R3.H BY R4.L; +//rh4 = lshift (rh4 by rl4); +R5.H = LSHIFT R5.H BY R4.L; +R6.H = LSHIFT R6.H BY R4.L; +R7.H = LSHIFT R7.H BY R4.L; +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40000000; +CHECKREG r2, 0x40010000; +CHECKREG r3, 0x40010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x40020000; +CHECKREG r6, 0x40030000; +CHECKREG r7, 0x40030000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = LSHIFT R0.H BY R5.L; +R1.H = LSHIFT R1.H BY R5.L; +R2.H = LSHIFT R2.H BY R5.L; +R3.H = LSHIFT R3.H BY R5.L; +R4.H = LSHIFT R4.H BY R5.L; +//rh5 = lshift (rh5 by rl5); +R6.H = LSHIFT R6.H BY R5.L; +R7.H = LSHIFT R7.H BY R5.L; +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40000000; +CHECKREG r2, 0x40010000; +CHECKREG r3, 0x40010000; +CHECKREG r4, 0x40020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x40030000; +CHECKREG r7, 0x40030000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = LSHIFT R0.H BY R6.L; +R1.L = LSHIFT R1.H BY R6.L; +R2.L = LSHIFT R2.H BY R6.L; +R3.L = LSHIFT R3.H BY R6.L; +R4.L = LSHIFT R4.H BY R6.L; +R5.L = LSHIFT R5.H BY R6.L; +//rl6 = lshift (rh6 by rl6); +R7.L = LSHIFT R7.H BY R6.L; +CHECKREG r0, 0xd0010001; +CHECKREG r1, 0xd0010001; +CHECKREG r2, 0xd0020001; +CHECKREG r3, 0xd0030001; +CHECKREG r4, 0xd0040001; +CHECKREG r5, 0xd0050001; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0xd0070001; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R0.H = LSHIFT R0.H BY R7.L; +R1.H = LSHIFT R1.H BY R7.L; +R2.H = LSHIFT R2.H BY R7.L; +R3.H = LSHIFT R3.H BY R7.L; +R4.H = LSHIFT R4.H BY R7.L; +R5.H = LSHIFT R5.H BY R7.L; +R6.H = LSHIFT R6.H BY R7.L; +//rh7 = lshift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_lhalf_rp.s b/tests/tcg/bfin/c_dsp32shift_lhalf_rp.s new file mode 100644 index 0000000000000..45fa6a06f4de3 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_lhalf_rp.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_rp/c_dsp32shift_lhalf_rp.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +//rl0 = lshift (rl0 by rl0); +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000800; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00001001; +CHECKREG r3, 0x00001801; +CHECKREG r4, 0x00002002; +CHECKREG r5, 0x00002802; +CHECKREG r6, 0x00003003; +CHECKREG r7, 0x00003803; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +R2.L = -15; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00002002; +R3.L = -16; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x10010800; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +R2.L = -15; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010001; +imm32 r1, 0x10010001; +imm32 r2, 0x20020002; +R3.L = -16; +imm32 r4, 0x40040004; +imm32 r5, 0x50050005; +imm32 r6, 0x60060006; +imm32 r7, 0x70070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R4.L; +R1.H = LSHIFT R1.L BY R4.L; +R2.H = LSHIFT R2.L BY R4.L; +R3.H = LSHIFT R3.L BY R4.L; +//rh4 = lshift (rl4 by rl4); +R5.H = LSHIFT R5.L BY R4.L; +R6.H = LSHIFT R6.L BY R4.L; +R7.H = LSHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R5.L; +R1.H = LSHIFT R1.L BY R5.L; +R2.H = LSHIFT R2.L BY R5.L; +R3.H = LSHIFT R3.L BY R5.L; +R4.H = LSHIFT R4.L BY R5.L; +//rh5 = lshift (rl5 by rl5); +R6.H = LSHIFT R6.L BY R5.L; +R7.H = LSHIFT R7.L BY R5.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00010002; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x00030006; +CHECKREG r7, 0x00030007; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r1, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = LSHIFT R0.L BY R6.L; +R1.H = LSHIFT R1.L BY R6.L; +R2.H = LSHIFT R2.L BY R6.L; +R3.H = LSHIFT R3.L BY R6.L; +R4.H = LSHIFT R4.L BY R6.L; +R5.H = LSHIFT R5.L BY R6.L; +//rh6 = lshift (rl6 by rl6); +R7.H = LSHIFT R7.L BY R6.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x00001001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +R7.L = -16; +R0.H = LSHIFT R0.L BY R7.L; +R1.H = LSHIFT R1.L BY R7.L; +R2.H = LSHIFT R2.L BY R7.L; +R3.H = LSHIFT R3.L BY R7.L; +R4.H = LSHIFT R4.L BY R7.L; +R5.H = LSHIFT R5.L BY R7.L; +R6.H = LSHIFT R6.L BY R7.L; +R7.H = LSHIFT R7.L BY R7.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002001; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x00006006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +R4.L = -1; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R4.L; +R1.H = LSHIFT R1.H BY R4.L; +R2.H = LSHIFT R2.H BY R4.L; +R3.H = LSHIFT R3.H BY R4.L; +//rh4 = lshift (rh4 by rl4); +R5.H = LSHIFT R5.H BY R4.L; +R6.H = LSHIFT R6.H BY R4.L; +R7.H = LSHIFT R7.H BY R4.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x00020000; +CHECKREG r6, 0x00030000; +CHECKREG r7, 0x00030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = LSHIFT R0.H BY R5.L; +R1.H = LSHIFT R1.H BY R5.L; +R2.H = LSHIFT R2.H BY R5.L; +R3.H = LSHIFT R3.H BY R5.L; +R4.H = LSHIFT R4.H BY R5.L; +//rh5 = lshift (rh5 by rl5); +R6.H = LSHIFT R6.H BY R5.L; +R7.H = LSHIFT R7.H BY R5.L; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x10010000; +CHECKREG r3, 0x18010000; +CHECKREG r4, 0x20020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x30030000; +CHECKREG r7, 0x38030000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = LSHIFT R0.H BY R6.L; +R1.L = LSHIFT R1.H BY R6.L; +R2.L = LSHIFT R2.H BY R6.L; +R3.L = LSHIFT R3.H BY R6.L; +R4.L = LSHIFT R4.H BY R6.L; +R5.L = LSHIFT R5.H BY R6.L; +//rl6 = lshift (rh6 by rl6); +R7.L = LSHIFT R7.H BY R6.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = LSHIFT R0.H BY R7.L; +R1.H = LSHIFT R1.H BY R7.L; +R2.H = LSHIFT R2.H BY R7.L; +R3.H = LSHIFT R3.H BY R7.L; +R4.H = LSHIFT R4.H BY R7.L; +R5.H = LSHIFT R5.H BY R7.L; +R6.H = LSHIFT R6.H BY R7.L; +//rh7 = lshift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; +pass diff --git a/tests/tcg/bfin/c_dsp32shift_ones.s b/tests/tcg/bfin/c_dsp32shift_ones.s new file mode 100644 index 0000000000000..40977773cf0ca --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_ones.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_ones/c_dsp32shift_ones.dsp +// Spec Reference: dsp32shift ones +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x88880000; +imm32 r1, 0x34560001; +imm32 r2, 0x08000002; +imm32 r3, 0x08000003; +imm32 r4, 0x08000004; +imm32 r5, 0x08000005; +imm32 r6, 0x08000006; +imm32 r7, 0x08000007; +R7.L = ONES R0; +R1.L = ONES R0; +R2.L = ONES R0; +R3.L = ONES R0; +R4.L = ONES R0; +R5.L = ONES R0; +R6.L = ONES R0; +R0.L = ONES R0; +CHECKREG r1, 0x34560004; +CHECKREG r0, 0x88880004; +CHECKREG r2, 0x08000004; +CHECKREG r3, 0x08000004; +CHECKREG r4, 0x08000004; +CHECKREG r5, 0x08000004; +CHECKREG r6, 0x08000004; +CHECKREG r7, 0x08000004; + +imm32 r0, 0x9999d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.L = ONES R1; +R7.L = ONES R1; +R2.L = ONES R1; +R3.L = ONES R1; +R4.L = ONES R1; +R5.L = ONES R1; +R6.L = ONES R1; +R1.L = ONES R1; +CHECKREG r0, 0x99990001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + + +imm32 r0, 0xaaaae001; +imm32 r1, 0x0000e001; +imm32 r2, 0xaaaa000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.L = ONES R2; +R1.L = ONES R2; +R7.L = ONES R2; +R3.L = ONES R2; +R4.L = ONES R2; +R5.L = ONES R2; +R6.L = ONES R2; +R2.L = ONES R2; +CHECKREG r0, 0xAAAA000C; +CHECKREG r1, 0x0000000C; +CHECKREG r2, 0xAAAA000C; +CHECKREG r3, 0x0000000C; +CHECKREG r4, 0x0000000C; +CHECKREG r5, 0x0000000C; +CHECKREG r6, 0x0000000C; +CHECKREG r7, 0x0000000C; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0xbbbb0010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = ONES R3; +R1.L = ONES R3; +R2.L = ONES R3; +R7.L = ONES R3; +R4.L = ONES R3; +R5.L = ONES R3; +R6.L = ONES R3; +R3.L = ONES R3; +CHECKREG r0, 0x0000000D; +CHECKREG r1, 0x0000000D; +CHECKREG r2, 0x0000000D; +CHECKREG r3, 0xBBBB000D; +CHECKREG r4, 0x0000000D; +CHECKREG r5, 0x0000000D; +CHECKREG r6, 0x0000000D; +CHECKREG r7, 0x0000000D; + +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0xcccc0000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ONES R4; +R1.L = ONES R4; +R2.L = ONES R4; +R3.L = ONES R4; +R7.L = ONES R4; +R5.L = ONES R4; +R6.L = ONES R4; +R4.L = ONES R4; +CHECKREG r0, 0x00000008; +CHECKREG r1, 0x00010008; +CHECKREG r2, 0x00020008; +CHECKREG r3, 0x00030008; +CHECKREG r4, 0xCCCC0008; +CHECKREG r5, 0x00050008; +CHECKREG r6, 0x00060008; +CHECKREG r7, 0x00070008; + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xaddd0000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ONES R5; +R1.L = ONES R5; +R2.L = ONES R5; +R3.L = ONES R5; +R4.L = ONES R5; +R7.L = ONES R5; +R6.L = ONES R5; +R5.L = ONES R5; +CHECKREG r0, 0xA001000B; +CHECKREG r1, 0xA001000B; +CHECKREG r2, 0xA002000B; +CHECKREG r3, 0xA003000B; +CHECKREG r4, 0xA004000B; +CHECKREG r5, 0xADDD000B; +CHECKREG r6, 0xA006000B; +CHECKREG r7, 0xA007000B; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xeeee0000; +imm32 r7, 0xb0070000; +R0.L = ONES R6; +R1.L = ONES R6; +R2.L = ONES R6; +R3.L = ONES R6; +R4.L = ONES R6; +R5.L = ONES R6; +R7.L = ONES R6; +R6.L = ONES R6; +CHECKREG r0, 0xB001000C; +CHECKREG r1, 0xB001000C; +CHECKREG r2, 0xB002000C; +CHECKREG r3, 0xB003000C; +CHECKREG r4, 0xB004000C; +CHECKREG r5, 0xB005000C; +CHECKREG r6, 0xEEEE000C; +CHECKREG r7, 0xB007000C; + +imm32 r0, 0xd0010001; +imm32 r1, 0xd0010002; +imm32 r2, 0xd0020003; +imm32 r3, 0xd0030014; +imm32 r4, 0xd0040005; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060007; +imm32 r7, 0xffff0000; +R0.L = ONES R7; +R1.L = ONES R7; +R2.L = ONES R7; +R3.L = ONES R7; +R4.L = ONES R7; +R5.L = ONES R7; +R6.L = ONES R7; +R7.L = ONES R7; + +CHECKREG r0, 0xD0010010; +CHECKREG r1, 0xD0010010; +CHECKREG r2, 0xD0020010; +CHECKREG r3, 0xD0030010; +CHECKREG r4, 0xD0040010; +CHECKREG r5, 0xD0050010; +CHECKREG r6, 0xD0060010; +CHECKREG r7, 0xFFFF0010; + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_pack.s b/tests/tcg/bfin/c_dsp32shift_pack.s new file mode 100644 index 0000000000000..56473094eff0d --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_pack.s @@ -0,0 +1,411 @@ +//Original:/testcases/core/c_dsp32shift_pack/c_dsp32shift_pack.dsp +// Spec Reference: dsp32shift pack +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x01230000; +imm32 r1, 0x02345678; +imm32 r2, 0x03456789; +imm32 r3, 0x0456789a; +imm32 r4, 0x056789ab; +imm32 r5, 0x06789abc; +imm32 r6, 0x0789abcd; +imm32 r7, 0x089abcde; +R1 = PACK( R0.L , R0.L ); +R2 = PACK( R1.L , R0.H ); +R3 = PACK( R2.H , R0.L ); +R4 = PACK( R3.H , R0.H ); +R5 = PACK( R4.L , R0.L ); +R6 = PACK( R5.L , R0.H ); +R7 = PACK( R6.H , R0.L ); +R0 = PACK( R7.H , R0.H ); +CHECKREG r1, 0x00000000; +CHECKREG r0, 0x00000123; +CHECKREG r2, 0x00000123; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000123; +CHECKREG r5, 0x01230000; +CHECKREG r6, 0x00000123; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11230001; +imm32 r1, 0x12345678; +imm32 r2, 0x1bcdef12; +imm32 r3, 0x1456789a; +imm32 r4, 0x1cdef012; +imm32 r5, 0x1456789a; +imm32 r6, 0x1789abcd; +imm32 r7, 0x189abcde; +R2 = PACK( R0.L , R1.L ); +R3 = PACK( R1.L , R1.H ); +R4 = PACK( R2.H , R1.L ); +R5 = PACK( R3.H , R1.H ); +R6 = PACK( R4.L , R1.L ); +R7 = PACK( R5.L , R1.H ); +R0 = PACK( R6.H , R1.L ); +R1 = PACK( R7.H , R1.H ); +CHECKREG r0, 0x56785678; +CHECKREG r1, 0x12341234; +CHECKREG r2, 0x00015678; +CHECKREG r3, 0x56781234; +CHECKREG r4, 0x00015678; +CHECKREG r5, 0x56781234; +CHECKREG r6, 0x56785678; +CHECKREG r7, 0x12341234; + +imm32 r0, 0x20230002; +imm32 r1, 0x21345678; +imm32 r2, 0x22456789; +imm32 r3, 0x2356789a; +imm32 r4, 0x246789ab; +imm32 r5, 0x25789abc; +imm32 r6, 0x2689abcd; +imm32 r7, 0x279abcde; +R3 = PACK( R0.L , R2.L ); +R4 = PACK( R1.L , R2.H ); +R5 = PACK( R2.H , R2.L ); +R6 = PACK( R3.H , R2.H ); +R7 = PACK( R4.L , R2.L ); +R0 = PACK( R5.L , R2.H ); +R1 = PACK( R6.H , R2.L ); +R2 = PACK( R7.H , R2.H ); +CHECKREG r0, 0x67892245; +CHECKREG r1, 0x00026789; +CHECKREG r2, 0x22452245; +CHECKREG r3, 0x00026789; +CHECKREG r4, 0x56782245; +CHECKREG r5, 0x22456789; +CHECKREG r6, 0x00022245; +CHECKREG r7, 0x22456789; + +imm32 r0, 0x31230003; +imm32 r1, 0x31345678; +imm32 r2, 0x31456789; +imm32 r3, 0x3156789a; +imm32 r4, 0x316789ab; +imm32 r5, 0x31789abc; +imm32 r6, 0x3189abcd; +imm32 r7, 0x311abcde; +R4 = PACK( R0.L , R3.L ); +R5 = PACK( R1.L , R3.H ); +R6 = PACK( R2.H , R3.L ); +R7 = PACK( R3.H , R3.H ); +R0 = PACK( R4.L , R3.L ); +R1 = PACK( R5.L , R3.H ); +R2 = PACK( R6.H , R3.L ); +R3 = PACK( R7.H , R3.H ); +CHECKREG r0, 0x789A789A; +CHECKREG r1, 0x31563156; +CHECKREG r2, 0x3145789A; +CHECKREG r3, 0x31563156; +CHECKREG r4, 0x0003789A; +CHECKREG r5, 0x56783156; +CHECKREG r6, 0x3145789A; +CHECKREG r7, 0x31563156; + +imm32 r0, 0x41230004; +imm32 r1, 0x42345678; +imm32 r2, 0x43456789; +imm32 r3, 0x4456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x46789abc; +imm32 r6, 0x4789abcd; +imm32 r7, 0x489abcde; +R0 = PACK( R0.L , R4.L ); +R1 = PACK( R1.L , R4.H ); +R2 = PACK( R2.H , R4.L ); +R3 = PACK( R3.H , R4.H ); +R4 = PACK( R4.L , R4.L ); +R5 = PACK( R5.L , R4.H ); +R6 = PACK( R6.H , R4.L ); +R7 = PACK( R7.H , R4.H ); +CHECKREG r0, 0x000489AB; +CHECKREG r1, 0x56784567; +CHECKREG r2, 0x434589AB; +CHECKREG r3, 0x44564567; +CHECKREG r4, 0x89AB89AB; +CHECKREG r5, 0x9ABC89AB; +CHECKREG r6, 0x478989AB; +CHECKREG r7, 0x489A89AB; + +imm32 r0, 0x51230005; +imm32 r1, 0x52345678; +imm32 r2, 0x53456789; +imm32 r3, 0x5456789a; +imm32 r4, 0x556789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x5789abcd; +imm32 r7, 0x589abcde; +R6 = PACK( R0.L , R5.L ); +R7 = PACK( R1.L , R5.H ); +R0 = PACK( R2.H , R5.L ); +R1 = PACK( R3.H , R5.H ); +R2 = PACK( R4.L , R5.L ); +R3 = PACK( R5.L , R5.H ); +R4 = PACK( R6.H , R5.L ); +R5 = PACK( R7.H , R5.H ); +CHECKREG r0, 0x53459ABC; +CHECKREG r1, 0x54565678; +CHECKREG r2, 0x89AB9ABC; +CHECKREG r3, 0x9ABC5678; +CHECKREG r4, 0x00059ABC; +CHECKREG r5, 0x56785678; +CHECKREG r6, 0x00059ABC; +CHECKREG r7, 0x56785678; + +imm32 r0, 0x61230006; +imm32 r1, 0x62345678; +imm32 r2, 0x63456789; +imm32 r3, 0x6456789a; +imm32 r4, 0x656789ab; +imm32 r5, 0x66789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x689abcde; +R7 = PACK( R0.L , R6.L ); +R0 = PACK( R1.L , R6.H ); +R1 = PACK( R2.H , R6.L ); +R2 = PACK( R3.H , R6.H ); +R3 = PACK( R4.L , R6.L ); +R4 = PACK( R5.L , R6.H ); +R5 = PACK( R6.H , R6.L ); +R6 = PACK( R7.H , R6.H ); +CHECKREG r0, 0x56786789; +CHECKREG r1, 0x6345ABCD; +CHECKREG r2, 0x64566789; +CHECKREG r3, 0x89ABABCD; +CHECKREG r4, 0x9ABC6789; +CHECKREG r5, 0x6789ABCD; +CHECKREG r6, 0x00066789; +CHECKREG r7, 0x0006ABCD; + +imm32 r0, 0x71230007; +imm32 r1, 0x72345678; +imm32 r2, 0x73456789; +imm32 r3, 0x7456789a; +imm32 r4, 0x756789ab; +imm32 r5, 0x76789abc; +imm32 r6, 0x7789abcd; +imm32 r7, 0x789abcde; +R0 = PACK( R0.L , R7.L ); +R1 = PACK( R1.L , R7.H ); +R2 = PACK( R2.H , R7.L ); +R3 = PACK( R3.H , R7.H ); +R4 = PACK( R4.L , R7.L ); +R5 = PACK( R5.L , R7.H ); +R6 = PACK( R6.H , R7.L ); +R7 = PACK( R7.H , R7.H ); +CHECKREG r0, 0x0007BCDE; +CHECKREG r1, 0x5678789A; +CHECKREG r2, 0x7345BCDE; +CHECKREG r3, 0x7456789A; +CHECKREG r4, 0x89ABBCDE; +CHECKREG r5, 0x9ABC789A; +CHECKREG r6, 0x7789BCDE; +CHECKREG r7, 0x789A789A; + +imm32 r0, 0x81230008; +imm32 r1, 0x82345678; +imm32 r2, 0x83456789; +imm32 r3, 0x8456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x8789abcd; +imm32 r7, 0x889abcde; +R0 = PACK( R0.L , R0.L ); +R1 = PACK( R1.L , R0.H ); +R2 = PACK( R2.H , R0.L ); +R3 = PACK( R3.H , R0.H ); +R4 = PACK( R4.L , R0.L ); +R5 = PACK( R5.L , R0.H ); +R6 = PACK( R6.H , R0.L ); +R7 = PACK( R7.H , R0.H ); +CHECKREG r0, 0x00080008; +CHECKREG r1, 0x56780008; +CHECKREG r2, 0x83450008; +CHECKREG r3, 0x84560008; +CHECKREG r4, 0x89AB0008; +CHECKREG r5, 0x9ABC0008; +CHECKREG r6, 0x87890008; +CHECKREG r7, 0x889A0008; + +imm32 r0, 0x91230009; +imm32 r1, 0x92345678; +imm32 r2, 0x93456789; +imm32 r3, 0x9456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0x9789abcd; +imm32 r7, 0x989abcde; +R0 = PACK( R0.L , R1.L ); +R1 = PACK( R1.L , R1.H ); +R2 = PACK( R2.H , R1.L ); +R3 = PACK( R3.H , R1.H ); +R4 = PACK( R4.L , R1.L ); +R5 = PACK( R5.L , R1.H ); +R6 = PACK( R6.H , R1.L ); +R7 = PACK( R7.H , R1.H ); +CHECKREG r0, 0x00095678; +CHECKREG r1, 0x56789234; +CHECKREG r2, 0x93459234; +CHECKREG r3, 0x94565678; +CHECKREG r4, 0x89AB9234; +CHECKREG r5, 0x9ABC5678; +CHECKREG r6, 0x97899234; +CHECKREG r7, 0x989A5678; + + +imm32 r0, 0xa123000a; +imm32 r1, 0xa2345678; +imm32 r2, 0xa3456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xa56789ab; +imm32 r5, 0xa6789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xa89abcde; +R0 = PACK( R0.L , R2.L ); +R1 = PACK( R1.L , R2.H ); +R2 = PACK( R2.H , R2.L ); +R3 = PACK( R3.H , R2.H ); +R4 = PACK( R4.L , R2.L ); +R5 = PACK( R5.L , R2.H ); +R6 = PACK( R6.H , R2.L ); +R7 = PACK( R7.H , R2.H ); +CHECKREG r0, 0x000A6789; +CHECKREG r1, 0x5678A345; +CHECKREG r2, 0xA3456789; +CHECKREG r3, 0xA456A345; +CHECKREG r4, 0x89AB6789; +CHECKREG r5, 0x9ABCA345; +CHECKREG r6, 0xA7896789; +CHECKREG r7, 0xA89AA345; + +imm32 r0, 0xb123000b; +imm32 r1, 0xb2345678; +imm32 r2, 0xb3456789; +imm32 r3, 0xb456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xb6789abc; +imm32 r6, 0xb789abcd; +imm32 r7, 0xb89abcde; +R0 = PACK( R0.L , R3.L ); +R1 = PACK( R1.L , R3.H ); +R2 = PACK( R2.H , R3.L ); +R3 = PACK( R3.H , R3.H ); +R4 = PACK( R4.L , R3.L ); +R5 = PACK( R5.L , R3.H ); +R6 = PACK( R6.H , R3.L ); +R7 = PACK( R7.H , R3.H ); +CHECKREG r0, 0x000B789A; +CHECKREG r1, 0x5678B456; +CHECKREG r2, 0xB345789A; +CHECKREG r3, 0xB456B456; +CHECKREG r4, 0x89ABB456; +CHECKREG r5, 0x9ABCB456; +CHECKREG r6, 0xB789B456; +CHECKREG r7, 0xB89AB456; + +imm32 r0, 0xc123000c; +imm32 r1, 0xc2345678; +imm32 r2, 0xc3456789; +imm32 r3, 0xc456789a; +imm32 r4, 0xc56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xc789abcd; +imm32 r7, 0xc89abcde; +R0 = PACK( R0.L , R4.L ); +R1 = PACK( R1.L , R4.H ); +R2 = PACK( R2.H , R4.L ); +R3 = PACK( R3.H , R4.H ); +R4 = PACK( R4.L , R4.L ); +R5 = PACK( R5.L , R4.H ); +R6 = PACK( R6.H , R4.L ); +R7 = PACK( R7.H , R4.H ); +CHECKREG r0, 0x000C89AB; +CHECKREG r1, 0x5678C567; +CHECKREG r2, 0xC34589AB; +CHECKREG r3, 0xC456C567; +CHECKREG r4, 0x89AB89AB; +CHECKREG r5, 0x9ABC89AB; +CHECKREG r6, 0xC78989AB; +CHECKREG r7, 0xC89A89AB; + +imm32 r0, 0xd123000d; +imm32 r1, 0xd2345678; +imm32 r2, 0xd3456789; +imm32 r3, 0xd456789a; +imm32 r4, 0xd56789ab; +imm32 r5, 0xd6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xd89abcde; +R0 = PACK( R0.L , R5.L ); +R1 = PACK( R1.L , R5.H ); +R2 = PACK( R2.H , R5.L ); +R3 = PACK( R3.H , R5.H ); +R4 = PACK( R4.L , R5.L ); +R5 = PACK( R5.L , R5.H ); +R6 = PACK( R6.H , R5.L ); +R7 = PACK( R7.H , R5.H ); +CHECKREG r0, 0x000D9ABC; +CHECKREG r1, 0x5678D678; +CHECKREG r2, 0xD3459ABC; +CHECKREG r3, 0xD456D678; +CHECKREG r4, 0x89AB9ABC; +CHECKREG r5, 0x9ABCD678; +CHECKREG r6, 0xD789D678; +CHECKREG r7, 0xD89A9ABC; + + +imm32 r0, 0xe123000e; +imm32 r1, 0xe2345678; +imm32 r2, 0xe3456789; +imm32 r3, 0xe456789a; +imm32 r4, 0xe56789ab; +imm32 r5, 0xe6789abc; +imm32 r6, 0xe789abcd; +imm32 r7, 0xe89abcde; +R0 = PACK( R0.L , R6.L ); +R1 = PACK( R1.L , R6.H ); +R2 = PACK( R2.H , R6.L ); +R3 = PACK( R3.H , R6.H ); +R4 = PACK( R4.L , R6.L ); +R5 = PACK( R5.L , R6.H ); +R6 = PACK( R6.H , R6.L ); +R7 = PACK( R7.H , R6.H ); +CHECKREG r0, 0x000EABCD; +CHECKREG r1, 0x5678E789; +CHECKREG r2, 0xE345ABCD; +CHECKREG r3, 0xE456E789; +CHECKREG r4, 0x89ABABCD; +CHECKREG r5, 0x9ABCE789; +CHECKREG r6, 0xE789ABCD; +CHECKREG r7, 0xE89AE789; + +imm32 r0, 0xf123000f; +imm32 r1, 0xf2345678; +imm32 r2, 0xf3456789; +imm32 r3, 0xf456789a; +imm32 r4, 0xf56789ab; +imm32 r5, 0xf6789abc; +imm32 r6, 0xf789abcd; +imm32 r7, 0xf89abcde; +R0 = PACK( R0.L , R7.L ); +R1 = PACK( R1.L , R7.H ); +R2 = PACK( R2.H , R7.L ); +R3 = PACK( R3.H , R7.H ); +R4 = PACK( R4.L , R7.L ); +R5 = PACK( R5.L , R7.H ); +R6 = PACK( R6.H , R7.L ); +R7 = PACK( R7.H , R7.H ); +CHECKREG r0, 0x000FBCDE; +CHECKREG r1, 0x5678F89A; +CHECKREG r2, 0xF345BCDE; +CHECKREG r3, 0xF456F89A; +CHECKREG r4, 0x89ABBCDE; +CHECKREG r5, 0x9ABCF89A; +CHECKREG r6, 0xF789BCDE; +CHECKREG r7, 0xF89AF89A; +pass diff --git a/tests/tcg/bfin/c_dsp32shift_rot.s b/tests/tcg/bfin/c_dsp32shift_rot.s new file mode 100644 index 0000000000000..d4b2ff293f4ed --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_rot.s @@ -0,0 +1,427 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot/c_dsp32shift_rot.dsp +// Spec Reference: dsp32shift rot +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1 = ROT R0 BY R0.L; + R2 = ROT R1 BY R0.L; + R3 = ROT R2 BY R0.L; + R4 = ROT R3 BY R0.L; + R5 = ROT R4 BY R0.L; + R6 = ROT R5 BY R0.L; + R7 = ROT R6 BY R0.L; + R0 = ROT R7 BY R0.L; + CHECKREG r1, 0x02460002; + CHECKREG r0, 0x23000100; + CHECKREG r2, 0x048C0004; + CHECKREG r3, 0x09180008; + CHECKREG r4, 0x12300010; + CHECKREG r5, 0x24600020; + CHECKREG r6, 0x48C00040; + CHECKREG r7, 0x91800080; + + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1.L = 15; + R2 = ROT R0 BY R1.L; + R3 = ROT R1 BY R1.L; + R4 = ROT R2 BY R1.L; + R5 = ROT R3 BY R1.L; + R6 = ROT R4 BY R1.L; + R7 = ROT R5 BY R1.L; + R0 = ROT R6 BY R1.L; + R1 = ROT R7 BY R1.L; + CHECKREG r0, 0x2C04C400; + CHECKREG r1, 0x5C489000; + CHECKREG r2, 0x8000C048; + CHECKREG r3, 0x0007C48D; + CHECKREG r4, 0x60242000; + CHECKREG r5, 0xE2468001; + CHECKREG r6, 0x10005809; + CHECKREG r7, 0x4000B891; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2 = 16; + R3 = ROT R0 BY R2.L; + R4 = ROT R1 BY R2.L; + R5 = ROT R2 BY R2.L; + R6 = ROT R3 BY R2.L; + R7 = ROT R4 BY R2.L; + R0 = ROT R5 BY R2.L; + R1 = ROT R6 BY R2.L; + R2 = ROT R7 BY R2.L; + CHECKREG r0, 0x00000008; + CHECKREG r1, 0x00010048; + CHECKREG r2, 0x2B3CC48D; + CHECKREG r3, 0x00020091; + CHECKREG r4, 0x5678891A; + CHECKREG r5, 0x00100000; + CHECKREG r6, 0x00910001; + CHECKREG r7, 0x891A2B3C; + + imm32 r0, 0x01230003; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R3.L = 31; + R4 = ROT R0 BY R3.L; + R5 = ROT R1 BY R3.L; + R6 = ROT R2 BY R3.L; + R7 = ROT R3 BY R3.L; + R0 = ROT R4 BY R3.L; + R1 = ROT R5 BY R3.L; + R2 = ROT R6 BY R3.L; + R3 = ROT R7 BY R3.L; + CHECKREG r0, 0x60123000; + CHECKREG r1, 0x11234567; + CHECKREG r2, 0x62345678; + CHECKREG r3, 0xE3456001; + CHECKREG r4, 0x8048C000; + CHECKREG r5, 0x448D159E; + CHECKREG r6, 0x88D159E2; + CHECKREG r7, 0x8D158007; + + imm32 r0, 0x01230004; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; + R4 = ROT R4 BY R4.L; + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x80918002; + CHECKREG r1, 0x091A2B3C; + CHECKREG r2, 0x11A2B3C4; + CHECKREG r3, 0x9A2B3C4D; + CHECKREG r4, 0x22B3FFFF; + CHECKREG r5, 0xAB3C4D5E; + CHECKREG r6, 0x33C4D5E6; + CHECKREG r7, 0xBC4D5E6F; + + imm32 r0, 0x01230005; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -15; + R6 = ROT R0 BY R5.L; + R7 = ROT R1 BY R5.L; + R0 = ROT R2 BY R5.L; + R1 = ROT R3 BY R5.L; + R2 = ROT R4 BY R5.L; + R3 = ROT R5 BY R5.L; + R4 = ROT R6 BY R5.L; + R5 = ROT R7 BY R5.L; + CHECKREG r0, 0x9E26468A; + CHECKREG r1, 0xE26A68AC; + CHECKREG r2, 0x26AE8ACF; + CHECKREG r3, 0xFFC4ACF1; + CHECKREG r4, 0x091A0028; + CHECKREG r5, 0x91A0B3C0; + CHECKREG r6, 0x00140246; + CHECKREG r7, 0x59E02468; + + imm32 r0, 0x01230006; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -16; + R7 = ROT R0 BY R6.L; + R0 = ROT R1 BY R6.L; + R1 = ROT R2 BY R6.L; + R2 = ROT R3 BY R6.L; + R3 = ROT R4 BY R6.L; + R4 = ROT R5 BY R6.L; + R5 = ROT R6 BY R6.L; + R6 = ROT R7 BY R6.L; + CHECKREG r0, 0xACF01234; + CHECKREG r1, 0xCF122345; + CHECKREG r2, 0xF1343456; + CHECKREG r3, 0x13564567; + CHECKREG r4, 0x35795678; + CHECKREG r5, 0xFFE16789; + CHECKREG r6, 0x0247000C; + CHECKREG r7, 0x000C0123; + + imm32 r0, 0x01230007; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R7.L = -27; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x48C001C0; + CHECKREG r1, 0x8D159E02; + CHECKREG r2, 0xD159E244; + CHECKREG r3, 0x159E2686; + CHECKREG r4, 0x59E26AE8; + CHECKREG r5, 0x9E26AF2A; + CHECKREG r6, 0xE26AF36C; + CHECKREG r7, 0x26BFF96F; + + imm32 r0, 0x01230008; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R0.L = 7; +//r0 = rot (r0 by rl0); + R1 = ROT R1 BY R0.L; + R2 = ROT R2 BY R0.L; + R3 = ROT R3 BY R0.L; + R4 = ROT R4 BY R0.L; + R5 = ROT R5 BY R0.L; + R6 = ROT R6 BY R0.L; + R7 = ROT R7 BY R0.L; + CHECKREG r0, 0x01230007; + CHECKREG r1, 0x1A2B3C04; + CHECKREG r2, 0xA2B3C4C8; + CHECKREG r3, 0x2B3C4D4D; + CHECKREG r4, 0xB3C4D591; + CHECKREG r5, 0x3C4D5E15; + CHECKREG r6, 0xC4D5E6D9; + CHECKREG r7, 0x4D5E6F5E; + + imm32 r0, 0x01230009; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1.L = 16; + R0 = ROT R0 BY R1.L; +//r1 = rot (r1 by rl1); + R2 = ROT R2 BY R1.L; + R3 = ROT R3 BY R1.L; + R4 = ROT R4 BY R1.L; + R5 = ROT R5 BY R1.L; + R6 = ROT R6 BY R1.L; + R7 = ROT R7 BY R1.L; + CHECKREG r0, 0x00090091; + CHECKREG r1, 0x12340010; + CHECKREG r2, 0x678991A2; + CHECKREG r3, 0x789A9A2B; + CHECKREG r4, 0x89AB22B3; + CHECKREG r5, 0x9ABCAB3C; + CHECKREG r6, 0xABCD33C4; + CHECKREG r7, 0xBCDEBC4D; + + imm32 r0, 0x0123000a; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 30; + R0 = ROT R0 BY R2.L; + R1 = ROT R1 BY R2.L; +//r2 = rot (r2 by rl2); + R3 = ROT R3 BY R2.L; + R4 = ROT R4 BY R2.L; + R5 = ROT R5 BY R2.L; + R6 = ROT R6 BY R2.L; + R7 = ROT R7 BY R2.L; + CHECKREG r0, 0x80246001; + CHECKREG r1, 0x02468ACF; + CHECKREG r2, 0x2345001E; + CHECKREG r3, 0x868ACF13; + CHECKREG r4, 0xC8ACF135; + CHECKREG r5, 0x0ACF1357; + CHECKREG r6, 0x6CF13579; + CHECKREG r7, 0xAF13579B; + + imm32 r0, 0x0123000b; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R3.L = 31; + R0 = ROT R0 BY R3.L; + R1 = ROT R1 BY R3.L; + R2 = ROT R2 BY R3.L; +//r3 = rot (r3 by rl3); + R4 = ROT R4 BY R3.L; + R5 = ROT R5 BY R3.L; + R6 = ROT R6 BY R3.L; + R7 = ROT R7 BY R3.L; + CHECKREG r0, 0xC048C002; + CHECKREG r1, 0x448D159E; + CHECKREG r2, 0x88D159E2; + CHECKREG r3, 0x3456001F; + CHECKREG r4, 0x9159E26A; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000c; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -2; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; +//r4 = rot (r4 by rl4); + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x4048C003; + CHECKREG r1, 0x048D159E; + CHECKREG r2, 0x88D159E2; + CHECKREG r3, 0x0D159E26; + CHECKREG r4, 0x4567FFFE; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000d; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -17; + R0 = ROT R0 BY R5.L; + R1 = ROT R1 BY R5.L; + R2 = ROT R2 BY R5.L; + R3 = ROT R3 BY R5.L; + R4 = ROT R4 BY R5.L; +//r5 = rot (r5 by rl5); + R6 = ROT R6 BY R5.L; + R7 = ROT R7 BY R5.L; + CHECKREG r0, 0x000D8091; + CHECKREG r1, 0x5678891A; + CHECKREG r2, 0x678911A2; + CHECKREG r3, 0x789A9A2B; + CHECKREG r4, 0x89AB22B3; + CHECKREG r5, 0x5678FFEF; + CHECKREG r6, 0xABCDB3C4; + CHECKREG r7, 0xBCDEBC4D; + + imm32 r0, 0x0123000e; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -30; + R0 = ROT R0 BY R6.L; + R1 = ROT R1 BY R6.L; + R2 = ROT R2 BY R6.L; + R3 = ROT R3 BY R6.L; + R4 = ROT R4 BY R6.L; + R5 = ROT R5 BY R6.L; +//r6 = rot (r6 by rl6); + R7 = ROT R7 BY R6.L; + CHECKREG r0, 0x09180070; + CHECKREG r1, 0x91A2B3C0; + CHECKREG r2, 0x1A2B3C48; + CHECKREG r3, 0xA2B3C4D4; + CHECKREG r4, 0x2B3C4D5D; + CHECKREG r5, 0xB3C4D5E1; + CHECKREG r6, 0x6789FFE2; + CHECKREG r7, 0xC4D5E6F1; + + imm32 r0, 0x0123000f; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R7.L = -31; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x048C003E; + CHECKREG r1, 0x48D159E0; + CHECKREG r2, 0x8D159E24; + CHECKREG r3, 0xD159E268; + CHECKREG r4, 0x159E26AC; + CHECKREG r5, 0x59E26AF2; + CHECKREG r6, 0x9E26AF36; + CHECKREG r7, 0xE26BFF86; + + pass diff --git a/tests/tcg/bfin/c_dsp32shift_rot_mix.s b/tests/tcg/bfin/c_dsp32shift_rot_mix.s new file mode 100644 index 0000000000000..5ade06aa827fd --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_rot_mix.s @@ -0,0 +1,375 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot_mix/c_dsp32shift_rot_mix.dsp +// Spec Reference: dsp32shift rot +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0x01230000; + imm32 r1, 0x12345678; + imm32 r2, 0x83456789; + imm32 r3, 0x9456789a; + imm32 r4, 0xa56789ab; + imm32 r5, 0xb6789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0xd89abcde; + R1 = ROT R0 BY R0.L; + R2 = ROT R1 BY R0.L; + R3 = ROT R2 BY R0.L; + R4 = ROT R3 BY R0.L; + R5 = ROT R4 BY R0.L; + R6 = ROT R5 BY R0.L; + R7 = ROT R6 BY R0.L; + R0 = ROT R7 BY R0.L; + CHECKREG r0, 0x01230000; + CHECKREG r1, 0x01230000; + CHECKREG r2, 0x01230000; + CHECKREG r3, 0x01230000; + CHECKREG r4, 0x01230000; + CHECKREG r5, 0x01230000; + CHECKREG r6, 0x01230000; + CHECKREG r7, 0x01230000; + + imm32 r0, 0x11230001; + imm32 r1, 0xc2345678; + imm32 r2, 0xd3456789; + imm32 r3, 0xb456789a; + imm32 r4, 0x056789ab; + imm32 r5, 0x36789abc; + imm32 r6, 0x1789abcd; + imm32 r7, 0x189abcde; + R1.L = 5; + R2 = ROT R0 BY R1.L; + R3 = ROT R1 BY R1.L; + R4 = ROT R2 BY R1.L; + R5 = ROT R3 BY R1.L; + R6 = ROT R4 BY R1.L; + R7 = ROT R5 BY R1.L; + R0 = ROT R6 BY R1.L; + R1 = ROT R7 BY R1.L; + CHECKREG r0, 0x00108908; + CHECKREG r1, 0x005613A0; + CHECKREG r2, 0x24600021; + CHECKREG r3, 0x468000AC; + CHECKREG r4, 0x8C000422; + CHECKREG r5, 0xD0001584; + CHECKREG r6, 0x80008448; + CHECKREG r7, 0x0002B09D; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x8456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0x789abcde; + R2 = 15; + R3 = ROT R0 BY R2.L; + R4 = ROT R1 BY R2.L; + R5 = ROT R2 BY R2.L; + R6 = ROT R3 BY R2.L; + R7 = ROT R4 BY R2.L; + R0 = ROT R5 BY R2.L; + R1 = ROT R6 BY R2.L; + R2 = ROT R7 BY R2.L; + CHECKREG r0, 0xC0000001; + CHECKREG r1, 0x10006009; + CHECKREG r2, 0x45678891; + CHECKREG r3, 0x80010048; + CHECKREG r4, 0x2B3C448D; + CHECKREG r5, 0x00078000; + CHECKREG r6, 0x80242000; + CHECKREG r7, 0x22468ACF; + + imm32 r0, 0x21230003; + imm32 r1, 0x22345678; + imm32 r2, 0x23456789; + imm32 r3, 0x2456789a; + imm32 r4, 0x256789ab; + imm32 r5, 0x26789abc; + imm32 r6, 0x2789abcd; + imm32 r7, 0x289abcde; + R3.L = 24; + R4 = ROT R0 BY R3.L; + R5 = ROT R1 BY R3.L; + R6 = ROT R2 BY R3.L; + R7 = ROT R3 BY R3.L; + R0 = ROT R4 BY R3.L; + R1 = ROT R5 BY R3.L; + R2 = ROT R6 BY R3.L; + R3 = ROT R7 BY R3.L; + CHECKREG r0, 0x8001C848; + CHECKREG r1, 0x2BBC088D; + CHECKREG r2, 0xB34488D1; + CHECKREG r3, 0x000C4915; + CHECKREG r4, 0x03909180; + CHECKREG r5, 0x78111A2B; + CHECKREG r6, 0x8911A2B3; + CHECKREG r7, 0x18922B00; + + imm32 r0, 0x01230004; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; + R4 = ROT R4 BY R4.L; + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x80918002; + CHECKREG r1, 0x091A2B3C; + CHECKREG r2, 0x11A2B3C4; + CHECKREG r3, 0x9A2B3C4D; + CHECKREG r4, 0x22B3FFFF; + CHECKREG r5, 0xAB3C4D5E; + CHECKREG r6, 0x33C4D5E6; + CHECKREG r7, 0xBC4D5E6F; + + imm32 r0, 0x01230005; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -6; + R6 = ROT R0 BY R5.L; + R7 = ROT R1 BY R5.L; + R0 = ROT R2 BY R5.L; + R1 = ROT R3 BY R5.L; + R2 = ROT R4 BY R5.L; + R3 = ROT R5 BY R5.L; + R4 = ROT R6 BY R5.L; + R5 = ROT R7 BY R5.L; + CHECKREG r0, 0x4C8D159E; + CHECKREG r1, 0xD0D159E2; + CHECKREG r2, 0x59159E26; + CHECKREG r3, 0xD559E3FF; + CHECKREG r4, 0x04A01230; + CHECKREG r5, 0xCB012345; + CHECKREG r6, 0x28048C00; + CHECKREG r7, 0xC048D159; + + imm32 r0, 0x01230006; + imm32 r1, 0x82345678; + imm32 r2, 0x73456789; + imm32 r3, 0x3456789a; + imm32 r4, 0xd56789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0x789abcde; + R6.L = -15; + R7 = ROT R0 BY R6.L; + R0 = ROT R1 BY R6.L; + R1 = ROT R2 BY R6.L; + R2 = ROT R3 BY R6.L; + R3 = ROT R4 BY R6.L; + R4 = ROT R5 BY R6.L; + R5 = ROT R6 BY R6.L; + R6 = ROT R7 BY R6.L; + CHECKREG r0, 0x59E10468; + CHECKREG r1, 0x9E26E68A; + CHECKREG r2, 0xE26A68AC; + CHECKREG r3, 0x26AFAACF; + CHECKREG r4, 0x6AF0ACF1; + CHECKREG r5, 0xFFC58F13; + CHECKREG r6, 0x091A0030; + CHECKREG r7, 0x00180246; + + imm32 r0, 0x01230007; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R7.L = -27; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x48C001C0; + CHECKREG r1, 0x8D159E02; + CHECKREG r2, 0xD159E244; + CHECKREG r3, 0x159E2686; + CHECKREG r4, 0x59E26AE8; + CHECKREG r5, 0x9E26AF2A; + CHECKREG r6, 0xE26AF36C; + CHECKREG r7, 0x26BFF96F; + + imm32 r0, 0x01230008; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R0.L = 7; +//r0 = rot (r0 by rl0); + R1 = ROT R1 BY R0.L; + R2 = ROT R2 BY R0.L; + R3 = ROT R3 BY R0.L; + R4 = ROT R4 BY R0.L; + R5 = ROT R5 BY R0.L; + R6 = ROT R6 BY R0.L; + R7 = ROT R7 BY R0.L; + CHECKREG r0, 0x01230007; + CHECKREG r1, 0x1A2B3C04; + CHECKREG r2, 0xA2B3C4C8; + CHECKREG r3, 0x2B3C4D4D; + CHECKREG r4, 0xB3C4D591; + CHECKREG r5, 0x3C4D5E15; + CHECKREG r6, 0xC4D5E6D9; + CHECKREG r7, 0x4D5E6F5E; + + imm32 r0, 0x01230009; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1.L = 16; + R0 = ROT R0 BY R1.L; +//r1 = rot (r1 by rl1); + R2 = ROT R2 BY R1.L; + R3 = ROT R3 BY R1.L; + R4 = ROT R4 BY R1.L; + R5 = ROT R5 BY R1.L; + R6 = ROT R6 BY R1.L; + R7 = ROT R7 BY R1.L; + CHECKREG r0, 0x00090091; + CHECKREG r1, 0x12340010; + CHECKREG r2, 0x678991A2; + CHECKREG r3, 0x789A9A2B; + CHECKREG r4, 0x89AB22B3; + CHECKREG r5, 0x9ABCAB3C; + CHECKREG r6, 0xABCD33C4; + CHECKREG r7, 0xBCDEBC4D; + + imm32 r0, 0x0123000a; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 31; + R0 = ROT R0 BY R2.L; + R1 = ROT R1 BY R2.L; +//r2 = rot (r2 by rl2); + R3 = ROT R3 BY R2.L; + R4 = ROT R4 BY R2.L; + R5 = ROT R5 BY R2.L; + R6 = ROT R6 BY R2.L; + R7 = ROT R7 BY R2.L; + CHECKREG r0, 0x0048C002; + CHECKREG r1, 0x448D159E; + CHECKREG r2, 0x2345001F; + CHECKREG r3, 0x0D159E26; + CHECKREG r4, 0xD159E26A; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000c; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -2; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; +//r4 = rot (r4 by rl4); + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x4048C003; + CHECKREG r1, 0x048D159E; + CHECKREG r2, 0x88D159E2; + CHECKREG r3, 0x0D159E26; + CHECKREG r4, 0x4567FFFE; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000d; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -14; + R0 = ROT R0 BY R5.L; + R1 = ROT R1 BY R5.L; + R2 = ROT R2 BY R5.L; + R3 = ROT R3 BY R5.L; + R4 = ROT R4 BY R5.L; +//r5 = rot (r5 by rl5); + R6 = ROT R6 BY R5.L; + R7 = ROT R7 BY R5.L; + CHECKREG r0, 0x006C048C; + CHECKREG r1, 0xB3C048D1; + CHECKREG r2, 0x3C488D15; + CHECKREG r3, 0xC4D4D159; + CHECKREG r4, 0x4D5D159E; + CHECKREG r5, 0x5678FFF2; + CHECKREG r6, 0x5E699E26; + CHECKREG r7, 0xE6F5E26A; + + imm32 r0, 0x0123000e; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -16; + R0 = ROT R0 BY R6.L; + R1 = ROT R1 BY R6.L; + R2 = ROT R2 BY R6.L; + R3 = ROT R3 BY R6.L; + R4 = ROT R4 BY R6.L; + R5 = ROT R5 BY R6.L; +//r6 = rot (r6 by rl6); + R7 = ROT R7 BY R6.L; + CHECKREG r0, 0x001D0123; + CHECKREG r1, 0xACF01234; + CHECKREG r2, 0xCF122345; + CHECKREG r3, 0xF1343456; + CHECKREG r4, 0x13564567; + CHECKREG r5, 0x35795678; + CHECKREG r6, 0x6789FFF0; + CHECKREG r7, 0x79BD789A; + + pass diff --git a/tests/tcg/bfin/c_dsp32shift_signbits_r.s b/tests/tcg/bfin/c_dsp32shift_signbits_r.s new file mode 100644 index 0000000000000..6bdb7a0496a01 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_signbits_r.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_signbits_r/c_dsp32shift_signbits_r.dsp +// Spec Reference: dsp32shift signbits dregs +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0x88880000; +imm32 r1, 0x34560001; +imm32 r2, 0x08000002; +imm32 r3, 0x08000003; +imm32 r4, 0x08000004; +imm32 r5, 0x08000005; +imm32 r6, 0x08000006; +imm32 r7, 0x08000007; +R7.L = SIGNBITS R0; +R1.L = SIGNBITS R0; +R2.L = SIGNBITS R0; +R3.L = SIGNBITS R0; +R4.L = SIGNBITS R0; +R5.L = SIGNBITS R0; +R6.L = SIGNBITS R0; +R0.L = SIGNBITS R0; +CHECKREG r0, 0x88880000; +CHECKREG r1, 0x34560000; +CHECKREG r2, 0x08000000; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x08000000; +CHECKREG r5, 0x08000000; +CHECKREG r6, 0x08000000; +CHECKREG r7, 0x08000000; + +imm32 r0, 0x9999001E; +imm32 r1, 0x0000001E; +imm32 r2, 0x0000001E; +imm32 r3, 0x0000001E; +imm32 r4, 0x0000001E; +imm32 r5, 0x0000001E; +imm32 r6, 0x0000001E; +imm32 r7, 0x0000001E; +R0.L = SIGNBITS R1; +R7.L = SIGNBITS R1; +R2.L = SIGNBITS R1; +R3.L = SIGNBITS R1; +R4.L = SIGNBITS R1; +R5.L = SIGNBITS R1; +R6.L = SIGNBITS R1; +R1.L = SIGNBITS R1; +CHECKREG r0, 0x9999001A; +CHECKREG r1, 0x0000001A; +CHECKREG r2, 0x0000001A; +CHECKREG r3, 0x0000001A; +CHECKREG r4, 0x0000001A; +CHECKREG r5, 0x0000001A; +CHECKREG r6, 0x0000001A; +CHECKREG r7, 0x0000001A; + + +imm32 r0, 0x0aaae001; +imm32 r1, 0x0000e001; +imm32 r2, 0xaaaa000f; +imm32 r3, 0x0a00e003; +imm32 r4, 0x00a0e004; +imm32 r5, 0x00a0e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0b00e007; +R0.L = SIGNBITS R2; +R1.L = SIGNBITS R2; +R7.L = SIGNBITS R2; +R3.L = SIGNBITS R2; +R4.L = SIGNBITS R2; +R5.L = SIGNBITS R2; +R6.L = SIGNBITS R2; +R2.L = SIGNBITS R2; +CHECKREG r0, 0x0AAA0000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xAAAA0000; +CHECKREG r3, 0x0A000000; +CHECKREG r4, 0x00A00000; +CHECKREG r5, 0x00A00000; +CHECKREG r6, 0x0A000000; +CHECKREG r7, 0x0B000000; + +imm32 r0, 0x0b00f001; +imm32 r1, 0x0a00f001; +imm32 r2, 0x0b00f002; +imm32 r3, 0xbbbb0010; +imm32 r4, 0x0b00f004; +imm32 r5, 0x0b00f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x00b0f007; +R0.L = SIGNBITS R3; +R1.L = SIGNBITS R3; +R2.L = SIGNBITS R3; +R7.L = SIGNBITS R3; +R4.L = SIGNBITS R3; +R5.L = SIGNBITS R3; +R6.L = SIGNBITS R3; +R3.L = SIGNBITS R3; +CHECKREG r0, 0x0B000000; +CHECKREG r1, 0x0A000000; +CHECKREG r2, 0x0B000000; +CHECKREG r3, 0xBBBB0000; +CHECKREG r4, 0x0B000000; +CHECKREG r5, 0x0B000000; +CHECKREG r6, 0x0B000000; +CHECKREG r7, 0x00B00000; + +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0xcccc0000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = SIGNBITS R4; +R1.L = SIGNBITS R4; +R2.L = SIGNBITS R4; +R3.L = SIGNBITS R4; +R7.L = SIGNBITS R4; +R5.L = SIGNBITS R4; +R6.L = SIGNBITS R4; +R4.L = SIGNBITS R4; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020001; +CHECKREG r3, 0x00030001; +CHECKREG r4, 0xCCCC0001; +CHECKREG r5, 0x00050001; +CHECKREG r6, 0x00060001; +CHECKREG r7, 0x00070001; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xdddd0000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = SIGNBITS R5; +R1.L = SIGNBITS R5; +R2.L = SIGNBITS R5; +R3.L = SIGNBITS R5; +R4.L = SIGNBITS R5; +R7.L = SIGNBITS R5; +R6.L = SIGNBITS R5; +R5.L = SIGNBITS R5; +CHECKREG r0, 0xA0010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0xA0020001; +CHECKREG r3, 0xA0030001; +CHECKREG r4, 0xA0040001; +CHECKREG r5, 0xDDDD0001; +CHECKREG r6, 0xA0060001; +CHECKREG r7, 0xA0070001; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xeeee0000; +imm32 r7, 0xb0070000; +R0.L = SIGNBITS R6; +R1.L = SIGNBITS R6; +R2.L = SIGNBITS R6; +R3.L = SIGNBITS R6; +R4.L = SIGNBITS R6; +R5.L = SIGNBITS R6; +R7.L = SIGNBITS R6; +R6.L = SIGNBITS R6; +CHECKREG r0, 0xB0010002; +CHECKREG r1, 0xB0010002; +CHECKREG r2, 0xB0020002; +CHECKREG r3, 0xB0030002; +CHECKREG r4, 0xB0040002; +CHECKREG r5, 0xB0050002; +CHECKREG r6, 0xEEEE0002; +CHECKREG r7, 0xB0070002; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xffff0000; +R0.L = SIGNBITS R7; +R1.L = SIGNBITS R7; +R2.L = SIGNBITS R7; +R3.L = SIGNBITS R7; +R4.L = SIGNBITS R7; +R5.L = SIGNBITS R7; +R6.L = SIGNBITS R7; +R7.L = SIGNBITS R7; + +CHECKREG r0, 0xD001000F; +CHECKREG r1, 0xD001000F; +CHECKREG r2, 0xD002000F; +CHECKREG r3, 0xD003000F; +CHECKREG r4, 0xD004000F; +CHECKREG r5, 0xD005000F; +CHECKREG r6, 0xD006000F; +CHECKREG r7, 0xFFFF000F; +pass diff --git a/tests/tcg/bfin/c_dsp32shift_signbits_rh.s b/tests/tcg/bfin/c_dsp32shift_signbits_rh.s new file mode 100644 index 0000000000000..8ae46aeff143a --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_signbits_rh.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_signbits_rh/c_dsp32shift_signbits_rh.dsp +// Spec Reference: dsp32shift signbits dregs_hi +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xd1000000; +imm32 r1, 0xd2000001; +imm32 r2, 0xd3000002; +imm32 r3, 0xd4000003; +imm32 r4, 0xd5000004; +imm32 r5, 0xd6000005; +imm32 r6, 0xd7000006; +imm32 r7, 0xd8000007; +R0.L = SIGNBITS R0.H; +R1.L = SIGNBITS R0.H; +R2.L = SIGNBITS R0.H; +R3.L = SIGNBITS R0.H; +R4.L = SIGNBITS R0.H; +R5.L = SIGNBITS R0.H; +R6.L = SIGNBITS R0.H; +R7.L = SIGNBITS R0.H; +CHECKREG r0, 0xD1000001; +CHECKREG r1, 0xD2000001; +CHECKREG r2, 0xD3000001; +CHECKREG r3, 0xD4000001; +CHECKREG r4, 0xD5000001; +CHECKREG r5, 0xD6000001; +CHECKREG r6, 0xD7000001; +CHECKREG r7, 0xD8000001; + +imm32 r0, 0xe200d001; +imm32 r1, 0xe2000001; +imm32 r2, 0xe200d002; +imm32 r3, 0xe200d003; +imm32 r4, 0xe200d004; +imm32 r5, 0xe200d005; +imm32 r6, 0xe200d006; +imm32 r7, 0xe200d007; +R0.L = SIGNBITS R1.H; +R1.L = SIGNBITS R1.H; +R2.L = SIGNBITS R1.H; +R3.L = SIGNBITS R1.H; +R4.L = SIGNBITS R1.H; +R5.L = SIGNBITS R1.H; +R6.L = SIGNBITS R1.H; +R7.L = SIGNBITS R1.H; +CHECKREG r0, 0xE2000002; +CHECKREG r1, 0xE2000002; +CHECKREG r2, 0xE2000002; +CHECKREG r3, 0xE2000002; +CHECKREG r4, 0xE2000002; +CHECKREG r5, 0xE2000002; +CHECKREG r6, 0xE2000002; +CHECKREG r7, 0xE2000002; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0xf000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.L = SIGNBITS R2.H; +R1.L = SIGNBITS R2.H; +R2.L = SIGNBITS R2.H; +R3.L = SIGNBITS R2.H; +R4.L = SIGNBITS R2.H; +R5.L = SIGNBITS R2.H; +R6.L = SIGNBITS R2.H; +R7.L = SIGNBITS R2.H; +CHECKREG r0, 0x00000003; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0xF0000003; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000003; +CHECKREG r5, 0x00000003; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x0100f001; +imm32 r1, 0x0100f001; +imm32 r2, 0x0100f002; +imm32 r3, 0x01000010; +imm32 r4, 0x0100f004; +imm32 r5, 0x0100f005; +imm32 r6, 0x0100f006; +imm32 r7, 0x0100f007; +R0.L = SIGNBITS R3.H; +R1.L = SIGNBITS R3.H; +R2.L = SIGNBITS R3.H; +R3.L = SIGNBITS R3.H; +R4.L = SIGNBITS R3.H; +R5.L = SIGNBITS R3.H; +R6.L = SIGNBITS R3.H; +R7.L = SIGNBITS R3.H; +CHECKREG r0, 0x01000006; +CHECKREG r1, 0x01000006; +CHECKREG r2, 0x01000006; +CHECKREG r3, 0x01000006; +CHECKREG r4, 0x01000006; +CHECKREG r5, 0x01000006; +CHECKREG r6, 0x01000006; +CHECKREG r7, 0x01000006; + +imm32 r0, 0x04000000; +imm32 r1, 0x04010000; +imm32 r2, 0x04020000; +imm32 r3, 0x04030000; +imm32 r4, 0x04040000; +imm32 r5, 0x04050000; +imm32 r6, 0x04060000; +imm32 r7, 0x04070000; +R0.L = SIGNBITS R4.H; +R1.L = SIGNBITS R4.H; +R2.L = SIGNBITS R4.H; +R3.L = SIGNBITS R4.H; +R4.L = SIGNBITS R4.H; +R5.L = SIGNBITS R4.H; +R6.L = SIGNBITS R4.H; +R7.L = SIGNBITS R4.H; +CHECKREG r0, 0x04000004; +CHECKREG r1, 0x04010004; +CHECKREG r2, 0x04020004; +CHECKREG r3, 0x04030004; +CHECKREG r4, 0x04040004; +CHECKREG r5, 0x04050004; +CHECKREG r6, 0x04060004; +CHECKREG r7, 0x04070004; + +imm32 r0, 0xa5010000; +imm32 r1, 0xa5010001; +imm32 r2, 0xa5020000; +imm32 r3, 0xa5030000; +imm32 r4, 0xa5540000; +imm32 r5, 0xa5550000; +imm32 r6, 0xa5060000; +imm32 r7, 0xa5070000; +R0.L = SIGNBITS R5.H; +R1.L = SIGNBITS R5.H; +R2.L = SIGNBITS R5.H; +R3.L = SIGNBITS R5.H; +R4.L = SIGNBITS R5.H; +R5.L = SIGNBITS R5.H; +R6.L = SIGNBITS R5.H; +R7.L = SIGNBITS R5.H; +CHECKREG r0, 0xA5010000; +CHECKREG r1, 0xA5010000; +CHECKREG r2, 0xA5020000; +CHECKREG r3, 0xA5030000; +CHECKREG r4, 0xA5540000; +CHECKREG r5, 0xA5550000; +CHECKREG r6, 0xA5060000; +CHECKREG r7, 0xA5070000; + + +imm32 r0, 0xb6010000; +imm32 r1, 0xb6010000; +imm32 r2, 0xb602000f; +imm32 r3, 0xb6030000; +imm32 r4, 0xb6040000; +imm32 r5, 0xb6050000; +imm32 r6, 0xb6060000; +imm32 r7, 0xb6670000; +R0.L = SIGNBITS R6.H; +R1.L = SIGNBITS R6.H; +R2.L = SIGNBITS R6.H; +R3.L = SIGNBITS R6.H; +R4.L = SIGNBITS R6.H; +R5.L = SIGNBITS R6.H; +R6.L = SIGNBITS R6.H; +R7.L = SIGNBITS R6.H; +CHECKREG r0, 0xB6010000; +CHECKREG r1, 0xB6010000; +CHECKREG r2, 0xB6020000; +CHECKREG r3, 0xB6030000; +CHECKREG r4, 0xB6040000; +CHECKREG r5, 0xB6050000; +CHECKREG r6, 0xB6060000; +CHECKREG r7, 0xB6670000; + +imm32 r0, 0xd7010000; +imm32 r1, 0xd7010000; +imm32 r2, 0xd7020000; +imm32 r3, 0xd7030010; +imm32 r4, 0xd7040000; +imm32 r5, 0xd7050000; +imm32 r6, 0xd7060000; +imm32 r7, 0xd7070000; +R0.L = SIGNBITS R7.H; +R1.L = SIGNBITS R7.H; +R2.L = SIGNBITS R7.H; +R3.L = SIGNBITS R7.H; +R4.L = SIGNBITS R7.H; +R5.L = SIGNBITS R7.H; +R6.L = SIGNBITS R7.H; +R7.L = SIGNBITS R7.H; +CHECKREG r0, 0xD7010001; +CHECKREG r1, 0xD7010001; +CHECKREG r2, 0xD7020001; +CHECKREG r3, 0xD7030001; +CHECKREG r4, 0xD7040001; +CHECKREG r5, 0xD7050001; +CHECKREG r6, 0xD7060001; +CHECKREG r7, 0xD7070001; + + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_signbits_rl.s b/tests/tcg/bfin/c_dsp32shift_signbits_rl.s new file mode 100644 index 0000000000000..3f3ccfd994859 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_signbits_rl.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_signbits_rl/c_dsp32shift_signbits_rl.dsp +// Spec Reference: dsp32shift signbits dregs_lo +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R7.L = SIGNBITS R0.L; +R1.L = SIGNBITS R0.L; +R2.L = SIGNBITS R0.L; +R3.L = SIGNBITS R0.L; +R4.L = SIGNBITS R0.L; +R5.L = SIGNBITS R0.L; +R6.L = SIGNBITS R0.L; +R0.L = SIGNBITS R0.L; +CHECKREG r1, 0x0000000F; +CHECKREG r0, 0x0000000F; +CHECKREG r2, 0x0000000F; +CHECKREG r3, 0x0000000F; +CHECKREG r4, 0x0000000F; +CHECKREG r5, 0x0000000F; +CHECKREG r6, 0x0000000F; +CHECKREG r7, 0x0000000F; + +imm32 r0, 0x00000001; +imm32 r1, 0x00008001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = SIGNBITS R1.L; +R7.L = SIGNBITS R1.L; +R2.L = SIGNBITS R1.L; +R3.L = SIGNBITS R1.L; +R4.L = SIGNBITS R1.L; +R5.L = SIGNBITS R1.L; +R6.L = SIGNBITS R1.L; +R1.L = SIGNBITS R1.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000c00f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = SIGNBITS R2.L; +R1.L = SIGNBITS R2.L; +R7.L = SIGNBITS R2.L; +R3.L = SIGNBITS R2.L; +R4.L = SIGNBITS R2.L; +R5.L = SIGNBITS R2.L; +R6.L = SIGNBITS R2.L; +R2.L = SIGNBITS R2.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000e10; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = SIGNBITS R3.L; +R1.L = SIGNBITS R3.L; +R2.L = SIGNBITS R3.L; +R7.L = SIGNBITS R3.L; +R4.L = SIGNBITS R3.L; +R5.L = SIGNBITS R3.L; +R6.L = SIGNBITS R3.L; +R3.L = SIGNBITS R3.L; +CHECKREG r0, 0x00000003; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000003; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000003; +CHECKREG r5, 0x00000003; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x0000f000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = SIGNBITS R4.L; +R1.L = SIGNBITS R4.L; +R2.L = SIGNBITS R4.L; +R3.L = SIGNBITS R4.L; +R7.L = SIGNBITS R4.L; +R5.L = SIGNBITS R4.L; +R6.L = SIGNBITS R4.L; +R4.L = SIGNBITS R4.L; +CHECKREG r0, 0x00000003; +CHECKREG r1, 0x00010003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00000003; +CHECKREG r5, 0x00050003; +CHECKREG r6, 0x00060003; +CHECKREG r7, 0x00070003; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x9008f000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = SIGNBITS R5.L; +R1.L = SIGNBITS R5.L; +R2.L = SIGNBITS R5.L; +R3.L = SIGNBITS R5.L; +R4.L = SIGNBITS R5.L; +R7.L = SIGNBITS R5.L; +R6.L = SIGNBITS R5.L; +R5.L = SIGNBITS R5.L; +CHECKREG r0, 0x90010003; +CHECKREG r1, 0x00010003; +CHECKREG r2, 0x90020003; +CHECKREG r3, 0x90030003; +CHECKREG r4, 0x90040003; +CHECKREG r5, 0x90080003; +CHECKREG r6, 0x90060003; +CHECKREG r7, 0x90070003; + +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa000fc00; +imm32 r7, 0xa0070000; +R0.L = SIGNBITS R6.L; +R1.L = SIGNBITS R6.L; +R2.L = SIGNBITS R6.L; +R3.L = SIGNBITS R6.L; +R4.L = SIGNBITS R6.L; +R5.L = SIGNBITS R6.L; +R7.L = SIGNBITS R6.L; +R6.L = SIGNBITS R6.L; +CHECKREG r0, 0x90010005; +CHECKREG r1, 0xA0010005; +CHECKREG r2, 0xA0020005; +CHECKREG r3, 0xA0030005; +CHECKREG r4, 0xA0040005; +CHECKREG r5, 0xA0050005; +CHECKREG r6, 0xA0000005; +CHECKREG r7, 0xA0070005; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc007e007; +R0.L = SIGNBITS R7.L; +R1.L = SIGNBITS R7.L; +R2.L = SIGNBITS R7.L; +R3.L = SIGNBITS R7.L; +R4.L = SIGNBITS R7.L; +R5.L = SIGNBITS R7.L; +R6.L = SIGNBITS R7.L; +R7.L = SIGNBITS R7.L; +CHECKREG r0, 0xC0010002; +CHECKREG r1, 0xC0010002; +CHECKREG r2, 0xC0020002; +CHECKREG r3, 0xC0030002; +CHECKREG r4, 0xC0040002; +CHECKREG r5, 0xC0050002; +CHECKREG r6, 0xC0060002; +CHECKREG r7, 0xC0070002; + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_vmax.s b/tests/tcg/bfin/c_dsp32shift_vmax.s new file mode 100644 index 0000000000000..4f3ccd1b5b6ae --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_vmax.s @@ -0,0 +1,113 @@ +//Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp +// Spec Reference: dsp32shift vmax +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x11001001; +imm32 r1, 0x11001001; +imm32 r2, 0x12345678; +imm32 r3, 0x11001003; +imm32 r4, 0x11001004; +imm32 r5, 0x11001005; +imm32 r6, 0x11001006; +imm32 r7, 0x11001007; +A0 = R2; +R0.L = VIT_MAX( R0 ) (ASL); +R1.L = VIT_MAX( R1 ) (ASL); +R2.L = VIT_MAX( R2 ) (ASL); +R3.L = VIT_MAX( R3 ) (ASL); +R4.L = VIT_MAX( R4 ) (ASL); +R5.L = VIT_MAX( R5 ) (ASL); +R6.L = VIT_MAX( R6 ) (ASL); +R7.L = VIT_MAX( R7 ) (ASL); +CHECKREG r0, 0x11001100; +CHECKREG r1, 0x11001100; +CHECKREG r2, 0x12345678; +CHECKREG r3, 0x11001100; +CHECKREG r4, 0x11001100; +CHECKREG r5, 0x11001100; +CHECKREG r6, 0x11001100; +CHECKREG r7, 0x11001100; + +imm32 r0, 0xa1001001; +imm32 r1, 0x1b001001; +imm32 r2, 0x11c01002; +imm32 r3, 0x110d1003; +imm32 r4, 0x1100e004; +imm32 r5, 0x11001f05; +imm32 r6, 0x11001006; +imm32 r7, 0x11001001; +R1.L = VIT_MAX( R0 ) (ASL); +R2.L = VIT_MAX( R1 ) (ASL); +R3.L = VIT_MAX( R2 ) (ASL); +R4.L = VIT_MAX( R3 ) (ASL); +R5.L = VIT_MAX( R4 ) (ASL); +R6.L = VIT_MAX( R5 ) (ASL); +R7.L = VIT_MAX( R6 ) (ASL); +R0.L = VIT_MAX( R7 ) (ASL); +CHECKREG r0, 0xA1001B00; +CHECKREG r1, 0x1B001001; +CHECKREG r2, 0x11C01B00; +CHECKREG r3, 0x110D1B00; +CHECKREG r4, 0x11001B00; +CHECKREG r5, 0x11001B00; +CHECKREG r6, 0x11001B00; +CHECKREG r7, 0x11001B00; + + +imm32 r0, 0x20000000; +imm32 r1, 0x4300c001; +imm32 r2, 0x4040c002; +imm32 r3, 0x40056003; +imm32 r4, 0x4000c704; +imm32 r5, 0x4000c085; +imm32 r6, 0x4000c096; +imm32 r7, 0x4000c000; +R0.L = VIT_MAX( R0 ) (ASR); +R1.L = VIT_MAX( R1 ) (ASR); +R2.L = VIT_MAX( R2 ) (ASR); +R3.L = VIT_MAX( R3 ) (ASR); +R4.L = VIT_MAX( R4 ) (ASR); +R5.L = VIT_MAX( R5 ) (ASR); +R6.L = VIT_MAX( R6 ) (ASR); +R7.L = VIT_MAX( R7 ) (ASR); +CHECKREG r0, 0x20002000; +CHECKREG r1, 0x4300C001; +CHECKREG r2, 0x4040C002; +CHECKREG r3, 0x40056003; +CHECKREG r4, 0x40004000; +CHECKREG r5, 0x40004000; +CHECKREG r6, 0x40004000; +CHECKREG r7, 0x4000C000; + +imm32 r0, 0x10000000; +imm32 r1, 0x4200c001; +imm32 r2, 0x4030c002; +imm32 r3, 0x4004c003; +imm32 r4, 0x40005004; +imm32 r5, 0x4000c605; +imm32 r6, 0x4000c076; +imm32 r7, 0x4000c008; +R2.L = VIT_MAX( R0 ) (ASR); +R3.L = VIT_MAX( R1 ) (ASR); +R4.L = VIT_MAX( R2 ) (ASR); +R5.L = VIT_MAX( R3 ) (ASR); +R6.L = VIT_MAX( R4 ) (ASR); +R7.L = VIT_MAX( R5 ) (ASR); +R0.L = VIT_MAX( R6 ) (ASR); +R1.L = VIT_MAX( R7 ) (ASR); +CHECKREG r0, 0x10004030; +CHECKREG r1, 0x42004000; +CHECKREG r2, 0x40301000; +CHECKREG r3, 0x4004C001; +CHECKREG r4, 0x40004030; +CHECKREG r5, 0x4000C001; +CHECKREG r6, 0x40004030; +CHECKREG r7, 0x40004000; + + +pass diff --git a/tests/tcg/bfin/c_dsp32shift_vmaxvmax.s b/tests/tcg/bfin/c_dsp32shift_vmaxvmax.s new file mode 100644 index 0000000000000..48e8d4bef52e3 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shift_vmaxvmax.s @@ -0,0 +1,113 @@ +//Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp +// Spec Reference: dsp32shift vmax / vmax +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x11002001; +imm32 r1, 0x12001001; +imm32 r2, 0x11301302; +imm32 r3, 0x43001003; +imm32 r4, 0x11601604; +imm32 r5, 0x71001705; +imm32 r6, 0x81008006; +imm32 r7, 0x1900b007; +A0 = R3; +R1 = VIT_MAX( R1 , R0 ) (ASL); +R2 = VIT_MAX( R2 , R1 ) (ASL); +R3 = VIT_MAX( R3 , R2 ) (ASL); +R4 = VIT_MAX( R4 , R3 ) (ASL); +R5 = VIT_MAX( R5 , R4 ) (ASL); +R6 = VIT_MAX( R6 , R5 ) (ASL); +R7 = VIT_MAX( R7 , R6 ) (ASL); +R0 = VIT_MAX( R0 , R7 ) (ASL); +CHECKREG r0, 0x20018100; +CHECKREG r1, 0x12002001; +CHECKREG r2, 0x13022001; +CHECKREG r3, 0x43002001; +CHECKREG r4, 0x16044300; +CHECKREG r5, 0x71004300; +CHECKREG r6, 0x81007100; +CHECKREG r7, 0x19008100; + +imm32 r0, 0xa11002001; +imm32 r1, 0xd2001001; +imm32 r2, 0x14301302; +imm32 r3, 0x43001003; +imm32 r4, 0x11f01604; +imm32 r5, 0xb1001705; +imm32 r6, 0xd1008006; +imm32 r7, 0x39056707; +R1 = VIT_MAX( R1 , R3 ) (ASL); +R2 = VIT_MAX( R2 , R4 ) (ASL); +R3 = VIT_MAX( R3 , R6 ) (ASL); +R4 = VIT_MAX( R4 , R5 ) (ASL); +R5 = VIT_MAX( R5 , R7 ) (ASL); +R6 = VIT_MAX( R6 , R0 ) (ASL); +R7 = VIT_MAX( R7 , R1 ) (ASL); +R0 = VIT_MAX( R0 , R2 ) (ASL); +CHECKREG r0, 0x20011604; +CHECKREG r1, 0x10014300; +CHECKREG r2, 0x14301604; +CHECKREG r3, 0x4300D100; +CHECKREG r4, 0x16041705; +CHECKREG r5, 0x17056707; +CHECKREG r6, 0xD1002001; +CHECKREG r7, 0x67074300; + +imm32 r0, 0xa1011001; +imm32 r1, 0x1b002001; +imm32 r2, 0x81c01302; +imm32 r3, 0x910d1403; +imm32 r4, 0x2100e504; +imm32 r5, 0x31007f65; +imm32 r6, 0x41007006; +imm32 r7, 0x15001801; +R1 = VIT_MAX( R1 , R0 ) (ASR); +R2 = VIT_MAX( R2 , R1 ) (ASR); +R3 = VIT_MAX( R3 , R2 ) (ASR); +R4 = VIT_MAX( R4 , R3 ) (ASR); +R5 = VIT_MAX( R5 , R4 ) (ASR); +R6 = VIT_MAX( R6 , R5 ) (ASR); +R7 = VIT_MAX( R7 , R6 ) (ASR); +R0 = VIT_MAX( R0 , R7 ) (ASR); +CHECKREG r0, 0x1001910D; +CHECKREG r1, 0x20011001; +CHECKREG r2, 0x81C02001; +CHECKREG r3, 0x910D81C0; +CHECKREG r4, 0x2100910D; +CHECKREG r5, 0x7F65910D; +CHECKREG r6, 0x7006910D; +CHECKREG r7, 0x1801910D; + +imm32 r0, 0xe1011001; +imm32 r1, 0x4b002001; +imm32 r2, 0x8fc01302; +imm32 r3, 0x910d1403; +imm32 r4, 0xb100e504; +imm32 r5, 0x41007f65; +imm32 r6, 0xaf007006; +imm32 r7, 0x16001801; +R0 = VIT_MAX( R4 , R0 ) (ASR); +R1 = VIT_MAX( R5 , R1 ) (ASR); +R2 = VIT_MAX( R6 , R2 ) (ASR); +R3 = VIT_MAX( R7 , R3 ) (ASR); +R4 = VIT_MAX( R0 , R4 ) (ASR); +R5 = VIT_MAX( R1 , R5 ) (ASR); +R6 = VIT_MAX( R2 , R6 ) (ASR); +R7 = VIT_MAX( R3 , R7 ) (ASR); +CHECKREG r0, 0xE5041001; +CHECKREG r1, 0x7F654B00; +CHECKREG r2, 0xAF008FC0; +CHECKREG r3, 0x1801910D; +CHECKREG r4, 0x1001E504; +CHECKREG r5, 0x7F657F65; +CHECKREG r6, 0xAF00AF00; +CHECKREG r7, 0x910D1801; + + + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_a0alr.s b/tests/tcg/bfin/c_dsp32shiftim_a0alr.s new file mode 100644 index 0000000000000..13bd53293f213 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_a0alr.s @@ -0,0 +1,213 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_a0alr/c_dsp32shiftim_a0alr.dsp +// Spec Reference: dsp32shift a0 ashift, lshift, rot +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x11140000; + imm32 r1, 0x012C003E; + imm32 r2, 0x81359E24; + imm32 r3, 0x81459E24; + imm32 r4, 0xD159E268; + imm32 r5, 0x51626AF2; + imm32 r6, 0x9176AF36; + imm32 r7, 0xE18BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = A0 << 0; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x012C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = A0 << 1; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x026B3C48; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = A0 << 15; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0xCF120000; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = A0 << 31; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x00000000; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = A0 >>> 1; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x28B13579; + + R5.L = -16; + A0 = 0; + A0.L = R6.L; + A0.H = R6.H; + A0 = A0 >>> 16; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x00009176; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = A0 >>> 31; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x00000001; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + .dw 0xC683 // .dw 0xC683 // A0 = A0 >>> 32; + .dw 0x0100 + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x00000000; + + imm32 r0, 0x12340000; + imm32 r1, 0x028C003E; + imm32 r2, 0x82159E24; + imm32 r3, 0x82159E24; + imm32 r4, 0xD259E268; + imm32 r5, 0x52E26AF2; + imm32 r6, 0x9226AF36; + imm32 r7, 0xE26BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = A0 << 0; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x028C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = A0 << 3; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x10ACF120; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = A0 << 15; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0xCF120000; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = A0 << 31; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x00000000; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = A0 >> 1; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x29713579; + + R5.L = -16; + A0 = 0; + A0.L = R6.L; + A0.H = R6.H; + A0 = A0 >> 16; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x00009226; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = A0 >> 31; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x00000001; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + .dw 0xC683 + .dw 0x4100 // A0 = A0 >> 32; + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x00000000; + + imm32 r0, 0x13340000; + imm32 r1, 0x038C003E; + imm32 r2, 0x83159E24; + imm32 r3, 0x83159E24; + imm32 r4, 0xD359E268; + imm32 r5, 0x53E26AF2; + imm32 r6, 0x9326AF36; + imm32 r7, 0xE36BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = ROT A0 BY 0; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x038C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = ROT A0 BY 1; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x062B3C48; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = ROT A0 BY 15; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0xCF120060; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = ROT A0 BY 31; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x62B4D678; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = ROT A0 BY -1; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x29F13579; + + R5.L = -16; + A0.L = R6.L; + A0.H = R6.H; + A0 = ROT A0 BY -16; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x6C9A9326; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = ROT A0 BY -31; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0xAFFE1ABD; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + A0 = ROT A0 BY -32; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x6800018D; + + pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_af.s b/tests/tcg/bfin/c_dsp32shiftim_af.s new file mode 100644 index 0000000000000..1c994f4331b2b --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_af.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_dsp32shiftim_af/c_dsp32shiftim_af.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift + + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R0 = R0 << 0; +R1 = R1 << 3; +R2 = R2 << 7; +R3 = R3 << 8; +R4 = R4 << 15; +R5 = R5 << 24; +R6 = R6 << 31; +R7 = R7 << 20; +CHECKREG r0, 0xA1230001; +CHECKREG r1, 0xD9A2B3C0; +CHECKREG r2, 0xE2B3C480; +CHECKREG r3, 0xD6789A00; +CHECKREG r4, 0xC4D58000; +CHECKREG r5, 0xBC000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0xCDE00000; + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R6 = R0 >>> 1; +R7 = R1 >>> 3; +R0 = R2 >>> 7; +R1 = R3 >>> 8; +R2 = R4 >>> 15; +R3 = R5 >>> 24; +R4 = R6 >>> 31; +R5 = R7 >>> 20; +CHECKREG r0, 0x00478ACF; +CHECKREG r1, 0x0034D678; +CHECKREG r2, 0xFFFF0B4F; +CHECKREG r3, 0xFFFFFF96; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x00000036; +CHECKREG r6, 0xD0918000; +CHECKREG r7, 0x03668ACF; + + + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_af_s.s b/tests/tcg/bfin/c_dsp32shiftim_af_s.s new file mode 100644 index 0000000000000..f05bffcac80a9 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_af_s.s @@ -0,0 +1,37 @@ +//Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift saturated + +imm32 r0, 0x3a1230001; +imm32 r1, 0x1e345678; +imm32 r2, 0x23f56789; +imm32 r3, 0x34db789a; +imm32 r4, 0x85a7a9ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa78dabcd; +imm32 r7, 0xb8914cde; +R6 = R0 >>> 1; +R7 = R1 >>> 3; +R0 = R2 >>> 7; +R1 = R3 >>> 8; +R2 = R4 >>> 15; +R3 = R5 >>> 24; +R4 = R6 >>> 31; +R5 = R7 >>> 20; +CHECKREG r0, 0x0047EACF; +CHECKREG r1, 0x0034DB78; +CHECKREG r2, 0xFFFF0B4F; +CHECKREG r3, 0xFFFFFF96; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x0000003C; +CHECKREG r6, 0xD0918000; +CHECKREG r7, 0x03C68ACF; + + + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_ahalf_ln.s b/tests/tcg/bfin/c_dsp32shiftim_ahalf_ln.s new file mode 100644 index 0000000000000..e911d3a587e08 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_ahalf_ln.s @@ -0,0 +1,406 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_ln/c_dsp32shiftim_ahalf_ln.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + +// Ashift : neg data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x1000c000; +imm32 r1, 0x1000c001; +imm32 r2, 0x1000c002; +imm32 r3, 0x1000c003; +imm32 r4, 0x1000c004; +imm32 r5, 0x1000c005; +imm32 r6, 0x1000c006; +imm32 r7, 0x1000c007; +R0.L = R0.L << 1; +R1.L = R1.L << 1; +R2.L = R2.L << 1; +R3.L = R3.L << 1; +R4.L = R4.L << 1; +R5.L = R5.L << 1; +R6.L = R6.L << 1; +R7.L = R7.L << 1; +CHECKREG r0, 0x10008000; +CHECKREG r1, 0x10008002; +CHECKREG r2, 0x10008004; +CHECKREG r3, 0x10008006; +CHECKREG r4, 0x10008008; +CHECKREG r5, 0x1000800A; +CHECKREG r6, 0x1000800C; +CHECKREG r7, 0x1000800E; + +imm32 r0, 0x20008001; +imm32 r1, 0x20000001; +imm32 r2, 0x2000d002; +imm32 r3, 0x2000e003; +imm32 r4, 0x2000f004; +imm32 r5, 0x2000c005; +imm32 r6, 0x2000d006; +imm32 r7, 0x2000e007; +R7.L = R0.L << 1; +R6.L = R1.L << 1; +R5.L = R2.L << 1; +R4.L = R3.L << 1; +R3.L = R4.L << 1; +R2.L = R5.L << 1; +R1.L = R6.L << 1; +R0.L = R7.L << 1; + +imm32 r0, 0x3000c001; +imm32 r1, 0x3000d001; +imm32 r2, 0x3000000f; +imm32 r3, 0x3000e003; +imm32 r4, 0x3000f004; +imm32 r5, 0x3000f005; +imm32 r6, 0x3000f006; +imm32 r7, 0x3000f007; +R6.L = R0.L << 12; +R7.L = R1.L << 12; +R5.L = R2.L << 12; +R4.L = R3.L << 12; +R3.L = R4.L << 12; +R2.L = R5.L << 12; +R1.L = R6.L << 12; +R0.L = R7.L << 12; +CHECKREG r1, 0x30000000; +CHECKREG r0, 0x30000000; +CHECKREG r2, 0x30000000; +CHECKREG r3, 0x30000000; +CHECKREG r4, 0x30003000; +CHECKREG r5, 0x3000F000; +CHECKREG r6, 0x30001000; +CHECKREG r7, 0x30001000; + +imm32 r0, 0x40009001; +imm32 r1, 0x4000a001; +imm32 r2, 0x4000b002; +imm32 r3, 0x40000010; +imm32 r4, 0x4000c004; +imm32 r5, 0x4000d005; +imm32 r6, 0x4000e006; +imm32 r7, 0x4000f007; +R5.L = R0.L << 13; +R6.L = R1.L << 13; +R7.L = R2.L << 13; +R0.L = R3.L << 13; +R1.L = R4.L << 13; +R2.L = R5.L << 13; +R3.L = R6.L << 13; +R4.L = R7.L << 13; +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40008000; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x40000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x40002000; +CHECKREG r6, 0x40002000; +CHECKREG r7, 0x40004000; + +imm32 r0, 0x00005000; +imm32 r1, 0x00015000; +imm32 r2, 0x00025000; +imm32 r3, 0x00035000; +imm32 r4, 0x00045000; +imm32 r5, 0x00055000; +imm32 r6, 0x00065000; +imm32 r7, 0x00075500; +R0.L = R0.H << 10; +R1.L = R1.H << 10; +R2.L = R2.H << 10; +R3.L = R3.H << 10; +R4.L = R4.H << 10; +R5.L = R5.H << 10; +R6.L = R6.H << 10; +R7.L = R7.H << 10; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010400; +CHECKREG r2, 0x00020800; +CHECKREG r3, 0x00030C00; +CHECKREG r4, 0x00041000; +CHECKREG r5, 0x00051400; +CHECKREG r6, 0x00061800; +CHECKREG r7, 0x00071C00; + +imm32 r0, 0x90010000; +imm32 r1, 0x90010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R2.L = R0.H << 11; +R3.L = R1.H << 11; +R4.L = R2.H << 11; +R5.L = R3.H << 11; +R6.L = R4.H << 11; +R7.L = R5.H << 11; +R0.L = R6.H << 11; +R1.L = R7.H << 11; +CHECKREG r0, 0x90013000; +CHECKREG r1, 0x90013800; +CHECKREG r2, 0x90020800; +CHECKREG r3, 0x90030800; +CHECKREG r4, 0x90041000; +CHECKREG r5, 0x90051800; +CHECKREG r6, 0x90062000; +CHECKREG r7, 0x90072800; + + +imm32 r0, 0xa0010600; +imm32 r1, 0xa0010600; +imm32 r2, 0xa002060f; +imm32 r3, 0xa0030600; +imm32 r4, 0xa0040600; +imm32 r5, 0xa0050600; +imm32 r6, 0xa0060600; +imm32 r7, 0xa0070600; +R0.L = R0.H << 12; +R1.L = R1.H << 12; +R2.L = R2.H << 12; +R3.L = R3.H << 12; +R4.L = R4.H << 12; +R5.L = R5.H << 12; +R6.L = R6.H << 12; +R7.L = R7.H << 12; +CHECKREG r0, 0xA0011000; +CHECKREG r1, 0xA0011000; +CHECKREG r2, 0xA0022000; +CHECKREG r3, 0xA0033000; +CHECKREG r4, 0xA0044000; +CHECKREG r5, 0xA0055000; +CHECKREG r6, 0xA0066000; +CHECKREG r7, 0xA0077000; + +imm32 r0, 0xc0010701; +imm32 r1, 0xc0010701; +imm32 r2, 0xc0020702; +imm32 r3, 0xc0030710; +imm32 r4, 0xc0040704; +imm32 r5, 0xc0050705; +imm32 r6, 0xc0060706; +imm32 r7, 0xc0070707; +R0.L = R0.H << 13; +R1.L = R1.H << 13; +R2.L = R2.H << 13; +R3.L = R3.H << 13; +R4.L = R4.H << 13; +R5.L = R5.H << 13; +R6.L = R6.H << 13; +R7.L = R7.H << 13; +CHECKREG r0, 0xC0012000; +CHECKREG r1, 0xC0012000; +CHECKREG r2, 0xC0024000; +CHECKREG r3, 0xC0036000; +CHECKREG r4, 0xC0048000; +CHECKREG r5, 0xC005A000; +CHECKREG r6, 0xC006C000; +CHECKREG r7, 0xC007E000; + +imm32 r0, 0x00008000; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = R0.L << 0; +R1.H = R1.L << 1; +R2.H = R2.L << 2; +R3.H = R3.L << 3; +R4.H = R4.L << 4; +R5.H = R5.L << 5; +R6.H = R6.L << 6; +R7.H = R7.L << 7; +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x00028001; +CHECKREG r2, 0x00088002; +CHECKREG r3, 0x00188003; +CHECKREG r4, 0x00408004; +CHECKREG r5, 0x00A08005; +CHECKREG r6, 0x01808006; +CHECKREG r7, 0x03808007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R2.H = R0.L << 8; +R3.H = R1.L << 9; +R4.H = R2.L << 10; +R5.H = R3.L << 11; +R6.H = R4.L << 12; +R7.H = R5.L << 13; +R0.H = R6.L << 14; +R1.H = R7.L << 15; +CHECKREG r0, 0x8000D001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x0100D002; +CHECKREG r3, 0x0200D003; +CHECKREG r4, 0x0800D004; +CHECKREG r5, 0x1800D005; +CHECKREG r6, 0x4000D006; +CHECKREG r7, 0xA000D007; + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = R0.L << 12; +R1.H = R1.L << 12; +R2.H = R2.L << 12; +R3.H = R3.L << 12; +R4.H = R4.L << 12; +R5.H = R5.L << 12; +R6.H = R6.L << 12; +R7.H = R7.L << 12; +CHECKREG r0, 0x1000E001; +CHECKREG r1, 0x1000E001; +CHECKREG r2, 0xF000000F; +CHECKREG r3, 0x3000E003; +CHECKREG r4, 0x4000E004; +CHECKREG r5, 0x5000E005; +CHECKREG r6, 0x6000E006; +CHECKREG r7, 0x7000E007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R5.H = R0.L << 13; +R6.H = R1.L << 13; +R7.H = R2.L << 13; +R0.H = R3.L << 13; +R1.H = R4.L << 13; +R2.H = R5.L << 13; +R3.H = R6.L << 13; +R4.H = R7.L << 13; +CHECKREG r0, 0x0000F001; +CHECKREG r1, 0x8000F001; +CHECKREG r2, 0xA000F002; +CHECKREG r3, 0xC0000010; +CHECKREG r4, 0xE000F004; +CHECKREG r5, 0x2000F005; +CHECKREG r6, 0x2000F006; +CHECKREG r7, 0x4000F007; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x90000000; +imm32 r1, 0x90010000; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R4.H = R0.H << 10; +R5.H = R1.H << 10; +R6.H = R2.H << 10; +R7.H = R3.H << 10; +R0.H = R4.H << 10; +R1.H = R5.H << 10; +R2.H = R6.H << 10; +R3.H = R7.H << 10; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x04000000; +CHECKREG r6, 0x08000000; +CHECKREG r7, 0x0C000000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R7.H = R0.H << 11; +R0.H = R1.H << 11; +R1.H = R2.H << 11; +R2.H = R3.H << 11; +R3.H = R4.H << 11; +R4.H = R5.H << 11; +R5.H = R6.H << 11; +R6.H = R7.H << 11; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x10000001; +CHECKREG r2, 0x18000000; +CHECKREG r3, 0x20000000; +CHECKREG r4, 0x28000000; +CHECKREG r5, 0x30000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x08000000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R6.H = R0.H << 12; +R7.H = R1.H << 12; +R0.H = R2.H << 12; +R1.H = R3.H << 12; +R2.H = R4.H << 12; +R3.H = R5.H << 12; +R4.H = R6.H << 12; +R5.H = R7.H << 12; +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x30000000; +CHECKREG r2, 0x4000000F; +CHECKREG r3, 0x50000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x10000000; +CHECKREG r7, 0x10000000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R5.H = R0.H << 3; +R6.H = R1.H << 3; +R7.H = R2.H << 3; +R0.H = R3.H << 3; +R1.H = R4.H << 3; +R2.H = R5.H << 3; +R3.H = R6.H << 3; +R4.H = R7.H << 3; +CHECKREG r0, 0x80180000; +CHECKREG r1, 0x80200000; +CHECKREG r2, 0x00400000; +CHECKREG r3, 0x00400010; +CHECKREG r4, 0x00800000; +CHECKREG r5, 0x80080000; +CHECKREG r6, 0x80080000; +CHECKREG r7, 0x80100000; +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_ahalf_lp.s b/tests/tcg/bfin/c_dsp32shiftim_ahalf_lp.s new file mode 100644 index 0000000000000..44e8882a31ce1 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_ahalf_lp.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_lp/c_dsp32shiftim_ahalf_lp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x01010100; +imm32 r1, 0x01020101; +imm32 r2, 0x01030102; +imm32 r3, 0x01040103; +imm32 r4, 0x01050104; +imm32 r5, 0x01060105; +imm32 r6, 0x01070106; +imm32 r7, 0x01080107; +R0.L = R0.L << 0; +R1.L = R1.L << 1; +R2.L = R2.L << 2; +R3.L = R3.L << 3; +R4.L = R4.L << 4; +R5.L = R5.L << 5; +R6.L = R6.L << 6; +R7.L = R7.L << 7; +CHECKREG r0, 0x01010100; +CHECKREG r1, 0x01020202; +CHECKREG r2, 0x01030408; +CHECKREG r3, 0x01040818; +CHECKREG r4, 0x01051040; +CHECKREG r5, 0x010620A0; +CHECKREG r6, 0x01074180; +CHECKREG r7, 0x01088380; + +imm32 r0, 0x00090201; +imm32 r1, 0x00100201; +imm32 r2, 0x00110202; +imm32 r3, 0x00120203; +imm32 r4, 0x00130204; +imm32 r5, 0x00140205; +imm32 r6, 0x00150206; +imm32 r7, 0x00160207; +R7.L = R0.L << 8; +R6.L = R1.L << 9; +R5.L = R2.L << 10; +R4.L = R3.L << 11; +R3.L = R4.L << 12; +R2.L = R5.L << 13; +R1.L = R6.L << 14; +R0.L = R7.L << 15; +CHECKREG r1, 0x00100000; +CHECKREG r0, 0x00090000; +CHECKREG r2, 0x00110000; +CHECKREG r3, 0x00120000; +CHECKREG r4, 0x00131800; +CHECKREG r5, 0x00140800; +CHECKREG r6, 0x00150200; +CHECKREG r7, 0x00160100; + + +imm32 r0, 0x00170401; +imm32 r1, 0x00180401; +imm32 r2, 0x0019040f; +imm32 r3, 0x00200403; +imm32 r4, 0x00210404; +imm32 r5, 0x00220405; +imm32 r6, 0x00230406; +imm32 r7, 0x00244407; +R6.L = R0.L << 15; +R5.L = R1.L << 15; +R4.L = R2.L << 15; +R3.L = R3.L << 15; +R2.L = R4.L << 15; +R1.L = R5.L << 15; +R0.L = R6.L << 15; +R7.L = R7.L << 15; +CHECKREG r0, 0x00170000; +CHECKREG r1, 0x00180000; +CHECKREG r2, 0x00190000; +CHECKREG r3, 0x00208000; +CHECKREG r4, 0x00218000; +CHECKREG r5, 0x00228000; +CHECKREG r6, 0x00238000; +CHECKREG r7, 0x00248000; + +imm32 r0, 0x00005001; +imm32 r1, 0x00005001; +imm32 r2, 0x00005002; +imm32 r3, 0x00005010; +imm32 r4, 0x00005004; +imm32 r5, 0x00005005; +imm32 r6, 0x00000506; +imm32 r7, 0x00000507; +R5.L = R0.L << 13; +R6.L = R1.L << 13; +R7.L = R2.L << 13; +R0.L = R3.L << 13; +R1.L = R4.L << 13; +R2.L = R5.L << 13; +R3.L = R6.L << 13; +R4.L = R7.L << 13; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00002000; +CHECKREG r6, 0x00002000; +CHECKREG r7, 0x00004000; + +// RHx by RLx +imm32 r0, 0x00006010; +imm32 r1, 0x00016020; +imm32 r2, 0x00026030; +imm32 r3, 0x00036040; +imm32 r4, 0x00046050; +imm32 r5, 0x00056060; +imm32 r6, 0x00066070; +imm32 r7, 0x00076080; +R0.L = R0.H << 10; +R1.L = R1.H << 10; +R2.L = R2.H << 10; +R3.L = R3.H << 10; +R4.L = R4.H << 10; +R5.L = R5.H << 10; +R6.L = R6.H << 10; +R7.L = R7.H << 10; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010400; +CHECKREG r2, 0x00020800; +CHECKREG r3, 0x00030C00; +CHECKREG r4, 0x00041000; +CHECKREG r5, 0x00051400; +CHECKREG r6, 0x00061800; +CHECKREG r7, 0x00071C00; + +imm32 r0, 0x00010090; +imm32 r1, 0x00010111; +imm32 r2, 0x00020120; +imm32 r3, 0x00030130; +imm32 r4, 0x00040140; +imm32 r5, 0x00050150; +imm32 r6, 0x00060160; +imm32 r7, 0x00070170; +R1.L = R0.H << 1; +R2.L = R1.H << 1; +R3.L = R2.H << 1; +R4.L = R3.H << 1; +R5.L = R4.H << 1; +R6.L = R5.H << 1; +R7.L = R6.H << 1; +R0.L = R7.H << 1; +CHECKREG r1, 0x00010002; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030004; +CHECKREG r4, 0x00040006; +CHECKREG r5, 0x00050008; +CHECKREG r6, 0x0006000A; +CHECKREG r7, 0x0007000C; +CHECKREG r0, 0x0001000E; + + +imm32 r0, 0x0a010000; +imm32 r1, 0x0b010000; +imm32 r2, 0x0c02000f; +imm32 r3, 0x0d030000; +imm32 r4, 0x0e040000; +imm32 r5, 0x0f050000; +imm32 r6, 0x01060000; +imm32 r7, 0x02070000; +R2.L = R0.H << 12; +R3.L = R1.H << 12; +R4.L = R2.H << 12; +R5.L = R3.H << 12; +R6.L = R4.H << 12; +R7.L = R5.H << 12; +R0.L = R6.H << 12; +R1.L = R7.H << 12; +CHECKREG r0, 0x0A016000; +CHECKREG r1, 0x0B017000; +CHECKREG r2, 0x0C021000; +CHECKREG r3, 0x0D031000; +CHECKREG r4, 0x0E042000; +CHECKREG r5, 0x0F053000; +CHECKREG r6, 0x01064000; +CHECKREG r7, 0x02075000; + +imm32 r0, 0x01010001; +imm32 r1, 0x02010001; +imm32 r2, 0x03020002; +imm32 r3, 0x04030010; +imm32 r4, 0x05040004; +imm32 r5, 0x06050005; +imm32 r6, 0x07060006; +imm32 r7, 0x08070007; +R3.L = R0.H << 13; +R4.L = R1.H << 13; +R5.L = R2.H << 13; +R6.L = R3.H << 13; +R7.L = R4.H << 13; +R0.L = R5.H << 13; +R1.L = R6.H << 13; +R2.L = R7.H << 13; +CHECKREG r0, 0x0101A000; +CHECKREG r1, 0x0201C000; +CHECKREG r2, 0x0302E000; +CHECKREG r3, 0x04032000; +CHECKREG r4, 0x05042000; +CHECKREG r5, 0x06054000; +CHECKREG r6, 0x07066000; +CHECKREG r7, 0x08078000; + +// RLx by RLx +imm32 r0, 0xa0000400; +imm32 r1, 0xbb000401; +imm32 r2, 0xc0000402; +imm32 r3, 0xd0000403; +imm32 r4, 0xe0000404; +imm32 r5, 0xf0000405; +imm32 r6, 0x10000406; +imm32 r7, 0x20000407; +R0.H = R0.L << 14; +R1.H = R1.L << 14; +R2.H = R2.L << 14; +R3.H = R3.L << 14; +R4.H = R4.L << 14; +R5.H = R5.L << 14; +R6.H = R6.L << 14; +R7.H = R7.L << 14; +CHECKREG r0, 0x00000400; +CHECKREG r1, 0x40000401; +CHECKREG r2, 0x80000402; +CHECKREG r3, 0xC0000403; +CHECKREG r4, 0x00000404; +CHECKREG r5, 0x40000405; +CHECKREG r6, 0x80000406; +CHECKREG r7, 0xC0000407; + +imm32 r0, 0x0a000001; +imm32 r1, 0x0b000001; +imm32 r2, 0x0cd00002; +imm32 r3, 0x0d000003; +imm32 r4, 0x0e000004; +imm32 r5, 0x0f000005; +imm32 r6, 0x03000006; +imm32 r7, 0x04000007; +R1.H = R0.L << 15; +R2.H = R1.L << 15; +R3.H = R2.L << 15; +R4.H = R3.L << 15; +R5.H = R4.L << 15; +R6.H = R5.L << 15; +R7.H = R6.L << 15; +R0.H = R7.L << 15; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x80000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x80000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x80000006; +CHECKREG r7, 0x00000007; +CHECKREG r0, 0x80000001; + + +imm32 r0, 0x10000001; +imm32 r1, 0x02000001; +imm32 r2, 0x0300000f; +imm32 r3, 0x04000003; +imm32 r4, 0x05000004; +imm32 r5, 0x06000005; +imm32 r6, 0x07000006; +imm32 r7, 0x00800007; +R2.H = R0.L << 2; +R3.H = R1.L << 2; +R4.H = R2.L << 2; +R5.H = R3.L << 2; +R6.H = R4.L << 2; +R7.H = R5.L << 2; +R0.H = R6.L << 2; +R1.H = R7.L << 2; +CHECKREG r0, 0x00180001; +CHECKREG r1, 0x001C0001; +CHECKREG r2, 0x0004000F; +CHECKREG r3, 0x00040003; +CHECKREG r4, 0x003C0004; +CHECKREG r5, 0x000C0005; +CHECKREG r6, 0x00100006; +CHECKREG r7, 0x00140007; + +imm32 r0, 0x00000801; +imm32 r1, 0x00000801; +imm32 r2, 0x00000802; +imm32 r3, 0x00000810; +imm32 r4, 0x00000804; +imm32 r5, 0x00000805; +imm32 r6, 0x00000806; +imm32 r7, 0x00000807; +R3.H = R0.L << 3; +R4.H = R1.L << 3; +R5.H = R2.L << 3; +R6.H = R3.L << 3; +R7.H = R4.L << 3; +R0.H = R5.L << 3; +R1.H = R6.L << 3; +R2.H = R7.L << 3; +CHECKREG r0, 0x40280801; +CHECKREG r1, 0x40300801; +CHECKREG r2, 0x40380802; +CHECKREG r3, 0x40080810; +CHECKREG r4, 0x40080804; +CHECKREG r5, 0x40100805; +CHECKREG r6, 0x40800806; +CHECKREG r7, 0x40200807; + +// RHx by RLx +imm32 r0, 0x00000400; +imm32 r1, 0x00010500; +imm32 r2, 0x00020060; +imm32 r3, 0x00030070; +imm32 r4, 0x00040800; +imm32 r5, 0x00050090; +imm32 r6, 0x00060d00; +imm32 r7, 0x00070a00; +R7.H = R0.H << 10; +R6.H = R1.H << 10; +R5.H = R2.H << 10; +R4.H = R3.H << 10; +R3.H = R4.H << 10; +R2.H = R5.H << 10; +R1.H = R6.H << 10; +R0.H = R7.H << 10; +CHECKREG r1, 0x00000500; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000070; +CHECKREG r4, 0x0C000800; +CHECKREG r5, 0x08000090; +CHECKREG r6, 0x04000D00; +CHECKREG r7, 0x00000A00; +CHECKREG r0, 0x00000400; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020001; +imm32 r3, 0x00030002; +imm32 r4, 0x00040003; +imm32 r5, 0x00050004; +imm32 r6, 0x00060005; +imm32 r7, 0x00070006; +R6.H = R0.H << 11; +R5.H = R1.H << 11; +R4.H = R2.H << 11; +R3.H = R3.H << 11; +R2.H = R4.H << 11; +R1.H = R5.H << 11; +R7.H = R6.H << 11; +R0.H = R7.H << 11; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x18000002; +CHECKREG r4, 0x10000003; +CHECKREG r5, 0x08000004; +CHECKREG r6, 0x08000005; +CHECKREG r7, 0x00000006; +CHECKREG r0, 0x00000000; + + +imm32 r0, 0x00010060; +imm32 r1, 0x00010060; +imm32 r2, 0x0002006f; +imm32 r3, 0x00030060; +imm32 r4, 0x00040060; +imm32 r5, 0x00050060; +imm32 r6, 0x00060060; +imm32 r7, 0x00070060; +R4.H = R0.H << 12; +R5.H = R1.H << 12; +R6.H = R2.H << 12; +R7.H = R3.H << 12; +R0.H = R4.H << 12; +R1.H = R5.H << 12; +R2.H = R6.H << 12; +R3.H = R7.H << 12; +CHECKREG r0, 0x00000060; +CHECKREG r1, 0x00000060; +CHECKREG r2, 0x0000006F; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x10000060; +CHECKREG r5, 0x10000060; +CHECKREG r6, 0x20000060; +CHECKREG r7, 0x30000060; + +imm32 r0, 0x12010070; +imm32 r1, 0x23010070; +imm32 r2, 0x34020070; +imm32 r3, 0x45030070; +imm32 r4, 0x56040070; +imm32 r5, 0x67050070; +imm32 r6, 0x78060070; +imm32 r7, 0x09070070; +R4.H = R0.H << 3; +R5.H = R1.H << 3; +R6.H = R2.H << 3; +R7.H = R3.H << 3; +R0.H = R4.H << 3; +R1.H = R5.H << 3; +R2.H = R6.H << 3; +R3.H = R7.H << 3; +CHECKREG r0, 0x80400070; +CHECKREG r1, 0xC0400070; +CHECKREG r2, 0x00800070; +CHECKREG r3, 0x40C00070; +CHECKREG r4, 0x90080070; +CHECKREG r5, 0x18080070; +CHECKREG r6, 0xA0100070; +CHECKREG r7, 0x28180070; + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_ahalf_rn.s b/tests/tcg/bfin/c_dsp32shiftim_ahalf_rn.s new file mode 100644 index 0000000000000..30d84f2642958 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_ahalf_rn.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rn/c_dsp32shiftim_ahalf_rn.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >>> 10; +R1.L = R1.L >>> 10; +R2.L = R2.L >>> 10; +R3.L = R3.L >>> 10; +R4.L = R4.L >>> 10; +R5.L = R5.L >>> 10; +R6.L = R6.L >>> 10; +R7.L = R7.L >>> 10; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x0000FFE0; +CHECKREG r2, 0x0000FFE0; +CHECKREG r3, 0x0000FFE0; +CHECKREG r4, 0x0000FFE0; +CHECKREG r5, 0x0000FFE0; +CHECKREG r6, 0x0000FFE0; +CHECKREG r7, 0x0000FFE0; + +imm32 r0, 0x02008020; +imm32 r0, 0x02008021; +imm32 r2, 0x02008022; +imm32 r3, 0x02008023; +imm32 r4, 0x02008024; +imm32 r5, 0x02008025; +imm32 r6, 0x02008026; +imm32 r7, 0x02008027; +R0.L = R0.L >>> 11; +R1.L = R1.L >>> 11; +R2.L = R2.L >>> 11; +R3.L = R3.L >>> 11; +R4.L = R4.L >>> 11; +R5.L = R5.L >>> 11; +R6.L = R6.L >>> 11; +R7.L = R7.L >>> 11; +CHECKREG r0, 0x0200FFF0; +CHECKREG r1, 0x0000FFFF; +CHECKREG r2, 0x0200FFF0; +CHECKREG r3, 0x0200FFF0; +CHECKREG r4, 0x0200FFF0; +CHECKREG r5, 0x0200FFF0; +CHECKREG r6, 0x0200FFF0; +CHECKREG r7, 0x0200FFF0; + + +imm32 r0, 0x00308001; +imm32 r1, 0x00308001; +R2.L = -15; +imm32 r3, 0x00308003; +imm32 r4, 0x00308004; +imm32 r5, 0x00308005; +imm32 r6, 0x00308006; +imm32 r7, 0x00308007; +R0.L = R0.L >>> 12; +R1.L = R1.L >>> 12; +R2.L = R2.L >>> 12; +R3.L = R3.L >>> 12; +R4.L = R4.L >>> 12; +R5.L = R5.L >>> 12; +R6.L = R6.L >>> 12; +R7.L = R7.L >>> 12; +CHECKREG r0, 0x0030FFF8; +CHECKREG r1, 0x0030FFF8; +CHECKREG r2, 0x0200FFFF; +CHECKREG r3, 0x0030FFF8; +CHECKREG r4, 0x0030FFF8; +CHECKREG r5, 0x0030FFF8; +CHECKREG r6, 0x0030FFF8; +CHECKREG r7, 0x0030FFF8; + +imm32 r0, 0x00008401; +imm32 r1, 0x00008401; +imm32 r2, 0x00008402; +R3.L = -16; +imm32 r4, 0x00008404; +imm32 r5, 0x00008405; +imm32 r6, 0x00008406; +imm32 r7, 0x00008407; +R0.L = R0.L >>> 3; +R1.L = R1.L >>> 3; +R2.L = R2.L >>> 3; +R3.L = R3.L >>> 3; +R4.L = R4.L >>> 3; +R5.L = R5.L >>> 3; +R6.L = R6.L >>> 3; +R7.L = R7.L >>> 3; +CHECKREG r0, 0x0000F080; +CHECKREG r1, 0x0000F080; +CHECKREG r2, 0x0000F080; +CHECKREG r3, 0x0030FFFE; +CHECKREG r4, 0x0000F080; +CHECKREG r5, 0x0000F080; +CHECKREG r6, 0x0000F080; +CHECKREG r7, 0x0000F080; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x05000500; +imm32 r1, 0x85010500; +imm32 r2, 0x85020500; +imm32 r3, 0x85030500; +imm32 r4, 0x85040500; +imm32 r5, 0x85050500; +imm32 r6, 0x85060500; +imm32 r7, 0x85070500; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0x05000001; +CHECKREG r1, 0x8501FFE1; +CHECKREG r2, 0x8502FFE1; +CHECKREG r3, 0x8503FFE1; +CHECKREG r4, 0x8504FFE1; +CHECKREG r5, 0x8505FFE1; +CHECKREG r6, 0x8506FFE1; +CHECKREG r7, 0x8507FFE1; + +imm32 r0, 0x80610000; +R1.L = -1; +imm32 r2, 0x80620000; +imm32 r3, 0x80630000; +imm32 r4, 0x80640000; +imm32 r5, 0x80650000; +imm32 r6, 0x80660000; +imm32 r7, 0x80670000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x8061FFF0; +CHECKREG r1, 0x8501FFF0; +CHECKREG r2, 0x8062FFF0; +CHECKREG r3, 0x8063FFF0; +CHECKREG r4, 0x8064FFF0; +CHECKREG r5, 0x8065FFF0; +CHECKREG r6, 0x8066FFF0; +CHECKREG r7, 0x8067FFF0; + + +imm32 r0, 0xa0010070; +imm32 r1, 0xa0010070; +R2.L = -15; +imm32 r3, 0xa0030070; +imm32 r4, 0xa0040070; +imm32 r5, 0xa0050070; +imm32 r6, 0xa0060070; +imm32 r7, 0xa0070070; +R0.L = R0.H >>> 12; +R1.L = R1.H >>> 12; +R2.L = R2.H >>> 12; +R3.L = R3.H >>> 12; +R4.L = R4.H >>> 12; +R5.L = R5.H >>> 12; +R6.L = R6.H >>> 12; +R7.L = R7.H >>> 12; +CHECKREG r0, 0xA001FFFA; +CHECKREG r1, 0xA001FFFA; +CHECKREG r2, 0x8062FFF8; +CHECKREG r3, 0xA003FFFA; +CHECKREG r4, 0xA004FFFA; +CHECKREG r5, 0xA005FFFA; +CHECKREG r6, 0xA006FFFA; +CHECKREG r7, 0xA007FFFA; + +imm32 r0, 0xb8010001; +imm32 r1, 0xb8010001; +imm32 r2, 0xb8020002; +R3.L = -16; +imm32 r4, 0xb8040004; +imm32 r5, 0xb8050005; +imm32 r6, 0xb8060006; +imm32 r7, 0xb8070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0xB801FFFD; +CHECKREG r1, 0xB801FFFD; +CHECKREG r2, 0xB802FFFD; +CHECKREG r3, 0xA003FFFD; +CHECKREG r4, 0xB804FFFD; +CHECKREG r5, 0xB805FFFD; +CHECKREG r6, 0xB806FFFD; +CHECKREG r7, 0xB807FFFD; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009000; +imm32 r5, 0x00009005; +imm32 r6, 0x00009006; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0xFFFE9001; +CHECKREG r1, 0xFFFE9001; +CHECKREG r2, 0xFFFE9002; +CHECKREG r3, 0xFFFE9003; +CHECKREG r4, 0xFFFE9000; +CHECKREG r5, 0xFFFE9005; +CHECKREG r6, 0xFFFE9006; +CHECKREG r7, 0xFFFE9007; + +imm32 r0, 0xa0008001; +imm32 r1, 0xa0008001; +imm32 r2, 0xa0008002; +imm32 r3, 0xa0008003; +imm32 r4, 0xa0008004; +R5.L = -1; +imm32 r6, 0xa0008006; +imm32 r7, 0xa0008007; +R0.H = R0.L >>> 5; +R1.H = R1.L >>> 5; +R2.H = R2.L >>> 5; +R3.H = R3.L >>> 5; +R4.H = R4.L >>> 5; +R5.H = R5.L >>> 5; +R6.H = R6.L >>> 5; +R7.H = R7.L >>> 5; +CHECKREG r0, 0xFC008001; +CHECKREG r1, 0xFC008001; +CHECKREG r2, 0xFC008002; +CHECKREG r3, 0xFC008003; +CHECKREG r4, 0xFC008004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFC008006; +CHECKREG r7, 0xFC008007; + + +imm32 r0, 0x00009b01; +imm32 r1, 0x00009b01; +imm32 r2, 0x00009b02; +imm32 r3, 0x00009b03; +imm32 r4, 0x00009b04; +imm32 r5, 0x00009b05; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0xFE6C9B01; +CHECKREG r1, 0xFE6C9B01; +CHECKREG r2, 0xFE6C9B02; +CHECKREG r3, 0xFE6C9B03; +CHECKREG r4, 0xFE6C9B04; +CHECKREG r5, 0xFE6C9B05; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0xFE409007; + +imm32 r0, 0x0000a0c1; +imm32 r1, 0x0000a0c1; +imm32 r2, 0x0000a0c2; +imm32 r3, 0x0000a0c3; +imm32 r4, 0x0000a0c4; +imm32 r5, 0x0000a0c5; +imm32 r6, 0x0000a0c6; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0xFF41A0C1; +CHECKREG r1, 0xFF41A0C1; +CHECKREG r2, 0xFF41A0C2; +CHECKREG r3, 0xFF41A0C3; +CHECKREG r4, 0xFF41A0C4; +CHECKREG r5, 0xFF41A0C5; +CHECKREG r6, 0xFF41A0C6; +CHECKREG r7, 0xFFFFFFF0; + +imm32 r0, 0x80010d00; +imm32 r1, 0x80010d00; +imm32 r2, 0x80020d00; +imm32 r3, 0x80030d00; +R4.L = -1; +imm32 r5, 0x80050d00; +imm32 r6, 0x80060d00; +imm32 r7, 0x80070d00; +R0.H = R0.H >>> 14; +R1.H = R1.H >>> 14; +R2.H = R2.H >>> 14; +R3.H = R3.H >>> 14; +R4.H = R4.H >>> 14; +R5.H = R5.H >>> 14; +R6.H = R6.H >>> 14; +R7.H = R7.H >>> 14; +CHECKREG r0, 0xFFFE0D00; +CHECKREG r1, 0xFFFE0D00; +CHECKREG r2, 0xFFFE0D00; +CHECKREG r3, 0xFFFE0D00; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFE0D00; +CHECKREG r6, 0xFFFE0D00; +CHECKREG r7, 0xFFFE0D00; + +imm32 r0, 0x8d010000; +imm32 r1, 0x8d010000; +imm32 r2, 0x8d020000; +imm32 r3, 0x8d030000; +imm32 r4, 0x8d040000; +R5.L = -1; +imm32 r6, 0x8d060000; +imm32 r7, 0x8d070000; +R0.H = R0.H >>> 15; +R1.H = R1.H >>> 15; +R2.H = R2.H >>> 15; +R3.H = R3.H >>> 15; +R4.H = R4.H >>> 15; +R5.H = R5.H >>> 15; +R6.H = R6.H >>> 15; +R7.H = R7.H >>> 15; +CHECKREG r0, 0xFFFF0000; +CHECKREG r1, 0xFFFF0000; +CHECKREG r2, 0xFFFF0000; +CHECKREG r3, 0xFFFF0000; +CHECKREG r4, 0xFFFF0000; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFF0000; +CHECKREG r7, 0xFFFF0000; + + +imm32 r0, 0xde010000; +imm32 r1, 0xde010000; +imm32 r2, 0xde020000; +imm32 r3, 0xde030000; +imm32 r4, 0xde040000; +imm32 r5, 0xde050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0xDE01FFF7; +CHECKREG r1, 0xDE01FFF7; +CHECKREG r2, 0xDE02FFF7; +CHECKREG r3, 0xDE03FFF7; +CHECKREG r4, 0xDE04FFF7; +CHECKREG r5, 0xDE05FFF7; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xD007FFF4; + +imm32 r0, 0x9f010c00; +imm32 r1, 0xaf010c00; +imm32 r2, 0xbf020c00; +imm32 r3, 0xcf030c00; +imm32 r4, 0xdf040c00; +imm32 r5, 0xef050c00; +imm32 r6, 0xff060c00; +R7.L = -16; +R0.H = R0.H >>> 5; +R1.H = R1.H >>> 5; +R2.H = R2.H >>> 5; +R3.H = R3.H >>> 5; +R4.H = R4.H >>> 5; +R5.H = R5.H >>> 5; +R6.H = R6.H >>> 5; +R7.H = R7.H >>> 5; +CHECKREG r0, 0xFCF80C00; +CHECKREG r1, 0xFD780C00; +CHECKREG r2, 0xFDF80C00; +CHECKREG r3, 0xFE780C00; +CHECKREG r4, 0xFEF80C00; +CHECKREG r5, 0xFF780C00; +CHECKREG r6, 0xFFF80C00; +CHECKREG r7, 0xFE80FFF0; +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_ahalf_rn_s.s b/tests/tcg/bfin/c_dsp32shiftim_ahalf_rn_s.s new file mode 100644 index 0000000000000..20770d579e57c --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_ahalf_rn_s.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rn_s/c_dsp32shiftim_ahalf_rn_s.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >>> 10; +R1.L = R1.L >>> 10; +R2.L = R2.L >>> 10; +R3.L = R3.L >>> 10; +R4.L = R4.L >>> 10; +R5.L = R5.L >>> 10; +R6.L = R6.L >>> 10; +R7.L = R7.L >>> 10; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x0000FFE0; +CHECKREG r2, 0x0000FFE0; +CHECKREG r3, 0x0000FFE0; +CHECKREG r4, 0x0000FFE0; +CHECKREG r5, 0x0000FFE0; +CHECKREG r6, 0x0000FFE0; +CHECKREG r7, 0x0000FFE0; + +imm32 r0, 0x02008020; +imm32 r0, 0x02008021; +imm32 r2, 0x02008022; +imm32 r3, 0x02008023; +imm32 r4, 0x02008024; +imm32 r5, 0x02008025; +imm32 r6, 0x02008026; +imm32 r7, 0x02008027; +R0.L = R0.L >>> 11; +R1.L = R1.L >>> 11; +R2.L = R2.L >>> 11; +R3.L = R3.L >>> 11; +R4.L = R4.L >>> 11; +R5.L = R5.L >>> 11; +R6.L = R6.L >>> 11; +R7.L = R7.L >>> 11; +CHECKREG r0, 0x0200FFF0; +CHECKREG r1, 0x0000FFFF; +CHECKREG r2, 0x0200FFF0; +CHECKREG r3, 0x0200FFF0; +CHECKREG r4, 0x0200FFF0; +CHECKREG r5, 0x0200FFF0; +CHECKREG r6, 0x0200FFF0; +CHECKREG r7, 0x0200FFF0; + + +imm32 r0, 0x00308001; +imm32 r1, 0x00308001; +R2.L = -15; +imm32 r3, 0x00308003; +imm32 r4, 0x00308004; +imm32 r5, 0x00308005; +imm32 r6, 0x00308006; +imm32 r7, 0x00308007; +R0.L = R0.L >>> 12; +R1.L = R1.L >>> 12; +R2.L = R2.L >>> 12; +R3.L = R3.L >>> 12; +R4.L = R4.L >>> 12; +R5.L = R5.L >>> 12; +R6.L = R6.L >>> 12; +R7.L = R7.L >>> 12; +CHECKREG r0, 0x0030FFF8; +CHECKREG r1, 0x0030FFF8; +CHECKREG r2, 0x0200FFFF; +CHECKREG r3, 0x0030FFF8; +CHECKREG r4, 0x0030FFF8; +CHECKREG r5, 0x0030FFF8; +CHECKREG r6, 0x0030FFF8; +CHECKREG r7, 0x0030FFF8; + +imm32 r0, 0x00008401; +imm32 r1, 0x00008401; +imm32 r2, 0x00008402; +R3.L = -16; +imm32 r4, 0x00008404; +imm32 r5, 0x00008405; +imm32 r6, 0x00008406; +imm32 r7, 0x00008407; +R0.L = R0.L >>> 3; +R1.L = R1.L >>> 3; +R2.L = R2.L >>> 3; +R3.L = R3.L >>> 3; +R4.L = R4.L >>> 3; +R5.L = R5.L >>> 3; +R6.L = R6.L >>> 3; +R7.L = R7.L >>> 3; +CHECKREG r0, 0x0000F080; +CHECKREG r1, 0x0000F080; +CHECKREG r2, 0x0000F080; +CHECKREG r3, 0x0030FFFE; +CHECKREG r4, 0x0000F080; +CHECKREG r5, 0x0000F080; +CHECKREG r6, 0x0000F080; +CHECKREG r7, 0x0000F080; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x05000500; +imm32 r1, 0x85010500; +imm32 r2, 0x85020500; +imm32 r3, 0x85030500; +imm32 r4, 0x85040500; +imm32 r5, 0x85050500; +imm32 r6, 0x85060500; +imm32 r7, 0x85070500; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0x05000001; +CHECKREG r1, 0x8501FFE1; +CHECKREG r2, 0x8502FFE1; +CHECKREG r3, 0x8503FFE1; +CHECKREG r4, 0x8504FFE1; +CHECKREG r5, 0x8505FFE1; +CHECKREG r6, 0x8506FFE1; +CHECKREG r7, 0x8507FFE1; + +imm32 r0, 0x80610000; +R1.L = -1; +imm32 r2, 0x80620000; +imm32 r3, 0x80630000; +imm32 r4, 0x80640000; +imm32 r5, 0x80650000; +imm32 r6, 0x80660000; +imm32 r7, 0x80670000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x8061FFF0; +CHECKREG r1, 0x8501FFF0; +CHECKREG r2, 0x8062FFF0; +CHECKREG r3, 0x8063FFF0; +CHECKREG r4, 0x8064FFF0; +CHECKREG r5, 0x8065FFF0; +CHECKREG r6, 0x8066FFF0; +CHECKREG r7, 0x8067FFF0; + + +imm32 r0, 0xa0010070; +imm32 r1, 0xa0010070; +R2.L = -15; +imm32 r3, 0xa0030070; +imm32 r4, 0xa0040070; +imm32 r5, 0xa0050070; +imm32 r6, 0xa0060070; +imm32 r7, 0xa0070070; +R0.L = R0.H >>> 12; +R1.L = R1.H >>> 12; +R2.L = R2.H >>> 12; +R3.L = R3.H >>> 12; +R4.L = R4.H >>> 12; +R5.L = R5.H >>> 12; +R6.L = R6.H >>> 12; +R7.L = R7.H >>> 12; +CHECKREG r0, 0xA001FFFA; +CHECKREG r1, 0xA001FFFA; +CHECKREG r2, 0x8062FFF8; +CHECKREG r3, 0xA003FFFA; +CHECKREG r4, 0xA004FFFA; +CHECKREG r5, 0xA005FFFA; +CHECKREG r6, 0xA006FFFA; +CHECKREG r7, 0xA007FFFA; + +imm32 r0, 0xb8010001; +imm32 r1, 0xb8010001; +imm32 r2, 0xb8020002; +R3.L = -16; +imm32 r4, 0xb8040004; +imm32 r5, 0xb8050005; +imm32 r6, 0xb8060006; +imm32 r7, 0xb8070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0xB801FFFD; +CHECKREG r1, 0xB801FFFD; +CHECKREG r2, 0xB802FFFD; +CHECKREG r3, 0xA003FFFD; +CHECKREG r4, 0xB804FFFD; +CHECKREG r5, 0xB805FFFD; +CHECKREG r6, 0xB806FFFD; +CHECKREG r7, 0xB807FFFD; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009000; +imm32 r5, 0x00009005; +imm32 r6, 0x00009006; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0xFFFE9001; +CHECKREG r1, 0xFFFE9001; +CHECKREG r2, 0xFFFE9002; +CHECKREG r3, 0xFFFE9003; +CHECKREG r4, 0xFFFE9000; +CHECKREG r5, 0xFFFE9005; +CHECKREG r6, 0xFFFE9006; +CHECKREG r7, 0xFFFE9007; + +imm32 r0, 0xa0008001; +imm32 r1, 0xa0008001; +imm32 r2, 0xa0008002; +imm32 r3, 0xa0008003; +imm32 r4, 0xa0008004; +R5.L = -1; +imm32 r6, 0xa0008006; +imm32 r7, 0xa0008007; +R0.H = R0.L >>> 5; +R1.H = R1.L >>> 5; +R2.H = R2.L >>> 5; +R3.H = R3.L >>> 5; +R4.H = R4.L >>> 5; +R5.H = R5.L >>> 5; +R6.H = R6.L >>> 5; +R7.H = R7.L >>> 5; +CHECKREG r0, 0xFC008001; +CHECKREG r1, 0xFC008001; +CHECKREG r2, 0xFC008002; +CHECKREG r3, 0xFC008003; +CHECKREG r4, 0xFC008004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFC008006; +CHECKREG r7, 0xFC008007; + + +imm32 r0, 0x00009b01; +imm32 r1, 0x00009b01; +imm32 r2, 0x00009b02; +imm32 r3, 0x00009b03; +imm32 r4, 0x00009b04; +imm32 r5, 0x00009b05; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0xFE6C9B01; +CHECKREG r1, 0xFE6C9B01; +CHECKREG r2, 0xFE6C9B02; +CHECKREG r3, 0xFE6C9B03; +CHECKREG r4, 0xFE6C9B04; +CHECKREG r5, 0xFE6C9B05; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0xFE409007; + +imm32 r0, 0x0000a0c1; +imm32 r1, 0x0000a0c1; +imm32 r2, 0x0000a0c2; +imm32 r3, 0x0000a0c3; +imm32 r4, 0x0000a0c4; +imm32 r5, 0x0000a0c5; +imm32 r6, 0x0000a0c6; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0xFF41A0C1; +CHECKREG r1, 0xFF41A0C1; +CHECKREG r2, 0xFF41A0C2; +CHECKREG r3, 0xFF41A0C3; +CHECKREG r4, 0xFF41A0C4; +CHECKREG r5, 0xFF41A0C5; +CHECKREG r6, 0xFF41A0C6; +CHECKREG r7, 0xFFFFFFF0; + +imm32 r0, 0x80010d00; +imm32 r1, 0x80010d00; +imm32 r2, 0x80020d00; +imm32 r3, 0x80030d00; +R4.L = -1; +imm32 r5, 0x80050d00; +imm32 r6, 0x80060d00; +imm32 r7, 0x80070d00; +R0.H = R0.H >>> 14; +R1.H = R1.H >>> 14; +R2.H = R2.H >>> 14; +R3.H = R3.H >>> 14; +R4.H = R4.H >>> 14; +R5.H = R5.H >>> 14; +R6.H = R6.H >>> 14; +R7.H = R7.H >>> 14; +CHECKREG r0, 0xFFFE0D00; +CHECKREG r1, 0xFFFE0D00; +CHECKREG r2, 0xFFFE0D00; +CHECKREG r3, 0xFFFE0D00; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFE0D00; +CHECKREG r6, 0xFFFE0D00; +CHECKREG r7, 0xFFFE0D00; + +imm32 r0, 0x8d010000; +imm32 r1, 0x8d010000; +imm32 r2, 0x8d020000; +imm32 r3, 0x8d030000; +imm32 r4, 0x8d040000; +R5.L = -1; +imm32 r6, 0x8d060000; +imm32 r7, 0x8d070000; +R0.H = R0.H >>> 15; +R1.H = R1.H >>> 15; +R2.H = R2.H >>> 15; +R3.H = R3.H >>> 15; +R4.H = R4.H >>> 15; +R5.H = R5.H >>> 15; +R6.H = R6.H >>> 15; +R7.H = R7.H >>> 15; +CHECKREG r0, 0xFFFF0000; +CHECKREG r1, 0xFFFF0000; +CHECKREG r2, 0xFFFF0000; +CHECKREG r3, 0xFFFF0000; +CHECKREG r4, 0xFFFF0000; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFF0000; +CHECKREG r7, 0xFFFF0000; + + +imm32 r0, 0xde010000; +imm32 r1, 0xde010000; +imm32 r2, 0xde020000; +imm32 r3, 0xde030000; +imm32 r4, 0xde040000; +imm32 r5, 0xde050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0xDE01FFF7; +CHECKREG r1, 0xDE01FFF7; +CHECKREG r2, 0xDE02FFF7; +CHECKREG r3, 0xDE03FFF7; +CHECKREG r4, 0xDE04FFF7; +CHECKREG r5, 0xDE05FFF7; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xD007FFF4; + +imm32 r0, 0x9f010c00; +imm32 r1, 0xaf010c00; +imm32 r2, 0xbf020c00; +imm32 r3, 0xcf030c00; +imm32 r4, 0xdf040c00; +imm32 r5, 0xef050c00; +imm32 r6, 0xff060c00; +R7.L = -16; +R0.H = R0.H >>> 5; +R1.H = R1.H >>> 5; +R2.H = R2.H >>> 5; +R3.H = R3.H >>> 5; +R4.H = R4.H >>> 5; +R5.H = R5.H >>> 5; +R6.H = R6.H >>> 5; +R7.H = R7.H >>> 5; +CHECKREG r0, 0xFCF80C00; +CHECKREG r1, 0xFD780C00; +CHECKREG r2, 0xFDF80C00; +CHECKREG r3, 0xFE780C00; +CHECKREG r4, 0xFEF80C00; +CHECKREG r5, 0xFF780C00; +CHECKREG r6, 0xFFF80C00; +CHECKREG r7, 0xFE80FFF0; +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_ahalf_rp.s b/tests/tcg/bfin/c_dsp32shiftim_ahalf_rp.s new file mode 100644 index 0000000000000..471795eedaf82 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_ahalf_rp.s @@ -0,0 +1,420 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rp/c_dsp32shiftim_ahalf_rp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00010001; +imm32 r2, 0x00010002; +imm32 r3, 0x00010003; +imm32 r4, 0x00010004; +imm32 r5, 0x00010005; +imm32 r6, 0x00010006; +imm32 r7, 0x00010007; +R0.L = R0.L >>> 1; +R1.L = R1.L >>> 1; +R2.L = R2.L >>> 1; +R3.L = R3.L >>> 1; +R4.L = R4.L >>> 1; +R5.L = R5.L >>> 1; +R6.L = R6.L >>> 1; +R7.L = R7.L >>> 1; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00010001; +CHECKREG r3, 0x00010001; +CHECKREG r4, 0x00010002; +CHECKREG r5, 0x00010002; +CHECKREG r6, 0x00010003; +CHECKREG r7, 0x00010003; + +imm32 r0, 0x00201001; +R1.L = -1; +imm32 r2, 0x00202002; +imm32 r3, 0x00203003; +imm32 r4, 0x00204004; +imm32 r5, 0x00205005; +imm32 r6, 0x00206006; +imm32 r7, 0x00207007; +R7.L = R0.L >>> 5; +R0.L = R1.L >>> 5; +R1.L = R2.L >>> 5; +R2.L = R3.L >>> 5; +R3.L = R4.L >>> 5; +R4.L = R5.L >>> 5; +R5.L = R6.L >>> 5; +R6.L = R7.L >>> 5; +CHECKREG r0, 0x0020FFFF; +CHECKREG r1, 0x00010100; +CHECKREG r2, 0x00200180; +CHECKREG r3, 0x00200200; +CHECKREG r4, 0x00200280; +CHECKREG r5, 0x00200300; +CHECKREG r6, 0x00200004; +CHECKREG r7, 0x00200080; + + +imm32 r0, 0x03001001; +imm32 r1, 0x03001001; +R2.L = -15; +imm32 r3, 0x03003003; +imm32 r4, 0x03004004; +imm32 r5, 0x03005005; +imm32 r6, 0x03006006; +imm32 r7, 0x03007007; +R6.L = R0.L >>> 2; +R7.L = R1.L >>> 2; +R0.L = R2.L >>> 2; +R1.L = R3.L >>> 2; +R2.L = R4.L >>> 2; +R3.L = R5.L >>> 2; +R4.L = R6.L >>> 2; +R5.L = R7.L >>> 2; +CHECKREG r0, 0x0300FFFC; +CHECKREG r1, 0x03000C00; +CHECKREG r2, 0x00201001; +CHECKREG r3, 0x03001401; +CHECKREG r4, 0x03000100; +CHECKREG r5, 0x03000100; +CHECKREG r6, 0x03000400; +CHECKREG r7, 0x03000400; + +imm32 r0, 0x40001001; +imm32 r1, 0x40001001; +imm32 r2, 0x40002002; +R3.L = -16; +imm32 r4, 0x40004004; +imm32 r5, 0x40005005; +imm32 r6, 0x40006006; +imm32 r7, 0x40007007; +R5.L = R0.L >>> 13; +R6.L = R1.L >>> 13; +R7.L = R2.L >>> 13; +R0.L = R3.L >>> 13; +R1.L = R4.L >>> 13; +R2.L = R5.L >>> 13; +R3.L = R6.L >>> 13; +R4.L = R7.L >>> 13; +CHECKREG r0, 0x4000FFFF; +CHECKREG r1, 0x40000002; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x40000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x40000001; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x50000000; +imm32 r1, 0x50010000; +imm32 r2, 0x50020000; +imm32 r3, 0x50030000; +imm32 r4, 0x50040000; +imm32 r5, 0x50050000; +imm32 r6, 0x50060000; +imm32 r7, 0x50070000; +R3.L = R0.H >>> 10; +R4.L = R1.H >>> 10; +R5.L = R2.H >>> 10; +R6.L = R3.H >>> 10; +R7.L = R4.H >>> 10; +R0.L = R5.H >>> 10; +R1.L = R6.H >>> 10; +R2.L = R7.H >>> 10; +CHECKREG r0, 0x50000014; +CHECKREG r1, 0x50010014; +CHECKREG r2, 0x50020014; +CHECKREG r3, 0x50030014; +CHECKREG r4, 0x50040014; +CHECKREG r5, 0x50050014; +CHECKREG r6, 0x50060014; +CHECKREG r7, 0x50070014; + +imm32 r0, 0x10016000; +R1.L = -1; +imm32 r2, 0x20026000; +imm32 r3, 0x30036000; +imm32 r4, 0x40046000; +imm32 r5, 0x50056000; +imm32 r6, 0x60060000; +imm32 r7, 0x70076000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x10010002; +CHECKREG r1, 0x5001000A; +CHECKREG r2, 0x20020004; +CHECKREG r3, 0x30030006; +CHECKREG r4, 0x40040008; +CHECKREG r5, 0x5005000A; +CHECKREG r6, 0x6006000C; +CHECKREG r7, 0x7007000E; + + +imm32 r0, 0x10010700; +imm32 r1, 0x10010700; +R2.L = -15; +imm32 r3, 0x30030700; +imm32 r4, 0x40040000; +imm32 r5, 0x50050700; +imm32 r6, 0x60060000; +imm32 r7, 0x70070700; +R0.L = R0.H >>> 15; +R1.L = R1.H >>> 15; +R2.L = R2.H >>> 15; +R3.L = R3.H >>> 15; +R4.L = R4.H >>> 15; +R5.L = R5.H >>> 15; +R6.L = R6.H >>> 15; +R7.L = R7.H >>> 15; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x18010001; +imm32 r1, 0x18010001; +imm32 r2, 0x28020002; +R3.L = -16; +imm32 r4, 0x48040004; +imm32 r5, 0x58050005; +imm32 r6, 0x68060006; +imm32 r7, 0x78070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0x18010000; +CHECKREG r1, 0x18010000; +CHECKREG r2, 0x28020001; +CHECKREG r3, 0x30030001; +CHECKREG r4, 0x48040002; +CHECKREG r5, 0x58050002; +CHECKREG r6, 0x68060003; +CHECKREG r7, 0x78070003; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x09000091; +imm32 r1, 0x09000091; +imm32 r2, 0x09000092; +imm32 r3, 0x09000093; +imm32 r4, 0x09000090; +imm32 r5, 0x09000095; +imm32 r6, 0x09000096; +imm32 r7, 0x09000097; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0x00000091; +CHECKREG r1, 0x00000091; +CHECKREG r2, 0x00000092; +CHECKREG r3, 0x00000093; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x00000095; +CHECKREG r6, 0x00000096; +CHECKREG r7, 0x00000097; + +imm32 r0, 0xa0000001; +imm32 r1, 0xa0000001; +imm32 r2, 0xa0000002; +imm32 r3, 0xa0000003; +imm32 r4, 0xa0000004; +R5.L = -1; +imm32 r6, 0xa0000006; +imm32 r7, 0xa0000007; +R0.H = R0.L >>> 15; +R1.H = R1.L >>> 15; +R2.H = R2.L >>> 15; +R3.H = R3.L >>> 15; +R4.H = R4.L >>> 15; +R5.H = R5.L >>> 15; +R6.H = R6.L >>> 15; +R7.H = R7.L >>> 15; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + + +imm32 r0, 0xb0001001; +imm32 r1, 0xb0001001; +imm32 r1, 0xb0002002; +imm32 r3, 0xb0003003; +imm32 r4, 0xb0004004; +imm32 r5, 0xb0005005; +R6.L = -15; +imm32 r7, 0xb0007007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0x00401001; +CHECKREG r1, 0x00802002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00C03003; +CHECKREG r4, 0x01004004; +CHECKREG r5, 0x01405005; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0x01C07007; + +imm32 r0, 0x0c001c01; +imm32 r1, 0x0c002c01; +imm32 r2, 0x0c002c02; +imm32 r3, 0x0c003c03; +imm32 r4, 0x0c004c04; +imm32 r5, 0x0c005c05; +imm32 r6, 0x0c006c06; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0x00381C01; +CHECKREG r1, 0x00582C01; +CHECKREG r2, 0x00582C02; +CHECKREG r3, 0x00783C03; +CHECKREG r4, 0x00984C04; +CHECKREG r5, 0x00B85C05; +CHECKREG r6, 0x00D86C06; +CHECKREG r7, 0xFFFFFFF0; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x0d01d000; +imm32 r1, 0x0d01d000; +imm32 r2, 0x0d02d000; +imm32 r3, 0x0d03d000; +R4.L = -1; +imm32 r5, 0x0d05d000; +imm32 r6, 0x0d06d000; +imm32 r7, 0x0d07d000; +R0.H = R0.H >>> 4; +R1.H = R1.H >>> 4; +R2.H = R2.H >>> 4; +R3.H = R3.H >>> 4; +R4.H = R4.H >>> 4; +R5.H = R5.H >>> 4; +R6.H = R6.H >>> 4; +R7.H = R6.H >>> 4; +CHECKREG r0, 0x00D0D000; +CHECKREG r1, 0x00D0D000; +CHECKREG r2, 0x00D0D000; +CHECKREG r3, 0x00D0D000; +CHECKREG r4, 0x0009FFFF; +CHECKREG r5, 0x00D0D000; +CHECKREG r6, 0x00D0D000; +CHECKREG r7, 0x000DD000; + +imm32 r0, 0x1e010000; +imm32 r1, 0x1e010000; +imm32 r2, 0x2e020000; +imm32 r3, 0x3e030000; +imm32 r4, 0x4e040000; +R5.L = -1; +imm32 r6, 0x6e060000; +imm32 r7, 0x7e070000; +R7.H = R0.H >>> 15; +R6.H = R1.H >>> 15; +R0.H = R2.H >>> 15; +R1.H = R3.H >>> 15; +R2.H = R4.H >>> 15; +R3.H = R5.H >>> 15; +R4.H = R6.H >>> 15; +R5.H = R7.H >>> 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x1f010000; +imm32 r1, 0x1f010000; +imm32 r2, 0x2f020000; +imm32 r3, 0x3f030000; +imm32 r4, 0x4f040000; +imm32 r5, 0x5f050000; +R6.L = -15; +imm32 r7, 0x70070000; +R6.H = R0.H >>> 6; +R7.H = R1.H >>> 6; +R5.H = R2.H >>> 6; +R0.H = R3.H >>> 6; +R1.H = R4.H >>> 6; +R2.H = R5.H >>> 6; +R3.H = R6.H >>> 6; +R4.H = R7.H >>> 6; +CHECKREG r0, 0x00FC0000; +CHECKREG r1, 0x013C0000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00010000; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x00BC0000; +CHECKREG r6, 0x007CFFF1; +CHECKREG r7, 0x007C0000; + +imm32 r0, 0x11010a00; +imm32 r1, 0x11010b00; +imm32 r2, 0x21020d00; +imm32 r2, 0x31030c00; +imm32 r4, 0x41040d00; +imm32 r5, 0x51050e00; +imm32 r6, 0x610600f0; +R7.L = -16; +R5.H = R0.H >>> 7; +R6.H = R1.H >>> 7; +R7.H = R2.H >>> 7; +R2.H = R3.H >>> 7; +R3.H = R4.H >>> 7; +R4.H = R5.H >>> 7; +R0.H = R6.H >>> 7; +R1.H = R7.H >>> 7; +CHECKREG r0, 0x00000A00; +CHECKREG r1, 0x00000B00; +CHECKREG r2, 0x00000C00; +CHECKREG r3, 0x00820000; +CHECKREG r4, 0x00000D00; +CHECKREG r5, 0x00220E00; +CHECKREG r6, 0x002200F0; +CHECKREG r7, 0x0062FFF0; +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_ahalf_rp_s.s b/tests/tcg/bfin/c_dsp32shiftim_ahalf_rp_s.s new file mode 100644 index 0000000000000..6429fb10ab49b --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_ahalf_rp_s.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rp_s/c_dsp32shiftim_ahalf_rp_s.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00010001; +imm32 r2, 0x00010002; +imm32 r3, 0x00010003; +imm32 r4, 0x00010004; +imm32 r5, 0x00010005; +imm32 r6, 0x00010006; +imm32 r7, 0x00010007; +R0.L = R0.L >>> 1; +R1.L = R1.L >>> 1; +R2.L = R2.L >>> 1; +R3.L = R3.L >>> 1; +R4.L = R4.L >>> 1; +R5.L = R5.L >>> 1; +R6.L = R6.L >>> 1; +R7.L = R7.L >>> 1; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00010001; +CHECKREG r3, 0x00010001; +CHECKREG r4, 0x00010002; +CHECKREG r5, 0x00010002; +CHECKREG r6, 0x00010003; +CHECKREG r7, 0x00010003; + +imm32 r0, 0x00201001; +R1.L = -1; +imm32 r2, 0x00202002; +imm32 r3, 0x00203003; +imm32 r4, 0x00204004; +imm32 r5, 0x00205005; +imm32 r6, 0x00206006; +imm32 r7, 0x00207007; +R7.L = R0.L >>> 5; +R0.L = R1.L >>> 5; +R1.L = R2.L >>> 5; +R2.L = R3.L >>> 5; +R3.L = R4.L >>> 5; +R4.L = R5.L >>> 5; +R5.L = R6.L >>> 5; +R6.L = R7.L >>> 5; +CHECKREG r0, 0x0020FFFF; +CHECKREG r1, 0x00010100; +CHECKREG r2, 0x00200180; +CHECKREG r3, 0x00200200; +CHECKREG r4, 0x00200280; +CHECKREG r5, 0x00200300; +CHECKREG r6, 0x00200004; +CHECKREG r7, 0x00200080; + + +imm32 r0, 0x03001001; +imm32 r1, 0x03001001; +R2.L = -15; +imm32 r3, 0x03003003; +imm32 r4, 0x03004004; +imm32 r5, 0x03005005; +imm32 r6, 0x03006006; +imm32 r7, 0x03007007; +R6.L = R0.L >>> 2; +R7.L = R1.L >>> 2; +R0.L = R2.L >>> 2; +R1.L = R3.L >>> 2; +R2.L = R4.L >>> 2; +R3.L = R5.L >>> 2; +R4.L = R6.L >>> 2; +R5.L = R7.L >>> 2; +CHECKREG r0, 0x0300FFFC; +CHECKREG r1, 0x03000C00; +CHECKREG r2, 0x00201001; +CHECKREG r3, 0x03001401; +CHECKREG r4, 0x03000100; +CHECKREG r5, 0x03000100; +CHECKREG r6, 0x03000400; +CHECKREG r7, 0x03000400; + +imm32 r0, 0x40001001; +imm32 r1, 0x40001001; +imm32 r2, 0x40002002; +R3.L = -16; +imm32 r4, 0x40004004; +imm32 r5, 0x40005005; +imm32 r6, 0x40006006; +imm32 r7, 0x40007007; +R5.L = R0.L >>> 13; +R6.L = R1.L >>> 13; +R7.L = R2.L >>> 13; +R0.L = R3.L >>> 13; +R1.L = R4.L >>> 13; +R2.L = R5.L >>> 13; +R3.L = R6.L >>> 13; +R4.L = R7.L >>> 13; +CHECKREG r0, 0x4000FFFF; +CHECKREG r1, 0x40000002; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x40000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x40000001; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x50000000; +imm32 r1, 0x50010000; +imm32 r2, 0x50020000; +imm32 r3, 0x50030000; +imm32 r4, 0x50040000; +imm32 r5, 0x50050000; +imm32 r6, 0x50060000; +imm32 r7, 0x50070000; +R3.L = R0.H >>> 10; +R4.L = R1.H >>> 10; +R5.L = R2.H >>> 10; +R6.L = R3.H >>> 10; +R7.L = R4.H >>> 10; +R0.L = R5.H >>> 10; +R1.L = R6.H >>> 10; +R2.L = R7.H >>> 10; +CHECKREG r0, 0x50000014; +CHECKREG r1, 0x50010014; +CHECKREG r2, 0x50020014; +CHECKREG r3, 0x50030014; +CHECKREG r4, 0x50040014; +CHECKREG r5, 0x50050014; +CHECKREG r6, 0x50060014; +CHECKREG r7, 0x50070014; + +imm32 r0, 0x10016000; +R1.L = -1; +imm32 r2, 0x20026000; +imm32 r3, 0x30036000; +imm32 r4, 0x40046000; +imm32 r5, 0x50056000; +imm32 r6, 0x60060000; +imm32 r7, 0x70076000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x10010002; +CHECKREG r1, 0x5001000A; +CHECKREG r2, 0x20020004; +CHECKREG r3, 0x30030006; +CHECKREG r4, 0x40040008; +CHECKREG r5, 0x5005000A; +CHECKREG r6, 0x6006000C; +CHECKREG r7, 0x7007000E; + + +imm32 r0, 0x10010700; +imm32 r1, 0x10010700; +R2.L = -15; +imm32 r3, 0x30030700; +imm32 r4, 0x40040000; +imm32 r5, 0x50050700; +imm32 r6, 0x60060000; +imm32 r7, 0x70070700; +R0.L = R0.H >>> 15; +R1.L = R1.H >>> 15; +R2.L = R2.H >>> 15; +R3.L = R3.H >>> 15; +R4.L = R4.H >>> 15; +R5.L = R5.H >>> 15; +R6.L = R6.H >>> 15; +R7.L = R7.H >>> 15; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x18010001; +imm32 r1, 0x18010001; +imm32 r2, 0x28020002; +R3.L = -16; +imm32 r4, 0x48040004; +imm32 r5, 0x58050005; +imm32 r6, 0x68060006; +imm32 r7, 0x78070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0x18010000; +CHECKREG r1, 0x18010000; +CHECKREG r2, 0x28020001; +CHECKREG r3, 0x30030001; +CHECKREG r4, 0x48040002; +CHECKREG r5, 0x58050002; +CHECKREG r6, 0x68060003; +CHECKREG r7, 0x78070003; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x09000091; +imm32 r1, 0x09000091; +imm32 r2, 0x09000092; +imm32 r3, 0x09000093; +imm32 r4, 0x09000090; +imm32 r5, 0x09000095; +imm32 r6, 0x09000096; +imm32 r7, 0x09000097; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0x00000091; +CHECKREG r1, 0x00000091; +CHECKREG r2, 0x00000092; +CHECKREG r3, 0x00000093; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x00000095; +CHECKREG r6, 0x00000096; +CHECKREG r7, 0x00000097; + +imm32 r0, 0xa0000001; +imm32 r1, 0xa0000001; +imm32 r2, 0xa0000002; +imm32 r3, 0xa0000003; +imm32 r4, 0xa0000004; +R5.L = -1; +imm32 r6, 0xa0000006; +imm32 r7, 0xa0000007; +R0.H = R0.L >>> 15; +R1.H = R1.L >>> 15; +R2.H = R2.L >>> 15; +R3.H = R3.L >>> 15; +R4.H = R4.L >>> 15; +R5.H = R5.L >>> 15; +R6.H = R6.L >>> 15; +R7.H = R7.L >>> 15; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + + +imm32 r0, 0xb0001001; +imm32 r1, 0xb0001001; +imm32 r1, 0xb0002002; +imm32 r3, 0xb0003003; +imm32 r4, 0xb0004004; +imm32 r5, 0xb0005005; +R6.L = -15; +imm32 r7, 0xb0007007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0x00401001; +CHECKREG r1, 0x00802002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00C03003; +CHECKREG r4, 0x01004004; +CHECKREG r5, 0x01405005; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0x01C07007; + +imm32 r0, 0x0c001c01; +imm32 r1, 0x0c002c01; +imm32 r2, 0x0c002c02; +imm32 r3, 0x0c003c03; +imm32 r4, 0x0c004c04; +imm32 r5, 0x0c005c05; +imm32 r6, 0x0c006c06; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0x00381C01; +CHECKREG r1, 0x00582C01; +CHECKREG r2, 0x00582C02; +CHECKREG r3, 0x00783C03; +CHECKREG r4, 0x00984C04; +CHECKREG r5, 0x00B85C05; +CHECKREG r6, 0x00D86C06; +CHECKREG r7, 0xFFFFFFF0; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x0d01d000; +imm32 r1, 0x0d01d000; +imm32 r2, 0x0d02d000; +imm32 r3, 0x0d03d000; +R4.L = -1; +imm32 r5, 0x0d05d000; +imm32 r6, 0x0d06d000; +imm32 r7, 0x0d07d000; +R0.H = R0.H >>> 4; +R1.H = R1.H >>> 4; +R2.H = R2.H >>> 4; +R3.H = R3.H >>> 4; +R4.H = R4.H >>> 4; +R5.H = R5.H >>> 4; +R6.H = R6.H >>> 4; +R7.H = R6.H >>> 4; +CHECKREG r0, 0x00D0D000; +CHECKREG r1, 0x00D0D000; +CHECKREG r2, 0x00D0D000; +CHECKREG r3, 0x00D0D000; +CHECKREG r4, 0x0009FFFF; +CHECKREG r5, 0x00D0D000; +CHECKREG r6, 0x00D0D000; +CHECKREG r7, 0x000DD000; + +imm32 r0, 0x1e010000; +imm32 r1, 0x1e010000; +imm32 r2, 0x2e020000; +imm32 r3, 0x3e030000; +imm32 r4, 0x4e040000; +R5.L = -1; +imm32 r6, 0x6e060000; +imm32 r7, 0x7e070000; +R7.H = R0.H >>> 15; +R6.H = R1.H >>> 15; +R0.H = R2.H >>> 15; +R1.H = R3.H >>> 15; +R2.H = R4.H >>> 15; +R3.H = R5.H >>> 15; +R4.H = R6.H >>> 15; +R5.H = R7.H >>> 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x1f010000; +imm32 r1, 0x1f010000; +imm32 r2, 0x2f020000; +imm32 r3, 0x3f030000; +imm32 r4, 0x4f040000; +imm32 r5, 0x5f050000; +R6.L = -15; +imm32 r7, 0x70070000; +R6.H = R0.H >>> 6; +R7.H = R1.H >>> 6; +R5.H = R2.H >>> 6; +R0.H = R3.H >>> 6; +R1.H = R4.H >>> 6; +R2.H = R5.H >>> 6; +R3.H = R6.H >>> 6; +R4.H = R7.H >>> 6; +CHECKREG r0, 0x00FC0000; +CHECKREG r1, 0x013C0000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00010000; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x00BC0000; +CHECKREG r6, 0x007CFFF1; +CHECKREG r7, 0x007C0000; + +imm32 r0, 0x11010a00; +imm32 r1, 0x11010b00; +imm32 r2, 0x21020d00; +imm32 r2, 0x31030c00; +imm32 r4, 0x41040d00; +imm32 r5, 0x51050e00; +imm32 r6, 0x610600f0; +R7.L = -16; +R5.H = R0.H >>> 7; +R6.H = R1.H >>> 7; +R7.H = R2.H >>> 7; +R2.H = R3.H >>> 7; +R3.H = R4.H >>> 7; +R4.H = R5.H >>> 7; +R0.H = R6.H >>> 7; +R1.H = R7.H >>> 7; +CHECKREG r0, 0x00000A00; +CHECKREG r1, 0x00000B00; +CHECKREG r2, 0x00000C00; +CHECKREG r3, 0x00820000; +CHECKREG r4, 0x00000D00; +CHECKREG r5, 0x00220E00; +CHECKREG r6, 0x002200F0; +CHECKREG r7, 0x0062FFF0; +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_ahh.s b/tests/tcg/bfin/c_dsp32shiftim_ahh.s new file mode 100644 index 0000000000000..79d19242536cd --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_ahh.s @@ -0,0 +1,65 @@ +//Original:/testcases/core/c_dsp32shiftim_ahh/c_dsp32shiftim_ahh.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift / ashift + + + +imm32 r0, 0x01230abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0 = R0 << 0 (V); +R1 = R1 << 3 (V); +R2 = R2 << 5 (V); +R3 = R3 << 8 (V); +R4 = R4 << 9 (V); +R5 = R5 << 15 (V); +R6 = R6 << 7 (V); +R7 = R7 << 13 (V); +CHECKREG r0, 0x01230ABC; +CHECKREG r1, 0x91A0B3C0; +CHECKREG r2, 0x68A0F120; +CHECKREG r3, 0x56009A00; +CHECKREG r4, 0xCE005600; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xC480E680; +CHECKREG r7, 0x4000C000; + +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7 = R0 >>> 1 (V); +R0 = R1 >>> 8 (V); +R1 = R2 >>> 14 (V); +R2 = R3 >>> 15 (V); +R3 = R4 >>> 11 (V); +R4 = R5 >>> 4 (V); +R5 = R6 >>> 9 (V); +R6 = R7 >>> 6 (V); +CHECKREG r0, 0x00120056; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0008FFF1; +CHECKREG r4, 0x0567F9AB; +CHECKREG r5, 0x0033FFD5; +CHECKREG r6, 0x00020000; +CHECKREG r7, 0x00910000; + + + + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_amix.s b/tests/tcg/bfin/c_dsp32shiftim_amix.s new file mode 100644 index 0000000000000..df33964f7a7ee --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_amix.s @@ -0,0 +1,124 @@ +//Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: mix + + + +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// Ashift : positive data, count (+)=left (half reg) +imm32 r0, 0x00010001; +imm32 r1, 1; +imm32 r2, 0x00020002; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1; /* r4 = 0x00020002 */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r5 = 0x00080008 */ +R6 = R0 << 1 (V); /* r6 = 0x00020002 */ +R7 = R2 << 2 (V); /* r7 = 0x00080008 */ +CHECKREG r4, 0x00020002; +CHECKREG r5, 0x00080008; +CHECKREG r6, 0x00020002; +CHECKREG r7, 0x00080008; + +imm32 r1, 3; +imm32 r3, 4; +R6 = R0 << 3; /* r6 = 0x00080010 */ +R7 = R2 << 4; +CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ +CHECKREG r7, 0x00200020; + +A0 = 0; +A0.L = R0.L; +A0.H = R0.H; +A0 = A0 << 3; /* a0 = 0x00080008 */ +R5 = A0.w; /* r5 = 0x00080008 */ +CHECKREG r5, 0x00080008; + +imm32 r4, 0x30000003; +imm32 r1, 1; +R5 = R4 << 1; /* r5 = 0x60000006 */ + +imm32 r1, 2; +R6 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ +CHECKREG r5, 0x60000006; +CHECKREG r6, 0xc000000c; + + +// Ashift : count (-)=right (half reg) +imm32 r0, 0x10001000; +imm32 r1, -1; +imm32 r2, 0x10001000; +imm32 r3, -2; +R4.H = R0.H >>> 1; +R4.L = R0.L >>> 1; /* r4 = 0x08000800 */ +R5.H = R2.H >>> 2; +R5.L = R2.L >>> 2; /* r4 = 0x04000400 */ +R6 = R0 >>> 1 (V); /* r4 = 0x08000800 */ +R7 = R2 >>> 2 (V); /* r4 = 0x04000400 */ +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x04000400; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x04000400; + +// Ashift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >>> 3; /* r6 = 0x02000200 */ +R7 = R2 >>> 4; /* r7 = 0x01000100 */ +CHECKREG r6, 0x02000200; +CHECKREG r7, 0x01000100; + +// NEGATIVE +// Ashift : NEGATIVE data, count (+)=left (half reg) +imm32 r0, 0xc00f800f; +imm32 r1, 1; +imm32 r2, 0xe00fe00f; +imm32 r3, 2; +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r4 = 0x803c803c */ +CHECKREG r5, 0x803c803c; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +imm32 r1, 4; +imm32 r3, 5; +R6 = R0 << 4; /* r6 = 0x80fe00f0 */ +R7 = R2 << 5; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok +imm32 r0, 0x80f080f0; +imm32 r1, -1; +imm32 r2, 0x80f080f0; +imm32 r3, -2; +R4.H = R0.H >>> 1; +R4.L = R0.L >>> 1; /* r4 = 0xc078c078 */ +R5.H = R2.H >>> 2; +R5.L = R2.L >>> 2; /* r4 = 0xe03ce03c */ +CHECKREG r4, 0xc078c078; +CHECKREG r5, 0xe03ce03c; +R6 = R0 >>> 1 (V); /* r6 = 0xc078c078 */ +R7 = R2 >>> 2 (V); /* r7 = 0xe03ce03c */ +CHECKREG r6, 0xc078c078; +CHECKREG r7, 0xe03ce03c; + +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >>> 3; /* r6 = 0xf01e101e */ +R7 = R2 >>> 4; /* r7 = 0xf80f080f */ +CHECKREG r6, 0xf01e101e; +CHECKREG r7, 0xf80f080f; + + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_lf.s b/tests/tcg/bfin/c_dsp32shiftim_lf.s new file mode 100644 index 0000000000000..30831731d28b2 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_lf.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_dsp32shiftim_lf/c_dsp32shiftim_lf.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm lshift: lshift + + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R0 = R0 << 0; +R1 = R1 << 3; +R2 = R2 << 7; +R3 = R3 << 8; +R4 = R4 << 15; +R5 = R5 << 24; +R6 = R6 << 31; +R7 = R7 << 20; +CHECKREG r0, 0xA1230001; +CHECKREG r1, 0xD9A2B3C0; +CHECKREG r2, 0xE2B3C480; +CHECKREG r3, 0xD6789A00; +CHECKREG r4, 0xC4D58000; +CHECKREG r5, 0xBC000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0xCDE00000; + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R6 = R0 >> 1; +R7 = R1 >> 3; +R0 = R2 >> 7; +R1 = R3 >> 8; +R2 = R4 >> 15; +R3 = R5 >> 24; +R4 = R6 >> 31; +R5 = R7 >> 20; +CHECKREG r0, 0x00478ACF; +CHECKREG r1, 0x0034D678; +CHECKREG r2, 0x00010B4F; +CHECKREG r3, 0x00000096; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000036; +CHECKREG r6, 0x50918000; +CHECKREG r7, 0x03668ACF; + + + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_lhalf_ln.s b/tests/tcg/bfin/c_dsp32shiftim_lhalf_ln.s new file mode 100644 index 0000000000000..36004fd1911b6 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_lhalf_ln.s @@ -0,0 +1,401 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_ln/c_dsp32shiftim_lhalf_ln.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : neg data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = R0.L << 1; +R1.L = R1.L << 0; +R2.L = R2.L << 0; +R3.L = R3.L << 0; +R4.L = R4.L << 0; +R5.L = R5.L << 0; +R6.L = R6.L << 0; +R7.L = R7.L << 0; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000C001; +CHECKREG r2, 0x0000C002; +CHECKREG r3, 0x0000C003; +CHECKREG r4, 0x0000C004; +CHECKREG r5, 0x0000C005; +CHECKREG r6, 0x0000C006; +CHECKREG r7, 0x0000C007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R1.L = R0.L << 1; +R2.L = R1.L << 2; +R3.L = R2.L << 3; +R4.L = R3.L << 4; +R5.L = R4.L << 5; +R6.L = R5.L << 6; +R7.L = R6.L << 7; +R0.L = R7.L << 8; +imm32 r1, 0x2000d001; +imm32 r2, 0x2000000f; +imm32 r3, 0x2000e003; +imm32 r4, 0x2000f004; +imm32 r5, 0x2200f005; +imm32 r6, 0x2000f006; +imm32 r7, 0x2000f007; +imm32 r0, 0x2000c001; + +R2.L = R0.L << 10; +R3.L = R1.L << 12; +R4.L = R2.L << 13; +R5.L = R3.L << 14; +R6.L = R4.L << 15; +R7.L = R5.L << 15; +R0.L = R6.L << 2; +R1.L = R7.L << 3; +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x20000000; +CHECKREG r2, 0x20000400; +CHECKREG r3, 0x20001000; +CHECKREG r4, 0x20000000; +CHECKREG r5, 0x22000000; +CHECKREG r6, 0x20000000; +CHECKREG r7, 0x20000000; + +imm32 r0, 0x30009001; +imm32 r1, 0x3000a001; +imm32 r2, 0x3000b002; +imm32 r3, 0x30000010; +imm32 r4, 0x3000c004; +imm32 r5, 0x3000d005; +imm32 r6, 0x3000e006; +imm32 r7, 0x3000f007; +R3.L = R0.L << 12; +R4.L = R1.L << 13; +R5.L = R2.L << 14; +R6.L = R3.L << 15; +R7.L = R4.L << 11; +R0.L = R5.L << 12; +R1.L = R6.L << 13; +R2.L = R7.L << 15; +CHECKREG r0, 0x30000000; +CHECKREG r1, 0x30000000; +CHECKREG r2, 0x30000000; +CHECKREG r3, 0x30001000; +CHECKREG r4, 0x30002000; +CHECKREG r5, 0x30008000; +CHECKREG r6, 0x30000000; +CHECKREG r7, 0x30000000; +// RHx by RLx +imm32 r0, 0x00000040; +imm32 r1, 0x00010040; +imm32 r2, 0x00020040; +imm32 r3, 0x00030040; +imm32 r4, 0x00040040; +imm32 r5, 0x00050040; +imm32 r6, 0x00060040; +imm32 r7, 0x00070040; +R0.L = R0.H << 0; +R1.L = R1.H << 1; +R2.L = R2.H << 2; +R3.L = R3.H << 3; +R4.L = R4.H << 4; +R5.L = R5.H << 5; +R6.L = R6.H << 6; +R7.L = R7.H << 7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010002; +CHECKREG r2, 0x00020008; +CHECKREG r3, 0x00030018; +CHECKREG r4, 0x00040040; +CHECKREG r5, 0x000500A0; +CHECKREG r6, 0x00060180; +CHECKREG r7, 0x00070380; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R1.L = R0.H << 1; +R2.L = R1.H << 2; +R3.L = R2.H << 3; +R4.L = R3.H << 4; +R5.L = R4.H << 5; +R6.L = R5.H << 6; +R7.L = R6.H << 7; +R0.L = R7.H << 8; +CHECKREG r1, 0x00012002; +CHECKREG r2, 0x90020004; +CHECKREG r3, 0x90038010; +CHECKREG r4, 0x90040030; +CHECKREG r5, 0x90050080; +CHECKREG r6, 0x90060140; +CHECKREG r7, 0x90070300; +CHECKREG r0, 0x90010700; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R2.L = R0.H << 15; +R3.L = R1.H << 15; +R4.L = R2.H << 15; +R5.L = R3.H << 15; +R6.L = R4.H << 15; +R7.L = R5.H << 15; +R0.L = R6.H << 15; +R1.L = R7.H << 15; +CHECKREG r0, 0xA0010000; +CHECKREG r1, 0xA0018000; +CHECKREG r2, 0xA0028000; +CHECKREG r3, 0xA0038000; +CHECKREG r4, 0xA0040000; +CHECKREG r5, 0xA0058000; +CHECKREG r6, 0xA0060000; +CHECKREG r7, 0xA0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R3.L = R0.H << 14; +R4.L = R1.H << 14; +R5.L = R2.H << 14; +R6.L = R3.H << 14; +R7.L = R4.H << 14; +R0.L = R5.H << 14; +R1.L = R6.H << 14; +R2.L = R7.H << 14; +CHECKREG r0, 0xC0014000; +CHECKREG r1, 0xC0018000; +CHECKREG r2, 0xC002C000; +CHECKREG r3, 0xC0034000; +CHECKREG r4, 0xC0044000; +CHECKREG r5, 0xC0058000; +CHECKREG r6, 0xC006C000; +CHECKREG r7, 0xC0070000; + +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = R0.L << 12; +R1.H = R1.L << 12; +R2.H = R2.L << 13; +R3.H = R3.L << 14; +R4.H = R4.L << 15; +R5.H = R5.L << 14; +R6.H = R6.L << 7; +R7.H = R7.L << 8; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x10000001; +CHECKREG r2, 0x40000002; +CHECKREG r3, 0xC0000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x40000005; +CHECKREG r6, 0x03000006; +CHECKREG r7, 0x07000007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R1.H = R0.L << 3; +R2.H = R1.L << 4; +R3.H = R2.L << 5; +R4.H = R3.L << 6; +R5.H = R4.L << 7; +R6.H = R5.L << 8; +R7.H = R6.L << 9; +R0.H = R7.L << 8; +CHECKREG r1, 0x80080001; +CHECKREG r2, 0x0010D002; +CHECKREG r3, 0x0040D003; +CHECKREG r4, 0x00C0D004; +CHECKREG r5, 0x0200D005; +CHECKREG r6, 0x0500D006; +CHECKREG r7, 0x0C00D007; +CHECKREG r0, 0x0700D001; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R2.H = R0.L << 15; +R3.H = R1.L << 15; +R4.H = R2.L << 15; +R5.H = R3.L << 15; +R6.H = R4.L << 15; +R7.H = R5.L << 15; +R0.H = R6.L << 15; +R1.H = R7.L << 15; +CHECKREG r0, 0x0000E001; +CHECKREG r1, 0x8000E001; +CHECKREG r2, 0x8000000F; +CHECKREG r3, 0x8000E003; +CHECKREG r4, 0x8000E004; +CHECKREG r5, 0x8000E005; +CHECKREG r6, 0x0000E006; +CHECKREG r7, 0x8000E007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R3.H = R0.L << 13; +R4.H = R1.L << 13; +R5.H = R2.L << 13; +R6.H = R3.L << 13; +R7.H = R4.L << 13; +R0.H = R5.L << 13; +R1.H = R6.L << 13; +R2.H = R7.L << 13; +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = R0.H << 0; +R1.H = R1.H << 0; +R2.H = R2.H << 0; +R3.H = R3.H << 0; +R4.H = R4.H << 0; +R5.H = R5.H << 0; +R6.H = R6.H << 0; +R7.H = R7.H << 0; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R1.H = R0.H << 1; +R2.H = R1.H << 1; +R3.H = R2.H << 1; +R4.H = R3.H << 1; +R5.H = R4.H << 1; +R6.H = R5.H << 1; +R7.H = R6.H << 1; +R0.H = R7.H << 1; +CHECKREG r1, 0x40020001; +CHECKREG r2, 0x80040000; +CHECKREG r3, 0x00080000; +CHECKREG r4, 0x00100000; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00400000; +CHECKREG r7, 0x00800000; +CHECKREG r0, 0x01000000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R2.H = R0.H << 15; +R3.H = R1.H << 15; +R4.H = R2.H << 15; +R5.H = R3.H << 15; +R6.H = R4.H << 15; +R7.H = R5.H << 15; +R0.H = R6.H << 15; +R1.H = R7.H << 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x8000000F; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R6.H = R0.H << 12; +R7.H = R1.H << 12; +R0.H = R2.H << 12; +R1.H = R3.H << 12; +R2.H = R4.H << 12; +R3.H = R5.H << 12; +R4.H = R6.H << 12; +R5.H = R7.H << 12; +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x30000000; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x50000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x10000000; +CHECKREG r7, 0x10000000; + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_lhalf_lp.s b/tests/tcg/bfin/c_dsp32shiftim_lhalf_lp.s new file mode 100644 index 0000000000000..53e53f2ab213e --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_lhalf_lp.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_lp/c_dsp32shiftim_lhalf_lp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY imm5) +// RLx by imm5 +imm32 r0, 0x00100a00; +imm32 r1, 0x00100a01; +imm32 r2, 0x00100a02; +imm32 r3, 0x00100a03; +imm32 r4, 0x00100a04; +imm32 r5, 0x00100a05; +imm32 r6, 0x00100a06; +imm32 r7, 0x00100a07; +R7.L = R0.L << 0; +R0.L = R1.L << 1; +R1.L = R2.L << 2; +R2.L = R3.L << 3; +R3.L = R4.L << 4; +R4.L = R5.L << 5; +R5.L = R6.L << 6; +R6.L = R7.L << 7; +CHECKREG r1, 0x00102808; +CHECKREG r0, 0x00101402; +CHECKREG r2, 0x00105018; +CHECKREG r3, 0x0010A040; +CHECKREG r4, 0x001040A0; +CHECKREG r5, 0x00108180; +CHECKREG r6, 0x00100000; +CHECKREG r7, 0x00100A00; + +imm32 r0, 0x00200018; +imm32 r1, 0x00200019; +imm32 r2, 0x0020001a; +imm32 r3, 0x0020001b; +imm32 r4, 0x0020001c; +imm32 r5, 0x0020001d; +imm32 r6, 0x0020001e; +imm32 r7, 0x0020001f; +R2.L = R0.L << 8; +R3.L = R1.L << 9; +R4.L = R2.L << 10; +R5.L = R3.L << 11; +R6.L = R4.L << 12; +R7.L = R5.L << 13; +R0.L = R6.L << 14; +R1.L = R7.L << 15; +CHECKREG r0, 0x00200000; +CHECKREG r1, 0x00200000; +CHECKREG r2, 0x00201800; +CHECKREG r3, 0x00203200; +CHECKREG r4, 0x00200000; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00200000; +CHECKREG r7, 0x00200000; + +imm32 r0, 0x05002001; +imm32 r1, 0x05002001; +imm32 r2, 0x0500000f; +imm32 r3, 0x05002003; +imm32 r4, 0x05002004; +imm32 r5, 0x05002005; +imm32 r6, 0x05002006; +imm32 r7, 0x05002007; +R3.L = R0.L << 0; +R4.L = R1.L << 1; +R5.L = R2.L << 2; +R6.L = R3.L << 3; +R7.L = R4.L << 4; +R0.L = R5.L << 5; +R1.L = R6.L << 6; +R2.L = R7.L << 7; +CHECKREG r0, 0x05000780; +CHECKREG r1, 0x05000200; +CHECKREG r2, 0x05001000; +CHECKREG r3, 0x05002001; +CHECKREG r4, 0x05004002; +CHECKREG r5, 0x0500003C; +CHECKREG r6, 0x05000008; +CHECKREG r7, 0x05000020; + +imm32 r0, 0x03000031; +imm32 r1, 0x03000031; +imm32 r2, 0x03000032; +imm32 r3, 0x03000030; +imm32 r4, 0x03000034; +imm32 r5, 0x03000035; +imm32 r6, 0x03000036; +imm32 r7, 0x03000037; +R4.L = R0.L << 8; +R5.L = R1.L << 9; +R6.L = R2.L << 10; +R7.L = R3.L << 11; +R0.L = R4.L << 12; +R1.L = R5.L << 13; +R2.L = R6.L << 14; +R3.L = R7.L << 15; +CHECKREG r0, 0x03000000; +CHECKREG r1, 0x03000000; +CHECKREG r2, 0x03000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x03003100; +CHECKREG r5, 0x03006200; +CHECKREG r6, 0x0300C800; +CHECKREG r7, 0x03008000; +// RHx by RLx +imm32 r0, 0x03000000; +imm32 r1, 0x03000000; +imm32 r2, 0x03000000; +imm32 r3, 0x03000000; +imm32 r4, 0x03003100; +imm32 r5, 0x03006200; +imm32 r6, 0x0300C800; +imm32 r7, 0x03008000; +R5.L = R0.H << 0; +R6.L = R1.H << 1; +R7.L = R2.H << 2; +R0.L = R3.H << 3; +R1.L = R4.H << 4; +R2.L = R5.H << 5; +R3.L = R6.H << 6; +R4.L = R7.H << 7; +CHECKREG r0, 0x03001800; +CHECKREG r1, 0x03003000; +CHECKREG r2, 0x03006000; +CHECKREG r3, 0x0300C000; +CHECKREG r4, 0x03008000; +CHECKREG r5, 0x03000300; +CHECKREG r6, 0x03000600; +CHECKREG r7, 0x03000C00; + +imm32 r0, 0x05018000; +imm32 r1, 0x05018001; +imm32 r2, 0x05028000; +imm32 r3, 0x05038000; +imm32 r4, 0x05048000; +imm32 r5, 0x05058000; +imm32 r6, 0x05068000; +imm32 r7, 0x05078000; +R6.L = R0.H << 8; +R7.L = R1.H << 9; +R0.L = R2.H << 10; +R1.L = R3.H << 11; +R2.L = R4.H << 12; +R3.L = R5.H << 13; +R4.L = R6.H << 14; +R5.L = R7.H << 15; +CHECKREG r0, 0x05010800; +CHECKREG r1, 0x05011800; +CHECKREG r2, 0x05024000; +CHECKREG r3, 0x0503A000; +CHECKREG r4, 0x05048000; +CHECKREG r5, 0x05058000; +CHECKREG r6, 0x05060100; +CHECKREG r7, 0x05070200; + + +imm32 r0, 0x60019000; +imm32 r1, 0x60019000; +imm32 r2, 0x6002900f; +imm32 r3, 0x60039000; +imm32 r4, 0x60049000; +imm32 r5, 0x60059000; +imm32 r6, 0x60069000; +imm32 r7, 0x60079000; +R7.L = R0.H << 0; +R0.L = R1.H << 1; +R1.L = R2.H << 2; +R2.L = R3.H << 3; +R3.L = R4.H << 4; +R4.L = R5.H << 5; +R5.L = R6.H << 6; +R6.L = R7.H << 7; +CHECKREG r0, 0x6001C002; +CHECKREG r1, 0x60018008; +CHECKREG r2, 0x60020018; +CHECKREG r3, 0x60030040; +CHECKREG r4, 0x600400A0; +CHECKREG r5, 0x60050180; +CHECKREG r6, 0x60060380; +CHECKREG r7, 0x60076001; + +imm32 r0, 0x70010001; +imm32 r1, 0x70010001; +imm32 r2, 0x70020002; +imm32 r3, 0x77030010; +imm32 r4, 0x70040004; +imm32 r5, 0x70050005; +imm32 r6, 0x70060006; +imm32 r7, 0x70070007; +R0.L = R0.H << 8; +R1.L = R1.H << 9; +R2.L = R2.H << 10; +R3.L = R3.H << 11; +R4.L = R4.H << 12; +R5.L = R5.H << 13; +R6.L = R6.H << 14; +R7.L = R7.H << 15; +CHECKREG r0, 0x70010100; +CHECKREG r1, 0x70010200; +CHECKREG r2, 0x70020800; +CHECKREG r3, 0x77031800; +CHECKREG r4, 0x70044000; +CHECKREG r5, 0x7005A000; +CHECKREG r6, 0x70068000; +CHECKREG r7, 0x70078000; + +// d_hi = lshft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0xa8000000; +imm32 r1, 0xa8000001; +imm32 r2, 0xa8000002; +imm32 r3, 0xa8000003; +imm32 r4, 0xa8000004; +imm32 r5, 0xa8000005; +imm32 r6, 0xa8000006; +imm32 r7, 0xa8000007; +R0.H = R0.L << 0; +R1.H = R1.L << 1; +R2.H = R2.L << 2; +R3.H = R3.L << 3; +R4.H = R4.L << 4; +R5.H = R5.L << 5; +R6.H = R6.L << 6; +R7.H = R7.L << 7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00080002; +CHECKREG r3, 0x00180003; +CHECKREG r4, 0x00400004; +CHECKREG r5, 0x00A00005; +CHECKREG r6, 0x01800006; +CHECKREG r7, 0x03800007; + +imm32 r0, 0xf0090001; +imm32 r1, 0xf0090001; +imm32 r2, 0xf0090002; +imm32 r3, 0xf0090003; +imm32 r4, 0xf0090004; +imm32 r5, 0xf0090005; +imm32 r6, 0xf0000006; +imm32 r7, 0xf0000007; +R1.H = R0.L << 8; +R2.H = R1.L << 9; +R3.H = R2.L << 10; +R4.H = R3.L << 11; +R5.H = R4.L << 12; +R6.H = R5.L << 13; +R7.H = R6.L << 14; +R0.H = R7.L << 15; +CHECKREG r1, 0x01000001; +CHECKREG r2, 0x02000002; +CHECKREG r3, 0x08000003; +CHECKREG r4, 0x18000004; +CHECKREG r5, 0x40000005; +CHECKREG r6, 0xA0000006; +CHECKREG r7, 0x80000007; +CHECKREG r0, 0x80000001; + + +imm32 r0, 0x07000001; +imm32 r1, 0x07000001; +imm32 r2, 0x0700000f; +imm32 r3, 0x07000003; +imm32 r4, 0x07000004; +imm32 r5, 0x07000005; +imm32 r6, 0x07000006; +imm32 r7, 0x07000007; +R3.H = R0.L << 0; +R4.H = R1.L << 1; +R5.H = R2.L << 2; +R6.H = R3.L << 3; +R7.H = R4.L << 4; +R0.H = R5.L << 5; +R1.H = R6.L << 6; +R2.H = R7.L << 7; +CHECKREG r0, 0x00A00001; +CHECKREG r1, 0x01800001; +CHECKREG r2, 0x0380000F; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +CHECKREG r5, 0x003C0005; +CHECKREG r6, 0x00180006; +CHECKREG r7, 0x00400007; + +imm32 r0, 0x00000501; +imm32 r1, 0x00000501; +imm32 r2, 0x00000502; +imm32 r3, 0x00000510; +imm32 r4, 0x00000504; +imm32 r5, 0x00000505; +imm32 r6, 0x00000506; +imm32 r7, 0x00000507; +R4.H = R0.L << 8; +R5.H = R1.L << 9; +R6.H = R2.L << 10; +R7.H = R3.L << 11; +R0.H = R4.L << 12; +R1.H = R5.L << 13; +R2.H = R6.L << 14; +R3.H = R7.L << 15; +CHECKREG r0, 0x40000501; +CHECKREG r1, 0xA0000501; +CHECKREG r2, 0x80000502; +CHECKREG r3, 0x80000510; +CHECKREG r4, 0x01000504; +CHECKREG r5, 0x02000505; +CHECKREG r6, 0x08000506; +CHECKREG r7, 0x80000507; + +imm32 r0, 0x00a00800; +imm32 r1, 0x00a10800; +imm32 r2, 0x00a20800; +imm32 r3, 0x00a30800; +imm32 r4, 0x00a40800; +imm32 r5, 0x00a50800; +imm32 r6, 0x00a60800; +imm32 r7, 0x00a70800; +R5.H = R0.H << 0; +R6.H = R1.H << 1; +R7.H = R2.H << 2; +R0.H = R3.H << 3; +R1.H = R4.H << 4; +R2.H = R5.H << 5; +R3.H = R6.H << 6; +R4.H = R7.H << 7; +CHECKREG r0, 0x05180800; +CHECKREG r1, 0x0A400800; +CHECKREG r2, 0x14000800; +CHECKREG r3, 0x50800800; +CHECKREG r4, 0x44000800; +CHECKREG r5, 0x00A00800; +CHECKREG r6, 0x01420800; +CHECKREG r7, 0x02880800; + +imm32 r0, 0x0c010000; +imm32 r1, 0x0c010001; +imm32 r2, 0x0c020000; +imm32 r3, 0x0c030000; +imm32 r4, 0x0c040000; +imm32 r5, 0x0c050000; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c070000; +R6.H = R0.H << 8; +R7.H = R1.H << 9; +R0.H = R2.H << 10; +R1.H = R3.H << 11; +R2.H = R4.H << 12; +R3.H = R5.H << 13; +R4.H = R6.H << 14; +R5.H = R7.H << 15; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x18000001; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0xA0000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x01000000; +CHECKREG r7, 0x02000000; + + +imm32 r0, 0x00b10000; +imm32 r1, 0x00b10000; +imm32 r2, 0x00b2000f; +imm32 r3, 0x00b30000; +imm32 r4, 0x00b40000; +imm32 r5, 0x00b50000; +imm32 r6, 0x00b60000; +imm32 r7, 0x00b70000; +R7.L = R0.H << 0; +R0.L = R1.H << 1; +R1.L = R2.H << 2; +R2.L = R3.H << 3; +R3.L = R4.H << 4; +R4.L = R5.H << 5; +R5.L = R6.H << 6; +R6.L = R7.H << 7; +CHECKREG r0, 0x00B10162; +CHECKREG r1, 0x00B102C8; +CHECKREG r2, 0x00B20598; +CHECKREG r3, 0x00B30B40; +CHECKREG r4, 0x00B416A0; +CHECKREG r5, 0x00B52D80; +CHECKREG r6, 0x00B65B80; +CHECKREG r7, 0x00B700B1; + +imm32 r0, 0x0a010700; +imm32 r1, 0x0a010700; +imm32 r2, 0x0a020700; +imm32 r3, 0x0a030710; +imm32 r4, 0x0a040700; +imm32 r5, 0x0a050700; +imm32 r6, 0x0a060700; +imm32 r7, 0x0a070700; +R0.H = R0.H << 8; +R1.H = R1.H << 9; +R2.H = R2.H << 10; +R3.H = R3.H << 11; +R4.H = R4.H << 12; +R5.H = R5.H << 13; +R6.H = R6.H << 14; +R7.H = R7.H << 15; +CHECKREG r0, 0x01000700; +CHECKREG r1, 0x02000700; +CHECKREG r2, 0x08000700; +CHECKREG r3, 0x18000710; +CHECKREG r4, 0x40000700; +CHECKREG r5, 0xA0000700; +CHECKREG r6, 0x80000700; +CHECKREG r7, 0x80000700; + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_lhalf_rn.s b/tests/tcg/bfin/c_dsp32shiftim_lhalf_rn.s new file mode 100644 index 0000000000000..a14a4c3fa1ba5 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_lhalf_rn.s @@ -0,0 +1,424 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_rn/c_dsp32shiftim_lhalf_rn.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : neg data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >> 1; +R1.L = R1.L >> 2; +R2.L = R2.L >> 3; +R3.L = R3.L >> 4; +R4.L = R4.L >> 5; +R5.L = R5.L >> 6; +R6.L = R6.L >> 7; +R7.L = R7.L >> 8; +CHECKREG r0, 0x00007FFF; +CHECKREG r1, 0x00002000; +CHECKREG r2, 0x00001000; +CHECKREG r3, 0x00000800; +CHECKREG r4, 0x00000400; +CHECKREG r5, 0x00000200; +CHECKREG r6, 0x00000100; +CHECKREG r7, 0x00000080; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >> 9; +R1.L = R1.L >> 10; +R2.L = R2.L >> 11; +R3.L = R3.L >> 12; +R4.L = R4.L >> 13; +R5.L = R5.L >> 14; +R6.L = R6.L >> 15; +R7.L = R7.L >> 10; +CHECKREG r0, 0x00000040; +CHECKREG r1, 0x0000003F; +CHECKREG r2, 0x00000010; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000020; + + +imm32 r0, 0x30008001; +imm32 r1, 0x30008001; +R2.L = -15; +imm32 r3, 0x30008003; +imm32 r4, 0x30008004; +imm32 r5, 0x30008005; +imm32 r6, 0x30008006; +imm32 r7, 0x30008007; +R7.L = R0.L >> 1; +R6.L = R1.L >> 2; +R5.L = R2.L >> 3; +R4.L = R3.L >> 4; +R3.L = R4.L >> 5; +R2.L = R5.L >> 6; +R0.L = R7.L >> 8; +R1.L = R6.L >> 7; +CHECKREG r0, 0x30000040; +CHECKREG r1, 0x30000040; +CHECKREG r2, 0x0000007F; +CHECKREG r3, 0x30000040; +CHECKREG r4, 0x30000800; +CHECKREG r5, 0x30001FFE; +CHECKREG r6, 0x30002000; +CHECKREG r7, 0x30004000; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R6.L = R0.L >> 13; +R5.L = R1.L >> 13; +R4.L = R2.L >> 13; +R3.L = R3.L >> 13; +R2.L = R4.L >> 13; +R1.L = R5.L >> 13; +R0.L = R6.L >> 13; +R7.L = R7.L >> 13; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x30000007; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000004; +CHECKREG r6, 0x00000004; +CHECKREG r7, 0x00000004; + +// d_lo = lshift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = R0.H >> 1; +R1.L = R1.H >> 1; +R2.L = R2.H >> 1; +R3.L = R3.H >> 1; +R4.L = R4.H >> 1; +R5.L = R5.H >> 1; +R6.L = R6.H >> 1; +R7.L = R7.H >> 1; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80014000; +CHECKREG r2, 0x80024001; +CHECKREG r3, 0x80034001; +CHECKREG r4, 0x80044002; +CHECKREG r5, 0x80054002; +CHECKREG r6, 0x80064003; +CHECKREG r7, 0x80074003; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R1.L = R0.H >> 10; +R2.L = R1.H >> 11; +R3.L = R2.H >> 12; +R4.L = R3.H >> 13; +R5.L = R4.H >> 14; +R6.L = R5.H >> 15; +R0.L = R7.H >> 15; +R7.L = R6.H >> 15; +CHECKREG r0, 0x80010001; +CHECKREG r1, 0x80010020; +CHECKREG r2, 0x80020010; +CHECKREG r3, 0x80030008; +CHECKREG r4, 0x80040004; +CHECKREG r5, 0x80050002; +CHECKREG r6, 0x80060001; +CHECKREG r7, 0x80070001; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R2.L = R0.H >> 2; +R3.L = R1.H >> 2; +R4.L = R2.H >> 2; +R5.L = R3.H >> 2; +R6.L = R4.H >> 2; +R7.L = R5.H >> 2; +R0.L = R6.H >> 2; +R1.L = R7.H >> 2; +CHECKREG r0, 0xA0012801; +CHECKREG r1, 0xA0012801; +CHECKREG r2, 0x80022800; +CHECKREG r3, 0xA0032800; +CHECKREG r4, 0xA0042000; +CHECKREG r5, 0xA0052800; +CHECKREG r6, 0xA0062801; +CHECKREG r7, 0xA0072801; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R3.L = R0.H >> 13; +R4.L = R1.H >> 13; +R5.L = R2.H >> 13; +R6.L = R3.H >> 13; +R7.L = R4.H >> 13; +R0.L = R5.H >> 13; +R1.L = R6.H >> 13; +R2.L = R7.H >> 13; +CHECKREG r0, 0xB0010005; +CHECKREG r1, 0xB0010005; +CHECKREG r2, 0xB0020005; +CHECKREG r3, 0xA0030005; +CHECKREG r4, 0xB0040005; +CHECKREG r5, 0xB0050005; +CHECKREG r6, 0xB0060005; +CHECKREG r7, 0xB0070005; + +// d_hi = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = R0.L >> 14; +R1.H = R1.L >> 14; +R2.H = R2.L >> 14; +R3.H = R3.L >> 14; +R4.H = R4.L >> 14; +R5.H = R5.L >> 14; +R6.H = R6.L >> 14; +R7.H = R7.L >> 14; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R1.H = R0.L >> 5; +R0.H = R7.L >> 5; +R2.H = R1.L >> 5; +R3.H = R2.L >> 5; +R4.H = R3.L >> 5; +R5.H = R4.L >> 5; +R6.H = R5.L >> 5; +R7.H = R6.L >> 5; +CHECKREG r0, 0x04008001; +CHECKREG r1, 0x04008001; +CHECKREG r2, 0x04008002; +CHECKREG r3, 0x04008003; +CHECKREG r4, 0x04008004; +CHECKREG r5, 0x0400FFFF; +CHECKREG r6, 0x07FF8006; +CHECKREG r7, 0x04008007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R3.H = R0.L >> 14; +R4.H = R1.L >> 14; +R5.H = R2.L >> 14; +R6.H = R3.L >> 14; +R7.H = R4.L >> 14; +R0.H = R5.L >> 14; +R1.H = R6.L >> 14; +R2.H = R7.L >> 14; +CHECKREG r0, 0x00029001; +CHECKREG r1, 0x00039001; +CHECKREG r2, 0x00029002; +CHECKREG r3, 0x00029003; +CHECKREG r4, 0x00029004; +CHECKREG r5, 0x00029005; +CHECKREG r6, 0x0002FFF1; +CHECKREG r7, 0x00029007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R4.H = R0.L >> 15; +R5.H = R1.L >> 15; +R6.H = R2.L >> 15; +R7.H = R3.L >> 15; +R0.H = R4.L >> 15; +R1.H = R5.L >> 15; +R2.H = R6.L >> 15; +R3.H = R7.L >> 15; +CHECKREG r0, 0x0001A001; +CHECKREG r1, 0x0001A001; +CHECKREG r2, 0x0001A002; +CHECKREG r3, 0x0001A003; +CHECKREG r4, 0x0001A004; +CHECKREG r5, 0x0001A005; +CHECKREG r6, 0x0001A006; +CHECKREG r7, 0x0001FFF0; + +// d_lo = lshft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = R0.H >> 4; +R1.H = R1.H >> 4; +R2.H = R2.H >> 4; +R3.H = R3.H >> 4; +R4.H = R4.H >> 4; +R5.H = R5.H >> 4; +R6.H = R6.H >> 4; +R7.H = R7.H >> 4; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x08000000; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x08000000; +CHECKREG r6, 0x08000000; +CHECKREG r7, 0x08000000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R1.H = R0.H >> 15; +R2.H = R1.H >> 15; +R3.H = R2.H >> 15; +R4.H = R3.H >> 15; +R5.H = R4.H >> 15; +R6.H = R5.H >> 15; +R0.H = R7.H >> 15; +R7.H = R6.H >> 15; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R3.H = R0.H >> 6; +R4.H = R1.H >> 6; +R5.H = R2.H >> 6; +R6.H = R3.H >> 6; +R7.H = R4.H >> 6; +R0.H = R5.H >> 6; +R1.H = R6.H >> 6; +R2.H = R7.H >> 6; +CHECKREG r0, 0x000D0000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x03400000; +CHECKREG r4, 0x03400000; +CHECKREG r5, 0x03400000; +CHECKREG r6, 0x000DFFF1; +CHECKREG r7, 0x000D0000; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R4.H = R0.H >> 7; +R5.H = R1.H >> 7; +R6.H = R2.H >> 7; +R7.H = R3.H >> 7; +R0.H = R4.H >> 7; +R1.H = R5.H >> 7; +R2.H = R6.H >> 7; +R3.H = R7.H >> 7; +CHECKREG r0, 0x00030000; +CHECKREG r1, 0x00030000; +CHECKREG r2, 0x00030000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x01C00000; +CHECKREG r5, 0x01C00000; +CHECKREG r6, 0x01C00000; +CHECKREG r7, 0x01C0FFF0; + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_lhalf_rp.s b/tests/tcg/bfin/c_dsp32shiftim_lhalf_rp.s new file mode 100644 index 0000000000000..a26a3ebc766c2 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_lhalf_rp.s @@ -0,0 +1,421 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_rp/c_dsp32shiftim_lhalf_rp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x90000001; +imm32 r2, 0x90000002; +imm32 r3, 0x90000003; +imm32 r4, 0x90000004; +imm32 r5, 0x90000005; +imm32 r6, 0x90000006; +imm32 r7, 0x90000007; +R0.L = R0.L << 0; +R1.L = R1.L >> 1; +R2.L = R2.L >> 2; +R3.L = R3.L >> 3; +R4.L = R4.L >> 4; +R5.L = R5.L >> 5; +R6.L = R6.L >> 6; +R7.L = R7.L >> 7; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x90000000; +CHECKREG r2, 0x90000000; +CHECKREG r3, 0x90000000; +CHECKREG r4, 0x90000000; +CHECKREG r5, 0x90000000; +CHECKREG r6, 0x90000000; +CHECKREG r7, 0x90000000; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0xa0002002; +imm32 r3, 0xa0003003; +imm32 r4, 0xa0004004; +imm32 r5, 0xa0005005; +imm32 r6, 0xa0006006; +imm32 r7, 0xa0007007; +R0.L = R0.L >> 1; +R1.L = R1.L >> 1; +R2.L = R2.L >> 1; +R3.L = R3.L >> 1; +R4.L = R4.L >> 1; +R5.L = R5.L >> 1; +R6.L = R6.L >> 1; +R7.L = R7.L >> 1; +CHECKREG r0, 0x00000800; +CHECKREG r1, 0x90007FFF; +CHECKREG r2, 0xA0001001; +CHECKREG r3, 0xA0001801; +CHECKREG r4, 0xA0002002; +CHECKREG r5, 0xA0002802; +CHECKREG r6, 0xA0003003; +CHECKREG r7, 0xA0003803; + + +imm32 r0, 0xb0001001; +imm32 r1, 0xb0001001; +R2.L = -15; +imm32 r3, 0xb0003003; +imm32 r4, 0xb0004004; +imm32 r5, 0xb0005005; +imm32 r6, 0xb0006006; +imm32 r7, 0xb0007007; +R0.L = R0.L >> 15; +R1.L = R1.L >> 15; +R2.L = LSHIFT R2.L BY R2.L; +R3.L = R3.L >> 15; +R4.L = R4.L >> 15; +R5.L = R5.L >> 15; +R6.L = R6.L >> 15; +R7.L = R7.L >> 15; +CHECKREG r0, 0xb0000000; +CHECKREG r1, 0xb0000000; +CHECKREG r2, 0xA0000001; +CHECKREG r3, 0xB0000000; +CHECKREG r4, 0xb0000000; +CHECKREG r5, 0xb0000000; +CHECKREG r6, 0xb0000000; +CHECKREG r7, 0xB0000000; + +imm32 r0, 0xc0001001; +imm32 r1, 0xc0001001; +imm32 r2, 0xc0002002; +R3.L = -16; +imm32 r4, 0xc0004004; +imm32 r5, 0xc0005005; +imm32 r6, 0xc0006006; +imm32 r7, 0xc0007007; +R0.L = R0.L >> 13; +R1.L = R1.L >> 13; +R2.L = R2.L >> 13; +R3.L = R3.L >> 13; +R4.L = R4.L >> 13; +R5.L = R5.L >> 13; +R6.L = R6.L >> 13; +R7.L = R7.L >> 13; +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xC0000001; +CHECKREG r3, 0xB0000007; +CHECKREG r4, 0xC0000002; +CHECKREG r5, 0xC0000002; +CHECKREG r6, 0xC0000003; +CHECKREG r7, 0xC0000003; + +// RHx by RLx +imm32 r0, 0x0000c000; +imm32 r1, 0x0001c000; +imm32 r2, 0x0002c000; +imm32 r3, 0x0003c000; +imm32 r4, 0x0004c000; +imm32 r5, 0x0005c000; +imm32 r6, 0x0006c000; +imm32 r7, 0x0007c000; +R0.L = R0.H << 0; +R1.L = R1.H << 0; +R2.L = R2.H << 0; +R3.L = R3.H << 0; +R4.L = R4.H << 0; +R5.L = R5.H << 0; +R6.L = R6.H << 0; +R7.L = R7.H << 0; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = R0.H >> 1; +R1.L = R1.H >> 1; +R2.L = R2.H >> 1; +R3.L = R3.H >> 1; +R4.L = R4.H >> 1; +R5.L = R5.H >> 1; +R6.L = R6.H >> 1; +R7.L = R7.H >> 1; +CHECKREG r0, 0x10010800; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x1001e000; +imm32 r1, 0x1001e000; +R2.L = -15; +imm32 r3, 0x3003e000; +imm32 r4, 0x4004e000; +imm32 r5, 0x5005e000; +imm32 r6, 0x6006e000; +imm32 r7, 0x7007e000; +R0.L = R0.H >> 15; +R1.L = R1.H >> 15; +R2.L = R2.H >> 15; +R3.L = R3.H >> 15; +R4.L = R4.H >> 15; +R5.L = R5.H >> 15; +R6.L = R6.H >> 15; +R7.L = R7.H >> 15; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x1001f001; +imm32 r1, 0x1001f001; +imm32 r2, 0x2002f002; +R3.L = -16; +imm32 r4, 0x4004f004; +imm32 r5, 0x5005f005; +imm32 r6, 0x6006f006; +imm32 r7, 0x7007f007; +R0.L = R0.H >> 13; +R1.L = R1.H >> 13; +R2.L = R2.H >> 13; +R3.L = R3.H >> 13; +R4.L = R4.H >> 13; +R5.L = R5.H >> 13; +R6.L = R6.H >> 13; +R7.L = R7.H >> 13; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020001; +CHECKREG r3, 0x30030001; +CHECKREG r4, 0x40040002; +CHECKREG r5, 0x50050002; +CHECKREG r6, 0x60060003; +CHECKREG r7, 0x70070003; + +// RLx by RLx +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00001002; +imm32 r3, 0x00001003; +imm32 r4, 0x00001000; +imm32 r5, 0x00001005; +imm32 r6, 0x00001006; +imm32 r7, 0x00001007; +R0.H = R0.L >> 14; +R1.H = R1.L >> 14; +R2.H = R2.L >> 14; +R3.H = R3.L >> 14; +R4.H = R4.L >> 14; +R5.H = R5.L >> 14; +R6.H = R6.L >> 14; +R7.H = R7.L >> 14; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00001001; +CHECKREG r2, 0x00001002; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00001005; +CHECKREG r6, 0x00001006; +CHECKREG r7, 0x00001007; + +imm32 r0, 0x00002001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00002003; +imm32 r4, 0x00002004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = R0.L >> 5; +R1.H = R1.L >> 5; +R2.H = R2.L >> 5; +R3.H = R3.L >> 5; +R4.H = R4.L >> 5; +R5.H = R5.L >> 5; +R6.H = R6.L >> 5; +R7.H = R7.L >> 5; +CHECKREG r0, 0x01002001; +CHECKREG r1, 0x01002001; +CHECKREG r2, 0x01002002; +CHECKREG r3, 0x01002003; +CHECKREG r4, 0x01002004; +CHECKREG r5, 0x07FFFFFF; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + + +imm32 r0, 0x30001001; +imm32 r1, 0x30001001; +imm32 r1, 0x30002002; +imm32 r3, 0x30003003; +imm32 r4, 0x30004004; +imm32 r5, 0x30005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = R0.L >> 15; +R1.H = R1.L >> 15; +R2.H = R2.L >> 15; +R3.H = R3.L >> 15; +R4.H = R4.L >> 15; +R5.H = R5.L >> 15; +R6.H = R6.L >> 15; +R7.H = R7.L >> 15; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x0001FFF1; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x40001001; +imm32 r1, 0x40002001; +imm32 r2, 0x40002002; +imm32 r3, 0x40003003; +imm32 r4, 0x40004004; +imm32 r5, 0x40005005; +imm32 r6, 0x40006006; +R7.L = -16; +R0.H = R0.L >> 7; +R1.H = R1.L >> 7; +R2.H = R2.L >> 7; +R3.H = R3.L >> 7; +R4.H = R4.L >> 7; +R5.H = R5.L >> 7; +R6.H = R6.L >> 7; +R7.H = R7.L >> 7; +CHECKREG r0, 0x00201001; +CHECKREG r1, 0x00402001; +CHECKREG r2, 0x00402002; +CHECKREG r3, 0x00603003; +CHECKREG r4, 0x00804004; +CHECKREG r5, 0x00A05005; +CHECKREG r6, 0x00C06006; +CHECKREG r7, 0x01FFFFF0; + +// RHx by RLx +imm32 r0, 0x50010000; +imm32 r1, 0x50010000; +imm32 r2, 0x50020000; +imm32 r3, 0x50030000; +R4.L = -1; +imm32 r5, 0x50050000; +imm32 r6, 0x50060000; +imm32 r7, 0x50070000; +R0.H = R0.H >> 1; +R1.H = R1.H >> 1; +R2.H = R2.H >> 1; +R3.H = R3.H >> 1; +R4.H = R4.H >> 1; +R5.H = R5.H >> 1; +R6.H = R6.H >> 1; +R7.H = R7.H >> 1; +CHECKREG r0, 0x28000000; +CHECKREG r1, 0x28000000; +CHECKREG r2, 0x28010000; +CHECKREG r3, 0x28010000; +CHECKREG r4, 0x0040FFFF; +CHECKREG r5, 0x28020000; +CHECKREG r6, 0x28030000; +CHECKREG r7, 0x28030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = R0.H >> 5; +R1.H = R1.H >> 5; +R2.H = R2.H >> 5; +R3.H = R3.H >> 5; +R4.H = R4.H >> 5; +R5.H = R5.H >> 5; +R6.H = R6.H >> 5; +R7.H = R7.H >> 5; +CHECKREG r0, 0x00800000; +CHECKREG r1, 0x00800000; +CHECKREG r2, 0x01000000; +CHECKREG r3, 0x01800000; +CHECKREG r4, 0x02000000; +CHECKREG r5, 0x0140FFFF; +CHECKREG r6, 0x03000000; +CHECKREG r7, 0x03800000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = R0.H >> 6; +R1.L = R1.H >> 6; +R2.L = R2.H >> 6; +R3.L = R3.H >> 6; +R4.L = R4.H >> 6; +R5.L = R5.H >> 6; +R6.L = R6.H >> 6; +R7.L = R7.H >> 6; +CHECKREG r0, 0x10010040; +CHECKREG r1, 0x10010040; +CHECKREG r2, 0x20020080; +CHECKREG r3, 0x300300C0; +CHECKREG r4, 0x40040100; +CHECKREG r5, 0x50050140; +CHECKREG r6, 0x0300000C; +CHECKREG r7, 0x700701C0; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = R0.H >> 15; +R1.H = R1.H >> 15; +R2.H = R2.H >> 15; +R3.H = R3.H >> 15; +R4.H = R4.H >> 15; +R5.H = R5.H >> 15; +R6.H = R6.H >> 15; +R7.H = R7.H >> 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x000000C0; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x0000FFF0; + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_lhh.s b/tests/tcg/bfin/c_dsp32shiftim_lhh.s new file mode 100644 index 0000000000000..e129dcad5bf5f --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_lhh.s @@ -0,0 +1,65 @@ +//Original:/testcases/core/c_dsp32shiftim_lhh/c_dsp32shiftim_lhh.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm lshift: lshift / lshift + + + +imm32 r0, 0x01230abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0 = R0 << 0 (V); +R1 = R1 << 3 (V); +R2 = R2 << 5 (V); +R3 = R3 << 8 (V); +R4 = R4 << 9 (V); +R5 = R5 << 15 (V); +R6 = R6 << 7 (V); +R7 = R7 << 13 (V); +CHECKREG r0, 0x01230ABC; +CHECKREG r1, 0x91A0B3C0; +CHECKREG r2, 0x68A0F120; +CHECKREG r3, 0x56009A00; +CHECKREG r4, 0xCE005600; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xC480E680; +CHECKREG r7, 0x4000C000; + +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7 = R0 >> 11 (V); +R0 = R1 >> 8 (V); +R1 = R2 >> 14 (V); +R2 = R3 >> 15 (V); +R3 = R4 >> 10 (V); +R4 = R5 >> 2 (V); +R5 = R6 >> 9 (V); +R6 = R7 >> 6 (V); +CHECKREG r0, 0x00120056; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00110022; +CHECKREG r4, 0x159E26AF; +CHECKREG r5, 0x00330055; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + + + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_lmix.s b/tests/tcg/bfin/c_dsp32shiftim_lmix.s new file mode 100644 index 0000000000000..82845fff7da04 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_lmix.s @@ -0,0 +1,138 @@ +//Original:/testcases/core/c_dsp32shiftim_lmix/c_dsp32shiftim_lmix.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm lshift: mix + + + + +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + + +// Lshift (Logical ) +// Lshift : positive data, count (+)=left (half reg) +imm32 r0, 0x00010001; +imm32 r1, 1; +imm32 r2, 0x00020002; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1; /* r4 = 0x00020002 */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r5 = 0x00080008 */ +R6 = R0 << 1 (V); /* r6 = 0x00020002 */ +R7 = R2 << 2 (V); /* r7 = 0x00080008 */ +CHECKREG r4, 0x00020002; +CHECKREG r5, 0x00080008; +CHECKREG r6, 0x00020002; +CHECKREG r7, 0x00080008; + +// Lshift : (full reg) +imm32 r1, 3; +imm32 r3, 4; +R6 = R0 << 3; /* r6 = 0x00080010 */ +R7 = R2 << 4; +CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ +CHECKREG r7, 0x00200020; + +A0 = 0; +A0.L = R0.L; +A0.H = R0.H; +A0 = A0 << 3; /* a0 = 0x00080008 */ +R5 = A0.w; /* r5 = 0x00080008 */ +CHECKREG r5, 0x00080008; + +imm32 r4, 0x30000003; +imm32 r1, 1; +R5 = R4 << 1; /* r5 = 0x60000006 */ +imm32 r1, 2; +R6 = R4 << 2; /* r6 = 0xc000000c like LSHIFT */ +CHECKREG r5, 0x60000006; +CHECKREG r6, 0xc000000c; + + +// lshift : count (-)=right (half reg) +imm32 r0, 0x10001000; +imm32 r1, -1; +imm32 r2, 0x10001000; +imm32 r3, -2; +R4.H = R0.H >> 1; +R4.L = R0.L >> 1; /* r4 = 0x08000800 */ +R5.H = R2.H >> 2; +R5.L = R2.L >> 2; /* r4 = 0x04000400 */ +R6 = R0 >> 1 (V); /* r4 = 0x08000800 */ +R7 = R2 >> 2 (V); /* r4 = 0x04000400 */ +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x04000400; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x04000400; + +// lshift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >> 3; /* r6 = 0x02000200 */ +R7 = R2 >> 4; /* r7 = 0x01000100 */ +CHECKREG r6, 0x02000200; +CHECKREG r7, 0x01000100; + +// NEGATIVE +// lshift : NEGATIVE data, count (+)=left (half reg) +imm32 r0, 0xc00f800f; +imm32 r1, 1; +imm32 r2, 0xe00fe00f; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1; /* r4 = 0x801e001e */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r4 = 0x803c803c */ +CHECKREG r4, 0x801e001e; +CHECKREG r5, 0x803c803c; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +imm32 r1, 4; +imm32 r3, 5; +R6 = R0 << 4; /* r6 = 0x80fe00f0 */ +R7 = R2 << 5; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xf80fe00f; +imm32 r2, 0xfc0fe00f; +R6 = R0 << 4; /* r6 = 0x80fe00f0 */ +R7 = R2 << 5; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + + + +// lshift : NEGATIVE data, count (-)=right (half reg) Working ok +imm32 r0, 0x80f080f0; +imm32 r1, -1; +imm32 r2, 0x80f080f0; +imm32 r3, -2; +R4.H = R0.H >> 1; +R4.L = R0.L >> 1; /* r4 = 0x40784078 */ +R5.H = R2.H >> 2; +R5.L = R2.L >> 2; /* r4 = 0x203c203c */ +CHECKREG r4, 0x40784078; +CHECKREG r5, 0x203c203c; +R6 = R0 >> 1 (V); /* r6 = 0x40784078 */ +R7 = R2 >> 2 (V); /* r7 = 0x203c203c */ +CHECKREG r6, 0x40784078; +CHECKREG r7, 0x203c203c; + +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >> 3; /* r6 = 0x101e101e */ +R7 = R2 >> 4; /* r7 = 0x080f080f */ +CHECKREG r6, 0x101e101e; +CHECKREG r7, 0x080f080f; + +pass diff --git a/tests/tcg/bfin/c_dsp32shiftim_rot.s b/tests/tcg/bfin/c_dsp32shiftim_rot.s new file mode 100644 index 0000000000000..0b47eda1a2ca2 --- /dev/null +++ b/tests/tcg/bfin/c_dsp32shiftim_rot.s @@ -0,0 +1,62 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_rot/c_dsp32shiftim_rot.dsp +// Spec Reference: dsp32shiftimm rot: +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0xa1230001; + imm32 r1, 0x1b345678; + imm32 r2, 0x23c56789; + imm32 r3, 0x34d6789a; + imm32 r4, 0x85a789ab; + imm32 r5, 0x967c9abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb8912cde; + R0 = ROT R0 BY 1; + R1 = ROT R1 BY 5; + R2 = ROT R2 BY 9; + R3 = ROT R3 BY 8; + R4 = ROT R4 BY 24; + R5 = ROT R5 BY 31; + R6 = ROT R6 BY 14; + R7 = ROT R7 BY 25; + CHECKREG r0, 0x42460002; + CHECKREG r1, 0x668ACF11; + CHECKREG r2, 0x8ACF1323; + CHECKREG r3, 0xD6789A9A; + CHECKREG r4, 0xAB42D3C4; + CHECKREG r5, 0x659F26AF; + CHECKREG r6, 0x6AF354F1; + CHECKREG r7, 0xBCB8912C; + + imm32 r0, 0xa1230001; + imm32 r1, 0x1b345678; + imm32 r2, 0x23c56789; + imm32 r3, 0x34d6789a; + imm32 r4, 0x85a789ab; + imm32 r5, 0x967c9abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb8912cde; + R6 = ROT R0 BY -3; + R7 = ROT R1 BY -9; + R0 = ROT R2 BY -8; + R1 = ROT R3 BY -7; + R2 = ROT R4 BY -15; + R3 = ROT R5 BY -24; + R4 = ROT R6 BY -31; + R5 = ROT R7 BY -22; + CHECKREG r0, 0x1223C567; + CHECKREG r1, 0x6A69ACF1; + CHECKREG r2, 0x26AD0B4F; + CHECKREG r3, 0xF9357896; + CHECKREG r4, 0xD0918000; + CHECKREG r5, 0x6CD15DE0; + CHECKREG r6, 0x74246000; + CHECKREG r7, 0x780D9A2B; + + pass diff --git a/tests/tcg/bfin/c_dspldst_ld_dr_i.s b/tests/tcg/bfin/c_dspldst_ld_dr_i.s new file mode 100644 index 0000000000000..02743cc2ef32c --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_ld_dr_i.s @@ -0,0 +1,168 @@ +//Original:/testcases/core/c_dspldst_ld_dr_i/c_dspldst_ld_dr_i.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: c_dspldst ld_dr_i + + +// set all regs + + INIT_R_REGS 0; + +// initial values + loadsym I0, DATA1 + loadsym I1, DATA2 + loadsym I2, DATA3 + loadsym I3, DATA4 + + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x00010203; + CHECKREG r5, 0x20212223; + CHECKREG r6, 0x40414243; + CHECKREG r7, 0x60616263; + R1 = [ I0 ]; + R2 = [ I1 ]; + R3 = [ I2 ]; + R4 = [ I3 ]; + R5 = [ I0 ]; + R6 = [ I1 ]; + R7 = [ I2 ]; + R0 = [ I3 ]; + CHECKREG r0, 0x60616263; + CHECKREG r1, 0x00010203; + CHECKREG r2, 0x20212223; + CHECKREG r3, 0x40414243; + CHECKREG r4, 0x60616263; + CHECKREG r5, 0x00010203; + CHECKREG r6, 0x20212223; + CHECKREG r7, 0x40414243; + R2 = [ I0 ]; + R3 = [ I1 ]; + R4 = [ I2 ]; + R5 = [ I3 ]; + R6 = [ I0 ]; + R7 = [ I1 ]; + R0 = [ I2 ]; + R1 = [ I3 ]; + CHECKREG r0, 0x40414243; + CHECKREG r1, 0x60616263; + CHECKREG r2, 0x00010203; + CHECKREG r3, 0x20212223; + CHECKREG r4, 0x40414243; + CHECKREG r5, 0x60616263; + CHECKREG r6, 0x00010203; + CHECKREG r7, 0x20212223; + + R3 = [ I0 ]; + R4 = [ I1 ]; + R5 = [ I2 ]; + R6 = [ I3 ]; + R7 = [ I0 ]; + R0 = [ I1 ]; + R1 = [ I2 ]; + R2 = [ I3 ]; + CHECKREG r0, 0x20212223; + CHECKREG r1, 0x40414243; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x00010203; + CHECKREG r4, 0x20212223; + CHECKREG r5, 0x40414243; + CHECKREG r6, 0x60616263; + CHECKREG r7, 0x00010203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_ld_dr_ipp.s b/tests/tcg/bfin/c_dspldst_ld_dr_ipp.s new file mode 100644 index 0000000000000..d94dfc29e808c --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_ld_dr_ipp.s @@ -0,0 +1,348 @@ +//Original:/testcases/core/c_dspldst_ld_dr_ipp/c_dspldst_ld_dr_ipp.dsp +// Spec Reference: c_dspldst ld_dr_i++/-- +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x44454647; + CHECKREG r7, 0x64656667; + R1 = [ I0 ++ ]; + R2 = [ I1 ++ ]; + R3 = [ I2 ++ ]; + R4 = [ I3 ++ ]; + R5 = [ I0 ++ ]; + R6 = [ I1 ++ ]; + R7 = [ I2 ++ ]; + R0 = [ I3 ++ ]; + CHECKREG r0, 0x6C6D6E6F; + CHECKREG r1, 0x08090A0B; + CHECKREG r2, 0x28292A2B; + CHECKREG r3, 0x48494A4B; + CHECKREG r4, 0x68696A6B; + CHECKREG r5, 0x0C0D0E0F; + CHECKREG r6, 0x2C2D2E2F; + CHECKREG r7, 0x4C4D4E4F; + R2 = [ I0 ++ ]; + R3 = [ I1 ++ ]; + R4 = [ I2 ++ ]; + R5 = [ I3 ++ ]; + R6 = [ I0 ++ ]; + R7 = [ I1 ++ ]; + R0 = [ I2 ++ ]; + R1 = [ I3 ++ ]; + CHECKREG r0, 0x54555657; + CHECKREG r1, 0x74757677; + CHECKREG r2, 0x10111213; + CHECKREG r3, 0x30313233; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x70717273; + CHECKREG r6, 0x14151617; + CHECKREG r7, 0x34353637; + + R3 = [ I0 ++ ]; + R4 = [ I1 ++ ]; + R5 = [ I2 ++ ]; + R6 = [ I3 ++ ]; + R7 = [ I0 ++ ]; + R0 = [ I1 ++ ]; + R1 = [ I2 ++ ]; + R2 = [ I3 ++ ]; + CHECKREG r0, 0x3C3D3E3F; + CHECKREG r1, 0xC5C6C7C8; + CHECKREG r2, 0x7C7D7E7F; + CHECKREG r3, 0x18191A1B; + CHECKREG r4, 0x38393A3B; + CHECKREG r5, 0x58595A5B; + CHECKREG r6, 0x78797A7B; + CHECKREG r7, 0x1C1D1E1F; + +// reverse to minus mninus i-- + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x11223344; + CHECKREG r1, 0x91929394; + CHECKREG r2, 0xC9CACBCD; + CHECKREG r3, 0xEBECEDEE; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r5, 0x3C3D3E3F; + CHECKREG r6, 0xC5C6C7C8; + CHECKREG r7, 0x7C7D7E7F; + R1 = [ I0 -- ]; + R2 = [ I1 -- ]; + R3 = [ I2 -- ]; + R4 = [ I3 -- ]; + R5 = [ I0 -- ]; + R6 = [ I1 -- ]; + R7 = [ I2 -- ]; + R0 = [ I3 -- ]; + CHECKREG r0, 0x74757677; + CHECKREG r1, 0x18191A1B; + CHECKREG r2, 0x38393A3B; + CHECKREG r3, 0x58595A5B; + CHECKREG r4, 0x78797A7B; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x34353637; + CHECKREG r7, 0x54555657; + R2 = [ I0 -- ]; + R3 = [ I1 -- ]; + R4 = [ I2 -- ]; + R5 = [ I3 -- ]; + R6 = [ I0 -- ]; + R7 = [ I1 -- ]; + R0 = [ I2 -- ]; + R1 = [ I3 -- ]; + CHECKREG r0, 0x4C4D4E4F; + CHECKREG r1, 0x6C6D6E6F; + CHECKREG r2, 0x10111213; + CHECKREG r3, 0x30313233; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x70717273; + CHECKREG r6, 0x0C0D0E0F; + CHECKREG r7, 0x2C2D2E2F; + + R3 = [ I0 -- ]; + R4 = [ I1 -- ]; + R5 = [ I2 -- ]; + R6 = [ I3 -- ]; + R7 = [ I0 -- ]; + R0 = [ I1 -- ]; + R1 = [ I2 -- ]; + R2 = [ I3 -- ]; + CHECKREG r0, 0x24252627; + CHECKREG r1, 0x44454647; + CHECKREG r2, 0x64656667; + CHECKREG r3, 0x08090A0B; + CHECKREG r4, 0x28292A2B; + CHECKREG r5, 0x48494A4B; + CHECKREG r6, 0x68696A6B; + CHECKREG r7, 0x04050607; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_ld_dr_ippm.s b/tests/tcg/bfin/c_dspldst_ld_dr_ippm.s new file mode 100644 index 0000000000000..abdc823222e22 --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_ld_dr_ippm.s @@ -0,0 +1,328 @@ +//Original:/testcases/core/c_dspldst_ld_dr_ippm/c_dspldst_ld_dr_ippm.dsp +// Spec Reference: c_dspldst ld_dr_i++m +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + M0 = 0 (X); + M1 = 0x4 (X); + M2 = 0x0 (X); + M3 = 0x4 (X); + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + R0 = [ I0 ++ M0 ]; + R1 = [ I1 ++ M1 ]; + R2 = [ I2 ++ M2 ]; + R3 = [ I3 ++ M3 ]; + R4 = [ I0 ++ M1 ]; + R5 = [ I1 ++ M2 ]; + R6 = [ I2 ++ M3 ]; + R7 = [ I3 ++ M0 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x00010203; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x40414243; + CHECKREG r7, 0x64656667; + R1 = [ I0 ++ M2 ]; + R2 = [ I1 ++ M3 ]; + R3 = [ I2 ++ M0 ]; + R4 = [ I3 ++ M1 ]; + R5 = [ I0 ++ M3 ]; + R6 = [ I1 ++ M0 ]; + R7 = [ I2 ++ M1 ]; + R0 = [ I3 ++ M2 ]; + CHECKREG r0, 0x68696A6B; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x24252627; + CHECKREG r3, 0x44454647; + CHECKREG r4, 0x64656667; + CHECKREG r5, 0x04050607; + CHECKREG r6, 0x28292A2B; + CHECKREG r7, 0x44454647; + + M0 = 4 (X); + M1 = 0x0 (X); + M2 = 0x4 (X); + M3 = 0x0 (X); + R2 = [ I0 ++ M0 ]; + R3 = [ I1 ++ M1 ]; + R4 = [ I2 ++ M2 ]; + R5 = [ I3 ++ M3 ]; + R6 = [ I0 ++ M1 ]; + R7 = [ I1 ++ M2 ]; + R0 = [ I2 ++ M3 ]; + R1 = [ I3 ++ M0 ]; + CHECKREG r0, 0x4C4D4E4F; + CHECKREG r1, 0x68696A6B; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x28292A2B; + CHECKREG r4, 0x48494A4B; + CHECKREG r5, 0x68696A6B; + CHECKREG r6, 0x0C0D0E0F; + CHECKREG r7, 0x28292A2B; + + R3 = [ I0 ++ M2 ]; + R4 = [ I1 ++ M3 ]; + R5 = [ I2 ++ M0 ]; + R6 = [ I3 ++ M1 ]; + R7 = [ I0 ++ M3 ]; + R0 = [ I1 ++ M0 ]; + R1 = [ I2 ++ M1 ]; + R2 = [ I3 ++ M2 ]; + CHECKREG r0, 0x2C2D2E2F; + CHECKREG r1, 0x50515253; + CHECKREG r2, 0x6C6D6E6F; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x2C2D2E2F; + CHECKREG r5, 0x4C4D4E4F; + CHECKREG r6, 0x6C6D6E6F; + CHECKREG r7, 0x10111213; + + R5 = [ I0 ++ M2 ]; + R6 = [ I1 ++ M3 ]; + R7 = [ I2 ++ M0 ]; + R0 = [ I3 ++ M1 ]; + R1 = [ I0 ++ M3 ]; + R2 = [ I1 ++ M0 ]; + R3 = [ I2 ++ M1 ]; + R4 = [ I3 ++ M2 ]; + CHECKREG r0, 0x70717273; + CHECKREG r1, 0x14151617; + CHECKREG r2, 0x30313233; + CHECKREG r3, 0x54555657; + CHECKREG r4, 0x70717273; + CHECKREG r5, 0x10111213; + CHECKREG r6, 0x30313233; + CHECKREG r7, 0x50515253; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_ld_drhi_i.s b/tests/tcg/bfin/c_dspldst_ld_drhi_i.s new file mode 100644 index 0000000000000..3ada17568f0b2 --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_ld_drhi_i.s @@ -0,0 +1,168 @@ +//Original:/testcases/core/c_dspldst_ld_drhi_i/c_dspldst_ld_drhi_i.dsp +// Spec Reference: c_dspldst ld_drhi_i +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + +// Load upper half of Dregs + R0.H = W [ I0 ]; + R1.H = W [ I1 ]; + R2.H = W [ I2 ]; + R3.H = W [ I3 ]; + R4.H = W [ I0 ]; + R5.H = W [ I1 ]; + R6.H = W [ I2 ]; + R7.H = W [ I3 ]; + CHECKREG r0, 0x02030000; + CHECKREG r1, 0x22230000; + CHECKREG r2, 0x42430000; + CHECKREG r3, 0x62630000; + CHECKREG r4, 0x02030000; + CHECKREG r5, 0x22230000; + CHECKREG r6, 0x42430000; + CHECKREG r7, 0x62630000; + + R1.H = W [ I0 ]; + R2.H = W [ I1 ]; + R3.H = W [ I2 ]; + R4.H = W [ I3 ]; + R5.H = W [ I0 ]; + R6.H = W [ I1 ]; + R7.H = W [ I2 ]; + R0.H = W [ I3 ]; + CHECKREG r0, 0x62630000; + CHECKREG r1, 0x02030000; + CHECKREG r2, 0x22230000; + CHECKREG r3, 0x42430000; + CHECKREG r4, 0x62630000; + CHECKREG r5, 0x02030000; + CHECKREG r6, 0x22230000; + CHECKREG r7, 0x42430000; + + R2.H = W [ I0 ]; + R3.H = W [ I1 ]; + R4.H = W [ I2 ]; + R5.H = W [ I3 ]; + R6.H = W [ I0 ]; + R7.H = W [ I1 ]; + R0.H = W [ I2 ]; + R1.H = W [ I3 ]; + CHECKREG r0, 0x42430000; + CHECKREG r1, 0x62630000; + CHECKREG r2, 0x02030000; + CHECKREG r3, 0x22230000; + CHECKREG r4, 0x42430000; + CHECKREG r5, 0x62630000; + CHECKREG r6, 0x02030000; + CHECKREG r7, 0x22230000; + + R3.H = W [ I0 ]; + R4.H = W [ I1 ]; + R5.H = W [ I2 ]; + R6.H = W [ I3 ]; + R7.H = W [ I0 ]; + R0.H = W [ I1 ]; + R1.H = W [ I2 ]; + R2.H = W [ I3 ]; + + CHECKREG r0, 0x22230000; + CHECKREG r1, 0x42430000; + CHECKREG r2, 0x62630000; + CHECKREG r3, 0x02030000; + CHECKREG r4, 0x22230000; + CHECKREG r5, 0x42430000; + CHECKREG r6, 0x62630000; + CHECKREG r7, 0x02030000; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_ld_drhi_ipp.s b/tests/tcg/bfin/c_dspldst_ld_drhi_ipp.s new file mode 100644 index 0000000000000..e4531af597c7d --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_ld_drhi_ipp.s @@ -0,0 +1,364 @@ +//Original:/testcases/core/c_dspldst_ld_drhi_ipp/c_dspldst_ld_drhi_ipp.dsp +// Spec Reference: c_dspldst ld_drhi_i++/-- +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + + INIT_R_REGS 0; + +// initial values +//i0=0x3000; +//i1=0x4000; +//i2=0x5000; +//i3=0x6000; + loadsym I0, DATA_ADDR_3; + loadsym I1, DATA_ADDR_4; + loadsym I2, DATA_ADDR_5; + loadsym I3, DATA_ADDR_6; + +// Load Upper half of Dregs + R0.H = W [ I0 ++ ]; + R1.H = W [ I1 ++ ]; + R2.H = W [ I2 ++ ]; + R3.H = W [ I3 ++ ]; + R4.H = W [ I0 ++ ]; + R5.H = W [ I1 ++ ]; + R6.H = W [ I2 ++ ]; + R7.H = W [ I3 ++ ]; + CHECKREG r0, 0x02030000; + CHECKREG r1, 0x22230000; + CHECKREG r2, 0x42430000; + CHECKREG r3, 0x62630000; + CHECKREG r4, 0x00010000; + CHECKREG r5, 0x20210000; + CHECKREG r6, 0x40410000; + CHECKREG r7, 0x60610000; + + R1.H = W [ I0 ++ ]; + R2.H = W [ I1 ++ ]; + R3.H = W [ I2 ++ ]; + R4.H = W [ I3 ++ ]; + R5.H = W [ I0 ++ ]; + R6.H = W [ I1 ++ ]; + R7.H = W [ I2 ++ ]; + R0.H = W [ I3 ++ ]; + CHECKREG r0, 0x64650000; + CHECKREG r1, 0x06070000; + CHECKREG r2, 0x26270000; + CHECKREG r3, 0x46470000; + CHECKREG r4, 0x66670000; + CHECKREG r5, 0x04050000; + CHECKREG r6, 0x24250000; + CHECKREG r7, 0x44450000; + + R2.H = W [ I0 ++ ]; + R3.H = W [ I1 ++ ]; + R4.H = W [ I2 ++ ]; + R5.H = W [ I3 ++ ]; + R6.H = W [ I0 ++ ]; + R7.H = W [ I1 ++ ]; + R0.H = W [ I2 ++ ]; + R1.H = W [ I3 ++ ]; + CHECKREG r0, 0x48490000; + CHECKREG r1, 0x68690000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x2A2B0000; + CHECKREG r4, 0x4A4B0000; + CHECKREG r5, 0x6A6B0000; + CHECKREG r6, 0x08090000; + CHECKREG r7, 0x28290000; + + R3.H = W [ I0 ++ ]; + R4.H = W [ I1 ++ ]; + R5.H = W [ I2 ++ ]; + R6.H = W [ I3 ++ ]; + R7.H = W [ I0 ++ ]; + R0.H = W [ I1 ++ ]; + R1.H = W [ I2 ++ ]; + R2.H = W [ I3 ++ ]; + + CHECKREG r0, 0x2C2D0000; + CHECKREG r1, 0x4C4D0000; + CHECKREG r2, 0x6C6D0000; + CHECKREG r3, 0x0E0F0000; + CHECKREG r4, 0x2E2F0000; + CHECKREG r5, 0x4E4F0000; + CHECKREG r6, 0x6E6F0000; + CHECKREG r7, 0x0C0D0000; + +// reverse to minus mninus i-- +// Load Upper half of Dregs + R0.H = W [ I0 -- ]; + R1.H = W [ I1 -- ]; + R2.H = W [ I2 -- ]; + R3.H = W [ I3 -- ]; + R4.H = W [ I0 -- ]; + R5.H = W [ I1 -- ]; + R6.H = W [ I2 -- ]; + R7.H = W [ I3 -- ]; + CHECKREG r0, 0x12130000; + CHECKREG r1, 0x32330000; + CHECKREG r2, 0x52530000; + CHECKREG r3, 0x72730000; + CHECKREG r4, 0x0C0D0000; + CHECKREG r5, 0x2C2D0000; + CHECKREG r6, 0x4C4D0000; + CHECKREG r7, 0x6C6D0000; + + R1.H = W [ I0 -- ]; + R2.H = W [ I1 -- ]; + R3.H = W [ I2 -- ]; + R4.H = W [ I3 -- ]; + R5.H = W [ I0 -- ]; + R6.H = W [ I1 -- ]; + R7.H = W [ I2 -- ]; + R0.H = W [ I3 -- ]; + CHECKREG r0, 0x68690000; + CHECKREG r1, 0x0E0F0000; + CHECKREG r2, 0x2E2F0000; + CHECKREG r3, 0x4E4F0000; + CHECKREG r4, 0x6E6F0000; + CHECKREG r5, 0x08090000; + CHECKREG r6, 0x28290000; + CHECKREG r7, 0x48490000; + + R2.H = W [ I0 -- ]; + R3.H = W [ I1 -- ]; + R4.H = W [ I2 -- ]; + R5.H = W [ I3 -- ]; + R6.H = W [ I0 -- ]; + R7.H = W [ I1 -- ]; + R0.H = W [ I2 -- ]; + R1.H = W [ I3 -- ]; + CHECKREG r0, 0x44450000; + CHECKREG r1, 0x64650000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x2A2B0000; + CHECKREG r4, 0x4A4B0000; + CHECKREG r5, 0x6A6B0000; + CHECKREG r6, 0x04050000; + CHECKREG r7, 0x24250000; + + R3.H = W [ I0 -- ]; + R4.H = W [ I1 -- ]; + R5.H = W [ I2 -- ]; + R6.H = W [ I3 -- ]; + R7.H = W [ I0 -- ]; + R0.H = W [ I1 -- ]; + R1.H = W [ I2 -- ]; + R2.H = W [ I3 -- ]; + + CHECKREG r0, 0x20210000; + CHECKREG r1, 0x40410000; + CHECKREG r2, 0x60610000; + CHECKREG r3, 0x06070000; + CHECKREG r4, 0x26270000; + CHECKREG r5, 0x46470000; + CHECKREG r6, 0x66670000; + CHECKREG r7, 0x00010000; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_ld_drlo_i.s b/tests/tcg/bfin/c_dspldst_ld_drlo_i.s new file mode 100644 index 0000000000000..aec575ce3d1ff --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_ld_drlo_i.s @@ -0,0 +1,164 @@ +//Original:/testcases/core/c_dspldst_ld_drlo_i/c_dspldst_ld_drlo_i.dsp +// Spec Reference: c_dspldst ld_drlo_i +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + +// Load Lower half of Dregs + R0.L = W [ I0 ]; + R1.L = W [ I1 ]; + R2.L = W [ I2 ]; + R3.L = W [ I3 ]; + R4.L = W [ I0 ]; + R5.L = W [ I1 ]; + R6.L = W [ I2 ]; + R7.L = W [ I3 ]; + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00000203; + CHECKREG r5, 0x00002223; + CHECKREG r6, 0x00004243; + CHECKREG r7, 0x00006263; + + R1.L = W [ I0 ]; + R2.L = W [ I1 ]; + R3.L = W [ I2 ]; + R4.L = W [ I3 ]; + R5.L = W [ I0 ]; + R6.L = W [ I1 ]; + R7.L = W [ I2 ]; + R0.L = W [ I3 ]; + CHECKREG r0, 0x00006263; + CHECKREG r1, 0x00000203; + CHECKREG r2, 0x00002223; + CHECKREG r3, 0x00004243; + CHECKREG r4, 0x00006263; + CHECKREG r5, 0x00000203; + CHECKREG r6, 0x00002223; + CHECKREG r7, 0x00004243; + + R2.L = W [ I0 ]; + R3.L = W [ I1 ]; + R4.L = W [ I2 ]; + R5.L = W [ I3 ]; + R6.L = W [ I0 ]; + R7.L = W [ I1 ]; + R0.L = W [ I2 ]; + R1.L = W [ I3 ]; + CHECKREG r0, 0x00004243; + CHECKREG r1, 0x00006263; + CHECKREG r2, 0x00000203; + CHECKREG r3, 0x00002223; + CHECKREG r4, 0x00004243; + CHECKREG r5, 0x00006263; + CHECKREG r6, 0x00000203; + CHECKREG r7, 0x00002223; + + R3.L = W [ I0 ]; + R4.L = W [ I1 ]; + R5.L = W [ I2 ]; + R6.L = W [ I3 ]; + R7.L = W [ I0 ]; + R0.L = W [ I1 ]; + R1.L = W [ I2 ]; + R2.L = W [ I3 ]; + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0x00000203; + CHECKREG r4, 0x00002223; + CHECKREG r5, 0x00004243; + CHECKREG r6, 0x00006263; + CHECKREG r7, 0x00000203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_ld_drlo_ipp.s b/tests/tcg/bfin/c_dspldst_ld_drlo_ipp.s new file mode 100644 index 0000000000000..d47b6b803d43b --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_ld_drlo_ipp.s @@ -0,0 +1,355 @@ +//Original:/testcases/core/c_dspldst_ld_drlo_ipp/c_dspldst_ld_drlo_ipp.dsp +// Spec Reference: c_dspldst ld_drlo_i++/-- +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + +// Load Lower half of Dregs + R0.L = W [ I0 ++ ]; + R1.L = W [ I1 ++ ]; + R2.L = W [ I2 ++ ]; + R3.L = W [ I3 ++ ]; + R4.L = W [ I0 ++ ]; + R5.L = W [ I1 ++ ]; + R6.L = W [ I2 ++ ]; + R7.L = W [ I3 ++ ]; + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0x00002021; + CHECKREG r6, 0x00004041; + CHECKREG r7, 0x00006061; + + R1.L = W [ I0 ++ ]; + R2.L = W [ I1 ++ ]; + R3.L = W [ I2 ++ ]; + R4.L = W [ I3 ++ ]; + R5.L = W [ I0 ++ ]; + R6.L = W [ I1 ++ ]; + R7.L = W [ I2 ++ ]; + R0.L = W [ I3 ++ ]; + CHECKREG r0, 0x00006465; + CHECKREG r1, 0x00000607; + CHECKREG r2, 0x00002627; + CHECKREG r3, 0x00004647; + CHECKREG r4, 0x00006667; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00004445; + + R2.L = W [ I0 ++ ]; + R3.L = W [ I1 ++ ]; + R4.L = W [ I2 ++ ]; + R5.L = W [ I3 ++ ]; + R6.L = W [ I0 ++ ]; + R7.L = W [ I1 ++ ]; + R0.L = W [ I2 ++ ]; + R1.L = W [ I3 ++ ]; + CHECKREG r0, 0x00004849; + CHECKREG r1, 0x00006869; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00002A2B; + CHECKREG r4, 0x00004A4B; + CHECKREG r5, 0x00006A6B; + CHECKREG r6, 0x00000809; + CHECKREG r7, 0x00002829; + + R3.L = W [ I0 ++ ]; + R4.L = W [ I1 ++ ]; + R5.L = W [ I2 ++ ]; + R6.L = W [ I3 ++ ]; + R7.L = W [ I0 ++ ]; + R0.L = W [ I1 ++ ]; + R1.L = W [ I2 ++ ]; + R2.L = W [ I3 ++ ]; + CHECKREG r0, 0x00002C2D; + CHECKREG r1, 0x00004C4D; + CHECKREG r2, 0x00006C6D; + CHECKREG r3, 0x00000E0F; + CHECKREG r4, 0x00002E2F; + CHECKREG r5, 0x00004E4F; + CHECKREG r6, 0x00006E6F; + CHECKREG r7, 0x00000C0D; + +// reverse to minus mninus i-- + +// Load Lower half of Dregs + R0.L = W [ I0 -- ]; + R1.L = W [ I1 -- ]; + R2.L = W [ I2 -- ]; + R3.L = W [ I3 -- ]; + R4.L = W [ I0 -- ]; + R5.L = W [ I1 -- ]; + R6.L = W [ I2 -- ]; + R7.L = W [ I3 -- ]; + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00003233; + CHECKREG r2, 0x00005253; + CHECKREG r3, 0x00007273; + CHECKREG r4, 0x00000C0D; + CHECKREG r5, 0x00002C2D; + CHECKREG r6, 0x00004C4D; + CHECKREG r7, 0x00006C6D; + + R1.L = W [ I0 -- ]; + R2.L = W [ I1 -- ]; + R3.L = W [ I2 -- ]; + R4.L = W [ I3 -- ]; + R5.L = W [ I0 -- ]; + R6.L = W [ I1 -- ]; + R7.L = W [ I2 -- ]; + R0.L = W [ I3 -- ]; + CHECKREG r0, 0x00006869; + CHECKREG r1, 0x00000E0F; + CHECKREG r2, 0x00002E2F; + CHECKREG r3, 0x00004E4F; + CHECKREG r4, 0x00006E6F; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00002829; + CHECKREG r7, 0x00004849; + + R2.L = W [ I0 -- ]; + R3.L = W [ I1 -- ]; + R4.L = W [ I2 -- ]; + R5.L = W [ I3 -- ]; + R6.L = W [ I0 -- ]; + R7.L = W [ I1 -- ]; + R0.L = W [ I2 -- ]; + R1.L = W [ I3 -- ]; + CHECKREG r0, 0x00004445; + CHECKREG r1, 0x00006465; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00002A2B; + CHECKREG r4, 0x00004A4B; + CHECKREG r5, 0x00006A6B; + CHECKREG r6, 0x00000405; + CHECKREG r7, 0x00002425; + + R3.L = W [ I0 -- ]; + R4.L = W [ I1 -- ]; + R5.L = W [ I2 -- ]; + R6.L = W [ I3 -- ]; + R7.L = W [ I0 -- ]; + R0.L = W [ I1 -- ]; + R1.L = W [ I2 -- ]; + R2.L = W [ I3 -- ]; + CHECKREG r0, 0x00002021; + CHECKREG r1, 0x00004041; + CHECKREG r2, 0x00006061; + CHECKREG r3, 0x00000607; + CHECKREG r4, 0x00002627; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00006667; + CHECKREG r7, 0x00000001; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_st_dr_i.s b/tests/tcg/bfin/c_dspldst_st_dr_i.s new file mode 100644 index 0000000000000..7434607f87454 --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_st_dr_i.s @@ -0,0 +1,185 @@ +//Original:/testcases/core/c_dspldst_st_dr_i/c_dspldst_st_dr_i.dsp +// Spec Reference: c_dspldst st_dr_i +# mach: bfin + +.include "testutils.inc" + start + + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + [ I0 ] = R0; + [ I1 ] = R1; + [ I2 ] = R2; + [ I3 ] = R3; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x0a234507; + CHECKREG r5, 0x1b345618; + CHECKREG r6, 0x2c456729; + CHECKREG r7, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + [ I0 ] = R1; + [ I1 ] = R2; + [ I2 ] = R3; + [ I3 ] = R4; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x1b345618; + CHECKREG r5, 0x2c456729; + CHECKREG r6, 0x3d56783a; + CHECKREG r7, 0x4e67894b; + + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + [ I0 ] = R2; + [ I1 ] = R3; + [ I2 ] = R4; + [ I3 ] = R5; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x2c456729; + CHECKREG r5, 0x3d56783a; + CHECKREG r6, 0x4e67894b; + CHECKREG r7, 0x5f789a5c; + + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + [ I0 ] = R3; + [ I1 ] = R4; + [ I2 ] = R5; + [ I3 ] = R6; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x3d56783a; + CHECKREG r5, 0x4e67894b; + CHECKREG r6, 0x5f789a5c; + CHECKREG r7, 0x6089ab6d; + + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + [ I0 ] = R4; + [ I1 ] = R5; + [ I2 ] = R6; + [ I3 ] = R7; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x4e67894b; + CHECKREG r1, 0x5f789a5c; + CHECKREG r2, 0x6089ab6d; + CHECKREG r3, 0x719abc7e; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_st_dr_ipp.s b/tests/tcg/bfin/c_dspldst_st_dr_ipp.s new file mode 100644 index 0000000000000..87404a15053ef --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_st_dr_ipp.s @@ -0,0 +1,326 @@ +//Original:testcases/core/c_dspldst_st_dr_ipp/c_dspldst_st_dr_ipp.dsp +// Spec Reference: c_dspldst st_dr_ipp +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +//INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + +// initial values + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + [ I0 ++ ] = R0; + [ I1 ++ ] = R1; + [ I2 ++ ] = R2; + [ I3 ++ ] = R3; + + [ I0 ++ ] = R1; + [ I1 ++ ] = R2; + [ I2 ++ ] = R3; + [ I3 ++ ] = R4; + + [ I0 ++ ] = R3; + [ I1 ++ ] = R4; + [ I2 ++ ] = R5; + [ I3 ++ ] = R6; + + [ I0 ++ ] = R4; + [ I1 ++ ] = R5; + [ I2 ++ ] = R6; + [ I3 ++ ] = R7; + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x0a234507; + CHECKREG r1, 0x1b345618; + CHECKREG r2, 0x2c456729; + CHECKREG r3, 0x3d56783a; + CHECKREG r4, 0x1B345618; + CHECKREG r5, 0x2C456729; + CHECKREG r6, 0x3D56783A; + CHECKREG r7, 0x4E67894B; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x3D56783A; + CHECKREG r1, 0x4E67894B; + CHECKREG r2, 0x5F789A5C; + CHECKREG r3, 0x6089AB6D; + CHECKREG r4, 0x4E67894B; + CHECKREG r5, 0x5F789A5C; + CHECKREG r6, 0x6089AB6D; + CHECKREG r7, 0x719ABC7E; + +// initial values + + imm32 r0, 0xa0b2c3d4; + imm32 r1, 0x1b245618; + imm32 r2, 0x22b36729; + imm32 r3, 0xbd3c483a; + imm32 r4, 0xde64d54b; + imm32 r5, 0x5f785e6c; + imm32 r6, 0x30896bf7; + imm32 r7, 0x719ab770; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + + [ I0 -- ] = R0; + [ I1 -- ] = R1; + [ I2 -- ] = R2; + [ I3 -- ] = R3; + [ I0 -- ] = R4; + [ I1 -- ] = R5; + [ I2 -- ] = R6; + [ I3 -- ] = R7; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0xA0B2C3D4; + CHECKREG r1, 0x1B245618; + CHECKREG r2, 0x22B36729; + CHECKREG r3, 0xBD3C483A; + CHECKREG r4, 0xDE64D54B; + CHECKREG r5, 0x5F785E6C; + CHECKREG r6, 0x30896BF7; + CHECKREG r7, 0x719AB770; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_st_dr_ippm.s b/tests/tcg/bfin/c_dspldst_st_dr_ippm.s new file mode 100644 index 0000000000000..9b088386970b7 --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_st_dr_ippm.s @@ -0,0 +1,279 @@ +//Original:/testcases/core/c_dspldst_st_dr_ippm/c_dspldst_st_dr_ippm.dsp +// Spec Reference: c_dspldst st_dr_ippm +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + M0 = 4 (X); + M1 = 0x4 (X); + M2 = 0x4 (X); + M3 = 0x4 (X); + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + [ I0 ++ M0 ] = R0; + [ I1 ++ M1 ] = R1; + [ I2 ++ M2 ] = R2; + [ I3 ++ M3 ] = R3; + [ I0 ++ M1 ] = R1; + [ I1 ++ M2 ] = R2; + [ I2 ++ M3 ] = R3; + [ I3 ++ M0 ] = R4; + + [ I0 ++ M2 ] = R3; + [ I1 ++ M3 ] = R4; + [ I2 ++ M0 ] = R5; + [ I3 ++ M1 ] = R6; + [ I0 ++ M3 ] = R4; + [ I1 ++ M0 ] = R5; + [ I2 ++ M1 ] = R6; + [ I3 ++ M2 ] = R7; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + R0 = [ I0 ++ M0 ]; + R1 = [ I1 ++ M1 ]; + R2 = [ I2 ++ M2 ]; + R3 = [ I3 ++ M3 ]; + R4 = [ I0 ++ M1 ]; + R5 = [ I1 ++ M2 ]; + R6 = [ I2 ++ M3 ]; + R7 = [ I3 ++ M0 ]; + CHECKREG r0, 0x0A234507; + CHECKREG r1, 0x1B345618; + CHECKREG r2, 0x2C456729; + CHECKREG r3, 0x3D56783A; + CHECKREG r4, 0x1B345618; + CHECKREG r5, 0x2C456729; + CHECKREG r6, 0x3D56783A; + CHECKREG r7, 0x4E67894B; + R0 = [ I0 ++ M2 ]; + R1 = [ I1 ++ M3 ]; + R2 = [ I2 ++ M0 ]; + R3 = [ I3 ++ M1 ]; + R4 = [ I0 ++ M3 ]; + R5 = [ I1 ++ M0 ]; + R6 = [ I2 ++ M1 ]; + R7 = [ I3 ++ M2 ]; + CHECKREG r0, 0x3D56783A; + CHECKREG r1, 0x4E67894B; + CHECKREG r2, 0x5F789A5C; + CHECKREG r3, 0x6089AB6D; + CHECKREG r4, 0x4E67894B; + CHECKREG r5, 0x5F789A5C; + CHECKREG r6, 0x6089AB6D; + CHECKREG r7, 0x719ABC7E; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_st_drhi_i.s b/tests/tcg/bfin/c_dspldst_st_drhi_i.s new file mode 100644 index 0000000000000..a5aefc8982261 --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_st_drhi_i.s @@ -0,0 +1,161 @@ +//Original:/testcases/core/c_dspldst_st_drhi_i/c_dspldst_st_drhi_i.dsp +// Spec Reference: c_dspldst st_drhi_i +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ] = R0.H; + W [ I1 ] = R1.H; + W [ I2 ] = R2.H; + W [ I3 ] = R3.H; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x00010A23; + CHECKREG r5, 0x20211B34; + CHECKREG r6, 0x40412C45; + CHECKREG r7, 0x60613D56; + W [ I0 ] = R1.H; + W [ I1 ] = R2.H; + W [ I2 ] = R3.H; + W [ I3 ] = R4.H; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x00011B34; + CHECKREG r5, 0x20212C45; + CHECKREG r6, 0x40413D56; + CHECKREG r7, 0x60610001; + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + W [ I0 ] = R2.H; + W [ I1 ] = R3.H; + W [ I2 ] = R4.H; + W [ I3 ] = R5.H; + R0 = [ I0 ]; + R1 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r0, 0x00012C45; + CHECKREG r1, 0x20213D56; + CHECKREG r6, 0x40414E67; + CHECKREG r7, 0x60615F78; + + W [ I0 ] = R4.H; + W [ I1 ] = R5.H; + W [ I2 ] = R6.H; + W [ I3 ] = R7.H; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x00014E67; + CHECKREG r1, 0x20215F78; + CHECKREG r6, 0x40414E67; + CHECKREG r7, 0x60615F78; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_st_drhi_ipp.s b/tests/tcg/bfin/c_dspldst_st_drhi_ipp.s new file mode 100644 index 0000000000000..4e25d9d0c688e --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_st_drhi_ipp.s @@ -0,0 +1,355 @@ +//Original:testcases/core/c_dspldst_st_drhi_ipp/c_dspldst_st_drhi_ipp.dsp +// Spec Reference: c_dspldst st_drhi_ipp +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// Half reg 16 bit mem store + + imm32 r0, 0x0a123456; + imm32 r1, 0x11b12345; + imm32 r2, 0x222c1234; + imm32 r3, 0x3344d012; + imm32 r4, 0x5566e012; + imm32 r5, 0x789abf01; + imm32 r6, 0xabcd0123; + imm32 r7, 0x01234567; + +// initial values + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ++ ] = R0.H; + W [ I1 ++ ] = R1.H; + W [ I2 ++ ] = R2.H; + W [ I3 ++ ] = R3.H; + W [ I0 ++ ] = R1.H; + W [ I1 ++ ] = R2.H; + W [ I2 ++ ] = R3.H; + W [ I3 ++ ] = R4.H; + + W [ I0 ++ ] = R3.H; + W [ I1 ++ ] = R4.H; + W [ I2 ++ ] = R5.H; + W [ I3 ++ ] = R6.H; + + W [ I0 ++ ] = R4.H; + W [ I1 ++ ] = R5.H; + W [ I2 ++ ] = R6.H; + W [ I3 ++ ] = R7.H; + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x11B10A12; + CHECKREG r1, 0x222C11B1; + CHECKREG r2, 0x3344222C; + CHECKREG r3, 0x55663344; + CHECKREG r4, 0x55663344; + CHECKREG r5, 0x789A5566; + CHECKREG r6, 0xABCD789A; + CHECKREG r7, 0x0123ABCD; + + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x0C0D0E0F; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x4C4D4E4F; + CHECKREG r7, 0x6C6D6E6F; + +// initial values + + imm32 r0, 0x01b2c3d4; + imm32 r1, 0x10145618; + imm32 r2, 0xa2016729; + imm32 r3, 0xbb30183a; + imm32 r4, 0xdec4014b; + imm32 r5, 0x5f7d501c; + imm32 r6, 0x3089eb01; + imm32 r7, 0x719abf70; + + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + + W [ I0 -- ] = R0.H; + W [ I1 -- ] = R1.H; + W [ I2 -- ] = R2.H; + W [ I3 -- ] = R3.H; + W [ I0 -- ] = R1.H; + W [ I1 -- ] = R2.H; + W [ I2 -- ] = R3.H; + W [ I3 -- ] = R4.H; + + W [ I0 -- ] = R3.H; + W [ I1 -- ] = R4.H; + W [ I2 -- ] = R5.H; + W [ I3 -- ] = R6.H; + W [ I0 -- ] = R4.H; + W [ I1 -- ] = R5.H; + W [ I2 -- ] = R6.H; + W [ I3 -- ] = R7.H; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x000001B2; + CHECKREG r1, 0x00001014; + CHECKREG r2, 0x0000A201; + CHECKREG r3, 0x0000BB30; + CHECKREG r4, 0x1014BB30; + CHECKREG r5, 0xA201DEC4; + CHECKREG r6, 0xBB305F7D; + CHECKREG r7, 0xDEC43089; + + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0xDEC41A1B; + CHECKREG r1, 0x5F7D3A3B; + CHECKREG r2, 0x30895A5B; + CHECKREG r3, 0x719A7A7B; + CHECKREG r4, 0x14151617; + CHECKREG r5, 0x34353637; + CHECKREG r6, 0x54555657; + CHECKREG r7, 0x74757677; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_st_drlo_i.s b/tests/tcg/bfin/c_dspldst_st_drlo_i.s new file mode 100644 index 0000000000000..7b36691609abd --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_st_drlo_i.s @@ -0,0 +1,163 @@ +//Original:/testcases/core/c_dspldst_st_drlo_i/c_dspldst_st_drlo_i.dsp +// Spec Reference: c_dspldst st_drlo_i +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ] = R0.L; + W [ I1 ] = R1.L; + W [ I2 ] = R2.L; + W [ I3 ] = R3.L; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x00014507; + CHECKREG r5, 0x20215618; + CHECKREG r6, 0x40416729; + CHECKREG r7, 0x6061783A; + W [ I0 ] = R3.L; + W [ I1 ] = R2.L; + W [ I2 ] = R1.L; + W [ I3 ] = R0.L; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x0001783A; + CHECKREG r5, 0x20216729; + CHECKREG r6, 0x40415618; + CHECKREG r7, 0x60614507; + + imm32 r0, 0x1a334507; + imm32 r1, 0x12345618; + imm32 r2, 0x2c3e6729; + imm32 r3, 0x3d54f83a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f789c5c; + imm32 r6, 0x6089ad7d; + imm32 r7, 0x739abc88; + + W [ I0 ] = R4.L; + W [ I1 ] = R5.L; + W [ I2 ] = R6.L; + W [ I3 ] = R7.L; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x0001594B; + CHECKREG r1, 0x20219C5C; + CHECKREG r2, 0x4041AD7D; + CHECKREG r3, 0x6061BC88; + + W [ I0 ] = R7.L; + W [ I1 ] = R6.L; + W [ I2 ] = R5.L; + W [ I3 ] = R4.L; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x0001BC88; + CHECKREG r1, 0x2021AD7D; + CHECKREG r2, 0x40419C5C; + CHECKREG r3, 0x6061594B; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_dspldst_st_drlo_ipp.s b/tests/tcg/bfin/c_dspldst_st_drlo_ipp.s new file mode 100644 index 0000000000000..08483e38ba6da --- /dev/null +++ b/tests/tcg/bfin/c_dspldst_st_drlo_ipp.s @@ -0,0 +1,351 @@ +//Original:testcases/core/c_dspldst_st_drlo_ipp/c_dspldst_st_drlo_ipp.dsp +// Spec Reference: c_dspldst st_drlo_ipp +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// Half reg 16 bit mem store + + imm32 r0, 0x0a123456; + imm32 r1, 0x11b12345; + imm32 r2, 0x222c1234; + imm32 r3, 0x3344d012; + imm32 r4, 0x5566e012; + imm32 r5, 0x789abf01; + imm32 r6, 0xabcd0123; + imm32 r7, 0x01234567; + +// initial values + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ++ ] = R0.L; + W [ I1 ++ ] = R1.L; + W [ I2 ++ ] = R2.L; + W [ I3 ++ ] = R3.L; + W [ I0 ++ ] = R1.L; + W [ I1 ++ ] = R2.L; + W [ I2 ++ ] = R3.L; + W [ I3 ++ ] = R4.L; + + W [ I0 ++ ] = R3.L; + W [ I1 ++ ] = R4.L; + W [ I2 ++ ] = R5.L; + W [ I3 ++ ] = R6.L; + W [ I0 ++ ] = R4.L; + W [ I1 ++ ] = R5.L; + W [ I2 ++ ] = R6.L; + W [ I3 ++ ] = R7.L; + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x23453456; + CHECKREG r1, 0x12342345; + CHECKREG r2, 0xD0121234; + CHECKREG r3, 0xE012D012; + CHECKREG r4, 0xE012D012; + CHECKREG r5, 0xBF01E012; + CHECKREG r6, 0x0123BF01; + CHECKREG r7, 0x45670123; + + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x0C0D0E0F; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x4C4D4E4F; + CHECKREG r7, 0x6C6D6E6F; + +// initial values + + imm32 r0, 0x01b2c3d4; + imm32 r1, 0x10145618; + imm32 r2, 0xa2016729; + imm32 r3, 0xbb30183a; + imm32 r4, 0xdec4014b; + imm32 r5, 0x5f7d501c; + imm32 r6, 0x3089eb01; + imm32 r7, 0x719abf70; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + + W [ I0 -- ] = R0.L; + W [ I1 -- ] = R1.L; + W [ I2 -- ] = R2.L; + W [ I3 -- ] = R3.L; + W [ I0 -- ] = R1.L; + W [ I1 -- ] = R2.L; + W [ I2 -- ] = R3.L; + W [ I3 -- ] = R4.L; + + W [ I0 -- ] = R3.L; + W [ I1 -- ] = R4.L; + W [ I2 -- ] = R5.L; + W [ I3 -- ] = R6.L; + W [ I0 -- ] = R4.L; + W [ I1 -- ] = R5.L; + W [ I2 -- ] = R6.L; + W [ I3 -- ] = R7.L; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x0000C3D4; + CHECKREG r1, 0x00005618; + CHECKREG r2, 0x00006729; + CHECKREG r3, 0x0000183A; + CHECKREG r4, 0x5618183A; + CHECKREG r5, 0x6729014B; + CHECKREG r6, 0x183A501C; + CHECKREG r7, 0x014BEB01; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x014B1A1B; + CHECKREG r1, 0x501C3A3B; + CHECKREG r2, 0xEB015A5B; + CHECKREG r3, 0xBF707A7B; + CHECKREG r4, 0x14151617; + CHECKREG r5, 0x34353637; + CHECKREG r6, 0x54555657; + CHECKREG r7, 0x74757677; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldimmhalf_dreg.s b/tests/tcg/bfin/c_ldimmhalf_dreg.s new file mode 100644 index 0000000000000..b39e4e1734bb5 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_dreg.s @@ -0,0 +1,60 @@ +//Original:/testcases/core/c_ldimmhalf_dreg/c_ldimmhalf_dreg.dsp +// Spec Reference: ldimmhalf dreg imm16 +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + +// test Dreg +R0 = 0x0123 (X); +R1 = 0x1234 (X); +R2 = 0x2345 (X); +R3 = 0x3456 (X); +R4 = 0x4567 (X); +R5 = 0x5678 (X); +R6 = 0x6789 (X); +R7 = 0x789a (X); +CHECKREG r0, 0x00000123; +CHECKREG r1, 0x00001234; +CHECKREG r2, 0x00002345; +CHECKREG r3, 0x00003456; +CHECKREG r4, 0x00004567; +CHECKREG r5, 0x00005678; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x0000789A; + +R0 = -32768 (X); +R1 = -1111 (X); +R2 = -2222 (X); +R3 = -3333 (X); +R4 = -4444 (X); +R5 = -5555 (X); +R6 = -6666 (X); +R7 = -7777 (X); +CHECKREG r0, 0xFFFF8000; +CHECKREG r1, 0xFFFFFBA9; +CHECKREG r2, 0xFFFFF752; +CHECKREG r3, 0xFFFFF2FB; +CHECKREG r4, 0xFFFFEEA4; +CHECKREG r5, 0xFFFFEA4D; +CHECKREG r6, 0xFFFFE5F6; +CHECKREG r7, 0xFFFFE19F; + +R0 = 0x7fff (X); +R1 = 0x7ffe (X); +R2 = 32767 (X); +R3 = 32766 (X); +R4 = -32768 (X); +R5 = -32767 (X); +CHECKREG r0, 0x00007fff; +CHECKREG r1, 0x00007ffe; +CHECKREG r2, 0x00007fff; +CHECKREG r3, 0x00007ffe; +CHECKREG r4, 0xFFFF8000; +CHECKREG r5, 0xFFFF8001; + +pass diff --git a/tests/tcg/bfin/c_ldimmhalf_drhi.s b/tests/tcg/bfin/c_ldimmhalf_drhi.s new file mode 100644 index 0000000000000..3b7194adf2b59 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_drhi.s @@ -0,0 +1,85 @@ +//Original:/testcases/core/c_ldimmhalf_drhi/c_ldimmhalf_drhi.dsp +// Spec Reference: ldimmhalf dreg hi +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + +// test Dreg +R0.H = 0x0001; +R1.H = 0x0003; +R2.H = 0x0005; +R3.H = 0x0007; +R4.H = 0x0009; +R5.H = 0x000b; +R6.H = 0x000d; +R7.H = 0x000f; +CHECKREG r0, 0x0001FFFF; +CHECKREG r1, 0x0003FFFF; +CHECKREG r2, 0x0005FFFF; +CHECKREG r3, 0x0007FFFF; +CHECKREG r4, 0x0009FFFF; +CHECKREG r5, 0x000bFFFF; +CHECKREG r6, 0x000dFFFF; +CHECKREG r7, 0x000fFFFF; + +R0.H = 0x0020; +R1.H = 0x0040; +R2.H = 0x0060; +R3.H = 0x0080; +R4.H = 0x00a0; +R5.H = 0x00b0; +R6.H = 0x00c0; +R7.H = 0x00d0; +CHECKREG r0, 0x0020FFFF; +CHECKREG r1, 0x0040FFFF; +CHECKREG r2, 0x0060FFFF; +CHECKREG r3, 0x0080FFFF; +CHECKREG r4, 0x00a0FFFF; +CHECKREG r5, 0x00b0FFFF; +CHECKREG r6, 0x00c0FFFF; +CHECKREG r7, 0x00d0FFFF; + +R0.H = 0x0100; +R1.H = 0x0200; +R2.H = 0x0300; +R3.H = 0x0400; +R4.H = 0x0500; +R5.H = 0x0600; +R6.H = 0x0700; +R7.H = 0x0800; +CHECKREG r0, 0x0100FFFF; +CHECKREG r1, 0x0200FFFF; +CHECKREG r2, 0x0300FFFF; +CHECKREG r3, 0x0400FFFF; +CHECKREG r4, 0x0500FFFF; +CHECKREG r5, 0x0600FFFF; +CHECKREG r6, 0x0700FFFF; +CHECKREG r7, 0x0800FFFF; + +R0 = 0; +R1 = 0; +R2 = 0; +R3 = 0; +R4 = 0; +R5 = 0; +R6 = 0; +R7 = 0; +R0.H = 0x7fff; +R1.H = 0x7ffe; +R2.H = 32767; +R3.H = 32766; +R4.H = -32768; +R5.H = -32767; +CHECKREG r0, 0x7fff0000; +CHECKREG r1, 0x7ffe0000; +CHECKREG r2, 0x7fff0000; +CHECKREG r3, 0x7ffe0000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80010000; + +pass diff --git a/tests/tcg/bfin/c_ldimmhalf_drlo.s b/tests/tcg/bfin/c_ldimmhalf_drlo.s new file mode 100644 index 0000000000000..0a33d4a774dd7 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_drlo.s @@ -0,0 +1,89 @@ +//Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp +// Spec Reference: ldimmhalf dreg lo +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + +// test Dreg +R0.L = 0x0001; +R1.L = 0x0003; +R2.L = 0x0005; +R3.L = 0x0007; +R4.L = 0x0009; +R5.L = 0x000b; +R6.L = 0x000d; +R7.L = 0x000f; +CHECKREG r0, 0xFFFF0001; +CHECKREG r1, 0xFFFF0003; +CHECKREG r2, 0xFFFF0005; +CHECKREG r3, 0xFFFF0007; +CHECKREG r4, 0xFFFF0009; +CHECKREG r5, 0xFFFF000b; +CHECKREG r6, 0xFFFF000D; +CHECKREG r7, 0xFFFF000F; + +R0.L = 0x0020; +R1.L = 0x0040; +R2.L = 0x0060; +R3.L = 0x0080; +R4.L = 0x00a0; +R5.L = 0x00b0; +R6.L = 0x00c0; +R7.L = 0x00d0; +CHECKREG r0, 0xFFFF0020; +CHECKREG r1, 0xFFFF0040; +CHECKREG r2, 0xFFFF0060; +CHECKREG r3, 0xFFFF0080; +CHECKREG r4, 0xFFFF00a0; +CHECKREG r5, 0xFFFF00b0; +CHECKREG r6, 0xFFFF00c0; +CHECKREG r7, 0xFFFF00d0; + +R0.L = 0x0100; +R1.L = 0x0200; +R2.L = 0x0300; +R3.L = 0x0400; +R4.L = 0x0500; +R5.L = 0x0600; +R6.L = 0x0700; +R7.L = 0x0800; +CHECKREG r0, 0xFFFF0100; +CHECKREG r1, 0xFFFF0200; +CHECKREG r2, 0xFFFF0300; +CHECKREG r3, 0xFFFF0400; +CHECKREG r4, 0xFFFF0500; +CHECKREG r5, 0xFFFF0600; +CHECKREG r6, 0xFFFF0700; +CHECKREG r7, 0xFFFF0800; + +R0 = 0; +R1 = 0; +R2 = 0; +R3 = 0; +R4 = 0; +R5 = 0; +R6 = 0; +R7 = 0; +R0.L = 0x7fff; +R1.L = 0x7ffe; +R2.L = -32768; +R3.L = -32767; +R4.L = 32767; +R5.L = 32766; +R6.L = 32765; +R7.L = 32764; +CHECKREG r0, 0x00007fff; +CHECKREG r1, 0x00007ffe; +CHECKREG r2, 0x00008000; +CHECKREG r3, 0x00008001; +CHECKREG r4, 0x00007FFF; +CHECKREG r5, 0x00007FFE; +CHECKREG r6, 0x00007FFD; +CHECKREG r7, 0x00007FFC; + +pass diff --git a/tests/tcg/bfin/c_ldimmhalf_h_dr.s b/tests/tcg/bfin/c_ldimmhalf_h_dr.s new file mode 100644 index 0000000000000..83e60db619b6c --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_h_dr.s @@ -0,0 +1,82 @@ +//Original:/testcases/core/c_ldimmhalf_h_dr/c_ldimmhalf_h_dr.dsp +// Spec Reference: ldimmhalf h dreg +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + + +// test Dreg +R0.H = 0x0000; +R1.H = 0x0002; +R2.H = 0x0004; +R3.H = 0x0006; +R4.H = 0x0008; +R5.H = 0x000a; +R6.H = 0x000c; +R7.H = 0x000e; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0002ffff; +CHECKREG r2, 0x0004ffff; +CHECKREG r3, 0x0006ffff; +CHECKREG r4, 0x0008ffff; +CHECKREG r5, 0x000affff; +CHECKREG r6, 0x000cffff; +CHECKREG r7, 0x000effff; + +R0.H = 0x0000; +R1.H = 0x0020; +R2.H = 0x0040; +R3.H = 0x0060; +R4.H = 0x0080; +R5.H = 0x00a0; +R6.H = 0x00c0; +R7.H = 0x00e0; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0020ffff; +CHECKREG r2, 0x0040ffff; +CHECKREG r3, 0x0060ffff; +CHECKREG r4, 0x0080ffff; +CHECKREG r5, 0x00a0ffff; +CHECKREG r6, 0x00c0ffff; +CHECKREG r7, 0x00e0ffff; + +R0.H = 0x0000; +R1.H = 0x0200; +R2.H = 0x0400; +R3.H = 0x0600; +R4.H = 0x0800; +R5.H = 0x0a00; +R6.H = 0x0c00; +R7.H = 0x0e00; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0200ffff; +CHECKREG r2, 0x0400ffff; +CHECKREG r3, 0x0600ffff; +CHECKREG r4, 0x0800ffff; +CHECKREG r5, 0x0a00ffff; +CHECKREG r6, 0x0c00ffff; +CHECKREG r7, 0x0e00ffff; + +R0.H = 0x0000; +R1.H = 0x2000; +R2.H = 0x4000; +R3.H = 0x6000; +R4.H = 0x8000; +R5.H = 0xa000; +R6.H = 0xc000; +R7.H = 0xe000; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x2000ffff; +CHECKREG r2, 0x4000ffff; +CHECKREG r3, 0x6000ffff; +CHECKREG r4, 0x8000ffff; +CHECKREG r5, 0xa000ffff; +CHECKREG r6, 0xc000ffff; +CHECKREG r7, 0xe000ffff; + +pass diff --git a/tests/tcg/bfin/c_ldimmhalf_h_ibml.s b/tests/tcg/bfin/c_ldimmhalf_h_ibml.s new file mode 100644 index 0000000000000..8aedc09658959 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_h_ibml.s @@ -0,0 +1,165 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_ibml/c_ldimmhalf_h_ibml.dsp +// Spec Reference: ldimmhalf h ibml +# mach: bfin + +.include "testutils.inc" + start + + INIT_I_REGS -1; + INIT_L_REGS -1; + INIT_B_REGS -1; + INIT_M_REGS -1; + + I0.H = 0x2000; + I1.H = 0x2002; + I2.H = 0x2004; + I3.H = 0x2006; + L0.H = 0x2008; + L1.H = 0x200a; + L2.H = 0x200c; + L3.H = 0x200e; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x2000ffff; + CHECKREG r1, 0x2002ffff; + CHECKREG r2, 0x2004ffff; + CHECKREG r3, 0x2006ffff; + CHECKREG r4, 0x2008ffff; + CHECKREG r5, 0x200affff; + CHECKREG r6, 0x200cffff; + CHECKREG r7, 0x200effff; + + I0.H = 0x0111; + I1.H = 0x1111; + I2.H = 0x2222; + I3.H = 0x3333; + L0.H = 0x4444; + L1.H = 0x5555; + L2.H = 0x6666; + L3.H = 0x7777; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x0111ffff; + CHECKREG r1, 0x1111ffff; + CHECKREG r2, 0x2222ffff; + CHECKREG r3, 0x3333ffff; + CHECKREG r4, 0x4444ffff; + CHECKREG r5, 0x5555ffff; + CHECKREG r6, 0x6666ffff; + CHECKREG r7, 0x7777ffff; + + I0.H = 0x8888; + I1.H = 0x9aaa; + I2.H = 0xabbb; + I3.H = 0xbccc; + L0.H = 0xcddd; + L1.H = 0xdeee; + L2.H = 0xefff; + L3.H = 0xf111; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x8888ffff; + CHECKREG r1, 0x9aaaffff; + CHECKREG r2, 0xabbbffff; + CHECKREG r3, 0xbcccffff; + CHECKREG r4, 0xcdddffff; + CHECKREG r5, 0xdeeeffff; + CHECKREG r6, 0xefffffff; + CHECKREG r7, 0xf111ffff; + + B0.H = 0x3000; + B1.H = 0x3002; + B2.H = 0x3004; + B3.H = 0x3006; + M0.H = 0x3008; + M1.H = 0x300a; + M2.H = 0x300c; + M3.H = 0x300e; + + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0x3000ffff; + CHECKREG r1, 0x3002ffff; + CHECKREG r2, 0x3004ffff; + CHECKREG r3, 0x3006ffff; + CHECKREG r4, 0x3008ffff; + CHECKREG r5, 0x300Affff; + CHECKREG r6, 0x300cffff; + CHECKREG r7, 0x300effff; + + B0.H = 0x0110; + B1.H = 0x1110; + B2.H = 0x2220; + B3.H = 0x3330; + M0.H = 0x4440; + M1.H = 0x5550; + M2.H = 0x6660; + M3.H = 0x7770; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0x0110FFFF; + CHECKREG r1, 0x1110FFFF; + CHECKREG r2, 0x2220FFFF; + CHECKREG r3, 0x3330FFFF; + CHECKREG r4, 0x4440FFFF; + CHECKREG r5, 0x5550FFFF; + CHECKREG r6, 0x6660FFFF; + CHECKREG r7, 0x7770FFFF; + + B0.H = 0xf880; + B1.H = 0xfaa0; + B2.H = 0xfbb0; + B3.H = 0xfcc0; + M0.H = 0xfdd0; + M1.H = 0xfee0; + M2.H = 0xfff0; + M3.H = 0xf110; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xf880ffff; + CHECKREG r1, 0xfaa0ffff; + CHECKREG r2, 0xfbb0ffff; + CHECKREG r3, 0xfcc0ffff; + CHECKREG r4, 0xfdd0ffff; + CHECKREG r5, 0xfee0ffff; + CHECKREG r6, 0xfff0ffff; + CHECKREG r7, 0xf110ffff; + + pass diff --git a/tests/tcg/bfin/c_ldimmhalf_h_pr.s b/tests/tcg/bfin/c_ldimmhalf_h_pr.s new file mode 100644 index 0000000000000..cf7fb414d5a43 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_h_pr.s @@ -0,0 +1,74 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_pr/c_ldimmhalf_h_pr.dsp +// Spec Reference: ldimmhalf h preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + INIT_P_REGS -1; + imm32 sp, 0xffffffff; + imm32 fp, 0xffffffff; + +// test Preg + P1.H = 0x0002; + P2.H = 0x0004; + P3.H = 0x0006; + P4.H = 0x0008; + P5.H = 0x000a; + FP.H = 0x000c; + SP.H = 0x000e; + CHECKREG p1, 0x0002ffff; + CHECKREG p2, 0x0004ffff; + CHECKREG p3, 0x0006ffff; + CHECKREG p4, 0x0008ffff; + CHECKREG p5, 0x000affff; + CHECKREG fp, 0x000cffff; + CHECKREG sp, 0x000effff; + + P1.H = 0x0020; + P2.H = 0x0040; + P3.H = 0x0060; + P4.H = 0x0080; + P5.H = 0x00a0; + FP.H = 0x00c0; + SP.H = 0x00e0; + CHECKREG p1, 0x0020ffff; + CHECKREG p2, 0x0040ffff; + CHECKREG p3, 0x0060ffff; + CHECKREG p4, 0x0080ffff; + CHECKREG p5, 0x00a0ffff; + CHECKREG fp, 0x00c0ffff; + CHECKREG sp, 0x00e0ffff; + + P1.H = 0x0200; + P2.H = 0x0400; + P3.H = 0x0600; + P4.H = 0x0800; + P5.H = 0x0a00; + FP.H = 0x0c00; + SP.H = 0x0e00; + CHECKREG p1, 0x0200ffff; + CHECKREG p2, 0x0400ffff; + CHECKREG p3, 0x0600ffff; + CHECKREG p4, 0x0800ffff; + CHECKREG p5, 0x0a00ffff; + CHECKREG fp, 0x0c00ffff; + CHECKREG sp, 0x0e00ffff; + + P1.H = 0x2000; + P2.H = 0x4000; + P3.H = 0x6000; + P4.H = 0x8000; + P5.H = 0xa000; + FP.H = 0xc000; + SP.H = 0xe000; + CHECKREG p1, 0x2000ffff; + CHECKREG p2, 0x4000ffff; + CHECKREG p3, 0x6000ffff; + CHECKREG p4, 0x8000ffff; + CHECKREG p5, 0xa000ffff; + CHECKREG fp, 0xc000ffff; + CHECKREG sp, 0xe000ffff; + + pass diff --git a/tests/tcg/bfin/c_ldimmhalf_l_dr.s b/tests/tcg/bfin/c_ldimmhalf_l_dr.s new file mode 100644 index 0000000000000..b47284db5602c --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_l_dr.s @@ -0,0 +1,82 @@ +//Original:/testcases/core/c_ldimmhalf_l_dr/c_ldimmhalf_l_dr.dsp +// Spec Reference: ldimmhalf l dreg +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + + +// test Dreg +R0.L = 0x0001; +R1.L = 0x0003; +R2.L = 0x0005; +R3.L = 0x0007; +R4.L = 0x0009; +R5.L = 0x000b; +R6.L = 0x000d; +R7.L = 0x000f; +CHECKREG r0, 0xffff0001; +CHECKREG r1, 0xffff0003; +CHECKREG r2, 0xffff0005; +CHECKREG r3, 0xffff0007; +CHECKREG r4, 0xffff0009; +CHECKREG r5, 0xffff000b; +CHECKREG r6, 0xffff000d; +CHECKREG r7, 0xffff000f; + +R0.L = 0x0010; +R1.L = 0x0030; +R2.L = 0x0050; +R3.L = 0x0070; +R4.L = 0x0090; +R5.L = 0x00b0; +R6.L = 0x00d0; +R7.L = 0x00f0; +CHECKREG r0, 0xffff0010; +CHECKREG r1, 0xffff0030; +CHECKREG r2, 0xffff0050; +CHECKREG r3, 0xffff0070; +CHECKREG r4, 0xffff0090; +CHECKREG r5, 0xffff00b0; +CHECKREG r6, 0xffff00d0; +CHECKREG r7, 0xffff00f0; + +R0.L = 0x0100; +R1.L = 0x0300; +R2.L = 0x0500; +R3.L = 0x0700; +R4.L = 0x0900; +R5.L = 0x0b00; +R6.L = 0x0d00; +R7.L = 0x0f00; +CHECKREG r0, 0xffff0100; +CHECKREG r1, 0xffff0300; +CHECKREG r2, 0xffff0500; +CHECKREG r3, 0xffff0700; +CHECKREG r4, 0xffff0900; +CHECKREG r5, 0xffff0b00; +CHECKREG r6, 0xffff0d00; +CHECKREG r7, 0xffff0f00; + +R0.L = 0x1000; +R1.L = 0x3000; +R2.L = 0x5000; +R3.L = 0x7000; +R4.L = 0x9000; +R5.L = 0xb000; +R6.L = 0xd000; +R7.L = 0xf000; +CHECKREG r0, 0xffff1000; +CHECKREG r1, 0xffff3000; +CHECKREG r2, 0xffff5000; +CHECKREG r3, 0xffff7000; +CHECKREG r4, 0xffff9000; +CHECKREG r5, 0xffffb000; +CHECKREG r6, 0xffffd000; +CHECKREG r7, 0xfffff000; + +pass diff --git a/tests/tcg/bfin/c_ldimmhalf_l_ibml.s b/tests/tcg/bfin/c_ldimmhalf_l_ibml.s new file mode 100644 index 0000000000000..66f83b049d0bf --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_l_ibml.s @@ -0,0 +1,165 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_ibml/c_ldimmhalf_l_ibml.dsp +// Spec Reference: ldimmhalf l ibml +# mach: bfin + +.include "testutils.inc" + start + + INIT_I_REGS -1; + INIT_L_REGS -1; + INIT_M_REGS -1; + INIT_B_REGS -1; + + I0.L = 0x2001; + I1.L = 0x2003; + I2.L = 0x2005; + I3.L = 0x2007; + L0.L = 0x2009; + L1.L = 0x200b; + L2.L = 0x200d; + L3.L = 0x200f; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xffff2001; + CHECKREG r1, 0xffff2003; + CHECKREG r2, 0xffff2005; + CHECKREG r3, 0xffff2007; + CHECKREG r4, 0xffff2009; + CHECKREG r5, 0xffff200b; + CHECKREG r6, 0xffff200d; + CHECKREG r7, 0xffff200f; + + I0.L = 0x0111; + I1.L = 0x1111; + I2.L = 0x2222; + I3.L = 0x3333; + L0.L = 0x4444; + L1.L = 0x5555; + L2.L = 0x6666; + L3.L = 0x7777; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xffff0111; + CHECKREG r1, 0xffff1111; + CHECKREG r2, 0xffff2222; + CHECKREG r3, 0xffff3333; + CHECKREG r4, 0xffff4444; + CHECKREG r5, 0xffff5555; + CHECKREG r6, 0xffff6666; + CHECKREG r7, 0xffff7777; + + I0.L = 0x8888; + I1.L = 0x9aaa; + I2.L = 0xabbb; + I3.L = 0xbccc; + L0.L = 0xcddd; + L1.L = 0xdeee; + L2.L = 0xefff; + L3.L = 0xf111; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xffff8888; + CHECKREG r1, 0xffff9aaa; + CHECKREG r2, 0xffffabbb; + CHECKREG r3, 0xffffbccc; + CHECKREG r4, 0xffffcddd; + CHECKREG r5, 0xffffdeee; + CHECKREG r6, 0xffffefff; + CHECKREG r7, 0xfffff111; + + B0.L = 0x3001; + B1.L = 0x3003; + B2.L = 0x3005; + B3.L = 0x3007; + M0.L = 0x3009; + M1.L = 0x300b; + M2.L = 0x300d; + M3.L = 0x300f; + + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xffff3001; + CHECKREG r1, 0xffff3003; + CHECKREG r2, 0xffff3005; + CHECKREG r3, 0xffff3007; + CHECKREG r4, 0xffff3009; + CHECKREG r5, 0xffff300B; + CHECKREG r6, 0xffff300d; + CHECKREG r7, 0xffff300f; + + B0.L = 0x0110; + B1.L = 0x1110; + B2.L = 0x2220; + B3.L = 0x3330; + M0.L = 0x4440; + M1.L = 0x5550; + M2.L = 0x6660; + M3.L = 0x7770; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xffff0110; + CHECKREG r1, 0xffff1110; + CHECKREG r2, 0xffff2220; + CHECKREG r3, 0xffff3330; + CHECKREG r4, 0xffff4440; + CHECKREG r5, 0xffff5550; + CHECKREG r6, 0xffff6660; + CHECKREG r7, 0xffff7770; + + B0.L = 0xf880; + B1.L = 0xfaa0; + B2.L = 0xfbb0; + B3.L = 0xfcc0; + M0.L = 0xfdd0; + M1.L = 0xfee0; + M2.L = 0xfff0; + M3.L = 0xf110; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xfffff880; + CHECKREG r1, 0xfffffaa0; + CHECKREG r2, 0xfffffbb0; + CHECKREG r3, 0xfffffcc0; + CHECKREG r4, 0xfffffdd0; + CHECKREG r5, 0xfffffee0; + CHECKREG r6, 0xfffffff0; + CHECKREG r7, 0xfffff110; + + pass diff --git a/tests/tcg/bfin/c_ldimmhalf_l_pr.s b/tests/tcg/bfin/c_ldimmhalf_l_pr.s new file mode 100644 index 0000000000000..c0678622fe36e --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_l_pr.s @@ -0,0 +1,76 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_pr/c_ldimmhalf_l_pr.dsp +// Spec Reference: ldimmhalf l preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + INIT_P_REGS -1; + + imm32 sp, 0xffffffff; + imm32 fp, 0xffffffff; + +// test Preg + P1.L = 0x0003; + P2.L = 0x0005; + P3.L = 0x0007; + P4.L = 0x0009; + P5.L = 0x000b; + FP.L = 0x000d; + SP.L = 0x000f; + CHECKREG p1, 0xffff0003; + CHECKREG p2, 0xffff0005; + CHECKREG p3, 0xffff0007; + CHECKREG p4, 0xffff0009; + CHECKREG p5, 0xffff000b; + CHECKREG fp, 0xffff000d; + CHECKREG sp, 0xffff000f; + + P1.L = 0x0030; + P2.L = 0x0050; + P3.L = 0x0070; + P4.L = 0x0090; + P5.L = 0x00b0; + FP.L = 0x00d0; + SP.L = 0x00f0; +//CHECKREG p0, 0x00000010; + CHECKREG p1, 0xffff0030; + CHECKREG p2, 0xffff0050; + CHECKREG p3, 0xffff0070; + CHECKREG p4, 0xffff0090; + CHECKREG p5, 0xffff00b0; + CHECKREG fp, 0xffff00d0; + CHECKREG sp, 0xffff00f0; + + P1.L = 0x0300; + P2.L = 0x0500; + P3.L = 0x0700; + P4.L = 0x0900; + P5.L = 0x0b00; + FP.L = 0x0d00; + SP.L = 0x0f00; + CHECKREG p1, 0xffff0300; + CHECKREG p2, 0xffff0500; + CHECKREG p3, 0xffff0700; + CHECKREG p4, 0xffff0900; + CHECKREG p5, 0xffff0b00; + CHECKREG fp, 0xffff0d00; + CHECKREG sp, 0xffff0f00; + + P1.L = 0x3000; + P2.L = 0x5000; + P3.L = 0x7000; + P4.L = 0x9000; + P5.L = 0xb000; + FP.L = 0xd000; + SP.L = 0xf000; + CHECKREG p1, 0xffff3000; + CHECKREG p2, 0xffff5000; + CHECKREG p3, 0xffff7000; + CHECKREG p4, 0xffff9000; + CHECKREG p5, 0xffffb000; + CHECKREG fp, 0xffffd000; + CHECKREG sp, 0xfffff000; + + pass diff --git a/tests/tcg/bfin/c_ldimmhalf_lz_dr.s b/tests/tcg/bfin/c_ldimmhalf_lz_dr.s new file mode 100644 index 0000000000000..a2ae95ff2a39e --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_lz_dr.s @@ -0,0 +1,81 @@ +//Original:/testcases/core/c_ldimmhalf_lz_dr/c_ldimmhalf_lz_dr.dsp +// Spec Reference: ldimmhalf lz dreg +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS -1; + + +// test Dreg +R0 = 0x0001 (Z); +R1 = 0x0003 (Z); +R2 = 0x0005 (Z); +R3 = 0x0007 (Z); +R4 = 0x0009 (Z); +R5 = 0x000b (Z); +R6 = 0x000d (Z); +R7 = 0x000f (Z); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000005; +CHECKREG r3, 0x00000007; +CHECKREG r4, 0x00000009; +CHECKREG r5, 0x0000000b; +CHECKREG r6, 0x0000000d; +CHECKREG r7, 0x0000000f; + +R0 = 0x0010 (Z); +R1 = 0x0030 (Z); +R2 = 0x0050 (Z); +R3 = 0x0070 (Z); +R4 = 0x0090 (Z); +R5 = 0x00b0 (Z); +R6 = 0x00d0 (Z); +R7 = 0x00f0 (Z); +CHECKREG r0, 0x00000010; +CHECKREG r1, 0x00000030; +CHECKREG r2, 0x00000050; +CHECKREG r3, 0x00000070; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x000000b0; +CHECKREG r6, 0x000000d0; +CHECKREG r7, 0x000000f0; + +R0 = 0x0100 (Z); +R1 = 0x0300 (Z); +R2 = 0x0500 (Z); +R3 = 0x0700 (Z); +R4 = 0x0900 (Z); +R5 = 0x0b00 (Z); +R6 = 0x0d00 (Z); +R7 = 0x0f00 (Z); +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x00000300; +CHECKREG r2, 0x00000500; +CHECKREG r3, 0x00000700; +CHECKREG r4, 0x00000900; +CHECKREG r5, 0x00000b00; +CHECKREG r6, 0x00000d00; +CHECKREG r7, 0x00000f00; + +R0 = 0x1000 (Z); +R1 = 0x3000 (Z); +R2 = 0x5000 (Z); +R3 = 0x7000 (Z); +R4 = 0x9000 (Z); +R5 = 0xb000 (Z); +R6 = 0xd000 (Z); +R7 = 0xf000 (Z); +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00003000; +CHECKREG r2, 0x00005000; +CHECKREG r3, 0x00007000; +CHECKREG r4, 0x00009000; +CHECKREG r5, 0x0000b000; +CHECKREG r6, 0x0000d000; +CHECKREG r7, 0x0000f000; + +pass diff --git a/tests/tcg/bfin/c_ldimmhalf_lz_ibml.s b/tests/tcg/bfin/c_ldimmhalf_lz_ibml.s new file mode 100644 index 0000000000000..efe77ae0db248 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_lz_ibml.s @@ -0,0 +1,168 @@ +//Original:/testcases/core/c_ldimmhalf_lz_ibml/c_ldimmhalf_lz_ibml.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: ldimmhalf lz ibml + + + + +I0 = 0x2001 (Z); +I1 = 0x2003 (Z); +I2 = 0x2005 (Z); +I3 = 0x2007 (Z); +L0 = 0x2009 (Z); +L1 = 0x200b (Z); +L2 = 0x200d (Z); +L3 = 0x200f (Z); + + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x00002001; +CHECKREG r1, 0x00002003; +CHECKREG r2, 0x00002005; +CHECKREG r3, 0x00002007; +CHECKREG r4, 0x00002009; +CHECKREG r5, 0x0000200b; +CHECKREG r6, 0x0000200d; +CHECKREG r7, 0x0000200f; + +I0 = 0x0111 (Z); +I1 = 0x1111 (Z); +I2 = 0x2222 (Z); +I3 = 0x3333 (Z); +L0 = 0x4444 (Z); +L1 = 0x5555 (Z); +L2 = 0x6666 (Z); +L3 = 0x7777 (Z); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x00000111; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00002222; +CHECKREG r3, 0x00003333; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00005555; +CHECKREG r6, 0x00006666; +CHECKREG r7, 0x00007777; + +I0 = 0x8888 (Z); +I1 = 0x9aaa (Z); +I2 = 0xabbb (Z); +I3 = 0xbccc (Z); +L0 = 0xcddd (Z); +L1 = 0xdeee (Z); +L2 = 0xefff (Z); +L3 = 0xf111 (Z); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x00008888; +CHECKREG r1, 0x00009aaa; +CHECKREG r2, 0x0000abbb; +CHECKREG r3, 0x0000bccc; +CHECKREG r4, 0x0000cddd; +CHECKREG r5, 0x0000deee; +CHECKREG r6, 0x0000efff; +CHECKREG r7, 0x0000f111; + +B0 = 0x3001 (Z); +B1 = 0x3003 (Z); +B2 = 0x3005 (Z); +B3 = 0x3007 (Z); +M0 = 0x3009 (Z); +M1 = 0x300b (Z); +M2 = 0x300d (Z); +M3 = 0x300f (Z); + +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00003001; +CHECKREG r1, 0x00003003; +CHECKREG r2, 0x00003005; +CHECKREG r3, 0x00003007; +CHECKREG r4, 0x00003009; +CHECKREG r5, 0x0000300B; +CHECKREG r6, 0x0000300d; +CHECKREG r7, 0x0000300f; + + +B0 = 0x0110 (Z); +B1 = 0x1110 (Z); +B2 = 0x2220 (Z); +B3 = 0x3330 (Z); +M0 = 0x4440 (Z); +M1 = 0x5550 (Z); +M2 = 0x6660 (Z); +M3 = 0x7770 (Z); +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00000110; +CHECKREG r1, 0x00001110; +CHECKREG r2, 0x00002220; +CHECKREG r3, 0x00003330; +CHECKREG r4, 0x00004440; +CHECKREG r5, 0x00005550; +CHECKREG r6, 0x00006660; +CHECKREG r7, 0x00007770; + +B0 = 0xf880 (Z); +B1 = 0xfaa0 (Z); +B2 = 0xfbb0 (Z); +B3 = 0xfcc0 (Z); +M0 = 0xfdd0 (Z); +M1 = 0xfee0 (Z); +M2 = 0xfff0 (Z); +M3 = 0xf110 (Z); +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x0000f880; +CHECKREG r1, 0x0000faa0; +CHECKREG r2, 0x0000fbb0; +CHECKREG r3, 0x0000fcc0; +CHECKREG r4, 0x0000fdd0; +CHECKREG r5, 0x0000fee0; +CHECKREG r6, 0x0000fff0; +CHECKREG r7, 0x0000f110; + + +pass diff --git a/tests/tcg/bfin/c_ldimmhalf_lz_pr.s b/tests/tcg/bfin/c_ldimmhalf_lz_pr.s new file mode 100644 index 0000000000000..23d31910c97b9 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_lz_pr.s @@ -0,0 +1,72 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lz_pr/c_ldimmhalf_lz_pr.dsp +// Spec Reference: ldimmhalf lz preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + +// test Preg + P1 = 0x0003 (Z); + P2 = 0x0005 (Z); + P3 = 0x0007 (Z); + P4 = 0x0009 (Z); + P5 = 0x000b (Z); + FP = 0x000d (Z); + SP = 0x000f (Z); + CHECKREG p1, 0x00000003; + CHECKREG p2, 0x00000005; + CHECKREG p3, 0x00000007; + CHECKREG p4, 0x00000009; + CHECKREG p5, 0x0000000b; + CHECKREG fp, 0x0000000d; + CHECKREG sp, 0x0000000f; + + P1 = 0x0030 (Z); + P2 = 0x0050 (Z); + P3 = 0x0070 (Z); + P4 = 0x0090 (Z); + P5 = 0x00b0 (Z); + FP = 0x00d0 (Z); + SP = 0x00f0 (Z); +//CHECKREG p0, 0x00000010; + CHECKREG p1, 0x00000030; + CHECKREG p2, 0x00000050; + CHECKREG p3, 0x00000070; + CHECKREG p4, 0x00000090; + CHECKREG p5, 0x000000b0; + CHECKREG fp, 0x000000d0; + CHECKREG sp, 0x000000f0; + + P1 = 0x0300 (Z); + P2 = 0x0500 (Z); + P3 = 0x0700 (Z); + P4 = 0x0900 (Z); + P5 = 0x0b00 (Z); + FP = 0x0d00 (Z); + SP = 0x0f00 (Z); + CHECKREG p1, 0x00000300; + CHECKREG p2, 0x00000500; + CHECKREG p3, 0x00000700; + CHECKREG p4, 0x00000900; + CHECKREG p5, 0x00000b00; + CHECKREG fp, 0x00000d00; + CHECKREG sp, 0x00000f00; + + P1 = 0x3000 (Z); + P2 = 0x5000 (Z); + P3 = 0x7000 (Z); + P4 = 0x9000 (Z); + P5 = 0xb000 (Z); + FP = 0xd000 (Z); + SP = 0xf000 (Z); + CHECKREG p1, 0x00003000; + CHECKREG p2, 0x00005000; + CHECKREG p3, 0x00007000; + CHECKREG p4, 0x00009000; + CHECKREG p5, 0x0000b000; + CHECKREG fp, 0x0000d000; + CHECKREG sp, 0x0000f000; + + pass diff --git a/tests/tcg/bfin/c_ldimmhalf_lzhi_dr.s b/tests/tcg/bfin/c_ldimmhalf_lzhi_dr.s new file mode 100644 index 0000000000000..67e652a140b03 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_lzhi_dr.s @@ -0,0 +1,113 @@ +//Original:/testcases/core/c_ldimmhalf_lzhi_dr/c_ldimmhalf_lzhi_dr.dsp +// Spec Reference: ldimmhalf lz & hi dreg +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS -1; + + +// test Dreg +R0 = 0x0001 (Z); +R0.H = 0x0000; +R1 = 0x0003 (Z); +R1.H = 0x0002; +R2 = 0x0005 (Z); +R2.H = 0x0004; +R3 = 0x0007 (Z); +R3.H = 0x0006; +R4 = 0x0009 (Z); +R4.H = 0x0008; +R5 = 0x000b (Z); +R5.H = 0x000a; +R6 = 0x000d (Z); +R6.H = 0x000c; +R7 = 0x000f (Z); +R7.H = 0x000e; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000e000f; + +R0 = 0x0010 (Z); +R0.H = 0x0000; +R1 = 0x0030 (Z); +R1.H = 0x0020; +R2 = 0x0050 (Z); +R2.H = 0x0040; +R3 = 0x0070 (Z); +R3.H = 0x0060; +R4 = 0x0090 (Z); +R4.H = 0x0080; +R5 = 0x00b0 (Z); +R5.H = 0x00a0; +R6 = 0x00d0 (Z); +R6.H = 0x00c0; +R7 = 0x00f0 (Z); +R7.H = 0x00e0; +CHECKREG r0, 0x00000010; +CHECKREG r1, 0x00200030; +CHECKREG r2, 0x00400050; +CHECKREG r3, 0x00600070; +CHECKREG r4, 0x00800090; +CHECKREG r5, 0x00a000b0; +CHECKREG r6, 0x00c000d0; +CHECKREG r7, 0x00e000f0; + +R0 = 0x0100 (Z); +R0.H = 0x0000; +R1 = 0x0300 (Z); +R1.H = 0x0200; +R2 = 0x0500 (Z); +R2.H = 0x0400; +R3 = 0x0700 (Z); +R3.H = 0x0600; +R4 = 0x0900 (Z); +R4.H = 0x0800; +R5 = 0x0b00 (Z); +R5.H = 0x0a00; +R6 = 0x0d00 (Z); +R6.H = 0x0c00; +R7 = 0x0f00 (Z); +R7.H = 0x0e00; +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x02000300; +CHECKREG r2, 0x04000500; +CHECKREG r3, 0x06000700; +CHECKREG r4, 0x08000900; +CHECKREG r5, 0x0a000b00; +CHECKREG r6, 0x0c000d00; +CHECKREG r7, 0x0e000f00; + +R0 = 0x1000 (Z); +R0.H = 0x0000; +R1 = 0x3000 (Z); +R1.H = 0x2000; +R2 = 0x5000 (Z); +R2.H = 0x4000; +R3 = 0x7000 (Z); +R3.H = 0x6000; +R4 = 0x9000 (Z); +R4.H = 0x8000; +R5 = 0xb000 (Z); +R5.H = 0xa000; +R6 = 0xd000 (Z); +R6.H = 0xc000; +R7 = 0xf000 (Z); +R7.H = 0xe000; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x20003000; +CHECKREG r2, 0x40005000; +CHECKREG r3, 0x60007000; +CHECKREG r4, 0x80009000; +CHECKREG r5, 0xa000b000; +CHECKREG r6, 0xc000d000; +CHECKREG r7, 0xe000f000; + +pass diff --git a/tests/tcg/bfin/c_ldimmhalf_lzhi_ibml.s b/tests/tcg/bfin/c_ldimmhalf_lzhi_ibml.s new file mode 100644 index 0000000000000..6f5720b436092 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_lzhi_ibml.s @@ -0,0 +1,216 @@ +//Original:/testcases/core/c_ldimmhalf_lzhi_ibml/c_ldimmhalf_lzhi_ibml.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: ldimmhalf lzhi ibml + + + + +I0 = 0x2001 (Z); +I0.H = 0x2000; +I1 = 0x2003 (Z); +I1.H = 0x2002; +I2 = 0x2005 (Z); +I2.H = 0x2004; +I3 = 0x2007 (Z); +I3.H = 0x2006; +L0 = 0x2009 (Z); +L0.H = 0x2008; +L1 = 0x200b (Z); +L1.H = 0x200a; +L2 = 0x200d (Z); +L2.H = 0x200c; +L3 = 0x200f (Z); +L3.H = 0x200e; + + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x20002001; +CHECKREG r1, 0x20022003; +CHECKREG r2, 0x20042005; +CHECKREG r3, 0x20062007; +CHECKREG r4, 0x20082009; +CHECKREG r5, 0x200a200b; +CHECKREG r6, 0x200c200d; +CHECKREG r7, 0x200e200f; + +I0 = 0x0111 (Z); +I0.H = 0x1000; +I1 = 0x1111 (Z); +I1.H = 0x1000; +I2 = 0x2222 (Z); +I2.H = 0x2000; +I3 = 0x3333 (Z); +I3.H = 0x3000; +L0 = 0x4444 (Z); +L0.H = 0x4000; +L1 = 0x5555 (Z); +L1.H = 0x5000; +L2 = 0x6666 (Z); +L2.H = 0x6000; +L3 = 0x7777 (Z); +L3.H = 0x7000; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x10000111; +CHECKREG r1, 0x10001111; +CHECKREG r2, 0x20002222; +CHECKREG r3, 0x30003333; +CHECKREG r4, 0x40004444; +CHECKREG r5, 0x50005555; +CHECKREG r6, 0x60006666; +CHECKREG r7, 0x70007777; + +I0 = 0x8888 (Z); +I0.H = 0x8000; +I1 = 0x9aaa (Z); +I1.H = 0x9000; +I2 = 0xabbb (Z); +I2.H = 0xa000; +I3 = 0xbccc (Z); +I3.H = 0xb000; +L0 = 0xcddd (Z); +L0.H = 0xc000; +L1 = 0xdeee (Z); +L1.H = 0xd000; +L2 = 0xefff (Z); +L2.H = 0xe000; +L3 = 0xf111 (Z); +L3.H = 0xf000; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x80008888; +CHECKREG r1, 0x90009aaa; +CHECKREG r2, 0xa000abbb; +CHECKREG r3, 0xb000bccc; +CHECKREG r4, 0xc000cddd; +CHECKREG r5, 0xd000deee; +CHECKREG r6, 0xe000efff; +CHECKREG r7, 0xf000f111; + +B0 = 0x3001 (Z); +B0.H = 0x3000; +B1 = 0x3003 (Z); +B1.H = 0x3002; +B2 = 0x3005 (Z); +B2.H = 0x3004; +B3 = 0x3007 (Z); +B3.H = 0x3006; +M0 = 0x3009 (Z); +M0.H = 0x3008; +M1 = 0x300b (Z); +M1.H = 0x300a; +M2 = 0x300d (Z); +M2.H = 0x300c; +M3 = 0x300f (Z); +M3.H = 0x300e; + +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x30003001; +CHECKREG r1, 0x30023003; +CHECKREG r2, 0x30043005; +CHECKREG r3, 0x30063007; +CHECKREG r4, 0x30083009; +CHECKREG r5, 0x300A300B; +CHECKREG r6, 0x300c300d; +CHECKREG r7, 0x300e300f; + + +B0 = 0x0110 (Z); +B0.H = 0x1000; +B1 = 0x1110 (Z); +B1.H = 0x1000; +B2 = 0x2220 (Z); +B2.H = 0x2000; +B3 = 0x3330 (Z); +B3.H = 0x3000; +M0 = 0x4440 (Z); +M0.H = 0x4000; +M1 = 0x5550 (Z); +M1.H = 0x5000; +M2 = 0x6660 (Z); +M2.H = 0x6000; +M3 = 0x7770 (Z); +M3.H = 0x7000; +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x10000110; +CHECKREG r1, 0x10001110; +CHECKREG r2, 0x20002220; +CHECKREG r3, 0x30003330; +CHECKREG r4, 0x40004440; +CHECKREG r5, 0x50005550; +CHECKREG r6, 0x60006660; +CHECKREG r7, 0x70007770; + +B0 = 0xf880 (Z); +B0.H = 0x8000; +B1 = 0xfaa0 (Z); +B1.H = 0xa000; +B2 = 0xfbb0 (Z); +B2.H = 0xb000; +B3 = 0xfcc0 (Z); +B3.H = 0xc000; +M0 = 0xfdd0 (Z); +M0.H = 0xd000; +M1 = 0xfee0 (Z); +M1.H = 0xe000; +M2 = 0xfff0 (Z); +M2.H = 0xf000; +M3 = 0xf110 (Z); +M3.H = 0x1000; +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x8000f880; +CHECKREG r1, 0xa000faa0; +CHECKREG r2, 0xb000fbb0; +CHECKREG r3, 0xc000fcc0; +CHECKREG r4, 0xd000fdd0; +CHECKREG r5, 0xe000fee0; +CHECKREG r6, 0xf000fff0; +CHECKREG r7, 0x1000f110; + + +pass diff --git a/tests/tcg/bfin/c_ldimmhalf_lzhi_pr.s b/tests/tcg/bfin/c_ldimmhalf_lzhi_pr.s new file mode 100644 index 0000000000000..9276d36946530 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_lzhi_pr.s @@ -0,0 +1,102 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lzhi_pr/c_ldimmhalf_lzhi_pr.dsp +// Spec Reference: ldimmhalf lzhi preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + +// test Preg +//lz(p0)=0x0001; +//h(p0) =0x0000; + P1 = 0x0003 (Z); + P1.H = 0x0002; + P2 = 0x0005 (Z); + P2.H = 0x0004; + P3 = 0x0007 (Z); + P3.H = 0x0006; + P4 = 0x0009 (Z); + P4.H = 0x0008; + P5 = 0x000b (Z); + P5.H = 0x000a; + FP = 0x000d (Z); + FP.H = 0x000c; + SP = 0x000f (Z); + SP.H = 0x000e; + CHECKREG p1, 0x00020003; + CHECKREG p2, 0x00040005; + CHECKREG p3, 0x00060007; + CHECKREG p4, 0x00080009; + CHECKREG p5, 0x000a000b; + CHECKREG fp, 0x000c000d; + CHECKREG sp, 0x000e000f; + + P1 = 0x0030 (Z); + P1.H = 0x0020; + P2 = 0x0050 (Z); + P2.H = 0x0040; + P3 = 0x0070 (Z); + P3.H = 0x0060; + P4 = 0x0090 (Z); + P4.H = 0x0080; + P5 = 0x00b0 (Z); + P5.H = 0x00a0; + FP = 0x00d0 (Z); + FP.H = 0x00c0; + SP = 0x00f0 (Z); + SP.H = 0x00e0; +//CHECKREG p0, 0x00000010; + CHECKREG p1, 0x00200030; + CHECKREG p2, 0x00400050; + CHECKREG p3, 0x00600070; + CHECKREG p4, 0x00800090; + CHECKREG p5, 0x00a000b0; + CHECKREG fp, 0x00c000d0; + CHECKREG sp, 0x00e000f0; + + P1 = 0x0300 (Z); + P1.H = 0x0200; + P2 = 0x0500 (Z); + P2.H = 0x0400; + P3 = 0x0700 (Z); + P3.H = 0x0600; + P4 = 0x0900 (Z); + P4.H = 0x0800; + P5 = 0x0b00 (Z); + P5.H = 0x0a00; + FP = 0x0d00 (Z); + FP.H = 0x0c00; + SP = 0x0f00 (Z); + SP.H = 0x0e00; + CHECKREG p1, 0x02000300; + CHECKREG p2, 0x04000500; + CHECKREG p3, 0x06000700; + CHECKREG p4, 0x08000900; + CHECKREG p5, 0x0a000b00; + CHECKREG fp, 0x0c000d00; + CHECKREG sp, 0x0e000f00; + + P1 = 0x3000 (Z); + P1.H = 0x2000; + P2 = 0x5000 (Z); + P2.H = 0x4000; + P3 = 0x7000 (Z); + P3.H = 0x6000; + P4 = 0x9000 (Z); + P4.H = 0x8000; + P5 = 0xb000 (Z); + P5.H = 0xa000; + FP = 0xd000 (Z); + FP.H = 0xc000; + SP = 0xf000 (Z); + SP.H = 0xe000; + CHECKREG p1, 0x20003000; + CHECKREG p2, 0x40005000; + CHECKREG p3, 0x60007000; + CHECKREG p4, 0x80009000; + CHECKREG p5, 0xa000b000; + CHECKREG fp, 0xc000d000; + CHECKREG sp, 0xe000f000; + + pass diff --git a/tests/tcg/bfin/c_ldimmhalf_pibml.s b/tests/tcg/bfin/c_ldimmhalf_pibml.s new file mode 100644 index 0000000000000..a7e8f8be50b86 --- /dev/null +++ b/tests/tcg/bfin/c_ldimmhalf_pibml.s @@ -0,0 +1,212 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_pibml/c_ldimmhalf_pibml.dsp +// Spec Reference: ldimmhalf p i b m l +# mach: bfin + +.include "testutils.inc" + start + +// set all reg=-1 + + +//p0 =0x0123; + P1 = 0x1234 (X); + P2 = 0x2345 (X); + P3 = 0x3456 (X); + P4 = 0x4567 (X); + P5 = 0x5678 (X); + FP = 0x6789 (X); + SP = 0x789a (X); +//CHECKREG p0, 0x00000123; + CHECKREG p1, 0x00001234; + CHECKREG p2, 0x00002345; + CHECKREG p3, 0x00003456; + CHECKREG p4, 0x00004567; + CHECKREG p5, 0x00005678; + CHECKREG fp, 0x00006789; + CHECKREG sp, 0x0000789A; + +//p0 = -32768; + P1 = -32768 (X); + P2 = -2222 (X); + P3 = -3333 (X); + P4 = -4444 (X); + P5 = -5555 (X); + FP = -6666 (X); + SP = -7777 (X); +//CHECKREG r0, 0xFFFF8000; + CHECKREG p1, 0xFFFF8000; + CHECKREG p2, 0xFFFFF752; + CHECKREG p3, 0xFFFFF2FB; + CHECKREG p4, 0xFFFFEEA4; + CHECKREG p5, 0xFFFFEA4D; + CHECKREG fp, 0xFFFFE5F6; + CHECKREG sp, 0xFFFFE19F; + +//p0 =0x0123; + P1 = 0x7abc (X); + P2 = 0x6def (X); + P3 = 0x5f56 (X); + P4 = 0x7dd7 (X); + P5 = 0x4abd (X); + FP = 0x7fff (X); + SP = 0x7ffa (X); +//CHECKREG p0, 0x00000123; + CHECKREG p1, 0x00007abc; + CHECKREG p2, 0x00006def; + CHECKREG p3, 0x00005f56; + CHECKREG p4, 0x00007dd7; + CHECKREG p5, 0x00004abd; + CHECKREG fp, 0x00007fff; + CHECKREG sp, 0x00007ffa; + + I0 = 0x0123 (X); + I1 = 0x1234 (X); + I2 = 0x2345 (X); + I3 = 0x3456 (X); + B0 = 0x0567 (X); + B1 = 0x1678 (X); + B2 = 0x2789 (X); + B3 = 0x389a (X); + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x00000123; + CHECKREG r1, 0x00001234; + CHECKREG r2, 0x00002345; + CHECKREG r3, 0x00003456; + CHECKREG r4, 0x00000567; + CHECKREG r5, 0x00001678; + CHECKREG r6, 0x00002789; + CHECKREG r7, 0x0000389A; + + I0 = -32768 (X); + I1 = -12345 (X); + I2 = -23456 (X); + I3 = -3456 (X); + B0 = -4567 (X); + B1 = -5678 (X); + B2 = -6678 (X); + B3 = -7012 (X); + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xFFFF8000; + CHECKREG r1, 0xFFFFCFC7; + CHECKREG r2, 0xFFFFA460; + CHECKREG r3, 0xFFFFF280; + CHECKREG r4, 0xFFFFEE29; + CHECKREG r5, 0xFFFFE9D2; + CHECKREG r6, 0xFFFFE5EA; + CHECKREG r7, 0xFFFFE49C; + + I0 = 0x7abd (X); + I1 = 0x7bf4 (X); + I2 = 0x6c45 (X); + I3 = 0x7d56 (X); + B0 = 0x7e67 (X); + B1 = 0x7f78 (X); + B2 = 0x7ff9 (X); + B3 = 0x7fff (X); + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x00007abd; + CHECKREG r1, 0x00007bf4; + CHECKREG r2, 0x00006c45; + CHECKREG r3, 0x00007d56; + CHECKREG r4, 0x00007e67; + CHECKREG r5, 0x00007f78; + CHECKREG r6, 0x00007ff9; + CHECKREG r7, 0x00007fff; + + M0 = 0x7123 (X); + M1 = 0x7234 (X); + M2 = 0x7345 (X); + M3 = 0x7456 (X); + L0 = 0x7567 (X); + L1 = 0x7678 (X); + L2 = 0x7789 (X); + L3 = 0x789a (X); + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x00007123; + CHECKREG r1, 0x00007234; + CHECKREG r2, 0x00007345; + CHECKREG r3, 0x00007456; + CHECKREG r4, 0x00007567; + CHECKREG r5, 0x00007678; + CHECKREG r6, 0x00007789; + CHECKREG r7, 0x0000789A; + + M0 = -32768 (X); + M1 = -123 (X); + M2 = -234 (X); + M3 = -345 (X); + L0 = -456 (X); + L1 = -567 (X); + L2 = -667 (X); + L3 = -701 (X); + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xFFFF8000; + CHECKREG r1, 0xFFFFFF85; + CHECKREG r2, 0xFFFFFF16; + CHECKREG r3, 0xFFFFFEA7; + CHECKREG r4, 0xFFFFFE38; + CHECKREG r5, 0xFFFFFDC9; + CHECKREG r6, 0xFFFFFD65; + CHECKREG r7, 0xFFFFFD43; + + M0 = 0x7aaa (X); + M1 = 0x7bbb (X); + M2 = 0x7ccc (X); + M3 = 0x7ddd (X); + L0 = 0x7eee (X); + L1 = 0x7fa8 (X); + L2 = 0x7fb9 (X); + L3 = 0x7fcc (X); + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x00007aaa; + CHECKREG r1, 0x00007bbb; + CHECKREG r2, 0x00007ccc; + CHECKREG r3, 0x00007ddd; + CHECKREG r4, 0x00007eee; + CHECKREG r5, 0x00007fa8; + CHECKREG r6, 0x00007fb9; + CHECKREG r7, 0x00007fcc; + + pass diff --git a/tests/tcg/bfin/c_ldst_ld_d_p.s b/tests/tcg/bfin/c_ldst_ld_d_p.s new file mode 100644 index 0000000000000..1183e44dc7bc4 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p.s @@ -0,0 +1,372 @@ +//Original:/testcases/core/c_ldst_ld_d_p/c_ldst_ld_d_p.dsp +// Spec Reference: c_ldst ld d [p] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ P5 ]; + R6 = [ FP ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x80818283; + CHECKREG r6, 0x00010203; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + CHECKREG r0, 0x20212223; + CHECKREG r1, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + CHECKREG r0, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + R3 = [ P5 ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x80818283; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + R3 = [ P5 ]; + R4 = [ FP ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x80818283; + CHECKREG r4, 0x00010203; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + R3 = [ P5 ]; + R4 = [ FP ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x80818283; + CHECKREG r4, 0x00010203; + CHECKREG r6, 0x00010203; + CHECKREG r7, 0x00010203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_b.s b/tests/tcg/bfin/c_ldst_ld_d_p_b.s new file mode 100644 index 0000000000000..369bb6dea2b7a --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_b.s @@ -0,0 +1,353 @@ +//Original:/testcases/core/c_ldst_ld_d_p_b/c_ldst_ld_d_p_b.dsp +// Spec Reference: c_ldst ld d [p] b +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 8 bits from memory, and zero extend into 32-bit reg + R0 = B [ P1 ] (Z); + R1 = B [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = B [ P3 ] (Z); +.else + R2 = 0x43 (Z); +.endif + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ P5 ] (Z); + R6 = B [ FP ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000083; + CHECKREG r6, 0x00000003; + R1 = B [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = B [ P3 ] (Z); +.else + R2 = 0x43 (Z); +.endif + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ FP ] (Z); + R7 = B [ P1 ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; +.ifndef BFIN_HOST + R2 = B [ P3 ] (Z); +.else + R2 = 0x43 (Z); +.endif + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ FP ] (Z); + R7 = B [ P1 ] (Z); + R0 = B [ P2 ] (Z); + CHECKREG r0, 0x00000023; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ FP ] (Z); + R7 = B [ P1 ] (Z); + R0 = B [ P2 ] (Z); +.ifndef BFIN_HOST + R1 = B [ P3 ] (Z); +.else + R1 = 0x43; +.endif + CHECKREG r0, 0x00000023; + CHECKREG r1, 0x00000043; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_h.s b/tests/tcg/bfin/c_ldst_ld_d_p_h.s new file mode 100644 index 0000000000000..fb68de57b81fe --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_h.s @@ -0,0 +1,351 @@ +//Original:/testcases/core/c_ldst_ld_d_p_h/c_ldst_ld_d_p_h.dsp +// Spec Reference: c_ldst ld d [p] h +# mach: bfin + +.include "testutils.inc" + start + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 16 bits from memory and zero extend into 32-bit reg + R0 = W [ P1 ] (Z); + R1 = W [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = W [ P3 ] (Z); +.else + R2 = 0x4243(Z); +.endif + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ P5 ] (Z); + R6 = W [ FP ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00008283; + CHECKREG r6, 0x00000203; + R1 = W [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = W [ P3 ] (Z); +.else + R2 = 0x4243 (Z); +.endif + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ FP ] (Z); + R7 = W [ P1 ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; +.ifndef BFIN_HOST + R2 = W [ P3 ] (Z); +.else + R2 = 0x4243 (Z); +.endif + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ FP ] (Z); + R7 = W [ P1 ] (Z); + R0 = W [ P2 ] (Z); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ FP ] (Z); + R7 = W [ P1 ] (Z); + R0 = W [ P2 ] (Z); +.ifndef BFIN_HOST + R1 = W [ P3 ] (Z); +.else + R1 = 0x4243 (Z); +.endif + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_mm.s b/tests/tcg/bfin/c_ldst_ld_d_p_mm.s new file mode 100644 index 0000000000000..56e49a46e0755 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_mm.s @@ -0,0 +1,417 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm/c_ldst_ld_d_p_mm.dsp +// Spec Reference: c_ldst ld d [p--] +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P5 -- ]; + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r0, 0x11223344; + CHECKREG r1, 0x91929394; + CHECKREG r2, 0xC9CACBCD; + CHECKREG r3, 0xEBECEDEE; + CHECKREG r4, 0x0F101213; + CHECKREG r5, 0x20212223; + CHECKREG r6, 0xA0A1A2A3; + R1 = [ P5 -- ]; + R2 = [ P1 -- ]; + R3 = [ P2 -- ]; + R4 = [ P3 -- ]; + R5 = [ P4 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r0, 0x11223344; + CHECKREG r1, 0x1C1D1E1F; + CHECKREG r2, 0x3C3D3E3F; + CHECKREG r3, 0xC5C6C7C8; + CHECKREG r4, 0x7C7D7E7F; + CHECKREG r5, 0x9C9D9E9F; + CHECKREG r6, 0x1C1D1E1F; + CHECKREG r7, 0x9C9D9E9F; + R2 = [ P5 -- ]; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r0, 0x98999A9B; + CHECKREG r1, 0x1C1D1E1F; + CHECKREG r2, 0x18191A1B; + CHECKREG r3, 0x38393A3B; + CHECKREG r4, 0x58595A5B; + CHECKREG r5, 0x78797A7B; + CHECKREG r6, 0x98999A9B; + CHECKREG r7, 0x18191A1B; + + R3 = [ P5 -- ]; + R4 = [ P1 -- ]; + R5 = [ P2 -- ]; + R6 = [ P3 -- ]; + R7 = [ P4 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r0, 0x14151617; + CHECKREG r1, 0x94959697; + CHECKREG r2, 0x18191A1B; + CHECKREG r3, 0x14151617; + CHECKREG r4, 0x34353637; + CHECKREG r5, 0x54555657; + CHECKREG r6, 0x74757677; + CHECKREG r7, 0x94959697; + + R4 = [ P5 -- ]; + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ FP -- ]; + R2 = [ SP -- ]; + CHECKREG r0, 0x90919293; + CHECKREG r1, 0x10111213; + CHECKREG r2, 0x90919293; + CHECKREG r3, 0x14151617; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x30313233; + CHECKREG r6, 0x50515253; + CHECKREG r7, 0x70717273; + + R5 = [ P5 -- ]; + R6 = [ P1 -- ]; + R7 = [ P2 -- ]; + R0 = [ P3 -- ]; + R1 = [ P4 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r0, 0x6C6D6E6F; + CHECKREG r1, 0x8C8D8E8F; + CHECKREG r2, 0x0C0D0E0F; + CHECKREG r3, 0x8C8D8E8F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x0C0D0E0F; + CHECKREG r6, 0x2C2D2E2F; + CHECKREG r7, 0x4C4D4E4F; + + R6 = [ P5 -- ]; + R7 = [ P1 -- ]; + R0 = [ P2 -- ]; + R1 = [ P3 -- ]; + R2 = [ P4 -- ]; + R3 = [ FP -- ]; + R4 = [ SP -- ]; + CHECKREG r0, 0x48494A4B; + CHECKREG r1, 0x68696A6B; + CHECKREG r2, 0x88898A8B; + CHECKREG r3, 0x08090A0B; + CHECKREG r4, 0x88898A8B; + CHECKREG r5, 0x0C0D0E0F; + CHECKREG r6, 0x08090A0B; + CHECKREG r7, 0x28292A2B; + + R7 = [ P5 -- ]; + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ FP -- ]; + R5 = [ SP -- ]; + CHECKREG r0, 0x24252627; + CHECKREG r1, 0x44454647; + CHECKREG r2, 0x64656667; + CHECKREG r3, 0x84858687; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x84858687; + CHECKREG r6, 0x08090A0B; + CHECKREG r7, 0x04050607; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_mm_b.s b/tests/tcg/bfin/c_ldst_ld_d_p_mm_b.s new file mode 100644 index 0000000000000..f571553917a25 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_mm_b.s @@ -0,0 +1,353 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_b/c_ldst_ld_d_p_mm_b.dsp +// Spec Reference: c_ldst ld d [p--] b +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x14; + loadsym p1, DATA_ADDR_2, 0x14; + loadsym p2, DATA_ADDR_3, 0x14; + loadsym i1, DATA_ADDR_4, 0x14; + loadsym p4, DATA_ADDR_5, 0x14; + loadsym fp, DATA_ADDR_6, 0x14; + loadsym i3, DATA_ADDR_7, 0x14; + P3 = I1; SP = I3; + + R0 = B [ P5 -- ] (Z); + R1 = B [ P1 -- ] (Z); + R2 = B [ P2 -- ] (Z); + R3 = B [ P3 -- ] (Z); + R4 = B [ P4 -- ] (Z); + R5 = B [ FP -- ] (Z); + R6 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000017; + CHECKREG r1, 0x00000037; + CHECKREG r2, 0x00000057; + CHECKREG r3, 0x00000077; + CHECKREG r4, 0x00000097; + CHECKREG r5, 0x00000017; + CHECKREG r6, 0x00000097; + R1 = B [ P5 -- ] (Z); + R2 = B [ P1 -- ] (Z); + R3 = B [ P2 -- ] (Z); + R4 = B [ P3 -- ] (Z); + R5 = B [ P4 -- ] (Z); + R6 = B [ FP -- ] (Z); + R7 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000017; + CHECKREG r1, 0x00000010; + CHECKREG r2, 0x00000030; + CHECKREG r3, 0x00000050; + CHECKREG r4, 0x00000070; + CHECKREG r5, 0x00000090; + CHECKREG r6, 0x00000010; + CHECKREG r7, 0x00000090; + R2 = B [ P5 -- ] (Z); + R3 = B [ P1 -- ] (Z); + R4 = B [ P2 -- ] (Z); + R5 = B [ P3 -- ] (Z); + R6 = B [ P4 -- ] (Z); + R7 = B [ FP -- ] (Z); + R0 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000091; + CHECKREG r1, 0x00000010; + CHECKREG r2, 0x00000011; + CHECKREG r3, 0x00000031; + CHECKREG r4, 0x00000051; + CHECKREG r5, 0x00000071; + CHECKREG r6, 0x00000091; + CHECKREG r7, 0x00000011; + + R3 = B [ P5 -- ] (Z); + R4 = B [ P1 -- ] (Z); + R5 = B [ P2 -- ] (Z); + R6 = B [ P3 -- ] (Z); + R7 = B [ P4 -- ] (Z); + R0 = B [ FP -- ] (Z); + R1 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000012; + CHECKREG r1, 0x00000092; + CHECKREG r2, 0x00000011; + CHECKREG r3, 0x00000012; + CHECKREG r4, 0x00000032; + CHECKREG r5, 0x00000052; + CHECKREG r6, 0x00000072; + CHECKREG r7, 0x00000092; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_mm_h.s b/tests/tcg/bfin/c_ldst_ld_d_p_mm_h.s new file mode 100644 index 0000000000000..207f93adbf16a --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_mm_h.s @@ -0,0 +1,330 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_h/c_ldst_ld_d_p_mm_h.dsp +// Spec Reference: c_ldst ld d [p--] h +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// initial values + loadsym p5, DATA_ADDR_1, 0x10; + loadsym p1, DATA_ADDR_2, 0x10; + loadsym p2, DATA_ADDR_3, 0x10; + loadsym p4, DATA_ADDR_5, 0x10; + loadsym fp, DATA_ADDR_6, 0x10; + + R0 = W [ P5 -- ] (Z); + R1 = W [ P1 -- ] (Z); + R2 = W [ P2 -- ] (Z); + R4 = W [ P4 -- ] (Z); + R5 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00003233; + CHECKREG r2, 0x00005253; + CHECKREG r4, 0x00009293; + CHECKREG r5, 0x00001213; + R1 = W [ P5 -- ] (Z); + R2 = W [ P1 -- ] (Z); + R3 = W [ P2 -- ] (Z); + R5 = W [ P4 -- ] (Z); + R6 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00002C2D; + CHECKREG r3, 0x00004C4D; + CHECKREG r5, 0x00008C8D; + CHECKREG r6, 0x00000C0D; + R2 = W [ P5 -- ] (Z); + R3 = W [ P1 -- ] (Z); + R4 = W [ P2 -- ] (Z); + R6 = W [ P4 -- ] (Z); + R7 = W [ FP -- ] (Z); + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00002E2F; + CHECKREG r4, 0x00004E4F; + CHECKREG r6, 0x00008E8F; + CHECKREG r7, 0x00000E0F; + + R3 = W [ P5 -- ] (Z); + R4 = W [ P1 -- ] (Z); + R5 = W [ P2 -- ] (Z); + R7 = W [ P4 -- ] (Z); + R0 = W [ FP -- ] (Z); + CHECKREG r0, 0x00000809; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00002829; + CHECKREG r5, 0x00004849; + CHECKREG r7, 0x00008889; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_mm_xb.s b/tests/tcg/bfin/c_ldst_ld_d_p_mm_xb.s new file mode 100644 index 0000000000000..e545ca818d825 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_mm_xb.s @@ -0,0 +1,341 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_xb/c_ldst_ld_d_p_mm_xb.dsp +// Spec Reference: c_ldst ld d [p--] xb + +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R5 = B [ P5 -- ] (X); + R6 = B [ P1 -- ] (X); + R7 = B [ P2 -- ] (X); + R0 = B [ P3 -- ] (X); + R1 = B [ P4 -- ] (X); + R2 = B [ FP -- ] (X); + R3 = B [ SP -- ] (X); + CHECKREG r0, 0xFFFFFFEE; + CHECKREG r1, 0x00000013; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0xFFFFFFA3; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000044; + CHECKREG r6, 0xFFFFFF94; + CHECKREG r7, 0xFFFFFFCD; + + R6 = B [ P5 -- ] (X); + R7 = B [ P1 -- ] (X); + R0 = B [ P2 -- ] (X); + R1 = B [ P3 -- ] (X); + R2 = B [ P4 -- ] (X); + R3 = B [ FP -- ] (X); + R4 = B [ SP -- ] (X); + CHECKREG r0, 0xFFFFFFC5; + CHECKREG r1, 0x0000007C; + CHECKREG r2, 0xFFFFFF9C; + CHECKREG r3, 0x0000001C; + CHECKREG r4, 0xFFFFFF9C; + CHECKREG r5, 0x00000044; + CHECKREG r6, 0x0000001C; + CHECKREG r7, 0x0000003C; + + R7 = B [ P5 -- ] (X); + R0 = B [ P1 -- ] (X); + R1 = B [ P2 -- ] (X); + R2 = B [ P3 -- ] (X); + R3 = B [ P4 -- ] (X); + R4 = B [ FP -- ] (X); + R5 = B [ SP -- ] (X); + CHECKREG r0, 0x0000003D; + CHECKREG r1, 0xFFFFFFC6; + CHECKREG r2, 0x0000007D; + CHECKREG r3, 0xFFFFFF9D; + CHECKREG r4, 0x0000001D; + CHECKREG r5, 0xFFFFFF9D; + CHECKREG r6, 0x0000001C; + CHECKREG r7, 0x0000001D; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_mm_xh.s b/tests/tcg/bfin/c_ldst_ld_d_p_mm_xh.s new file mode 100644 index 0000000000000..16676a5d0f7c1 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_mm_xh.s @@ -0,0 +1,355 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_xh/c_ldst_ld_d_p_mm_xh.dsp +// Spec Reference: c_ldst ld d [p++/--] h b xh xb +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x08; + loadsym p1, DATA_ADDR_2, 0x08; + loadsym p2, DATA_ADDR_3, 0x08; + loadsym i1, DATA_ADDR_4, 0x08; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + loadsym i3, DATA_ADDR_7, 0x08; + P3 = I1; SP = I3; + + R4 = W [ P5 -- ] (X); + R5 = W [ P1 -- ] (X); + R6 = W [ P2 -- ] (X); + R7 = W [ P3 -- ] (X); + R0 = W [ P4 -- ] (X); + R1 = W [ FP -- ] (X); + R2 = W [ SP -- ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r2, 0xFFFF8A8B; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + CHECKREG r7, 0x00006A6B; + + R5 = W [ P5 -- ] (X); + R6 = W [ P1 -- ] (X); + R7 = W [ P2 -- ] (X); + R0 = W [ P3 -- ] (X); + R1 = W [ P4 -- ] (X); + R2 = W [ FP -- ] (X); + R3 = W [ SP -- ] (X); + CHECKREG r0, 0x00006465; + CHECKREG r1, 0xFFFF8485; + CHECKREG r2, 0x00000405; + CHECKREG r3, 0xFFFF8485; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00004445; + + R6 = W [ P5 -- ] (X); + R7 = W [ P1 -- ] (X); + R0 = W [ P2 -- ] (X); + R1 = W [ P3 -- ] (X); + R2 = W [ P4 -- ] (X); + R3 = W [ FP -- ] (X); + R4 = W [ SP -- ] (X); + CHECKREG r0, 0x00004647; + CHECKREG r1, 0x00006667; + CHECKREG r2, 0xFFFF8687; + CHECKREG r3, 0x00000607; + CHECKREG r4, 0xFFFF8687; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00002627; + + R7 = W [ P5 -- ] (X); + R0 = W [ P1 -- ] (X); + R1 = W [ P2 -- ] (X); + R2 = W [ P3 -- ] (X); + R3 = W [ P4 -- ] (X); + R4 = W [ FP -- ] (X); + R5 = W [ SP -- ] (X); + CHECKREG r0, 0x00002021; + CHECKREG r1, 0x00004041; + CHECKREG r2, 0x00006061; + CHECKREG r3, 0xFFFF8081; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0xFFFF8081; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00000001; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_pp.s b/tests/tcg/bfin/c_ldst_ld_d_p_pp.s new file mode 100644 index 0000000000000..c03ed687bb719 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_pp.s @@ -0,0 +1,371 @@ +//Original:/testcases/core/c_ldst_ld_d_p_pp/c_ldst_ld_d_p_pp.dsp +// Spec Reference: c_ldst ld d [p++] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = [ P5 ++ ]; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + R1 = [ P5 ++ ]; + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ FP ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x24252627; + CHECKREG r3, 0x44454647; + CHECKREG r5, 0x84858687; + CHECKREG r6, 0x04050607; + R2 = [ P5 ++ ]; + R3 = [ P1 ++ ]; + R4 = [ P2 ++ ]; + R6 = [ P4 ++ ]; + R7 = [ FP ++ ]; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x28292A2B; + CHECKREG r4, 0x48494A4B; + CHECKREG r6, 0x88898A8B; + CHECKREG r7, 0x08090A0B; + + R3 = [ P5 ++ ]; + R4 = [ P1 ++ ]; + R5 = [ P2 ++ ]; + R7 = [ P4 ++ ]; + R0 = [ FP ++ ]; + CHECKREG r0, 0x0C0D0E0F; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x2C2D2E2F; + CHECKREG r5, 0x4C4D4E4F; + CHECKREG r7, 0x8C8D8E8F; + + R4 = [ P5 ++ ]; + R5 = [ P1 ++ ]; + R6 = [ P2 ++ ]; + R0 = [ P4 ++ ]; + R1 = [ FP ++ ]; + CHECKREG r0, 0x90919293; + CHECKREG r1, 0x10111213; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x30313233; + CHECKREG r6, 0x50515253; + + R5 = [ P5 ++ ]; + R6 = [ P1 ++ ]; + R7 = [ P2 ++ ]; + R1 = [ P4 ++ ]; + R2 = [ FP ++ ]; + CHECKREG r1, 0x94959697; + CHECKREG r2, 0x14151617; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x34353637; + CHECKREG r7, 0x54555657; + + R6 = [ P5 ++ ]; + R7 = [ P1 ++ ]; + R0 = [ P2 ++ ]; + R2 = [ P4 ++ ]; + R3 = [ FP ++ ]; + CHECKREG r0, 0x58595A5B; + CHECKREG r2, 0x98999A9B; + CHECKREG r3, 0x18191A1B; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x18191A1B; + CHECKREG r7, 0x38393A3B; + + R7 = [ P5 ++ ]; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ FP ++ ]; + CHECKREG r0, 0x3C3D3E3F; + CHECKREG r1, 0xC5C6C7C8; + CHECKREG r3, 0x9C9D9E9F; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r6, 0x18191A1B; + CHECKREG r7, 0x1C1D1E1F; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_pp_b.s b/tests/tcg/bfin/c_ldst_ld_d_p_pp_b.s new file mode 100644 index 0000000000000..492ef3c9c166a --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_pp_b.s @@ -0,0 +1,324 @@ +//Original:/testcases/core/c_ldst_ld_d_p_pp_b/c_ldst_ld_d_p_pp_b.dsp +// Spec Reference: c_ldst ld d [p++] b +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = B [ P5 ++ ] (Z); + R1 = B [ P1 ++ ] (Z); + R2 = B [ P2 ++ ] (Z); + R4 = B [ P4 ++ ] (Z); + R5 = B [ FP ++ ] (Z); + + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + R1 = B [ P5 ++ ] (Z); + R2 = B [ P1 ++ ] (Z); + R3 = B [ P2 ++ ] (Z); + R5 = B [ P4 ++ ] (Z); + R6 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000022; + CHECKREG r3, 0x00000042; + CHECKREG r5, 0x00000082; + CHECKREG r6, 0x00000002; + R2 = B [ P5 ++ ] (Z); + R3 = B [ P1 ++ ] (Z); + R4 = B [ P2 ++ ] (Z); + R6 = B [ P4 ++ ] (Z); + R7 = B [ FP ++ ] (Z); + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000021; + CHECKREG r4, 0x00000041; + CHECKREG r6, 0x00000081; + CHECKREG r7, 0x00000001; + + R3 = B [ P5 ++ ] (Z); + R4 = B [ P1 ++ ] (Z); + R5 = B [ P2 ++ ] (Z); + R7 = B [ P4 ++ ] (Z); + R0 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000000; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000020; + CHECKREG r5, 0x00000040; + CHECKREG r7, 0x00000080; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_pp_h.s b/tests/tcg/bfin/c_ldst_ld_d_p_pp_h.s new file mode 100644 index 0000000000000..b5bd84f9de7f3 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_pp_h.s @@ -0,0 +1,350 @@ +//Original:/testcases/core/c_ldst_ld_d_p_pp_h/c_ldst_ld_d_p_pp_h.dsp +// Spec Reference: c_ldst ld d [p++] h +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_4; +.endif + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = W [ P5 ++ ] (Z); + R1 = W [ P1 ++ ] (Z); + R2 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R3 = W [ P3 ++ ] (Z); +.endif + R4 = W [ P4 ++ ] (Z); + R5 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; +.ifndef BFIN_HOST + CHECKREG r3, 0x00006263; +.endif + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + R1 = W [ P5 ++ ] (Z); + R2 = W [ P1 ++ ] (Z); + R3 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R4 = W [ P3 ++ ] (Z); +.endif + R5 = W [ P4 ++ ] (Z); + R6 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00002021; + CHECKREG r3, 0x00004041; +.ifndef BFIN_HOST + CHECKREG r4, 0x00006061; +.endif + CHECKREG r5, 0x00008081; + CHECKREG r6, 0x00000001; + R2 = W [ P5 ++ ] (Z); + R3 = W [ P1 ++ ] (Z); + R4 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R5 = W [ P3 ++ ] (Z); +.endif + R6 = W [ P4 ++ ] (Z); + R7 = W [ FP ++ ] (Z); + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00004647; +.ifndef BFIN_HOST + CHECKREG r5, 0x00006667; +.endif + CHECKREG r6, 0x00008687; + CHECKREG r7, 0x00000607; + + R3 = W [ P5 ++ ] (Z); + R4 = W [ P1 ++ ] (Z); + R5 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R6 = W [ P3 ++ ] (Z); +.endif + R7 = W [ P4 ++ ] (Z); + R0 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000405; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00002425; +.ifndef BFIN_HOST + CHECKREG r5, 0x00004445; + CHECKREG r6, 0x00006465; +.endif + CHECKREG r7, 0x00008485; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_pp_xb.s b/tests/tcg/bfin/c_ldst_ld_d_p_pp_xb.s new file mode 100644 index 0000000000000..834508b3aec21 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_pp_xb.s @@ -0,0 +1,355 @@ +//Original:testcases/core/c_ldst_ld_d_p_pp_xb/c_ldst_ld_d_p_pp_xb.dsp +// Spec Reference: c_ldst ld d [p++] xb +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x04; + loadsym p1, DATA_ADDR_2, 0x04; + loadsym p2, DATA_ADDR_3, 0x04; + loadsym i1, DATA_ADDR_4, 0x04; + loadsym p4, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x04; + loadsym i3, DATA_ADDR_7, 0x04; + P3 = I1; SP = I3; + + R4 = B [ P5 ++ ] (X); + R5 = B [ P1 ++ ] (X); + R6 = B [ P2 ++ ] (X); + R7 = B [ P3 ++ ] (X); + R0 = B [ P4 ++ ] (X); + R1 = B [ FP ++ ] (X); + R2 = B [ SP ++ ] (X); + CHECKREG r0, 0xFFFFFF87; + CHECKREG r1, 0x00000007; + CHECKREG r2, 0xFFFFFF87; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000027; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000067; + + R5 = B [ P5 ++ ] (X); + R6 = B [ P1 ++ ] (X); + R7 = B [ P2 ++ ] (X); + R0 = B [ P3 ++ ] (X); + R1 = B [ P4 ++ ] (X); + R2 = B [ FP ++ ] (X); + R3 = B [ SP ++ ] (X); + CHECKREG r0, 0x00000066; + CHECKREG r1, 0xFFFFFF86; + CHECKREG r2, 0x00000006; + CHECKREG r3, 0xFFFFFF86; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000026; + CHECKREG r7, 0x00000046; + + R6 = B [ P5 ++ ] (X); + R7 = B [ P1 ++ ] (X); + R0 = B [ P2 ++ ] (X); + R1 = B [ P3 ++ ] (X); + R2 = B [ P4 ++ ] (X); + R3 = B [ FP ++ ] (X); + R4 = B [ SP ++ ] (X); + CHECKREG r0, 0x00000045; + CHECKREG r1, 0x00000065; + CHECKREG r2, 0xFFFFFF85; + CHECKREG r3, 0x00000005; + CHECKREG r4, 0xFFFFFF85; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000025; + + R7 = B [ P5 ++ ] (X); + R0 = B [ P1 ++ ] (X); + R1 = B [ P2 ++ ] (X); + R2 = B [ P3 ++ ] (X); + R3 = B [ P4 ++ ] (X); + R4 = B [ FP ++ ] (X); + R5 = B [ SP ++ ] (X); + CHECKREG r0, 0x00000024; + CHECKREG r1, 0x00000044; + CHECKREG r2, 0x00000064; + CHECKREG r3, 0xFFFFFF84; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0xFFFFFF84; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000004; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_pp_xh.s b/tests/tcg/bfin/c_ldst_ld_d_p_pp_xh.s new file mode 100644 index 0000000000000..bab5d7894e94d --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_pp_xh.s @@ -0,0 +1,333 @@ +//Original:testcases/core/c_ldst_ld_d_p_pp_xh/c_ldst_ld_d_p_pp_xh.dsp +// Spec Reference: c_ldst ld d [p++] xh +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// initial values + loadsym p5, DATA_ADDR_1, 0x08; + loadsym p1, DATA_ADDR_2, 0x08; + loadsym p2, DATA_ADDR_3, 0x08; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + + R4 = W [ P5 ++ ] (X); + R5 = W [ P1 ++ ] (X); + R6 = W [ P2 ++ ] (X); + R0 = W [ P4 ++ ] (X); + R1 = W [ FP ++ ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + + R5 = W [ P5 ++ ] (X); + R6 = W [ P1 ++ ] (X); + R7 = W [ P2 ++ ] (X); + R1 = W [ P4 ++ ] (X); + R2 = W [ FP ++ ] (X); + CHECKREG r1, 0xFFFF8889; + CHECKREG r2, 0x00000809; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00002829; + CHECKREG r7, 0x00004849; + + R6 = W [ P5 ++ ] (X); + R7 = W [ P1 ++ ] (X); + R0 = W [ P2 ++ ] (X); + R2 = W [ P4 ++ ] (X); + R3 = W [ FP ++ ] (X); + CHECKREG r0, 0x00004E4F; + CHECKREG r2, 0xFFFF8E8F; + CHECKREG r3, 0x00000E0F; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00002E2F; + + R7 = W [ P5 ++ ] (X); + R0 = W [ P1 ++ ] (X); + R1 = W [ P2 ++ ] (X); + R3 = W [ P4 ++ ] (X); + R4 = W [ FP ++ ] (X); + CHECKREG r0, 0x00002C2D; + CHECKREG r1, 0x00004C4D; + CHECKREG r3, 0xFFFF8C8D; + CHECKREG r4, 0x00000C0D; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00000C0D; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_ppmm_hbx.s b/tests/tcg/bfin/c_ldst_ld_d_p_ppmm_hbx.s new file mode 100644 index 0000000000000..f782e83693df7 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_ppmm_hbx.s @@ -0,0 +1,656 @@ +//Original:/testcases/core/c_ldst_ld_d_p_ppmm_hbx/c_ldst_ld_d_p_ppmm_hbx.dsp +// Spec Reference: c_ldst ld d [p++/--] h b xh xb +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = W [ P5 ++ ] (Z); + R1 = W [ P1 ++ ] (Z); + R2 = W [ P2 ++ ] (Z); + R4 = W [ P4 ++ ] (Z); + R5 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + R1 = W [ P5 ++ ] (Z); + R2 = W [ P1 ++ ] (Z); + R3 = W [ P2 ++ ] (Z); + R5 = W [ P4 ++ ] (Z); + R6 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00002021; + CHECKREG r3, 0x00004041; + CHECKREG r5, 0x00008081; + CHECKREG r6, 0x00000001; + R2 = W [ P5 ++ ] (Z); + R3 = W [ P1 ++ ] (Z); + R4 = W [ P2 ++ ] (Z); + R6 = W [ P4 ++ ] (Z); + R7 = W [ FP ++ ] (Z); + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00004647; + CHECKREG r6, 0x00008687; + CHECKREG r7, 0x00000607; + + R3 = W [ P5 ++ ] (Z); + R4 = W [ P1 ++ ] (Z); + R5 = W [ P2 ++ ] (Z); + R7 = W [ P4 ++ ] (Z); + R0 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000405; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00002425; + CHECKREG r5, 0x00004445; + CHECKREG r7, 0x00008485; + + R4 = W [ P5 ++ ] (X); + R5 = W [ P1 ++ ] (X); + R6 = W [ P2 ++ ] (X); + R0 = W [ P4 ++ ] (X); + R1 = W [ FP ++ ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + + R5 = W [ P5 ++ ] (X); + R6 = W [ P1 ++ ] (X); + R7 = W [ P2 ++ ] (X); + R1 = W [ P4 ++ ] (X); + R2 = W [ FP ++ ] (X); + CHECKREG r1, 0xFFFF8889; + CHECKREG r2, 0x00000809; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00002829; + CHECKREG r7, 0x00004849; + + R6 = W [ P5 ++ ] (X); + R7 = W [ P1 ++ ] (X); + R0 = W [ P2 ++ ] (X); + R2 = W [ P4 ++ ] (X); + R3 = W [ FP ++ ] (X); + CHECKREG r0, 0x00004E4F; + CHECKREG r2, 0xFFFF8E8F; + CHECKREG r3, 0x00000E0F; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00002E2F; + + R7 = W [ P5 ++ ] (X); + R0 = W [ P1 ++ ] (X); + R1 = W [ P2 ++ ] (X); + R3 = W [ P4 ++ ] (X); + R4 = W [ FP ++ ] (X); + CHECKREG r0, 0x00002C2D; + CHECKREG r1, 0x00004C4D; + CHECKREG r3, 0xFFFF8C8D; + CHECKREG r4, 0x00000C0D; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00000C0D; + + R0 = W [ P5 -- ] (Z); + R1 = W [ P1 -- ] (Z); + R2 = W [ P2 -- ] (Z); + R4 = W [ P4 -- ] (Z); + R5 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00003233; + CHECKREG r2, 0x00005253; + CHECKREG r4, 0x00009293; + CHECKREG r5, 0x00001213; + R1 = W [ P5 -- ] (Z); + R2 = W [ P1 -- ] (Z); + R3 = W [ P2 -- ] (Z); + R5 = W [ P4 -- ] (Z); + R6 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00002C2D; + CHECKREG r3, 0x00004C4D; + CHECKREG r5, 0x00008C8D; + CHECKREG r6, 0x00000C0D; + R2 = W [ P5 -- ] (Z); + R3 = W [ P1 -- ] (Z); + R4 = W [ P2 -- ] (Z); + R6 = W [ P4 -- ] (Z); + R7 = W [ FP -- ] (Z); + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00002E2F; + CHECKREG r4, 0x00004E4F; + CHECKREG r6, 0x00008E8F; + CHECKREG r7, 0x00000E0F; + + R3 = W [ P5 -- ] (Z); + R4 = W [ P1 -- ] (Z); + R5 = W [ P2 -- ] (Z); + R7 = W [ P4 -- ] (Z); + R0 = W [ FP -- ] (Z); + CHECKREG r0, 0x00000809; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00002829; + CHECKREG r5, 0x00004849; + CHECKREG r7, 0x00008889; + + R4 = W [ P5 -- ] (X); + R5 = W [ P1 -- ] (X); + R6 = W [ P2 -- ] (X); + R0 = W [ P4 -- ] (X); + R1 = W [ FP -- ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + + R5 = W [ P5 -- ] (X); + R6 = W [ P1 -- ] (X); + R7 = W [ P2 -- ] (X); + R1 = W [ P4 -- ] (X); + R2 = W [ FP -- ] (X); + CHECKREG r1, 0xFFFF8485; + CHECKREG r2, 0x00000405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00004445; + + R6 = W [ P5 -- ] (X); + R7 = W [ P1 -- ] (X); + R0 = W [ P2 -- ] (X); + R2 = W [ P4 -- ] (X); + R3 = W [ FP -- ] (X); + CHECKREG r0, 0x00004647; + CHECKREG r2, 0xFFFF8687; + CHECKREG r3, 0x00000607; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00002627; + + R7 = W [ P5 -- ] (X); + R0 = W [ P1 -- ] (X); + R1 = W [ P2 -- ] (X); + R3 = W [ P4 -- ] (X); + R4 = W [ FP -- ] (X); + CHECKREG r0, 0x00002021; + CHECKREG r1, 0x00004041; + CHECKREG r3, 0xFFFF8081; + CHECKREG r4, 0x00000001; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00000001; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = B [ P5 ++ ] (Z); + R1 = B [ P1 ++ ] (Z); + R2 = B [ P2 ++ ] (Z); + R4 = B [ P4 ++ ] (Z); + R5 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + R1 = B [ P5 ++ ] (Z); + R2 = B [ P1 ++ ] (Z); + R3 = B [ P2 ++ ] (Z); + R5 = B [ P4 ++ ] (Z); + R6 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000022; + CHECKREG r3, 0x00000042; + CHECKREG r5, 0x00000082; + CHECKREG r6, 0x00000002; + R2 = B [ P5 ++ ] (Z); + R3 = B [ P1 ++ ] (Z); + R4 = B [ P2 ++ ] (Z); + R6 = B [ P4 ++ ] (Z); + R7 = B [ FP ++ ] (Z); + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000021; + CHECKREG r4, 0x00000041; + CHECKREG r6, 0x00000081; + CHECKREG r7, 0x00000001; + + R3 = B [ P5 ++ ] (Z); + R4 = B [ P1 ++ ] (Z); + R5 = B [ P2 ++ ] (Z); + R7 = B [ P4 ++ ] (Z); + R0 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000000; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000020; + CHECKREG r5, 0x00000040; + CHECKREG r7, 0x00000080; + + R4 = B [ P5 ++ ] (X); + R5 = B [ P1 ++ ] (X); + R6 = B [ P2 ++ ] (X); + R0 = B [ P4 ++ ] (X); + R1 = B [ FP ++ ] (X); + CHECKREG r0, 0xFFFFFF87; + CHECKREG r1, 0x00000007; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000027; + CHECKREG r6, 0x00000047; + + R5 = B [ P5 ++ ] (X); + R6 = B [ P1 ++ ] (X); + R7 = B [ P2 ++ ] (X); + R1 = B [ P4 ++ ] (X); + R2 = B [ FP ++ ] (X); + CHECKREG r1, 0xFFFFFF86; + CHECKREG r2, 0x00000006; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000026; + CHECKREG r7, 0x00000046; + + R6 = B [ P5 ++ ] (X); + R7 = B [ P1 ++ ] (X); + R0 = B [ P2 ++ ] (X); + R2 = B [ P4 ++ ] (X); + R3 = B [ FP ++ ] (X); + CHECKREG r0, 0x00000045; + CHECKREG r2, 0xFFFFFF85; + CHECKREG r3, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000025; + + R7 = B [ P5 ++ ] (X); + R0 = B [ P1 ++ ] (X); + R1 = B [ P2 ++ ] (X); + R3 = B [ P4 ++ ] (X); + R4 = B [ FP ++ ] (X); + CHECKREG r0, 0x00000024; + CHECKREG r1, 0x00000044; + CHECKREG r3, 0xFFFFFF84; + CHECKREG r4, 0x00000004; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000004; + + R0 = B [ P5 -- ] (Z); + R1 = B [ P1 -- ] (Z); + R2 = B [ P2 -- ] (Z); + R4 = B [ P4 -- ] (Z); + R5 = B [ FP -- ] (Z); + CHECKREG r0, 0x0000000B; + CHECKREG r1, 0x0000002B; + CHECKREG r2, 0x0000004B; + CHECKREG r4, 0x0000008B; + CHECKREG r5, 0x0000000B; + R1 = B [ P5 -- ] (Z); + R2 = B [ P1 -- ] (Z); + R3 = B [ P2 -- ] (Z); + R5 = B [ P4 -- ] (Z); + R6 = B [ FP -- ] (Z); + CHECKREG r0, 0x0000000B; + CHECKREG r1, 0x00000004; + CHECKREG r2, 0x00000024; + CHECKREG r3, 0x00000044; + CHECKREG r5, 0x00000084; + CHECKREG r6, 0x00000004; + R2 = B [ P5 -- ] (Z); + R3 = B [ P1 -- ] (Z); + R4 = B [ P2 -- ] (Z); + R6 = B [ P4 -- ] (Z); + R7 = B [ FP -- ] (Z); + CHECKREG r1, 0x00000004; + CHECKREG r2, 0x00000005; + CHECKREG r3, 0x00000025; + CHECKREG r4, 0x00000045; + CHECKREG r6, 0x00000085; + CHECKREG r7, 0x00000005; + + R3 = B [ P5 -- ] (Z); + R4 = B [ P1 -- ] (Z); + R5 = B [ P2 -- ] (Z); + R7 = B [ P4 -- ] (Z); + R0 = B [ FP -- ] (Z); + CHECKREG r0, 0x00000006; + CHECKREG r2, 0x00000005; + CHECKREG r3, 0x00000006; + CHECKREG r4, 0x00000026; + CHECKREG r5, 0x00000046; + CHECKREG r7, 0x00000086; + + R4 = B [ P5 -- ] (X); + R5 = B [ P1 -- ] (X); + R6 = B [ P2 -- ] (X); + R0 = B [ P4 -- ] (X); + R1 = B [ FP -- ] (X); + CHECKREG r0, 0xFFFFFF87; + CHECKREG r1, 0x00000007; + CHECKREG r3, 0x00000006; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000027; + CHECKREG r6, 0x00000047; + + R5 = B [ P5 -- ] (X); + R6 = B [ P1 -- ] (X); + R7 = B [ P2 -- ] (X); + R1 = B [ P4 -- ] (X); + R2 = B [ FP -- ] (X); + CHECKREG r1, 0xFFFFFF80; + CHECKREG r2, 0x00000000; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000020; + CHECKREG r7, 0x00000040; + + R6 = B [ P5 -- ] (X); + R7 = B [ P1 -- ] (X); + R0 = B [ P2 -- ] (X); + R2 = B [ P4 -- ] (X); + R3 = B [ FP -- ] (X); + CHECKREG r0, 0x00000041; + CHECKREG r2, 0xFFFFFF81; + CHECKREG r3, 0x00000001; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000001; + CHECKREG r7, 0x00000021; + + R7 = B [ P5 -- ] (X); + R0 = B [ P1 -- ] (X); + R1 = B [ P2 -- ] (X); + R3 = B [ P4 -- ] (X); + R4 = B [ FP -- ] (X); + CHECKREG r0, 0x00000022; + CHECKREG r1, 0x00000042; + CHECKREG r3, 0xFFFFFF82; + CHECKREG r4, 0x00000002; + CHECKREG r6, 0x00000001; + CHECKREG r7, 0x00000002; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_xb.s b/tests/tcg/bfin/c_ldst_ld_d_p_xb.s new file mode 100644 index 0000000000000..2337a7a8be1b1 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_xb.s @@ -0,0 +1,326 @@ +//Original:/testcases/core/c_ldst_ld_d_p_xb/c_ldst_ld_d_p_xb.dsp +// Spec Reference: c_ldst ld d [p] xb +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 8 bits from memory & sign extend into 32-bit reg + R4 = B [ P5 ] (X); + R5 = B [ FP ] (X); + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0xFFFFFF83; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R5 = B [ FP ] (X); + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + R3 = B [ P5 ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0xFFFFFF83; + CHECKREG r4, 0xFFFFFF83; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + R3 = B [ P5 ] (X); + R4 = B [ FP ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0xFFFFFF83; + CHECKREG r4, 0x00000003; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + R3 = B [ P5 ] (X); + R4 = B [ FP ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0xFFFFFF83; + CHECKREG r4, 0x00000003; + CHECKREG r7, 0x00000003; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_d_p_xh.s b/tests/tcg/bfin/c_ldst_ld_d_p_xh.s new file mode 100644 index 0000000000000..480a98d17b66c --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_d_p_xh.s @@ -0,0 +1,354 @@ +//Original:/testcases/core/c_ldst_ld_d_p_xh/c_ldst_ld_d_p_xh.dsp +// Spec Reference: c_ldst ld d [p] xh +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 16 bits from memory and sign extend into 32-bit reg + R4 = W [ P5 ] (X); + R5 = W [ FP ] (X); + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 r1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0xFFFF8283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R5 = W [ FP ] (X); + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 R1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + R3 = W [ P5 ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0xFFFF8283; + CHECKREG r4, 0xFFFF8283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 R1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + R3 = W [ P5 ] (X); + R4 = W [ FP ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0xFFFF8283; + CHECKREG r4, 0x00000203; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 R1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + R3 = W [ P5 ] (X); + R4 = W [ FP ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0xFFFF8283; + CHECKREG r4, 0x00000203; + CHECKREG r7, 0x00000203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_p_p.s b/tests/tcg/bfin/c_ldst_ld_p_p.s new file mode 100644 index 0000000000000..96658b5569ab7 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_p_p.s @@ -0,0 +1,327 @@ +//Original:/testcases/core/c_ldst_ld_p_p/c_ldst_ld_p_p.dsp +// Spec Reference: c_ldst ld p [p] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + P2 = [ P1 ]; + P4 = [ P1 ]; + P5 = [ P1 ]; + FP = [ P1 ]; + CHECKREG p2, 0x78910213; + CHECKREG p4, 0x78910213; + CHECKREG p5, 0x78910213; + CHECKREG fp, 0x78910213; + + loadsym p2, DATA_ADDR_2; + P1 = [ P2 ]; + P4 = [ P2 ]; + P5 = [ P2 ]; + FP = [ P2 ]; + CHECKREG p1, 0x20212223; + CHECKREG p4, 0x20212223; + CHECKREG p5, 0x20212223; + CHECKREG fp, 0x20212223; + + loadsym p4, DATA_ADDR_4; + P1 = [ P4 ]; + P2 = [ P4 ]; + P5 = [ P4 ]; + FP = [ P4 ]; + CHECKREG p1, 0x60616263; + CHECKREG p2, 0x60616263; + CHECKREG p5, 0x60616263; + CHECKREG fp, 0x60616263; + + loadsym p5, DATA_ADDR_5; + P1 = [ P5 ]; + P2 = [ P5 ]; + P4 = [ P5 ]; + FP = [ P5 ]; + CHECKREG p1, 0x8A8B8C8D; + CHECKREG p2, 0x8A8B8C8D; + CHECKREG p4, 0x8A8B8C8D; + CHECKREG fp, 0x8A8B8C8D; + + loadsym fp, DATA_ADDR_7; + P1 = [ FP ]; + P2 = [ FP ]; + P4 = [ FP ]; + P5 = [ FP ]; + CHECKREG p1, 0x80818283; + CHECKREG p2, 0x80818283; + CHECKREG p4, 0x80818283; + CHECKREG p5, 0x80818283; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x78910213 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x8A8B8C8D + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_p_p_mm.s b/tests/tcg/bfin/c_ldst_ld_p_p_mm.s new file mode 100644 index 0000000000000..75471c82f5040 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_p_p_mm.s @@ -0,0 +1,406 @@ +//Original:testcases/core/c_ldst_ld_p_p_mm/c_ldst_ld_p_p_mm.dsp +// Spec Reference: c_ldst ld p [p--] +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x18; + loadsym p2, DATA_ADDR_2, 0x18; + loadsym i1, DATA_ADDR_3, 0x18; + loadsym p4, DATA_ADDR_4, 0x18; + loadsym p5, DATA_ADDR_5, 0x18; + loadsym fp, DATA_ADDR_6, 0x18; + loadsym i3, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + P2 = [ P1 -- ]; + P3 = [ P1 -- ]; + P4 = [ P1 -- ]; + P5 = [ P1 -- ]; + SP = [ P1 -- ]; + FP = [ P1 -- ]; + CHECKREG p2, 0x18191A1B; + CHECKREG p3, 0x14151617; + CHECKREG p4, 0x10111213; + CHECKREG p5, 0x0C0D0E0F; + CHECKREG sp, 0x08090A0B; + CHECKREG fp, 0x04050607; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x18; + P3 = I1; SP = I3; + + P1 = [ P2 -- ]; + P3 = [ P2 -- ]; + P4 = [ P2 -- ]; + P5 = [ P2 -- ]; + SP = [ P2 -- ]; + FP = [ P2 -- ]; + CHECKREG p1, 0x38393A3B; + CHECKREG p3, 0x34353637; + CHECKREG p4, 0x30313233; + CHECKREG p5, 0x2C2D2E2F; + CHECKREG sp, 0x28292A2B; + CHECKREG fp, 0x24252627; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x18; + P3 = I1; SP = I3; + + P1 = [ P3 -- ]; + P2 = [ P3 -- ]; + P4 = [ P3 -- ]; + P5 = [ P3 -- ]; + SP = [ P3 -- ]; + FP = [ P3 -- ]; + CHECKREG p1, 0x58595A5B; + CHECKREG p2, 0x54555657; + CHECKREG p4, 0x50515253; + CHECKREG p5, 0x4C4D4E4F; + CHECKREG sp, 0x48494A4B; + CHECKREG fp, 0x44454647; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x18; + P3 = I1; SP = I3; + + P1 = [ P4 -- ]; + P2 = [ P4 -- ]; + P3 = [ P4 -- ]; + P5 = [ P4 -- ]; + SP = [ P4 -- ]; + FP = [ P4 -- ]; + CHECKREG p1, 0x78797A7B; + CHECKREG p2, 0x74757677; + CHECKREG p3, 0x70717273; + CHECKREG p5, 0x6C6D6E6F; + CHECKREG sp, 0x68696A6B; + CHECKREG fp, 0x64656667; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x18; + P3 = I1; SP = I3; + + P1 = [ P5 -- ]; + P2 = [ P5 -- ]; + P3 = [ P5 -- ]; + P4 = [ P5 -- ]; + SP = [ P5 -- ]; + FP = [ P5 -- ]; + CHECKREG p1, 0x98999A9B; + CHECKREG p2, 0x94959697; + CHECKREG p3, 0x90919293; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG sp, 0x88898A8B; + CHECKREG fp, 0x84858687; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x18; + P3 = I1; SP = I3; + + P1 = [ SP -- ]; + P2 = [ SP -- ]; + P3 = [ SP -- ]; + P4 = [ SP -- ]; + P5 = [ SP -- ]; + FP = [ SP -- ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x14151617; + CHECKREG p3, 0x10111213; + CHECKREG p4, 0x0C0D0E0F; + CHECKREG p5, 0x08090A0B; + CHECKREG fp, 0x04050607; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + P1 = [ FP -- ]; + P2 = [ FP -- ]; + P3 = [ FP -- ]; + P4 = [ FP -- ]; + P5 = [ FP -- ]; + SP = [ FP -- ]; + CHECKREG p1, 0x98999A9B; + CHECKREG p2, 0x94959697; + CHECKREG p3, 0x90919293; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG p5, 0x88898A8B; + CHECKREG sp, 0x84858687; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x78910213 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x8A8B8C8D + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_ld_p_p_pp.s b/tests/tcg/bfin/c_ldst_ld_p_p_pp.s new file mode 100644 index 0000000000000..c66440a347905 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_ld_p_p_pp.s @@ -0,0 +1,335 @@ +//Original:/testcases/core/c_ldst_ld_p_p_pp/c_ldst_ld_p_p_pp.dsp +// Spec Reference: c_ldst ld p [p++] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + P2 = [ P1 ++ ]; + P1 += 4; + P4 = [ P1 ++ ]; + P5 = [ P1 ++ ]; + P1 += 4; + FP = [ P1 ++ ]; + CHECKREG p2, 0x78910213; + CHECKREG p4, 0x08090A0B; + CHECKREG p5, 0x0C0D0E0F; + CHECKREG fp, 0x14151617; + + loadsym p2, DATA_ADDR_2; + P1 = [ P2 ++ ]; + P2 += 4; + P4 = [ P2 ++ ]; + P5 = [ P2 ++ ]; + P2 += 4; + FP = [ P2 ++ ]; + CHECKREG p1, 0x20212223; + CHECKREG p4, 0x28292A2B; + CHECKREG p5, 0x2C2D2E2F; + CHECKREG fp, 0x34353637; + + loadsym p4, DATA_ADDR_4; + P1 = [ P4 ++ ]; + P2 = [ P4 ++ ]; + P4 += 4; + P5 = [ P4 ++ ]; + P4 += 4; + FP = [ P4 ++ ]; + CHECKREG p1, 0x60616263; + CHECKREG p2, 0x64656667; + CHECKREG p5, 0x6C6D6E6F; + CHECKREG fp, 0x74757677; + + loadsym p5, DATA_ADDR_5; + P1 = [ P5 ++ ]; + P2 = [ P5 ++ ]; + P5 += 4; + P4 = [ P5 ++ ]; + P5 += 4; + FP = [ P5 ++ ]; + CHECKREG p1, 0x8A8B8C8D; + CHECKREG p2, 0x84858687; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG fp, 0x94959697; + + loadsym fp, DATA_ADDR_7; + P1 = [ FP ++ ]; + P2 = [ FP ++ ]; + FP += 4; + P4 = [ FP ++ ]; + P5 = [ FP ++ ]; + CHECKREG p1, 0x80818283; + CHECKREG p2, 0x84858687; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG p5, 0x90919293; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data +DATA_ADDR_1: + .dd 0x78910213 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x8A8B8C8D + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_st_p_d.s b/tests/tcg/bfin/c_ldst_st_p_d.s new file mode 100644 index 0000000000000..504b0279793d0 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_d.s @@ -0,0 +1,299 @@ +//Original:/testcases/core/c_ldst_st_p_d/c_ldst_st_p_d.dsp +// Spec Reference: c_ldst st_p_d +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + [ P5 ] = R0; + [ P1 ] = R1; + [ P2 ] = R2; + [ P4 ] = R4; + [ FP ] = R5; + + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x5F786A5C; + CHECKREG r7, 0x719A8C7E; + + imm32 r0, 0x1a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c353729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b7d; + imm32 r7, 0x719a8c78; + [ P5 ] = R1; + [ P1 ] = R2; + [ P2 ] = R3; + [ P4 ] = R5; + [ FP ] = R6; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2C353729; + CHECKREG r1, 0x3D54483A; + CHECKREG r3, 0x5F78665C; + CHECKREG r4, 0x12342618; + CHECKREG r5, 0x60897B7D; + CHECKREG r7, 0x719A8C78; + + imm32 r0, 0x2a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c253729; + imm32 r3, 0x3d52483a; + imm32 r4, 0x4e67294b; + imm32 r5, 0x5f78625c; + imm32 r6, 0x60897b2d; + imm32 r7, 0x719a8c72; + [ P5 ] = R2; + [ P1 ] = R3; + [ P2 ] = R4; + [ P4 ] = R6; + [ FP ] = R7; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x3D52483A; + CHECKREG r1, 0x4E67294B; + CHECKREG r3, 0x60897B2D; + CHECKREG r4, 0x2C253729; + CHECKREG r5, 0x719A8C72; + CHECKREG r7, 0x719A8C72; + + imm32 r0, 0x3a231507; + imm32 r1, 0x13342618; + imm32 r2, 0x2c353729; + imm32 r3, 0x3d53483a; + imm32 r4, 0x4e67394b; + imm32 r5, 0x5f78635c; + imm32 r6, 0x60897b3d; + imm32 r7, 0x719a8c73; + [ P5 ] = R3; + [ P1 ] = R4; + [ P2 ] = R5; + [ P4 ] = R7; + [ FP ] = R0; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x4E67394B; + CHECKREG r1, 0x5F78635C; + CHECKREG r3, 0x719A8C73; + CHECKREG r4, 0x3D53483A; + CHECKREG r5, 0x3A231507; + CHECKREG r7, 0x719A8C73; + + imm32 r0, 0x4a231507; + imm32 r1, 0x14342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67494b; + imm32 r5, 0x5f78645c; + imm32 r6, 0x60897b4d; + imm32 r7, 0x719a8c74; + [ P5 ] = R4; + [ P1 ] = R5; + [ P2 ] = R6; + [ P4 ] = R0; + [ FP ] = R1; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x5F78645C; + CHECKREG r1, 0x60897B4D; + CHECKREG r3, 0x4A231507; + CHECKREG r4, 0x4E67494B; + CHECKREG r5, 0x14342618; + CHECKREG r7, 0x719A8C74; + + imm32 r0, 0x5a231507; + imm32 r1, 0x15342618; + imm32 r2, 0x2c553729; + imm32 r3, 0x3d55483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78655c; + imm32 r6, 0x60897b5d; + imm32 r7, 0x719a8c75; + [ P5 ] = R5; + [ P1 ] = R6; + [ P2 ] = R7; + [ P4 ] = R1; + [ FP ] = R2; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x60897B5D; + CHECKREG r1, 0x719A8C75; + CHECKREG r3, 0x15342618; + CHECKREG r4, 0x5F78655C; + CHECKREG r5, 0x2C553729; + CHECKREG r7, 0x719A8C75; + + imm32 r0, 0x6a231507; + imm32 r1, 0x16342618; + imm32 r2, 0x2c653729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67694b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c76; + [ P5 ] = R6; + [ P1 ] = R7; + [ P2 ] = R0; + [ P4 ] = R2; + [ FP ] = R3; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x719A8C76; + CHECKREG r1, 0x6A231507; + CHECKREG r3, 0x2C653729; + CHECKREG r4, 0x60897B6D; + CHECKREG r5, 0x3D56483A; + CHECKREG r7, 0x719A8C76; + + imm32 r0, 0x7a231507; + imm32 r1, 0x17342618; + imm32 r2, 0x2c753729; + imm32 r3, 0x3d57483a; + imm32 r4, 0x4e67794b; + imm32 r5, 0x5f78675c; + imm32 r6, 0x60897b7d; + imm32 r7, 0x719a8c77; + [ P5 ] = R7; + [ P1 ] = R0; + [ P2 ] = R1; + [ P4 ] = R3; + [ FP ] = R4; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x7A231507; + CHECKREG r1, 0x17342618; + CHECKREG r3, 0x3D57483A; + CHECKREG r4, 0x719A8C77; + CHECKREG r5, 0x4E67794B; + CHECKREG r7, 0x719A8C77; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_st_p_d_b.s b/tests/tcg/bfin/c_ldst_st_p_d_b.s new file mode 100644 index 0000000000000..1575c001e5c08 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_d_b.s @@ -0,0 +1,300 @@ +//Original:/testcases/core/c_ldst_st_p_d_b/c_ldst_st_p_d_b.dsp +// Spec Reference: c_ldst st_p d b +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + B [ P5 ] = R0; + B [ P1 ] = R1; + B [ P2 ] = R2; + B [ P4 ] = R4; + B [ FP ] = R5; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212218; + CHECKREG r1, 0x40414229; + CHECKREG r3, 0x8081824B; + CHECKREG r4, 0x00010207; + CHECKREG r5, 0xA0A1A25C; + CHECKREG r7, 0x719A8C7E; + + imm32 r0, 0x1a231507; + imm32 r1, 0x11342618; + imm32 r2, 0x2c153729; + imm32 r3, 0x3d51483a; + imm32 r4, 0x4e67194b; + imm32 r5, 0x5f78615c; + imm32 r6, 0x60897b1d; + imm32 r7, 0x719a8c71; + B [ P5 ] = R1; + B [ P1 ] = R2; + B [ P2 ] = R3; + B [ P4 ] = R5; + B [ FP ] = R6; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212229; + CHECKREG r1, 0x4041423A; + CHECKREG r3, 0x8081825C; + CHECKREG r4, 0x00010218; + CHECKREG r5, 0xA0A1A21D; + CHECKREG r7, 0x719A8C71; + + imm32 r0, 0x2a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c253729; + imm32 r3, 0x3d52483a; + imm32 r4, 0x4e67294b; + imm32 r5, 0x5f78625c; + imm32 r6, 0x60897b2d; + imm32 r7, 0x719a8c72; + B [ P5 ] = R2; + B [ P1 ] = R3; + B [ P2 ] = R4; + B [ P4 ] = R6; + B [ FP ] = R7; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021223A; + CHECKREG r1, 0x4041424B; + CHECKREG r2, 0x2c253729; + CHECKREG r3, 0x8081822D; + CHECKREG r4, 0x00010229; + CHECKREG r5, 0xA0A1A272; + CHECKREG r7, 0x719A8C72; + + imm32 r0, 0x3a231507; + imm32 r1, 0x13342618; + imm32 r3, 0x3d53483a; + imm32 r4, 0x4e67394b; + imm32 r5, 0x5f78635c; + imm32 r6, 0x60897b3d; + imm32 r7, 0x719a8c73; + B [ P5 ] = R3; + B [ P1 ] = R4; + B [ P2 ] = R5; + B [ P4 ] = R7; + B [ FP ] = R0; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021224B; + CHECKREG r1, 0x4041425C; + CHECKREG r3, 0x80818273; + CHECKREG r4, 0x0001023A; + CHECKREG r5, 0xA0A1A207; + CHECKREG r7, 0x719A8C73; + + imm32 r0, 0x4a231507; + imm32 r1, 0x14342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67494b; + imm32 r5, 0x5f78645c; + imm32 r6, 0x60897b4d; + imm32 r7, 0x719a8c74; + B [ P5 ] = R4; + B [ P1 ] = R5; + B [ P2 ] = R6; + B [ P4 ] = R0; + B [ FP ] = R1; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021225C; + CHECKREG r1, 0x4041424D; + CHECKREG r3, 0x80818207; + CHECKREG r4, 0x0001024B; + CHECKREG r5, 0xA0A1A218; + CHECKREG r7, 0x719A8C74; + + imm32 r0, 0x5a231507; + imm32 r1, 0x15342618; + imm32 r2, 0x2c553729; + imm32 r3, 0x3d55483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78655c; + imm32 r6, 0x60897b5d; + imm32 r7, 0x719a8c75; + B [ P5 ] = R5; + B [ P1 ] = R6; + B [ P2 ] = R7; + B [ P4 ] = R1; + B [ FP ] = R2; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021225D; + CHECKREG r1, 0x40414275; + CHECKREG r3, 0x80818218; + CHECKREG r4, 0x0001025C; + CHECKREG r5, 0xA0A1A229; + CHECKREG r7, 0x719A8C75; + + imm32 r0, 0x6a231507; + imm32 r1, 0x16342618; + imm32 r2, 0x2c653729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67694b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c76; + B [ P5 ] = R6; + B [ P1 ] = R7; + B [ P2 ] = R0; + B [ P4 ] = R2; + B [ FP ] = R3; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212276; + CHECKREG r1, 0x40414207; + CHECKREG r3, 0x80818229; + CHECKREG r4, 0x0001026D; + CHECKREG r5, 0xA0A1A23A; + CHECKREG r7, 0x719A8C76; + + imm32 r0, 0x7a231507; + imm32 r1, 0x17342618; + imm32 r2, 0x2c753729; + imm32 r3, 0x3d57483a; + imm32 r4, 0x4e67794b; + imm32 r5, 0x5f78675c; + imm32 r6, 0x60897b7d; + imm32 r7, 0x719a8c77; + B [ P5 ] = R7; + B [ P1 ] = R0; + B [ P2 ] = R1; + B [ P4 ] = R3; + B [ FP ] = R4; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212207; + CHECKREG r1, 0x40414218; + CHECKREG r3, 0x8081823A; + CHECKREG r4, 0x00010277; + CHECKREG r5, 0xA0A1A24B; + CHECKREG r7, 0x719A8C77; + + pass + +// Pre-load memory witb known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_st_p_d_h.s b/tests/tcg/bfin/c_ldst_st_p_d_h.s new file mode 100644 index 0000000000000..dc0906ca4149f --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_d_h.s @@ -0,0 +1,280 @@ +//Original:/testcases/core/c_ldst_st_p_d_h/c_ldst_st_p_d_h.dsp +// Spec Reference: c_ldst st_p d h +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + W [ P5 ] = R0; + W [ P1 ] = R1; + W [ P2 ] = R2; + W [ P4 ] = R4; + W [ FP ] = R5; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212618; + CHECKREG r1, 0x40413729; + CHECKREG r3, 0x8081594B; + CHECKREG r4, 0x00011507; + CHECKREG r5, 0xA0A16A5C; + CHECKREG r7, 0x719A8C7E; + + imm32 r0, 0x1a231507; + imm32 r1, 0x11342618; + imm32 r2, 0x2c153729; + imm32 r3, 0x3d51483a; + imm32 r4, 0x4e67194b; + imm32 r5, 0x5f78615c; + imm32 r6, 0x60897b1d; + imm32 r7, 0x719a8c71; + W [ P5 ] = R1; + W [ P1 ] = R2; + W [ P2 ] = R3; + W [ P4 ] = R5; + W [ FP ] = R6; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20213729; + CHECKREG r1, 0x4041483A; + CHECKREG r3, 0x8081615C; + CHECKREG r4, 0x00012618; + CHECKREG r5, 0xA0A17B1D; + CHECKREG r6, 0x60897b1d; + + imm32 r0, 0x2a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c253729; + imm32 r3, 0x3d52483a; + imm32 r4, 0x4e67294b; + imm32 r5, 0x5f78625c; + imm32 r6, 0x60897b2d; + imm32 r7, 0x719a8c72; + W [ P5 ] = R2; + W [ P1 ] = R3; + W [ P2 ] = R4; + W [ P4 ] = R6; + W [ FP ] = R7; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021483A; + CHECKREG r1, 0x4041294B; + CHECKREG r3, 0x80817B2D; + CHECKREG r4, 0x00013729; + CHECKREG r5, 0xA0A18C72; + CHECKREG r7, 0x719A8C72; + + imm32 r0, 0x3a231507; + imm32 r1, 0x13342618; + imm32 r2, 0x2c353729; + imm32 r3, 0x3d53483a; + imm32 r4, 0x4e67394b; + imm32 r5, 0x5f78635c; + imm32 r6, 0x60897b3d; + imm32 r7, 0x719a8c73; + W [ P5 ] = R3; + W [ P1 ] = R4; + W [ P2 ] = R5; + W [ P4 ] = R7; + W [ FP ] = R0; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021394B; + CHECKREG r1, 0x4041635C; + CHECKREG r3, 0x80818C73; + CHECKREG r4, 0x0001483A; + CHECKREG r5, 0xA0A11507; + CHECKREG r7, 0x719A8C73; + + imm32 r0, 0x4a231507; + imm32 r1, 0x14342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67494b; + imm32 r5, 0x5f78645c; + imm32 r6, 0x60897b4d; + imm32 r7, 0x719a8c74; + W [ P5 ] = R4; + W [ P1 ] = R5; + W [ P2 ] = R6; + W [ P4 ] = R0; + W [ FP ] = R1; + + W [ P5 ] = R5; + W [ P1 ] = R6; + W [ P2 ] = R7; + W [ P4 ] = R1; + W [ FP ] = R2; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20217B4D; + CHECKREG r1, 0x40418C74; + CHECKREG r3, 0x80812618; + CHECKREG r4, 0x0001645C; + CHECKREG r5, 0xA0A13729; + CHECKREG r7, 0x719A8C74; + + imm32 r0, 0x5a231507; + imm32 r1, 0x15342618; + imm32 r2, 0x2c553729; + imm32 r3, 0x3d55483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78655c; + imm32 r6, 0x60897b5d; + imm32 r7, 0x719a8c75; + W [ P5 ] = R6; + W [ P1 ] = R7; + W [ P2 ] = R0; + W [ P4 ] = R2; + W [ FP ] = R3; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20218C75; + CHECKREG r1, 0x40411507; + CHECKREG r3, 0x80813729; + CHECKREG r4, 0x00017B5D; + CHECKREG r5, 0xA0A1483A; + CHECKREG r7, 0x719A8C75; + + imm32 r0, 0x6a231507; + imm32 r1, 0x16342618; + imm32 r2, 0x2c653729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67694b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c76; + W [ P5 ] = R7; + W [ P1 ] = R0; + W [ P2 ] = R1; + W [ P4 ] = R3; + W [ FP ] = R4; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20211507; + CHECKREG r1, 0x40412618; + CHECKREG r3, 0x8081483A; + CHECKREG r4, 0x00018C76; + CHECKREG r5, 0xA0A1694B; + CHECKREG r7, 0x719A8C76; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_st_p_d_mm.s b/tests/tcg/bfin/c_ldst_st_p_d_mm.s new file mode 100644 index 0000000000000..54d7faa4ca1b9 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_d_mm.s @@ -0,0 +1,601 @@ +//Original:testcases/core/c_ldst_st_p_d_mm/c_ldst_st_p_d_mm.dsp +// Spec Reference: c_ldst st_p++/p-- +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + [ P5 ++ ] = R0; + [ P1 ++ ] = R1; + [ P2 ++ ] = R2; + [ P3 ++ ] = R3; + [ P4 ++ ] = R4; + [ FP ++ ] = R5; + [ SP ++ ] = R6; + + [ P5 ++ ] = R2; + [ P1 ++ ] = R3; + [ P2 ++ ] = R4; + [ P3 ++ ] = R5; + [ P4 ++ ] = R6; + [ FP ++ ] = R7; + [ SP ++ ] = R0; + + [ P5 ++ ] = R5; + [ P1 ++ ] = R6; + [ P2 ++ ] = R7; + [ P3 ++ ] = R0; + [ P4 ++ ] = R1; + [ FP ++ ] = R2; + [ SP ++ ] = R3; + + [ P5 ++ ] = R7; + [ P1 ++ ] = R0; + [ P2 ++ ] = R1; + [ P3 ++ ] = R2; + [ P4 ++ ] = R3; + [ FP ++ ] = R4; + [ SP ++ ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R2 = [ P3 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + R6 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x60897B6D; + CHECKREG r7, 0x719A8C7E; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R2 = [ P3 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + R6 = [ SP ++ ]; + CHECKREG r0, 0x3D56483A; + CHECKREG r1, 0x4E67594B; + CHECKREG r2, 0x5F786A5C; + CHECKREG r3, 0x60897B6D; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x719A8C7E; + CHECKREG r6, 0x0A231507; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R3 = [ P3 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + R7 = [ SP ++ ]; + CHECKREG r0, 0x3D56483A; + CHECKREG r1, 0x60897B6D; + CHECKREG r2, 0x719A8C7E; + CHECKREG r3, 0x0A231507; + CHECKREG r4, 0x1B342618; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x2C453729; + CHECKREG r7, 0x3D56483A; + R3 = [ P1 ++ ]; + R4 = [ P2 ++ ]; + R5 = [ P3 ++ ]; + R6 = [ P4 ++ ]; + R7 = [ P5 ++ ]; + R0 = [ FP ++ ]; + R1 = [ SP ++ ]; + CHECKREG r0, 0x4E67594B; + CHECKREG r1, 0x5F786A5C; + CHECKREG r2, 0x719A8C7E; + CHECKREG r3, 0x0A231507; + CHECKREG r4, 0x1B342618; + CHECKREG r5, 0x2C453729; + CHECKREG r6, 0x3D56483A; + CHECKREG r7, 0x719A8C7E; + +// reset values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + [ P5 -- ] = R0; + [ P1 -- ] = R1; + [ P2 -- ] = R2; + [ P3 -- ] = R3; + [ P4 -- ] = R4; + [ FP -- ] = R5; + [ SP -- ] = R6; + + [ P5 -- ] = R2; + [ P1 -- ] = R3; + [ P2 -- ] = R4; + [ P3 -- ] = R5; + [ P4 -- ] = R6; + [ FP -- ] = R7; + [ SP -- ] = R0; + + [ P5 -- ] = R5; + [ P1 -- ] = R6; + [ P2 -- ] = R7; + [ P3 -- ] = R0; + [ P4 -- ] = R1; + [ FP -- ] = R2; + [ SP -- ] = R3; + + [ P5 -- ] = R6; + [ P1 -- ] = R7; + [ P2 -- ] = R0; + [ P3 -- ] = R1; + [ P4 -- ] = R2; + [ FP -- ] = R3; + [ SP -- ] = R4; + [ P1 -- ] = R0; + [ P2 -- ] = R1; + [ P3 -- ] = R2; + [ P4 -- ] = R3; + [ FP -- ] = R4; + [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r0, 0x5F786A5C; + CHECKREG r1, 0x719A8C7E; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x4E67594B; + CHECKREG r5, 0x2C453729; + CHECKREG r6, 0x3D56483A; + CHECKREG r7, 0x719A8C7E; + R2 = [ P1 -- ]; + R3 = [ P2 -- ]; + R4 = [ P3 -- ]; + R5 = [ P4 -- ]; + R6 = [ P5 -- ]; + R7 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r0, 0x4E67594B; + CHECKREG r1, 0x719A8C7E; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x3D56483A; + CHECKREG r6, 0x719A8C7E; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r0, 0x719A8C7E; + CHECKREG r1, 0x0A231507; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x719A8C7E; + CHECKREG r5, 0x4E67594B; + CHECKREG r6, 0x5F786A5C; + CHECKREG r7, 0x2C453729; + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ P5 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r0, 0x719A8C7E; + CHECKREG r1, 0x3D56483A; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x719A8C7E; + CHECKREG r5, 0x719A8C7E; + CHECKREG r6, 0x4E67594B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/tests/tcg/bfin/c_ldst_st_p_d_mm_b.s b/tests/tcg/bfin/c_ldst_st_p_d_mm_b.s new file mode 100644 index 0000000000000..1a2c3a98ad623 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_d_mm_b.s @@ -0,0 +1,498 @@ +//Original:testcases/core/c_ldst_st_p_d_mm_b/c_ldst_st_p_d_mm_b.dsp +// Spec Reference: c_ldst st_p-- b byte +# mach: bfin + +.include "testutils.inc" + start + + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// reset values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + B [ P5 -- ] = R0; + B [ P1 -- ] = R1; + B [ P2 -- ] = R2; + B [ P3 -- ] = R3; + B [ P4 -- ] = R4; + B [ FP -- ] = R5; + B [ SP -- ] = R6; + + B [ P5 -- ] = R1; + B [ P1 -- ] = R2; + B [ P2 -- ] = R3; + B [ P3 -- ] = R4; + B [ P4 -- ] = R5; + B [ FP -- ] = R6; + B [ SP -- ] = R7; + + B [ P5 -- ] = R2; + B [ P1 -- ] = R3; + B [ P2 -- ] = R4; + B [ P3 -- ] = R5; + B [ P4 -- ] = R6; + B [ FP -- ] = R7; + B [ SP -- ] = R0; + + B [ P5 -- ] = R3; + B [ P1 -- ] = R4; + B [ P2 -- ] = R5; + B [ P3 -- ] = R6; + B [ P4 -- ] = R7; + B [ FP -- ] = R0; + B [ SP -- ] = R1; + + B [ P5 -- ] = R4; + B [ P1 -- ] = R5; + B [ P2 -- ] = R6; + B [ P3 -- ] = R7; + B [ P4 -- ] = R0; + B [ FP -- ] = R1; + B [ SP -- ] = R2; + + B [ P5 -- ] = R5; + B [ P1 -- ] = R6; + B [ P2 -- ] = R7; + B [ P3 -- ] = R0; + B [ P4 -- ] = R1; + B [ FP -- ] = R2; + B [ SP -- ] = R3; + + B [ P5 -- ] = R6; + B [ P1 -- ] = R7; + B [ P2 -- ] = R0; + B [ P3 -- ] = R1; + B [ P4 -- ] = R2; + B [ FP -- ] = R3; + B [ SP -- ] = R4; + + B [ P5 -- ] = R7; + B [ P1 -- ] = R0; + B [ P2 -- ] = R1; + B [ P3 -- ] = R2; + B [ P4 -- ] = R3; + B [ FP -- ] = R4; + B [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x00000029; + CHECKREG r2, 0x0000003A; + CHECKREG r3, 0x0000004B; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x0000005C; + CHECKREG r6, 0xE0E1E26D; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ P5 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r1, 0x293A4B5C; + CHECKREG r2, 0x3A4B5C6D; + CHECKREG r3, 0x4B5C6D7E; + CHECKREG r4, 0x5C6D7E07; + CHECKREG r5, 0x18293A4B; + CHECKREG r6, 0x6D7E0718; + CHECKREG r7, 0x7E071829; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r1, 0x3A4B5CDB; + CHECKREG r2, 0x3A4B5C6D; + CHECKREG r3, 0x6D7E073B; + CHECKREG r4, 0x7E07185B; + CHECKREG r5, 0x0718297B; + CHECKREG r6, 0x18293A9B; + CHECKREG r7, 0x5C6D7E1B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/tests/tcg/bfin/c_ldst_st_p_d_mm_h.s b/tests/tcg/bfin/c_ldst_st_p_d_mm_h.s new file mode 100644 index 0000000000000..883bf35d3741c --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_d_mm_h.s @@ -0,0 +1,554 @@ +//Original:testcases/core/c_ldst_st_p_d_mm_h/c_ldst_st_p_d_mm_h.dsp +// Spec Reference: c_ldst st_p-- h half +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// reset values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + W [ P5 -- ] = R0; + W [ P1 -- ] = R1; + W [ P2 -- ] = R2; + W [ P3 -- ] = R3; + W [ P4 -- ] = R4; + W [ FP -- ] = R5; + W [ SP -- ] = R6; + + W [ P5 -- ] = R1; + W [ P1 -- ] = R2; + W [ P2 -- ] = R3; + W [ P3 -- ] = R4; + W [ P4 -- ] = R5; + W [ FP -- ] = R6; + W [ SP -- ] = R7; + + W [ P5 -- ] = R2; + W [ P1 -- ] = R3; + W [ P2 -- ] = R4; + W [ P3 -- ] = R5; + W [ P4 -- ] = R6; + W [ FP -- ] = R7; + W [ SP -- ] = R0; + + W [ P5 -- ] = R3; + W [ P1 -- ] = R4; + W [ P2 -- ] = R5; + W [ P3 -- ] = R6; + W [ P4 -- ] = R7; + W [ FP -- ] = R0; + W [ SP -- ] = R1; + + W [ P5 -- ] = R4; + W [ P1 -- ] = R5; + W [ P2 -- ] = R6; + W [ P3 -- ] = R7; + W [ P4 -- ] = R0; + W [ FP -- ] = R1; + W [ SP -- ] = R2; + + W [ P5 -- ] = R5; + W [ P1 -- ] = R6; + W [ P2 -- ] = R7; + W [ P3 -- ] = R0; + W [ P4 -- ] = R1; + W [ FP -- ] = R2; + W [ SP -- ] = R3; + + W [ P5 -- ] = R6; + W [ P1 -- ] = R7; + W [ P2 -- ] = R0; + W [ P3 -- ] = R1; + W [ P4 -- ] = R2; + W [ FP -- ] = R3; + W [ SP -- ] = R4; + + W [ P5 -- ] = R7; + W [ P1 -- ] = R0; + W [ P2 -- ] = R1; + W [ P3 -- ] = R2; + W [ P4 -- ] = R3; + W [ FP -- ] = R4; + W [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x00003729; + CHECKREG r2, 0x0000483A; + CHECKREG r3, 0x0000594B; + CHECKREG r4, 0x00001507; + CHECKREG r5, 0x00006A5C; + CHECKREG r6, 0xE0E17B6D; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ P5 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r1, 0x3729483A; + CHECKREG r2, 0x483A594B; + CHECKREG r3, 0x594B6A5C; + CHECKREG r4, 0x6A5C7B6D; + CHECKREG r5, 0x26183729; + CHECKREG r6, 0x7B6D8C7E; + CHECKREG r7, 0x8C7E1507; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r1, 0x26183729; + CHECKREG r2, 0x483A594B; + CHECKREG r3, 0x594B6A5C; + CHECKREG r4, 0x6A5C7B6D; + CHECKREG r5, 0x7B6D8C7E; + CHECKREG r6, 0x8C7E1507; + CHECKREG r7, 0x483A594B; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r1, 0x483A594B; + CHECKREG r2, 0x483A594B; + CHECKREG r3, 0x7B6D8C7E; + CHECKREG r4, 0x8C7E1507; + CHECKREG r5, 0x15072618; + CHECKREG r6, 0x26183729; + CHECKREG r7, 0x6A5C7B6D; + R4 = [ P1 -- ]; + R5 = [ P2 -- ]; + R6 = [ P3 -- ]; + R7 = [ P4 -- ]; + R0 = [ P5 -- ]; + R1 = [ FP -- ]; + R2 = [ SP -- ]; + CHECKREG r1, 0x594BB2B3; + CHECKREG r2, 0x6A5CD2D3; + CHECKREG r3, 0x7B6D8C7E; + CHECKREG r4, 0x15073233; + CHECKREG r5, 0x26185253; + CHECKREG r6, 0x37297273; + CHECKREG r7, 0x483A9293; + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ P5 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r1, 0x0C0D0E0F; + CHECKREG r2, 0xACADAEAF; + CHECKREG r3, 0xCCCDCECF; + CHECKREG r4, 0x15073233; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x4C4D4E4F; + CHECKREG r7, 0x6C6D6E6F; + R6 = [ P1 -- ]; + R7 = [ P2 -- ]; + R0 = [ P3 -- ]; + R1 = [ P4 -- ]; + R2 = [ P5 -- ]; + R3 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r1, 0x88898A8B; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0xA8A9AAAB; + CHECKREG r4, 0x15073233; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x28292A2B; + CHECKREG r7, 0x48494A4B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/tests/tcg/bfin/c_ldst_st_p_d_pp.s b/tests/tcg/bfin/c_ldst_st_p_d_pp.s new file mode 100644 index 0000000000000..05e96bcb558a6 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_d_pp.s @@ -0,0 +1,804 @@ +//Original:testcases/core/c_ldst_st_p_d_pp/c_ldst_st_p_d_pp.dsp +// Spec Reference: c_ldst st_p++ d +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + [ P5 ++ ] = R0; + [ P1 ++ ] = R1; + [ P2 ++ ] = R2; + [ P3 ++ ] = R3; + [ P4 ++ ] = R4; + [ FP ++ ] = R5; + [ SP ++ ] = R6; + + [ P5 ++ ] = R1; + [ P1 ++ ] = R2; + [ P2 ++ ] = R3; + [ P3 ++ ] = R4; + [ P4 ++ ] = R5; + [ FP ++ ] = R6; + [ SP ++ ] = R7; + + [ P5 ++ ] = R2; + [ P1 ++ ] = R3; + [ P2 ++ ] = R4; + [ P3 ++ ] = R5; + [ P4 ++ ] = R6; + [ FP ++ ] = R7; + [ SP ++ ] = R0; + + [ P5 ++ ] = R3; + [ P1 ++ ] = R4; + [ P2 ++ ] = R5; + [ P3 ++ ] = R6; + [ P4 ++ ] = R7; + [ FP ++ ] = R0; + [ SP ++ ] = R1; + + [ P5 ++ ] = R4; + [ P1 ++ ] = R5; + [ P2 ++ ] = R6; + [ P3 ++ ] = R7; + [ P4 ++ ] = R0; + [ FP ++ ] = R1; + [ SP ++ ] = R2; + + [ P5 ++ ] = R5; + [ P1 ++ ] = R6; + [ P2 ++ ] = R7; + [ P3 ++ ] = R0; + [ P4 ++ ] = R1; + [ FP ++ ] = R2; + [ SP ++ ] = R3; + + [ P5 ++ ] = R6; + [ P1 ++ ] = R7; + [ P2 ++ ] = R0; + [ P3 ++ ] = R1; + [ P4 ++ ] = R2; + [ FP ++ ] = R3; + [ SP ++ ] = R4; + + [ P5 ++ ] = R7; + [ P1 ++ ] = R0; + [ P2 ++ ] = R1; + [ P3 ++ ] = R2; + [ P4 ++ ] = R3; + [ FP ++ ] = R4; + [ SP ++ ] = R5; + +// Read back and check + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R2 = [ P3 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + R6 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x60897B6D; + CHECKREG r7, 0x719A8C7E; + + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R3 = [ P3 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + R7 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x1B342618; + CHECKREG r6, 0x60897B6D; + CHECKREG r7, 0x719A8C7E; + + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R4 = [ P3 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ P5 ++ ]; + R7 = [ FP ++ ]; + R0 = [ SP ++ ]; + CHECKREG r0, 0x0A231507; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x2C453729; + CHECKREG r7, 0x719A8C7E; + + R3 = [ P1 ++ ]; + R4 = [ P2 ++ ]; + R5 = [ P3 ++ ]; + R6 = [ P4 ++ ]; + R7 = [ P5 ++ ]; + R0 = [ FP ++ ]; + R1 = [ SP ++ ]; + CHECKREG r0, 0x0A231507; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x3D56483A; + + R4 = [ P1 ++ ]; + R5 = [ P2 ++ ]; + R6 = [ P3 ++ ]; + R7 = [ P4 ++ ]; + R0 = [ P5 ++ ]; + R1 = [ FP ++ ]; + R2 = [ SP ++ ]; + CHECKREG r0, 0x4E67594B; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x2C453729; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + + R5 = [ P1 ++ ]; + R6 = [ P2 ++ ]; + R7 = [ P3 ++ ]; + R0 = [ P4 ++ ]; + R1 = [ P5 ++ ]; + R2 = [ FP ++ ]; + R3 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x5F786A5C; + CHECKREG r2, 0x2C453729; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + + R6 = [ P1 ++ ]; + R7 = [ P2 ++ ]; + R0 = [ P3 ++ ]; + R1 = [ P4 ++ ]; + R2 = [ P5 ++ ]; + R3 = [ FP ++ ]; + R4 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x60897B6D; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x4E67594B; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + + R7 = [ P1 ++ ]; + R0 = [ P2 ++ ]; + R1 = [ P3 ++ ]; + R2 = [ P4 ++ ]; + R3 = [ P5 ++ ]; + R4 = [ FP ++ ]; + R5 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x719A8C7E; + CHECKREG r4, 0x4E67594B; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + +// reset values + imm32 r0, 0x1a235507; + imm32 r1, 0x12342518; + imm32 r2, 0x23353729; + imm32 r3, 0x3f54483a; + imm32 r4, 0x4467694b; + imm32 r5, 0x5ff86a5c; + imm32 r6, 0x608b7b1d; + imm32 r7, 0x719a8c71; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + [ P5 -- ] = R0; + [ P1 -- ] = R1; + [ P2 -- ] = R2; + [ P3 -- ] = R3; + [ P4 -- ] = R4; + [ FP -- ] = R5; + [ SP -- ] = R6; + + [ P5 -- ] = R1; + [ P1 -- ] = R2; + [ P2 -- ] = R3; + [ P3 -- ] = R4; + [ P4 -- ] = R5; + [ FP -- ] = R6; + [ SP -- ] = R7; + + [ P5 -- ] = R2; + [ P1 -- ] = R3; + [ P2 -- ] = R4; + [ P3 -- ] = R5; + [ P4 -- ] = R6; + [ FP -- ] = R7; + [ SP -- ] = R0; + + [ P5 -- ] = R3; + [ P1 -- ] = R4; + [ P2 -- ] = R5; + [ P3 -- ] = R6; + [ P4 -- ] = R7; + [ FP -- ] = R0; + [ SP -- ] = R1; + + [ P5 -- ] = R4; + [ P1 -- ] = R5; + [ P2 -- ] = R6; + [ P3 -- ] = R7; + [ P4 -- ] = R0; + [ FP -- ] = R1; + [ SP -- ] = R2; + + [ P5 -- ] = R5; + [ P1 -- ] = R6; + [ P2 -- ] = R7; + [ P3 -- ] = R0; + [ P4 -- ] = R1; + [ FP -- ] = R2; + [ SP -- ] = R3; + + [ P5 -- ] = R6; + [ P1 -- ] = R7; + [ P2 -- ] = R0; + [ P3 -- ] = R1; + [ P4 -- ] = R2; + [ FP -- ] = R3; + [ SP -- ] = R4; + + [ P5 -- ] = R7; + [ P1 -- ] = R0; + [ P2 -- ] = R1; + [ P3 -- ] = R2; + [ P4 -- ] = R3; + [ FP -- ] = R4; + [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x1A235507; + CHECKREG r5, 0x5FF86A5C; + CHECKREG r6, 0x608B7B1D; + CHECKREG r7, 0x719A8C71; + + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ P5 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x12342518; + CHECKREG r6, 0x608B7B1D; + CHECKREG r7, 0x719A8C71; + + R2 = [ P1 -- ]; + R3 = [ P2 -- ]; + R4 = [ P3 -- ]; + R5 = [ P4 -- ]; + R6 = [ P5 -- ]; + R7 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r0, 0x1A235507; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x23353729; + CHECKREG r7, 0x719A8C71; + + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r0, 0x1A235507; + CHECKREG r1, 0x12342518; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x3F54483A; + + R4 = [ P1 -- ]; + R5 = [ P2 -- ]; + R6 = [ P3 -- ]; + R7 = [ P4 -- ]; + R0 = [ P5 -- ]; + R1 = [ FP -- ]; + R2 = [ SP -- ]; + CHECKREG r0, 0x4467694B; + CHECKREG r1, 0x12342518; + CHECKREG r2, 0x23353729; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ P5 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x5FF86A5C; + CHECKREG r2, 0x23353729; + CHECKREG r3, 0x3F54483A; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + R6 = [ P1 -- ]; + R7 = [ P2 -- ]; + R0 = [ P3 -- ]; + R1 = [ P4 -- ]; + R2 = [ P5 -- ]; + R3 = [ FP -- ]; + R4 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x608B7B1D; + CHECKREG r3, 0x3F54483A; + CHECKREG r4, 0x4467694B; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + R7 = [ P1 -- ]; + R0 = [ P2 -- ]; + R1 = [ P3 -- ]; + R2 = [ P4 -- ]; + R3 = [ P5 -- ]; + R4 = [ FP -- ]; + R5 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x719A8C71; + CHECKREG r4, 0x4467694B; + CHECKREG r5, 0x5FF86A5C; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + P3 = I1; SP = I3; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/tests/tcg/bfin/c_ldst_st_p_d_pp_b.s b/tests/tcg/bfin/c_ldst_st_p_d_pp_b.s new file mode 100644 index 0000000000000..823aa9b55145f --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_d_pp_b.s @@ -0,0 +1,455 @@ +//Original:/testcases/core/c_ldst_st_p_d_pp_b/c_ldst_st_p_d_pp_b.dsp +// Spec Reference: c_ldst st_p++ b byte +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// store incremented by 1 loc + B [ P5 ++ ] = R0; + B [ P1 ++ ] = R1; + B [ P2 ++ ] = R2; + B [ P4 ++ ] = R4; + B [ FP ++ ] = R5; + + B [ P5 ++ ] = R1; + B [ P1 ++ ] = R2; + B [ P2 ++ ] = R3; + B [ P4 ++ ] = R5; + B [ FP ++ ] = R6; + + B [ P5 ++ ] = R2; + B [ P1 ++ ] = R3; + B [ P2 ++ ] = R4; + B [ P4 ++ ] = R6; + B [ FP ++ ] = R7; + + B [ P5 ++ ] = R3; + B [ P1 ++ ] = R4; + B [ P2 ++ ] = R5; + B [ P4 ++ ] = R7; + B [ FP ++ ] = R0; + + B [ P5 ++ ] = R4; + B [ P1 ++ ] = R5; + B [ P2 ++ ] = R6; + B [ P4 ++ ] = R0; + B [ FP ++ ] = R1; + + B [ P5 ++ ] = R5; + B [ P1 ++ ] = R6; + B [ P2 ++ ] = R7; + B [ P4 ++ ] = R1; + B [ FP ++ ] = R2; + + B [ P5 ++ ] = R6; + B [ P1 ++ ] = R7; + B [ P2 ++ ] = R0; + B [ P4 ++ ] = R2; + B [ FP ++ ] = R3; + + B [ P5 ++ ] = R7; + B [ P1 ++ ] = R0; + B [ P2 ++ ] = R1; + B [ P4 ++ ] = R3; + B [ FP ++ ] = R4; + +// Read back and check + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r0, 0x4B3A2918; + CHECKREG r1, 0x5C4B3A29; + CHECKREG r3, 0x7E6D5C4B; + CHECKREG r4, 0x3A291807; + CHECKREG r5, 0x077E6D5C; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + CHECKREG r0, 0x4B3A2918; + CHECKREG r1, 0x077E6D5C; + CHECKREG r2, 0x18077E6D; + CHECKREG r4, 0x3A291807; + CHECKREG r5, 0x7E6D5C4B; + CHECKREG r6, 0x4B3A2918; + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ P5 ++ ]; + R7 = [ FP ++ ]; + CHECKREG r1, 0x077E6D5C; + CHECKREG r2, 0x28292A2B; + CHECKREG r3, 0x48494A4B; + CHECKREG r5, 0x88898A8B; + CHECKREG r6, 0x08090A0B; + CHECKREG r7, 0xA8A9AAAB; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/tests/tcg/bfin/c_ldst_st_p_d_pp_h.s b/tests/tcg/bfin/c_ldst_st_p_d_pp_h.s new file mode 100644 index 0000000000000..c8b453a2106f0 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_d_pp_h.s @@ -0,0 +1,457 @@ +//Original:/testcases/core/c_ldst_st_p_d_pp_h/c_ldst_st_p_d_pp_h.dsp +// Spec Reference: c_ldst st_p++/p-- h half +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// half word 16-bit store incremented by 2 + W [ P5 ++ ] = R0; + W [ P1 ++ ] = R1; + W [ P2 ++ ] = R2; + W [ P4 ++ ] = R4; + W [ FP ++ ] = R5; + + W [ P5 ++ ] = R1; + W [ P1 ++ ] = R2; + W [ P2 ++ ] = R3; + W [ P4 ++ ] = R5; + W [ FP ++ ] = R6; + + W [ P5 ++ ] = R2; + W [ P1 ++ ] = R3; + W [ P2 ++ ] = R4; + W [ P4 ++ ] = R6; + W [ FP ++ ] = R7; + + W [ P5 ++ ] = R3; + W [ P1 ++ ] = R4; + W [ P2 ++ ] = R5; + W [ P4 ++ ] = R7; + W [ FP ++ ] = R0; + + W [ P5 ++ ] = R4; + W [ P1 ++ ] = R5; + W [ P2 ++ ] = R6; + W [ P4 ++ ] = R0; + W [ FP ++ ] = R1; + + W [ P5 ++ ] = R5; + W [ P1 ++ ] = R6; + W [ P2 ++ ] = R7; + W [ P4 ++ ] = R1; + W [ FP ++ ] = R2; + + W [ P5 ++ ] = R6; + W [ P1 ++ ] = R7; + W [ P2 ++ ] = R0; + W [ P4 ++ ] = R2; + W [ FP ++ ] = R3; + + W [ P5 ++ ] = R7; + W [ P1 ++ ] = R0; + W [ P2 ++ ] = R1; + W [ P4 ++ ] = R3; + W [ FP ++ ] = R4; + +// Read back and check + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r0, 0x37292618; + CHECKREG r1, 0x483A3729; + CHECKREG r3, 0x6A5C594B; + CHECKREG r4, 0x26181507; + CHECKREG r5, 0x7B6D6A5C; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + CHECKREG r0, 0x37292618; + CHECKREG r1, 0x594B483A; + CHECKREG r2, 0x6A5C594B; + CHECKREG r4, 0x8C7E7B6D; + CHECKREG r5, 0x483A3729; + CHECKREG r6, 0x15078C7E; + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ P5 ++ ]; + R7 = [ FP ++ ]; + CHECKREG r1, 0x594B483A; + CHECKREG r2, 0x7B6D6A5C; + CHECKREG r3, 0x8C7E7B6D; + CHECKREG r5, 0x26181507; + CHECKREG r6, 0x6A5C594B; + CHECKREG r7, 0x37292618; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/tests/tcg/bfin/c_ldst_st_p_p.s b/tests/tcg/bfin/c_ldst_st_p_p.s new file mode 100644 index 0000000000000..1cc87a1f8cb17 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_p.s @@ -0,0 +1,128 @@ +//Original:/testcases/core/c_ldst_st_p_p/c_ldst_st_p_p.dsp +// Spec Reference: c_ldst st_p_p +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values p-p + imm32 p5, 0x0a231507; + imm32 p1, 0x1b342618; + imm32 p2, 0x2c453729; + + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + [ P4 ] = P1; + [ FP ] = P2; + R5 = [ P4 ]; + R6 = [ FP ]; + CHECKREG r5, 0x1B342618; + CHECKREG r6, 0x2C453729; + + [ P4 ] = P2; + [ FP ] = R3; + R5 = [ P4 ]; + R6 = [ FP ]; + CHECKREG r5, 0x2C453729; + CHECKREG r6, 0x3D56483A; + + [ P4 ] = R3; + [ FP ] = P5; + R5 = [ P4 ]; + R6 = [ FP ]; + CHECKREG r5, 0x3D56483A; + CHECKREG r6, 0x0A231507; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldst_st_p_p_mm.s b/tests/tcg/bfin/c_ldst_st_p_p_mm.s new file mode 100644 index 0000000000000..e7dd3cdf866e0 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_p_mm.s @@ -0,0 +1,428 @@ +//Original:testcases/core/c_ldst_st_p_p_mm/c_ldst_st_p_p_mm.dsp +// Spec Reference: c_ldst st p-- p +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values p-p + imm32 p5, 0x0a231507; + imm32 p1, 0x1b342618; + imm32 p2, 0x2c453729; + imm32 p3, 0x4356789a; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_5, 0x18; + loadsym fp, DATA_ADDR_6, 0x18; + loadsym i3, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + [ P4 -- ] = P1; + [ FP -- ] = P2; + [ SP -- ] = R3; + + [ P4 -- ] = P2; + [ FP -- ] = P3; + [ SP -- ] = P5; + + [ P4 -- ] = P3; + [ FP -- ] = P5; + [ SP -- ] = P1; + + [ P4 -- ] = P5; + [ FP -- ] = P1; + [ SP -- ] = P2; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_5, 0x18; + loadsym fp, DATA_ADDR_6, 0x18; + loadsym i3, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + R1 = [ P4 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + R4 = [ P4 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x2C453729; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x4356789A; + CHECKREG r6, 0x0A231507; + R1 = [ P4 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + R4 = [ P4 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x4356789A; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x1B342618; + CHECKREG r6, 0x2C453729; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x10000080 + .dd 0x02000800 + .dd 0x00207000 + .dd 0x000d0000 + .dd 0x0006b000 + .dd 0x00500a00 + .dd 0x0d0000f0 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x10006000 + .dd 0xa2050800 + .dd 0x0c30db00 + .dd 0x00b40000 + .dd 0xa0045000 + .dd 0x0000f600 + .dd 0x00d00070 + .dd 0x00000008 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x10000000 + .dd 0x0d000000 + .dd 0x00400000 + .dd 0x000b0000 + .dd 0x000d0b00 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/tests/tcg/bfin/c_ldst_st_p_p_pp.s b/tests/tcg/bfin/c_ldst_st_p_p_pp.s new file mode 100644 index 0000000000000..c8068deb67d58 --- /dev/null +++ b/tests/tcg/bfin/c_ldst_st_p_p_pp.s @@ -0,0 +1,397 @@ +//Original:/testcases/core/c_ldst_st_p_p_pp/c_ldst_st_p_p_pp.dsp +// Spec Reference: c_ldst st p++ p +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values p-p + imm32 p5, 0x0a231507; + imm32 p1, 0x1b342618; + imm32 p2, 0x2c453729; + imm32 p0, 0x125afbd3; + + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + [ P4 ++ ] = P1; + [ FP ++ ] = P2; + + [ P4 ++ ] = P2; + [ FP ++ ] = P0; + + [ P4 ++ ] = P0; + [ FP ++ ] = P5; + + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + R1 = [ P4 ++ ]; + R2 = [ FP ++ ]; + R4 = [ P4 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x2C453729; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x125AFBD3; + R1 = [ P4 ++ ]; + R2 = [ FP ++ ]; + R4 = [ P4 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r1, 0x125AFBD3; + CHECKREG r2, 0x0A231507; + CHECKREG r4, 0x8C8D8E8F; + CHECKREG r5, 0xACADAEAF; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/tests/tcg/bfin/c_ldstidxl_ld_dr_b.s b/tests/tcg/bfin/c_ldstidxl_ld_dr_b.s new file mode 100644 index 0000000000000..74b4222c01bb5 --- /dev/null +++ b/tests/tcg/bfin/c_ldstidxl_ld_dr_b.s @@ -0,0 +1,554 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_b/c_ldstidxl_ld_dr_b.dsp +// Spec Reference: c_ldstidxl load dreg B (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; + +// initial values + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + + R0 = B [ P1 + 151 ] (Z); + R1 = B [ P1 + 83 ] (Z); + R2 = B [ P1 + 45 ] (Z); + R3 = B [ P1 + 17 ] (Z); + R4 = B [ P1 + 39 ] (Z); + R5 = B [ P1 + 21 ] (Z); + R6 = B [ P1 + 123 ] (Z); + R7 = B [ P1 + 155 ] (Z); + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000018; + CHECKREG r2, 0x00000076; + CHECKREG r3, 0x00000012; + CHECKREG r4, 0x00000055; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000058; + CHECKREG r7, 0x00000004; + + R0 = B [ P2 + -121 ] (Z); + R1 = B [ P2 + -113 ] (Z); + R2 = B [ P2 + -35 ] (Z); + R3 = B [ P2 + -27 ] (Z); + R4 = B [ P2 + -49 ] (Z); + R5 = B [ P2 + -5 ] (Z); + R6 = B [ P2 + -51 ] (Z); + R7 = B [ P2 + -147 ] (Z); + CHECKREG r0, 0x000000CF; + CHECKREG r1, 0x000000D7; + CHECKREG r2, 0x00000056; + CHECKREG r3, 0x00000064; + CHECKREG r4, 0x00000094; + CHECKREG r5, 0x0000004C; + CHECKREG r6, 0x00000099; + CHECKREG r7, 0x0000004E; + + R0 = B [ P4 + 47 ] (Z); + R1 = B [ P4 + -41 ] (Z); + R2 = B [ P4 + 38 ] (Z); + R3 = B [ P4 + -31 ] (Z); + R4 = B [ P4 + 28 ] (Z); + R5 = B [ P4 + 26 ] (Z); + R6 = B [ P4 + -22 ] (Z); + R7 = B [ P4 + 105 ] (Z); + CHECKREG r0, 0x00000050; + CHECKREG r1, 0x00000093; + CHECKREG r2, 0x00000049; + CHECKREG r3, 0x00000099; + CHECKREG r4, 0x00000043; + CHECKREG r5, 0x00000067; + CHECKREG r6, 0x000000E8; + CHECKREG r7, 0x00000099; + + R0 = B [ P5 + -14 ] (Z); + R1 = B [ P5 + 12 ] (Z); + R2 = B [ P5 + -6 ] (Z); + R3 = B [ P5 + 4 ] (Z); + R4 = B [ P5 + 0 ] (Z); + R5 = B [ P5 + -2 ] (Z); + R6 = B [ P5 + 8 ] (Z); + R7 = B [ P5 + -107 ] (Z); + CHECKREG r0, 0x00000035; + CHECKREG r1, 0x00000065; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000057; + CHECKREG r4, 0x00000053; + CHECKREG r5, 0x00000047; + CHECKREG r6, 0x00000061; + CHECKREG r7, 0x00000006; + + R0 = B [ FP + 99 ] (Z); + R1 = B [ FP + -15 ] (Z); + R2 = B [ FP + 41 ] (Z); + R3 = B [ FP + -65 ] (Z); + R4 = B [ FP + 25 ] (Z); + R5 = B [ FP + -34 ] (Z); + R6 = B [ FP + 37 ] (Z); + R7 = B [ FP + -97 ] (Z); + CHECKREG r0, 0x00000093; + CHECKREG r1, 0x00000099; + CHECKREG r2, 0x0000004E; + CHECKREG r3, 0x000000D7; + CHECKREG r4, 0x00000068; + CHECKREG r5, 0x000000E8; + CHECKREG r6, 0x0000004A; + CHECKREG r7, 0x0000004C; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstidxl_ld_dr_h.s b/tests/tcg/bfin/c_ldstidxl_ld_dr_h.s new file mode 100644 index 0000000000000..334ad17a11e6a --- /dev/null +++ b/tests/tcg/bfin/c_ldstidxl_ld_dr_h.s @@ -0,0 +1,595 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_h/c_ldstidxl_ld_dr_h.dsp +// Spec Reference: c_ldstidxl load dreg H (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + R0 = W [ P1 + 154 ] (Z); + R1 = W [ P1 + 84 ] (Z); + R2 = W [ P1 + 48 ] (Z); + R3 = W [ P1 + 10 ] (Z); + R4 = W [ P1 + 34 ] (Z); + R5 = W [ P1 + 20 ] (Z); + R6 = W [ P1 + 126 ] (Z); + R7 = W [ P1 + 154 ] (Z); + CHECKREG r0, 0x00000405; + CHECKREG r1, 0x00002425; + CHECKREG r2, 0x00008485; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00001122; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00006263; + CHECKREG r7, 0x00000405; + + R0 = W [ P2 + -120 ] (Z); + R1 = W [ P2 + -114 ] (Z); + R2 = W [ P2 + -36 ] (Z); + R3 = W [ P2 + -22 ] (Z); + R4 = W [ P2 + -44 ] (Z); + R5 = W [ P2 + -6 ] (Z); + R6 = W [ P2 + -52 ] (Z); + R7 = W [ P2 + -146 ] (Z); + CHECKREG r0, 0x0000D5D6; + CHECKREG r1, 0x0000D7D8; + CHECKREG r2, 0x0000565A; + CHECKREG r3, 0x0000A667; + CHECKREG r4, 0x000099EA; + CHECKREG r5, 0x00004C4D; + CHECKREG r6, 0x000099EA; + CHECKREG r7, 0x00004C4D; + + R0 = W [ P3 + 56 ] (Z); + R1 = W [ P3 + 62 ] (Z); + R2 = W [ P3 + -64 ] (Z); + R3 = W [ P3 + 60 ] (Z); + R4 = W [ P3 + -56 ] (Z); + R5 = W [ P3 + 10 ] (Z); + R6 = W [ P3 + -28 ] (Z); + R7 = W [ P3 + -110 ] (Z); + CHECKREG r0, 0x00001617; + CHECKREG r1, 0x00001819; + CHECKREG r2, 0x00008485; + CHECKREG r3, 0x00001A1B; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00005859; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00000001; + + R0 = W [ P4 + 42 ] (Z); + R1 = W [ P4 + -40 ] (Z); + R2 = W [ P4 + 38 ] (Z); + R3 = W [ P4 + -32 ] (Z); + R4 = W [ P4 + 28 ] (Z); + R5 = W [ P4 + 26 ] (Z); + R6 = W [ P4 + -22 ] (Z); + R7 = W [ P4 + 106 ] (Z); + CHECKREG r0, 0x00004C4D; + CHECKREG r1, 0x000099EA; + CHECKREG r2, 0x00004849; + CHECKREG r3, 0x000099EA; + CHECKREG r4, 0x00004243; + CHECKREG r5, 0x0000A667; + CHECKREG r6, 0x000098E8; + CHECKREG r7, 0x000095E8; + + R0 = W [ P5 + -14 ] (Z); + R1 = W [ P5 + 12 ] (Z); + R2 = W [ P5 + -6 ] (Z); + R3 = W [ P5 + 4 ] (Z); + R4 = W [ P5 + 0 ] (Z); + R5 = W [ P5 + -2 ] (Z); + R6 = W [ P5 + 8 ] (Z); + R7 = W [ P5 + -108 ] (Z); + CHECKREG r0, 0x00003435; + CHECKREG r1, 0x00006465; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00005657; + CHECKREG r4, 0x00005253; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00006061; + CHECKREG r7, 0x00000607; + + R0 = W [ FP + 90 ] (Z); + R1 = W [ FP + -14 ] (Z); + R2 = W [ FP + 42 ] (Z); + R3 = W [ FP + -66 ] (Z); + R4 = W [ FP + 26 ] (Z); + R5 = W [ FP + -34 ] (Z); + R6 = W [ FP + 38 ] (Z); + R7 = W [ FP + -98 ] (Z); + CHECKREG r0, 0x000091E8; + CHECKREG r1, 0x000091E8; + CHECKREG r2, 0x00004C4D; + CHECKREG r3, 0x0000D7D8; + CHECKREG r4, 0x0000A667; + CHECKREG r5, 0x000095E8; + CHECKREG r6, 0x00004849; + CHECKREG r7, 0x00004C4D; + + R0 = W [ SP + 46 ] (Z); + R1 = W [ SP + -42 ] (Z); + R2 = W [ SP + 48 ] (Z); + R3 = W [ SP + 50 ] (Z); + R4 = W [ SP + -102 ] (Z); + R5 = W [ SP + 82 ] (Z); + R6 = W [ SP + 62 ] (Z); + R7 = W [ SP + 46 ] (Z); + CHECKREG r0, 0x00000809; + CHECKREG r1, 0x00000506; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000C0D; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0x00007475; + CHECKREG r6, 0x00001819; + CHECKREG r7, 0x00000809; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstidxl_ld_dr_xb.s b/tests/tcg/bfin/c_ldstidxl_ld_dr_xb.s new file mode 100644 index 0000000000000..e5a3515eec0b2 --- /dev/null +++ b/tests/tcg/bfin/c_ldstidxl_ld_dr_xb.s @@ -0,0 +1,594 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_xb/c_ldstidxl_ld_dr_xb.dsp +// Spec Reference: c_ldstidxl load dreg XB (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + R0 = B [ P1 + 151 ] (X); + R1 = B [ P1 + 83 ] (X); + R2 = B [ P1 + 45 ] (X); + R3 = B [ P1 + 17 ] (X); + R4 = B [ P1 + 39 ] (X); + R5 = B [ P1 + 21 ] (X); + R6 = B [ P1 + 123 ] (X); + R7 = B [ P1 + 155 ] (X); + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000018; + CHECKREG r2, 0x00000076; + CHECKREG r3, 0x00000012; + CHECKREG r4, 0x00000055; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000058; + CHECKREG r7, 0x00000004; + + R0 = B [ P2 + -121 ] (X); + R1 = B [ P2 + -113 ] (X); + R2 = B [ P2 + -35 ] (X); + R3 = B [ P2 + -27 ] (X); + R4 = B [ P2 + -49 ] (X); + R5 = B [ P2 + -5 ] (X); + R6 = B [ P2 + -51 ] (X); + R7 = B [ P2 + -147 ] (X); + CHECKREG r0, 0xFFFFFFCF; + CHECKREG r1, 0xFFFFFFD7; + CHECKREG r2, 0x00000056; + CHECKREG r3, 0x00000064; + CHECKREG r4, 0xFFFFFF94; + CHECKREG r5, 0x0000004C; + CHECKREG r6, 0xFFFFFF99; + CHECKREG r7, 0x0000004E; + + R0 = B [ P3 + 56 ] (X); + R1 = B [ P3 + 62 ] (X); + R2 = B [ P3 + -63 ] (X); + R3 = B [ P3 + 61 ] (X); + R4 = B [ P3 + -59 ] (X); + R5 = B [ P3 + 11 ] (X); + R6 = B [ P3 + -23 ] (X); + R7 = B [ P3 + -111 ] (X); + CHECKREG r0, 0x00000017; + CHECKREG r1, 0x00000019; + CHECKREG r2, 0xFFFFFF84; + CHECKREG r3, 0x0000001A; + CHECKREG r4, 0xFFFFFF88; + CHECKREG r5, 0x00000058; + CHECKREG r6, 0x00000028; + CHECKREG r7, 0x00000002; + + R0 = B [ P4 + 47 ] (X); + R1 = B [ P4 + -41 ] (X); + R2 = B [ P4 + 38 ] (X); + R3 = B [ P4 + -31 ] (X); + R4 = B [ P4 + 28 ] (X); + R5 = B [ P4 + 26 ] (X); + R6 = B [ P4 + -22 ] (X); + R7 = B [ P4 + 105 ] (X); + CHECKREG r0, 0x00000050; + CHECKREG r1, 0xFFFFFF93; + CHECKREG r2, 0x00000049; + CHECKREG r3, 0xFFFFFF99; + CHECKREG r4, 0x00000043; + CHECKREG r5, 0x00000067; + CHECKREG r6, 0xFFFFFFE8; + CHECKREG r7, 0xFFFFFF99; + + R0 = B [ P5 + -14 ] (X); + R1 = B [ P5 + 12 ] (X); + R2 = B [ P5 + -6 ] (X); + R3 = B [ P5 + 4 ] (X); + R4 = B [ P5 + 0 ] (X); + R5 = B [ P5 + -2 ] (X); + R6 = B [ P5 + 8 ] (X); + R7 = B [ P5 + -107 ] (X); + CHECKREG r0, 0x00000035; + CHECKREG r1, 0x00000065; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000057; + CHECKREG r4, 0x00000053; + CHECKREG r5, 0x00000047; + CHECKREG r6, 0x00000061; + CHECKREG r7, 0x00000006; + + R0 = B [ FP + 99 ] (X); + R1 = B [ FP + -15 ] (X); + R2 = B [ FP + 41 ] (X); + R3 = B [ FP + -65 ] (X); + R4 = B [ FP + 25 ] (X); + R5 = B [ FP + -34 ] (X); + R6 = B [ FP + 37 ] (X); + R7 = B [ FP + -97 ] (X); + CHECKREG r0, 0xFFFFFF93; + CHECKREG r1, 0xFFFFFF99; + CHECKREG r2, 0x0000004E; + CHECKREG r3, 0xFFFFFFD7; + CHECKREG r4, 0x00000068; + CHECKREG r5, 0xFFFFFFE8; + CHECKREG r6, 0x0000004A; + CHECKREG r7, 0x0000004C; + + R0 = B [ SP + 46 ] (X); + R1 = B [ SP + -41 ] (X); + R2 = B [ SP + 48 ] (X); + R3 = B [ SP + 51 ] (X); + R4 = B [ SP + -102 ] (X); + R5 = B [ SP + 89 ] (X); + R6 = B [ SP + 62 ] (X); + R7 = B [ SP + 43 ] (X); + CHECKREG r0, 0x00000009; + CHECKREG r1, 0x00000005; + CHECKREG r2, 0x0000000F; + CHECKREG r3, 0x0000000C; + CHECKREG r4, 0x00000009; + CHECKREG r5, 0xFFFFFF88; + CHECKREG r6, 0x00000019; + CHECKREG r7, 0x00000004; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstidxl_ld_dr_xh.s b/tests/tcg/bfin/c_ldstidxl_ld_dr_xh.s new file mode 100644 index 0000000000000..7d1dda1537b8b --- /dev/null +++ b/tests/tcg/bfin/c_ldstidxl_ld_dr_xh.s @@ -0,0 +1,595 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_xh/c_ldstidxl_ld_dr_xh.dsp +// Spec Reference: c_ldstidxl load dreg XH (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + R0 = W [ P1 + 154 ] (X); + R1 = W [ P1 + 84 ] (X); + R2 = W [ P1 + 48 ] (X); + R3 = W [ P1 + 10 ] (X); + R4 = W [ P1 + 34 ] (X); + R5 = W [ P1 + 20 ] (X); + R6 = W [ P1 + 126 ] (X); + R7 = W [ P1 + 154 ] (X); + CHECKREG r0, 0x00000405; + CHECKREG r1, 0x00002425; + CHECKREG r2, 0xFFFF8485; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00001122; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00006263; + CHECKREG r7, 0x00000405; + + R0 = W [ P2 + -120 ] (X); + R1 = W [ P2 + -114 ] (X); + R2 = W [ P2 + -36 ] (X); + R3 = W [ P2 + -22 ] (X); + R4 = W [ P2 + -44 ] (X); + R5 = W [ P2 + -6 ] (X); + R6 = W [ P2 + -52 ] (X); + R7 = W [ P2 + -146 ] (X); + CHECKREG r0, 0xFFFFD5D6; + CHECKREG r1, 0xFFFFD7D8; + CHECKREG r2, 0x0000565A; + CHECKREG r3, 0xFFFFA667; + CHECKREG r4, 0xFFFF99EA; + CHECKREG r5, 0x00004C4D; + CHECKREG r6, 0xFFFF99EA; + CHECKREG r7, 0x00004C4D; + + R0 = W [ P3 + 56 ] (X); + R1 = W [ P3 + 62 ] (X); + R2 = W [ P3 + -64 ] (X); + R3 = W [ P3 + 60 ] (X); + R4 = W [ P3 + -56 ] (X); + R5 = W [ P3 + 10 ] (X); + R6 = W [ P3 + -28 ] (X); + R7 = W [ P3 + -110 ] (X); + CHECKREG r0, 0x00001617; + CHECKREG r1, 0x00001819; + CHECKREG r2, 0xFFFF8485; + CHECKREG r3, 0x00001A1B; + CHECKREG r4, 0xFFFF8283; + CHECKREG r5, 0x00005859; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00000001; + + R0 = W [ P4 + 42 ] (X); + R1 = W [ P4 + -40 ] (X); + R2 = W [ P4 + 38 ] (X); + R3 = W [ P4 + -32 ] (X); + R4 = W [ P4 + 28 ] (X); + R5 = W [ P4 + 26 ] (X); + R6 = W [ P4 + -22 ] (X); + R7 = W [ P4 + 106 ] (X); + CHECKREG r0, 0x00004C4D; + CHECKREG r1, 0xFFFF99EA; + CHECKREG r2, 0x00004849; + CHECKREG r3, 0xFFFF99EA; + CHECKREG r4, 0x00004243; + CHECKREG r5, 0xFFFFA667; + CHECKREG r6, 0xFFFF98E8; + CHECKREG r7, 0xFFFF95E8; + + R0 = W [ P5 + -14 ] (X); + R1 = W [ P5 + 12 ] (X); + R2 = W [ P5 + -6 ] (X); + R3 = W [ P5 + 4 ] (X); + R4 = W [ P5 + 0 ] (X); + R5 = W [ P5 + -2 ] (X); + R6 = W [ P5 + 8 ] (X); + R7 = W [ P5 + -108 ] (X); + CHECKREG r0, 0x00003435; + CHECKREG r1, 0x00006465; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00005657; + CHECKREG r4, 0x00005253; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00006061; + CHECKREG r7, 0x00000607; + + R0 = W [ FP + 90 ] (X); + R1 = W [ FP + -14 ] (X); + R2 = W [ FP + 42 ] (X); + R3 = W [ FP + -66 ] (X); + R4 = W [ FP + 26 ] (X); + R5 = W [ FP + -34 ] (X); + R6 = W [ FP + 38 ] (X); + R7 = W [ FP + -98 ] (X); + CHECKREG r0, 0xFFFF91E8; + CHECKREG r1, 0xFFFF91E8; + CHECKREG r2, 0x00004C4D; + CHECKREG r3, 0xFFFFD7D8; + CHECKREG r4, 0xFFFFA667; + CHECKREG r5, 0xFFFF95E8; + CHECKREG r6, 0x00004849; + CHECKREG r7, 0x00004C4D; + + R0 = W [ SP + 46 ] (X); + R1 = W [ SP + -42 ] (X); + R2 = W [ SP + 48 ] (X); + R3 = W [ SP + 50 ] (X); + R4 = W [ SP + -102 ] (X); + R5 = W [ SP + 82 ] (X); + R6 = W [ SP + 62 ] (X); + R7 = W [ SP + 46 ] (X); + CHECKREG r0, 0x00000809; + CHECKREG r1, 0x00000506; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000C0D; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0x00007475; + CHECKREG r6, 0x00001819; + CHECKREG r7, 0x00000809; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstidxl_ld_dreg.s b/tests/tcg/bfin/c_ldstidxl_ld_dreg.s new file mode 100644 index 0000000000000..4c2509965967d --- /dev/null +++ b/tests/tcg/bfin/c_ldstidxl_ld_dreg.s @@ -0,0 +1,554 @@ +//Original:testcases/core/c_ldstidxl_ld_dreg/c_ldstidxl_ld_dreg.dsp +// Spec Reference: c_ldstidxl load dreg (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; + +// initial values + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + + R0 = [ P1 + 156 ]; + R1 = [ P1 + 84 ]; + R2 = [ P1 + 48 ]; + R3 = [ P1 + 12 ]; + R4 = [ P1 + 36 ]; + R5 = [ P1 + 20 ]; + R6 = [ P1 + 128 ]; + R7 = [ P1 + 156 ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x22232425; + CHECKREG r2, 0x82838485; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x55667788; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x66676869; + CHECKREG r7, 0x08090A0B; + + R0 = [ P2 + -120 ]; + R1 = [ P2 + -112 ]; + R2 = [ P2 + -36 ]; + R3 = [ P2 + -24 ]; + R4 = [ P2 + -44 ]; + R5 = [ P2 + -8 ]; + R6 = [ P2 + -52 ]; + R7 = [ P2 + -148 ]; + CHECKREG r0, 0xD3D4D5D6; + CHECKREG r1, 0xDBDCDDDE; + CHECKREG r2, 0xA455565A; + CHECKREG r3, 0xA667686A; + CHECKREG r4, 0x96E899EA; + CHECKREG r5, 0x4C4D4E4F; + CHECKREG r6, 0x94E899EA; + CHECKREG r7, 0x4C4D4E4F; + + R0 = [ P4 + 44 ]; + R1 = [ P4 + -40 ]; + R2 = [ P4 + 36 ]; + R3 = [ P4 + -32 ]; + R4 = [ P4 + 28 ]; + R5 = [ P4 + 24 ]; + R6 = [ P4 + -20 ]; + R7 = [ P4 + 108 ]; + CHECKREG r0, 0x50515253; + CHECKREG r1, 0x94E899EA; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x96E899EA; + CHECKREG r4, 0x40414243; + CHECKREG r5, 0xA667686A; + CHECKREG r6, 0x99E899EA; + CHECKREG r7, 0x96E899EA; + + R0 = [ P5 + -16 ]; + R1 = [ P5 + 12 ]; + R2 = [ P5 + -8 ]; + R3 = [ P5 + 4 ]; + R4 = [ P5 + 0 ]; + R5 = [ P5 + -4 ]; + R6 = [ P5 + 8 ]; + R7 = [ P5 + -108 ]; + CHECKREG r0, 0x34353637; + CHECKREG r1, 0x62636465; + CHECKREG r2, 0x42434445; + CHECKREG r3, 0x54555657; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x46474849; + CHECKREG r6, 0x58596061; + CHECKREG r7, 0x04050607; + + R0 = [ FP + 92 ]; + R1 = [ FP + -16 ]; + R2 = [ FP + 40 ]; + R3 = [ FP + -64 ]; + R4 = [ FP + 28 ]; + R5 = [ FP + -32 ]; + R6 = [ FP + 36 ]; + R7 = [ FP + -96 ]; + CHECKREG r0, 0x92E899EA; + CHECKREG r1, 0x91E899EA; + CHECKREG r2, 0x4C4D4E4F; + CHECKREG r3, 0xDBDCDDDE; + CHECKREG r4, 0x40414243; + CHECKREG r5, 0x96E899EA; + CHECKREG r6, 0x48494A4B; + CHECKREG r7, 0x50515253; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstidxl_ld_preg.s b/tests/tcg/bfin/c_ldstidxl_ld_preg.s new file mode 100644 index 0000000000000..503c24e6a9742 --- /dev/null +++ b/tests/tcg/bfin/c_ldstidxl_ld_preg.s @@ -0,0 +1,672 @@ +//Original:testcases/core/c_ldstidxl_ld_preg/c_ldstidxl_ld_preg.dsp +// Spec Reference: c_ldstidxl load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + P2 = [ P1 + 12 ]; + P3 = [ P1 + 44 ]; + P4 = [ P1 + 8 ]; + P5 = [ P1 + 156 ]; + SP = [ P1 + 16 ]; + FP = [ P1 + 120 ]; + P1 = [ P1 + 24 ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x0C0D0E0F; + CHECKREG p3, 0x74757677; + CHECKREG p4, 0x08090A0B; + CHECKREG p5, 0x08090A0B; + CHECKREG sp, 0x10111213; + CHECKREG fp, 0x58596061; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0xA0; + P3 = I1; SP = I3; + + P1 = [ P2 + -128 ]; + P3 = [ P2 + -36 ]; + P4 = [ P2 + -40 ]; + P5 = [ P2 + -144 ]; + SP = [ P2 + -48 ]; + FP = [ P2 + 52 ]; + P2 = [ P2 + -132 ]; + CHECKREG p1, 0xEBECEDEE; + CHECKREG p2, 0x7C7D7E7F; + CHECKREG p3, 0xA60CAD7E; + CHECKREG p4, 0xA50CAD6E; + CHECKREG p5, 0x70717273; + CHECKREG sp, 0xA30CAD4E; + CHECKREG fp, 0x64656667; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + P1 = [ P3 + 56 ]; + P2 = [ P3 + -104 ]; + P4 = [ P3 + 80 ]; + P5 = [ P3 + -56 ]; + SP = [ P3 + 52 ]; + FP = [ P3 + -48 ]; + P3 = [ P3 + 84 ]; + CHECKREG p1, 0x14151617; + CHECKREG p2, 0x08090A0B; + CHECKREG p3, 0x82838485; + CHECKREG p4, 0x74757677; + CHECKREG p5, 0x80818283; + CHECKREG sp, 0x10111213; + CHECKREG fp, 0x01020304; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_2, 0x70; + P3 = I1; SP = I3; + P1 = [ P4 + 44 ]; + P2 = [ P4 + -40 ]; + P3 = [ P4 + -96 ]; + P5 = [ P4 + -68 ]; + SP = [ P4 + 84 ]; + FP = [ P4 + 108 ]; + P4 = [ P4 + -32 ]; + CHECKREG p1, 0x6C6D6E6F; + CHECKREG p2, 0xAB0CAD03; + CHECKREG p3, 0x70717273; + CHECKREG p4, 0xAB0CAD05; + CHECKREG p5, 0xFBFCFDFE; + CHECKREG sp, 0x03040506; + CHECKREG fp, 0x6C6D6E6F; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + P1 = [ P5 + 16 ]; + P2 = [ P5 + 12 ]; + P3 = [ P5 + 96 ]; + P4 = [ P5 + 0 ]; + SP = [ P5 + -44 ]; + FP = [ P5 + 28 ]; + P5 = [ P5 + -84 ]; + CHECKREG p1, 0x66676869; + CHECKREG p2, 0x62636465; + CHECKREG p3, 0x84858687; + CHECKREG p4, 0x50515253; + CHECKREG p5, 0x1C1D1E1F; + CHECKREG sp, 0x05060708; + CHECKREG fp, 0x72636467; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_2, 0x70; + P3 = I1; SP = I3; + + P1 = [ SP + -72 ]; + P2 = [ SP + 16 ]; + P3 = [ SP + -80 ]; + P4 = [ SP + 92 ]; + P5 = [ SP + -28 ]; + FP = [ SP + 32 ]; + SP = [ SP + -36 ]; + CHECKREG p1, 0xF7F8F9FA; + CHECKREG p2, 0xB455565B; + CHECKREG p3, 0xEBECEDEE; + CHECKREG p4, 0x0B0CAD0E; + CHECKREG p5, 0xAB0CAD06; + CHECKREG sp, 0xAB0CAD04; + CHECKREG fp, 0x60616263; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_2, 0x70; + P3 = I1; SP = I3; + + P1 = [ FP + 40 ]; + P2 = [ FP + 44 ]; + P3 = [ FP + 96 ]; + P4 = [ FP + 52 ]; + P5 = [ FP + 104 ]; + SP = [ FP + 60 ]; + FP = [ FP + 64 ]; + CHECKREG p1, 0x68696A6B; + CHECKREG p2, 0x6C6D6E6F; + CHECKREG p3, 0x60616263; + CHECKREG p4, 0x74757677; + CHECKREG p5, 0x68696A6B; + CHECKREG sp, 0x7C7D7E7F; + CHECKREG fp, 0xEBECEDEE; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xa667686a + +DATA_ADDR_2: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstidxl_st_dr_b.s b/tests/tcg/bfin/c_ldstidxl_st_dr_b.s new file mode 100644 index 0000000000000..5ed1a119b1cb2 --- /dev/null +++ b/tests/tcg/bfin/c_ldstidxl_st_dr_b.s @@ -0,0 +1,612 @@ +//Original:testcases/core/c_ldstidxl_st_dr_b/c_ldstidxl_st_dr_b.dsp +// Spec Reference: c_ldstidxl store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f5080; + imm32 r1, 0x204e6091; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80b3; + imm32 r4, 0x501b90c4; + imm32 r5, 0x600aa0d5; + imm32 r6, 0x7019b0e6; + imm32 r7, 0xd028c0f7; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xc8; + loadsym i1, DATA_ADDR_1, 0x10; + loadsym p4, DATA_ADDR_2, 0xc8; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym fp, DATA_ADDR_2, 0xc8; + loadsym i3, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + B [ P1 + 0x1101 ] = R0; + B [ P1 + 0x1013 ] = R1; + B [ P1 + 0x1015 ] = R2; + B [ P1 + 0x1007 ] = R3; + B [ P2 + -0x1019 ] = R4; + B [ P2 + -0x1011 ] = R5; + B [ P2 + -0x1013 ] = R6; + B [ P2 + -0x1015 ] = R7; + R6 = B [ P1 + 0x1101 ] (Z); + R5 = B [ P1 + 0x1013 ] (Z); + R4 = B [ P1 + 0x1015 ] (Z); + R3 = B [ P1 + 0x1007 ] (Z); + R2 = B [ P2 + -0x1019 ] (Z); + R7 = B [ P2 + -0x1011 ] (Z); + R0 = B [ P2 + -0x1013 ] (Z); + R1 = B [ P2 + -0x1015 ] (Z); + CHECKREG r0, 0x000000E6; + CHECKREG r1, 0x000000F7; + CHECKREG r2, 0x000000C4; + CHECKREG r3, 0x000000B3; + CHECKREG r4, 0x000000A2; + CHECKREG r5, 0x00000091; + CHECKREG r6, 0x00000080; + CHECKREG r7, 0x000000D5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + B [ P3 + 0x1011 ] = R0; + B [ P3 + 0x1023 ] = R1; + B [ P3 + 0x1025 ] = R2; + B [ P3 + 0x1027 ] = R3; + B [ P4 + -0x1029 ] = R4; + B [ P4 + -0x1021 ] = R5; + B [ P4 + -0x1033 ] = R6; + B [ P4 + -0x1035 ] = R7; + R3 = B [ P3 + 0x1011 ] (Z); + R4 = B [ P3 + 0x1023 ] (Z); + R0 = B [ P3 + 0x1025 ] (Z); + R1 = B [ P3 + 0x1027 ] (Z); + R2 = B [ P4 + -0x1029 ] (Z); + R5 = B [ P4 + -0x1021 ] (Z); + R6 = B [ P4 + -0x1033 ] (Z); + R7 = B [ P4 + -0x1035 ] (Z); + CHECKREG r0, 0x000000B2; + CHECKREG r1, 0x000000B3; + CHECKREG r2, 0x000000B4; + CHECKREG r3, 0x000000B0; + CHECKREG r4, 0x000000B1; + CHECKREG r5, 0x000000B5; + CHECKREG r6, 0x000000B6; + CHECKREG r7, 0x000000B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + B [ P5 + 0x1031 ] = R0; + B [ P5 + 0x1033 ] = R1; + B [ P5 + 0x1035 ] = R2; + B [ P5 + 0x1047 ] = R3; + B [ SP + -0x1049 ] = R4; + B [ SP + -0x1041 ] = R5; + B [ SP + -0x1043 ] = R6; + B [ SP + -0x1045 ] = R7; + R6 = B [ P5 + 0x1031 ] (Z); + R5 = B [ P5 + 0x1033 ] (Z); + R4 = B [ P5 + 0x1035 ] (Z); + R3 = B [ P5 + 0x1047 ] (Z); + R2 = B [ SP + -0x1049 ] (Z); + R0 = B [ SP + -0x1041 ] (Z); + R7 = B [ SP + -0x1043 ] (Z); + R1 = B [ SP + -0x1045 ] (Z); + CHECKREG r0, 0x000000C5; + CHECKREG r1, 0x000000C7; + CHECKREG r2, 0x000000C4; + CHECKREG r3, 0x000000C3; + CHECKREG r4, 0x000000C2; + CHECKREG r5, 0x000000C1; + CHECKREG r6, 0x000000C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + B [ FP + 0x1051 ] = R0; + B [ FP + 0x1053 ] = R1; + B [ FP + 0x1055 ] = R2; + B [ FP + 0x1057 ] = R3; + B [ FP + 0x1059 ] = R4; + B [ FP + 0x1061 ] = R5; + B [ FP + 0x1063 ] = R6; + B [ FP + 0x1065 ] = R7; + R3 = B [ FP + 0x1051 ] (Z); + R4 = B [ FP + 0x1053 ] (Z); + R0 = B [ FP + 0x1055 ] (Z); + R1 = B [ FP + 0x1057 ] (Z); + R2 = B [ FP + 0x1059 ] (Z); + R5 = B [ FP + 0x1061 ] (Z); + R6 = B [ FP + 0x1063 ] (Z); + R7 = B [ FP + 0x1065 ] (Z); + CHECKREG r0, 0x000000D2; + CHECKREG r1, 0x000000D3; + CHECKREG r2, 0x000000D4; + CHECKREG r3, 0x000000D0; + CHECKREG r4, 0x000000D1; + CHECKREG r5, 0x000000D5; + CHECKREG r6, 0x000000D6; + CHECKREG r7, 0x000000D7; + + P3 = I0; SP = I2; + pass + +// Pre-load memory witb known data +// More data is defined than will actually be used + + .data +// Make sure there is space between the text and data sections + .space (0x2000); + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/tests/tcg/bfin/c_ldstidxl_st_dr_h.s b/tests/tcg/bfin/c_ldstidxl_st_dr_h.s new file mode 100644 index 0000000000000..114d192423dba --- /dev/null +++ b/tests/tcg/bfin/c_ldstidxl_st_dr_h.s @@ -0,0 +1,609 @@ +//Original:testcases/core/c_ldstidxl_st_dr_h/c_ldstidxl_st_dr_h.dsp +// Spec Reference: c_ldstidxl store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xc8; + loadsym i1, DATA_ADDR_1, 0x10; + loadsym p4, DATA_ADDR_2, 0xc8; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym fp, DATA_ADDR_2, 0xc8; + loadsym i3, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + W [ P1 + 0x1002 ] = R0; + W [ P1 + 0x1004 ] = R1; + W [ P1 + 0x1006 ] = R2; + W [ P1 + 0x1008 ] = R3; + W [ P2 + -0x1010 ] = R4; + W [ P2 + -0x1022 ] = R5; + W [ P2 + -0x1034 ] = R6; + W [ P2 + -0x1046 ] = R7; + R6 = W [ P1 + 0x1002 ] (Z); + R5 = W [ P1 + 0x1004 ] (Z); + R4 = W [ P1 + 0x1006 ] (Z); + R3 = W [ P1 + 0x1008 ] (Z); + R2 = W [ P2 + -0x1010 ] (Z); + R7 = W [ P2 + -0x1022 ] (Z); + R0 = W [ P2 + -0x1034 ] (Z); + R1 = W [ P2 + -0x1046 ] (Z); + CHECKREG r0, 0x0000B0A6; + CHECKREG r1, 0x0000C0A7; + CHECKREG r2, 0x000090A4; + CHECKREG r3, 0x000080A3; + CHECKREG r4, 0x000070A2; + CHECKREG r5, 0x000060A1; + CHECKREG r6, 0x000050A0; + CHECKREG r7, 0x0000A0A5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + W [ P3 + 0x1018 ] = R0; + W [ P3 + 0x1020 ] = R1; + W [ P3 + 0x1022 ] = R2; + W [ P3 + 0x1024 ] = R3; + W [ P4 + -0x1026 ] = R4; + W [ P4 + -0x1028 ] = R5; + W [ P4 + -0x1030 ] = R6; + W [ P4 + -0x1052 ] = R7; + R3 = W [ P3 + 0x1018 ] (Z); + R4 = W [ P3 + 0x1020 ] (Z); + R0 = W [ P3 + 0x1022 ] (Z); + R1 = W [ P3 + 0x1024 ] (Z); + R2 = W [ P4 + -0x1026 ] (Z); + R5 = W [ P4 + -0x1028 ] (Z); + R6 = W [ P4 + -0x1030 ] (Z); + R7 = W [ P4 + -0x1052 ] (Z); + CHECKREG r0, 0x000070B2; + CHECKREG r1, 0x000080B3; + CHECKREG r2, 0x000090B4; + CHECKREG r3, 0x000050B0; + CHECKREG r4, 0x000060B1; + CHECKREG r5, 0x0000A0B5; + CHECKREG r6, 0x0000B0B6; + CHECKREG r7, 0x0000C0B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + W [ P5 + 0x1034 ] = R0; + W [ P5 + 0x1036 ] = R1; + W [ P5 + 0x1038 ] = R2; + W [ P5 + 0x1040 ] = R3; + W [ SP + -0x1042 ] = R4; + W [ SP + -0x1054 ] = R5; + W [ SP + -0x1066 ] = R6; + W [ SP + -0x1078 ] = R7; + R6 = W [ P5 + 0x1034 ] (Z); + R5 = W [ P5 + 0x1036 ] (Z); + R4 = W [ P5 + 0x1038 ] (Z); + R3 = W [ P5 + 0x1040 ] (Z); + R2 = W [ SP + -0x1042 ] (Z); + R0 = W [ SP + -0x1054 ] (Z); + R7 = W [ SP + -0x1066 ] (Z); + R1 = W [ SP + -0x1078 ] (Z); + CHECKREG r0, 0x0000A0C5; + CHECKREG r1, 0x0000C0C7; + CHECKREG r2, 0x000090C4; + CHECKREG r3, 0x000080C3; + CHECKREG r4, 0x000070C2; + CHECKREG r5, 0x000060C1; + CHECKREG r6, 0x000050C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + W [ FP + 0x1050 ] = R0; + W [ FP + 0x1052 ] = R1; + W [ FP + 0x1054 ] = R2; + W [ FP + 0x1056 ] = R3; + W [ FP + 0x1058 ] = R4; + W [ FP + 0x1060 ] = R5; + W [ FP + 0x1062 ] = R6; + W [ FP + 0x1064 ] = R7; + R3 = W [ FP + 0x1050 ] (Z); + R4 = W [ FP + 0x1052 ] (Z); + R0 = W [ FP + 0x1054 ] (Z); + R1 = W [ FP + 0x1056 ] (Z); + R2 = W [ FP + 0x1058 ] (Z); + R5 = W [ FP + 0x1060 ] (Z); + R6 = W [ FP + 0x1062 ] (Z); + R7 = W [ FP + 0x1064 ] (Z); + CHECKREG r0, 0x000070D2; + CHECKREG r1, 0x000080D3; + CHECKREG r2, 0x000090D4; + CHECKREG r3, 0x000050D0; + CHECKREG r4, 0x000060D1; + CHECKREG r5, 0x0000A0D5; + CHECKREG r6, 0x0000B0D6; + CHECKREG r7, 0x0000C0D7; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + .space (0x2000); +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/tests/tcg/bfin/c_ldstidxl_st_dreg.s b/tests/tcg/bfin/c_ldstidxl_st_dreg.s new file mode 100644 index 0000000000000..ac1f028f7df66 --- /dev/null +++ b/tests/tcg/bfin/c_ldstidxl_st_dreg.s @@ -0,0 +1,780 @@ +//Original:testcases/core/c_ldstidxl_st_dreg/c_ldstidxl_st_dreg.dsp +// Spec Reference: c_ldstidxl store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xc8; + loadsym i1, DATA_ADDR_1, 0x10; + loadsym p4, DATA_ADDR_2, 0xc8; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym fp, DATA_ADDR_2, 0xc8; + loadsym i3, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + [ P1 + 0x1004 ] = R0; + [ P1 + 0x1008 ] = R1; + [ P1 + 0x1010 ] = R2; + [ P1 + 0x1014 ] = R3; + [ P2 + -0x1020 ] = R4; + [ P2 + -0x1024 ] = R5; + [ P2 + -0x1028 ] = R6; + [ P2 + -0x1030 ] = R7; + R6 = [ P1 + 0x1004 ]; + R5 = [ P1 + 0x1008 ]; + R4 = [ P1 + 0x1010 ]; + R3 = [ P1 + 0x1014 ]; + R2 = [ P2 + -0x1020 ]; + R7 = [ P2 + -0x1024 ]; + R0 = [ P2 + -0x1028 ]; + R1 = [ P2 + -0x1030 ]; + CHECKREG r0, 0x7019B0A6; + CHECKREG r1, 0xD028C0A7; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + CHECKREG r7, 0x600AA0A5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + [ P3 + 0x1034 ] = R0; + [ P3 + 0x1040 ] = R1; + [ P3 + 0x1044 ] = R2; + [ P3 + 0x1048 ] = R3; + [ P4 + -0x1050 ] = R4; + [ P4 + -0x1054 ] = R5; + [ P4 + -0x1060 ] = R6; + [ P4 + -0x1064 ] = R7; + R3 = [ P3 + 0x1034 ]; + R4 = [ P3 + 0x1040 ]; + R0 = [ P3 + 0x1044 ]; + R1 = [ P3 + 0x1048 ]; + R2 = [ P4 + -0x1050 ]; + R5 = [ P4 + -0x1054 ]; + R6 = [ P4 + -0x1060 ]; + R7 = [ P4 + -0x1064 ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + CHECKREG r7, 0x80B8C0B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + [ P5 + 1004 ] = R0; + [ P5 + 1008 ] = R1; + [ P5 + 1012 ] = R2; + [ P5 + 1016 ] = R3; + [ SP + -0x1020 ] = R4; + [ SP + -0x1024 ] = R5; + [ SP + -0x1028 ] = R6; + [ SP + -0x1030 ] = R7; + R6 = [ P5 + 1004 ]; + R4 = [ P5 + 1008 ]; + R5 = [ P5 + 1012 ]; + R3 = [ P5 + 1016 ]; + R2 = [ SP + -0x1020 ]; + R0 = [ SP + -0x1024 ]; + R7 = [ SP + -0x1028 ]; + R1 = [ SP + -0x1030 ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0xD0C8C0C7; + CHECKREG r2, 0x50CB90C4; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x20CE60C1; + CHECKREG r5, 0x30C370C2; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + [ FP + 0x1034 ] = R0; + [ FP + 0x1040 ] = R1; + [ FP + 0x1044 ] = R2; + [ FP + 0x1048 ] = R3; + [ FP + 0x1050 ] = R4; + [ FP + 0x1054 ] = R5; + [ FP + 0x1060 ] = R6; + [ FP + 0x1064 ] = R7; + + R3 = [ FP + 0x1034 ]; + R4 = [ FP + 0x1040 ]; + R0 = [ FP + 0x1044 ]; + R1 = [ FP + 0x1048 ]; + R2 = [ FP + 0x1050 ]; + R5 = [ FP + 0x1054 ]; + R6 = [ FP + 0x1060 ]; + R7 = [ FP + 0x1064 ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0x60DF50D0; + CHECKREG r4, 0x70DE60D1; + CHECKREG r5, 0xB0DAA0D5; + CHECKREG r6, 0xC0D9B0D6; + CHECKREG r7, 0xD0D8C0D7; + + P3 = I0; SP = I2; + pass + + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +// Make sure there is space between the text section, and the data section + .space (0x2000); + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_2: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/tests/tcg/bfin/c_ldstidxl_st_preg.s b/tests/tcg/bfin/c_ldstidxl_st_preg.s new file mode 100644 index 0000000000000..6520f82174b09 --- /dev/null +++ b/tests/tcg/bfin/c_ldstidxl_st_preg.s @@ -0,0 +1,709 @@ +//Original:testcases/core/c_ldstidxl_st_preg/c_ldstidxl_st_preg.dsp +// Spec Reference: c_ldstidxl store preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + P3 = 0x0123 (X); + P4 = 0x4567 (X); + P5 = 0x79ab (X); + FP = 0x6def (X); + SP = 0x1ace (X); + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x0000; + loadsym p2, DATA_ADDR_2, 0x00c8; + P3 = I1; SP = I3; + + [ P1 + 0x1004 ] = P5; + [ P1 + 0x1008 ] = P3; + [ P1 + 0x1014 ] = P4; + [ P1 + 0x1018 ] = P3; + [ P2 + -0x1020 ] = P4; + [ P2 + -0x1024 ] = P5; + [ P2 + -0x1028 ] = SP; + [ P2 + -0x1034 ] = FP; + R6 = [ P1 + 0x1004 ]; + R5 = [ P1 + 0x1008 ]; + R4 = [ P1 + 0x1014 ]; + R3 = [ P1 + 0x1018 ]; + R2 = [ P2 + -0x1020 ]; + R7 = [ P2 + -0x1024 ]; + R0 = [ P2 + -0x1028 ]; + R1 = [ P2 + -0x1034 ]; + CHECKREG r0, 0x00001ACE; + CHECKREG r1, 0x00006DEF; + CHECKREG r2, 0x00004567; + CHECKREG r3, 0x00000123; + CHECKREG r4, 0x00004567; + CHECKREG r5, 0x00000123; + CHECKREG r6, 0x000079AB; + CHECKREG r7, 0x000079AB; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P1 = 0x3456 (X); + P2 = 0x1234 (X); + P5 = 0x5e23 (X); + FP = 0x2ac5 (X); + SP = 0x6378 (X); + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x0000; + loadsym p4, DATA_ADDR_2, 0x00c8; + P3 = I1; SP = I3; + + [ P3 + 0x1034 ] = P2; + [ P3 + 0x1040 ] = P1; + [ P3 + 0x1044 ] = P2; + [ P3 + 0x1048 ] = P1; + [ P4 + -0x1054 ] = P2; + [ P4 + -0x1058 ] = P5; + [ P4 + -0x1060 ] = SP; + [ P4 + -0x1064 ] = FP; + R3 = [ P3 + 0x1034 ]; + R4 = [ P3 + 0x1040 ]; + R0 = [ P3 + 0x1044 ]; + R1 = [ P3 + 0x1048 ]; + R2 = [ P4 + -0x1054 ]; + R5 = [ P4 + -0x1058 ]; + R6 = [ P4 + -0x1060 ]; + R7 = [ P4 + -0x1064 ]; + CHECKREG r0, 0x00001234; + CHECKREG r1, 0x00003456; + CHECKREG r2, 0x00001234; + CHECKREG r3, 0x00001234; + CHECKREG r4, 0x00003456; + CHECKREG r5, 0x00005E23; + CHECKREG r6, 0x00006378; + CHECKREG r7, 0x00002AC5; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P1 = 0x2125 (X); + P2 = 0x7345 (X); + P3 = 0x3230 (X); + P4 = 0x5789 (X); + FP = 0x5bcd (X); + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x0000; + loadsym i3, DATA_ADDR_2, 0x00c8; + P3 = I1; SP = I3; + + [ P5 + 0x1004 ] = P2; + [ P5 + 0x1008 ] = P1; + [ P5 + 0x1014 ] = P2; + [ P5 + 0x1018 ] = P3; + [ SP + -0x1020 ] = P4; + [ SP + -0x1024 ] = P2; + [ SP + -0x1028 ] = P3; + [ SP + -0x1034 ] = FP; + R6 = [ P5 + 0x1004 ]; + R5 = [ P5 + 0x1008 ]; + R4 = [ P5 + 0x1014 ]; + R3 = [ P5 + 0x1018 ]; + R2 = [ SP + -0x1020 ]; + R0 = [ SP + -0x1024 ]; + R7 = [ SP + -0x1028 ]; + R1 = [ SP + -0x1034 ]; + CHECKREG r0, 0x00007345; + CHECKREG r1, 0x00005BCD; + CHECKREG r2, 0x00005789; + CHECKREG r3, 0x00003230; + CHECKREG r4, 0x00007345; + CHECKREG r5, 0x00002125; + CHECKREG r6, 0x00007345; + CHECKREG r7, 0x00003230; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P1 = 0x5bcd (X); + P2 = 0x1122 (X); + P3 = 0x3455 (X); + P4 = 0x6677 (X); + P5 = 0x58ab (X); + SP = 0x1ace (X); + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0x0010; + P3 = I1; SP = I3; + [ FP + 0x1034 ] = P1; + [ FP + 0x2040 ] = P1; + [ FP + 0x1144 ] = P2; + [ FP + 0x2048 ] = P3; + [ FP + 0x1050 ] = P4; + [ FP + 0x2058 ] = P5; + [ FP + 0x1160 ] = P2; + [ FP + 0x2064 ] = SP; + R3 = [ FP + 0x1034 ]; + R4 = [ FP + 0x2040 ]; + R0 = [ FP + 0x1144 ]; + R1 = [ FP + 0x2048 ]; + R2 = [ FP + 0x1050 ]; + R5 = [ FP + 0x2058 ]; + R6 = [ FP + 0x1160 ]; + R7 = [ FP + 0x2064 ]; + CHECKREG r0, 0x00001122; + CHECKREG r1, 0x00003455; + CHECKREG r2, 0x00006677; + CHECKREG r3, 0x00005BCD; + CHECKREG r4, 0x00005BCD; + CHECKREG r5, 0x000058AB; + CHECKREG r6, 0x00001122; + CHECKREG r7, 0x00001ace; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +// Make sure there is space between the text and data sections + .space (0x2000); + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_2: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/tests/tcg/bfin/c_ldstii_ld_dr_h.s b/tests/tcg/bfin/c_ldstii_ld_dr_h.s new file mode 100644 index 0000000000000..a2daecd5dd04a --- /dev/null +++ b/tests/tcg/bfin/c_ldstii_ld_dr_h.s @@ -0,0 +1,541 @@ +//Original:testcases/core/c_ldstii_ld_dr_h/c_ldstii_ld_dr_h.dsp +// Spec Reference: c_ldstii load dreg h +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0 = W [ P1 + 0 ] (Z); + R1 = W [ P1 + 4 ] (Z); + R2 = W [ P1 + 8 ] (Z); + R3 = W [ P1 + 12 ] (Z); + R4 = W [ P1 + 16 ] (Z); + R5 = W [ P1 + 20 ] (Z); + R6 = W [ P1 + 24 ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000607; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000E0F; + CHECKREG r4, 0x00001213; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00001A1B; + + R0 = W [ P2 + 28 ] (Z); + R1 = W [ P2 + 32 ] (Z); + R2 = W [ P2 + 36 ] (Z); + R3 = W [ P2 + 40 ] (Z); + R4 = W [ P2 + 44 ] (Z); + R5 = W [ P2 + 48 ] (Z); + R6 = W [ P2 + 52 ] (Z); + CHECKREG r0, 0x00009394; + CHECKREG r1, 0x00009798; + CHECKREG r2, 0x0000A2A3; + CHECKREG r3, 0x0000A7A8; + CHECKREG r4, 0x0000B1B2; + CHECKREG r5, 0x0000B5B6; + CHECKREG r6, 0x0000B9C0; + + R0 = W [ P3 + 56 ] (Z); + R1 = W [ P3 + 60 ] (Z); + R2 = W [ P3 + 64 ] (Z); + R3 = W [ P3 + 60 ] (Z); + R4 = W [ P3 + 56 ] (Z); + R5 = W [ P3 + 52 ] (Z); + R6 = W [ P3 + 48 ] (Z); + CHECKREG r0, 0x000099EA; + CHECKREG r1, 0x000099EA; + CHECKREG r2, 0x000099EA; + CHECKREG r3, 0x000099EA; + CHECKREG r4, 0x000099EA; + CHECKREG r5, 0x0000E5E6; + CHECKREG r6, 0x0000E1E2; + + R0 = W [ P4 + 44 ] (Z); + R1 = W [ P4 + 40 ] (Z); + R2 = W [ P4 + 36 ] (Z); + R3 = W [ P4 + 32 ] (Z); + R4 = W [ P4 + 28 ] (Z); + R5 = W [ P4 + 24 ] (Z); + R6 = W [ P4 + 20 ] (Z); + CHECKREG r0, 0x00007677; + CHECKREG r1, 0x00007273; + CHECKREG r2, 0x00007788; + CHECKREG r3, 0x00003344; + CHECKREG r4, 0x00001E1F; + CHECKREG r5, 0x00001A1B; + CHECKREG r6, 0x00001617; + + R0 = W [ P5 + 16 ] (Z); + R1 = W [ P5 + 12 ] (Z); + R2 = W [ P5 + 8 ] (Z); + R3 = W [ P5 + 4 ] (Z); + R4 = W [ P5 + 0 ] (Z); + R5 = W [ P5 + 4 ] (Z); + R6 = W [ P5 + 8 ] (Z); + CHECKREG r0, 0x00003233; + CHECKREG r1, 0x00002E2F; + CHECKREG r2, 0x00002A2B; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00002223; + CHECKREG r5, 0x00002627; + CHECKREG r6, 0x00002A2B; + + R0 = W [ FP + 12 ] (Z); + R1 = W [ FP + 16 ] (Z); + R2 = W [ FP + 20 ] (Z); + R3 = W [ FP + 24 ] (Z); + R4 = W [ FP + 28 ] (Z); + R5 = W [ FP + 32 ] (Z); + R6 = W [ FP + 36 ] (Z); + CHECKREG r0, 0x00004E4F; + CHECKREG r1, 0x00005253; + CHECKREG r2, 0x00005657; + CHECKREG r3, 0x00005A5B; + CHECKREG r4, 0x0000C7C8; + CHECKREG r5, 0x0000CBCD; + CHECKREG r6, 0x0000D1D2; + + R0 = W [ SP + 40 ] (Z); + R1 = W [ SP + 44 ] (Z); + R2 = W [ SP + 48 ] (Z); + R3 = W [ SP + 52 ] (Z); + R4 = W [ SP + 56 ] (Z); + R5 = W [ SP + 60 ] (Z); + R6 = W [ SP + 64 ] (Z); + CHECKREG r0, 0x0000F9FA; + CHECKREG r1, 0x0000FDFE; + CHECKREG r2, 0x00000102; + CHECKREG r3, 0x00000506; + CHECKREG r4, 0x0000090A; + CHECKREG r5, 0x0000AD0E; + CHECKREG r6, 0x0000AD01; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstii_ld_dr_xh.s b/tests/tcg/bfin/c_ldstii_ld_dr_xh.s new file mode 100644 index 0000000000000..07b097fc6361c --- /dev/null +++ b/tests/tcg/bfin/c_ldstii_ld_dr_xh.s @@ -0,0 +1,541 @@ +//Original:testcases/core/c_ldstii_ld_dr_xh/c_ldstii_ld_dr_xh.dsp +// Spec Reference: c_ldstii load dreg xh +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0 = W [ P1 + 0 ] (X); + R1 = W [ P1 + 4 ] (X); + R2 = W [ P1 + 8 ] (X); + R3 = W [ P1 + 12 ] (X); + R4 = W [ P1 + 16 ] (X); + R5 = W [ P1 + 20 ] (X); + R6 = W [ P1 + 24 ] (X); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000607; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000E0F; + CHECKREG r4, 0x00001213; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00001A1B; + + R0 = W [ P2 + 28 ] (X); + R1 = W [ P2 + 32 ] (X); + R2 = W [ P2 + 36 ] (X); + R3 = W [ P2 + 40 ] (X); + R4 = W [ P2 + 44 ] (X); + R5 = W [ P2 + 48 ] (X); + R6 = W [ P2 + 52 ] (X); + CHECKREG r0, 0xFFFF9394; + CHECKREG r1, 0xFFFF9798; + CHECKREG r2, 0xFFFFA2A3; + CHECKREG r3, 0xFFFFA7A8; + CHECKREG r4, 0xFFFFB1B2; + CHECKREG r5, 0xFFFFB5B6; + CHECKREG r6, 0xFFFFB9C0; + + R0 = W [ P3 + 56 ] (X); + R1 = W [ P3 + 60 ] (X); + R2 = W [ P3 + 64 ] (X); + R3 = W [ P3 + 60 ] (X); + R4 = W [ P3 + 56 ] (X); + R5 = W [ P3 + 52 ] (X); + R6 = W [ P3 + 48 ] (X); + CHECKREG r0, 0xFFFF99EA; + CHECKREG r1, 0xFFFF99EA; + CHECKREG r2, 0xFFFF99EA; + CHECKREG r3, 0xFFFF99EA; + CHECKREG r4, 0xFFFF99EA; + CHECKREG r5, 0xFFFFE5E6; + CHECKREG r6, 0xFFFFE1E2; + + R0 = W [ P4 + 44 ] (X); + R1 = W [ P4 + 40 ] (X); + R2 = W [ P4 + 36 ] (X); + R3 = W [ P4 + 32 ] (X); + R4 = W [ P4 + 28 ] (X); + R5 = W [ P4 + 24 ] (X); + R6 = W [ P4 + 20 ] (X); + CHECKREG r0, 0x00007677; + CHECKREG r1, 0x00007273; + CHECKREG r2, 0x00007788; + CHECKREG r3, 0x00003344; + CHECKREG r4, 0x00001E1F; + CHECKREG r5, 0x00001A1B; + CHECKREG r6, 0x00001617; + + R0 = W [ P5 + 16 ] (X); + R1 = W [ P5 + 12 ] (X); + R2 = W [ P5 + 8 ] (X); + R3 = W [ P5 + 4 ] (X); + R4 = W [ P5 + 0 ] (X); + R5 = W [ P5 + 4 ] (X); + R6 = W [ P5 + 8 ] (X); + CHECKREG r0, 0x00003233; + CHECKREG r1, 0x00002E2F; + CHECKREG r2, 0x00002A2B; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00002223; + CHECKREG r5, 0x00002627; + CHECKREG r6, 0x00002A2B; + + R0 = W [ FP + 12 ] (X); + R1 = W [ FP + 16 ] (X); + R2 = W [ FP + 20 ] (X); + R3 = W [ FP + 24 ] (X); + R4 = W [ FP + 28 ] (X); + R5 = W [ FP + 32 ] (X); + R6 = W [ FP + 36 ] (X); + CHECKREG r0, 0x00004E4F; + CHECKREG r1, 0x00005253; + CHECKREG r2, 0x00005657; + CHECKREG r3, 0x00005A5B; + CHECKREG r4, 0xFFFFC7C8; + CHECKREG r5, 0xFFFFCBCD; + CHECKREG r6, 0xFFFFD1D2; + + R0 = W [ SP + 40 ] (X); + R1 = W [ SP + 44 ] (X); + R2 = W [ SP + 48 ] (X); + R3 = W [ SP + 52 ] (X); + R4 = W [ SP + 56 ] (X); + R5 = W [ SP + 60 ] (X); + R6 = W [ SP + 64 ] (X); + CHECKREG r0, 0xFFFFF9FA; + CHECKREG r1, 0xFFFFFDFE; + CHECKREG r2, 0x00000102; + CHECKREG r3, 0x00000506; + CHECKREG r4, 0x0000090A; + CHECKREG r5, 0xFFFFAD0E; + CHECKREG r6, 0xFFFFAD01; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstii_ld_dreg.s b/tests/tcg/bfin/c_ldstii_ld_dreg.s new file mode 100644 index 0000000000000..00757f3ca8e37 --- /dev/null +++ b/tests/tcg/bfin/c_ldstii_ld_dreg.s @@ -0,0 +1,540 @@ +//Original:testcases/core/c_ldstii_ld_dreg/c_ldstii_ld_dreg.dsp +// Spec Reference: c_ldstii load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0 = [ P1 + 0 ]; + R1 = [ P1 + 4 ]; + R2 = [ P1 + 8 ]; + R3 = [ P1 + 12 ]; + R4 = [ P1 + 16 ]; + R5 = [ P1 + 20 ]; + R6 = [ P1 + 24 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x18191A1B; + + R0 = [ P2 + 28 ]; + R1 = [ P2 + 32 ]; + R2 = [ P2 + 36 ]; + R3 = [ P2 + 40 ]; + R4 = [ P2 + 44 ]; + R5 = [ P2 + 48 ]; + R6 = [ P2 + 52 ]; + CHECKREG r0, 0x91929394; + CHECKREG r1, 0x95969798; + CHECKREG r2, 0x99A1A2A3; + CHECKREG r3, 0xA5A6A7A8; + CHECKREG r4, 0xA9B0B1B2; + CHECKREG r5, 0xB3B4B5B6; + CHECKREG r6, 0xB7B8B9C0; + + R0 = [ P3 + 56 ]; + R1 = [ P3 + 60 ]; + R2 = [ P3 + 64 ]; + R3 = [ P3 + 60 ]; + R4 = [ P3 + 56 ]; + R5 = [ P3 + 52 ]; + R6 = [ P3 + 48 ]; + CHECKREG r0, 0x91E899EA; + CHECKREG r1, 0x92E899EA; + CHECKREG r2, 0x93E899EA; + CHECKREG r3, 0x92E899EA; + CHECKREG r4, 0x91E899EA; + CHECKREG r5, 0xE3E4E5E6; + CHECKREG r6, 0xDFE0E1E2; + + R0 = [ P4 + 44 ]; + R1 = [ P4 + 40 ]; + R2 = [ P4 + 36 ]; + R3 = [ P4 + 32 ]; + R4 = [ P4 + 28 ]; + R5 = [ P4 + 24 ]; + R6 = [ P4 + 20 ]; + CHECKREG r0, 0x74757677; + CHECKREG r1, 0x99717273; + CHECKREG r2, 0x55667788; + CHECKREG r3, 0x11223344; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r5, 0x18191A1B; + CHECKREG r6, 0x14151617; + + R0 = [ P5 + 16 ]; + R1 = [ P5 + 12 ]; + R2 = [ P5 + 8 ]; + R3 = [ P5 + 4 ]; + R4 = [ P5 + 0 ]; + R5 = [ P5 + 4 ]; + R6 = [ P5 + 8 ]; + CHECKREG r0, 0x30313233; + CHECKREG r1, 0x2C2D2E2F; + CHECKREG r2, 0x28292A2B; + CHECKREG r3, 0x24252627; + CHECKREG r4, 0x20212223; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x28292A2B; + + R0 = [ FP + 12 ]; + R1 = [ FP + 16 ]; + R2 = [ FP + 20 ]; + R3 = [ FP + 24 ]; + R4 = [ FP + 28 ]; + R5 = [ FP + 32 ]; + R6 = [ FP + 36 ]; + CHECKREG r0, 0x4C4D4E4F; + CHECKREG r1, 0x50515253; + CHECKREG r2, 0x54555657; + CHECKREG r3, 0x58595A5B; + CHECKREG r4, 0xC5C6C7C8; + CHECKREG r5, 0xC9CACBCD; + CHECKREG r6, 0xCFD0D1D2; + + R0 = [ SP + 40 ]; + R1 = [ SP + 44 ]; + R2 = [ SP + 48 ]; + R3 = [ SP + 52 ]; + R4 = [ SP + 56 ]; + R5 = [ SP + 60 ]; + R6 = [ SP + 64 ]; + CHECKREG r0, 0xF7F8F9FA; + CHECKREG r1, 0xFBFCFDFE; + CHECKREG r2, 0xFF000102; + CHECKREG r3, 0x03040506; + CHECKREG r4, 0x0708090A; + CHECKREG r5, 0x0B0CAD0E; + CHECKREG r6, 0xAB0CAD01; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstii_ld_preg.s b/tests/tcg/bfin/c_ldstii_ld_preg.s new file mode 100644 index 0000000000000..961b7d3f14f8f --- /dev/null +++ b/tests/tcg/bfin/c_ldstii_ld_preg.s @@ -0,0 +1,564 @@ +//Original:testcases/core/c_ldstii_ld_preg/c_ldstii_ld_preg.dsp +// Spec Reference: c_ldstii load preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + P2 = [ P1 + 0 ]; + P3 = [ P1 + 4 ]; + P4 = [ P1 + 8 ]; + P5 = [ P1 + 12 ]; + SP = [ P1 + 16 ]; + FP = [ P1 + 20 ]; + P1 = [ P1 + 24 ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x00010203; + CHECKREG p3, 0x04050607; + CHECKREG p4, 0x08090A0B; + CHECKREG p5, 0x0C0D0E0F; + CHECKREG sp, 0x10111213; + CHECKREG fp, 0x14151617; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x04; + P3 = I1; SP = I3; + + P1 = [ P2 + 28 ]; + P3 = [ P2 + 36 ]; + P4 = [ P2 + 40 ]; + P5 = [ P2 + 44 ]; + SP = [ P2 + 48 ]; + FP = [ P2 + 52 ]; + P2 = [ P2 + 32 ]; + CHECKREG p1, 0x91929394; + CHECKREG p2, 0x95969798; + CHECKREG p3, 0x99A1A2A3; + CHECKREG p4, 0xA5A6A7A8; + CHECKREG p5, 0xA9B0B1B2; + CHECKREG sp, 0xB3B4B5B6; + CHECKREG fp, 0xB7B8B9C0; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + P1 = [ P3 + 56 ]; + P2 = [ P3 + 60 ]; + P4 = [ P3 + 60 ]; + P5 = [ P3 + 56 ]; + SP = [ P3 + 52 ]; + FP = [ P3 + 48 ]; + P3 = [ P3 + 64 ]; + CHECKREG p1, 0xE3E4E5E6; + CHECKREG p2, 0x91E899EA; + CHECKREG p3, 0x92E899EA; + CHECKREG p4, 0x91E899EA; + CHECKREG p5, 0xE3E4E5E6; + CHECKREG sp, 0xDFE0E1E2; + CHECKREG fp, 0xDBDCDDDE; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + P1 = [ P4 + 44 ]; + P2 = [ P4 + 40 ]; + P3 = [ P4 + 36 ]; + P5 = [ P4 + 28 ]; + SP = [ P4 + 24 ]; + FP = [ P4 + 20 ]; + P4 = [ P4 + 32 ]; + CHECKREG p1, 0xFBFCFDFE; + CHECKREG p2, 0xF7F8F9FA; + CHECKREG p3, 0xF3F4F5F6; + CHECKREG p4, 0xEBECEDEE; + CHECKREG p5, 0x7C7D7E7F; + CHECKREG sp, 0x78797A7B; + CHECKREG fp, 0x74757677; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + P1 = [ P5 + 16 ]; + P2 = [ P5 + 12 ]; + P3 = [ P5 + 8 ]; + P4 = [ P5 + 0 ]; + SP = [ P5 + 4 ]; + FP = [ P5 + 8 ]; + P5 = [ P5 + 4 ]; + CHECKREG p1, 0x10111213; + CHECKREG p2, 0x0C0D0E0F; + CHECKREG p3, 0x08090A0B; + CHECKREG p4, 0x00010203; + CHECKREG p5, 0x04050607; + CHECKREG sp, 0x04050607; + CHECKREG fp, 0x08090A0B; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + + P1 = [ SP + 12 ]; + P2 = [ SP + 16 ]; + P3 = [ SP + 20 ]; + P4 = [ SP + 24 ]; + P5 = [ SP + 28 ]; + FP = [ SP + 32 ]; + SP = [ SP + 36 ]; + CHECKREG p1, 0x2C2D2E2F; + CHECKREG p2, 0x30313233; + CHECKREG p3, 0x34353637; + CHECKREG p4, 0x38393A3B; + CHECKREG p5, 0x3C3D3E3F; + CHECKREG sp, 0x95969798; + CHECKREG fp, 0x91929394; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + P1 = [ FP + 40 ]; + P2 = [ FP + 44 ]; + P3 = [ FP + 48 ]; + P4 = [ FP + 52 ]; + P5 = [ FP + 56 ]; + SP = [ FP + 60 ]; + FP = [ FP + 64 ]; + CHECKREG p1, 0xD3D4D5D6; + CHECKREG p2, 0xD7D8D9DA; + CHECKREG p3, 0xDBDCDDDE; + CHECKREG p4, 0xDFE0E1E2; + CHECKREG p5, 0xE3E4E5E6; + CHECKREG sp, 0x91E899EA; + CHECKREG fp, 0x92E899EA; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstii_st_dr_h.s b/tests/tcg/bfin/c_ldstii_st_dr_h.s new file mode 100644 index 0000000000000..2f855348dbe10 --- /dev/null +++ b/tests/tcg/bfin/c_ldstii_st_dr_h.s @@ -0,0 +1,605 @@ +//Original:/testcases/core/c_ldstii_st_dr_h/c_ldstii_st_dr_h.dsp +// Spec Reference: c_ldstii store dreg +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_1; + loadsym fp, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym sp, DATA_ADDR_3; +.endif + + W [ P1 + 2 ] = R0; + W [ P1 + 4 ] = R1; + W [ P1 + 6 ] = R2; + W [ P1 + 8 ] = R3; + W [ P2 + 10 ] = R4; + W [ P2 + 12 ] = R5; + W [ P2 + 14 ] = R6; + W [ P2 + 16 ] = R7; + R6 = W [ P1 + 2 ] (Z); + R5 = W [ P1 + 4 ] (Z); + R4 = W [ P1 + 6 ] (Z); + R3 = W [ P1 + 8 ] (Z); + R2 = W [ P2 + 10 ] (Z); + R7 = W [ P2 + 12 ] (Z); + R0 = W [ P2 + 14 ] (Z); + R1 = W [ P2 + 16 ] (Z); + CHECKREG r0, 0x0000B0A6; + CHECKREG r1, 0x0000C0A7; + CHECKREG r2, 0x000090A4; + CHECKREG r3, 0x000080A3; + CHECKREG r4, 0x000070A2; + CHECKREG r5, 0x000060A1; + CHECKREG r6, 0x000050A0; + CHECKREG r7, 0x0000A0A5; + +.ifndef BFIN_HOST + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + W [ P3 + 18 ] = R0; + W [ P3 + 20 ] = R1; + W [ P3 + 22 ] = R2; + W [ P3 + 24 ] = R3; + W [ P4 + 26 ] = R4; + W [ P4 + 28 ] = R5; + W [ P4 + 30 ] = R6; + W [ P4 + 32 ] = R7; + R3 = W [ P3 + 18 ] (Z); + R4 = W [ P3 + 20 ] (Z); + R0 = W [ P3 + 22 ] (Z); + R1 = W [ P3 + 24 ] (Z); + R2 = W [ P4 + 26 ] (Z); + R5 = W [ P4 + 28 ] (Z); + R6 = W [ P4 + 30 ] (Z); + R7 = W [ P4 + 32 ] (Z); + CHECKREG r0, 0x000070B2; + CHECKREG r1, 0x000080B3; + CHECKREG r2, 0x000090B4; + CHECKREG r3, 0x000050B0; + CHECKREG r4, 0x000060B1; + CHECKREG r5, 0x0000A0B5; + CHECKREG r6, 0x0000B0B6; + CHECKREG r7, 0x0000C0B7; +.endif + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + W [ P5 + 34 ] = R0; + W [ P5 + 36 ] = R1; + W [ P5 + 38 ] = R2; + W [ P5 + 40 ] = R3; +.ifndef BFIN_HOST + W [ SP + 42 ] = R4; + W [ SP + 44 ] = R5; + W [ SP + 46 ] = R6; + W [ SP + 48 ] = R7; +.endif + R6 = W [ P5 + 34 ] (Z); + R5 = W [ P5 + 36 ] (Z); + R4 = W [ P5 + 38 ] (Z); + R3 = W [ P5 + 40 ] (Z); +.ifndef BFIN_HOST + R2 = W [ SP + 42 ] (Z); + R0 = W [ SP + 44 ] (Z); + R7 = W [ SP + 46 ] (Z); + R1 = W [ SP + 48 ] (Z); + + CHECKREG r0, 0x0000A0C5; + CHECKREG r1, 0x0000C0C7; + CHECKREG r2, 0x000090C4; +.endif + CHECKREG r3, 0x000080C3; + CHECKREG r4, 0x000070C2; + CHECKREG r5, 0x000060C1; + CHECKREG r6, 0x000050C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + W [ FP + 50 ] = R0; + W [ FP + 52 ] = R1; + W [ FP + 54 ] = R2; + W [ FP + 56 ] = R3; + W [ FP + 58 ] = R4; + W [ FP + 60 ] = R5; + W [ FP + 62 ] = R6; + W [ FP + 64 ] = R7; + R3 = W [ FP + 50 ] (Z); + R4 = W [ FP + 52 ] (Z); + R0 = W [ FP + 54 ] (Z); + R1 = W [ FP + 56 ] (Z); + R2 = W [ FP + 58 ] (Z); + R5 = W [ FP + 60 ] (Z); + R6 = W [ FP + 62 ] (Z); + R7 = W [ FP + 64 ] (Z); + CHECKREG r0, 0x000070D2; + CHECKREG r1, 0x000080D3; + CHECKREG r2, 0x000090D4; + CHECKREG r3, 0x000050D0; + CHECKREG r4, 0x000060D1; + CHECKREG r5, 0x0000A0D5; + CHECKREG r6, 0x0000B0D6; + CHECKREG r7, 0x0000C0D7; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstii_st_dreg.s b/tests/tcg/bfin/c_ldstii_st_dreg.s new file mode 100644 index 0000000000000..af04cd5861627 --- /dev/null +++ b/tests/tcg/bfin/c_ldstii_st_dreg.s @@ -0,0 +1,640 @@ +//Original:/testcases/core/c_ldstii_st_dreg/c_ldstii_st_dreg.dsp +// Spec Reference: c_ldstii store dreg +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_1; + loadsym fp, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym sp, DATA_ADDR_3; +.endif + + [ P1 + 4 ] = R0; + [ P1 + 8 ] = R1; + [ P1 + 12 ] = R2; + [ P1 + 16 ] = R3; + [ P2 + 20 ] = R4; + [ P2 + 24 ] = R5; + [ P2 + 28 ] = R6; + [ P2 + 32 ] = R7; + R6 = [ P1 + 4 ]; + R5 = [ P1 + 8 ]; + R4 = [ P1 + 12 ]; + R3 = [ P1 + 16 ]; + R2 = [ P2 + 20 ]; + R7 = [ P2 + 24 ]; + R0 = [ P2 + 28 ]; + R1 = [ P2 + 32 ]; + CHECKREG r0, 0x7019B0A6; + CHECKREG r1, 0xD028C0A7; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + CHECKREG r7, 0x600AA0A5; + +.ifndef BFIN_HOST + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + [ P3 + 36 ] = R0; + [ P3 + 40 ] = R1; + [ P3 + 44 ] = R2; + [ P3 + 48 ] = R3; + [ P4 + 52 ] = R4; + [ P4 + 56 ] = R5; + [ P4 + 60 ] = R6; + [ P4 + 64 ] = R7; + R3 = [ P3 + 36 ]; + R4 = [ P3 + 40 ]; + R0 = [ P3 + 44 ]; + R1 = [ P3 + 48 ]; + R2 = [ P4 + 52 ]; + R5 = [ P4 + 56 ]; + R6 = [ P4 + 60 ]; + R7 = [ P4 + 64 ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + CHECKREG r7, 0x80B8C0B7; +.endif + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + [ P5 + 4 ] = R0; + [ P5 + 8 ] = R1; + [ P5 + 12 ] = R2; + [ P5 + 16 ] = R3; +.ifndef BFIN_HOST + [ SP + 20 ] = R4; + [ SP + 24 ] = R5; + [ SP + 28 ] = R6; + [ SP + 32 ] = R7; +.endif + R6 = [ P5 + 4 ]; + R5 = [ P5 + 8 ]; + R4 = [ P5 + 12 ]; + R3 = [ P5 + 16 ]; +.ifndef BFIN_HOST + R2 = [ SP + 20 ]; + R0 = [ SP + 24 ]; + R7 = [ SP + 28 ]; + R1 = [ SP + 32 ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0xD0C8C0C7; + CHECKREG r2, 0x50CB90C4; +.endif + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x30C370C2; + CHECKREG r5, 0x20CE60C1; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + [ FP + 36 ] = R0; + [ FP + 40 ] = R1; + [ FP + 44 ] = R2; + [ FP + 48 ] = R3; + [ FP + 52 ] = R4; + [ FP + 56 ] = R5; + [ FP + 60 ] = R6; + [ FP + 64 ] = R7; + R3 = [ FP + 36 ]; + R4 = [ FP + 40 ]; + R0 = [ FP + 44 ]; + R1 = [ FP + 48 ]; + R2 = [ FP + 52 ]; + R5 = [ FP + 56 ]; + R6 = [ FP + 60 ]; + R7 = [ FP + 64 ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0x60DF50D0; + CHECKREG r4, 0x70DE60D1; + CHECKREG r5, 0xB0DAA0D5; + CHECKREG r6, 0xC0D9B0D6; + CHECKREG r7, 0xD0D8C0D7; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstii_st_preg.s b/tests/tcg/bfin/c_ldstii_st_preg.s new file mode 100644 index 0000000000000..126bd4d749e5b --- /dev/null +++ b/tests/tcg/bfin/c_ldstii_st_preg.s @@ -0,0 +1,603 @@ +//Original:/testcases/core/c_ldstii_st_preg/c_ldstii_st_preg.dsp +// Spec Reference: c_ldstii store preg +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + P4 = 0x4567 (X); + P5 = 0x79ab (X); + FP = 0x6def (X); + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + + [ P1 + 8 ] = P4; + [ P1 + 12 ] = P5; + [ P2 + 20 ] = P4; + [ P2 + 24 ] = P5; + [ P2 + 32 ] = FP; + R5 = [ P1 + 8 ]; + R4 = [ P1 + 12 ]; + R2 = [ P2 + 20 ]; + R7 = [ P2 + 24 ]; + R1 = [ P2 + 32 ]; + CHECKREG r1, 0x00006DEF; + CHECKREG r2, 0x00004567; + CHECKREG r4, 0x000079AB; + CHECKREG r5, 0x00004567; + CHECKREG r7, 0x000079AB; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P1 = 0x3456 (X); + P2 = 0x1234 (X); + P5 = 0x5e23 (X); + FP = 0x2ac5 (X); + loadsym p4, DATA_ADDR_4; + + [ P4 + 52 ] = P2; + [ P4 + 56 ] = P5; + [ P4 + 64 ] = FP; + R2 = [ P4 + 52 ]; + R5 = [ P4 + 56 ]; + R7 = [ P4 + 64 ]; + CHECKREG r2, 0x00001234; + CHECKREG r5, 0x00005E23; + CHECKREG r7, 0x00002AC5; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P1 = 0x2125 (X); + P2 = 0x7345 (X); + P4 = 0x5789 (X); + FP = 0x5bcd (X); + loadsym p5, DATA_ADDR_1; + + [ P5 + 4 ] = P2; + [ P5 + 8 ] = P1; + [ P5 + 12 ] = P2; + R6 = [ P5 + 4 ]; + R5 = [ P5 + 8 ]; + R4 = [ P5 + 12 ]; + CHECKREG r4, 0x00007345; + CHECKREG r5, 0x00002125; + CHECKREG r6, 0x00007345; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P1 = 0x5bcd (X); + P2 = 0x1122 (X); + P4 = 0x6677 (X); + P5 = 0x58ab (X); + loadsym fp, DATA_ADDR_2; + [ FP + 36 ] = P4; + [ FP + 40 ] = P1; + [ FP + 44 ] = P2; + [ FP + 52 ] = P4; + [ FP + 56 ] = P5; + [ FP + 64 ] = P2; + R3 = [ FP + 36 ]; + R4 = [ FP + 40 ]; + R0 = [ FP + 44 ]; + R2 = [ FP + 52 ]; + R5 = [ FP + 56 ]; + R7 = [ FP + 64 ]; + CHECKREG r0, 0x00001122; + CHECKREG r2, 0x00006677; + CHECKREG r3, 0x00006677; + CHECKREG r4, 0x00005BCD; + CHECKREG r5, 0x000058AB; + CHECKREG r7, 0x00001122; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstiifp_ld_dreg.s b/tests/tcg/bfin/c_ldstiifp_ld_dreg.s new file mode 100644 index 0000000000000..ad5cb82934d8a --- /dev/null +++ b/tests/tcg/bfin/c_ldstiifp_ld_dreg.s @@ -0,0 +1,528 @@ +//Original:testcases/core/c_ldstiifp_ld_dreg/c_ldstiifp_ld_dreg.dsp +// Spec Reference: c_ldstiifp load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0000; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0000; + P5 = 0x0000; + SP = 0x0000; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + r0 = [ fp + 0 ]; + R1 = [ FP + 4 ]; + R2 = [ FP + 8 ]; + R3 = [ FP + 12 ]; + R4 = [ FP + 16 ]; + R5 = [ FP + 20 ]; + R6 = [ FP + 24 ]; + R7 = [ FP + 28 ]; + CHECKREG r0, 0x86878889; + CHECKREG r1, 0x80818283; + CHECKREG r2, 0x84858687; + CHECKREG r3, 0x01020304; + CHECKREG r4, 0x05060708; + CHECKREG r5, 0x09101112; + CHECKREG r6, 0x14151617; + + R0 = [ FP + 32 ]; + R1 = [ FP + 36 ]; + R2 = [ FP + 40 ]; + R3 = [ FP + 44 ]; + R4 = [ FP + 48 ]; + R5 = [ FP + 52 ]; + R7 = [ FP + 56 ]; + CHECKREG r0, 0x22232425; + CHECKREG r1, 0x26272829; + CHECKREG r2, 0x30313233; + CHECKREG r3, 0x34353637; + CHECKREG r4, 0x38394041; + CHECKREG r5, 0x42434445; + CHECKREG r6, 0x14151617; + + R0 = [ FP + 56 ]; + R1 = [ FP + 60 ]; + R2 = [ FP + 64 ]; + R3 = [ FP + 68 ]; + R4 = [ FP + 72 ]; + R5 = [ FP + 76 ]; + R6 = [ FP + 80 ]; + CHECKREG r0, 0x46474849; + CHECKREG r1, 0x50515253; + CHECKREG r2, 0x54555657; + CHECKREG r3, 0x58596061; + CHECKREG r4, 0x62636465; + CHECKREG r5, 0x66676869; + CHECKREG r6, 0x74555657; + + R0 = [ FP + 84 ]; + R1 = [ FP + 88 ]; + R2 = [ FP + 92 ]; + R3 = [ FP + 96 ]; + R4 = [ FP + 100 ]; + R5 = [ FP + 104 ]; + R6 = [ FP + 108 ]; + CHECKREG r0, 0x78596067; + CHECKREG r1, 0x72636467; + CHECKREG r2, 0x76676867; + CHECKREG r3, 0x20212223; + CHECKREG r4, 0x24252627; + CHECKREG r5, 0x28292A2B; + CHECKREG r6, 0x2C2D2E2F; + + R0 = [ FP + 112 ]; + R1 = [ FP + 116 ]; + R2 = [ FP + 120 ]; + R3 = [ FP + 124 ]; + R4 = [ FP + 128 ]; + R5 = [ FP + -4 ]; + R6 = [ FP + -8 ]; + CHECKREG r0, 0x30313233; + CHECKREG r1, 0x34353637; + CHECKREG r2, 0x38393A3B; + CHECKREG r3, 0x3C3D3E3F; + CHECKREG r4, 0x91929394; + CHECKREG r5, 0x82838485; + CHECKREG r6, 0x74757677; + + R0 = [ FP + -12 ]; + R1 = [ FP + -16 ]; + R2 = [ FP + -20 ]; + R3 = [ FP + -24 ]; + R4 = [ FP + -28 ]; + R5 = [ FP + -32 ]; + R6 = [ FP + -36 ]; + CHECKREG r0, 0x99717273; + CHECKREG r1, 0x55667788; + CHECKREG r2, 0x11223344; + CHECKREG r3, 0x1C1D1E1F; + CHECKREG r4, 0x18191A1B; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x10111213; + + R0 = [ FP + -40 ]; + R1 = [ FP + -44 ]; + R2 = [ FP + -48 ]; + R3 = [ FP + -64 ]; + R4 = [ FP + -88 ]; + R5 = [ FP + -96 ]; + R6 = [ FP + -128 ]; + CHECKREG r0, 0x0C0D0E0F; + CHECKREG r1, 0x08090A0B; + CHECKREG r2, 0x04050607; + CHECKREG r3, 0x78596067; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x42434445; + CHECKREG r6, 0x09101112; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstiifp_ld_preg.s b/tests/tcg/bfin/c_ldstiifp_ld_preg.s new file mode 100644 index 0000000000000..7945d305071ce --- /dev/null +++ b/tests/tcg/bfin/c_ldstiifp_ld_preg.s @@ -0,0 +1,511 @@ +//Original:testcases/core/c_ldstiifp_ld_preg/c_ldstiifp_ld_preg.dsp +// Spec Reference: c_ldstiifp load preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P3 = I1; SP = I3; + p1 = [ fp + 0 ]; + P2 = [ FP + -4 ]; + P3 = [ FP + -8 ]; + P4 = [ FP + -12 ]; + P5 = [ FP + -16 ]; + SP = [ FP + -20 ]; + FP = [ FP + -24 ]; + CHECKREG p1, 0x86878889; + CHECKREG p2, 0x82838485; + CHECKREG p3, 0x74757677; + CHECKREG p4, 0x99717273; + CHECKREG p5, 0x55667788; + CHECKREG sp, 0x11223344; + CHECKREG fp, 0x1C1D1E1F; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -28 ]; + P2 = [ FP + -32 ]; + P3 = [ FP + -36 ]; + P4 = [ FP + -40 ]; + P5 = [ FP + -44 ]; + SP = [ FP + -48 ]; + FP = [ FP + -52 ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x14151617; + CHECKREG p3, 0x10111213; + CHECKREG p4, 0x0C0D0E0F; + CHECKREG p5, 0x08090A0B; + CHECKREG sp, 0x04050607; + CHECKREG fp, 0x00010203; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -56 ]; + P2 = [ FP + -60 ]; + P3 = [ FP + -64 ]; + P4 = [ FP + -68 ]; + P5 = [ FP + -72 ]; + SP = [ FP + -76 ]; + FP = [ FP + -80 ]; + CHECKREG p1, 0x76676867; + CHECKREG p2, 0x72636467; + CHECKREG p3, 0x78596067; + CHECKREG p4, 0x74555657; + CHECKREG p5, 0x66676869; + CHECKREG sp, 0x62636465; + CHECKREG fp, 0x58596061; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -84 ]; + P2 = [ FP + -88 ]; + P3 = [ FP + -92 ]; + P4 = [ FP + -96 ]; + P5 = [ FP + -100 ]; + SP = [ FP + -104 ]; + FP = [ FP + -108 ]; + CHECKREG p1, 0x54555657; + CHECKREG p2, 0x50515253; + CHECKREG p3, 0x46474849; + CHECKREG p4, 0x42434445; + CHECKREG p5, 0x38394041; + CHECKREG sp, 0x34353637; + CHECKREG fp, 0x30313233; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -112 ]; + P2 = [ FP + -116 ]; + P3 = [ FP + -120 ]; + P4 = [ FP + -124 ]; + P5 = [ FP + -128 ]; + SP = [ FP + -4 ]; + FP = [ FP + -8 ]; + CHECKREG p1, 0x26272829; + CHECKREG p2, 0x22232425; + CHECKREG p3, 0x18192021; + CHECKREG p4, 0x14151617; + CHECKREG p5, 0x09101112; + CHECKREG sp, 0x82838485; + CHECKREG fp, 0x74757677; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstiifp_st_dreg.s b/tests/tcg/bfin/c_ldstiifp_st_dreg.s new file mode 100644 index 0000000000000..4d1a36329e93d --- /dev/null +++ b/tests/tcg/bfin/c_ldstiifp_st_dreg.s @@ -0,0 +1,641 @@ +//Original:testcases/core/c_ldstiifp_st_dreg/c_ldstiifp_st_dreg.dsp +// Spec Reference: c_ldstiifp store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x00; + loadsym i1, DATA_ADDR_3, 0x00; + loadsym p4, DATA_ADDR_4, 0x00; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym i3, DATA_ADDR_3, 0x00; + loadsym fp, DATA_ADDR_1, 0xC8; + P3 = I1; SP = I3; + + [ FP + -4 ] = R0; + [ FP + -8 ] = R1; + [ FP + -12 ] = R2; + [ FP + -16 ] = R3; + [ FP + -20 ] = R4; + [ FP + -24 ] = R5; + [ FP + -28 ] = R6; + [ FP + -32 ] = R7; + R6 = [ FP + -4 ]; + R5 = [ FP + -8 ]; + R4 = [ FP + -12 ]; + R3 = [ FP + -16 ]; + R2 = [ FP + -20 ]; + R7 = [ FP + -24 ]; + R0 = [ FP + -28 ]; + R1 = [ FP + -32 ]; + CHECKREG r0, 0x7019B0A6; + CHECKREG r1, 0xD028C0A7; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + CHECKREG r7, 0x600AA0A5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + [ FP + -36 ] = R0; + [ FP + -40 ] = R1; + [ FP + -44 ] = R2; + [ FP + -48 ] = R3; + [ FP + -52 ] = R4; + [ FP + -56 ] = R5; + [ FP + -60 ] = R6; + [ FP + -64 ] = R7; + R3 = [ FP + -36 ]; + R4 = [ FP + -40 ]; + R0 = [ FP + -44 ]; + R1 = [ FP + -48 ]; + R2 = [ FP + -52 ]; + R5 = [ FP + -56 ]; + R6 = [ FP + -60 ]; + R7 = [ FP + -64 ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + CHECKREG r7, 0x80B8C0B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + [ FP + -68 ] = R0; + [ FP + -72 ] = R1; + [ FP + -76 ] = R2; + [ FP + -80 ] = R3; + [ FP + -84 ] = R4; + [ FP + -88 ] = R5; + [ FP + -92 ] = R6; + [ FP + -96 ] = R7; + R6 = [ FP + -68 ]; + R5 = [ FP + -72 ]; + R4 = [ FP + -76 ]; + R3 = [ FP + -80 ]; + R2 = [ FP + -84 ]; + R0 = [ FP + -88 ]; + R7 = [ FP + -92 ]; + R1 = [ FP + -96 ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0xD0C8C0C7; + CHECKREG r2, 0x50CB90C4; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x30C370C2; + CHECKREG r5, 0x20CE60C1; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + [ FP + -100 ] = R0; + [ FP + -104 ] = R1; + [ FP + -108 ] = R2; + [ FP + -112 ] = R3; + [ FP + -116 ] = R4; + [ FP + -120 ] = R5; + [ FP + -124 ] = R6; + [ FP + -128 ] = R7; + R3 = [ FP + -100 ]; + R4 = [ FP + -104 ]; + R0 = [ FP + -108 ]; + R1 = [ FP + -112 ]; + R2 = [ FP + -116 ]; + R5 = [ FP + -120 ]; + R6 = [ FP + -124 ]; + R7 = [ FP + -128 ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0x60DF50D0; + CHECKREG r4, 0x70DE60D1; + CHECKREG r5, 0xB0DAA0D5; + CHECKREG r6, 0xC0D9B0D6; + CHECKREG r7, 0xD0D8C0D7; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstiifp_st_preg.s b/tests/tcg/bfin/c_ldstiifp_st_preg.s new file mode 100644 index 0000000000000..3a132dc9492f6 --- /dev/null +++ b/tests/tcg/bfin/c_ldstiifp_st_preg.s @@ -0,0 +1,618 @@ +//Original:testcases/core/c_ldstiifp_st_preg/c_ldstiifp_st_preg.dsp +// Spec Reference: c_ldstiifp store preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + imm32 p1, 0x12345678; + imm32 p2, 0x6789abcd; + imm32 p4, 0x24680123; + imm32 p5, 0x57913597; + + loadsym fp, DATA_ADDR_1, 0xC8; + [ FP + -4 ] = P2; + [ FP + -8 ] = P1; + [ FP + -12 ] = P2; + [ FP + -20 ] = P4; + [ FP + -24 ] = P5; + [ FP + -32 ] = P5; + R6 = [ FP + -4 ]; + R5 = [ FP + -8 ]; + R4 = [ FP + -12 ]; + R2 = [ FP + -20 ]; + R7 = [ FP + -24 ]; + R1 = [ FP + -32 ]; + CHECKREG r1, 0x57913597; + CHECKREG r2, 0x24680123; + CHECKREG r4, 0x6789ABCD; + CHECKREG r5, 0x12345678; + CHECKREG r6, 0x6789ABCD; + CHECKREG r7, 0x57913597; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + imm32 p1, 0x11223344; + imm32 p2, 0x2349abcd; + imm32 p4, 0x44556623; + imm32 p5, 0x57913597; + [ FP + -36 ] = P4; + [ FP + -40 ] = P1; + [ FP + -44 ] = P2; + [ FP + -52 ] = P4; + [ FP + -56 ] = P5; + [ FP + -64 ] = P1; + R3 = [ FP + -36 ]; + R4 = [ FP + -40 ]; + R0 = [ FP + -44 ]; + R2 = [ FP + -52 ]; + R5 = [ FP + -56 ]; + R7 = [ FP + -64 ]; + CHECKREG r0, 0x2349ABCD; + CHECKREG r2, 0x44556623; + CHECKREG r3, 0x44556623; + CHECKREG r4, 0x11223344; + CHECKREG r5, 0x57913597; + CHECKREG r7, 0x11223344; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + imm32 p1, 0x19012345; + imm32 p2, 0x2146abcd; + imm32 p4, 0x24680123; + imm32 p5, 0x57913597; + [ FP + -68 ] = P2; + [ FP + -72 ] = P1; + [ FP + -76 ] = P2; + [ FP + -84 ] = P4; + [ FP + -88 ] = P5; + [ FP + -96 ] = P2; + R6 = [ FP + -68 ]; + R5 = [ FP + -72 ]; + R4 = [ FP + -76 ]; + R2 = [ FP + -84 ]; + R0 = [ FP + -88 ]; + R1 = [ FP + -96 ]; + CHECKREG r0, 0x57913597; + CHECKREG r1, 0x2146ABCD; + CHECKREG r2, 0x24680123; + CHECKREG r4, 0x2146ABCD; + CHECKREG r5, 0x19012345; + CHECKREG r6, 0x2146ABCD; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + imm32 p1, 0x13579678; + imm32 p2, 0x2468abcd; + imm32 p4, 0x45678123; + imm32 p5, 0x57913597; + [ FP + -104 ] = P1; + [ FP + -108 ] = P2; + [ FP + -116 ] = P4; + [ FP + -120 ] = P5; + R4 = [ FP + -104 ]; + R0 = [ FP + -108 ]; + R2 = [ FP + -116 ]; + R5 = [ FP + -120 ]; + CHECKREG r0, 0x2468ABCD; + CHECKREG r2, 0x45678123; + CHECKREG r4, 0x13579678; + CHECKREG r5, 0x57913597; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstpmod_ld_dr_hi.s b/tests/tcg/bfin/c_ldstpmod_ld_dr_hi.s new file mode 100644 index 0000000000000..982444eb448b2 --- /dev/null +++ b/tests/tcg/bfin/c_ldstpmod_ld_dr_hi.s @@ -0,0 +1,411 @@ +//Original:testcases/core/c_ldstpmod_ld_dr_hi/c_ldstpmod_ld_dr_hi.dsp +// Spec Reference: c_ldstpmod load dr hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_2, 0x04; + loadsym p2, DATA_ADDR_3, 0x04; + loadsym i1, DATA_ADDR_4, 0x04; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym p5, DATA_ADDR_1, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + + R0.H = W [ P1 ]; + R1.H = W [ P1 ]; + R2.H = W [ P1 ]; + R3.H = W [ P1 ]; + R4.H = W [ P1 ]; + R5.H = W [ P1 ]; + R6.H = W [ P1 ]; + R7.H = W [ P1 ]; + CHECKREG r0, 0x26270000; + CHECKREG r1, 0x26270000; + CHECKREG r2, 0x26270000; + CHECKREG r3, 0x26270000; + CHECKREG r4, 0x26270000; + CHECKREG r5, 0x26270000; + CHECKREG r6, 0x26270000; + CHECKREG r7, 0x26270000; + + R0.H = W [ P2 ]; + R1.H = W [ P2 ]; + R2.H = W [ P2 ]; + R3.H = W [ P2 ]; + R4.H = W [ P2 ]; + R5.H = W [ P2 ]; + R6.H = W [ P2 ]; + R7.H = W [ P2 ]; + CHECKREG r0, 0x46470000; + CHECKREG r1, 0x46470000; + CHECKREG r2, 0x46470000; + CHECKREG r3, 0x46470000; + CHECKREG r4, 0x46470000; + CHECKREG r5, 0x46470000; + CHECKREG r6, 0x46470000; + CHECKREG r7, 0x46470000; + + R0.H = W [ P3 ]; + R1.H = W [ P3 ]; + R2.H = W [ P3 ]; + R3.H = W [ P3 ]; + R4.H = W [ P3 ]; + R5.H = W [ P3 ]; + R6.H = W [ P3 ]; + R7.H = W [ P3 ]; + CHECKREG r0, 0x66670000; + CHECKREG r1, 0x66670000; + CHECKREG r2, 0x66670000; + CHECKREG r3, 0x66670000; + CHECKREG r4, 0x66670000; + CHECKREG r5, 0x66670000; + CHECKREG r6, 0x66670000; + CHECKREG r7, 0x66670000; + + R0.H = W [ P4 ]; + R1.H = W [ P4 ]; + R2.H = W [ P4 ]; + R3.H = W [ P4 ]; + R4.H = W [ P4 ]; + R5.H = W [ P4 ]; + R6.H = W [ P4 ]; + R7.H = W [ P4 ]; + CHECKREG r0, 0x8A8B0000; + CHECKREG r1, 0x8A8B0000; + CHECKREG r2, 0x8A8B0000; + CHECKREG r3, 0x8A8B0000; + CHECKREG r4, 0x8A8B0000; + CHECKREG r5, 0x8A8B0000; + CHECKREG r6, 0x8A8B0000; + CHECKREG r7, 0x8A8B0000; + + R0.H = W [ P5 ]; + R1.H = W [ P5 ]; + R2.H = W [ P5 ]; + R3.H = W [ P5 ]; + R4.H = W [ P5 ]; + R5.H = W [ P5 ]; + R6.H = W [ P5 ]; + R7.H = W [ P5 ]; + CHECKREG r0, 0x0A0B0000; + CHECKREG r1, 0x0A0B0000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x0A0B0000; + CHECKREG r4, 0x0A0B0000; + CHECKREG r5, 0x0A0B0000; + CHECKREG r6, 0x0A0B0000; + CHECKREG r7, 0x0A0B0000; + + R0.H = W [ SP ]; + R1.H = W [ SP ]; + R2.H = W [ SP ]; + R3.H = W [ SP ]; + R4.H = W [ SP ]; + R5.H = W [ SP ]; + R6.H = W [ SP ]; + R7.H = W [ SP ]; + CHECKREG r0, 0x8E8F0000; + CHECKREG r1, 0x8E8F0000; + CHECKREG r2, 0x8E8F0000; + CHECKREG r3, 0x8E8F0000; + CHECKREG r4, 0x8E8F0000; + CHECKREG r5, 0x8E8F0000; + CHECKREG r6, 0x8E8F0000; + CHECKREG r7, 0x8E8F0000; + + R0.H = W [ FP ]; + R1.H = W [ FP ]; + R2.H = W [ FP ]; + R3.H = W [ FP ]; + R4.H = W [ FP ]; + R5.H = W [ FP ]; + R6.H = W [ FP ]; + R7.H = W [ FP ]; + CHECKREG r0, 0x0A0B0000; + CHECKREG r1, 0x0A0B0000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x0A0B0000; + CHECKREG r4, 0x0A0B0000; + CHECKREG r5, 0x0A0B0000; + CHECKREG r6, 0x0A0B0000; + CHECKREG r7, 0x0A0B0000; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstpmod_ld_dr_lo.s b/tests/tcg/bfin/c_ldstpmod_ld_dr_lo.s new file mode 100644 index 0000000000000..e399a240abddb --- /dev/null +++ b/tests/tcg/bfin/c_ldstpmod_ld_dr_lo.s @@ -0,0 +1,410 @@ +//Original:testcases/core/c_ldstpmod_ld_dr_lo/c_ldstpmod_ld_dr_lo.dsp +// Spec Reference: c_ldstpmod load dr lo +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS(0); +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_2, 0x04; + loadsym p2, DATA_ADDR_3, 0x04; + loadsym i1, DATA_ADDR_4, 0x04; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym p5, DATA_ADDR_1, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + + R0.L = W [ P1 ]; + R1.L = W [ P1 ]; + R2.L = W [ P1 ]; + R3.L = W [ P1 ]; + R4.L = W [ P1 ]; + R5.L = W [ P1 ]; + R6.L = W [ P1 ]; + R7.L = W [ P1 ]; + CHECKREG r0, 0x00002627; + CHECKREG r1, 0x00002627; + CHECKREG r2, 0x00002627; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00002627; + CHECKREG r5, 0x00002627; + CHECKREG r6, 0x00002627; + CHECKREG r7, 0x00002627; + + R0.L = W [ P2 ]; + R1.L = W [ P2 ]; + R2.L = W [ P2 ]; + R3.L = W [ P2 ]; + R4.L = W [ P2 ]; + R5.L = W [ P2 ]; + R6.L = W [ P2 ]; + R7.L = W [ P2 ]; + CHECKREG r0, 0x00004647; + CHECKREG r1, 0x00004647; + CHECKREG r2, 0x00004647; + CHECKREG r3, 0x00004647; + CHECKREG r4, 0x00004647; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00004647; + CHECKREG r7, 0x00004647; + + R0.L = W [ P3 ]; + R1.L = W [ P3 ]; + R2.L = W [ P3 ]; + R3.L = W [ P3 ]; + R4.L = W [ P3 ]; + R5.L = W [ P3 ]; + R6.L = W [ P3 ]; + R7.L = W [ P3 ]; + CHECKREG r0, 0x00006667; + CHECKREG r1, 0x00006667; + CHECKREG r2, 0x00006667; + CHECKREG r3, 0x00006667; + CHECKREG r4, 0x00006667; + CHECKREG r5, 0x00006667; + CHECKREG r6, 0x00006667; + CHECKREG r7, 0x00006667; + + R0.L = W [ P4 ]; + R1.L = W [ P4 ]; + R2.L = W [ P4 ]; + R3.L = W [ P4 ]; + R4.L = W [ P4 ]; + R5.L = W [ P4 ]; + R6.L = W [ P4 ]; + R7.L = W [ P4 ]; + CHECKREG r0, 0x00008A8B; + CHECKREG r1, 0x00008A8B; + CHECKREG r2, 0x00008A8B; + CHECKREG r3, 0x00008A8B; + CHECKREG r4, 0x00008A8B; + CHECKREG r5, 0x00008A8B; + CHECKREG r6, 0x00008A8B; + CHECKREG r7, 0x00008A8B; + + R0.L = W [ P5 ]; + R1.L = W [ P5 ]; + R2.L = W [ P5 ]; + R3.L = W [ P5 ]; + R4.L = W [ P5 ]; + R5.L = W [ P5 ]; + R6.L = W [ P5 ]; + R7.L = W [ P5 ]; + CHECKREG r0, 0x00000A0B; + CHECKREG r1, 0x00000A0B; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000A0B; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000A0B; + CHECKREG r6, 0x00000A0B; + CHECKREG r7, 0x00000A0B; + + R0.L = W [ SP ]; + R1.L = W [ SP ]; + R2.L = W [ SP ]; + R3.L = W [ SP ]; + R4.L = W [ SP ]; + R5.L = W [ SP ]; + R6.L = W [ SP ]; + R7.L = W [ SP ]; + CHECKREG r0, 0x00008E8F; + CHECKREG r1, 0x00008E8F; + CHECKREG r2, 0x00008E8F; + CHECKREG r3, 0x00008E8F; + CHECKREG r4, 0x00008E8F; + CHECKREG r5, 0x00008E8F; + CHECKREG r6, 0x00008E8F; + CHECKREG r7, 0x00008E8F; + + R0.L = W [ FP ]; + R1.L = W [ FP ]; + R2.L = W [ FP ]; + R3.L = W [ FP ]; + R4.L = W [ FP ]; + R5.L = W [ FP ]; + R6.L = W [ FP ]; + R7.L = W [ FP ]; + CHECKREG r0, 0x00000A0B; + CHECKREG r1, 0x00000A0B; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000A0B; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000A0B; + CHECKREG r6, 0x00000A0B; + CHECKREG r7, 0x00000A0B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstpmod_ld_dreg.s b/tests/tcg/bfin/c_ldstpmod_ld_dreg.s new file mode 100644 index 0000000000000..cfcdf1dff3e9c --- /dev/null +++ b/tests/tcg/bfin/c_ldstpmod_ld_dreg.s @@ -0,0 +1,462 @@ +//Original:testcases/core/c_ldstpmod_ld_dreg/c_ldstpmod_ld_dreg.dsp +// Spec Reference: c_ldstpmod load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0008; + FP = 0x0008; + SP = 0x000c; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + R0 = [ P5 ++ P3 ]; + R1 = [ P5 ++ P1 ]; + R2 = [ P5 ++ P2 ]; + R3 = [ P5 ++ P3 ]; + R4 = [ P5 ++ P4 ]; + R5 = [ P5 ++ SP ]; + R6 = [ P5 ++ FP ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x18191A1B; + CHECKREG r6, 0x55667788; + +// initial values + P5 = 0x0000; + P2 = 0x0004; + P3 = 0x0008; + P4 = 0x0008; + FP = 0x000c; + SP = 0x000c; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = [ P1 ++ P5 ]; + R1 = [ P1 ++ P3 ]; + R2 = [ P1 ++ P2 ]; + R3 = [ P1 ++ P3 ]; + R4 = [ P1 ++ P4 ]; + R5 = [ P1 ++ SP ]; + R6 = [ P1 ++ FP ]; + CHECKREG r0, 0x04050607; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x0C0D0E0F; + CHECKREG r3, 0x10111213; + CHECKREG r4, 0x18191A1B; + CHECKREG r5, 0x11223344; + CHECKREG r6, 0x74757677; + +// initial values + P5 = 0x0000; + P1 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0008; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + R0 = [ P2 ++ P5 ]; + R1 = [ P2 ++ P1 ]; + R2 = [ P2 ++ P4 ]; + R3 = [ P2 ++ P3 ]; + R4 = [ P2 ++ P4 ]; + R5 = [ P2 ++ SP ]; + R6 = [ P2 ++ FP ]; + CHECKREG r0, 0x40414243; + CHECKREG r1, 0x40414243; + CHECKREG r2, 0x44454647; + CHECKREG r3, 0x48494A4B; + CHECKREG r4, 0x4C4D4E4F; + CHECKREG r5, 0x50515253; + CHECKREG r6, 0x54555657; + +// initial values + P5 = 0x0010; + P1 = 0x0004; + P2 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = [ P3 ++ P5 ]; + R1 = [ P3 ++ P1 ]; + R2 = [ P3 ++ P2 ]; + R3 = [ P3 ++ P1 ]; + R4 = [ P3 ++ P4 ]; + R5 = [ P3 ++ SP ]; + R6 = [ P3 ++ FP ]; + CHECKREG r0, 0x04050607; + CHECKREG r1, 0x14151617; + CHECKREG r2, 0x18191A1B; + CHECKREG r3, 0x1C1D1E1F; + CHECKREG r4, 0x11223344; + CHECKREG r5, 0x55667788; + CHECKREG r6, 0x99717273; + +// initial values + P5 = 0x0004; + P1 = 0x0008; + P2 = 0x000C; + P3 = 0x0004; + FP = 0x0008; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_2, 0x04; + P3 = I1; SP = I3; + + R0 = [ P4 ++ P5 ]; + R1 = [ P4 ++ P1 ]; + R2 = [ P4 ++ P2 ]; + R3 = [ P4 ++ P3 ]; + R4 = [ P4 ++ P2 ]; + R5 = [ P4 ++ SP ]; + R6 = [ P4 ++ FP ]; + CHECKREG r0, 0x24252627; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x30313233; + CHECKREG r3, 0x3C3D3E3F; + CHECKREG r4, 0x91929394; + CHECKREG r5, 0xA5A6A7A8; + CHECKREG r6, 0xB3B4B5B6; + +// initial values + P5 = 0x0000; + P1 = 0x0010; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = [ FP ++ P5 ]; + R1 = [ FP ++ P1 ]; + R2 = [ FP ++ P2 ]; + R3 = [ FP ++ P3 ]; + R4 = [ FP ++ P4 ]; + R5 = [ FP ++ SP ]; + R6 = [ FP ++ SP ]; + CHECKREG r0, 0x04050607; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x14151617; + CHECKREG r3, 0x18191A1B; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r5, 0x11223344; + CHECKREG r6, 0x99717273; + +// initial values + P5 = 0x0000; + P1 = 0x0004; + P2 = 0x0008; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_1, 0x08; + P3 = I1; SP = I3; + + R0 = [ SP ++ P5 ]; + R1 = [ SP ++ P1 ]; + R2 = [ SP ++ P2 ]; + R3 = [ SP ++ P3 ]; + R4 = [ SP ++ P4 ]; + R5 = [ SP ++ FP ]; + R6 = [ SP ++ FP ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x08090A0B; + CHECKREG r2, 0x0C0D0E0F; + CHECKREG r3, 0x14151617; + CHECKREG r4, 0x18191A1B; + CHECKREG r5, 0x1C1D1E1F; + CHECKREG r6, 0x11223344; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstpmod_ld_h_xh.s b/tests/tcg/bfin/c_ldstpmod_ld_h_xh.s new file mode 100644 index 0000000000000..c3c4eda228348 --- /dev/null +++ b/tests/tcg/bfin/c_ldstpmod_ld_h_xh.s @@ -0,0 +1,458 @@ +//Original:testcases/core/c_ldstpmod_ld_h_xh/c_ldstpmod_ld_h_xh.dsp +// Spec Reference: c_ldstpmod load dreg h & xh +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R0 = W [ P5 ++ P1 ] (Z); + R1 = W [ P5 ++ P1 ] (Z); + R2 = W [ P5 ++ P2 ] (Z); + R3 = W [ P5 ++ P3 ] (Z); + R4 = W [ P5 ++ P4 ] (Z); + R5 = W [ P5 ++ SP ] (Z); + R6 = W [ P5 ++ FP ] (Z); + CHECKREG r0, 0x0000A203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x0000B607; + CHECKREG r3, 0x00009405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x0000CE0F; + +// initial values + P5 = 0x0002; + P2 = 0x0002; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R0 = W [ P1 ++ P5 ] (X); + R1 = W [ P1 ++ P2 ] (X); + R2 = W [ P1 ++ P2 ] (X); + R3 = W [ P1 ++ P3 ] (X); + R4 = W [ P1 ++ P4 ] (X); + R5 = W [ P1 ++ SP ] (X); + R6 = W [ P1 ++ FP ] (X); + CHECKREG r0, 0xFFFFA203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0xFFFFB607; + CHECKREG r3, 0xFFFF9405; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0xFFFFAC0D; + CHECKREG r6, 0x00001011; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_3, 0x06; + P3 = I1; SP = I3; + R0 = W [ P2 ++ P5 ] (Z); + R1 = W [ P2 ++ P1 ] (Z); + R2 = W [ P2 ++ P2 ] (Z); + R3 = W [ P2 ++ P3 ] (Z); + R4 = W [ P2 ++ P4 ] (Z); + R5 = W [ P2 ++ SP ] (Z); + R6 = W [ P2 ++ FP ] (Z); + CHECKREG r0, 0x00008445; + CHECKREG r1, 0x00004A4B; + CHECKREG r2, 0x00004849; + CHECKREG r3, 0x00004849; + CHECKREG r4, 0x00004E4F; + CHECKREG r5, 0x00005253; + CHECKREG r6, 0x00005051; + +// initial values + P5 = 0x0004; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0004; + FP = 0x1002 (X); + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x02; + P3 = I1; SP = I3; + R0 = W [ P3 ++ P5 ] (X); + R1 = W [ P3 ++ P1 ] (X); + R2 = W [ P3 ++ P2 ] (X); + R3 = W [ P3 ++ P3 ] (X); + R4 = W [ P3 ++ P4 ] (X); + R5 = W [ P3 ++ SP ] (X); + R6 = W [ P3 ++ FP ] (X); + CHECKREG r0, 0x00000001; + CHECKREG r1, 0xFFFF9405; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0xFFFFAC0D; + CHECKREG r6, 0x00001213; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + R0 = W [ P4 ++ P5 ] (Z); + R1 = W [ P4 ++ P1 ] (X); + R2 = W [ P4 ++ P2 ] (X); + R3 = W [ P4 ++ P3 ] (Z); + R4 = W [ P4 ++ P4 ] (Z); + R5 = W [ P4 ++ SP ] (X); + R6 = W [ P4 ++ FP ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00002021; + CHECKREG r2, 0x00002627; + CHECKREG r3, 0x0000A425; + CHECKREG r4, 0x00002A2B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0xFFFF8829; + +// initial values + P5 = 0x0000; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0x02; + P3 = I1; SP = I3; + R0 = W [ FP ++ P5 ] (X); + R1 = W [ FP ++ P1 ] (X); + R2 = W [ FP ++ P2 ] (X); + R3 = W [ FP ++ P3 ] (X); + R4 = W [ FP ++ P4 ] (Z); + R5 = W [ FP ++ SP ] (Z); + R6 = W [ FP ++ FP ] (X); + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0xFFFFB607; + CHECKREG r3, 0xFFFF9405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0xFFFFAC0D; + +// initial values + P5 = 0x0000; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = W [ SP ++ P5 ] (Z); + R1 = W [ SP ++ P1 ] (X); + R2 = W [ SP ++ P2 ] (Z); + R3 = W [ SP ++ P3 ] (X); + R4 = W [ SP ++ P4 ] (Z); + R5 = W [ SP ++ P1 ] (X); + R6 = W [ SP ++ FP ] (Z); + CHECKREG r0, 0x0000B607; + CHECKREG r1, 0xFFFFB607; + CHECKREG r2, 0x00009405; + CHECKREG r3, 0x00000A0B; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0xFFFFCE0F; + CHECKREG r6, 0x0000AC0D; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + .space (0x2000); + +DATA_ADDR_1: + .dd 0x0001a203 + .dd 0x9405b607 + .dd 0x08090A0B + .dd 0xaC0DcE0F + .dd 0x10111213 + .dd 0xb415c617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0xa5060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0xc8192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0xb0313233 + .dd 0x34353637 + .dd 0xd8394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0xf0515253 + .dd 0x54555657 + .dd 0xe8596061 + .dd 0x62636465 + .dd 0xf6676869 + .dd 0x74555657 + .dd 0xa8596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0xa4252627 + .dd 0x88292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x84454647 + .dd 0x48494A4B + .dd 0x9C4D4E4F + .dd 0x50515253 + .dd 0xa4555657 + .dd 0xb8595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x90616263 + .dd 0x64656667 + .dd 0xa8696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0xd4757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x08898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x54959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0xa4050607 + .dd 0x08090A0B + .dd 0xfC0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x98191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x74252627 + .dd 0x28292A2B + .dd 0x8C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x98393A3B + .dd 0x3C3D3E3F + .dd 0xb0414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0xdC4D4E4F + .dd 0x50515253 + .dd 0x94555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0xf0616263 + .dd 0xf4656667 + .dd 0xf8696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x10919293 + .dd 0x24959697 + .dd 0x38999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0x54A5A6A7 + .dd 0x68A9AAAB + .dd 0x7CADAEAF + .dd 0xB0B1B2B3 + .dd 0x84B5B6B7 + .dd 0xB8B9BABB + .dd 0x4CBDBEBF + .dd 0xC0C1C2C3 + .dd 0x34C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0x20D1D2D3 + .dd 0xD4D5D6D7 + .dd 0x18D9DADB + .dd 0xDCDDDEDF + .dd 0x00E1E2E3 + .dd 0xE4E5E6E7 + .dd 0x18E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstpmod_ld_lohi.s b/tests/tcg/bfin/c_ldstpmod_ld_lohi.s new file mode 100644 index 0000000000000..4223e59809960 --- /dev/null +++ b/tests/tcg/bfin/c_ldstpmod_ld_lohi.s @@ -0,0 +1,462 @@ +//Original:testcases/core/c_ldstpmod_ld_lohi/c_ldstpmod_ld_lohi.dsp +// Spec Reference: c_ldstpmod load dreg lo & hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + R0.L = W [ P5 ++ P1 ]; + R1.L = W [ P5 ++ P1 ]; + R2.L = W [ P5 ++ P2 ]; + R3.L = W [ P5 ++ P3 ]; + R4.L = W [ P5 ++ P4 ]; + R5.L = W [ P5 ++ SP ]; + R6.L = W [ P5 ++ FP ]; + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00000E0F; + +// initial values + P5 = 0x0000; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + + R0.H = W [ P1 ++ P5 ]; + R1.H = W [ P1 ++ P2 ]; + R2.H = W [ P1 ++ P2 ]; + R3.H = W [ P1 ++ P3 ]; + R4.H = W [ P1 ++ P4 ]; + R5.H = W [ P1 ++ SP ]; + R6.H = W [ P1 ++ FP ]; + CHECKREG r0, 0x22230203; + CHECKREG r1, 0x22230001; + CHECKREG r2, 0x20210607; + CHECKREG r3, 0x26270405; + CHECKREG r4, 0x24250A0B; + CHECKREG r5, 0x2A2B0809; + CHECKREG r6, 0x28290E0F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x02; + P3 = I1; SP = I3; + + R0.L = W [ P2 ++ P5 ]; + R0.H = W [ P2 ++ P1 ]; + R1.L = W [ P2 ++ P1 ]; + R1.H = W [ P2 ++ P3 ]; + R2.H = W [ P2 ++ P4 ]; + R2.L = W [ P2 ++ SP ]; + R3.L = W [ P2 ++ FP ]; + CHECKREG r0, 0x26272021; + CHECKREG r1, 0x2A2B2425; + CHECKREG r2, 0x28292E2F; + CHECKREG r3, 0x26272C2D; + CHECKREG r4, 0x24250A0B; + CHECKREG r5, 0x2A2B0809; + CHECKREG r6, 0x28290E0F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + R3.L = W [ P3 ++ P5 ]; + R3.H = W [ P3 ++ P1 ]; + R4.L = W [ P3 ++ P2 ]; + R5.H = W [ P3 ++ P1 ]; + R5.L = W [ P3 ++ P4 ]; + R6.H = W [ P3 ++ SP ]; + R6.L = W [ P3 ++ FP ]; + CHECKREG r0, 0x26272021; + CHECKREG r1, 0x2A2B2425; + CHECKREG r2, 0x28292E2F; + CHECKREG r3, 0x40414243; + CHECKREG r4, 0x24254647; + CHECKREG r5, 0x44454A4B; + CHECKREG r6, 0x48494E4F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0.H = W [ P4 ++ P5 ]; + R0.L = W [ P4 ++ P1 ]; + R1.L = W [ P4 ++ P2 ]; + R1.H = W [ P4 ++ P3 ]; + R2.H = W [ P4 ++ P4 ]; + R3.L = W [ P4 ++ SP ]; + R3.H = W [ P4 ++ FP ]; + CHECKREG r0, 0x62636061; + CHECKREG r1, 0x64656667; + CHECKREG r2, 0x6A6B2E2F; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x24254647; + CHECKREG r5, 0x44454A4B; + CHECKREG r6, 0x48494E4F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + + R0.H = W [ FP ++ P5 ]; + R1.L = W [ FP ++ P1 ]; + R2.H = W [ FP ++ P2 ]; + R3.H = W [ FP ++ P3 ]; + R4.L = W [ FP ++ P4 ]; + R5.H = W [ FP ++ SP ]; + R6.L = W [ FP ++ P1 ]; + CHECKREG r0, 0x82836061; + CHECKREG r1, 0x64658081; + CHECKREG r2, 0x86872E2F; + CHECKREG r3, 0x84856A6B; + CHECKREG r4, 0x24258A8B; + CHECKREG r5, 0x88894A4B; + CHECKREG r6, 0x48498E8F; + +// initial values + P5 = 0x0000; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x00; + P3 = I1; SP = I3; + + R0.L = W [ SP ++ P5 ]; + R1.H = W [ SP ++ P1 ]; + R2.H = W [ SP ++ P2 ]; + R3.L = W [ SP ++ P3 ]; + R4.H = W [ SP ++ P4 ]; + R5.L = W [ SP ++ P5 ]; + R6.H = W [ SP ++ FP ]; + CHECKREG r0, 0x82830203; + CHECKREG r1, 0x02038081; + CHECKREG r2, 0x00012E2F; + CHECKREG r3, 0x84850607; + CHECKREG r4, 0x04058A8B; + CHECKREG r5, 0x88890A0B; + CHECKREG r6, 0x0A0B8E8F; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstpmod_st_dr_hi.s b/tests/tcg/bfin/c_ldstpmod_st_dr_hi.s new file mode 100644 index 0000000000000..4e19e60736be4 --- /dev/null +++ b/tests/tcg/bfin/c_ldstpmod_st_dr_hi.s @@ -0,0 +1,400 @@ +//Original:testcases/core/c_ldstpmod_st_dr_hi/c_ldstpmod_st_dr_hi.dsp +// Spec Reference: c_ldstpmod store dreg hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x0a; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + W [ P1 ] = R1.H; + W [ P2 ] = R2.H; + W [ P3 ] = R3.H; + W [ P4 ] = R4.H; + W [ P5 ] = R5.H; + W [ SP ] = R6.H; + W [ FP ] = R0.H; + R6.H = W [ P1 ]; + R5.H = W [ P2 ]; + R4.H = W [ P3 ]; + R3.H = W [ P4 ]; + R2.H = W [ P5 ]; + R0.H = W [ SP ]; + R1.H = W [ FP ]; + CHECKREG r0, 0xC0095000; + CHECKREG r1, 0x600F6001; + CHECKREG r2, 0xB00A7002; + CHECKREG r3, 0xA00B8003; + CHECKREG r4, 0x900C9004; + CHECKREG r5, 0x800DA005; + CHECKREG r6, 0x700EB006; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x0c; + loadsym p2, DATA_ADDR_2, 0x0a; + loadsym i1, DATA_ADDR_3, 0x08; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x02; + loadsym i3, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + W [ P1 ] = R2.H; + W [ P2 ] = R3.H; + W [ P3 ] = R4.H; + W [ P4 ] = R5.H; + W [ P5 ] = R6.H; + W [ SP ] = R7.H; + W [ FP ] = R1.H; + R1.L = W [ P1 ]; + R2.L = W [ P2 ]; + R3.L = W [ P3 ]; + R4.L = W [ P4 ]; + R5.L = W [ P5 ]; + R6.L = W [ SP ]; + R0.L = W [ FP ]; + CHECKREG r0, 0x105F204E; + CHECKREG r1, 0x204E3003; + CHECKREG r2, 0x3003402C; + CHECKREG r3, 0x402C501B; + CHECKREG r4, 0x501B600A; + CHECKREG r5, 0x600A7019; + CHECKREG r6, 0x7019D028; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x12345675; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x10; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x00; + loadsym p4, DATA_ADDR_4, 0x08; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x06; + loadsym i3, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + W [ P1 ] = R5.H; + W [ P2 ] = R6.H; + W [ P3 ] = R7.H; + W [ P4 ] = R0.H; + W [ P5 ] = R1.H; + W [ SP ] = R2.H; + W [ FP ] = R3.H; + R5.H = W [ P1 ]; + R4.H = W [ P2 ]; + R3.H = W [ P3 ]; + R2.H = W [ P4 ]; + R1.H = W [ P5 ]; + R0.H = W [ SP ]; + R6.H = W [ FP ]; + CHECKREG r0, 0x30BD50B0; + CHECKREG r1, 0x20BE60B1; + CHECKREG r2, 0x10BF70B2; + CHECKREG r3, 0x80B880B3; + CHECKREG r4, 0x70B990B4; + CHECKREG r5, 0x12345675; + CHECKREG r6, 0x40BCB0B6; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstpmod_st_dr_lo.s b/tests/tcg/bfin/c_ldstpmod_st_dr_lo.s new file mode 100644 index 0000000000000..b005545e86c8a --- /dev/null +++ b/tests/tcg/bfin/c_ldstpmod_st_dr_lo.s @@ -0,0 +1,401 @@ +//Original:testcases/core/c_ldstpmod_st_dr_lo/c_ldstpmod_st_dr_lo.dsp +// Spec Reference: c_ldstpmod store dreg lo +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x0a; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + + W [ P1 ] = R1.L; + W [ P2 ] = R2.L; + W [ P3 ] = R3.L; + W [ P4 ] = R4.L; + W [ P5 ] = R5.L; + W [ SP ] = R6.L; + W [ FP ] = R0.L; + R6.L = W [ P1 ]; + R5.L = W [ P2 ]; + R4.L = W [ P3 ]; + R3.L = W [ P4 ]; + R2.L = W [ P5 ]; + R0.L = W [ SP ]; + R1.L = W [ FP ]; + CHECKREG r0, 0x600FB006; + CHECKREG r1, 0x700E5000; + CHECKREG r2, 0x800DA005; + CHECKREG r3, 0x900C9004; + CHECKREG r4, 0xA00B8003; + CHECKREG r5, 0xB00A7002; + CHECKREG r6, 0xC0096001; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x0c; + loadsym p2, DATA_ADDR_2, 0x0a; + loadsym i1, DATA_ADDR_3, 0x08; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x02; + loadsym i3, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + W [ P1 ] = R2.L; + W [ P2 ] = R3.L; + W [ P3 ] = R4.L; + W [ P4 ] = R5.L; + W [ P5 ] = R6.L; + W [ SP ] = R7.L; + W [ FP ] = R1.L; + R1.L = W [ P1 ]; + R2.L = W [ P2 ]; + R3.L = W [ P3 ]; + R4.L = W [ P4 ]; + R5.L = W [ P5 ]; + R6.L = W [ SP ]; + R0.L = W [ FP ]; + CHECKREG r0, 0x105F60A1; + CHECKREG r1, 0x204E70A2; + CHECKREG r2, 0x300380A3; + CHECKREG r3, 0x402C90A4; + CHECKREG r4, 0x501BA0A5; + CHECKREG r5, 0x600AB0A6; + CHECKREG r6, 0x7019C0A7; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x10; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x00; + loadsym p4, DATA_ADDR_4, 0x08; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x06; + loadsym i3, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + W [ P1 ] = R5.L; + W [ P2 ] = R6.L; + W [ P3 ] = R7.L; + W [ P4 ] = R0.L; + W [ P5 ] = R1.L; + W [ SP ] = R2.L; + W [ FP ] = R3.L; + R5.L = W [ P1 ]; + R4.L = W [ P2 ]; + R3.L = W [ P3 ]; + R2.L = W [ P4 ]; + R1.L = W [ P5 ]; + R0.L = W [ SP ]; + R6.L = W [ FP ]; + CHECKREG r0, 0x10BF70B2; + CHECKREG r1, 0x20BE60B1; + CHECKREG r2, 0x30BD50B0; + CHECKREG r3, 0x40BCC0B7; + CHECKREG r4, 0x55BBB0B6; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B980B3; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstpmod_st_dreg.s b/tests/tcg/bfin/c_ldstpmod_st_dreg.s new file mode 100644 index 0000000000000..e1ec36fe85d8d --- /dev/null +++ b/tests/tcg/bfin/c_ldstpmod_st_dreg.s @@ -0,0 +1,623 @@ +//Original:testcases/core/c_ldstpmod_st_dreg/c_ldstpmod_st_dreg.dsp +// Spec Reference: c_ldstpmod store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + [ P5 ++ P1 ] = R0; + [ P5 ++ P1 ] = R1; + [ P5 ++ P2 ] = R2; + [ P5 ++ P3 ] = R3; + [ P5 ++ P4 ] = R4; + [ P5 ++ SP ] = R5; + [ P5 ++ FP ] = R6; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + R6 = [ P5 ++ P1 ]; + R5 = [ P5 ++ P1 ]; + R4 = [ P5 ++ P2 ]; + R3 = [ P5 ++ P3 ]; + R2 = [ P5 ++ P4 ]; + R0 = [ P5 ++ SP ]; + R1 = [ P5 ++ FP ]; + CHECKREG r0, 0xB00AA005; + CHECKREG r1, 0xC009B006; + CHECKREG r2, 0xA00B9004; + CHECKREG r3, 0x900C8003; + CHECKREG r4, 0x800D7002; + CHECKREG r5, 0x700E6001; + CHECKREG r6, 0x600F5000; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + P5 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0008; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + [ P1 ++ P5 ] = R0; + [ P1 ++ P5 ] = R1; + [ P1 ++ P2 ] = R2; + [ P1 ++ P3 ] = R3; + [ P1 ++ P4 ] = R4; + [ P1 ++ SP ] = R5; + [ P1 ++ FP ] = R6; + P5 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0008; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R6 = [ P1 ++ P5 ]; + R5 = [ P1 ++ P5 ]; + R4 = [ P1 ++ P2 ]; + R3 = [ P1 ++ P3 ]; + R2 = [ P1 ++ P4 ]; + R0 = [ P1 ++ SP ]; + R1 = [ P1 ++ FP ]; + CHECKREG r0, 0x600AA0A5; + CHECKREG r1, 0x7019B0A6; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P5 = 0x0004; + P1 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + [ P2 ++ P5 ] = R0; + [ P2 ++ P1 ] = R1; + [ P2 ++ P1 ] = R2; + [ P2 ++ P3 ] = R3; + [ P2 ++ P4 ] = R4; + [ P2 ++ SP ] = R5; + [ P2 ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + R3 = [ P2 ++ P5 ]; + R4 = [ P2 ++ P1 ]; + R0 = [ P2 ++ P1 ]; + R1 = [ P2 ++ P3 ]; + R2 = [ P2 ++ P4 ]; + R5 = [ P2 ++ SP ]; + R6 = [ P2 ++ FP ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + [ P3 ++ P5 ] = R0; + [ P3 ++ P1 ] = R1; + [ P3 ++ P2 ] = R2; + [ P3 ++ P1 ] = R3; + [ P3 ++ P4 ] = R4; + [ P3 ++ SP ] = R5; + [ P3 ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + R6 = [ P3 ++ P5 ]; + R5 = [ P3 ++ P1 ]; + R4 = [ P3 ++ P2 ]; + R3 = [ P3 ++ P1 ]; + R2 = [ P3 ++ P4 ]; + R0 = [ P3 ++ SP ]; + R1 = [ P3 ++ FP ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0x70C9B0C6; + CHECKREG r2, 0x50CB90C4; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x30C370C2; + CHECKREG r5, 0x20CE60C1; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + [ P4 ++ P5 ] = R0; + [ P4 ++ P1 ] = R1; + [ P4 ++ P2 ] = R2; + [ P4 ++ P3 ] = R3; + [ P4 ++ P1 ] = R4; + [ P4 ++ SP ] = R5; + [ P4 ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + R5 = [ P4 ++ P5 ]; + R6 = [ P4 ++ P1 ]; + R0 = [ P4 ++ P2 ]; + R1 = [ P4 ++ P3 ]; + R2 = [ P4 ++ P1 ]; + R3 = [ P4 ++ SP ]; + R4 = [ P4 ++ FP ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0xB0DAA0D5; + CHECKREG r4, 0xC0D9B0D6; + CHECKREG r5, 0x60DF50D0; + CHECKREG r6, 0x70DE60D1; + +// initial values + imm32 r0, 0x1e5f50e0; + imm32 r1, 0x2e4e60e1; + imm32 r2, 0x3e0370e2; + imm32 r3, 0x4e2c80e3; + imm32 r4, 0x5e1b90e4; + imm32 r5, 0x6e0aa0e5; + imm32 r6, 0x7e19b0e6; + imm32 r7, 0xde28c0e7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x00; + P3 = I1; SP = I3; + [ SP ++ P5 ] = R0; + [ SP ++ P1 ] = R1; + [ SP ++ P2 ] = R2; + [ SP ++ P3 ] = R3; + [ SP ++ P4 ] = R4; + [ SP ++ P1 ] = R5; + [ SP ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x00; + P3 = I1; SP = I3; + R6 = [ SP ++ P5 ]; + R5 = [ SP ++ P1 ]; + R4 = [ SP ++ P2 ]; + R3 = [ SP ++ P3 ]; + R2 = [ SP ++ P4 ]; + R0 = [ SP ++ P1 ]; + R1 = [ SP ++ FP ]; + CHECKREG r0, 0x6E0AA0E5; + CHECKREG r1, 0x7E19B0E6; + CHECKREG r2, 0x5E1B90E4; + CHECKREG r3, 0x4E2C80E3; + CHECKREG r4, 0x3E0370E2; + CHECKREG r5, 0x2E4E60E1; + CHECKREG r6, 0x1E5F50E0; + +// initial values + imm32 r0, 0x10ff50f0; + imm32 r1, 0x20fe60f1; + imm32 r2, 0x30fd70f2; + imm32 r3, 0x40fc80f3; + imm32 r4, 0x55fb90f4; + imm32 r5, 0x60faa0f5; + imm32 r6, 0x70f9b0f6; + imm32 r7, 0x80f8c0f7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x1004 (X); + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + [ FP ++ P5 ] = R0; + [ FP ++ P1 ] = R1; + [ FP ++ P2 ] = R2; + [ FP ++ P3 ] = R3; + [ FP ++ P4 ] = R4; + [ FP ++ SP ] = R5; + [ FP ++ P1 ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + R3 = [ FP ++ P5 ]; + R4 = [ FP ++ P1 ]; + R0 = [ FP ++ P2 ]; + R1 = [ FP ++ P3 ]; + R2 = [ FP ++ P4 ]; + R5 = [ FP ++ SP ]; + R6 = [ FP ++ P1 ]; + CHECKREG r0, 0x30FD70F2; + CHECKREG r1, 0x40FC80F3; + CHECKREG r2, 0x55FB90F4; + CHECKREG r3, 0x10FF50F0; + CHECKREG r4, 0x20FE60F1; + CHECKREG r5, 0x60FAA0F5; + CHECKREG r6, 0x70F9B0F6; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_ldstpmod_st_lohi.s b/tests/tcg/bfin/c_ldstpmod_st_lohi.s new file mode 100644 index 0000000000000..58990ad62a2c9 --- /dev/null +++ b/tests/tcg/bfin/c_ldstpmod_st_lohi.s @@ -0,0 +1,625 @@ +//Original:testcases/core/c_ldstpmod_st_lohi/c_ldstpmod_st_lohi.dsp +// Spec Reference: c_ldstpmod store dreg lo & hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0006; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + + W [ P5 ++ P1 ] = R0.L; + W [ P5 ++ P1 ] = R1.L; + W [ P5 ++ P2 ] = R2.L; + W [ P5 ++ P3 ] = R3.L; + W [ P5 ++ P4 ] = R4.L; + W [ P5 ++ SP ] = R5.L; + W [ P5 ++ FP ] = R6.L; + + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0006; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + + R6.L = W [ P5 ++ P1 ]; + R5.L = W [ P5 ++ P1 ]; + R4.L = W [ P5 ++ P2 ]; + R3.L = W [ P5 ++ P3 ]; + R2.L = W [ P5 ++ P4 ]; + R0.L = W [ P5 ++ SP ]; + R1.L = W [ P5 ++ FP ]; + CHECKREG r0, 0x600FA005; + CHECKREG r1, 0x700EB006; + CHECKREG r2, 0x800D9004; + CHECKREG r3, 0x900C8003; + CHECKREG r4, 0xA00B7002; + CHECKREG r5, 0xB00A6001; + CHECKREG r6, 0xC0095000; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x204EA0A5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + P5 = 0x0002; + P2 = 0x0002; + P3 = 0x0004; + P4 = 0x0002; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + W [ P1 ++ P5 ] = R0.H; + W [ P1 ++ P2 ] = R1.H; + W [ P1 ++ P2 ] = R2.H; + W [ P1 ++ P3 ] = R3.H; + W [ P1 ++ P4 ] = R4.H; + W [ P1 ++ SP ] = R5.H; + W [ P1 ++ FP ] = R6.H; + P5 = 0x0002; + P2 = 0x0002; + P3 = 0x0004; + P4 = 0x0002; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R6.H = W [ P1 ++ P5 ]; + R5.H = W [ P1 ++ P2 ]; + R4.H = W [ P1 ++ P2 ]; + R3.H = W [ P1 ++ P3 ]; + R2.H = W [ P1 ++ P4 ]; + R0.H = W [ P1 ++ SP ]; + R1.H = W [ P1 ++ FP ]; + CHECKREG r0, 0x204E50A0; + CHECKREG r1, 0x701960A1; + CHECKREG r2, 0x501B70A2; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300390A4; + CHECKREG r5, 0x204EA0A5; + CHECKREG r6, 0x105FB0A6; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x02; + P3 = I1; SP = I3; + W [ P2 ++ P5 ] = R0.L; + W [ P2 ++ P1 ] = R0.H; + W [ P2 ++ P2 ] = R2.H; + W [ P2 ++ P3 ] = R2.H; + W [ P2 ++ P4 ] = R4.L; + W [ P2 ++ SP ] = R4.H; + W [ P2 ++ FP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x02; + P3 = I1; SP = I3; + R3.L = W [ P2 ++ P5 ]; + R3.H = W [ P2 ++ P1 ]; + R0.L = W [ P2 ++ P2 ]; + R0.H = W [ P2 ++ P3 ]; + R2.L = W [ P2 ++ P4 ]; + R2.H = W [ P2 ++ SP ]; + R6.L = W [ P2 ++ FP ]; + CHECKREG r0, 0x30BD30BD; + CHECKREG r1, 0x20BE60B1; + CHECKREG r2, 0x2E2F2A2B; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x55BB90B4; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B955BB; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x02; + P3 = I1; SP = I3; + W [ P3 ++ P5 ] = R1.H; + W [ P3 ++ P1 ] = R1.L; + W [ P3 ++ P2 ] = R3.L; + W [ P3 ++ P2 ] = R3.H; + W [ P3 ++ P4 ] = R5.H; + W [ P3 ++ SP ] = R6.H; + W [ P3 ++ FP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x02; + P3 = I1; SP = I3; + R6.L = W [ P3 ++ P5 ]; + R6.H = W [ P3 ++ P1 ]; + R4.H = W [ P3 ++ P2 ]; + R4.L = W [ P3 ++ P2 ]; + R5.L = W [ P3 ++ P4 ]; + R5.H = W [ P3 ++ SP ]; + R1.L = W [ P3 ++ FP ]; + CHECKREG r0, 0x10CF50C0; + CHECKREG r1, 0x20CEB0C6; + CHECKREG r2, 0x30C370C2; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x80C340CC; + CHECKREG r5, 0x70C960CA; + CHECKREG r6, 0x60C120CE; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x02; + P3 = I1; SP = I3; + W [ P4 ++ P5 ] = R0.L; + W [ P4 ++ P1 ] = R1.H; + W [ P4 ++ P2 ] = R2.L; + W [ P4 ++ P3 ] = R3.H; + W [ P4 ++ P3 ] = R4.H; + W [ P4 ++ SP ] = R5.L; + W [ P4 ++ FP ] = R6.H; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x02; + P3 = I1; SP = I3; + R5.L = W [ P4 ++ P5 ]; + R6.L = W [ P4 ++ P1 ]; + R0.H = W [ P4 ++ P2 ]; + R1.L = W [ P4 ++ P3 ]; + R2.L = W [ P4 ++ P3 ]; + R3.H = W [ P4 ++ SP ]; + R4.H = W [ P4 ++ FP ]; + CHECKREG r0, 0x70D250D0; + CHECKREG r1, 0x70DE90DC; + CHECKREG r2, 0x80DDA0DB; + CHECKREG r3, 0xA0D580D3; + CHECKREG r4, 0xC0D990D4; + CHECKREG r5, 0xB0DA50D0; + CHECKREG r6, 0xC0D970DE; + +// initial values + imm32 r0, 0x1e5f50e0; + imm32 r1, 0x2e4e60e1; + imm32 r2, 0x3e0370e2; + imm32 r3, 0x4e2c80e3; + imm32 r4, 0x5e1b90e4; + imm32 r5, 0x6e0aa0e5; + imm32 r6, 0x7e19b0e6; + imm32 r7, 0xde28c0e7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0002; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x02; + P3 = I1; SP = I3; + W [ SP ++ P5 ] = R0.H; + W [ SP ++ P1 ] = R1.H; + W [ SP ++ P2 ] = R2.L; + W [ SP ++ P3 ] = R3.L; + W [ SP ++ P4 ] = R4.H; + W [ SP ++ FP ] = R5.H; + W [ SP ++ FP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x02; + P3 = I1; SP = I3; + R6.H = W [ SP ++ P5 ]; + R5.H = W [ SP ++ P1 ]; + R4.H = W [ SP ++ P2 ]; + R3.H = W [ SP ++ P3 ]; + R3.L = W [ SP ++ P4 ]; + R0.L = W [ SP ++ FP ]; + R1.L = W [ SP ++ FP ]; + CHECKREG r0, 0x1E5FB0E6; + CHECKREG r1, 0x2E4E1617; + CHECKREG r2, 0x3E0370E2; + CHECKREG r3, 0x80E35E1B; + CHECKREG r4, 0x70E290E4; + CHECKREG r5, 0x2E4EA0E5; + CHECKREG r6, 0x1E5FB0E6; + +// initial values + imm32 r0, 0x10ff50f0; + imm32 r1, 0x20fe60f1; + imm32 r2, 0x30fd70f2; + imm32 r3, 0x40fc80f3; + imm32 r4, 0x55fb90f4; + imm32 r5, 0x60faa0f5; + imm32 r6, 0x70f9b0f6; + imm32 r7, 0x80f8c0f7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + W [ FP ++ P5 ] = R0.L; + W [ FP ++ P1 ] = R1.H; + W [ FP ++ P2 ] = R2.H; + W [ FP ++ P3 ] = R3.H; + W [ FP ++ P4 ] = R4.L; + W [ FP ++ SP ] = R5.L; + W [ FP ++ SP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + R3.L = W [ FP ++ P5 ]; + R4.L = W [ FP ++ P1 ]; + R0.H = W [ FP ++ P2 ]; + R1.H = W [ FP ++ P3 ]; + R2.L = W [ FP ++ P4 ]; + R5.H = W [ FP ++ SP ]; + R6.H = W [ FP ++ SP ]; + CHECKREG r0, 0x30FD50F0; + CHECKREG r1, 0x40FC60F1; + CHECKREG r2, 0x30FD90F4; + CHECKREG r3, 0x40FC50F0; + CHECKREG r4, 0x55FB20FE; + CHECKREG r5, 0xA0F5A0F5; + CHECKREG r6, 0x9091B0F6; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/tests/tcg/bfin/c_linkage.s b/tests/tcg/bfin/c_linkage.s new file mode 100644 index 0000000000000..d7d673ed27b1d --- /dev/null +++ b/tests/tcg/bfin/c_linkage.s @@ -0,0 +1,60 @@ +//Original:testcases/core/c_linkage/c_linkage.dsp +// Spec Reference: linkage (link & unlnk) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS(0); + + loadsym sp, DATA_ADDR_1, 0x24; + p0 = sp; + + FP = 0x0064 (X); + R0 = 5; + RETS = R0; + + LINK 4; // push rets, push fp, fp=sp, sp=sp-framesize (4) + + R1 = 3; + RETS = R1; // initialize rets by a different value + + loadsym p1, SUBR + CALL ( P1 ); + + SP = 0x3333 (X); + + UNLINK; // sp = fp, fp = pop (old fp), rets = pop(old rets), + + R2 = RETS; // for checking + + CHECKREG r0, 0x00000005; + CHECKREG r1, 0x00000003; + CHECKREG r2, 0x00000005; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00001111; + CHECKREG r7, 0x00000000; + CHECKREG fp, 0x00000064; + CC = SP == P0; + if CC JUMP 1f; + fail; +1: + pass + +SUBR: // should jump here + R6.L = 0x1111; + RTS; + R7.L = 0x2222; // should not go here + RTS; + + .data +DATA_ADDR_1: +DATA: + .space (0x0100); + +// Stack Segments + + .space (0x100); +KSTACK: diff --git a/tests/tcg/bfin/c_logi2op_alshft_mix.s b/tests/tcg/bfin/c_logi2op_alshft_mix.s new file mode 100644 index 0000000000000..7e42664a90523 --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_alshft_mix.s @@ -0,0 +1,143 @@ +//Original:/testcases/core/c_logi2op_alshft_mix/c_logi2op_alshft_mix.dsp +// Spec Reference: Logi2op >>>=, >>=, <<= +# mach: bfin + +.include "testutils.inc" + start + +// Arithmetic >>>= : positive data +imm32 r0, 0x40000000; +imm32 r1, 0x01111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; +R0 >>>= 1; /* r0 = 0x20000000 */ +R1 >>>= 1; /* r1 = 0x00888888 */ +R2 >>>= 2; /* r2 = 0x08888888 */ +R3 >>>= 8; /* r3 = 0x00333333 */ +R4 >>>= 1; /* r4 = 0x22222222 */ +R5 >>>= 27; /* r5 = 0x0000000a */ +R6 >>>= 30; /* r5 = 0x00000001 */ +R7 >>>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x00888888; +CHECKREG r2, 0x08888888; +CHECKREG r3, 0x00333333; +CHECKREG r4, 0x22222222; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + + +// Arithmetic >>>= : negative data , +imm32 r0, 0x80000000; +imm32 r1, 0x81111111; +imm32 r2, 0xa2222222; +imm32 r3, 0xb3333333; +imm32 r4, 0xc4444444; +imm32 r5, 0xd5555555; +imm32 r6, 0xe6666666; +imm32 r7, 0xf7777777; +R0 >>>= 1; /* r0 = 0xc0000000 */ +R1 >>>= 1; /* r1 = 0xc0888888 */ +R2 >>>= 2; /* r2 = 0xe8888888 */ +R3 >>>= 8; /* r3 = 0x00333333 */ +R4 >>>= 1; /* r4 = 0x22222222 */ +R5 >>>= 27; /* r5 = 0x0000000a */ +R6 >>>= 30; /* r5 = 0x00000001 */ +R7 >>>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0888888; +CHECKREG r2, 0xe8888888; +CHECKREG r3, 0xffb33333; +CHECKREG r4, 0xe2222222; +CHECKREG r5, 0xfffffffa; +CHECKREG r6, 0xffffffff; +CHECKREG r7, 0xffffffff; + + +// Logical >>>= : positive data +imm32 r0, 0x40000000; +imm32 r1, 0x01111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; +R0 >>= 1; /* r0 = 0x20000000 */ +R1 >>= 1; /* r1 = 0x00888888 */ +R2 >>= 2; /* r2 = 0x08888888 */ +R3 >>= 8; /* r3 = 0x00333333 */ +R4 >>= 1; /* r4 = 0x22222222 */ +R5 >>= 27; /* r5 = 0x0000000a */ +R6 >>= 30; /* r5 = 0x00000001 */ +R7 >>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x00888888; +CHECKREG r2, 0x08888888; +CHECKREG r3, 0x00333333; +CHECKREG r4, 0x22222222; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// Logical >>= : negative data , +imm32 r0, 0x80000000; +imm32 r1, 0x81111111; +imm32 r2, 0xa2222222; +imm32 r3, 0xb3333333; +imm32 r4, 0xc4444444; +imm32 r5, 0xd5555555; +imm32 r6, 0xe6666666; +imm32 r7, 0xf7777777; +R0 >>= 1; /* r0 = 0x40000000 */ +R1 >>= 1; /* r1 = 0x40888888 */ +R2 >>= 2; /* r2 = 0x48888888 */ +R3 >>= 8; /* r3 = 0x40333333 */ +R4 >>= 1; /* r4 = 0xa2222222 */ +R5 >>= 27; /* r5 = 0x0000000a */ +R6 >>= 30; /* r5 = 0x00000001 */ +R7 >>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40888888; +CHECKREG r2, 0x28888888; +CHECKREG r3, 0x00b33333; +CHECKREG r4, 0x62222222; +CHECKREG r5, 0x0000001a; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000001; + + +// Logical <<= : negative data , +imm32 r0, 0x80000000; +imm32 r1, 0x81111111; +imm32 r2, 0xa2222222; +imm32 r3, 0xb3333333; +imm32 r4, 0xc4444444; +imm32 r5, 0xd5555555; +imm32 r6, 0xe6666666; +imm32 r7, 0xf7777777; +R0 <<= 1; /* r0 = 0x00000000 */ +R1 <<= 1; /* r1 = 0x40888888 */ +R2 <<= 2; /* r2 = 0x88888888 */ +R3 <<= 8; /* r3 = 0x33333300 */ +R4 <<= 1; /* r4 = 0x88888888 */ +R5 <<= 27; /* r5 = 0xa8000000 */ +R6 <<= 30; /* r5 = 0x80000000 */ +R7 <<= 31; /* r5 = 0x80000000 */ +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x02222222; +CHECKREG r2, 0x88888888; +CHECKREG r3, 0x33333300; +CHECKREG r4, 0x88888888; +CHECKREG r5, 0xa8000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + // hlt; + +pass diff --git a/tests/tcg/bfin/c_logi2op_arith_shft.s b/tests/tcg/bfin/c_logi2op_arith_shft.s new file mode 100644 index 0000000000000..110feee58b9a4 --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_arith_shft.s @@ -0,0 +1,223 @@ +//Original:/testcases/core/c_logi2op_arith_shft/c_logi2op_arith_shft.dsp +// Spec Reference: Logi2op >>>= +# mach: bfin + +.include "testutils.inc" + start + + + + + +// Arithmetic >>>= : negative data +// bit 0-7 +imm32 r0, 0x81111111; +imm32 r1, 0x81111111; +imm32 r2, 0x81111111; +imm32 r3, 0x81111111; +imm32 r4, 0x81111111; +imm32 r5, 0x81111111; +imm32 r6, 0x81111111; +imm32 r7, 0x81111111; +R0 >>>= 0; /* r0 = 0x81111111 */ +R1 >>>= 1; /* r1 = 0xC0888888 */ +R2 >>>= 2; /* r2 = 0xE0444444 */ +R3 >>>= 3; /* r3 = 0xF0222222 */ +R4 >>>= 4; /* r4 = 0xF8111111 */ +R5 >>>= 5; /* r5 = 0xFC088888 */ +R6 >>>= 6; /* r6 = 0xFE044444 */ +R7 >>>= 7; /* r7 = 0xFF022222 */ +CHECKREG r0, 0x81111111; +CHECKREG r1, 0xC0888888; +CHECKREG r2, 0xE0444444; +CHECKREG r3, 0xF0222222; +CHECKREG r4, 0xF8111111; +CHECKREG r5, 0xFC088888; +CHECKREG r6, 0xFE044444; +CHECKREG r7, 0xFF022222; + +// bit 8-15 +imm32 r0, 0x82222222; +imm32 r1, 0x82222222; +imm32 r2, 0x82222222; +imm32 r3, 0x82222222; +imm32 r4, 0x82222222; +imm32 r5, 0x82222222; +imm32 r6, 0x82222222; +imm32 r7, 0x82222222; +R0 >>>= 8; /* r0 = 0xFF822222 */ +R1 >>>= 9; /* r1 = 0xFFC11111 */ +R2 >>>= 10; /* r2 = 0xFFE08888 */ +R3 >>>= 11; /* r3 = 0xFFF04444 */ +R4 >>>= 12; /* r4 = 0xFFF82222 */ +R5 >>>= 13; /* r5 = 0xFFFC1111 */ +R6 >>>= 14; /* r6 = 0xFFFE0888 */ +R7 >>>= 15; /* r7 = 0xFFFF0444 */ +CHECKREG r0, 0xFF822222; +CHECKREG r1, 0xFFC11111; +CHECKREG r2, 0xFFE08888; +CHECKREG r3, 0xFFF04444; +CHECKREG r4, 0xFFF82222; +CHECKREG r5, 0xFFFC1111; +CHECKREG r6, 0xFFFE0888; +CHECKREG r7, 0xFFFF0444; + +// bit 16-23 +imm32 r0, 0x83333333; +imm32 r1, 0x83333333; +imm32 r2, 0x83333333; +imm32 r3, 0x83333333; +imm32 r4, 0x83333333; +imm32 r5, 0x83333333; +imm32 r6, 0x83333333; +imm32 r7, 0x83333333; +R0 >>>= 16; /* r0 = 0xFFFF8333 */ +R1 >>>= 17; /* r1 = 0xFFFFC199 */ +R2 >>>= 18; /* r2 = 0xFFFFE0CC */ +R3 >>>= 19; /* r3 = 0xFFFFF066 */ +R4 >>>= 20; /* r4 = 0xFFFFF833 */ +R5 >>>= 21; /* r5 = 0xFFFFFC19 */ +R6 >>>= 22; /* r6 = 0xFFFFFE0C */ +R7 >>>= 23; /* r7 = 0xFFFFFF06 */ +CHECKREG r0, 0xFFFF8333; +CHECKREG r1, 0xFFFFC199; +CHECKREG r2, 0xFFFFE0CC; +CHECKREG r3, 0xFFFFF066; +CHECKREG r4, 0xFFFFF833; +CHECKREG r5, 0xFFFFFC19; +CHECKREG r6, 0xFFFFFE0C; +CHECKREG r7, 0xFFFFFF06; + +// bit 24-31 +imm32 r0, 0x84444444; +imm32 r1, 0x84444444; +imm32 r2, 0x84444444; +imm32 r3, 0x84444444; +imm32 r4, 0x84444444; +imm32 r5, 0x84444444; +imm32 r6, 0x84444444; +imm32 r7, 0x84444444; +R0 >>>= 24; /* r0 = 0xFFFFFF84 */ +R1 >>>= 25; /* r1 = 0xFFFFFFC2 */ +R2 >>>= 26; /* r2 = 0xFFFFFFE1 */ +R3 >>>= 27; /* r3 = 0xFFFFFFF0 */ +R4 >>>= 28; /* r4 = 0xFFFFFFF8 */ +R5 >>>= 29; /* r5 = 0xFFFFFFFC */ +R6 >>>= 30; /* r6 = 0xFFFFFFFE */ +R7 >>>= 31; /* r7 = 0xFFFFFFFF */ +CHECKREG r0, 0xFFFFFF84; +CHECKREG r1, 0xFFFFFFC2; +CHECKREG r2, 0xFFFFFFE1; +CHECKREG r3, 0xFFFFFFF0; +CHECKREG r4, 0xFFFFFFF8; +CHECKREG r5, 0xFFFFFFFC; +CHECKREG r6, 0xFFFFFFFE; +CHECKREG r7, 0xFFFFFFFF; + +// Arithmetic >>>= : positive data +// bit 0-7 +imm32 r0, 0x41111111; +imm32 r1, 0x41111111; +imm32 r2, 0x41111111; +imm32 r3, 0x41111111; +imm32 r4, 0x41111111; +imm32 r5, 0x41111111; +imm32 r6, 0x41111111; +imm32 r7, 0x41111111; +R0 >>>= 0; /* r0 = 0x41111111 */ +R1 >>>= 1; /* r1 = 0x20888888 */ +R2 >>>= 2; /* r2 = 0x10444444 */ +R3 >>>= 3; /* r3 = 0x08222222 */ +R4 >>>= 4; /* r4 = 0x04111111 */ +R5 >>>= 5; /* r5 = 0x02088888 */ +R6 >>>= 6; /* r6 = 0x01044444 */ +R7 >>>= 7; /* r7 = 0x00822222 */ +CHECKREG r0, 0x41111111; +CHECKREG r1, 0x20888888; +CHECKREG r2, 0x10444444; +CHECKREG r3, 0x08222222; +CHECKREG r4, 0x04111111; +CHECKREG r5, 0x02088888; +CHECKREG r6, 0x01044444; +CHECKREG r7, 0x00822222; + +// bit 8-15 +imm32 r0, 0x42222222; +imm32 r1, 0x42222222; +imm32 r2, 0x42222222; +imm32 r3, 0x42222222; +imm32 r4, 0x42222222; +imm32 r5, 0x42222222; +imm32 r6, 0x42222222; +imm32 r7, 0x42222222; +R0 >>>= 8; /* r0 = 0x00422222 */ +R1 >>>= 9; /* r1 = 0x00211111 */ +R2 >>>= 10; /* r2 = 0x00108888 */ +R3 >>>= 11; /* r3 = 0x00084444 */ +R4 >>>= 12; /* r4 = 0x00042222 */ +R5 >>>= 13; /* r5 = 0x00021111 */ +R6 >>>= 14; /* r6 = 0x00010888 */ +R7 >>>= 15; /* r7 = 0x00008444 */ +CHECKREG r0, 0x00422222; +CHECKREG r1, 0x00211111; +CHECKREG r2, 0x00108888; +CHECKREG r3, 0x00084444; +CHECKREG r4, 0x00042222; +CHECKREG r5, 0x00021111; +CHECKREG r6, 0x00010888; +CHECKREG r7, 0x00008444; + +// bit 16-23 +imm32 r0, 0x43333333; +imm32 r1, 0x43333333; +imm32 r2, 0x43333333; +imm32 r3, 0x43333333; +imm32 r4, 0x43333333; +imm32 r5, 0x43333333; +imm32 r6, 0x43333333; +imm32 r7, 0x43333333; +R0 >>>= 16; /* r0 = 0x00004333 */ +R1 >>>= 17; /* r1 = 0x00002199 */ +R2 >>>= 18; /* r2 = 0x000010CC */ +R3 >>>= 19; /* r3 = 0x00000866 */ +R4 >>>= 20; /* r4 = 0x00000433 */ +R5 >>>= 21; /* r5 = 0x00000219 */ +R6 >>>= 22; /* r6 = 0x0000010C */ +R7 >>>= 23; /* r7 = 0x00000086 */ +CHECKREG r0, 0x00004333; +CHECKREG r1, 0x00002199; +CHECKREG r2, 0x000010CC; +CHECKREG r3, 0x00000866; +CHECKREG r4, 0x00000433; +CHECKREG r5, 0x00000219; +CHECKREG r6, 0x0000010C; +CHECKREG r7, 0x00000086; + +// bit 24-31 +imm32 r0, 0x44444444; +imm32 r1, 0x44444444; +imm32 r2, 0x44444444; +imm32 r3, 0x44444444; +imm32 r4, 0x44444444; +imm32 r5, 0x44444444; +imm32 r6, 0x44444444; +imm32 r7, 0x44444444; +R0 >>>= 24; /* r0 = 0x00000044 */ +R1 >>>= 25; /* r1 = 0x00000022 */ +R2 >>>= 26; /* r2 = 0x00000011 */ +R3 >>>= 27; /* r3 = 0x00000008 */ +R4 >>>= 28; /* r4 = 0x00000004 */ +R5 >>>= 29; /* r5 = 0x00000002 */ +R6 >>>= 30; /* r6 = 0x00000001 */ +R7 >>>= 31; /* r7 = 0x00000000 */ +CHECKREG r0, 0x00000044; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000011; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + +pass diff --git a/tests/tcg/bfin/c_logi2op_bitclr.s b/tests/tcg/bfin/c_logi2op_bitclr.s new file mode 100644 index 0000000000000..b5ca481ebe503 --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_bitclr.s @@ -0,0 +1,92 @@ +//Original:/testcases/core/c_logi2op_bitclr/c_logi2op_bitclr.dsp +// Spec Reference: Logi2op functions: bitclr +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0xffffffff; +imm32 r1, 0xffffffff; +imm32 r2, 0xffffffff; +imm32 r3, 0xffffffff; +imm32 r4, 0xffffffff; +imm32 r5, 0xffffffff; +imm32 r6, 0xffffffff; +imm32 r7, 0xffffffff; + +// bit clr +BITCLR( R0 , 0 ); /* r0 = 0x00000001 */ +BITCLR( R1 , 1 ); /* r1 = 0x00000002 */ +BITCLR( R2 , 2 ); /* r2 = 0x00000004 */ +BITCLR( R3 , 3 ); /* r3 = 0x00000008 */ +BITCLR( R4 , 4 ); /* r4 = 0x00000010 */ +BITCLR( R5 , 5 ); /* r5 = 0x00000020 */ +BITCLR( R6 , 6 ); /* r6 = 0x00000040 */ +BITCLR( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0xfffffffe; +CHECKREG r1, 0xfffffffd; +CHECKREG r2, 0xfffffffb; +CHECKREG r3, 0xfffffff7; +CHECKREG r4, 0xffffffef; +CHECKREG r5, 0xffffffdf; +CHECKREG r6, 0xffffffbf; +CHECKREG r7, 0xffffff7f; + +// bit clr +BITCLR( R0 , 8 ); /* r0 = 0x00000100 */ +BITCLR( R1 , 9 ); /* r1 = 0x00000200 */ +BITCLR( R2 , 10 ); /* r2 = 0x00000400 */ +BITCLR( R3 , 11 ); /* r3 = 0x00000800 */ +BITCLR( R4 , 12 ); /* r4 = 0x00001000 */ +BITCLR( R5 , 13 ); /* r5 = 0x00002000 */ +BITCLR( R6 , 14 ); /* r6 = 0x00004000 */ +BITCLR( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0xfffffefe; +CHECKREG r1, 0xfffffdfd; +CHECKREG r2, 0xfffffbfb; +CHECKREG r3, 0xfffff7f7; +CHECKREG r4, 0xffffefef; +CHECKREG r5, 0xffffdfdf; +CHECKREG r6, 0xffffbfbf; +CHECKREG r7, 0xffff7f7f; + +// bit clr +BITCLR( R0 , 16 ); /* r0 = 0x00000100 */ +BITCLR( R1 , 17 ); /* r1 = 0x00000200 */ +BITCLR( R2 , 18 ); /* r2 = 0x00000400 */ +BITCLR( R3 , 19 ); /* r3 = 0x00000800 */ +BITCLR( R4 , 20 ); /* r4 = 0x00001000 */ +BITCLR( R5 , 21 ); /* r5 = 0x00002000 */ +BITCLR( R6 , 22 ); /* r6 = 0x00004000 */ +BITCLR( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0xfffefefe; +CHECKREG r1, 0xfffdfdfd; +CHECKREG r2, 0xfffbfbfb; +CHECKREG r3, 0xfff7f7f7; +CHECKREG r4, 0xffefefef; +CHECKREG r5, 0xffdfdfdf; +CHECKREG r6, 0xffbfbfbf; +CHECKREG r7, 0xff7f7f7f; + +// bit clr +BITCLR( R0 , 24 ); /* r0 = 0x00000100 */ +BITCLR( R1 , 25 ); /* r1 = 0x00000200 */ +BITCLR( R2 , 26 ); /* r2 = 0x00000400 */ +BITCLR( R3 , 27 ); /* r3 = 0x00000800 */ +BITCLR( R4 , 28 ); /* r4 = 0x00001000 */ +BITCLR( R5 , 29 ); /* r5 = 0x00002000 */ +BITCLR( R6 , 30 ); /* r6 = 0x00004000 */ +BITCLR( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0xfefefefe; +CHECKREG r1, 0xfdfdfdfd; +CHECKREG r2, 0xfbfbfbfb; +CHECKREG r3, 0xf7f7f7f7; +CHECKREG r4, 0xefefefef; +CHECKREG r5, 0xdfdfdfdf; +CHECKREG r6, 0xbfbfbfbf; +CHECKREG r7, 0x7f7f7f7f; + + +pass diff --git a/tests/tcg/bfin/c_logi2op_bitset.s b/tests/tcg/bfin/c_logi2op_bitset.s new file mode 100644 index 0000000000000..ce86d674969e8 --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_bitset.s @@ -0,0 +1,92 @@ +//Original:/testcases/core/c_logi2op_bitset/c_logi2op_bitset.dsp +// Spec Reference: Logi2op +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit set +BITSET( R0 , 0 ); /* r0 = 0x00000001 */ +BITSET( R1 , 1 ); /* r1 = 0x00000002 */ +BITSET( R2 , 2 ); /* r2 = 0x00000004 */ +BITSET( R3 , 3 ); /* r3 = 0x00000008 */ +BITSET( R4 , 4 ); /* r4 = 0x00000010 */ +BITSET( R5 , 5 ); /* r5 = 0x00000020 */ +BITSET( R6 , 6 ); /* r6 = 0x00000040 */ +BITSET( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000080; + +// bit set +BITSET( R0 , 8 ); /* r0 = 0x00000100 */ +BITSET( R1 , 9 ); /* r1 = 0x00000200 */ +BITSET( R2 , 10 ); /* r2 = 0x00000400 */ +BITSET( R3 , 11 ); /* r3 = 0x00000800 */ +BITSET( R4 , 12 ); /* r4 = 0x00001000 */ +BITSET( R5 , 13 ); /* r5 = 0x00002000 */ +BITSET( R6 , 14 ); /* r6 = 0x00004000 */ +BITSET( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00000101; +CHECKREG r1, 0x00000202; +CHECKREG r2, 0x00000404; +CHECKREG r3, 0x00000808; +CHECKREG r4, 0x00001010; +CHECKREG r5, 0x00002020; +CHECKREG r6, 0x00004040; +CHECKREG r7, 0x00008080; + +// bit set +BITSET( R0 , 16 ); /* r0 = 0x00000100 */ +BITSET( R1 , 17 ); /* r1 = 0x00000200 */ +BITSET( R2 , 18 ); /* r2 = 0x00000400 */ +BITSET( R3 , 19 ); /* r3 = 0x00000800 */ +BITSET( R4 , 20 ); /* r4 = 0x00001000 */ +BITSET( R5 , 21 ); /* r5 = 0x00002000 */ +BITSET( R6 , 22 ); /* r6 = 0x00004000 */ +BITSET( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00010101; +CHECKREG r1, 0x00020202; +CHECKREG r2, 0x00040404; +CHECKREG r3, 0x00080808; +CHECKREG r4, 0x00101010; +CHECKREG r5, 0x00202020; +CHECKREG r6, 0x00404040; +CHECKREG r7, 0x00808080; + +// bit set +BITSET( R0 , 24 ); /* r0 = 0x00000100 */ +BITSET( R1 , 25 ); /* r1 = 0x00000200 */ +BITSET( R2 , 26 ); /* r2 = 0x00000400 */ +BITSET( R3 , 27 ); /* r3 = 0x00000800 */ +BITSET( R4 , 28 ); /* r4 = 0x00001000 */ +BITSET( R5 , 29 ); /* r5 = 0x00002000 */ +BITSET( R6 , 30 ); /* r6 = 0x00004000 */ +BITSET( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01010101; +CHECKREG r1, 0x02020202; +CHECKREG r2, 0x04040404; +CHECKREG r3, 0x08080808; +CHECKREG r4, 0x10101010; +CHECKREG r5, 0x20202020; +CHECKREG r6, 0x40404040; +CHECKREG r7, 0x80808080; + + +pass diff --git a/tests/tcg/bfin/c_logi2op_bittgl.s b/tests/tcg/bfin/c_logi2op_bittgl.s new file mode 100644 index 0000000000000..ca9fe41cda280 --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_bittgl.s @@ -0,0 +1,165 @@ +//Original:/testcases/core/c_logi2op_bittgl/c_logi2op_bittgl.dsp +// Spec Reference: Logi2op functions: bittgl +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit 0-7 +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ +BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ +BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ +BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ +BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ +BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ +BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000080; + +// bit 8-15 +BITTGL( R0 , 8 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00000101; +CHECKREG r1, 0x00000202; +CHECKREG r2, 0x00000404; +CHECKREG r3, 0x00000808; +CHECKREG r4, 0x00001010; +CHECKREG r5, 0x00002020; +CHECKREG r6, 0x00004040; +CHECKREG r7, 0x00008080; + +// bit 16-23 +BITTGL( R0 , 16 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 17 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 18 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 19 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 20 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 21 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 22 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00010101; +CHECKREG r1, 0x00020202; +CHECKREG r2, 0x00040404; +CHECKREG r3, 0x00080808; +CHECKREG r4, 0x00101010; +CHECKREG r5, 0x00202020; +CHECKREG r6, 0x00404040; +CHECKREG r7, 0x00808080; + +// bit 24-31 +BITTGL( R0 , 24 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 25 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 26 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 27 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 28 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 29 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 30 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01010101; +CHECKREG r1, 0x02020202; +CHECKREG r2, 0x04040404; +CHECKREG r3, 0x08080808; +CHECKREG r4, 0x10101010; +CHECKREG r5, 0x20202020; +CHECKREG r6, 0x40404040; +CHECKREG r7, 0x80808080; + +// bit 0-7 +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ +BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ +BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ +BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ +BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ +BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ +BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0x01010100; +CHECKREG r1, 0x02020200; +CHECKREG r2, 0x04040400; +CHECKREG r3, 0x08080800; +CHECKREG r4, 0x10101000; +CHECKREG r5, 0x20202000; +CHECKREG r6, 0x40404000; +CHECKREG r7, 0x80808000; + +// bit 8-15 +BITTGL( R0 , 8 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01010000; +CHECKREG r1, 0x02020000; +CHECKREG r2, 0x04040000; +CHECKREG r3, 0x08080000; +CHECKREG r4, 0x10100000; +CHECKREG r5, 0x20200000; +CHECKREG r6, 0x40400000; +CHECKREG r7, 0x80800000; + +// bit 16-23 +BITTGL( R0 , 16 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 17 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 18 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 19 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 20 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 21 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 22 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01000000; +CHECKREG r1, 0x02000000; +CHECKREG r2, 0x04000000; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x10000000; +CHECKREG r5, 0x20000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x80000000; + +// bit 24-31 +BITTGL( R0 , 24 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 25 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 26 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 27 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 28 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 29 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 30 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + + +pass diff --git a/tests/tcg/bfin/c_logi2op_bittst.s b/tests/tcg/bfin/c_logi2op_bittst.s new file mode 100644 index 0000000000000..cce9df57c7d3c --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_bittst.s @@ -0,0 +1,583 @@ +//Original:/testcases/core/c_logi2op_bittst/c_logi2op_bittst.dsp +// Spec Reference: Logi2op functions: bittst +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit(0-7) tst set clr toggle +CC = BITTST ( R0 , 0 ); /* cc = 0 */ +BITSET( R0 , 0 ); /* r0 = 0x00000001 */ +R1 = CC; +CC = BITTST ( R0 , 0 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 0 ); /* r0 = 0x00000000 */ +CC = BITTST ( R0 , 0 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +CC = BITTST ( R0 , 0 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 1 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 1 ); /* r1 = 0x00000002 */ +CC = BITTST ( R1 , 1 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 1 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 1 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ +CC = BITTST ( R1 , 1 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 2 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 2 ); /* r2 = 0x00000004 */ +CC = BITTST ( R2 , 2 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 2 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 2 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ +CC = BITTST ( R2 , 2 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; + +CC = BITTST ( R3 , 3 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 3 ); /* r3 = 0x00000008 */ +CC = BITTST ( R3 , 3 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 3 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 3 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ +CC = BITTST ( R3 , 3 ); /* cc = 1 */ +R7 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 4 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 4 ); /* r4 = 0x00000010 */ +CC = BITTST ( R4 , 4 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 4 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 4 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ +CC = BITTST ( R4 , 4 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 5 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 5 ); /* r5 = 0x00000020 */ +CC = BITTST ( R5 , 5 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 5 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 5 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ +CC = BITTST ( R5 , 5 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 6 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 6 ); /* r6 = 0x00000040 */ +CC = BITTST ( R6 , 6 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 6 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 6 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ +CC = BITTST ( R6 , 6 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 7 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 7 ); /* r7 = 0x00000080 */ +CC = BITTST ( R7 , 7 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 7 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 7 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ +CC = BITTST ( R7 , 7 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; + +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000080; + +// bit(8-15) tst set clr toggle +CC = BITTST ( R0 , 8 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 8 ); /* r0 = 0x00000101 */ +CC = BITTST ( R0 , 8 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 8 ); /* r0 = 0x00000000 */ +CC = BITTST ( R0 , 8 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 8 ); /* r0 = 0x00000101 */ +CC = BITTST ( R0 , 8 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 9 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 9 ); /* r1 = 0x00000200 */ +CC = BITTST ( R1 , 9 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 9 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 9 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ +CC = BITTST ( R1 , 9 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000200; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 10 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 10 ); /* r2 = 0x00000400 */ +CC = BITTST ( R2 , 10 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 10 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 10 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ +CC = BITTST ( R2 , 10 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000400; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; + +CC = BITTST ( R3 , 11 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 11 ); /* r3 = 0x00000800 */ +CC = BITTST ( R3 , 11 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 11 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 11 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ +CC = BITTST ( R3 , 11 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00000800; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 12 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 12 ); /* r4 = 0x00001000 */ +CC = BITTST ( R4 , 12 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 12 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 12 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ +CC = BITTST ( R4 , 12 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 13 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 13 ); /* r5 = 0x00002000 */ +CC = BITTST ( R5 , 13 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 13 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 13 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ +CC = BITTST ( R5 , 13 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00002000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 14 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 14 ); /* r6 = 0x00004000 */ +CC = BITTST ( R6 , 14 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 14 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 14 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ +CC = BITTST ( R6 , 14 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00004000; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 15 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 15 ); /* r7 = 0x00008000 */ +CC = BITTST ( R7 , 15 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 15 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 15 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ +CC = BITTST ( R7 , 15 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00002000; +CHECKREG r6, 0x00004000; +CHECKREG r7, 0x00008000; + +// bit(16-23) tst set clr toggle +CC = BITTST ( R0 , 16 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 16 ); /* r0 = 0x00010000 */ +CC = BITTST ( R0 , 16 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 16 ); /* r0 = 0x00000000 */ +CC = BITTST ( R0 , 16 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 16 ); /* r0 = 0x00010000 */ +CC = BITTST ( R0 , 16 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 17 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 17 ); /* r1 = 0x00020000 */ +CC = BITTST ( R1 , 17 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 17 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 17 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 17 ); /* r1 = 0x00020000 */ +CC = BITTST ( R1 , 17 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00020000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 18 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 18 ); /* r2 = 0x00020000 */ +CC = BITTST ( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 18 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITTGL( R2 , 18 ); /* r2 = 0x00020000 */ +CC = BITTST ( R2 , 18 ); /* cc = 1 */ +R5 = CC; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00004000; + +CC = BITTST ( R3 , 19 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 19 ); /* r3 = 0x00080000 */ +CC = BITTST ( R3 , 19 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 19 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 19 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 19 ); /* r3 = 0x00080000 */ +CC = BITTST ( R3 , 19 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00080000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 20 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 20 ); /* r4 = 0x00100000 */ +CC = BITTST ( R4 , 20 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 20 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 20 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 20 ); /* r4 = 0x00100000 */ +CC = BITTST ( R4 , 20 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00100000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 21 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 21 ); /* r5 = 0x00200000 */ +CC = BITTST ( R5 , 21 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 21 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 21 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 21 ); /* r5 = 0x00200000 */ +CC = BITTST ( R5 , 21 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 22 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 22 ); /* r6 = 0x00400000 */ +CC = BITTST ( R6 , 22 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 22 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 22 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 22 ); /* r6 = 0x00400000 */ +CC = BITTST ( R6 , 22 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00400000; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 23 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 23 ); /* r7 = 0x00800000 */ +CC = BITTST ( R7 , 23 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 23 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 23 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 23 ); /* r7 = 0x00800000 */ +CC = BITTST ( R7 , 23 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00100000; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00400000; +CHECKREG r7, 0x00800000; + +// bit(24-31) tst set clr toggle +CC = BITTST ( R0 , 24 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 24 ); /* r0 = 0x00000101 */ +CC = BITTST ( R0 , 24 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 24 ); /* r0 = 0x01000000 */ +CC = BITTST ( R0 , 24 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 24 ); /* r0 = 0x01000000 */ +CC = BITTST ( R0 , 24 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x01000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 25 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 25 ); /* r1 = 0x02000000 */ +CC = BITTST ( R1 , 25 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 25 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 25 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 25 ); /* r1 = 0x02000000 */ +CC = BITTST ( R1 , 25 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x02000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 26 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 26 ); /* r2 = 0x04000000 */ +CC = BITTST ( R2 , 26 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 26 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 26 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 26 ); /* r2 = 0x04000000 */ +CC = BITTST ( R2 , 26 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x04000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; + +CC = BITTST ( R3 , 27 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 27 ); /* r3 = 0x08000000 */ +CC = BITTST ( R3 , 27 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 27 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 27 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 27 ); /* r3 = 0x08000000 */ +CC = BITTST ( R3 , 27 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 28 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 28 ); /* r4 = 0x10000000 */ +CC = BITTST ( R4 , 28 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 28 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 28 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 28 ); /* r4 = 0x10000000 */ +CC = BITTST ( R4 , 28 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x10000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 29 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 29 ); /* r5 = 0x20000000 */ +CC = BITTST ( R5 , 29 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 29 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 29 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 29 ); /* r5 = 0x20000000 */ +CC = BITTST ( R5 , 29 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x20000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 30 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 30 ); /* r6 = 0x40000000 */ +CC = BITTST ( R6 , 30 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 30 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 30 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 30 ); /* r6 = 0x40000000 */ +CC = BITTST ( R6 , 30 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 31 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 31 ); /* r7 = 0x80000000 */ +CC = BITTST ( R7 , 31 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 31 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 31 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 31 ); /* r7 = 0x80000000 */ +CC = BITTST ( R7 , 31 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x10000000; +CHECKREG r5, 0x20000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x80000000; + +pass diff --git a/tests/tcg/bfin/c_logi2op_log_l_shft.s b/tests/tcg/bfin/c_logi2op_log_l_shft.s new file mode 100644 index 0000000000000..46a457a86ca73 --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_log_l_shft.s @@ -0,0 +1,222 @@ +//Original:/testcases/core/c_logi2op_log_l_shft/c_logi2op_log_l_shft.dsp +// Spec Reference: Logi2op <<= +# mach: bfin + +.include "testutils.inc" + start + + + + +// Logical <<= : negative data +// bit 0-7 +imm32 r0, 0x81111111; +imm32 r1, 0x81111111; +imm32 r2, 0x81111111; +imm32 r3, 0x81111111; +imm32 r4, 0x81111111; +imm32 r5, 0x81111111; +imm32 r6, 0x81111111; +imm32 r7, 0x81111111; +R0 <<= 0; /* r0 = 0x81111111 */ +R1 <<= 1; /* r1 = 0x40888888 */ +R2 <<= 2; /* r2 = 0x20444444 */ +R3 <<= 3; /* r3 = 0x10222222 */ +R4 <<= 4; /* r4 = 0x08111111 */ +R5 <<= 5; /* r5 = 0x04088888 */ +R6 <<= 6; /* r6 = 0x02044444 */ +R7 <<= 7; /* r7 = 0x01022222 */ +CHECKREG r0, 0x81111111; +CHECKREG r1, 0x02222222; +CHECKREG r2, 0x04444444; +CHECKREG r3, 0x08888888; +CHECKREG r4, 0x11111110; +CHECKREG r5, 0x22222220; +CHECKREG r6, 0x44444440; +CHECKREG r7, 0x88888880; + +// bit 8-15 +imm32 r0, 0x82222222; +imm32 r1, 0x82222222; +imm32 r2, 0x82222222; +imm32 r3, 0x82222222; +imm32 r4, 0x82222222; +imm32 r5, 0x82222222; +imm32 r6, 0x82222222; +imm32 r7, 0x82222222; +R0 <<= 8; +R1 <<= 9; +R2 <<= 10; +R3 <<= 11; +R4 <<= 12; +R5 <<= 13; +R6 <<= 14; +R7 <<= 15; +CHECKREG r0, 0x22222200; +CHECKREG r1, 0x44444400; +CHECKREG r2, 0x88888800; +CHECKREG r3, 0x11111000; +CHECKREG r4, 0x22222000; +CHECKREG r5, 0x44444000; +CHECKREG r6, 0x88888000; +CHECKREG r7, 0x11110000; + +// bit 16-23 +imm32 r0, 0x83333333; +imm32 r1, 0x83333333; +imm32 r2, 0x83333333; +imm32 r3, 0x83333333; +imm32 r4, 0x83333333; +imm32 r5, 0x83333333; +imm32 r6, 0x83333333; +imm32 r7, 0x83333333; +R0 <<= 16; +R1 <<= 17; +R2 <<= 18; +R3 <<= 19; +R4 <<= 20; +R5 <<= 21; +R6 <<= 22; +R7 <<= 23; +CHECKREG r0, 0x33330000; +CHECKREG r1, 0x66660000; +CHECKREG r2, 0xCCCC0000; +CHECKREG r3, 0x99980000; +CHECKREG r4, 0x33300000; +CHECKREG r5, 0x66600000; +CHECKREG r6, 0xCCC00000; +CHECKREG r7, 0x99800000; + +// bit 24-31 +imm32 r0, 0x84444444; +imm32 r1, 0x84444444; +imm32 r2, 0x84444444; +imm32 r3, 0x84444444; +imm32 r4, 0x84444444; +imm32 r5, 0x84444444; +imm32 r6, 0x84444444; +imm32 r7, 0x84444444; +R0 <<= 24; +R1 <<= 25; +R2 <<= 26; +R3 <<= 27; +R4 <<= 28; +R5 <<= 29; +R6 <<= 30; +R7 <<= 31; +CHECKREG r0, 0x44000000; +CHECKREG r1, 0x88000000; +CHECKREG r2, 0x10000000; +CHECKREG r3, 0x20000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// Arithmetic <<= : positive data +// bit 0-7 +imm32 r0, 0x41111111; +imm32 r1, 0x41111111; +imm32 r2, 0x41111111; +imm32 r3, 0x41111111; +imm32 r4, 0x41111111; +imm32 r5, 0x41111111; +imm32 r6, 0x41111111; +imm32 r7, 0x41111111; +R0 <<= 0; +R1 <<= 1; +R2 <<= 2; +R3 <<= 3; +R4 <<= 4; +R5 <<= 5; +R6 <<= 6; +R7 <<= 7; +CHECKREG r0, 0x41111111; +CHECKREG r1, 0x82222222; +CHECKREG r2, 0x04444444; +CHECKREG r3, 0x08888888; +CHECKREG r4, 0x11111110; +CHECKREG r5, 0x22222220; +CHECKREG r6, 0x44444440; +CHECKREG r7, 0x88888880; + +// bit 8-15 +imm32 r0, 0x42222222; +imm32 r1, 0x42222222; +imm32 r2, 0x42222222; +imm32 r3, 0x42222222; +imm32 r4, 0x42222222; +imm32 r5, 0x42222222; +imm32 r6, 0x42222222; +imm32 r7, 0x42222222; +R0 <<= 8; +R1 <<= 9; +R2 <<= 10; +R3 <<= 11; +R4 <<= 12; +R5 <<= 13; +R6 <<= 14; +R7 <<= 15; +CHECKREG r0, 0x22222200; +CHECKREG r1, 0x44444400; +CHECKREG r2, 0x88888800; +CHECKREG r3, 0x11111000; +CHECKREG r4, 0x22222000; +CHECKREG r5, 0x44444000; +CHECKREG r6, 0x88888000; +CHECKREG r7, 0x11110000; + +// bit 16-23 +imm32 r0, 0x43333333; +imm32 r1, 0x43333333; +imm32 r2, 0x43333333; +imm32 r3, 0x43333333; +imm32 r4, 0x43333333; +imm32 r5, 0x43333333; +imm32 r6, 0x43333333; +imm32 r7, 0x43333333; +R0 <<= 16; +R1 <<= 17; +R2 <<= 18; +R3 <<= 19; +R4 <<= 20; +R5 <<= 21; +R6 <<= 22; +R7 <<= 23; +CHECKREG r0, 0x33330000; +CHECKREG r1, 0x66660000; +CHECKREG r2, 0xCCCC0000; +CHECKREG r3, 0x99980000; +CHECKREG r4, 0x33300000; +CHECKREG r5, 0x66600000; +CHECKREG r6, 0xCCC00000; +CHECKREG r7, 0x99800000; + +// bit 24-31 +imm32 r0, 0x44444444; +imm32 r1, 0x44444444; +imm32 r2, 0x44444444; +imm32 r3, 0x44444444; +imm32 r4, 0x44444444; +imm32 r5, 0x44444444; +imm32 r6, 0x44444444; +imm32 r7, 0x44444444; +R0 <<= 24; +R1 <<= 25; +R2 <<= 26; +R3 <<= 27; +R4 <<= 28; +R5 <<= 29; +R6 <<= 30; +R7 <<= 31; +CHECKREG r0, 0x44000000; +CHECKREG r1, 0x88000000; +CHECKREG r2, 0x10000000; +CHECKREG r3, 0x20000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +pass diff --git a/tests/tcg/bfin/c_logi2op_log_l_shft_astat.S b/tests/tcg/bfin/c_logi2op_log_l_shft_astat.S new file mode 100644 index 0000000000000..6b3e8ca26e491 --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_log_l_shft_astat.S @@ -0,0 +1,82 @@ +# Test ASTAT bits with logical left shift (<<=) +# mach: bfin + +.include "testutils.inc" +#include "test.h" +start + +.macro __do val:req, shift:req, exp:req + # First test when ASTAT starts with all bits cleared + imm32 R2, \val; + ASTAT = R0; + R2 <<= \shift; + R3 = ASTAT; + CHECKREG R2, (\val << \shift); + CHECKREG R3, \exp; + + # Then test when ASTAT starts with all bits set + imm32 R2, \val; + ASTAT = R1; + R2 <<= \shift; + R3 = ASTAT; + CHECKREG R3, (\exp) | ~(_AZ|_AN|_V|_V_COPY); +.endm + +.macro _do shift:req, val:req + # Automatically test all shifted values + .if ((\val << \shift) & 0xffffffff) == 0 + __do \val, \shift, _AZ + .else + .if (\val << \shift) == 0x80000000 + __do \val, \shift, _AN + .else + __do \val, \shift, 0 + .endif + .endif + .if (\val << 1) & 0xffffffff + _do \shift, (\val << 1) + .endif +.endm + +.macro do shift:req +_l_shft_\shift: + _do \shift, 1 +.endm + +R0 = 0; +R1 = -1; + +do 0 +do 1 +do 2 +do 3 +do 4 +do 5 +do 6 +do 7 +do 8 +do 9 +do 10 +do 11 +do 12 +do 13 +do 14 +do 15 +do 16 +do 17 +do 18 +do 19 +do 20 +do 21 +do 22 +do 23 +do 24 +do 25 +do 26 +do 27 +do 28 +do 29 +do 30 +do 31 + +pass diff --git a/tests/tcg/bfin/c_logi2op_log_r_shft.s b/tests/tcg/bfin/c_logi2op_log_r_shft.s new file mode 100644 index 0000000000000..af4eb73d20fca --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_log_r_shft.s @@ -0,0 +1,222 @@ +//Original:/testcases/core/c_logi2op_log_r_shft/c_logi2op_log_r_shft.dsp +// Spec Reference: Logi2op >>= +# mach: bfin + +.include "testutils.inc" + start + + + + +// Logical >>= : negative data +// bit 0-7 +imm32 r0, 0x81111111; +imm32 r1, 0x81111111; +imm32 r2, 0x81111111; +imm32 r3, 0x81111111; +imm32 r4, 0x81111111; +imm32 r5, 0x81111111; +imm32 r6, 0x81111111; +imm32 r7, 0x81111111; +R0 >>= 0; /* r0 = 0x81111111 */ +R1 >>= 1; /* r1 = 0x40888888 */ +R2 >>= 2; /* r2 = 0x20444444 */ +R3 >>= 3; /* r3 = 0x10222222 */ +R4 >>= 4; /* r4 = 0x08111111 */ +R5 >>= 5; /* r5 = 0x04088888 */ +R6 >>= 6; /* r6 = 0x02044444 */ +R7 >>= 7; /* r7 = 0x01022222 */ +CHECKREG r0, 0x81111111; +CHECKREG r1, 0x40888888; +CHECKREG r2, 0x20444444; +CHECKREG r3, 0x10222222; +CHECKREG r4, 0x08111111; +CHECKREG r5, 0x04088888; +CHECKREG r6, 0x02044444; +CHECKREG r7, 0x01022222; + +// bit 8-15 +imm32 r0, 0x82222222; +imm32 r1, 0x82222222; +imm32 r2, 0x82222222; +imm32 r3, 0x82222222; +imm32 r4, 0x82222222; +imm32 r5, 0x82222222; +imm32 r6, 0x82222222; +imm32 r7, 0x82222222; +R0 >>= 8; /* r0 = 0x00822222 */ +R1 >>= 9; /* r1 = 0x00411111 */ +R2 >>= 10; /* r2 = 0x00208888 */ +R3 >>= 11; /* r3 = 0x00104444 */ +R4 >>= 12; /* r4 = 0x00082222 */ +R5 >>= 13; /* r5 = 0x00041111 */ +R6 >>= 14; /* r6 = 0x00020888 */ +R7 >>= 15; /* r7 = 0x00010444 */ +CHECKREG r0, 0x00822222; +CHECKREG r1, 0x00411111; +CHECKREG r2, 0x00208888; +CHECKREG r3, 0x00104444; +CHECKREG r4, 0x00082222; +CHECKREG r5, 0x00041111; +CHECKREG r6, 0x00020888; +CHECKREG r7, 0x00010444; + +// bit 16-23 +imm32 r0, 0x83333333; +imm32 r1, 0x83333333; +imm32 r2, 0x83333333; +imm32 r3, 0x83333333; +imm32 r4, 0x83333333; +imm32 r5, 0x83333333; +imm32 r6, 0x83333333; +imm32 r7, 0x83333333; +R0 >>= 16; /* r0 = 0x00008333 */ +R1 >>= 17; /* r1 = 0x00004199 */ +R2 >>= 18; /* r2 = 0x000020CC */ +R3 >>= 19; /* r3 = 0x00001066 */ +R4 >>= 20; /* r4 = 0x00000833 */ +R5 >>= 21; /* r5 = 0x00000419 */ +R6 >>= 22; /* r6 = 0x0000020C */ +R7 >>= 23; /* r7 = 0x00000106 */ +CHECKREG r0, 0x00008333; +CHECKREG r1, 0x00004199; +CHECKREG r2, 0x000020CC; +CHECKREG r3, 0x00001066; +CHECKREG r4, 0x00000833; +CHECKREG r5, 0x00000419; +CHECKREG r6, 0x0000020C; +CHECKREG r7, 0x00000106; + +// bit 24-31 +imm32 r0, 0x84444444; +imm32 r1, 0x84444444; +imm32 r2, 0x84444444; +imm32 r3, 0x84444444; +imm32 r4, 0x84444444; +imm32 r5, 0x84444444; +imm32 r6, 0x84444444; +imm32 r7, 0x84444444; +R0 >>= 24; /* r0 = 0x00000084 */ +R1 >>= 25; /* r1 = 0x00000042 */ +R2 >>= 26; /* r2 = 0x00000021 */ +R3 >>= 27; /* r3 = 0x00000010 */ +R4 >>= 28; /* r4 = 0x00000008 */ +R5 >>= 29; /* r5 = 0x00000004 */ +R6 >>= 30; /* r6 = 0x00000002 */ +R7 >>= 31; /* r7 = 0x00000001 */ +CHECKREG r0, 0x00000084; +CHECKREG r1, 0x00000042; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x00000004; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0x00000001; + +// Arithmetic >>= : positive data +// bit 0-7 +imm32 r0, 0x41111111; +imm32 r1, 0x41111111; +imm32 r2, 0x41111111; +imm32 r3, 0x41111111; +imm32 r4, 0x41111111; +imm32 r5, 0x41111111; +imm32 r6, 0x41111111; +imm32 r7, 0x41111111; +R0 >>= 0; /* r0 = 0x41111111 */ +R1 >>= 1; /* r1 = 0x20888888 */ +R2 >>= 2; /* r2 = 0x10444444 */ +R3 >>= 3; /* r3 = 0x08222222 */ +R4 >>= 4; /* r4 = 0x04111111 */ +R5 >>= 5; /* r5 = 0x02088888 */ +R6 >>= 6; /* r6 = 0x01044444 */ +R7 >>= 7; /* r7 = 0x00822222 */ +CHECKREG r0, 0x41111111; +CHECKREG r1, 0x20888888; +CHECKREG r2, 0x10444444; +CHECKREG r3, 0x08222222; +CHECKREG r4, 0x04111111; +CHECKREG r5, 0x02088888; +CHECKREG r6, 0x01044444; +CHECKREG r7, 0x00822222; + +// bit 8-15 +imm32 r0, 0x42222222; +imm32 r1, 0x42222222; +imm32 r2, 0x42222222; +imm32 r3, 0x42222222; +imm32 r4, 0x42222222; +imm32 r5, 0x42222222; +imm32 r6, 0x42222222; +imm32 r7, 0x42222222; +R0 >>= 8; /* r0 = 0x00422222 */ +R1 >>= 9; /* r1 = 0x00211111 */ +R2 >>= 10; /* r2 = 0x00108888 */ +R3 >>= 11; /* r3 = 0x00084444 */ +R4 >>= 12; /* r4 = 0x00042222 */ +R5 >>= 13; /* r5 = 0x00021111 */ +R6 >>= 14; /* r6 = 0x00010888 */ +R7 >>= 15; /* r7 = 0x00008444 */ +CHECKREG r0, 0x00422222; +CHECKREG r1, 0x00211111; +CHECKREG r2, 0x00108888; +CHECKREG r3, 0x00084444; +CHECKREG r4, 0x00042222; +CHECKREG r5, 0x00021111; +CHECKREG r6, 0x00010888; +CHECKREG r7, 0x00008444; + +// bit 16-23 +imm32 r0, 0x43333333; +imm32 r1, 0x43333333; +imm32 r2, 0x43333333; +imm32 r3, 0x43333333; +imm32 r4, 0x43333333; +imm32 r5, 0x43333333; +imm32 r6, 0x43333333; +imm32 r7, 0x43333333; +R0 >>= 16; /* r0 = 0x00004333 */ +R1 >>= 17; /* r1 = 0x00002199 */ +R2 >>= 18; /* r2 = 0x000010CC */ +R3 >>= 19; /* r3 = 0x00000866 */ +R4 >>= 20; /* r4 = 0x00000433 */ +R5 >>= 21; /* r5 = 0x00000219 */ +R6 >>= 22; /* r6 = 0x0000010C */ +R7 >>= 23; /* r7 = 0x00000086 */ +CHECKREG r0, 0x00004333; +CHECKREG r1, 0x00002199; +CHECKREG r2, 0x000010CC; +CHECKREG r3, 0x00000866; +CHECKREG r4, 0x00000433; +CHECKREG r5, 0x00000219; +CHECKREG r6, 0x0000010C; +CHECKREG r7, 0x00000086; + +// bit 24-31 +imm32 r0, 0x44444444; +imm32 r1, 0x44444444; +imm32 r2, 0x44444444; +imm32 r3, 0x44444444; +imm32 r4, 0x44444444; +imm32 r5, 0x44444444; +imm32 r6, 0x44444444; +imm32 r7, 0x44444444; +R0 >>= 24; /* r0 = 0x00000044 */ +R1 >>= 25; /* r1 = 0x00000022 */ +R2 >>= 26; /* r2 = 0x00000011 */ +R3 >>= 27; /* r3 = 0x00000008 */ +R4 >>= 28; /* r4 = 0x00000004 */ +R5 >>= 29; /* r5 = 0x00000002 */ +R6 >>= 30; /* r6 = 0x00000001 */ +R7 >>= 31; /* r7 = 0x00000000 */ +CHECKREG r0, 0x00000044; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000011; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + +pass diff --git a/tests/tcg/bfin/c_logi2op_log_r_shft_astat.S b/tests/tcg/bfin/c_logi2op_log_r_shft_astat.S new file mode 100644 index 0000000000000..4f2a22ba184cd --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_log_r_shft_astat.S @@ -0,0 +1,82 @@ +# Test ASTAT bits with logical right shift (>>=) +# mach: bfin + +.include "testutils.inc" +#include "test.h" +start + +.macro __do val:req, shift:req, exp:req + # First test when ASTAT starts with all bits cleared + imm32 R2, \val; + ASTAT = R0; + R2 >>= \shift; + R3 = ASTAT; + CHECKREG R2, (\val >> \shift); + CHECKREG R3, \exp; + + # Then test when ASTAT starts with all bits set + imm32 R2, \val; + ASTAT = R1; + R2 >>= \shift; + R3 = ASTAT; + CHECKREG R3, (\exp) | ~(_AZ|_AN|_V|_V_COPY); +.endm + +.macro _do shift:req, val:req + # Automatically test all shifted values + .if ((\val >> \shift) & 0xffffffff) == 0 + __do \val, \shift, _AZ + .else + .if (\val >> \shift) == 0x80000000 + __do \val, \shift, _AN + .else + __do \val, \shift, 0 + .endif + .endif + .if (\val >> 1) & 0xffffffff + _do \shift, (\val >> 1) + .endif +.endm + +.macro do shift:req +_l_shft_\shift: + _do \shift, 0x80000000 +.endm + +R0 = 0; +R1 = -1; + +do 0 +do 1 +do 2 +do 3 +do 4 +do 5 +do 6 +do 7 +do 8 +do 9 +do 10 +do 11 +do 12 +do 13 +do 14 +do 15 +do 16 +do 17 +do 18 +do 19 +do 20 +do 21 +do 22 +do 23 +do 24 +do 25 +do 26 +do 27 +do 28 +do 29 +do 30 +do 31 + +pass diff --git a/tests/tcg/bfin/c_logi2op_nbittst.s b/tests/tcg/bfin/c_logi2op_nbittst.s new file mode 100644 index 0000000000000..b881c2b9a9e6c --- /dev/null +++ b/tests/tcg/bfin/c_logi2op_nbittst.s @@ -0,0 +1,584 @@ +//Original:/testcases/core/c_logi2op_nbittst/c_logi2op_nbittst.dsp +// Spec Reference: Logi2op !bittst +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit(0-7) tst set clr toggle +CC = ! BITTST( R0 , 0 ); /* cc = 0 */ +BITSET( R0 , 0 ); /* r0 = 0x00000001 */ +R1 = CC; +CC = ! BITTST( R0 , 0 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 0 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 0 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +CC = ! BITTST( R0 , 0 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 1 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 1 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 1 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 1 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 1 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 1 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 1 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 2 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 2 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 2 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 2 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 2 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 2 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 2 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000005; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; + +CC = ! BITTST( R3 , 3 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 3 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 3 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 3 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 3 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 3 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 3 ); /* cc = 1 */ +R7 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000005; +CHECKREG r3, 0x00000009; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 4 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 4 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 4 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 4 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 4 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 4 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 4 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00000011; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 5 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 5 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 5 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 5 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 5 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 5 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 5 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00000021; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 6 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 6 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 6 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 6 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 6 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 6 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 6 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00000041; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 7 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 7 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 7 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 7 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 7 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 7 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 7 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; + +CHECKREG r4, 0x00000011; +CHECKREG r5, 0x00000021; +CHECKREG r6, 0x00000041; +CHECKREG r7, 0x00000081; + +// bit(8-15) tst set clr toggle +CC = ! BITTST( R0 , 8 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 8 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 8 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 8 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 8 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 8 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 8 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000101; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 9 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 9 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 9 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 9 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 9 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 9 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 9 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000201; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 10 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 10 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 10 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 10 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 10 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 10 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 10 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000401; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; + +CC = ! BITTST( R3 , 11 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 11 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 11 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 11 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 11 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 11 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 11 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00000801; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 12 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 12 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 12 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 12 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 12 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 12 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 12 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00001001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 13 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 13 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 13 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 13 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 13 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 13 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 13 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00002001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 14 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 14 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 14 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 14 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 14 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 14 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 14 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00004001; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 15 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 15 ); /* r0 = 0x00008080 */ +CC = ! BITTST( R7 , 15 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 15 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 15 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 15 ); /* r0 = 0x00008080 */ +CC = ! BITTST( R7 , 15 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00001001; +CHECKREG r5, 0x00002001; +CHECKREG r6, 0x00004001; +CHECKREG r7, 0x00008001; + +// bit(16-23) tst set clr toggle +CC = ! BITTST( R0 , 16 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 16 ); /* r0 = 0x00000001 */ +CC = ! BITTST( R0 , 16 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 16 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 16 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 16 ); /* r0 = 0x00000001 */ +CC = ! BITTST( R0 , 16 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 17 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 17 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 17 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 17 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 17 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 17 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 17 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 18 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 18 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 18 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITTGL( R2 , 18 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 18 ); /* cc = 1 */ +R5 = CC; +CHECKREG r2, 0x00040001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00004001; + +CC = ! BITTST( R3 , 19 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 19 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 19 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 19 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 19 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 19 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 19 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00080001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 20 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 20 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 20 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 20 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 20 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 20 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 20 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00100001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 21 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 21 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 21 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 21 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 21 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 21 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 21 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00200001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 22 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 22 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 22 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 22 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 22 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 22 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 22 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00400001; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 23 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 23 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 23 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 23 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 23 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 23 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 23 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00100001; +CHECKREG r5, 0x00200001; +CHECKREG r6, 0x00400001; +CHECKREG r7, 0x00800001; + +// bit(24-31) tst set clr toggle +CC = ! BITTST( R0 , 24 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 24 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 24 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 24 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 24 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 24 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 24 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x01000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 25 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 25 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 25 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 25 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 25 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 25 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 25 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x02000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 26 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 26 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 26 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 26 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 26 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 26 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 26 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x04000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; + +CC = ! BITTST( R3 , 27 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 27 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 27 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 27 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 27 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 27 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 27 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x08000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 28 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 28 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 28 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 28 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 28 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 28 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 28 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x10000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 29 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 29 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 29 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 29 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 29 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 29 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 29 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x20000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 30 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 30 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 30 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 30 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 30 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 30 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 30 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x40000001; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 31 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 31 ); /* r0 = 0x00008080 */ +CC = ! BITTST( R7 , 31 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 31 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 31 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 31 ); /* r0 = 0x80808080 */ +CC = ! BITTST( R7 , 31 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x10000001; +CHECKREG r5, 0x20000001; +CHECKREG r6, 0x40000001; +CHECKREG r7, 0x80000001; + +pass diff --git a/tests/tcg/bfin/c_loopsetup_nested.s b/tests/tcg/bfin/c_loopsetup_nested.s new file mode 100644 index 0000000000000..b351bc5383b45 --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_nested.s @@ -0,0 +1,166 @@ +//Original:/testcases/core/c_loopsetup_nested/c_loopsetup_nested.dsp +// Spec Reference: loopsetup nested inside +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LSETUP ( start3 , end3 ) LC1 = P3; +start3: R6 += 6; +LSETUP ( start4 , end4 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFEC; +CHECKREG r2, 0x00000056; +CHECKREG r3, 0x0000004C; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0x00000014; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +LSETUP ( start6 , end6 ) LC1 = SP >> 1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x0000005D; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x000000D0; +CHECKREG r7, 0xFFFFFFE4; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000063; +CHECKREG r4, 0x0000006B; +CHECKREG r5, 0x00000015; +CHECKREG r6, 0x000000D0; +CHECKREG r7, 0xFFFFFFE4; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC0 = P5; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P3; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC0 = P2; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000011; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x0000002C; +CHECKREG r3, 0x0000004E; +CHECKREG r4, 0x00000210; +CHECKREG r5, 0xFFFFFE80; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x00000060; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 1; + R1 += -1; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000055; +CHECKREG r4, 0x00000118; +CHECKREG r5, 0xFFFFFF78; +CHECKREG r6, 0x000001EC; +CHECKREG r7, 0xFFFFFEE4; + +pass diff --git a/tests/tcg/bfin/c_loopsetup_nested_bot.s b/tests/tcg/bfin/c_loopsetup_nested_bot.s new file mode 100644 index 0000000000000..118b6d259fde4 --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_nested_bot.s @@ -0,0 +1,165 @@ +//Original:/testcases/core/c_loopsetup_nested_bot/c_loopsetup_nested_bot.dsp +// Spec Reference: loopsetup nested same bottom +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; +ASTAT = r0; + +//p0 = 2; +P1 = 2; +P2 = 4; +P3 = 6; +P4 = 8; +P5 = 10; +SP = 12; +FP = 14; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x32; +R4 = 0x46 (X); +R5 = 0x50 (X); +R6 = 0x68 (X); +R7 = 0x72 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LSETUP ( start3 , end3 ) LC1 = P3; +start3: R6 += 6; +LSETUP ( start4 , end3 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000010; +CHECKREG r1, 0xFFFFFFFA; +CHECKREG r2, 0x00000041; +CHECKREG r3, 0x0000005D; +CHECKREG r4, 0x00000066; +CHECKREG r5, 0x00000028; +CHECKREG r6, 0x0000008C; +CHECKREG r7, 0x00000033; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x14; +R3 = 0x18; +R4 = 0x20; +R5 = 0x12; +R6 = 0x24; +R7 = 0x16; +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +LSETUP ( start6 , end5 ) LC1 = SP >> 1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000014; +CHECKREG r3, 0x00000183; +CHECKREG r4, 0x0000002A; +CHECKREG r5, 0xFFFFFF9A; +CHECKREG r6, 0x00000114; +CHECKREG r7, 0xFFFFFEEA; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000014; +CHECKREG r3, 0x00000189; +CHECKREG r4, 0x00000062; +CHECKREG r5, 0xFFFFFF54; +CHECKREG r6, 0x00000114; +CHECKREG r7, 0xFFFFFEEA; + +P1 = 04; +P2 = 08; +P3 = 10; +P4 = 12; +P5 = 14; +SP = 16; +FP = 18; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x12; +R3 = 0x20; +R4 = 0x18; +R5 = 0x14; +R6 = 0x16; +R7 = 0x28; +LSETUP ( start11 , end11 ) LC0 = P5; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC1 = P1; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start13 , end12 ) LC0 = P2; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC1 = P3; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000013; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000031; +CHECKREG r4, 0x0000005A; +CHECKREG r5, 0xFFFFFFD2; +CHECKREG r6, 0x00000017; +CHECKREG r7, 0x00000027; + +R0 = 0x05; +R1 = 0x08; +R2 = 0x12; +R3 = 0x24; +R4 = 0x18; +R5 = 0x20; +R6 = 0x32; +R7 = 0x46 (X); +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 1; + R1 += -1; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end14 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x00000011; +CHECKREG r1, 0xFFFFFFFC; +CHECKREG r2, 0x0000007E; +CHECKREG r3, 0x0000009D; +CHECKREG r4, 0x00000084; +CHECKREG r5, 0xFFFFFFB4; +CHECKREG r6, 0x000000F2; +CHECKREG r7, 0xFFFFFF86; + +pass diff --git a/tests/tcg/bfin/c_loopsetup_nested_prelc.s b/tests/tcg/bfin/c_loopsetup_nested_prelc.s new file mode 100644 index 0000000000000..f7de63cb209d6 --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_nested_prelc.s @@ -0,0 +1,184 @@ +//Original:/testcases/core/c_loopsetup_nested_prelc/c_loopsetup_nested_prelc.dsp +// Spec Reference: loopsetup nested preload lc0 lc1 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x12; +R3 = 0x14; +R4 = 0x18; +R5 = 0x16; +R6 = 0x16; +R7 = 0x18; + +LC0 = R0; +LC1 = R1; +LSETUP ( start1 , end1 ) LC0; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LC0 = R7; +LC1 = R6; +LSETUP ( start3 , end3 ) LC0; +start3: R6 += 6; +LSETUP ( start4 , end4 ) LC1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000037; +CHECKREG r1, 0xFFFFFFAC; +CHECKREG r2, 0x000000A8; +CHECKREG r3, 0x0000007E; +CHECKREG r4, 0x00000068; +CHECKREG r5, 0xFFFFFFB2; +CHECKREG r6, 0x000000A6; +CHECKREG r7, 0xFFFFFF70; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x08; +R3 = 0x0C; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); + +LC0 = R2; +LC1 = R3; +LSETUP ( start5 , end5 ) LC0; +start5: R4 += 1; +LSETUP ( start6 , end6 ) LC1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000008; +CHECKREG r3, 0x0000003F; +CHECKREG r4, 0x00000048; +CHECKREG r5, 0x00000040; +CHECKREG r6, 0x000000AC; +CHECKREG r7, 0x00000011; +LSETUP ( start7 , end7 ) LC0; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000008; +CHECKREG r3, 0x00000045; +CHECKREG r4, 0x0000004C; +CHECKREG r5, 0x0000003B; +CHECKREG r6, 0x000000AC; +CHECKREG r7, 0x00000011; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 12; +SP = 14; +FP = 16; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x14; +R3 = 0x18; +R4 = 0x16; +R5 = 0x04; +R6 = 0x30; +R7 = 0x30; + +LC0 = R5; +LC1 = R4; +LSETUP ( start11 , end11 ) LC0; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC1; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; + + +LSETUP ( start13 , end13 ) LC0 = P5; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC1 = P2; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000009; +CHECKREG r1, 0x0000000C; +CHECKREG r2, 0x00000018; +CHECKREG r3, 0x0000002A; +CHECKREG r4, 0x000000D7; +CHECKREG r5, 0xFFFFFF43; +CHECKREG r6, 0x0000003C; +CHECKREG r7, 0x00000024; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x14; +R7 = 0x08; +P4 = 6; +FP = 8; + +LC0 = R6; +LC1 = R7; +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 1; + R1 += -1; +LSETUP ( start16 , end16 ) LC1; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x00000026; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x00000058; +CHECKREG r5, 0x00000038; +CHECKREG r6, 0x00000021; +CHECKREG r7, 0xFFFFFFFB; + +pass diff --git a/tests/tcg/bfin/c_loopsetup_nested_top.s b/tests/tcg/bfin/c_loopsetup_nested_top.s new file mode 100644 index 0000000000000..54146a3f0c779 --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_nested_top.s @@ -0,0 +1,166 @@ +//Original:/testcases/core/c_loopsetup_nested_top/c_loopsetup_nested_top.dsp +// Spec Reference: loopsetup nested top +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LSETUP ( start3 , end3 ) LC1 = P3; +LSETUP ( start3 , end4 ) LC0 = P4; +start3: R6 += 6; + R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000012; +CHECKREG r1, 0xFFFFFFF6; +CHECKREG r2, 0x00000047; +CHECKREG r3, 0x0000004C; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0x00000014; +CHECKREG r6, 0x0000009C; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start5 , end5 ) LC0 = P5; +LSETUP ( start5 , end6 ) LC1 = SP >> 1; +start5: R4 += 1; + R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x0000005D; +CHECKREG r4, 0x0000004A; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000063; +CHECKREG r4, 0x0000006E; +CHECKREG r5, 0x00000015; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; + +P1 = 8; +P2 = 10; +P3 = 12; +P4 = 14; +P5 = 16; +SP = 18; +FP = 20; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1 >> 1; +LSETUP ( start11 , end15 ) LC0 = P5; +start11: R0 += 1; + R1 += -1; + R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1 = P3 >> 1; +LSETUP ( start12 , end13 ) LC0 = P2 >> 1; +start12: R6 += 1; + R4 += 1; +end13: R5 += -1; + R3 += 1; +end12: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000018; +CHECKREG r1, 0xFFFFFFFD; +CHECKREG r2, 0x00000024; +CHECKREG r3, 0x0000003C; +CHECKREG r4, 0x0000005D; +CHECKREG r5, 0x00000033; +CHECKREG r6, 0x0000006A; +CHECKREG r7, 0x0000006A; + +R0 = 0x04; +R1 = 0x06; +R2 = 0x08; +R3 = 0x10; +R4 = 0x12; +R5 = 0x14; +R6 = 0x16; +R7 = 0x18; +LSETUP ( start14 , end14 ) LC0 = P4; +LSETUP ( start14 , end16 ) LC1 = SP >> 1; +start14: R0 += 1; + R1 += -1; + R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x0000001A; +CHECKREG r1, 0xFFFFFFF0; +CHECKREG r2, 0x00000016; +CHECKREG r3, 0x0000002D; +CHECKREG r4, 0x0000009E; +CHECKREG r5, 0xFFFFFF88; +CHECKREG r6, 0x0000002C; +CHECKREG r7, 0x00000002; + +pass diff --git a/tests/tcg/bfin/c_loopsetup_overlap.s b/tests/tcg/bfin/c_loopsetup_overlap.s new file mode 100644 index 0000000000000..ff3b34346ed09 --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_overlap.s @@ -0,0 +1,167 @@ +//Original:/testcases/core/c_loopsetup_overlap/c_loopsetup_overlap.dsp +// Spec Reference: loopsetup overlap +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; + +LSETUP ( start3 , end3 ) LC1 = P3; +start3: R6 += 6; +LSETUP ( start4 , end4 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end3: R2 += 3; + R3 += 4; +end4: R7 += -7; + R3 += 1; +CHECKREG r0, 0x0000000F; +CHECKREG r1, 0xFFFFFFFC; +CHECKREG r2, 0x0000003E; +CHECKREG r3, 0x00000044; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0x00000014; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000005B; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +LSETUP ( start6 , end6 ) LC1 = SP >> 1; +start6: R6 += 4; +end5: R7 += -5; + R3 += 6; +end6: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x0000004B; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000048; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000051; +CHECKREG r4, 0x0000006B; +CHECKREG r5, 0x0000001B; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; + +P1 = 8; +P2 = 10; +P3 = 12; +P4 = 14; +P5 = 16; +SP = 18; +FP = 20; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC0 = P5; +start15: R4 += 5; +end11: R5 += -14; + R3 += 1; +end15: R2 += 17; + R3 += 12; +LSETUP ( start13 , end13 ) LC1 = P3; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC0 = P2; +start12: R4 += 22; +end13: R5 += -11; + R3 += 13; +end12: R7 += -1; + R3 += 14; +CHECKREG r0, 0x0000000D; +CHECKREG r1, 0x00000008; +CHECKREG r2, 0x00000130; +CHECKREG r3, 0x000000DC; +CHECKREG r4, 0x00000281; +CHECKREG r5, 0xFFFFFE27; +CHECKREG r6, 0x0000006C; +CHECKREG r7, 0x00000066; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 21; + R1 += -11; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 10; +end16: R7 += -12; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 31; +end14: R5 += -1; + R3 += 11; +end17: R2 += 41; + R3 += 1; +CHECKREG r0, 0x0000012B; +CHECKREG r1, 0xFFFFFF76; +CHECKREG r2, 0x000001BA; +CHECKREG r3, 0x000000AD; +CHECKREG r4, 0x00000309; +CHECKREG r5, 0x00000039; +CHECKREG r6, 0x00000A38; +CHECKREG r7, 0xFFFFF4A0; + +pass diff --git a/tests/tcg/bfin/c_loopsetup_preg_div2_lc0.s b/tests/tcg/bfin/c_loopsetup_preg_div2_lc0.s new file mode 100644 index 0000000000000..b14765973700f --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_preg_div2_lc0.s @@ -0,0 +1,95 @@ +//Original:/testcases/core/c_loopsetup_preg_div2_lc0/c_loopsetup_preg_div2_lc0.dsp +// Spec Reference: loopsetup preg lc0 / 2 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +P5 = 20; +P1 = 30; +P2 = 40; +P3 = 50; +P4 = 60; +//p5 = 7; +SP = 80 (X); +FP = 90 (X); + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1 >> 1; +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; +LSETUP ( start2 , end2 ) LC0 = P2 >> 1; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +LSETUP ( start3 , end3 ) LC0 = P3 >> 1; +start3: R6 += 6; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000014; +CHECKREG r1, 0xFFFFFFF2; +CHECKREG r2, 0x0000004D; +CHECKREG r3, 0x00000036; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0xFFFFFFEC; +CHECKREG r6, 0x000000F6; +CHECKREG r7, 0xFFFFFFC1; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start4 , end4 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +LSETUP ( start5 , end5 ) LC0 = P5 >> 1; +start5: R4 += 1; +end5: R5 += -2; + R3 += 3; +LSETUP ( start6 , end6 ) LC0 = SP >> 1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +CHECKREG r0, 0x00000023; +CHECKREG r1, 0xFFFFFFD4; +CHECKREG r2, 0x0000007A; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x0000004A; +CHECKREG r5, 0x0000003C; +CHECKREG r6, 0x00000100; +CHECKREG r7, 0xFFFFFFA8; +LSETUP ( start7 , end7 ) LC0 = FP >> 1; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000023; +CHECKREG r1, 0xFFFFFFD4; +CHECKREG r2, 0x0000007A; +CHECKREG r3, 0x00000043; +CHECKREG r4, 0x000000FE; +CHECKREG r5, 0xFFFFFF5B; +CHECKREG r6, 0x00000100; +CHECKREG r7, 0xFFFFFFA8; + + +pass diff --git a/tests/tcg/bfin/c_loopsetup_preg_div2_lc1.s b/tests/tcg/bfin/c_loopsetup_preg_div2_lc1.s new file mode 100644 index 0000000000000..73c7aa08f0415 --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_preg_div2_lc1.s @@ -0,0 +1,94 @@ +//Original:/testcases/core/c_loopsetup_preg_div2_lc1/c_loopsetup_preg_div2_lc1.dsp +// Spec Reference: loopsetup preg lc1 / 2 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1 >> 1; +start11: R0 += 1; + R1 += -1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1 = P2 >> 1; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P3 >> 1; +start13: R6 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x00000026; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000049; +CHECKREG r6, 0x00000068; +CHECKREG r7, 0x00000068; + +R0 = 0x06; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC1 = P4 >> 1; +start14: R0 += 1; + R1 += -1; +end14: R2 += 1; + R3 += 1; +LSETUP ( start15 , end15 ) LC1 = P5 >> 1; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +LSETUP ( start16 , end16 ) LC1 = SP >> 1; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +CHECKREG r0, 0x0000000F; +CHECKREG r1, 0x00000007; +CHECKREG r2, 0x00000029; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x0000004A; +CHECKREG r5, 0x00000046; +CHECKREG r6, 0x0000006B; +CHECKREG r7, 0x00000065; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +CHECKREG r0, 0x0000000F; +CHECKREG r1, 0x00000007; +CHECKREG r2, 0x00000029; +CHECKREG r3, 0x00000034; +CHECKREG r4, 0x00000056; +CHECKREG r5, 0x0000003A; +CHECKREG r6, 0x0000006B; +CHECKREG r7, 0x00000065; + +pass diff --git a/tests/tcg/bfin/c_loopsetup_preg_lc0.s b/tests/tcg/bfin/c_loopsetup_preg_lc0.s new file mode 100644 index 0000000000000..4429b1e07d54e --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_preg_lc0.s @@ -0,0 +1,95 @@ +//Original:/testcases/core/c_loopsetup_preg_lc0/c_loopsetup_preg_lc0.dsp +// Spec Reference: loopsetup preg lc0 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; +LSETUP ( start2 , end2 ) LC0 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +LSETUP ( start3 , end3 ) LC0 = P3; +start3: R6 += 6; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000008; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x00000029; +CHECKREG r3, 0x00000036; +CHECKREG r4, 0x00000050; +CHECKREG r5, 0x0000003C; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start4 , end4 ) LC0 = P4; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +end5: R5 += -2; + R3 += 3; +LSETUP ( start6 , end6 ) LC0 = SP; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x00000080; +CHECKREG r7, 0x00000048; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000043; +CHECKREG r4, 0x0000006B; +CHECKREG r5, 0x00000015; +CHECKREG r6, 0x00000080; +CHECKREG r7, 0x00000048; + + +pass diff --git a/tests/tcg/bfin/c_loopsetup_preg_lc1.s b/tests/tcg/bfin/c_loopsetup_preg_lc1.s new file mode 100644 index 0000000000000..8970f405311fb --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_preg_lc1.s @@ -0,0 +1,93 @@ +//Original:/testcases/core/c_loopsetup_preg_lc1/c_loopsetup_preg_lc1.dsp +// Spec Reference: loopsetup preg lc1 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1; +start11: R0 += 1; + R1 += -1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1 = P2; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P3; +start13: R6 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000011; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x0000002C; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x0000004E; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x00000060; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC1 = P4; +start14: R0 += 1; + R1 += -1; +end14: R2 += 1; + R3 += 1; +LSETUP ( start15 , end15 ) LC1 = P5; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x00000054; +CHECKREG r5, 0x0000003c; +CHECKREG r6, 0x00000076; +CHECKREG r7, 0x0000005A; +LSETUP ( start17 , end17 ) LC1 = FP; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000034; +CHECKREG r4, 0x0000006c; +CHECKREG r5, 0x00000024; +CHECKREG r6, 0x00000076; +CHECKREG r7, 0x0000005A; + +pass diff --git a/tests/tcg/bfin/c_loopsetup_prelc.s b/tests/tcg/bfin/c_loopsetup_prelc.s new file mode 100644 index 0000000000000..527988a1268c1 --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_prelc.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_loopsetup_prelc/c_loopsetup_prelc.dsp +// Spec Reference: loopsetup preload lc0 lc1 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); + +LC0 = R0; +LC1 = R1; + +LSETUP ( start1 , end1 ) LC0; +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; +LSETUP ( start2 , end2 ) LC1; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +LSETUP ( start3 , end3 ) LC0 = P3; +start3: R6 += 6; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x0000000a; +CHECKREG r1, 0x00000006; +CHECKREG r2, 0x0000002f; +CHECKREG r3, 0x00000036; +CHECKREG r4, 0x00000080; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); + +LC0 = R2; +LC1 = R3; + +LSETUP ( start4 , end4 ) LC0; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +LSETUP ( start5 , end5 ) LC1; +start5: R4 += 1; +end5: R5 += -2; + R3 += 3; + +LSETUP ( start6 , end6 ) LC0 = P2; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +CHECKREG r0, 0x00000025; +CHECKREG r1, 0xFFFFFFD0; +CHECKREG r2, 0x00000080; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0xFFFFFFF0; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x0000005C; +LSETUP ( start7 , end7 ) LC1; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000025; +CHECKREG r1, 0xFFFFFFD0; +CHECKREG r2, 0x00000080; +CHECKREG r3, 0x00000043; +CHECKREG r4, 0x00000074; +CHECKREG r5, 0xFFFFFFEB; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x0000005C; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x25; +R7 = 0x32; + +LC0 = R6; +LC1 = R7; +LSETUP ( start11 , end11 ) LC0; +start11: R0 += 1; + R1 += -1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P4; +start13: R6 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x0000002A; +CHECKREG r1, 0xFFFFFFEB; +CHECKREG r2, 0x00000045; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x00000072; +CHECKREG r5, 0x0000001E; +CHECKREG r6, 0x00000037; +CHECKREG r7, 0x00000020; + + +pass diff --git a/tests/tcg/bfin/c_loopsetup_topbotcntr.s b/tests/tcg/bfin/c_loopsetup_topbotcntr.s new file mode 100644 index 0000000000000..dc19b7dc13560 --- /dev/null +++ b/tests/tcg/bfin/c_loopsetup_topbotcntr.s @@ -0,0 +1,110 @@ +//Original:/proj/frio/dv/testcases/core/c_loopsetup_topbotcntr/c_loopsetup_topbotcntr.dsp +// Spec Reference: loopsetup top bot counter +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + + ASTAT = r0; + + R1 = 0x10; + R2 = 0x20; + R3 = 0x30; + R4 = 0x40 (X); + R5 = 0x08; + + loadsym R6, start1; + loadsym R7, end1; + + LT0 = R6; + LB0 = R7; + LC0 = R5; +//start immmediately +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; + + CHECKREG r0, 0x00000008; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000038; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000040; + CHECKREG r5, 0x00000008; +//CHECKREG r6, 0x00000090; +//CHECKREG r7, 0x00000094; + + R0 = 0x05; + R1 = 0x10; + R2 = 0x10; + R3 = 0x10; + R4 = 0x20; + R5 = 0x20; + R6 = 0x30; + R7 = 0x30; + + loadsym R1, start2; + R0 = R1; + loadsym R1, end2; + LT1 = R0; + LB1 = R1; + LC1 = R2; + +start2: R4 += 1; + R5 += 2; +end2: R6 += -3; + R7 += 4; + CHECKREG r3, 0x00000010; + CHECKREG r4, 0x00000030; + CHECKREG r5, 0x00000040; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000034; + + R0 = 0x05; + R1 = 0x10; + R2 = 0x20; + R3 = 0x30; + R4 = 0x40 (X); + R5 = 0x50 (X); + R6 = 0x60 (X); + R7 = 0x70 (X); + + loadsym R1, start3 + r0 = r1; + loadsym r1, end3; + LT0 = R0; + LB0 = R1; + LC0 = R2; + loadsym r3, start4; + loadsym r4, end4; + LT1 = R3; + LB1 = R4; + LC1 = R5; + + R0 = 0x10; + R1 = 0x15; + R2 = 0x20; + R3 = 0x26; + R4 = 0x30; + R5 = 0x40 (X); + +start3: R0 += 1; + R1 += -2; +start4: R2 += 3; + R3 += 4; +end4: R6 += 5; +end3: R7 += -6; + + CHECKREG r0, 0x00000030; + CHECKREG r1, 0xFFFFFFD5; + CHECKREG r2, 0x0000016D; + CHECKREG r3, 0x000001E2; + CHECKREG r4, 0x00000030; + CHECKREG r5, 0x00000040; + CHECKREG r6, 0x0000028B; + CHECKREG r7, 0xFFFFFFB0; + + pass diff --git a/tests/tcg/bfin/c_progctrl_call_pcpr.s b/tests/tcg/bfin/c_progctrl_call_pcpr.s new file mode 100644 index 0000000000000..4cc5b29528b9c --- /dev/null +++ b/tests/tcg/bfin/c_progctrl_call_pcpr.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_progctrl_call_pcpr/c_progctrl_call_pcpr.dsp +// Spec Reference: progctrl call (pc+pr) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + FP = SP; + + P2 = 0x0006; + +JMP: + CALL ( PC + P2 ); + JUMP.S JMP; + +STOP: + JUMP.S END; + +LAB1: + P2 = 0x000e; + R1 = 0x1111 (X); + RTS; + +LAB2: + P2 = 0x0016; + R2 = 0x2222 (X); + RTS; + +LAB3: + P2 = 0x001e; + R3 = 0x3333 (X); + RTS; + +LAB4: + P2 = 0x0026; + R4 = 0x4444 (X); + RTS; + +LAB5: + P2 = 0x0004; + R5 = 0x5555 (X); + RTS; + +END: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00001111; + CHECKREG r2, 0x00002222; + CHECKREG r3, 0x00003333; + CHECKREG r4, 0x00004444; + CHECKREG r5, 0x00005555; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass + + .data +DATA: + .space (0x0100); diff --git a/tests/tcg/bfin/c_progctrl_call_pr.s b/tests/tcg/bfin/c_progctrl_call_pr.s new file mode 100644 index 0000000000000..be8278e18230d --- /dev/null +++ b/tests/tcg/bfin/c_progctrl_call_pr.s @@ -0,0 +1,32 @@ +//Original:/testcases/core/c_progctrl_call_pr/c_progctrl_call_pr.dsp +// Spec Reference: progctrl call (pr) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + FP = SP; + + loadsym P1, SUBR; + CALL ( P1 ); + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00001111; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass + +SUBR: // should jump here + R1.L = 0x1111; + RTS; + R2.L = 0x2222; // should not go here + RTS; diff --git a/tests/tcg/bfin/c_progctrl_jump_pcpr.s b/tests/tcg/bfin/c_progctrl_jump_pcpr.s new file mode 100644 index 0000000000000..727025c1e4fb2 --- /dev/null +++ b/tests/tcg/bfin/c_progctrl_jump_pcpr.s @@ -0,0 +1,58 @@ +//Original:/testcases/core/c_progctrl_jump_pcpr/c_progctrl_jump_pcpr.dsp +// Spec Reference: progctrl jump pc+pr +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + + P2 = 0x0004; + +JMP: + JUMP ( PC + P2 ); +// jump JMP; + +STOP: +JUMP.S END; + +LAB1: + P2 = 0x000c; + R1 = 0x1111 (X); +JUMP.S JMP; + +LAB2: + P2 = 0x0014; + R2 = 0x2222 (X); +JUMP.S JMP; + +LAB3: + P2 = 0x001c; + R3 = 0x3333 (X); +JUMP.S JMP; + +LAB4: + P2 = 0x0024; + R4 = 0x4444 (X); +JUMP.S JMP; + +LAB5: + P2 = 0x0002; + R5 = 0x5555 (X); +JUMP.S JMP; + +END: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00002222; +CHECKREG r3, 0x00003333; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00005555; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/c_progctrl_jump_pr.s b/tests/tcg/bfin/c_progctrl_jump_pr.s new file mode 100644 index 0000000000000..8b77c3126e2cf --- /dev/null +++ b/tests/tcg/bfin/c_progctrl_jump_pr.s @@ -0,0 +1,56 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_jump_pr/c_progctrl_jump_pr.dsp +// Spec Reference: progctrl jump(p) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + loadsym p1, LAB1; + loadsym p2, LAB2; + loadsym fp, LAB3; + loadsym p4, LAB4; + loadsym p5, LAB5; + + JUMP ( P1 ); + +STOP: + JUMP.S END; + +LAB1: + R1 = 0x1111 (X); + JUMP ( P5 ); + R6 = 0x6666 (X); + +LAB2: + R2 = 0x2222 (X); + JUMP.S STOP; + +LAB3: + R3 = 0x3333 (X); + JUMP ( P2 ); + R7 = 0x7777 (X); + +LAB4: + R4 = 0x4444 (X); + JUMP ( FP ); + +LAB5: + R5 = 0x5555 (X); + JUMP ( P4 ); + +END: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00001111; + CHECKREG r2, 0x00002222; + CHECKREG r3, 0x00003333; + CHECKREG r4, 0x00004444; + CHECKREG r5, 0x00005555; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass diff --git a/tests/tcg/bfin/c_progctrl_nop.s b/tests/tcg/bfin/c_progctrl_nop.s new file mode 100644 index 0000000000000..77f744b3311d1 --- /dev/null +++ b/tests/tcg/bfin/c_progctrl_nop.s @@ -0,0 +1,55 @@ +//Original:/testcases/core/c_progctrl_nop/c_progctrl_nop.dsp +// Spec Reference: progctrl nop +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + + +I0 = 0x1122 (Z); +NOP; +R0 = I0; + +I1 = 0x3344 (Z); +NOP; +R1 = I1; + +I2 = 0x5566 (Z); +NOP; +R2 = I2; + +I3 = 0x7788 (Z); +NOP; +R3 = I3; + + +P2 = 0x99aa (Z); +NOP; NOP; +R4 = P2; + +P3 = 0xbbcc (Z); +NOP; NOP; +R5 = P3; + +P4 = 0xddee (Z); +NOP; NOP; +R6 = P4; + +P5 = 0x1234 (Z); +NOP; NOP; +R7 = P5; + +CHECKREG r0, 0x00001122; +CHECKREG r1, 0x00003344; +CHECKREG r2, 0x00005566; +CHECKREG r3, 0x00007788; +CHECKREG r4, 0x000099AA; +CHECKREG r5, 0x0000BBCC; +CHECKREG r6, 0x0000DDEE; +CHECKREG r7, 0x00001234; + + +pass diff --git a/tests/tcg/bfin/c_progctrl_rts.s b/tests/tcg/bfin/c_progctrl_rts.s new file mode 100644 index 0000000000000..3aa3bedd51d76 --- /dev/null +++ b/tests/tcg/bfin/c_progctrl_rts.s @@ -0,0 +1,36 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_rts/c_progctrl_rts.dsp +// Spec Reference: progctrl rts +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + loadsym R2, SUBR; + RETS = R2; + RTS; + +STOP: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r4, 0x00004444; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass + +SUBR: // should jump here + loadsym R3, STOP; + RETS = R3; + R4.L = 0x4444; + RTS; + RETS = R3; + R5.L = 0x5555; // should not go here + RTS; + + fail diff --git a/tests/tcg/bfin/c_ptr2op_pr_neg_pr.s b/tests/tcg/bfin/c_ptr2op_pr_neg_pr.s new file mode 100644 index 0000000000000..2d2784976a209 --- /dev/null +++ b/tests/tcg/bfin/c_ptr2op_pr_neg_pr.s @@ -0,0 +1,163 @@ +//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_neg_pr/c_ptr2op_pr_neg_pr.dsp +// Spec Reference: ptr2op preg -= preg +# mach: bfin + +.include "testutils.inc" + start + +// check p-reg to p-reg move + imm32 p1, 0xf0021003; + imm32 p2, 0x2e041005; + imm32 p3, 0x20d61007; + imm32 p4, 0x200a1009; + imm32 p5, 0x200a300b; + imm32 sp, 0x200c180d; + imm32 fp, 0x200e109f; + P1 -= P1; + P2 -= P1; + P3 -= P1; + P4 -= P1; + P5 -= P1; + SP -= P1; + FP -= P1; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x2E041005; + CHECKREG p3, 0x20D61007; + CHECKREG p4, 0x200A1009; + CHECKREG p5, 0x200A300B; + CHECKREG sp, 0x200C180D; + CHECKREG fp, 0x200E109F; + + imm32 p1, 0x50021003; + imm32 p2, 0x26041005; + imm32 p3, 0x20761007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a900b; + imm32 sp, 0x200c1a0d; + imm32 fp, 0x200e10bf; + P1 -= P2; + P2 -= P2; + P3 -= P2; + P4 -= P2; + P5 -= P2; + SP -= P2; + FP -= P2; + CHECKREG p1, 0x29FDFFFE; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x20761007; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x200A900B; + CHECKREG sp, 0x200C1A0D; + CHECKREG fp, 0x200E10BF; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 -= P3; + P2 -= P3; + P3 -= P3; + P4 -= P3; + P5 -= P3; + SP -= P3; + FP -= P3; + CHECKREG p1, 0xFFFBFFFC; + CHECKREG p2, 0xFFFDFFFE; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x200A100B; + CHECKREG sp, 0x200C100D; + CHECKREG fp, 0x200E100F; + + imm32 p1, 0xa0021003; + imm32 p2, 0x2c041005; + imm32 p3, 0x20b61007; + imm32 p4, 0x200d1009; + imm32 p5, 0x200ae00b; + imm32 sp, 0x200c110d; + imm32 fp, 0x200e104f; + P1 -= P4; + P2 -= P4; + P3 -= P4; + P4 -= P4; + P5 -= P4; + SP -= P4; + FP -= P4; + CHECKREG p1, 0x7FF4FFFA; + CHECKREG p2, 0x0BF6FFFC; + CHECKREG p3, 0x00A8FFFE; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0x200AE00B; + CHECKREG sp, 0x200C110D; + CHECKREG fp, 0x200E104F; + + imm32 p1, 0x10021003; + imm32 p2, 0x22041005; + imm32 p3, 0x20361007; + imm32 p4, 0x20041009; + imm32 p5, 0x200aa00b; + imm32 sp, 0x200c1b0d; + imm32 fp, 0x200e10cf; + P1 -= P5; + P2 -= P5; + P3 -= P5; + P4 -= P5; + P5 -= P5; + SP -= P5; + FP -= P5; + CHECKREG p1, 0xEFF76FF8; + CHECKREG p2, 0x01F96FFA; + CHECKREG p3, 0x002B6FFC; + CHECKREG p4, 0xFFF96FFE; + CHECKREG p5, 0x00000000; + CHECKREG sp, 0x200C1B0D; + CHECKREG fp, 0x200E10CF; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 -= SP; + P2 -= SP; + P3 -= SP; + P4 -= SP; + P5 -= SP; + SP -= SP; + FP -= SP; + CHECKREG p1, 0xFFF5FFF6; + CHECKREG p2, 0xFFF7FFF8; + CHECKREG p3, 0xFFF9FFFA; + CHECKREG p4, 0xFFFBFFFC; + CHECKREG p5, 0xFFFDFFFE; + CHECKREG sp, 0x00000000; + CHECKREG fp, 0x200E100F; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 -= FP; + P2 -= FP; + P3 -= FP; + P4 -= FP; + P5 -= FP; + SP -= FP; + FP -= FP; + CHECKREG p1, 0xFFF3FFF4; + CHECKREG p2, 0xFFF5FFF6; + CHECKREG p3, 0xFFF7FFF8; + CHECKREG p4, 0xFFF9FFFA; + CHECKREG p5, 0xFFFBFFFC; + CHECKREG sp, 0xFFFDFFFE; + CHECKREG fp, 0x00000000; + + pass diff --git a/tests/tcg/bfin/c_ptr2op_pr_sft_2_1.s b/tests/tcg/bfin/c_ptr2op_pr_sft_2_1.s new file mode 100644 index 0000000000000..dabd216cbc7fe --- /dev/null +++ b/tests/tcg/bfin/c_ptr2op_pr_sft_2_1.s @@ -0,0 +1,162 @@ +//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_sft_2_1/c_ptr2op_pr_sft_2_1.dsp +// Spec Reference: ptr2op preg = preg << 2 (>>2, >> 1) +# mach: bfin + +.include "testutils.inc" + start +// check p-reg to p-reg move + imm32 p1, 0xf0921203; + imm32 p2, 0xbe041305; + imm32 p3, 0xd0d61407; + imm32 p4, 0xa00a1089; + imm32 p5, 0x400a300b; + imm32 sp, 0xe07c180d; + imm32 fp, 0x206e109f; + P1 = P1 << 2; + P2 = P1 >> 2; + P3 = P1 << 2; + P4 = P1 >> 1; + P5 = P1 >> 2; + SP = P1 << 2; + FP = P1 >> 1; + CHECKREG p1, 0xC248480C; + CHECKREG p2, 0x30921203; + CHECKREG p3, 0x09212030; + CHECKREG p4, 0x61242406; + CHECKREG p5, 0x30921203; + CHECKREG sp, 0x09212030; + CHECKREG fp, 0x61242406; + + imm32 p1, 0x50021003; + imm32 p2, 0x26041005; + imm32 p3, 0x60761007; + imm32 p4, 0x20081009; + imm32 p5, 0xf00a900b; + imm32 sp, 0xb00c1a0d; + imm32 fp, 0x200e10bf; + P1 = P2; + P2 = P2; + P3 = P2; + P4 = P2; + P5 = P2; + SP = P2; + FP = P2; + CHECKREG p1, 0x26041005; + CHECKREG p2, 0x26041005; + CHECKREG p3, 0x26041005; + CHECKREG p4, 0x26041005; + CHECKREG p5, 0x26041005; + CHECKREG sp, 0x26041005; + CHECKREG fp, 0x26041005; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 = P3 << 2; + P2 = P3 >> 1; + P3 = P3 >> 2; + P4 = P3 << 2; + P5 = P3 << 2; + SP = P3 >> 1; + FP = P3 << 2; + CHECKREG p1, 0x8018401C; + CHECKREG p2, 0x10030803; + CHECKREG p3, 0x08018401; + CHECKREG p4, 0x20061004; + CHECKREG p5, 0x20061004; + CHECKREG sp, 0x0400C200; + CHECKREG fp, 0x20061004; + + imm32 p1, 0xa0021003; + imm32 p2, 0x2c041005; + imm32 p3, 0x40b61007; + imm32 p4, 0x250d1009; + imm32 p5, 0x260ae00b; + imm32 sp, 0x700c110d; + imm32 fp, 0x900e104f; + P1 = P4 >> 1; + P2 = P4 << 2; + P3 = P4 << 2; + P4 = P4 >> 2; + P5 = P4 << 2; + SP = P4 >> 2; + FP = P4 << 2; + CHECKREG p1, 0x12868804; + CHECKREG p2, 0x94344024; + CHECKREG p3, 0x94344024; + CHECKREG p4, 0x09434402; + CHECKREG p5, 0x250D1008; + CHECKREG sp, 0x0250D100; + CHECKREG fp, 0x250D1008; + + imm32 p1, 0x10021003; + imm32 p2, 0x22041005; + imm32 p3, 0x20361007; + imm32 p4, 0x20041009; + imm32 p5, 0x200aa00b; + imm32 sp, 0x200c1b0d; + imm32 fp, 0x200e10cf; + P1 = P5 << 2; + P2 = P5 >> 2; + P3 = P5 << 2; + P4 = P5 << 2; + P5 = P5 >> 1; + SP = P5 >> 2; + FP = P5 << 2; + CHECKREG p1, 0x802A802C; + CHECKREG p2, 0x0802A802; + CHECKREG p3, 0x802A802C; + CHECKREG p4, 0x802A802C; + CHECKREG p5, 0x10055005; + CHECKREG sp, 0x04015401; + CHECKREG fp, 0x40154014; + + imm32 p1, 0x50021003; + imm32 p2, 0x62041005; + imm32 p3, 0x70e61007; + imm32 p4, 0x290f1009; + imm32 p5, 0x700ab00b; + imm32 sp, 0x2a0c1d0d; + imm32 fp, 0xb00e1e0f; + P1 = SP << 2; + P2 = SP << 2; + P3 = SP >> 2; + P4 = SP << 2; + P5 = SP >> 2; + SP = SP >> 1; + FP = SP >> 2; + CHECKREG p1, 0xA8307434; + CHECKREG p2, 0xA8307434; + CHECKREG p3, 0x0A830743; + CHECKREG p4, 0xA8307434; + CHECKREG p5, 0x0A830743; + CHECKREG sp, 0x15060E86; + CHECKREG fp, 0x054183A1; + + imm32 p1, 0x32002003; + imm32 p2, 0x24004005; + imm32 p3, 0x20506007; + imm32 p4, 0x20068009; + imm32 p5, 0x200ae00b; + imm32 sp, 0x200c1f0d; + imm32 fp, 0x200e10bf; + P1 = FP >> 2; + P2 = FP >> 1; + P3 = FP << 2; + P4 = FP >> 2; + P5 = FP << 2; + SP = FP >> 2; + FP = FP << 2; + CHECKREG p1, 0x0803842F; + CHECKREG p2, 0x1007085F; + CHECKREG p3, 0x803842FC; + CHECKREG p4, 0x0803842F; + CHECKREG p5, 0x803842FC; + CHECKREG sp, 0x0803842F; + CHECKREG fp, 0x803842FC; + + pass diff --git a/tests/tcg/bfin/c_ptr2op_pr_shadd_1_2.s b/tests/tcg/bfin/c_ptr2op_pr_shadd_1_2.s new file mode 100644 index 0000000000000..dc6e2e82ca271 --- /dev/null +++ b/tests/tcg/bfin/c_ptr2op_pr_shadd_1_2.s @@ -0,0 +1,167 @@ +//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_shadd_1_2/c_ptr2op_pr_shadd_1_2.dsp +// Spec Reference: ptr2op shadd preg, pregs, 1 (2) +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + +// check p-reg to p-reg move + + imm32 p1, 0xf0921203; + imm32 p2, 0xbe041305; + imm32 p3, 0xd0d61407; + imm32 p4, 0xa00a1089; + imm32 p5, 0x400a300b; + imm32 sp, 0xe07c180d; + imm32 fp, 0x206e109f; + P1 = ( P1 + P1 ) << 2; + P2 = ( P2 + P1 ) << 2; + P3 = ( P3 + P1 ) << 2; + P4 = ( P4 + P1 ) << 1; + P5 = ( P5 + P1 ) << 2; + SP = ( SP + P1 ) << 2; + FP = ( FP + P1 ) << 1; + CHECKREG p1, 0x84909018; + CHECKREG p2, 0x0A528C74; + CHECKREG p3, 0x559A907C; + CHECKREG p4, 0x49354142; + CHECKREG p5, 0x126B008C; + CHECKREG sp, 0x9432A094; + CHECKREG fp, 0x49FD416E; + + imm32 p1, 0x50021003; + imm32 p2, 0x26041005; + imm32 p3, 0x60761007; + imm32 p4, 0x20081009; + imm32 p5, 0xf00a900b; + imm32 sp, 0xb00c1a0d; + imm32 fp, 0x200e10bf; + P1 = ( P1 + P2 ) << 1; + P2 = ( P2 + P2 ) << 2; + P3 = ( P3 + P2 ) << 1; + P4 = ( P4 + P2 ) << 2; + P5 = ( P5 + P2 ) << 2; + SP = ( SP + P2 ) << 1; + FP = ( FP + P2 ) << 2; + CHECKREG p1, 0xEC0C4010; + CHECKREG p2, 0x30208028; + CHECKREG p3, 0x212D205E; + CHECKREG p4, 0x40A240C4; + CHECKREG p5, 0x80AC40CC; + CHECKREG sp, 0xC059346A; + CHECKREG fp, 0x40BA439C; + + imm32 p1, 0x30026003; + imm32 p2, 0x40051005; + imm32 p3, 0x20e65057; + imm32 p4, 0x2d081089; + imm32 p5, 0xf00ab07b; + imm32 sp, 0x200c1b0d; + imm32 fp, 0x200e100f; + P1 = ( P1 + P3 ) << 2; + P2 = ( P2 + P3 ) << 1; + P3 = ( P3 + P3 ) << 2; + P4 = ( P4 + P3 ) << 2; + P5 = ( P5 + P3 ) << 2; + SP = ( SP + P3 ) << 1; + FP = ( FP + P3 ) << 2; + CHECKREG p1, 0x43A2C168; + CHECKREG p2, 0xC1D6C0B8; + CHECKREG p3, 0x073282B8; + CHECKREG p4, 0xD0EA4D04; + CHECKREG p5, 0xDCF4CCCC; + CHECKREG sp, 0x4E7D3B8A; + CHECKREG fp, 0x9D024B1C; + + imm32 p1, 0xa0021003; + imm32 p2, 0x2c041005; + imm32 p3, 0x40b61007; + imm32 p4, 0x250d1009; + imm32 p5, 0x260ae00b; + imm32 sp, 0x700c110d; + imm32 fp, 0x900e104f; + P1 = ( P1 + P4 ) << 1; + P2 = ( P2 + P4 ) << 2; + P3 = ( P3 + P4 ) << 2; + P4 = ( P4 + P4 ) << 2; + P5 = ( P5 + P4 ) << 1; + SP = ( SP + P4 ) << 2; + FP = ( FP + P4 ) << 2; + CHECKREG p1, 0x8A1E4018; + CHECKREG p2, 0x44448038; + CHECKREG p3, 0x970C8040; + CHECKREG p4, 0x28688048; + CHECKREG p5, 0x9CE6C0A6; + CHECKREG sp, 0x61D24554; + CHECKREG fp, 0xE1DA425C; + + imm32 p1, 0xae021003; + imm32 p2, 0x22041705; + imm32 p3, 0x20361487; + imm32 p4, 0x90743009; + imm32 p5, 0xa60aa00b; + imm32 sp, 0xb00c1b0d; + imm32 fp, 0x200e10cf; + P1 = ( P1 + P5 ) << 2; + P2 = ( P2 + P5 ) << 2; + P3 = ( P3 + P5 ) << 2; + P4 = ( P4 + P5 ) << 2; + P5 = ( P5 + P5 ) << 1; + SP = ( SP + P5 ) << 2; + FP = ( FP + P5 ) << 2; + CHECKREG p1, 0x5032C038; + CHECKREG p2, 0x203ADC40; + CHECKREG p3, 0x1902D248; + CHECKREG p4, 0xD9FB4050; + CHECKREG p5, 0x982A802C; + CHECKREG sp, 0x20DA6CE4; + CHECKREG fp, 0xE0E243EC; + + imm32 p1, 0x50021003; + imm32 p2, 0x62041005; + imm32 p3, 0x70e61007; + imm32 p4, 0x290f1009; + imm32 p5, 0x700ab00b; + imm32 sp, 0x2a0c1d0d; + imm32 fp, 0xb00e1e0f; + P1 = ( P1 + SP ) << 2; + P2 = ( P2 + SP ) << 1; + P3 = ( P3 + SP ) << 2; + P4 = ( P4 + SP ) << 2; + P5 = ( P5 + SP ) << 2; + SP = ( SP + SP ) << 1; + FP = ( FP + SP ) << 2; + CHECKREG p1, 0xE838B440; + CHECKREG p2, 0x18205A24; + CHECKREG p3, 0x6BC8B450; + CHECKREG p4, 0x4C6CB458; + CHECKREG p5, 0x685B3460; + CHECKREG sp, 0xA8307434; + CHECKREG fp, 0x60FA490C; + + imm32 p1, 0x32002003; + imm32 p2, 0x24004005; + imm32 p3, 0xe0506007; + imm32 p4, 0xd0068009; + imm32 p5, 0x230ae00b; + imm32 sp, 0x205c1f0d; + imm32 fp, 0x200e10bf; + P1 = ( P1 + FP ) << 2; + P2 = ( P2 + FP ) << 1; + P3 = ( P3 + FP ) << 2; + P4 = ( P4 + FP ) << 2; + P5 = ( P5 + FP ) << 2; + SP = ( SP + FP ) << 2; + FP = ( FP + FP ) << 2; + CHECKREG p1, 0x4838C308; + CHECKREG p2, 0x881CA188; + CHECKREG p3, 0x0179C318; + CHECKREG p4, 0xC0524320; + CHECKREG p5, 0x0C63C328; + CHECKREG sp, 0x01A8BF30; + CHECKREG fp, 0x007085F8; + + pass diff --git a/tests/tcg/bfin/c_pushpopmultiple_dp.s b/tests/tcg/bfin/c_pushpopmultiple_dp.s new file mode 100644 index 0000000000000..5d7de574ce059 --- /dev/null +++ b/tests/tcg/bfin/c_pushpopmultiple_dp.s @@ -0,0 +1,213 @@ +//Original:/testcases/core/c_pushpopmultiple_dp/c_pushpopmultiple_dp.dsp +// Spec Reference: pushpopmultiple dreg preg single group +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + P1 = 0xa1 (X); + P2 = 0xa2 (X); + P3 = 0xa3 (X); + P4 = 0xa4 (X); + P5 = 0xa5 (X); + [ -- SP ] = ( R7:0 ); + [ -- SP ] = ( P5:1 ); + + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + + P2 = 0xb2 (X); + P3 = 0xb3 (X); + P4 = 0xb4 (X); + P5 = 0xb5 (X); + [ -- SP ] = ( R7:1 ); + [ -- SP ] = ( P5:2 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + + P3 = 0xc3 (X); + P4 = 0xc4 (X); + P5 = 0xc5 (X); + [ -- SP ] = ( R7:2 ); + [ -- SP ] = ( P5:3 ); + + R3 = 0x34; + R4 = 0x35; + R5 = 0x36; + R6 = 0x37; + R7 = 0x38; + + P4 = 0xd4 (X); + P5 = 0xd5 (X); + [ -- SP ] = ( R7:3 ); + [ -- SP ] = ( P5:4 ); + + R4 = 0x45 (X); + R5 = 0x46 (X); + R6 = 0x47 (X); + R7 = 0x48 (X); + P5 = 0xe5 (X); + [ -- SP ] = ( R7:4 ); + [ -- SP ] = ( P5:5 ); + + R5 = 0x56 (X); + R6 = 0x57 (X); + R7 = 0x58 (X); + [ -- SP ] = ( R7:5 ); + R6 = 0x67 (X); + R7 = 0x68 (X); + [ -- SP ] = ( R7:6 ); + R7 = 0x78 (X); + [ -- SP ] = ( R7:7 ); + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + P1 = 0; + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( R7:7 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000078; + + ( R7:6 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000068; + + ( R7:5 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000057; + CHECKREG r7, 0x00000058; + + ( P5:5 ) = [ SP ++ ]; + ( R7:4 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0x000000e5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000046; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000048; + + ( P5:4 ) = [ SP ++ ]; + ( R7:3 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000d5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000035; + CHECKREG r5, 0x00000036; + CHECKREG r6, 0x00000037; + CHECKREG r7, 0x00000038; + + ( P5:3 ) = [ SP ++ ]; + ( R7:2 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000c4; + CHECKREG p5, 0x000000c5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000024; + CHECKREG r4, 0x00000025; + CHECKREG r5, 0x00000026; + CHECKREG r6, 0x00000027; + CHECKREG r7, 0x00000028; + + ( P5:2 ) = [ SP ++ ]; + ( R7:1 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000b3; + CHECKREG p4, 0x000000b4; + CHECKREG p5, 0x000000b5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000013; + CHECKREG r3, 0x00000014; + CHECKREG r4, 0x00000015; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000017; + CHECKREG r7, 0x00000018; + + ( P5:1 ) = [ SP ++ ]; + ( R7:0 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000a2; + CHECKREG p3, 0x000000a3; + CHECKREG p4, 0x000000a4; + CHECKREG p5, 0x000000a5; + + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000004; + CHECKREG r4, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000008; + pass diff --git a/tests/tcg/bfin/c_pushpopmultiple_dp_pair.s b/tests/tcg/bfin/c_pushpopmultiple_dp_pair.s new file mode 100644 index 0000000000000..78dae0130804b --- /dev/null +++ b/tests/tcg/bfin/c_pushpopmultiple_dp_pair.s @@ -0,0 +1,203 @@ +//Original:/testcases/core/c_pushpopmultiple_dp_pair/c_pushpopmultiple_dp_pair.dsp +// Spec Reference: pushpopmultiple dreg preg in group pair +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + P1 = 0xa1 (X); + P2 = 0xa2 (X); + P3 = 0xa3 (X); + P4 = 0xa4 (X); + P5 = 0xa5 (X); + [ -- SP ] = ( R7:0, P5:1 ); + + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + + P2 = 0xb2 (X); + P3 = 0xb3 (X); + P4 = 0xb4 (X); + P5 = 0xb5 (X); + [ -- SP ] = ( R7:1, P5:2 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + + P3 = 0xc3 (X); + P4 = 0xc4 (X); + P5 = 0xc5 (X); + [ -- SP ] = ( R7:2, P5:3 ); + + R3 = 0x34; + R4 = 0x35; + R5 = 0x36; + R6 = 0x37; + R7 = 0x38; + + P4 = 0xd4 (X); + P5 = 0xd5 (X); + [ -- SP ] = ( R7:3, P5:4 ); + + R4 = 0x45 (X); + R5 = 0x46 (X); + R6 = 0x47 (X); + R7 = 0x48 (X); + P5 = 0xe5 (X); + [ -- SP ] = ( R7:4, P5:5 ); + + R5 = 0x56 (X); + R6 = 0x57 (X); + R7 = 0x58 (X); + [ -- SP ] = ( R7:5 ); + R6 = 0x67 (X); + R7 = 0x68 (X); + [ -- SP ] = ( R7:6 ); + R7 = 0x78 (X); + [ -- SP ] = ( R7:7 ); + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + P1 = 0; + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( R7:7 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000078; + + ( R7:6 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000068; + + ( R7:5 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000057; + CHECKREG r7, 0x00000058; + + ( R7:4, P5:5 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0x000000e5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000046; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000048; + + ( R7:3, P5:4 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000d5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000035; + CHECKREG r5, 0x00000036; + CHECKREG r6, 0x00000037; + CHECKREG r7, 0x00000038; + + ( R7:2, P5:3 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000c4; + CHECKREG p5, 0x000000c5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000024; + CHECKREG r4, 0x00000025; + CHECKREG r5, 0x00000026; + CHECKREG r6, 0x00000027; + CHECKREG r7, 0x00000028; + + ( R7:1, P5:2 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000b3; + CHECKREG p4, 0x000000b4; + CHECKREG p5, 0x000000b5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000013; + CHECKREG r3, 0x00000014; + CHECKREG r4, 0x00000015; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000017; + CHECKREG r7, 0x00000018; + + ( R7:0, P5:1 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000a2; + CHECKREG p3, 0x000000a3; + CHECKREG p4, 0x000000a4; + CHECKREG p5, 0x000000a5; + + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000004; + CHECKREG r4, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000008; + pass diff --git a/tests/tcg/bfin/c_pushpopmultiple_dreg.s b/tests/tcg/bfin/c_pushpopmultiple_dreg.s new file mode 100644 index 0000000000000..ca1ebf1e2820e --- /dev/null +++ b/tests/tcg/bfin/c_pushpopmultiple_dreg.s @@ -0,0 +1,173 @@ +//Original:/testcases/core/c_pushpopmultiple_dreg/c_pushpopmultiple_dreg.dsp +// Spec Reference: pushpopmultiple dreg +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:0 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000004; + CHECKREG r4, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000008; + + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + [ -- SP ] = ( R7:1 ); + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:1 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000013; + CHECKREG r3, 0x00000014; + CHECKREG r4, 0x00000015; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000017; + CHECKREG r7, 0x00000018; + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + [ -- SP ] = ( R7:2 ); + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:2 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000024; + CHECKREG r4, 0x00000025; + CHECKREG r5, 0x00000026; + CHECKREG r6, 0x00000027; + CHECKREG r7, 0x00000028; + + R3 = 0x34; + R4 = 0x35; + R5 = 0x36; + R6 = 0x37; + R7 = 0x38; + [ -- SP ] = ( R7:3 ); + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:3 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000035; + CHECKREG r5, 0x00000036; + CHECKREG r6, 0x00000037; + CHECKREG r7, 0x00000038; + + R4 = 0x45 (X); + R5 = 0x46 (X); + R6 = 0x47 (X); + R7 = 0x48 (X); + [ -- SP ] = ( R7:4 ); + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:4 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000046; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000048; + + R5 = 0x56 (X); + R6 = 0x57 (X); + R7 = 0x58 (X); + [ -- SP ] = ( R7:5 ); + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:5 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000057; + CHECKREG r7, 0x00000058; + + R6 = 0x67 (X); + R7 = 0x68 (X); + [ -- SP ] = ( R7:6 ); + R6 = 0; + R7 = 0; + ( R7:6 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000068; + + R7 = 0x78 (X); + [ -- SP ] = ( R7:7 ); + R7 = 0; + ( R7:7 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000078; + + pass diff --git a/tests/tcg/bfin/c_pushpopmultiple_preg.s b/tests/tcg/bfin/c_pushpopmultiple_preg.s new file mode 100644 index 0000000000000..15c1937b39f51 --- /dev/null +++ b/tests/tcg/bfin/c_pushpopmultiple_preg.s @@ -0,0 +1,83 @@ +//Original:/testcases/core/c_pushpopmultiple_preg/c_pushpopmultiple_preg.dsp +// Spec Reference: pushpopmultiple preg +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + P1 = 0xa1 (X); + P2 = 0xa2 (X); + P3 = 0xa3 (X); + P4 = 0xa4 (X); + P5 = 0xa5 (X); + [ -- SP ] = ( P5:1 ); + P1 = 0; + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( P5:1 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000a2; + CHECKREG p3, 0x000000a3; + CHECKREG p4, 0x000000a4; + CHECKREG p5, 0x000000a5; + + P2 = 0xb2 (X); + P3 = 0xb3 (X); + P4 = 0xb4 (X); + P5 = 0xb5 (X); + [ -- SP ] = ( P5:2 ); + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( P5:2 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000b3; + CHECKREG p4, 0x000000b4; + CHECKREG p5, 0x000000b5; + + P3 = 0xc3 (X); + P4 = 0xc4 (X); + P5 = 0xc5 (X); + [ -- SP ] = ( P5:3 ); + P3 = 0; + P4 = 0; + P5 = 0; + ( P5:3 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000c4; + CHECKREG p5, 0x000000c5; + + P4 = 0xd4 (X); + P5 = 0xd5 (X); + [ -- SP ] = ( P5:4 ); + P4 = 0; + P5 = 0; + ( P5:4 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000d5; + + P5 = 0xe5 (X); + [ -- SP ] = ( P5:5 ); + P5 = 0; + ( P5:5 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000e5; + + pass diff --git a/tests/tcg/bfin/c_regmv_acc_acc.s b/tests/tcg/bfin/c_regmv_acc_acc.s new file mode 100644 index 0000000000000..08e4414cfac4e --- /dev/null +++ b/tests/tcg/bfin/c_regmv_acc_acc.s @@ -0,0 +1,125 @@ +//Original:/testcases/core/c_regmv_acc_acc/c_regmv_acc_acc.dsp +// Spec Reference: regmv acc-acc +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0xa9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0x0004000d; + imm32 r7, 0x000e500f; + A0 = R0; + + A1 = A0; + R2 = A1.w; + R3 = A1.x; + + A1.x = A0.w; + A1.w = A0.w; + A0.x = A0.w; + A0.w = A0.w; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + + CHECKREG r0, 0xA9627911; + CHECKREG r1, 0xD0158978; + CHECKREG r2, 0xA9627911; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r4, 0xA9627911; + CHECKREG r5, 0x00000011; + CHECKREG r6, 0xA9627911; + CHECKREG r7, 0x00000011; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A1 = R0; + + A0 = A1; + R2 = A0.w; + R3 = A0.x; + + A0.x = A1.w; + A0.w = A1.w; + A1.x = A1.w; + A1.w = A1.w; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0x90BA7911; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r4, 0x90BA7911; + CHECKREG r5, 0x00000011; + CHECKREG r6, 0x90BA7911; + CHECKREG r7, 0x00000011; + + imm32 r0, 0xf9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x789e534f; + A0 = R0; + + A0.x = A0.x; + A0.w = A0.x; + A1.w = A0.x; + A1.x = A0.x; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + CHECKREG r0, 0xF9627911; + CHECKREG r1, 0xD0158978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0xFFFFFFFF; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A1 = R0; + + A0.x = A1.x; + A0.w = A1.x; + A1.w = A1.x; + A1.x = A1.x; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0xFFFFFFFF; + + pass diff --git a/tests/tcg/bfin/c_regmv_dag_lz_dep.s b/tests/tcg/bfin/c_regmv_dag_lz_dep.s new file mode 100644 index 0000000000000..fb95a7324dc55 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_dag_lz_dep.s @@ -0,0 +1,148 @@ +//Original:/testcases/core/c_regmv_dag_lz_dep/c_regmv_dag_lz_dep.dsp +// Spec Reference: regmv dag lz dep forward +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 r0, 0x11111111; +imm32 r1, 0x22223331; +imm32 r2, 0x44445551; +imm32 r3, 0x66667771; +imm32 r4, 0x88889991; +imm32 r5, 0xaaaabbb1; +imm32 r6, 0xccccddd1; +imm32 r7, 0xeeeefff1; + +I0 = R0; +I0 = 0x1122 (Z); +R0 = I0; + +I1 = R1; +I1 = 0x3344 (Z); +R1 = I1; + +I2 = R2; +I2 = 0x5566 (Z); +R2 = I2; + +I3 = R3; +I3 = 0x7788 (Z); +R3 = I3; + + +B0 = R4; +B0 = 0x99aa (Z); +R4 = B0; + +B1 = R5; +B1 = 0xbbcc (Z); +R5 = B1; + +B2 = R6; +B2 = 0xddee (Z); +R6 = B2; + +B3 = R7; +B3 = 0xff01 (Z); +R7 = B3; + +CHECKREG r0, 0x00001122; +CHECKREG r1, 0x00003344; +CHECKREG r2, 0x00005566; +CHECKREG r3, 0x00007788; +CHECKREG r4, 0x000099AA; +CHECKREG r5, 0x0000BBCC; +CHECKREG r6, 0x0000DDEE; +CHECKREG r7, 0x0000FF01; + +imm32 r0, 0x11111112; +imm32 r1, 0x22223332; +imm32 r2, 0x44445552; +imm32 r3, 0x66667772; +imm32 r4, 0x88889992; +imm32 r5, 0xaaaabbb2; +imm32 r6, 0xccccddd2; +imm32 r7, 0xeeeefff2; +M0 = R0; +M0 = 0xa1a2 (Z); +R0 = M0; + +M1 = R1; +M1 = 0xb1b2 (Z); +R1 = M1; + +M2 = R2; +M2 = 0xc1c2 (Z); +R2 = M2; + +M3 = R3; +M3 = 0xd1d2 (Z); +R3 = M3; + + +L0 = R4; +L0 = 0xe1e2 (Z); +R4 = L0; + +L1 = R5; +L1 = 0xf1f2 (Z); +R5 = L1; + +L2 = R6; +L2 = 0x1112 (Z); +R6 = L2; + +L3 = R7; +L3 = 0x2122 (Z); +R7 = L3; + +CHECKREG r0, 0x0000A1A2; +CHECKREG r1, 0x0000B1B2; +CHECKREG r2, 0x0000C1C2; +CHECKREG r3, 0x0000D1D2; +CHECKREG r4, 0x0000E1E2; +CHECKREG r5, 0x0000F1F2; +CHECKREG r6, 0x00001112; +CHECKREG r7, 0x00002122; + +imm32 r0, 0x11111113; +imm32 r1, 0x22223333; +imm32 r2, 0x44445553; +imm32 r3, 0x66667773; +imm32 r4, 0x88889993; +imm32 r5, 0xaaaabbb3; +imm32 r6, 0xccccddd3; +imm32 r7, 0xeeeefff3; + +P1 = R1; +P1 = 0x3A3B (Z); +R1 = P1; + + +P2 = R2; +P2 = 0x4A4B (Z); +R2 = P2; + +P3 = R3; +P3 = 0x5A5B (Z); +R3 = P3; + +P4 = R4; +P4 = 0x6A6B (Z); +R4 = P4; + +P5 = R5; +P5 = 0x7A7B (Z); +R5 = P5; + +CHECKREG r1, 0x00003A3B; +CHECKREG r2, 0x00004A4B; +CHECKREG r3, 0x00005A5B; +CHECKREG r4, 0x00006A6B; +CHECKREG r5, 0x00007A7B; + +pass diff --git a/tests/tcg/bfin/c_regmv_dr_acc_acc.s b/tests/tcg/bfin/c_regmv_dr_acc_acc.s new file mode 100644 index 0000000000000..6af3d04dde6ce --- /dev/null +++ b/tests/tcg/bfin/c_regmv_dr_acc_acc.s @@ -0,0 +1,191 @@ +//Original:/testcases/core/c_regmv_dr_acc_acc/c_regmv_dr_acc_acc.dsp +// Spec Reference: regmv dreg-acc-acc +# mach: bfin + +.include "testutils.inc" + start + + + +// check R-reg to ACC + imm32 r0, 0x00000000; + imm32 r1, 0x12345678; + imm32 r2, 0x91234567; + imm32 r3, 0x00060007; + imm32 r4, 0x00080009; + imm32 r5, 0x000a000b; + imm32 r6, 0x000c000d; + imm32 r7, 0x000e000f; + A0 = R0; + A1 = R0; + A0 = R1; + A1 = R2; + + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x12345678; + CHECKREG r2, 0x91234567; + CHECKREG r3, 0x12345678; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x91234567; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0x000E000F; + + A1 = A0 = 0; + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + + imm32 r0, 0xa5678901; + imm32 r1, 0xb0158978; + imm32 r2, 0x91234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0x0004000d; + imm32 r7, 0x000e500f; + A0 = R0; + A1 = R1; + + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r0, 0xA5678901; + CHECKREG r1, 0xB0158978; + CHECKREG r2, 0x91234567; + CHECKREG r3, 0xA5678901; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, 0xB0158978; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0x000E500F; + + imm32 r0, 0xe9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0x0004000d; + imm32 r7, 0x000e500f; + A0 = R0; + A1 = A0; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A0.w = R0; + A0.x = R1; + A1.w = R2; + A1.x = R3; + + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0x90BA7911; + CHECKREG r5, 0x00000078; + CHECKREG r6, 0xC1234567; + CHECKREG r7, 0x00000007; + + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x90BA7911; + CHECKREG r4, 0x00000078; + CHECKREG r5, 0xC1234567; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000007; + + imm32 r0, 0xf9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x789e534f; + A0 = R6; + A1.w = A0.w; + A1.x = A0.x; + + R0 = A0.w; + R1 = A0.x; + R2 = A1.w; + R3 = A1.x; + + A1 = R7; + A0.w = A1.w; + A0.x = A1.x; + + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + + CHECKREG r0, 0xF247890D; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r2, 0xF247890D; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r4, 0x789E534F; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x789E534F; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A0.w = A1.x; + A0.x = A1.x; + R4 = A0.w; + R5 = A0.x; + + A0 = R2; + A1.w = A0.x; + A1.x = A0.x; + + R6 = A1.w; + R7 = A1.x; + + A0.x = A1.w; + A1.x = A0.w; + R0 = A0.x; + R1 = A1.x; + + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x00000067; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0xFFFFFFFF; + + pass diff --git a/tests/tcg/bfin/c_regmv_dr_dep_nostall.s b/tests/tcg/bfin/c_regmv_dr_dep_nostall.s new file mode 100644 index 0000000000000..118274dfd8852 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_dr_dep_nostall.s @@ -0,0 +1,245 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_dr_dep_nostall/c_regmv_dr_dep_nostall.dsp +// Spec Reference: regmv dr-dep no stall +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000001; + imm32 r1, 0x00110001; + imm32 r2, 0x00220002; + imm32 r3, 0x00330003; + imm32 r4, 0x00440004; + imm32 r5, 0x00550005; + imm32 r6, 0x00660006; + imm32 r7, 0x00770007; +// R-reg to R-reg: no stall + R0 = R0; + R1 = R0; + R2 = R1; + R3 = R2; + R4 = R3; + R5 = R4; + R6 = R5; + R7 = R6; + R0 = R7; + + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000001; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0x00000001; + CHECKREG r6, 0x00000001; + CHECKREG r7, 0x00000001; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22223333; + imm32 p2, 0x44445555; + imm32 p3, 0x66667777; + imm32 p4, 0x88889999; + imm32 p5, 0xaaaabbbb; + imm32 fp, 0xccccdddd; + imm32 sp, 0xeeeeffff; + +// P-reg to R-reg to I,M reg: no stall + R0 = P0; + I0 = R0; + R1 = P1; + I1 = R1; + R2 = P2; + I2 = R2; + R3 = P3; + I3 = R3; + R4 = P4; + M0 = R4; + R5 = P5; + M1 = R5; + R6 = FP; + M2 = R6; + R7 = SP; + M3 = R7; + + CHECKREG r1, 0x22223333; + CHECKREG r2, 0x44445555; + CHECKREG r3, 0x66667777; + CHECKREG r4, 0x88889999; + CHECKREG r5, 0xAAAABBBB; + CHECKREG r6, 0xCCCCDDDD; + CHECKREG r7, 0xEEEEFFFF; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0xEEEEFFFF; + CHECKREG r1, 0xCCCCDDDD; + CHECKREG r2, 0xAAAABBBB; + CHECKREG r3, 0x88889999; + CHECKREG r4, 0x66667777; + CHECKREG r5, 0x44445555; + CHECKREG r6, 0x22223333; + + imm32 i0, 0x00001111; + imm32 i1, 0x22223333; + imm32 i2, 0x44445555; + imm32 i3, 0x66667777; + imm32 m0, 0x88889999; + imm32 m0, 0xaaaabbbb; + imm32 m0, 0xccccdddd; + imm32 m0, 0xeeeeffff; + +// I,M-reg to R-reg to P-reg: no stall + R0 = I0; + P1 = R0; + R1 = I1; + P1 = R1; + R2 = I2; + P2 = R2; + R3 = I3; + P3 = R3; + R4 = M0; + P4 = R4; + R5 = M1; + P5 = R5; + R6 = M2; + SP = R6; + R7 = M3; + FP = R7; + + CHECKREG p1, 0x22223333; + CHECKREG p2, 0x44445555; + CHECKREG p3, 0x66667777; + CHECKREG p4, 0xEEEEFFFF; + CHECKREG p5, 0xAAAABBBB; + CHECKREG sp, 0xCCCCDDDD; + CHECKREG fp, 0xEEEEFFFF; + + imm32 i0, 0x10001111; + imm32 i1, 0x12221333; + imm32 i2, 0x14441555; + imm32 i3, 0x16661777; + imm32 m0, 0x18881999; + imm32 m1, 0x1aaa1bbb; + imm32 m2, 0x1ccc1ddd; + imm32 m3, 0x1eee1fff; + +// I,M-reg to R-reg to L,B reg: no stall + R0 = I0; + L0 = R0; + R1 = I1; + L1 = R1; + R2 = I2; + L2 = R2; + R3 = I3; + L3 = R3; + R4 = M0; + B0 = R4; + R5 = M1; + B1 = R5; + R6 = M2; + B2 = R6; + R7 = M3; + B3 = R7; + + CHECKREG r0, 0x10001111; + CHECKREG r1, 0x12221333; + CHECKREG r2, 0x14441555; + CHECKREG r3, 0x16661777; + CHECKREG r4, 0x18881999; + CHECKREG r5, 0x1AAA1BBB; + CHECKREG r6, 0x1CCC1DDD; + CHECKREG r7, 0x1EEE1FFF; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x16661777; + CHECKREG r1, 0x14441555; + CHECKREG r2, 0x12221333; + CHECKREG r3, 0x10001111; + CHECKREG r4, 0x1EEE1FFF; + CHECKREG r5, 0x1CCC1DDD; + CHECKREG r6, 0x1AAA1BBB; + CHECKREG r7, 0x18881999; + + imm32 l0, 0x20003111; + imm32 l1, 0x22223333; + imm32 l2, 0x24443555; + imm32 l3, 0x26663777; + imm32 b0, 0x28883999; + imm32 b0, 0x2aaa3bbb; + imm32 b0, 0x2ccc3ddd; + imm32 b0, 0x2eee3fff; + +// L,B-reg to R-reg to I,M reg: no stall + R0 = L0; + I0 = R0; + R1 = L1; + I1 = R1; + R2 = L2; + I2 = R2; + R3 = L3; + I3 = R3; + R4 = B0; + M0 = R4; + R5 = B1; + M1 = R5; + R6 = B2; + M2 = R6; + R7 = B3; + M3 = R7; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x1EEE1FFF; + CHECKREG r1, 0x1CCC1DDD; + CHECKREG r2, 0x1AAA1BBB; + CHECKREG r3, 0x2EEE3FFF; + CHECKREG r4, 0x26663777; + CHECKREG r5, 0x24443555; + CHECKREG r6, 0x22223333; + CHECKREG r7, 0x20003111; + + imm32 r0, 0x00000030; + imm32 r1, 0x00000031; + imm32 r2, 0x00000003; + imm32 r3, 0x00330003; + imm32 r4, 0x00440004; + imm32 r5, 0x00550005; + imm32 r6, 0x00660006; + imm32 r7, 0x00770007; + +// R-reg to R-reg to sysreg to Reg: no stall + R3 = R0; + ASTAT = R3; + R6 = ASTAT; + R4 = R1; + RETS = R4; + R7 = RETS; + + CHECKREG r0, 0x00000030; + CHECKREG r1, 0x00000031; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000030; + CHECKREG r4, 0x00000031; + CHECKREG r5, 0x00550005; + CHECKREG r6, 0x00000030; + CHECKREG r7, 0x00000031; + + pass diff --git a/tests/tcg/bfin/c_regmv_dr_dr.s b/tests/tcg/bfin/c_regmv_dr_dr.s new file mode 100644 index 0000000000000..e1fb6582d96f8 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_dr_dr.s @@ -0,0 +1,209 @@ +//Original:/testcases/core/c_regmv_dr_dr/c_regmv_dr_dr.dsp +// Spec Reference: regmv dreg-to-dreg +# mach: bfin + +.include "testutils.inc" + start + +// check R-reg to R-reg move +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R0; +R1 = R0; +R2 = R0; +R3 = R0; +R4 = R0; +R5 = R0; +R6 = R0; +R7 = R0; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R1; +R1 = R1; +R2 = R1; +R3 = R1; +R4 = R1; +R5 = R1; +R6 = R1; +R7 = R1; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R2; +R1 = R2; +R2 = R2; +R3 = R2; +R4 = R2; +R5 = R2; +R6 = R2; +R7 = R2; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R3; +R1 = R3; +R2 = R3; +R3 = R3; +R4 = R3; +R5 = R3; +R6 = R3; +R7 = R3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R4; +R1 = R4; +R2 = R4; +R3 = R4; +R4 = R4; +R5 = R4; +R6 = R4; +R7 = R4; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R5; +R1 = R5; +R2 = R5; +R3 = R5; +R4 = R5; +R5 = R5; +R6 = R5; +R7 = R5; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R6; +R1 = R6; +R2 = R6; +R3 = R6; +R4 = R6; +R5 = R6; +R6 = R6; +R7 = R6; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R7; +R1 = R7; +R2 = R7; +R3 = R7; +R4 = R7; +R5 = R7; +R6 = R7; +R7 = R7; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +pass diff --git a/tests/tcg/bfin/c_regmv_dr_imlb.s b/tests/tcg/bfin/c_regmv_dr_imlb.s new file mode 100644 index 0000000000000..01650b0f9f4d5 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_dr_imlb.s @@ -0,0 +1,539 @@ +//Original:/testcases/core/c_regmv_dr_imlb/c_regmv_dr_imlb.dsp +// Spec Reference: regmv dreg-to-imlb +# mach: bfin + +.include "testutils.inc" + start + +// check DR-reg to imlb-reg move +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R0; +I1 = R0; +I2 = R0; +I3 = R0; +M0 = R0; +M1 = R0; +M2 = R0; +M3 = R0; + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R1; +I1 = R1; +I2 = R1; +I3 = R1; +M0 = R1; +M1 = R1; +M2 = R1; +M3 = R1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R2; +I1 = R2; +I2 = R2; +I3 = R2; +M0 = R2; +M1 = R2; +M2 = R2; +M3 = R2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R3; +I1 = R3; +I2 = R3; +I3 = R3; +M0 = R3; +M1 = R3; +M2 = R3; +M3 = R3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R4; +I1 = R4; +I2 = R4; +I3 = R4; +M0 = R4; +M1 = R4; +M2 = R4; +M3 = R4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R5; +I1 = R5; +I2 = R5; +I3 = R5; +M0 = R5; +M1 = R5; +M2 = R5; +M3 = R5; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R6; +I1 = R6; +I2 = R6; +I3 = R6; +M0 = R6; +M1 = R6; +M2 = R6; +M3 = R6; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R7; +I1 = R7; +I2 = R7; +I3 = R7; +M0 = R7; +M1 = R7; +M2 = R7; +M3 = R7; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R0; +L1 = R0; +L2 = R0; +L3 = R0; +B0 = R0; +B1 = R0; +B2 = R0; +B3 = R0; + +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R1; +L1 = R1; +L2 = R1; +L3 = R1; +B0 = R1; +B1 = R1; +B2 = R1; +B3 = R1; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R2; +L1 = R2; +L2 = R2; +L3 = R2; +B0 = R2; +B1 = R2; +B2 = R2; +B3 = R2; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R3; +L1 = R3; +L2 = R3; +L3 = R3; +B0 = R3; +B1 = R3; +B2 = R3; +B3 = R3; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R4; +L1 = R4; +L2 = R4; +L3 = R4; +B0 = R4; +B1 = R4; +B2 = R4; +B3 = R4; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R5; +L1 = R5; +L2 = R5; +L3 = R5; +B0 = R5; +B1 = R5; +B2 = R5; +B3 = R5; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R6; +L1 = R6; +L2 = R6; +L3 = R6; +B0 = R6; +B1 = R6; +B2 = R6; +B3 = R6; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R7; +L1 = R7; +L2 = R7; +L3 = R7; +B0 = R7; +B1 = R7; +B2 = R7; +B3 = R7; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +pass diff --git a/tests/tcg/bfin/c_regmv_dr_pr.s b/tests/tcg/bfin/c_regmv_dr_pr.s new file mode 100644 index 0000000000000..fd8967c71a1f3 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_dr_pr.s @@ -0,0 +1,107 @@ +//Original:/testcases/core/c_regmv_dr_pr/c_regmv_dr_pr.dsp +// Spec Reference: regmv dreg-to-preg +# mach: bfin + +.include "testutils.inc" + start + +// check R-reg to R-reg move + imm32 r0, 0x20001001; + imm32 r1, 0x20021003; + imm32 r2, 0x20041005; + imm32 r3, 0x20061007; + imm32 r4, 0x20081009; + imm32 r5, 0x200a100b; + imm32 r6, 0x200c100d; + imm32 r7, 0x200e100f; + + P1 = R0; + P2 = R0; + P4 = R0; + P5 = R0; + FP = R0; + CHECKREG p1, 0x20001001; + CHECKREG p2, 0x20001001; + CHECKREG p4, 0x20001001; + CHECKREG p5, 0x20001001; + CHECKREG fp, 0x20001001; + + P1 = R1; + P2 = R1; + P4 = R1; + P5 = R1; + FP = R1; + CHECKREG p1, 0x20021003; + CHECKREG p2, 0x20021003; + CHECKREG p4, 0x20021003; + CHECKREG p5, 0x20021003; + CHECKREG fp, 0x20021003; + + P1 = R2; + P2 = R2; + P4 = R2; + P5 = R2; + FP = R2; + CHECKREG p1, 0x20041005; + CHECKREG p2, 0x20041005; + CHECKREG p4, 0x20041005; + CHECKREG p5, 0x20041005; + CHECKREG fp, 0x20041005; + + P1 = R3; + P2 = R3; + P4 = R3; + P5 = R3; + FP = R3; + CHECKREG p1, 0x20061007; + CHECKREG p2, 0x20061007; + CHECKREG p4, 0x20061007; + CHECKREG p5, 0x20061007; + CHECKREG fp, 0x20061007; + + P1 = R4; + P2 = R4; + P4 = R4; + P5 = R4; + FP = R4; + CHECKREG p1, 0x20081009; + CHECKREG p2, 0x20081009; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x20081009; + CHECKREG fp, 0x20081009; + + P1 = R5; + P2 = R5; + P4 = R5; + P5 = R5; + FP = R5; + CHECKREG p1, 0x200a100b; + CHECKREG p2, 0x200a100b; + CHECKREG p4, 0x200a100b; + CHECKREG p5, 0x200a100b; + CHECKREG fp, 0x200a100b; + + P1 = R6; + P2 = R6; + P4 = R6; + P5 = R6; + FP = R6; + CHECKREG p1, 0x200c100d; + CHECKREG p2, 0x200c100d; + CHECKREG p4, 0x200c100d; + CHECKREG p5, 0x200c100d; + CHECKREG fp, 0x200c100d; + + P1 = R7; + P2 = R7; + P4 = R7; + P5 = R7; + FP = R7; + CHECKREG p1, 0x200e100f; + CHECKREG p2, 0x200e100f; + CHECKREG p4, 0x200e100f; + CHECKREG p5, 0x200e100f; + CHECKREG fp, 0x200e100f; + +End: + pass diff --git a/tests/tcg/bfin/c_regmv_imlb_dep_nostall.s b/tests/tcg/bfin/c_regmv_imlb_dep_nostall.s new file mode 100644 index 0000000000000..cda1fb151fca1 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_imlb_dep_nostall.s @@ -0,0 +1,664 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_nostall/c_regmv_imlb_dep_nostall.dsp +// Spec Reference: regmv imlb-dep no stall +# mach: bfin + +.include "testutils.inc" + start + +// P-reg to I,M-reg to R-reg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x12213330; + imm32 p2, 0x14415550; + imm32 p3, 0x16617770; + imm32 p4, 0x18819990; + imm32 p5, 0x1aa1bbb0; + imm32 fp, 0x1cc1ddd0; + imm32 sp, 0x1ee1fff0; + I0 = P0; + R0 = I0; + I1 = P1; + R1 = I1; + I2 = P2; + R2 = I2; + I3 = P3; + R3 = I3; + M0 = P4; + R4 = M0; + M1 = P5; + R5 = M1; + M2 = SP; + R6 = M2; + M3 = FP; + R7 = M3; + + CHECKREG r1, 0x12213330; + CHECKREG r2, 0x14415550; + CHECKREG r3, 0x16617770; + CHECKREG r4, 0x18819990; + CHECKREG r5, 0x1aa1bbb0; + CHECKREG r6, 0x1EE1FFF0; + CHECKREG r7, 0x1CC1DDD0; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x1CC1DDD0; + CHECKREG r1, 0x1EE1FFF0; + CHECKREG r2, 0x1AA1BBB0; + CHECKREG r3, 0x18819990; + CHECKREG r4, 0x16617770; + CHECKREG r5, 0x14415550; + CHECKREG r6, 0x12213330; + +// P-reg to L,B-reg to R-reg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x21213331; + imm32 p2, 0x21415551; + imm32 p3, 0x21617771; + imm32 p4, 0x21819991; + imm32 p5, 0x21a1bbb1; + imm32 fp, 0x21c1ddd1; + imm32 sp, 0x21e1fff1; + L0 = P0; + R0 = L0; + L1 = P1; + R1 = L1; + L2 = P2; + R2 = L2; + L3 = P3; + R3 = L3; + B0 = P4; + R4 = B0; + B1 = P5; + R5 = B1; + B2 = SP; + R6 = B2; + B3 = FP; + R7 = B3; + + CHECKREG r1, 0x21213331; + CHECKREG r2, 0x21415551; + CHECKREG r3, 0x21617771; + CHECKREG r4, 0x21819991; + CHECKREG r5, 0x21a1bbb1; + CHECKREG r6, 0x21E1FFF1; + CHECKREG r7, 0x21C1DDD1; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x21617771; + CHECKREG r1, 0x21415551; + CHECKREG r2, 0x21213331; + CHECKREG r4, 0x21C1DDD1; + CHECKREG r5, 0x21E1FFF1; + CHECKREG r6, 0x21A1BBB1; + CHECKREG r7, 0x21819991; + +// P-reg to I,M-reg to L,B-reg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x72213337; + imm32 p2, 0x74415557; + imm32 p3, 0x76617777; + imm32 p4, 0x78819997; + imm32 p5, 0x7aa1bbb7; + imm32 fp, 0x7cc1ddd7; + imm32 sp, 0x77e1fff7; + I0 = P0; + L0 = I0; + I1 = P1; + L1 = I1; + I2 = P2; + L2 = I2; + I3 = P3; + L3 = I3; + M0 = P4; + B0 = M0; + M1 = P5; + B1 = M1; + M2 = SP; + B2 = M2; + M3 = FP; + B3 = M3; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x76617777; + CHECKREG r1, 0x74415557; + CHECKREG r2, 0x72213337; + CHECKREG r4, 0x7CC1DDD7; + CHECKREG r5, 0x77E1FFF7; + CHECKREG r6, 0x7AA1BBB7; + CHECKREG r7, 0x78819997; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x7CC1DDD7; + CHECKREG r1, 0x77E1FFF7; + CHECKREG r2, 0x7AA1BBB7; + CHECKREG r3, 0x78819997; + CHECKREG r4, 0x76617777; + CHECKREG r5, 0x74415557; + CHECKREG r6, 0x72213337; + +// P-reg to L,B-reg to I,Mreg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x81213338; + imm32 p2, 0x81415558; + imm32 p3, 0x81617778; + imm32 p4, 0x81819998; + imm32 p5, 0x81a1bbb8; + imm32 fp, 0x81c1ddd8; + imm32 sp, 0x81e1fff8; + L0 = P0; + I0 = L0; + L1 = P1; + I1 = L1; + L2 = P2; + I2 = L2; + L3 = P3; + I3 = L3; + B0 = P4; + M0 = B0; + B1 = P5; + M1 = B1; + B2 = SP; + M2 = B2; + B3 = FP; + M3 = B3; + + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x81819998; + CHECKREG r1, 0x81A1BBB8; + CHECKREG r2, 0x81E1FFF8; + CHECKREG r3, 0x81C1DDD8; + CHECKREG r5, 0x81213338; + CHECKREG r6, 0x81415558; + CHECKREG r7, 0x81617778; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x81617778; + CHECKREG r1, 0x81415558; + CHECKREG r2, 0x81213338; + CHECKREG r4, 0x81C1DDD8; + CHECKREG r5, 0x81E1FFF8; + CHECKREG r6, 0x81A1BBB8; + CHECKREG r7, 0x81819998; + +// I-to-M, I-to-I and to R-reg: no stall + imm32 i0, 0x30001111; + imm32 i1, 0x23213332; + imm32 i2, 0x14315552; + imm32 i3, 0x01637772; + imm32 m0, 0x80113992; + imm32 m1, 0xaa01b3b2; + imm32 m2, 0xccc01d32; + imm32 m3, 0xeee101f3; + M0 = I0; + R4 = M0; + M1 = I1; + R5 = M1; + M2 = I2; + R6 = M2; + M3 = I3; + R7 = M3; + I0 = I3; + R0 = I0; + I1 = I2; + R1 = I1; + I3 = I0; + R2 = I3; + I2 = I1; + R3 = I2; + + CHECKREG r0, 0x01637772; + CHECKREG r1, 0x14315552; + CHECKREG r2, 0x01637772; + CHECKREG r3, 0x14315552; + CHECKREG r4, 0x30001111; + CHECKREG r5, 0x23213332; + CHECKREG r6, 0x14315552; + CHECKREG r7, 0x01637772; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x30001111; + CHECKREG r1, 0x23213332; + CHECKREG r2, 0x14315552; + CHECKREG r3, 0x01637772; + CHECKREG r4, 0x01637772; + CHECKREG r5, 0x14315552; + CHECKREG r6, 0x14315552; + CHECKREG r7, 0x01637772; + +// I-to-M, I-to-I and to P-reg: no stall + imm32 i0, 0x00001111; + imm32 i1, 0x42213342; + imm32 i2, 0x44415542; + imm32 i3, 0x46617742; + imm32 m0, 0x48819942; + imm32 m1, 0x4aa1bb42; + imm32 m2, 0x4cc1dd42; + imm32 m3, 0x4ee1ff42; + M0 = I0; + R0 = M0; + M1 = I1; + P1 = M1; + M2 = I2; + P2 = M2; + M3 = I3; + P3 = M3; + I0 = I3; + P4 = I0; + I1 = I2; + P5 = I1; + I2 = I0; + SP = I2; + I3 = I1; + FP = I3; + + CHECKREG r0, 0x00001111; + CHECKREG p1, 0x42213342; + CHECKREG p2, 0x44415542; + CHECKREG p3, 0x46617742; + CHECKREG p4, 0x46617742; + CHECKREG p5, 0x44415542; + CHECKREG sp, 0x46617742; + CHECKREG fp, 0x44415542; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x00001111; + CHECKREG r1, 0x42213342; + CHECKREG r2, 0x44415542; + CHECKREG r3, 0x46617742; + CHECKREG r4, 0x46617742; + CHECKREG r5, 0x44415542; + CHECKREG r6, 0x46617742; + CHECKREG r7, 0x44415542; + +// L-to-B, L-to-L and to R-reg: no stall + imm32 l0, 0x40001114; + imm32 l1, 0x24213334; + imm32 l2, 0x54415554; + imm32 l3, 0x05647774; + imm32 b0, 0x60514994; + imm32 b1, 0xa605b4b4; + imm32 b2, 0xcc605d44; + imm32 b3, 0xeee605f4; + B0 = L0; + R4 = B0; + B1 = L1; + R5 = B1; + B2 = L2; + R6 = B2; + B3 = L3; + R7 = B3; + L0 = L3; + R0 = L0; + L1 = L2; + R1 = L1; + L3 = L0; + R2 = L3; + L2 = L1; + R3 = L2; + + CHECKREG r0, 0x05647774; + CHECKREG r1, 0x54415554; + CHECKREG r2, 0x05647774; + CHECKREG r3, 0x54415554; + CHECKREG r4, 0x40001114; + CHECKREG r5, 0x24213334; + CHECKREG r6, 0x54415554; + CHECKREG r7, 0x05647774; + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x05647774; + CHECKREG r1, 0x54415554; + CHECKREG r2, 0x54415554; + CHECKREG r3, 0x05647774; + CHECKREG r4, 0x40001114; + CHECKREG r5, 0x24213334; + CHECKREG r6, 0x54415554; + CHECKREG r7, 0x05647774; + +// L-to-B, L-to-L and to P-reg: no stall + imm32 l0, 0x60001116; + imm32 l1, 0x46213346; + imm32 l2, 0x74615546; + imm32 l3, 0x47667746; + imm32 b0, 0x48716946; + imm32 b1, 0x8aa7b646; + imm32 b2, 0x48c17d66; + imm32 b3, 0x4e81f746; + M0 = I0; + R0 = M0; + M1 = I1; + P1 = M1; + M2 = I2; + P2 = M2; + M3 = I3; + P3 = M3; + I0 = I3; + P4 = I0; + I1 = I2; + P5 = I1; + I2 = I0; + SP = I2; + I3 = I1; + FP = I3; + + CHECKREG r0, 0x46617742; + CHECKREG p1, 0x44415542; + CHECKREG p2, 0x46617742; + CHECKREG p3, 0x44415542; + CHECKREG p4, 0x44415542; + CHECKREG p5, 0x46617742; + CHECKREG sp, 0x44415542; + CHECKREG fp, 0x46617742; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x46617742; + CHECKREG r1, 0x44415542; + CHECKREG r2, 0x46617742; + CHECKREG r3, 0x44415542; + CHECKREG r4, 0x44415542; + CHECKREG r5, 0x46617742; + CHECKREG r6, 0x44415542; + CHECKREG r7, 0x46617742; + +// I-to-M-to-L, I-to-I-to-B -reg: no stall + imm32 i0, 0x90001119; + imm32 i1, 0x93213339; + imm32 i2, 0x94315559; + imm32 i3, 0x91637779; + imm32 m0, 0x90113999; + imm32 m1, 0x9a01b3b9; + imm32 m2, 0x9cc01d39; + imm32 m3, 0x9ee101f9; + M0 = I0; + L0 = M0; + M1 = I1; + L1 = M1; + M2 = I2; + L2 = M2; + M3 = I3; + L3 = M3; + I0 = I3; + B0 = I0; + I1 = I2; + B1 = I1; + I3 = I0; + B2 = I3; + I2 = I1; + B3 = I2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x90001119; + CHECKREG r1, 0x93213339; + CHECKREG r2, 0x94315559; + CHECKREG r3, 0x91637779; + CHECKREG r4, 0x91637779; + CHECKREG r5, 0x94315559; + CHECKREG r6, 0x91637779; + CHECKREG r7, 0x94315559; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x90001119; + CHECKREG r1, 0x93213339; + CHECKREG r2, 0x94315559; + CHECKREG r3, 0x91637779; + CHECKREG r4, 0x91637779; + CHECKREG r5, 0x94315559; + CHECKREG r6, 0x94315559; + CHECKREG r7, 0x91637779; + +// I-to-M-B, I-to-I-L reg: no stall + imm32 i0, 0xa000111a; + imm32 i1, 0xaa21334a; + imm32 i2, 0xa4a1554a; + imm32 i3, 0xa66a774a; + imm32 m0, 0xa881a94a; + imm32 m1, 0xaaa1ba4a; + imm32 m2, 0xacc1ddaa; + imm32 m3, 0xaee1ff4a; + M0 = I0; + B3 = M0; + M1 = I1; + B2 = M1; + M2 = I2; + B1 = M2; + M3 = I3; + B0 = M3; + I0 = I3; + L1 = I0; + I1 = I2; + L2 = I1; + I2 = I0; + L3 = I2; + I3 = I1; + L0 = I3; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xA4A1554A; + CHECKREG r1, 0xA66A774A; + CHECKREG r2, 0xA4A1554A; + CHECKREG r3, 0xA66A774A; + CHECKREG r4, 0xA66A774A; + CHECKREG r5, 0xA4A1554A; + CHECKREG r6, 0xAA21334A; + CHECKREG r7, 0xA000111A; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0xA000111A; + CHECKREG r1, 0xAA21334A; + CHECKREG r2, 0xA4A1554A; + CHECKREG r3, 0xA66A774A; + CHECKREG r4, 0xA66A774A; + CHECKREG r5, 0xA4A1554A; + CHECKREG r6, 0xA66A774A; + CHECKREG r7, 0xA4A1554A; + +// L-to-B-to-I, L-to-L-to-M reg: no stall + imm32 l0, 0xb000111b; + imm32 l1, 0xb421333b; + imm32 l2, 0xb441555b; + imm32 l3, 0xb564777b; + imm32 b0, 0xb051499b; + imm32 b1, 0xb605b4bb; + imm32 b2, 0xbc605d4b; + imm32 b3, 0xbee605fb; + B0 = L0; + I2 = B0; + B1 = L1; + I3 = B1; + B2 = L2; + I0 = B2; + B3 = L3; + I1 = B3; + L0 = L3; + M0 = L0; + L1 = L2; + M1 = L1; + L3 = L0; + M2 = L3; + L2 = L1; + M3 = L2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xB441555B; + CHECKREG r1, 0xB564777B; + CHECKREG r2, 0xB000111B; + CHECKREG r3, 0xB421333B; + CHECKREG r4, 0xB564777B; + CHECKREG r5, 0xB441555B; + CHECKREG r6, 0xB564777B; + CHECKREG r7, 0xB441555B; + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xB564777B; + CHECKREG r1, 0xB441555B; + CHECKREG r2, 0xB441555B; + CHECKREG r3, 0xB564777B; + CHECKREG r4, 0xB000111B; + CHECKREG r5, 0xB421333B; + CHECKREG r6, 0xB441555B; + CHECKREG r7, 0xB564777B; + +// B-to-L-to-M, B-to-B-to-I reg: no stall + imm32 l0, 0xc000111c; + imm32 l1, 0xc621334c; + imm32 l2, 0xc461554c; + imm32 l3, 0xc766774c; + imm32 b0, 0xc871694c; + imm32 b1, 0xcaa7b64c; + imm32 b2, 0xc8c17d6c; + imm32 b3, 0xce81f74c; + L0 = B0; + M1 = L0; + L1 = B1; + M2 = L1; + L2 = B2; + M3 = L2; + L3 = B3; + M0 = L3; + B3 = B0; + I0 = B3; + B0 = B1; + I1 = B0; + B1 = B2; + I2 = B1; + B2 = B3; + I3 = B2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xC871694C; + CHECKREG r1, 0xCAA7B64C; + CHECKREG r2, 0xC8C17D6C; + CHECKREG r3, 0xCE81F74C; + CHECKREG r4, 0xCAA7B64C; + CHECKREG r5, 0xC8C17D6C; + CHECKREG r6, 0xC871694C; + CHECKREG r7, 0xC871694C; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0xCE81F74C; + CHECKREG r1, 0xC871694C; + CHECKREG r2, 0xCAA7B64C; + CHECKREG r3, 0xC8C17D6C; + CHECKREG r4, 0xC871694C; + CHECKREG r5, 0xCAA7B64C; + CHECKREG r6, 0xC8C17D6C; + CHECKREG r7, 0xC871694C; + + pass diff --git a/tests/tcg/bfin/c_regmv_imlb_dep_stall.s b/tests/tcg/bfin/c_regmv_imlb_dep_stall.s new file mode 100644 index 0000000000000..8fd22355f2fe6 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_imlb_dep_stall.s @@ -0,0 +1,335 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_stall/c_regmv_imlb_dep_stall.dsp +// Spec Reference: regmv imlb-depepency stall +# mach: bfin + +.include "testutils.inc" + start + +// R-reg to I,M-reg to R-reg: stall + imm32 r0, 0x00001110; + imm32 r1, 0x00213330; + imm32 r2, 0x04015550; + imm32 r3, 0x06607770; + imm32 r4, 0x08010990; + imm32 r5, 0x0a01b0b0; + imm32 r6, 0x0c01dd00; + imm32 r7, 0x0e01f0f0; + I0 = R0; + R7 = I0; + I1 = R1; + R0 = I1; + I2 = R2; + R1 = I2; + I3 = R3; + R2 = I3; + M0 = R4; + R3 = M0; + M1 = R5; + R4 = M1; + M2 = R6; + R5 = M2; + M3 = R7; + R6 = M3; + + CHECKREG r0, 0x00213330; + CHECKREG r1, 0x04015550; + CHECKREG r2, 0x06607770; + CHECKREG r3, 0x08010990; + CHECKREG r4, 0x0A01B0B0; + CHECKREG r5, 0x0C01DD00; + CHECKREG r6, 0x00001110; + CHECKREG r7, 0x00001110; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x00001110; + CHECKREG r1, 0x0C01DD00; + CHECKREG r2, 0x0A01B0B0; + CHECKREG r3, 0x08010990; + CHECKREG r4, 0x06607770; + CHECKREG r5, 0x04015550; + CHECKREG r6, 0x00213330; + CHECKREG r7, 0x00001110; + +// R-to-M,I and to P-reg: stall + imm32 i0, 0x00001111; + imm32 i1, 0x12213341; + imm32 i2, 0x14415541; + imm32 i3, 0x16617741; + imm32 m0, 0x18819941; + imm32 m1, 0x1aa1bb41; + imm32 m2, 0x1cc1dd41; + imm32 m3, 0x1ee1ff41; + M0 = R0; + R0 = M0; + M1 = R1; + P1 = M1; + M2 = R2; + P2 = M2; + M3 = R3; + P3 = M3; + I0 = R4; + P4 = I0; + I1 = R5; + P5 = I1; + I2 = R6; + SP = I2; + I3 = R7; + FP = I3; + + CHECKREG r0, 0x00001110; + CHECKREG p1, 0x0C01DD00; + CHECKREG p2, 0x0A01B0B0; + CHECKREG p3, 0x08010990; + CHECKREG p4, 0x06607770; + CHECKREG p5, 0x04015550; + CHECKREG sp, 0x00213330; + CHECKREG fp, 0x00001110; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x00001110; + CHECKREG r1, 0x0C01DD00; + CHECKREG r2, 0x0A01B0B0; + CHECKREG r3, 0x08010990; + CHECKREG r4, 0x06607770; + CHECKREG r5, 0x04015550; + CHECKREG r6, 0x00213330; + CHECKREG r7, 0x00001110; + +// R-reg to L,B-reg to R-reg: stall + imm32 r0, 0x20001112; + imm32 r1, 0x22213332; + imm32 r2, 0x21215552; + imm32 r3, 0x21627772; + imm32 r4, 0x21812992; + imm32 r5, 0x21a1b2b2; + imm32 r6, 0x21c1d222; + imm32 r7, 0x21e1ff22; + L0 = R1; + R0 = L0; + L1 = R2; + R1 = L1; + L2 = R3; + R2 = L2; + L3 = R4; + R3 = L3; + B0 = R5; + R4 = B0; + B1 = R6; + R5 = B1; + B2 = R7; + R6 = B2; + B3 = R0; + R7 = B3; + + CHECKREG r0, 0x22213332; + CHECKREG r1, 0x21215552; + CHECKREG r2, 0x21627772; + CHECKREG r3, 0x21812992; + CHECKREG r4, 0x21A1B2B2; + CHECKREG r5, 0x21C1D222; + CHECKREG r6, 0x21E1FF22; + CHECKREG r7, 0x22213332; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x21812992; + CHECKREG r1, 0x21627772; + CHECKREG r2, 0x21215552; + CHECKREG r3, 0x22213332; + CHECKREG r4, 0x22213332; + CHECKREG r5, 0x21E1FF22; + CHECKREG r6, 0x21C1D222; + CHECKREG r7, 0x21A1B2B2; + +// R-reg to L,B-reg to P-reg: stall + imm32 r0, 0x50001115; + imm32 r1, 0x51213335; + imm32 r2, 0x51415555; + imm32 r3, 0x51617775; + imm32 r4, 0x51819995; + imm32 r5, 0x51a1bbb5; + imm32 r6, 0x51c1ddd5; + imm32 r7, 0x51e1fff5; + L0 = R1; + R0 = L0; + L1 = R2; + SP = L1; + L2 = R3; + FP = L2; + L3 = R4; + P1 = L3; + B0 = R5; + P2 = B0; + B1 = R6; + P3 = B1; + B2 = R7; + P4 = B2; + B3 = R0; + P5 = B3; + + CHECKREG r0, 0x51213335; + CHECKREG p1, 0x51819995; + CHECKREG p2, 0x51A1BBB5; + CHECKREG p3, 0x51C1DDD5; + CHECKREG p4, 0x51E1FFF5; + CHECKREG p5, 0x51213335; + CHECKREG sp, 0x51415555; + CHECKREG fp, 0x51617775; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x51819995; + CHECKREG r1, 0x51617775; + CHECKREG r2, 0x51415555; + CHECKREG r3, 0x51213335; + CHECKREG r4, 0x51213335; + CHECKREG r5, 0x51E1FFF5; + CHECKREG r6, 0x51C1DDD5; + CHECKREG r7, 0x51A1BBB5; + +// R-reg to I,M-reg to L,B-reg: stall + imm32 r0, 0x00001111; + imm32 r1, 0x72213337; + imm32 r2, 0x74415557; + imm32 r3, 0x76617777; + imm32 r4, 0x78819997; + imm32 r5, 0x7aa1bbb7; + imm32 r6, 0x7cc1ddd7; + imm32 r7, 0x77e1fff7; + I0 = R0; + L0 = I0; + I1 = R1; + L1 = I1; + I2 = R2; + L2 = I2; + I3 = R3; + L3 = I3; + M0 = R4; + B0 = M0; + M1 = R5; + B1 = M1; + M2 = R6; + B2 = M2; + M3 = R7; + B3 = M3; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x76617777; + CHECKREG r1, 0x74415557; + CHECKREG r2, 0x72213337; + CHECKREG r3, 0x00001111; + CHECKREG r4, 0x77E1FFF7; + CHECKREG r5, 0x7CC1DDD7; + CHECKREG r6, 0x7AA1BBB7; + CHECKREG r7, 0x78819997; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x77E1FFF7; + CHECKREG r1, 0x7CC1DDD7; + CHECKREG r2, 0x7AA1BBB7; + CHECKREG r3, 0x78819997; + CHECKREG r4, 0x76617777; + CHECKREG r5, 0x74415557; + CHECKREG r6, 0x72213337; + CHECKREG r7, 0x00001111; + +// R-reg to L,B-reg to I,M reg: stall + imm32 r0, 0x00001111; + imm32 r1, 0x81213338; + imm32 r2, 0x81415558; + imm32 r3, 0x81617778; + imm32 r4, 0x81819998; + imm32 r5, 0x81a1bbb8; + imm32 r6, 0x81c1ddd8; + imm32 r7, 0x81e1fff8; + L0 = R0; + I0 = L0; + L1 = R1; + I1 = L1; + L2 = R2; + I2 = L2; + L3 = R3; + I3 = L3; + B0 = R4; + M0 = B0; + B1 = R5; + M1 = B1; + B2 = R6; + M2 = B2; + B3 = R7; + M3 = B3; + + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x81819998; + CHECKREG r1, 0x81A1BBB8; + CHECKREG r2, 0x81C1DDD8; + CHECKREG r3, 0x81E1FFF8; + CHECKREG r4, 0x00001111; + CHECKREG r5, 0x81213338; + CHECKREG r6, 0x81415558; + CHECKREG r7, 0x81617778; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x81617778; + CHECKREG r1, 0x81415558; + CHECKREG r2, 0x81213338; + CHECKREG r3, 0x00001111; + CHECKREG r4, 0x81E1FFF8; + CHECKREG r5, 0x81C1DDD8; + CHECKREG r6, 0x81A1BBB8; + CHECKREG r7, 0x81819998; + + pass diff --git a/tests/tcg/bfin/c_regmv_imlb_dr.s b/tests/tcg/bfin/c_regmv_imlb_dr.s new file mode 100644 index 0000000000000..ec15df0158dc5 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_imlb_dr.s @@ -0,0 +1,313 @@ +//Original:/testcases/core/c_regmv_imlb_dr/c_regmv_imlb_dr.dsp +// Spec Reference: regmv imlb to dr +# mach: bfin + +.include "testutils.inc" + start + + + + + + +// initialize source regs +imm32 i0, 0x11111111; +imm32 i1, 0x22222222; +imm32 i2, 0x33333333; +imm32 i3, 0x44444444; + + +// i to dreg +R0 = I0; +R1 = I0; +R2 = I0; +R3 = I0; +R4 = I1; +R5 = I1; +R6 = I1; +R7 = I1; +CHECKREG r0, 0x11111111; +CHECKREG r1, 0x11111111; +CHECKREG r2, 0x11111111; +CHECKREG r3, 0x11111111; +CHECKREG r4, 0x22222222; +CHECKREG r5, 0x22222222; +CHECKREG r6, 0x22222222; +CHECKREG r7, 0x22222222; + +R0 = I1; +R1 = I1; +R2 = I1; +R3 = I1; +R4 = I0; +R5 = I0; +R6 = I0; +R7 = I0; +CHECKREG r0, 0x22222222; +CHECKREG r1, 0x22222222; +CHECKREG r2, 0x22222222; +CHECKREG r3, 0x22222222; +CHECKREG r4, 0x11111111; +CHECKREG r5, 0x11111111; +CHECKREG r6, 0x11111111; +CHECKREG r7, 0x11111111; + + +// i to dreg +R0 = I2; +R1 = I2; +R2 = I2; +R3 = I2; +R4 = I3; +R5 = I3; +R6 = I3; +R7 = I3; +CHECKREG r0, 0x33333333; +CHECKREG r1, 0x33333333; +CHECKREG r2, 0x33333333; +CHECKREG r3, 0x33333333; +CHECKREG r4, 0x44444444; +CHECKREG r5, 0x44444444; +CHECKREG r6, 0x44444444; +CHECKREG r7, 0x44444444; + +R0 = I3; +R1 = I3; +R2 = I3; +R3 = I3; +R4 = I2; +R5 = I2; +R6 = I2; +R7 = I2; +CHECKREG r0, 0x44444444; +CHECKREG r1, 0x44444444; +CHECKREG r2, 0x44444444; +CHECKREG r3, 0x44444444; +CHECKREG r4, 0x33333333; +CHECKREG r5, 0x33333333; +CHECKREG r6, 0x33333333; +CHECKREG r7, 0x33333333; + + +imm32 m0, 0x55555555; +imm32 m1, 0x66666666; +imm32 m2, 0x77777777; +imm32 m3, 0x88888888; +// m to dreg +R0 = M0; +R1 = M0; +R2 = M0; +R3 = M0; +R4 = M1; +R5 = M1; +R6 = M1; +R7 = M1; +CHECKREG r0, 0x55555555; +CHECKREG r1, 0x55555555; +CHECKREG r2, 0x55555555; +CHECKREG r3, 0x55555555; +CHECKREG r4, 0x66666666; +CHECKREG r5, 0x66666666; +CHECKREG r6, 0x66666666; +CHECKREG r7, 0x66666666; + +R0 = M1; +R1 = M1; +R2 = M1; +R3 = M1; +R4 = M0; +R5 = M0; +R6 = M0; +R7 = M0; +CHECKREG r0, 0x66666666; +CHECKREG r1, 0x66666666; +CHECKREG r2, 0x66666666; +CHECKREG r3, 0x66666666; +CHECKREG r4, 0x55555555; +CHECKREG r5, 0x55555555; +CHECKREG r6, 0x55555555; +CHECKREG r7, 0x55555555; + +R0 = M2; +R1 = M2; +R2 = M2; +R3 = M2; +R4 = M3; +R5 = M3; +R6 = M3; +R7 = M3; +CHECKREG r0, 0x77777777; +CHECKREG r1, 0x77777777; +CHECKREG r2, 0x77777777; +CHECKREG r3, 0x77777777; +CHECKREG r4, 0x88888888; +CHECKREG r5, 0x88888888; +CHECKREG r6, 0x88888888; +CHECKREG r7, 0x88888888; + +R0 = M3; +R1 = M3; +R2 = M3; +R3 = M3; +R4 = M2; +R5 = M2; +R6 = M2; +R7 = M2; +CHECKREG r0, 0x88888888; +CHECKREG r1, 0x88888888; +CHECKREG r2, 0x88888888; +CHECKREG r3, 0x88888888; +CHECKREG r4, 0x77777777; +CHECKREG r5, 0x77777777; +CHECKREG r6, 0x77777777; +CHECKREG r7, 0x77777777; + +imm32 l0, 0x99999999; +imm32 l1, 0xaaaaaaaa; +imm32 l2, 0xbbbbbbbb; +imm32 l3, 0xcccccccc; +// l to dreg +R0 = L0; +R1 = L0; +R2 = L0; +R3 = L0; +R4 = L1; +R5 = L1; +R6 = L1; +R7 = L1; +CHECKREG r0, 0x99999999; +CHECKREG r1, 0x99999999; +CHECKREG r2, 0x99999999; +CHECKREG r3, 0x99999999; +CHECKREG r4, 0xaaaaaaaa; +CHECKREG r5, 0xaaaaaaaa; +CHECKREG r6, 0xaaaaaaaa; +CHECKREG r7, 0xaaaaaaaa; + +R0 = L1; +R1 = L1; +R2 = L1; +R3 = L1; +R4 = L0; +R5 = L0; +R6 = L0; +R7 = L0; +CHECKREG r0, 0xaaaaaaaa; +CHECKREG r1, 0xaaaaaaaa; +CHECKREG r2, 0xaaaaaaaa; +CHECKREG r3, 0xaaaaaaaa; +CHECKREG r4, 0x99999999; +CHECKREG r5, 0x99999999; +CHECKREG r6, 0x99999999; +CHECKREG r7, 0x99999999; + + +R0 = L2; +R1 = L2; +R2 = L2; +R3 = L2; +R4 = L3; +R5 = L3; +R6 = L3; +R7 = L3; +CHECKREG r0, 0xbbbbbbbb; +CHECKREG r1, 0xbbbbbbbb; +CHECKREG r2, 0xbbbbbbbb; +CHECKREG r3, 0xbbbbbbbb; +CHECKREG r4, 0xcccccccc; +CHECKREG r5, 0xcccccccc; +CHECKREG r6, 0xcccccccc; +CHECKREG r7, 0xcccccccc; + +R0 = L3; +R1 = L3; +R2 = L3; +R3 = L3; +R4 = L2; +R5 = L2; +R6 = L2; +R7 = L2; +CHECKREG r0, 0xcccccccc; +CHECKREG r1, 0xcccccccc; +CHECKREG r2, 0xcccccccc; +CHECKREG r3, 0xcccccccc; +CHECKREG r4, 0xbbbbbbbb; +CHECKREG r5, 0xbbbbbbbb; +CHECKREG r6, 0xbbbbbbbb; +CHECKREG r7, 0xbbbbbbbb; + + +imm32 b0, 0xdddddddd; +imm32 b1, 0xeeeeeeee; +imm32 b2, 0xffffffff; +imm32 b3, 0x12345678; +// b to dreg +R0 = B0; +R1 = B0; +R2 = B0; +R3 = B0; +R4 = B1; +R5 = B1; +R6 = B1; +R7 = B1; +CHECKREG r0, 0xdddddddd; +CHECKREG r1, 0xdddddddd; +CHECKREG r2, 0xdddddddd; +CHECKREG r3, 0xdddddddd; +CHECKREG r4, 0xeeeeeeee; +CHECKREG r5, 0xeeeeeeee; +CHECKREG r6, 0xeeeeeeee; +CHECKREG r7, 0xeeeeeeee; + +R0 = B1; +R1 = B1; +R2 = B1; +R3 = B1; +R4 = B0; +R5 = B0; +R6 = B0; +R7 = B0; +CHECKREG r0, 0xeeeeeeee; +CHECKREG r1, 0xeeeeeeee; +CHECKREG r2, 0xeeeeeeee; +CHECKREG r3, 0xeeeeeeee; +CHECKREG r4, 0xdddddddd; +CHECKREG r5, 0xdddddddd; +CHECKREG r6, 0xdddddddd; +CHECKREG r7, 0xdddddddd; + +R0 = B2; +R1 = B2; +R2 = B2; +R3 = B2; +R4 = B3; +R5 = B3; +R6 = B3; +R7 = B3; +CHECKREG r0, 0xffffffff; +CHECKREG r1, 0xffffffff; +CHECKREG r2, 0xffffffff; +CHECKREG r3, 0xffffffff; +CHECKREG r4, 0x12345678; +CHECKREG r5, 0x12345678; +CHECKREG r6, 0x12345678; +CHECKREG r7, 0x12345678; + +R0 = B3; +R1 = B3; +R2 = B3; +R3 = B3; +R4 = B2; +R5 = B2; +R6 = B2; +R7 = B2; +CHECKREG r0, 0x12345678; +CHECKREG r1, 0x12345678; +CHECKREG r2, 0x12345678; +CHECKREG r3, 0x12345678; +CHECKREG r4, 0xffffffff; +CHECKREG r5, 0xffffffff; +CHECKREG r6, 0xffffffff; +CHECKREG r7, 0xffffffff; + +pass diff --git a/tests/tcg/bfin/c_regmv_imlb_imlb.s b/tests/tcg/bfin/c_regmv_imlb_imlb.s new file mode 100644 index 0000000000000..35146ec68e13e --- /dev/null +++ b/tests/tcg/bfin/c_regmv_imlb_imlb.s @@ -0,0 +1,925 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_imlb/c_regmv_imlb_imlb.dsp +// Spec Reference: regmv imlb-imlb +# mach: bfin + +.include "testutils.inc" + start + +// initialize source regs + imm32 i0, 0x11111111; + imm32 i1, 0x22222222; + imm32 i2, 0x33333333; + imm32 i3, 0x44444444; + imm32 m0, 0x55555555; + imm32 m1, 0x66666666; + imm32 m2, 0x77777777; + imm32 m3, 0x88888888; + imm32 l0, 0x99999999; + imm32 l1, 0xAAAAAAAA; + imm32 l2, 0xBBBBBBBB; + imm32 l3, 0xCCCCCCCC; + imm32 b0, 0xDDDDDDDD; + imm32 b1, 0xEEEEEEEE; + imm32 b2, 0xFFFFFFFF; + imm32 b3, 0x12345667; + +//*******************i-i & m-m, i-m & m-i, l-l & b-b, l-b & b-l +// i to i & m to m + I0 = I0; + I1 = I1; + I2 = I2; + I3 = I3; + M0 = M0; + M1 = M1; + M2 = M2; + M3 = M3; + + I0 = I1; + I1 = I2; + I2 = I3; + I3 = I0; + M0 = M1; + M1 = M2; + M2 = M3; + M3 = M0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x22222222; + CHECKREG r1, 0x33333333; + CHECKREG r2, 0x44444444; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x66666666; + CHECKREG r5, 0x77777777; + CHECKREG r6, 0x88888888; + CHECKREG r7, 0x66666666; + + I0 = I2; + I1 = I3; + I2 = I0; + I3 = I1; + M0 = M2; + M1 = M3; + M2 = M0; + M3 = M1; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x44444444; + CHECKREG r1, 0x22222222; + CHECKREG r2, 0x44444444; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x88888888; + CHECKREG r5, 0x66666666; + CHECKREG r6, 0x88888888; + CHECKREG r7, 0x66666666; + + I0 = I3; + I1 = I0; + I2 = I1; + I3 = I2; + M0 = M3; + M1 = M0; + M2 = M1; + M3 = M2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x22222222; + CHECKREG r1, 0x22222222; + CHECKREG r2, 0x22222222; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x66666666; + CHECKREG r5, 0x66666666; + CHECKREG r6, 0x66666666; + CHECKREG r7, 0x66666666; + + imm32 i0, 0xa1111110; + imm32 i1, 0xb2222220; + imm32 i2, 0xc3333330; + imm32 i3, 0xd4444440; + imm32 m0, 0xe5555550; + imm32 m1, 0xf6666660; + imm32 m2, 0x17777770; + imm32 m3, 0x28888888; + +// m to i & i to m + I0 = M0; + I1 = M1; + I2 = M2; + I3 = M3; + M0 = I0; + M1 = I1; + M2 = I2; + M3 = I3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xE5555550; + CHECKREG r1, 0xF6666660; + CHECKREG r2, 0x17777770; + CHECKREG r3, 0x28888888; + CHECKREG r4, 0xE5555550; + CHECKREG r5, 0xF6666660; + CHECKREG r6, 0x17777770; + CHECKREG r7, 0x28888888; + + I0 = M1; + I1 = M2; + I2 = M3; + I3 = M0; + M0 = I1; + M1 = I2; + M2 = I3; + M3 = I0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xF6666660; + CHECKREG r1, 0x17777770; + CHECKREG r2, 0x28888888; + CHECKREG r3, 0xE5555550; + CHECKREG r4, 0x17777770; + CHECKREG r5, 0x28888888; + CHECKREG r6, 0xE5555550; + CHECKREG r7, 0xF6666660; + + I0 = M2; + I1 = M3; + I2 = M0; + I3 = M1; + M0 = I2; + M1 = I3; + M2 = I0; + M3 = I1; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xE5555550; + CHECKREG r1, 0xF6666660; + CHECKREG r2, 0x17777770; + CHECKREG r3, 0x28888888; + CHECKREG r4, 0x17777770; + CHECKREG r5, 0x28888888; + CHECKREG r6, 0xE5555550; + CHECKREG r7, 0xF6666660; + + I0 = M3; + I1 = M0; + I2 = M1; + I3 = M2; + M0 = I3; + M1 = I0; + M2 = I1; + M3 = I2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xF6666660; + CHECKREG r1, 0x17777770; + CHECKREG r2, 0x28888888; + CHECKREG r3, 0xE5555550; + CHECKREG r4, 0xE5555550; + CHECKREG r5, 0xF6666660; + CHECKREG r6, 0x17777770; + CHECKREG r7, 0x28888888; + +// l to l & b to b + L0 = L0; + L1 = L1; + L2 = L2; + L3 = L3; + B0 = B0; + B1 = B1; + B2 = B2; + B3 = B3; + + L0 = L1; + L1 = L2; + L2 = L3; + L3 = L0; + B0 = B1; + B1 = B2; + B2 = B3; + B3 = B0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0xAAAAAAAA; + CHECKREG r1, 0xBBBBBBBB; + CHECKREG r2, 0xCCCCCCCC; + CHECKREG r3, 0xAAAAAAAA; + CHECKREG r4, 0xEEEEEEEE; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0x12345667; + CHECKREG r7, 0xEEEEEEEE; + + L0 = L2; + L1 = L3; + L2 = L0; + L3 = L1; + B0 = B2; + B1 = B3; + B2 = B0; + B3 = B1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0xCCCCCCCC; + CHECKREG r1, 0xAAAAAAAA; + CHECKREG r2, 0xCCCCCCCC; + CHECKREG r3, 0xAAAAAAAA; + CHECKREG r4, 0x12345667; + CHECKREG r5, 0xEEEEEEEE; + CHECKREG r6, 0x12345667; + CHECKREG r7, 0xEEEEEEEE; + + imm32 l0, 0x09499091; + imm32 l1, 0x0A55A0A2; + imm32 l2, 0x0B6BB0B3; + imm32 l3, 0x0C7CC0C4; + imm32 b0, 0x0D8DD0D5; + imm32 b1, 0x0E9EE0E6; + imm32 b2, 0x0F0FF0F7; + imm32 b3, 0x12145068; + + L0 = L3; + L1 = L0; + L2 = L1; + L3 = L2; + B0 = B3; + B1 = B0; + B2 = B1; + B3 = B2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x0C7CC0C4; + CHECKREG r1, 0x0C7CC0C4; + CHECKREG r2, 0x0C7CC0C4; + CHECKREG r3, 0x0C7CC0C4; + CHECKREG r4, 0x12145068; + CHECKREG r5, 0x12145068; + CHECKREG r6, 0x12145068; + CHECKREG r7, 0x12145068; + +// b to l & l to b + L0 = B0; + L1 = B1; + L2 = B2; + L3 = B3; + B0 = L0; + B1 = L1; + B2 = L2; + B3 = L3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xF6666660; + CHECKREG r1, 0x17777770; + CHECKREG r2, 0x28888888; + CHECKREG r3, 0xE5555550; + CHECKREG r4, 0xE5555550; + CHECKREG r5, 0xF6666660; + CHECKREG r6, 0x17777770; + CHECKREG r7, 0x28888888; + + imm32 l0, 0x01909910; + imm32 l1, 0x12A11220; + imm32 l2, 0x23B25530; + imm32 l3, 0x34C36640; + imm32 b0, 0x45D47750; + imm32 b1, 0x56E58860; + imm32 b2, 0x67F66676; + imm32 b3, 0x78375680; + + L0 = B1; + L1 = B2; + L2 = B3; + L3 = B0; + B0 = L1; + B1 = L2; + B2 = L3; + B3 = L0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x56E58860; + CHECKREG r1, 0x67F66676; + CHECKREG r2, 0x78375680; + CHECKREG r3, 0x45D47750; + CHECKREG r4, 0x67F66676; + CHECKREG r5, 0x78375680; + CHECKREG r6, 0x45D47750; + CHECKREG r7, 0x56E58860; + + imm32 l0, 0x09909990; + imm32 l1, 0x1AA11230; + imm32 l2, 0x2BB25550; + imm32 l3, 0x3CC36660; + imm32 b0, 0x4DD47770; + imm32 b1, 0x5EE58880; + imm32 b2, 0x6FF66666; + imm32 b3, 0x72375660; + + L0 = B2; + L1 = B3; + L2 = B0; + L3 = B1; + B0 = L2; + B1 = L3; + B2 = L0; + B3 = L1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x6FF66666; + CHECKREG r1, 0x72375660; + CHECKREG r2, 0x4DD47770; + CHECKREG r3, 0x5EE58880; + CHECKREG r4, 0x4DD47770; + CHECKREG r5, 0x5EE58880; + CHECKREG r6, 0x6FF66666; + CHECKREG r7, 0x72375660; + + L0 = B3; + L1 = B0; + L2 = B1; + L3 = B2; + B0 = L3; + B1 = L0; + B2 = L1; + B3 = L2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x72375660; + CHECKREG r1, 0x4DD47770; + CHECKREG r2, 0x5EE58880; + CHECKREG r3, 0x6FF66666; + CHECKREG r4, 0x6FF66666; + CHECKREG r5, 0x72375660; + CHECKREG r6, 0x4DD47770; + CHECKREG r7, 0x5EE58880; + + imm32 l0, 0x09999990; + imm32 l1, 0x1AAAAAA0; + imm32 l2, 0x2BBBBBB0; + imm32 l3, 0x3CCCCCC0; + imm32 b0, 0x4DDDDDD0; + imm32 b1, 0x5EEEEEE0; + imm32 b2, 0x6FFFFFF0; + imm32 b3, 0x72345660; + +//*******************l-i & l-m, b-i & b-m, i-l & i-b, m-l & m-b +// l to i & l to m + I0 = L0; + I1 = L1; + I2 = L2; + I3 = L3; + M0 = L0; + M1 = L1; + M2 = L2; + M3 = L3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x09999990; + CHECKREG r1, 0x1AAAAAA0; + CHECKREG r2, 0x2BBBBBB0; + CHECKREG r3, 0x3CCCCCC0; + CHECKREG r4, 0x09999990; + CHECKREG r5, 0x1AAAAAA0; + CHECKREG r6, 0x2BBBBBB0; + CHECKREG r7, 0x3CCCCCC0; + + I0 = L1; + I1 = L2; + I2 = L3; + I3 = L0; + M0 = L1; + M1 = L2; + M2 = L3; + M3 = L0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x1AAAAAA0; + CHECKREG r1, 0x2BBBBBB0; + CHECKREG r2, 0x3CCCCCC0; + CHECKREG r3, 0x09999990; + CHECKREG r4, 0x1AAAAAA0; + CHECKREG r5, 0x2BBBBBB0; + CHECKREG r6, 0x3CCCCCC0; + CHECKREG r7, 0x09999990; + + I0 = L2; + I1 = L3; + I2 = L0; + I3 = L1; + M0 = L2; + M1 = L3; + M2 = L0; + M3 = L1; + + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x1AAAAAA0; + CHECKREG r1, 0x2BBBBBB0; + CHECKREG r2, 0x3CCCCCC0; + CHECKREG r3, 0x09999990; + CHECKREG r4, 0x2BBBBBB0; + CHECKREG r5, 0x3CCCCCC0; + CHECKREG r6, 0x09999990; + CHECKREG r7, 0x1AAAAAA0; + + I0 = L3; + I1 = L0; + I2 = L1; + I3 = L2; + M0 = L3; + M1 = L0; + M2 = L1; + M3 = L2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x3CCCCCC0; + CHECKREG r1, 0x09999990; + CHECKREG r2, 0x1AAAAAA0; + CHECKREG r3, 0x2BBBBBB0; + CHECKREG r4, 0x3CCCCCC0; + CHECKREG r5, 0x09999990; + CHECKREG r6, 0x1AAAAAA0; + CHECKREG r7, 0x2BBBBBB0; + +// b to i & b to m + I0 = B0; + I1 = B1; + I2 = B2; + I3 = B3; + M0 = B0; + M1 = B1; + M2 = B2; + M3 = B3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x4DDDDDD0; + CHECKREG r1, 0x5EEEEEE0; + CHECKREG r2, 0x6FFFFFF0; + CHECKREG r3, 0x72345660; + CHECKREG r4, 0x4DDDDDD0; + CHECKREG r5, 0x5EEEEEE0; + CHECKREG r6, 0x6FFFFFF0; + CHECKREG r7, 0x72345660; + + I0 = B1; + I1 = B2; + I2 = B3; + I3 = B0; + M0 = B1; + M1 = B2; + M2 = B3; + M3 = B0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x5EEEEEE0; + CHECKREG r1, 0x6FFFFFF0; + CHECKREG r2, 0x72345660; + CHECKREG r3, 0x4DDDDDD0; + CHECKREG r4, 0x5EEEEEE0; + CHECKREG r5, 0x6FFFFFF0; + CHECKREG r6, 0x72345660; + CHECKREG r7, 0x4DDDDDD0; + + I0 = B2; + I1 = B3; + I2 = B0; + I3 = B1; + M0 = B2; + M1 = B3; + M2 = B0; + M3 = B1; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x6FFFFFF0; + CHECKREG r1, 0x72345660; + CHECKREG r2, 0x4DDDDDD0; + CHECKREG r3, 0x5EEEEEE0; + CHECKREG r4, 0x6FFFFFF0; + CHECKREG r5, 0x72345660; + CHECKREG r6, 0x4DDDDDD0; + CHECKREG r7, 0x5EEEEEE0; + + I0 = B3; + I1 = B0; + I2 = B1; + I3 = B2; + M0 = B3; + M1 = B0; + M2 = B1; + M3 = B2; + + P1 = I1; + P2 = I2; + P3 = I3; + P4 = M0; + P5 = M1; + FP = M2; + SP = M3; + + CHECKREG p1, 0x4DDDDDD0; + CHECKREG p2, 0x5EEEEEE0; + CHECKREG p3, 0x6FFFFFF0; + CHECKREG p4, 0x72345660; + CHECKREG p5, 0x4DDDDDD0; + CHECKREG fp, 0x5EEEEEE0; + CHECKREG sp, 0x6FFFFFF0; + +// i to l & i to b + imm32 i0, 0x09999990; + imm32 i1, 0x1AAAAAA0; + imm32 i2, 0x2BBBBBB0; + imm32 i3, 0x3CCCCCC0; + + L0 = I0; + L1 = I1; + L2 = I2; + L3 = I3; + B0 = I0; + B1 = I1; + B2 = I2; + B3 = I3; + + L0 = I1; + L1 = I2; + L2 = I3; + L3 = I0; + B0 = I1; + B1 = I2; + B2 = I3; + B3 = I0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x1AAAAAA0; + CHECKREG r1, 0x2BBBBBB0; + CHECKREG r2, 0x3CCCCCC0; + CHECKREG r3, 0x09999990; + CHECKREG r4, 0x1AAAAAA0; + CHECKREG r5, 0x2BBBBBB0; + CHECKREG r6, 0x3CCCCCC0; + CHECKREG r7, 0x09999990; + + L0 = I2; + L1 = I3; + L2 = I0; + L3 = I1; + B0 = I2; + B1 = I3; + B2 = I0; + B3 = I1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x2BBBBBB0; + CHECKREG r1, 0x3CCCCCC0; + CHECKREG r2, 0x09999990; + CHECKREG r3, 0x1AAAAAA0; + CHECKREG r4, 0x2BBBBBB0; + CHECKREG r5, 0x3CCCCCC0; + CHECKREG r6, 0x09999990; + CHECKREG r7, 0x1AAAAAA0; + + imm32 l0, 0x09499091; + imm32 l1, 0x0A55A0A2; + imm32 l2, 0x0B6BB0B3; + imm32 l3, 0x0C7CC0C4; + imm32 b0, 0x0D8DD0D5; + imm32 b1, 0x0E9EE0E6; + imm32 b2, 0x0F0FF0F7; + imm32 b3, 0x12145068; + + L0 = I3; + L1 = I0; + L2 = I1; + L3 = I2; + B0 = I3; + B1 = I0; + B2 = I1; + B3 = I2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x3CCCCCC0; + CHECKREG r1, 0x09999990; + CHECKREG r2, 0x1AAAAAA0; + CHECKREG r3, 0x2BBBBBB0; + CHECKREG r4, 0x3CCCCCC0; + CHECKREG r5, 0x09999990; + CHECKREG r6, 0x1AAAAAA0; + CHECKREG r7, 0x2BBBBBB0; + +// m to l & m to b + imm32 m0, 0x4DDDDDD0; + imm32 m1, 0x5EEEEEE0; + imm32 m2, 0x6FFFFFF0; + imm32 m3, 0x72345660; + L0 = M0; + L1 = M1; + L2 = M2; + L3 = M3; + B0 = M0; + B1 = M1; + B2 = M2; + B3 = M3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x09999990; + CHECKREG r1, 0x1AAAAAA0; + CHECKREG r2, 0x2BBBBBB0; + CHECKREG r3, 0x3CCCCCC0; + CHECKREG r4, 0x4DDDDDD0; + CHECKREG r5, 0x5EEEEEE0; + CHECKREG r6, 0x6FFFFFF0; + CHECKREG r7, 0x72345660; + + imm32 l0, 0x01909910; + imm32 l1, 0x12A11220; + imm32 l2, 0x23B25530; + imm32 l3, 0x34C36640; + imm32 b0, 0x45D47750; + imm32 b1, 0x56E58860; + imm32 b2, 0x67F66676; + imm32 b3, 0x78375680; + + L0 = M1; + L1 = M2; + L2 = M3; + L3 = M0; + B0 = M1; + B1 = M2; + B2 = M3; + B3 = M0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x5EEEEEE0; + CHECKREG r1, 0x6FFFFFF0; + CHECKREG r2, 0x72345660; + CHECKREG r3, 0x4DDDDDD0; + CHECKREG r4, 0x5EEEEEE0; + CHECKREG r5, 0x6FFFFFF0; + CHECKREG r6, 0x72345660; + CHECKREG r7, 0x4DDDDDD0; + + imm32 l0, 0x09909990; + imm32 l1, 0x1AA11230; + imm32 l2, 0x2BB25550; + imm32 l3, 0x3CC36660; + imm32 b0, 0x4DD47770; + imm32 b1, 0x5EE58880; + imm32 b2, 0x6FF66666; + imm32 b3, 0x72375660; + + L0 = M2; + L1 = M3; + L2 = M0; + L3 = M1; + B0 = M2; + B1 = M3; + B2 = M0; + B3 = M1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x6FFFFFF0; + CHECKREG r1, 0x72345660; + CHECKREG r2, 0x4DDDDDD0; + CHECKREG r3, 0x5EEEEEE0; + CHECKREG r4, 0x6FFFFFF0; + CHECKREG r5, 0x72345660; + CHECKREG r6, 0x4DDDDDD0; + CHECKREG r7, 0x5EEEEEE0; + + L0 = M3; + L1 = M0; + L2 = M1; + L3 = M2; + B0 = M3; + B1 = M0; + B2 = M1; + B3 = M2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x72345660; + CHECKREG r1, 0x4DDDDDD0; + CHECKREG r2, 0x5EEEEEE0; + CHECKREG r3, 0x6FFFFFF0; + CHECKREG r4, 0x72345660; + CHECKREG r5, 0x4DDDDDD0; + CHECKREG r6, 0x5EEEEEE0; + CHECKREG r7, 0x6FFFFFF0; + + pass diff --git a/tests/tcg/bfin/c_regmv_imlb_pr.s b/tests/tcg/bfin/c_regmv_imlb_pr.s new file mode 100644 index 0000000000000..7e32a29f93125 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_imlb_pr.s @@ -0,0 +1,302 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_pr/c_regmv_imlb_pr.dsp +// Spec Reference: regmv imlb to dr +# mach: bfin + +.include "testutils.inc" + start + +// initialize source regs + imm32 i0, 0x11111111; + imm32 i1, 0x22222222; + imm32 i2, 0x33333333; + imm32 i3, 0x44444444; + +// i to preg + R0 = I0; + P1 = I0; + P2 = I0; + P3 = I0; + P4 = I1; + P5 = I1; + SP = I1; + FP = I1; + CHECKREG r0, 0x11111111; + CHECKREG p1, 0x11111111; + CHECKREG p2, 0x11111111; + CHECKREG p3, 0x11111111; + CHECKREG p4, 0x22222222; + CHECKREG p5, 0x22222222; + CHECKREG sp, 0x22222222; + CHECKREG fp, 0x22222222; + + R0 = I1; + P1 = I1; + P2 = I1; + P3 = I1; + P4 = I0; + P5 = I0; + SP = I0; + FP = I0; + CHECKREG r0, 0x22222222; + CHECKREG p1, 0x22222222; + CHECKREG p2, 0x22222222; + CHECKREG p3, 0x22222222; + CHECKREG p4, 0x11111111; + CHECKREG p5, 0x11111111; + CHECKREG sp, 0x11111111; + CHECKREG fp, 0x11111111; + + R0 = I2; + P1 = I2; + P2 = I2; + P3 = I2; + P4 = I3; + P5 = I3; + SP = I3; + FP = I3; + CHECKREG r0, 0x33333333; + CHECKREG p1, 0x33333333; + CHECKREG p2, 0x33333333; + CHECKREG p3, 0x33333333; + CHECKREG p4, 0x44444444; + CHECKREG p5, 0x44444444; + CHECKREG sp, 0x44444444; + CHECKREG fp, 0x44444444; + + R0 = I3; + P1 = I3; + P2 = I3; + P3 = I3; + P4 = I2; + P5 = I2; + SP = I2; + FP = I2; + CHECKREG r0, 0x44444444; + CHECKREG p1, 0x44444444; + CHECKREG p2, 0x44444444; + CHECKREG p3, 0x44444444; + CHECKREG p4, 0x33333333; + CHECKREG p5, 0x33333333; + CHECKREG sp, 0x33333333; + CHECKREG fp, 0x33333333; + + imm32 m0, 0x55555555; + imm32 m1, 0x66666666; + imm32 m2, 0x77777777; + imm32 m3, 0x88888888; +// m to preg + R0 = M0; + P1 = M0; + P2 = M0; + P3 = M0; + P4 = M1; + P5 = M1; + SP = M1; + FP = M1; + CHECKREG r0, 0x55555555; + CHECKREG p1, 0x55555555; + CHECKREG p2, 0x55555555; + CHECKREG p3, 0x55555555; + CHECKREG p4, 0x66666666; + CHECKREG p5, 0x66666666; + CHECKREG sp, 0x66666666; + CHECKREG fp, 0x66666666; + + R0 = M1; + P1 = M1; + P2 = M1; + P3 = M1; + P4 = M0; + P5 = M0; + SP = M0; + FP = M0; + CHECKREG r0, 0x66666666; + CHECKREG p1, 0x66666666; + CHECKREG p2, 0x66666666; + CHECKREG p3, 0x66666666; + CHECKREG p4, 0x55555555; + CHECKREG p5, 0x55555555; + CHECKREG sp, 0x55555555; + CHECKREG fp, 0x55555555; + + R0 = M2; + P1 = M2; + P2 = M2; + P3 = M2; + P4 = M3; + P5 = M3; + SP = M3; + FP = M3; + CHECKREG r0, 0x77777777; + CHECKREG p1, 0x77777777; + CHECKREG p2, 0x77777777; + CHECKREG p3, 0x77777777; + CHECKREG p4, 0x88888888; + CHECKREG p5, 0x88888888; + CHECKREG sp, 0x88888888; + CHECKREG fp, 0x88888888; + + R0 = M3; + P1 = M3; + P2 = M3; + P3 = M3; + P4 = M2; + P5 = M2; + SP = M2; + FP = M2; + CHECKREG r0, 0x88888888; + CHECKREG p1, 0x88888888; + CHECKREG p2, 0x88888888; + CHECKREG p3, 0x88888888; + CHECKREG p4, 0x77777777; + CHECKREG p5, 0x77777777; + CHECKREG sp, 0x77777777; + CHECKREG fp, 0x77777777; + + imm32 l0, 0x99999999; + imm32 l1, 0xaaaaaaaa; + imm32 l2, 0xbbbbbbbb; + imm32 l3, 0xcccccccc; +// l to preg + R0 = L0; + P1 = L0; + P2 = L0; + P3 = L0; + P4 = L1; + P5 = L1; + SP = L1; + FP = L1; + CHECKREG r0, 0x99999999; + CHECKREG p1, 0x99999999; + CHECKREG p2, 0x99999999; + CHECKREG p3, 0x99999999; + CHECKREG p4, 0xaaaaaaaa; + CHECKREG p5, 0xaaaaaaaa; + CHECKREG sp, 0xaaaaaaaa; + CHECKREG fp, 0xaaaaaaaa; + + R0 = L1; + P1 = L1; + P2 = L1; + P3 = L1; + P4 = L0; + P5 = L0; + SP = L0; + FP = L0; + CHECKREG r0, 0xaaaaaaaa; + CHECKREG p1, 0xaaaaaaaa; + CHECKREG p2, 0xaaaaaaaa; + CHECKREG p3, 0xaaaaaaaa; + CHECKREG p4, 0x99999999; + CHECKREG p5, 0x99999999; + CHECKREG sp, 0x99999999; + CHECKREG fp, 0x99999999; + + R0 = L2; + P1 = L2; + P2 = L2; + P3 = L2; + P4 = L3; + P5 = L3; + SP = L3; + FP = L3; + CHECKREG r0, 0xbbbbbbbb; + CHECKREG p1, 0xbbbbbbbb; + CHECKREG p2, 0xbbbbbbbb; + CHECKREG p3, 0xbbbbbbbb; + CHECKREG p4, 0xcccccccc; + CHECKREG p5, 0xcccccccc; + CHECKREG sp, 0xcccccccc; + CHECKREG fp, 0xcccccccc; + + R0 = L3; + P1 = L3; + P2 = L3; + P3 = L3; + P4 = L2; + P5 = L2; + SP = L2; + FP = L2; + CHECKREG r0, 0xcccccccc; + CHECKREG p1, 0xcccccccc; + CHECKREG p2, 0xcccccccc; + CHECKREG p3, 0xcccccccc; + CHECKREG p4, 0xbbbbbbbb; + CHECKREG p5, 0xbbbbbbbb; + CHECKREG sp, 0xbbbbbbbb; + CHECKREG fp, 0xbbbbbbbb; + + imm32 b0, 0xdddddddd; + imm32 b1, 0xeeeeeeee; + imm32 b2, 0xffffffff; + imm32 b3, 0x12345678; +// b to preg + R0 = B0; + P1 = B0; + P2 = B0; + P3 = B0; + P4 = B1; + P5 = B1; + SP = B1; + FP = B1; + CHECKREG r0, 0xdddddddd; + CHECKREG p1, 0xdddddddd; + CHECKREG p2, 0xdddddddd; + CHECKREG p3, 0xdddddddd; + CHECKREG p4, 0xeeeeeeee; + CHECKREG p5, 0xeeeeeeee; + CHECKREG sp, 0xeeeeeeee; + CHECKREG fp, 0xeeeeeeee; + + R0 = B1; + P1 = B1; + P2 = B1; + P3 = B1; + P4 = B0; + P5 = B0; + SP = B0; + FP = B0; + CHECKREG r0, 0xeeeeeeee; + CHECKREG p1, 0xeeeeeeee; + CHECKREG p2, 0xeeeeeeee; + CHECKREG p3, 0xeeeeeeee; + CHECKREG p4, 0xdddddddd; + CHECKREG p5, 0xdddddddd; + CHECKREG sp, 0xdddddddd; + CHECKREG fp, 0xdddddddd; + + R0 = B2; + P1 = B2; + P2 = B2; + P3 = B2; + P4 = B3; + P5 = B3; + SP = B3; + FP = B3; + CHECKREG r0, 0xffffffff; + CHECKREG p1, 0xffffffff; + CHECKREG p2, 0xffffffff; + CHECKREG p3, 0xffffffff; + CHECKREG p4, 0x12345678; + CHECKREG p5, 0x12345678; + CHECKREG sp, 0x12345678; + CHECKREG fp, 0x12345678; + + R0 = B3; + P1 = B3; + P2 = B3; + P3 = B3; + P4 = B2; + P5 = B2; + SP = B2; + FP = B2; + CHECKREG r0, 0x12345678; + CHECKREG p1, 0x12345678; + CHECKREG p2, 0x12345678; + CHECKREG p3, 0x12345678; + CHECKREG p4, 0xffffffff; + CHECKREG p5, 0xffffffff; + CHECKREG sp, 0xffffffff; + CHECKREG fp, 0xffffffff; + + pass diff --git a/tests/tcg/bfin/c_regmv_pr_dep_nostall.s b/tests/tcg/bfin/c_regmv_pr_dep_nostall.s new file mode 100644 index 0000000000000..5525beafa2278 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_pr_dep_nostall.s @@ -0,0 +1,280 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_nostall/c_regmv_pr_dep_nostall.dsp +// Spec Reference: regmv pr-dep no stall +# mach: bfin + +.include "testutils.inc" + start + +//imm32 p0, 0x00001111; + imm32 p1, 0x32213330; + imm32 p2, 0x34415550; + imm32 p3, 0x36617770; + imm32 p4, 0x38819990; + imm32 p5, 0x3aa1bbb0; + imm32 fp, 0x3cc1ddd0; + imm32 sp, 0x3ee1fff0; +// P-reg to P-reg to R-reg: no stall + P4 = P1; + R1 = P4; + SP = P5; + R2 = SP; + P1 = FP; + R3 = P1; + CHECKREG r1, 0x32213330; + CHECKREG r2, 0x3AA1BBB0; + CHECKREG r3, 0x3CC1DDD0; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44415552; + imm32 p3, 0x66617772; + imm32 p4, 0x88819992; + imm32 p5, 0xaaa1bbb2; + imm32 fp, 0xccc1ddd2; + imm32 sp, 0xeee1fff2; + +// P-reg to P-reg to I reg: no stall + P1 = P2; + I0 = P1; + P3 = P2; + I1 = P3; + P5 = P4; + I2 = P5; + FP = SP; + I3 = FP; + + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r4, 0xEEE1FFF2; + CHECKREG r5, 0x88819992; + CHECKREG r6, 0x44415552; + CHECKREG r7, 0x44415552; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44415552; + imm32 p3, 0x66617772; + imm32 p4, 0x88819992; + imm32 p5, 0xaaa1bbb2; + imm32 fp, 0xccc1ddd2; + imm32 sp, 0xe111fff2; + +// P-reg to P-reg to M reg: no stall + P1 = P4; + M0 = P1; + P3 = P2; + M1 = P3; + P5 = P4; + M2 = P5; + FP = SP; + M3 = FP; + + R4 = M3; + R5 = M2; + R6 = M1; + R7 = M0; + CHECKREG r4, 0xE111FFF2; + CHECKREG r5, 0x88819992; + CHECKREG r6, 0x44415552; + CHECKREG r7, 0x88819992; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44215552; + imm32 p3, 0x66217772; + imm32 p4, 0x88219992; + imm32 p5, 0xaa21bbb2; + imm32 fp, 0xcc21ddd2; + imm32 sp, 0xee21fff2; + +// P-reg to P-reg to L reg: no stall + P1 = P0; + L0 = P1; + P3 = P2; + L1 = P3; + P5 = P4; + L2 = P5; + FP = SP; + L3 = FP; + + R4 = L3; + R5 = L2; + R6 = L1; + R7 = L0; + CHECKREG r4, 0xEE21FFF2; + CHECKREG r5, 0x88219992; + CHECKREG r6, 0x44215552; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44415532; + imm32 p3, 0x66617732; + imm32 p4, 0x88819932; + imm32 p5, 0xaaa1bb32; + imm32 fp, 0xccc1dd32; + imm32 sp, 0xeee1ff32; + +// P-reg to P-reg to B reg: no stall + P1 = FP; + B0 = P1; + P3 = P2; + B1 = P3; + P5 = P4; + B2 = P5; + FP = SP; + B3 = FP; + + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r4, 0xEEE1FF32; + CHECKREG r5, 0x88819932; + CHECKREG r6, 0x44415532; + CHECKREG r7, 0xccc1dd32; + + imm32 i0, 0x03001131; + imm32 i1, 0x23223333; + imm32 i2, 0x43445535; + imm32 i3, 0x63667737; + imm32 m0, 0x83889939; + imm32 m1, 0xa3aabb3b; + imm32 m2, 0xc3ccdd3d; + imm32 m3, 0xe3eeff3f; + +// I,M-reg to P-reg to R-reg: no stall + P1 = I0; + R0 = P1; + P2 = I1; + R1 = P2; + P3 = I2; + R2 = P3; + P4 = I3; + R3 = P4; + P5 = M0; + R4 = P5; + SP = M1; + R5 = SP; + FP = M2; + R6 = FP; + FP = M3; + R7 = FP; + + CHECKREG r0, 0x03001131; + CHECKREG r1, 0x23223333; + CHECKREG r2, 0x43445535; + CHECKREG r3, 0x63667737; + CHECKREG r4, 0x83889939; + CHECKREG r5, 0xA3AABB3B; + CHECKREG r6, 0xC3CCDD3D; + CHECKREG r7, 0xE3EEFF3F; + + imm32 i0, 0x12001111; + imm32 i1, 0x12221333; + imm32 i2, 0x12441555; + imm32 i3, 0x12661777; + imm32 m0, 0x12881999; + imm32 m1, 0x12aa1bbb; + imm32 m2, 0x12cc1ddd; + imm32 m3, 0x12ee1fff; + +// I,M-reg to P-reg to L,B reg: no stall + P1 = I0; + L0 = P1; + P1 = I1; + L1 = P1; + P2 = I2; + L2 = P2; + P3 = I3; + L3 = P3; + P4 = M0; + B0 = P4; + P5 = M1; + B1 = P5; + SP = M2; + B2 = SP; + FP = M3; + B3 = FP; + +//CHECKREG r0, 0x12001111; + CHECKREG p1, 0x12221333; + CHECKREG p2, 0x12441555; + CHECKREG p3, 0x12661777; + CHECKREG p4, 0x12881999; + CHECKREG p5, 0x12AA1BBB; + CHECKREG sp, 0x12CC1DDD; + CHECKREG fp, 0x12EE1FFF; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x12661777; + CHECKREG r1, 0x12441555; + CHECKREG r2, 0x12221333; + CHECKREG r3, 0x12001111; + CHECKREG r4, 0x12EE1FFF; + CHECKREG r5, 0x12CC1DDD; + CHECKREG r6, 0x12AA1BBB; + CHECKREG r7, 0x12881999; + + imm32 l0, 0x23003111; + imm32 l1, 0x23223333; + imm32 l2, 0x23443555; + imm32 l3, 0x23663777; + imm32 b0, 0x23883999; + imm32 b0, 0x23aa3bbb; + imm32 b0, 0x23cc3ddd; + imm32 b0, 0x23ee3fff; + +// L,B-reg to P-reg to I,M reg: no stall + P1 = L0; + I0 = P1; + P1 = L1; + I1 = P1; + P2 = L2; + I2 = P2; + P3 = L3; + I3 = P3; + P4 = B0; + M0 = P4; + P5 = B1; + M1 = P5; + SP = B2; + M2 = SP; + FP = B3; + M3 = FP; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; +//CHECKREG r0, 0x1EEE1FFF; + CHECKREG p1, 0x23223333; + CHECKREG p2, 0x23443555; + CHECKREG p3, 0x23663777; + CHECKREG p4, 0x23EE3FFF; + CHECKREG p5, 0x12AA1BBB; + CHECKREG sp, 0x12CC1DDD; + CHECKREG fp, 0x12EE1FFF; + + CHECKREG r0, 0x12EE1FFF; + CHECKREG r1, 0x12CC1DDD; + CHECKREG r2, 0x12AA1BBB; + CHECKREG r3, 0x23EE3FFF; + CHECKREG r4, 0x23663777; + CHECKREG r5, 0x23443555; + CHECKREG r6, 0x23223333; + CHECKREG r7, 0x23003111; + + pass diff --git a/tests/tcg/bfin/c_regmv_pr_dep_stall.s b/tests/tcg/bfin/c_regmv_pr_dep_stall.s new file mode 100644 index 0000000000000..91dd0f85e19eb --- /dev/null +++ b/tests/tcg/bfin/c_regmv_pr_dep_stall.s @@ -0,0 +1,237 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_stall/c_regmv_pr_dep_stall.dsp +// Spec Reference: regmv pr-dependency stall +# mach: bfin + +.include "testutils.inc" + start + + INIT_M_REGS 0; + +// R-reg to P-reg to R reg: stall + imm32 r0, 0x00001110; + imm32 r1, 0x00213330; + imm32 r2, 0x04015550; + imm32 r3, 0x06607770; + imm32 r4, 0x08810990; + imm32 r5, 0x01a1b0b0; + imm32 r6, 0x01c1dd00; + imm32 r7, 0x01e1fff0; + P1 = R1; + R0 = P1; + P2 = R2; + R1 = P2; + P3 = R3; + R2 = P3; + P4 = R4; + R3 = P4; + P5 = R5; + R4 = P5; + SP = R6; + R5 = P2; + FP = R7; + R6 = P3; + + CHECKREG r0, 0x00213330; + CHECKREG r1, 0x04015550; + CHECKREG r2, 0x06607770; + CHECKREG r3, 0x08810990; + CHECKREG r4, 0x01A1B0B0; + CHECKREG r5, 0x04015550; + CHECKREG r6, 0x06607770; + CHECKREG r7, 0x01E1FFF0; + +// R-reg to P-reg to I,M reg: stall + imm32 r0, 0x10001111; + imm32 r1, 0x11213331; + imm32 r2, 0x14115551; + imm32 r3, 0x16617771; + imm32 r4, 0x18811991; + imm32 r5, 0x11a1b1b1; + imm32 r6, 0x11c1dd11; + imm32 r7, 0x11e1fff1; + P1 = R0; + I0 = P1; + P2 = R1; + I1 = P2; + P3 = R2; + I2 = P3; + P4 = R3; + I3 = P4; + P5 = R4; + M0 = P5; + SP = R5; + M1 = SP; + FP = R6; + M2 = FP; + + R0 = I3; + R1 = I2; + R2 = I1; + R3 = I0; + R4 = M3; + R5 = M2; + R6 = M1; + R7 = M0; + CHECKREG r0, 0x16617771; + CHECKREG r1, 0x14115551; + CHECKREG r2, 0x11213331; + CHECKREG r3, 0x10001111; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x11C1DD11; + CHECKREG r6, 0x11A1B1B1; + CHECKREG r7, 0x18811991; + + CHECKREG p1, 0x10001111; + CHECKREG p2, 0x11213331; + CHECKREG p3, 0x14115551; + CHECKREG p4, 0x16617771; + CHECKREG p5, 0x18811991; + CHECKREG sp, 0x11A1B1B1; + CHECKREG fp, 0x11C1DD11; + + imm32 r0, 0x20001112; + imm32 r1, 0x21213332; + imm32 r2, 0x24115552; + imm32 r3, 0x26617772; + imm32 r4, 0x28811992; + imm32 r5, 0x21a1b1b2; + imm32 r6, 0x21c1dd12; + imm32 r7, 0x21e1fff2; + P1 = R3; + I3 = P1; + P2 = R4; + I0 = P2; + P3 = R5; + I1 = P3; + P4 = R6; + I2 = P4; + P5 = R7; + M1 = P5; + SP = R0; + M2 = SP; + FP = R1; + M3 = FP; + + R0 = I3; + R1 = I2; + R2 = I1; + R3 = I0; + R4 = M3; + R5 = M2; + R6 = M1; + R7 = M0; + CHECKREG r0, 0x26617772; + CHECKREG r1, 0x21C1DD12; + CHECKREG r2, 0x21A1B1B2; + CHECKREG r3, 0x28811992; + CHECKREG r4, 0x21213332; + CHECKREG r5, 0x20001112; + CHECKREG r6, 0x21E1FFF2; + CHECKREG r7, 0x18811991; + + CHECKREG p1, 0x26617772; + CHECKREG p2, 0x28811992; + CHECKREG p3, 0x21A1B1B2; + CHECKREG p4, 0x21C1DD12; + CHECKREG p5, 0x21E1FFF2; + CHECKREG sp, 0x20001112; + CHECKREG fp, 0x21213332; + +// R-reg to P-reg to L,B reg: stall + imm32 r0, 0x30001113; + imm32 r1, 0x31213333; + imm32 r2, 0x34115553; + imm32 r3, 0x36617773; + imm32 r4, 0x38811993; + imm32 r5, 0x31a1b1b3; + imm32 r6, 0x31c1dd13; + imm32 r7, 0x31e1fff3; + P1 = R4; + L0 = P1; + P2 = R5; + L1 = P2; + P3 = R6; + L2 = P3; + P4 = R7; + L3 = P4; + P5 = R0; + B0 = P5; + SP = R1; + B1 = SP; + FP = R2; + B2 = FP; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x31E1FFF3; + CHECKREG r1, 0x31C1DD13; + CHECKREG r2, 0x31A1B1B3; + CHECKREG r3, 0x38811993; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x34115553; + CHECKREG r6, 0x31213333; + CHECKREG r7, 0x30001113; + + CHECKREG p1, 0x38811993; + CHECKREG p2, 0x31A1B1B3; + CHECKREG p3, 0x31C1DD13; + CHECKREG p4, 0x31E1FFF3; + CHECKREG p5, 0x30001113; + CHECKREG sp, 0x31213333; + CHECKREG fp, 0x34115553; + + imm32 r0, 0x40001114; + imm32 r1, 0x44213334; + imm32 r2, 0x44415554; + imm32 r3, 0x46647774; + imm32 r4, 0x48814994; + imm32 r5, 0x41a1b4b4; + imm32 r6, 0x41c1dd44; + imm32 r7, 0x41e1fff4; + P1 = R5; + L2 = P1; + P2 = R6; + L3 = P2; + P3 = R7; + L0 = P3; + P4 = R0; + L1 = P4; + P5 = R1; + B2 = P5; + SP = R2; + B3 = SP; + FP = R3; + B0 = FP; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x41C1DD44; + CHECKREG r1, 0x41A1B4B4; + CHECKREG r2, 0x40001114; + CHECKREG r3, 0x41E1FFF4; + CHECKREG r4, 0x44415554; + CHECKREG r5, 0x44213334; + CHECKREG r6, 0x31213333; + CHECKREG r7, 0x46647774; + + CHECKREG p1, 0x41A1B4B4; + CHECKREG p2, 0x41C1DD44; + CHECKREG p3, 0x41E1FFF4; + CHECKREG p4, 0x40001114; + CHECKREG p5, 0x44213334; + CHECKREG sp, 0x44415554; + CHECKREG fp, 0x46647774; + + pass diff --git a/tests/tcg/bfin/c_regmv_pr_dr.s b/tests/tcg/bfin/c_regmv_pr_dr.s new file mode 100644 index 0000000000000..fe1826f1ae598 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_pr_dr.s @@ -0,0 +1,147 @@ +//Original:/testcases/core/c_regmv_pr_dr/c_regmv_pr_dr.dsp +// Spec Reference: regmv preg to dreg +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; + +//imm32 p0, 0x00000001; +imm32 p1, 0x10082001; +imm32 p2, 0x10092002; +imm32 p3, 0x100a2003; +imm32 p4, 0x100b2004; +imm32 p5, 0x100c2005; +imm32 sp, 0x100d2006; +imm32 fp, 0x100e2007; + +//--------- Preg to dreg : Rx <= Px ------ + + +R0 = P1; +R1 = P1; +R2 = P1; +R3 = P1; +R4 = P1; +R5 = P1; +R6 = P1; +R7 = P1; +CHECKREG r1, 0x10082001; +CHECKREG r2, 0x10082001; +CHECKREG r3, 0x10082001; +CHECKREG r4, 0x10082001; +CHECKREG r5, 0x10082001; +CHECKREG r6, 0x10082001; +CHECKREG r7, 0x10082001; + +R0 = P2; +R1 = P2; +R2 = P2; +R3 = P2; +R4 = P2; +R5 = P2; +R6 = P2; +R7 = P2; +CHECKREG r0, 0x10092002; +CHECKREG r1, 0x10092002; +CHECKREG r2, 0x10092002; +CHECKREG r3, 0x10092002; +CHECKREG r4, 0x10092002; +CHECKREG r5, 0x10092002; +CHECKREG r6, 0x10092002; +CHECKREG r7, 0x10092002; + +R0 = P3; +R1 = P3; +R2 = P3; +R3 = P3; +R4 = P3; +R5 = P3; +R6 = P3; +R7 = P3; +CHECKREG r1, 0x100a2003; +CHECKREG r2, 0x100a2003; +CHECKREG r3, 0x100a2003; +CHECKREG r4, 0x100a2003; +CHECKREG r5, 0x100a2003; +CHECKREG r6, 0x100a2003; +CHECKREG r7, 0x100a2003; + +R0 = P4; +R1 = P4; +R2 = P4; +R3 = P4; +R4 = P4; +R5 = P4; +R6 = P4; +R7 = P4; +CHECKREG r0, 0x100b2004; +CHECKREG r1, 0x100b2004; +CHECKREG r2, 0x100b2004; +CHECKREG r3, 0x100b2004; +CHECKREG r4, 0x100b2004; +CHECKREG r5, 0x100b2004; +CHECKREG r6, 0x100b2004; +CHECKREG r7, 0x100b2004; + +R1 = P5; +R2 = P5; +R3 = P5; +R4 = P5; +R5 = P5; +R6 = P5; +R7 = P5; +CHECKREG r1, 0x100c2005; +CHECKREG r2, 0x100c2005; +CHECKREG r3, 0x100c2005; +CHECKREG r4, 0x100c2005; +CHECKREG r5, 0x100c2005; +CHECKREG r6, 0x100c2005; +CHECKREG r7, 0x100c2005; + +R0 = SP; +R1 = SP; +R2 = SP; +R3 = SP; +R4 = SP; +R5 = SP; +R6 = SP; +R7 = SP; +CHECKREG r0, 0x100d2006; +CHECKREG r1, 0x100d2006; +CHECKREG r2, 0x100d2006; +CHECKREG r3, 0x100d2006; +CHECKREG r4, 0x100d2006; +CHECKREG r5, 0x100d2006; +CHECKREG r6, 0x100d2006; +CHECKREG r7, 0x100d2006; + +R0 = FP; +R1 = FP; +R2 = FP; +R3 = FP; +R4 = FP; +R5 = FP; +R6 = FP; +R7 = FP; +CHECKREG r1, 0x100e2007; +CHECKREG r2, 0x100e2007; +CHECKREG r3, 0x100e2007; +CHECKREG r4, 0x100e2007; +CHECKREG r5, 0x100e2007; +CHECKREG r6, 0x100e2007; +CHECKREG r7, 0x100e2007; + +pass diff --git a/tests/tcg/bfin/c_regmv_pr_imlb.s b/tests/tcg/bfin/c_regmv_pr_imlb.s new file mode 100644 index 0000000000000..31ff3e923d341 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_pr_imlb.s @@ -0,0 +1,382 @@ +//Original:/testcases/core/c_regmv_pr_imlb/c_regmv_pr_imlb.dsp +// Spec Reference: regmv preg-to-imlb reg +# mach: bfin + +.include "testutils.inc" + start + +// check R-reg to imlb-reg move + +imm32 r0, 0x00000001; +imm32 p1, 0x00020003; +imm32 p2, 0x00040005; +imm32 p3, 0x00060007; +imm32 p4, 0x00080009; +imm32 p5, 0x000a000b; +imm32 sp, 0x000c000d; +imm32 fp, 0x000e000f; +I0 = P1; +I1 = P1; +I2 = P1; +I3 = P1; +M0 = P1; +M1 = P1; +M2 = P1; +M3 = P1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 p2, 0x00040005; +I0 = P2; +I1 = P2; +I2 = P2; +I3 = P2; +M0 = P2; +M1 = P2; +M2 = P2; +M3 = P2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 p3, 0x00060007; +I0 = P3; +I1 = P3; +I2 = P3; +I3 = P3; +M0 = P3; +M1 = P3; +M2 = P3; +M3 = P3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 p4, 0x00080009; +I0 = P4; +I1 = P4; +I2 = P4; +I3 = P4; +M0 = P4; +M1 = P4; +M2 = P4; +M3 = P4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 p5, 0x000a000b; +I0 = P5; +I1 = P5; +I2 = P5; +I3 = P5; +M0 = P5; +M1 = P5; +M2 = P5; +M3 = P5; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 sp, 0x000c000d; +I0 = SP; +I1 = SP; +I2 = SP; +I3 = SP; +M0 = SP; +M1 = SP; +M2 = SP; +M3 = SP; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 fp, 0x000e000f; +I0 = FP; +I1 = FP; +I2 = FP; +I3 = FP; +M0 = FP; +M1 = FP; +M2 = FP; +M3 = FP; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + + +imm32 p1, 0x00020003; +L0 = P1; +L1 = P1; +L2 = P1; +L3 = P1; +B0 = P1; +B1 = P1; +B2 = P1; +B3 = P1; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 p2, 0x00040005; +L0 = P2; +L1 = P2; +L2 = P2; +L3 = P2; +B0 = P2; +B1 = P2; +B2 = P2; +B3 = P2; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 p3, 0x00060007; +L0 = P3; +L1 = P3; +L2 = P3; +L3 = P3; +B0 = P3; +B1 = P3; +B2 = P3; +B3 = P3; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 p4, 0x00080009; +L0 = P4; +L1 = P4; +L2 = P4; +L3 = P4; +B0 = P4; +B1 = P4; +B2 = P4; +B3 = P4; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 p5, 0x000a000b; +L0 = P5; +L1 = P5; +L2 = P5; +L3 = P5; +B0 = P5; +B1 = P5; +B2 = P5; +B3 = P5; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 sp, 0x000c000d; +L0 = SP; +L1 = SP; +L2 = SP; +L3 = SP; +B0 = SP; +B1 = SP; +B2 = SP; +B3 = SP; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 fp, 0x000e000f; +L0 = FP; +L1 = FP; +L2 = FP; +L3 = FP; +B0 = FP; +B1 = FP; +B2 = FP; +B3 = FP; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +pass diff --git a/tests/tcg/bfin/c_regmv_pr_pr.s b/tests/tcg/bfin/c_regmv_pr_pr.s new file mode 100644 index 0000000000000..9fb83f638c2e4 --- /dev/null +++ b/tests/tcg/bfin/c_regmv_pr_pr.s @@ -0,0 +1,95 @@ +//Original:/testcases/core/c_regmv_pr_pr/c_regmv_pr_pr.dsp +// Spec Reference: regmv preg-to-preg +# mach: bfin + +.include "testutils.inc" + start + +// check p-reg to p-reg move + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P1; + P2 = P1; + P4 = P1; + P5 = P1; + FP = P1; + CHECKREG p1, 0x20021003; + CHECKREG p2, 0x20021003; + CHECKREG p4, 0x20021003; + CHECKREG p5, 0x20021003; + CHECKREG fp, 0x20021003; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P2; + P2 = P2; + P4 = P2; + P5 = P2; + FP = P2; + CHECKREG p1, 0x20041005; + CHECKREG p2, 0x20041005; + CHECKREG p4, 0x20041005; + CHECKREG p5, 0x20041005; + CHECKREG fp, 0x20041005; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P4; + P2 = P4; + P4 = P4; + P5 = P4; + FP = P4; + CHECKREG p1, 0x20081009; + CHECKREG p2, 0x20081009; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x20081009; + CHECKREG fp, 0x20081009; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P5; + P2 = P5; + P4 = P5; + P5 = P5; + FP = P5; + CHECKREG p1, 0x200a100b; + CHECKREG p2, 0x200a100b; + CHECKREG p4, 0x200a100b; + CHECKREG p5, 0x200a100b; + CHECKREG fp, 0x200a100b; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = FP; + P2 = FP; + P4 = FP; + P5 = FP; + FP = FP; + CHECKREG p1, 0x200e100f; + CHECKREG p2, 0x200e100f; + CHECKREG p4, 0x200e100f; + CHECKREG p5, 0x200e100f; + CHECKREG fp, 0x200e100f; + + pass diff --git a/tests/tcg/bfin/c_ujump.s b/tests/tcg/bfin/c_ujump.s new file mode 100644 index 0000000000000..65dcf5ebf9174 --- /dev/null +++ b/tests/tcg/bfin/c_ujump.s @@ -0,0 +1,52 @@ +//Original:/testcases/core/c_ujump/c_ujump.dsp +// Spec Reference: ujump +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +JUMP.S LAB1; + + +STOP: +JUMP.S END; + +LAB1: + R1 = 0x1111 (X); +JUMP.S LAB5; + R6 = 0x6666 (X); + +LAB2: + R2 = 0x2222 (X); +JUMP.S STOP; + +LAB3: + R3 = 0x3333 (X); +JUMP.S LAB2; + R7 = 0x7777 (X); + +LAB4: + R4 = 0x4444 (X); +JUMP.S LAB3; + +LAB5: + R5 = 0x5555 (X); +JUMP.S LAB4; + +END: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00002222; +CHECKREG r3, 0x00003333; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00005555; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/tests/tcg/bfin/cc-astat-bits.s b/tests/tcg/bfin/cc-astat-bits.s new file mode 100644 index 0000000000000..1c7d485be783d --- /dev/null +++ b/tests/tcg/bfin/cc-astat-bits.s @@ -0,0 +1,101 @@ +# Blackfin testcase for setting all ASTAT bits via CC +# mach: bfin + +# We encode the opcodes directly since we test reserved bits +# which lack an insn in the ISA for it. It's a 16bit insn; +# the low 8 bits are always 0x03 while the encoding for the +# high 8 bits are: +# bit 7 - direction +# 0: CC=...; +# 1: ...=CC; +# bit 6/5 - operation +# 0: = assignment +# 1: | bit or +# 2: & bit and +# 3: ^ bit xor +# bit 4-0 - the bit in ASTAT to access + + .include "testutils.inc" + + .macro _do dir:req, op:req, bit:req, bit_in:req, cc_in:req, bg_val:req, bit_out:req, cc_out:req + /* CC = CC; is invalid, so skip it */ + .if \bit != 5 + + /* Calculate the before and after ASTAT values */ + imm32 R1, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_in << \bit) | (\cc_in << 5); + imm32 R3, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_out << \bit) | (\cc_out << 5); + + /* Test the actual opcode */ + ASTAT = R1; + .byte (\dir << 7) | (\op << 5) | \bit + .byte 0x03 + R2 = ASTAT; + + /* Make sure things line up */ + CC = R3 == R2; + IF !CC JUMP 1f; + JUMP 2f; +1: fail +2: + .endif + + /* Recurse through all the bits */ + .if \bit > 0 + _do \dir, \op, \bit - 1, \bit_in, \cc_in, \bg_val, \bit_out, \cc_out + .endif + .endm + + /* Test different background fields on ASTAT */ + .macro do dir:req, op:req, bit_in:req, cc_in:req, bit_out:req, cc_out:req + _do \dir, \op, 31, \bit_in, \cc_in, 0, \bit_out, \cc_out + _do \dir, \op, 31, \bit_in, \cc_in, -1, \bit_out, \cc_out + .endm + + start + nop; + +_cc_eq_bit: /* CC = bit */ + do 0, 0, 0, 0, 0, 0 + do 0, 0, 0, 1, 0, 0 + do 0, 0, 1, 0, 1, 1 + do 0, 0, 1, 1, 1, 1 +_bit_eq_cc: /* bit = CC */ + do 1, 0, 0, 0, 0, 0 + do 1, 0, 0, 1, 1, 1 + do 1, 0, 1, 0, 0, 0 + do 1, 0, 1, 1, 1, 1 + +_cc_or_bit: /* CC |= bit */ + do 0, 1, 0, 0, 0, 0 + do 0, 1, 0, 1, 0, 1 + do 0, 1, 1, 0, 1, 1 + do 0, 1, 1, 1, 1, 1 +_bit_or_cc: /* bit |= CC */ + do 1, 1, 0, 0, 0, 0 + do 1, 1, 0, 1, 1, 1 + do 1, 1, 1, 0, 1, 0 + do 1, 1, 1, 1, 1, 1 + +_cc_and_bit: /* CC &= bit */ + do 0, 2, 0, 0, 0, 0 + do 0, 2, 0, 1, 0, 0 + do 0, 2, 1, 0, 1, 0 + do 0, 2, 1, 1, 1, 1 +_bit_and_cc: /* bit &= CC */ + do 1, 2, 0, 0, 0, 0 + do 1, 2, 0, 1, 0, 1 + do 1, 2, 1, 0, 0, 0 + do 1, 2, 1, 1, 1, 1 + +_cc_xor_bit: /* CC ^= bit */ + do 0, 3, 0, 0, 0, 0 + do 0, 3, 0, 1, 0, 1 + do 0, 3, 1, 0, 1, 1 + do 0, 3, 1, 1, 1, 0 +_bit_xor_cc: /* bit ^= CC */ + do 1, 3, 0, 0, 0, 0 + do 1, 3, 0, 1, 1, 1 + do 1, 3, 1, 0, 1, 0 + do 1, 3, 1, 1, 0, 1 + + pass diff --git a/tests/tcg/bfin/cc1.s b/tests/tcg/bfin/cc1.s new file mode 100644 index 0000000000000..d5d86d8040e8f --- /dev/null +++ b/tests/tcg/bfin/cc1.s @@ -0,0 +1,26 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0x1234 (X); + CC = BITTST ( R0 , 2 ); + IF !CC JUMP s$0; + R0 += 1; +s$0: + nop; + DBGA ( R0.L , 0x1235 ); + CC = BITTST ( R0 , 1 ); + IF !CC JUMP s$1; + R0 += 1; +s$1: + nop; + DBGA ( R0.L , 0x1235 ); + CC = BITTST ( R0 , 12 ); + IF !CC JUMP s$3; + R0 = - R0; +s$3: + nop; + DBGA ( R0.L , 0xedcb ); + pass diff --git a/tests/tcg/bfin/cir.s b/tests/tcg/bfin/cir.s new file mode 100644 index 0000000000000..efbb9d4dda82e --- /dev/null +++ b/tests/tcg/bfin/cir.s @@ -0,0 +1,20 @@ +# Blackfin testcase for circular buffer limits +# mach: bfin + + .include "testutils.inc" + + start + + B0 = 0 (X); + I0 = 0x1100 (X); + L0 = 0x10c0 (X); + M0 = 0 (X); + I0 += M0; + R0 = I0; + + R1 = 0x40 (Z); + CC = R1 == R0 + if CC jump 1f; + fail +1: + pass diff --git a/tests/tcg/bfin/cir1.s b/tests/tcg/bfin/cir1.s new file mode 100644 index 0000000000000..78381acf494a3 --- /dev/null +++ b/tests/tcg/bfin/cir1.s @@ -0,0 +1,84 @@ +# Blackfin testcase for circular buffers +# mach: bfin + + .include "testutils.inc" + + .macro daginit i:req, b:req, l:req, m:req + imm32 I0, \i + imm32 B0, \b + imm32 L0, \l + imm32 M0, \m + .endm + .macro dagcheck newi:req + DBGA ( I0.L, \newi & 0xFFFF ); + DBGA ( I0.H, \newi >> 16 ); + .endm + + .macro dagadd i:req, b:req, l:req, m:req, newi:req + daginit \i, \b, \l, \m + I0 += M0; + dagcheck \newi + .endm + + .macro dagsub i:req, b:req, l:req, m:req, newi:req + daginit \i, \b, \l, \m + I0 -= M0; + dagcheck \newi + .endm + + .macro dag i:req, b:req, l:req, m:req, addi:req, subi:req + daginit \i, \b, \l, \m + I0 += M0; + dagcheck \addi + imm32 I0, \i + I0 -= M0; + dagcheck \subi + .endm + + start + + init_l_regs 0 + init_i_regs 0 + init_b_regs 0 + init_m_regs 0 + +_zero_len: + dag 0, 0, 0, 0, 0, 0 + dag 100, 0, 0, 0, 100, 100 + dag 100, 0, 0, 11, 111, 89 + dag 100, 0xaa00ff00, 0, 0, 100, 100 + dag 100, 0xaa00ff00, 0, 11, 111, 89 + +_zero_base: + dag 0, 0, 100, 10, 10, 90 + dag 50, 0, 100, 10, 60, 40 + dag 99, 0, 100, 10, 9, 89 + dag 50, 0, 100, 50, 0, 0 + dag 50, 0, 100, 100, 50, 50 + dag 50, 0, 100, 200, 150, -50 + dag 50, 0, 100, 2100, 2050, -1950 + dag 1000, 0, 100, 0, 900, 1000 + dag 1000, 0, 1000, 0, 0, 1000 + + dag 0xffff1000, 0, 0x1000, 0, 0xffff0000, 0xffff1000 + dag 0xaaaa1000, 0, 0xaaa1000, 0, 0xa0000000, 0xaaaa1000 + dag 0xaaaa1000, 0, 0xaaa1000, 0x1000, 0xa0001000, 0xaaaa0000 + dag 0xffff1000, 0, 0xffff0000, 0xffffff, 0x1000fff, 0xfeff1001 + +_positive_base: + dag 0, 100, 100, 10, 10, 90 + dag 90, 100, 100, 10, 100, 180 + dag 90, 100, 100, 2100, 2090, -1910 + dag 100, 100, 100, 100, 100, 100 + dag 0xfffff000, 0xffffff00, 0x10, 0xffff, 0xefef, 0xfffef011 + +_large_base_len: + dag 0, 0xffffff00, 0xffffff00, 0x00000100, 0x00000200, 0xfffffe00 + dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0x88888887, 0x77777779 + dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0x4ccccccc, 0x91111111, 0x6eeeeeef + dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0x00000000, 0x44444445, 0xbbbbbbbb + dag 0, 0xdddddddd, 0x7bbbbbbb, 0xcccccccc, 0xcccccccc, 0xb7777779 + dag 0, 0xbbbbbbbb, 0x7bbbbbbb, 0x4ccccccc, 0x4ccccccc, 0xb3333334 + dag 0, 0xbbbbbbbb, 0x7bbbbbbb, 0x00000000, 0x84444445, 0x7bbbbbbb + + pass diff --git a/tests/tcg/bfin/cmpdreg.S b/tests/tcg/bfin/cmpdreg.S new file mode 100644 index 0000000000000..b2265f5dc0642 --- /dev/null +++ b/tests/tcg/bfin/cmpdreg.S @@ -0,0 +1,40 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + r0 = 0; + ASTAT = R0; + + r0.h =0x8000; + r1 = 0; + r1.h =0x8000; + cc = r1==r0; + _dbg astat; + r7=astat; + CHECKREG R7, (_AC0|_AC0_COPY|_CC|_AZ); + + r7=0; + astat=r7; + r0.l = 0xffff; + r0.h =0x7fff; + r1.l = 0xffff; + r1.h =0x7fff; + cc = r1==r0; + _dbg astat; + r7=astat; + CHECKREG R7, (_AC0|_AC0_COPY|_CC|_AZ); + + r7=0; + astat=r7; + r0.l = 0; + r0.h =0x8000; + r1.l = 0xffff; + r1.h =0x7fff; + cc = r1==r0; + _dbg astat; + r7=astat; + CHECKREG R7, (_UNSET); + + pass; diff --git a/tests/tcg/bfin/compare.s b/tests/tcg/bfin/compare.s new file mode 100644 index 0000000000000..484518c7c01b0 --- /dev/null +++ b/tests/tcg/bfin/compare.s @@ -0,0 +1,15 @@ +# Blackfin testcase for compare instructions +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 0 (X); + R1 = 0 (X); + CC = R0 == R1; + IF !CC JUMP 1f; + IF !CC JUMP 1f (bp); + pass +1: + fail diff --git a/tests/tcg/bfin/d0.s b/tests/tcg/bfin/d0.s new file mode 100644 index 0000000000000..5e13959ff390d --- /dev/null +++ b/tests/tcg/bfin/d0.s @@ -0,0 +1,31 @@ +# mach: bfin + +.include "testutils.inc" + start + + I1 = 0x4 (X); + B1 = 0x0 (X); + L1 = 0x10 (X); + M0 = 8 (X); + I1 -= M0; + R0 = I1; + DBGA ( R0.L , 0xc ); + + I1 = 0xf0 (X); + B1 = 0x100 (X); + L1 = 0x10 (X); + M0 = 2 (X); + I1 += M0; + R0 = I1; + DBGA ( R0.L , 0xf2 ); + + I2 = 0x1000 (X); + B2.L = 0; + B2.H = 0x9000; + L2 = 0x10 (X); + M2 = 0 (X); + I2 += M2; + R0 = I2; + DBGA ( R0.L , 0x1000 ); + + pass diff --git a/tests/tcg/bfin/d1.s b/tests/tcg/bfin/d1.s new file mode 100644 index 0000000000000..ea563304034c4 --- /dev/null +++ b/tests/tcg/bfin/d1.s @@ -0,0 +1,17 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + I0 = 0x1100 (X); + L0 = 0x10c0 (X); + M0 = 0 (X); + B0 = 0 (X); + I0 += M0; + R0 = I0; + DBGA ( R0.L , 0x40 ); + + pass diff --git a/tests/tcg/bfin/d2.s b/tests/tcg/bfin/d2.s new file mode 100644 index 0000000000000..2634f4bbe19cc --- /dev/null +++ b/tests/tcg/bfin/d2.s @@ -0,0 +1,56 @@ +# Blackfin testcase for circular buffers and BREV +# mach: bfin + + .include "testutils.inc" + + start + + I0 = 0 (X); + M0 = 0x8 (X); + P0 = 16; + loadsym R1, vals; + +aaa: + I0 += M0 (BREV); + P0 += -1; + + R2 = I0; + R0 = R1 + R2 + P1 = R0; + R0 = B[P1] (Z); + + R3 = P0; + + CC = R0 == R3; + if !CC JUMP _fail; + + CC = P0 == 0; + IF !CC JUMP aaa (BP); + R0 = I0; + + DBGA(R0.L, 0x0000); + DBGA(R0.H, 0x0000); + + pass + +_fail: + fail + + .data +vals: +.db 0x0 /* 0 */ +.db 0x8 +.db 0xc +.db 0x4 /* 4 */ +.db 0xe +.db 0x6 +.db 0xa +.db 0x2 /* 8 */ +.db 0xf +.db 0x7 +.db 0xB +.db 0x3 /* c */ +.db 0xD +.db 0x5 +.db 0x9 /* f */ +.db 0x1 diff --git a/tests/tcg/bfin/div0.s b/tests/tcg/bfin/div0.s new file mode 100644 index 0000000000000..e52fe45bd4977 --- /dev/null +++ b/tests/tcg/bfin/div0.s @@ -0,0 +1,37 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 70 (X); + R1 = 5; + + P2 = 16; + DIVS ( R0 , R1 ); + LSETUP ( s0 , s0 ) LC0 = P2; +s0: + DIVQ ( R0 , R1 ); + + DBGA ( R0.L , 14 ); + + R0 = 3272 (X); + R1 = 55; + + DIVS ( R0 , R1 ); + LSETUP ( s1 , s1 ) LC0 = P2; +s1: + DIVQ ( R0 , R1 ); + + DBGA ( R0.L , 59 ); + + R0 = 32767 (X); + R1 = 55; + DIVS ( R0 , R1 ); + + LSETUP ( s2 , s2 ) LC0 = P2; +s2: + DIVQ ( R0 , R1 ); + + DBGA ( R0.L , 595 ); + + pass diff --git a/tests/tcg/bfin/divq.s b/tests/tcg/bfin/divq.s new file mode 100644 index 0000000000000..6cb881b1307a7 --- /dev/null +++ b/tests/tcg/bfin/divq.s @@ -0,0 +1,1322 @@ +# Blackfin testcase for divide instructions +# mach: bfin + + + .include "testutils.inc" + + start + + /* + * Evaluate given a signed integer dividend and signed interger divisor + * input is: + * r0 = dividend, or numerator + * r1 = divisor, or denominator + * output is: + * r0 = quotient (16-bits) + */ + .macro divide num:req, den:req + imm32 r0 \num + r1 = \den (Z); + + r0 <<= 1; /* Left shift dividend by 1 needed for integer division */ + p0 = 15; /* Evaluate the quotient to 16 bits. */ + + /* Initialize AQ status bit and dividend for the DIVQ loop. */ + divs (r0, r1); + + /* Evaluate DIVQ p0=15 times. */ + lsetup (1f, 1f) lc0=p0; +1: + divq (r0, r1); + + /* Sign extend the 16-bit quotient to 32bits. */ + r0 = r0.l (x); + + imm32 r1, (\num / \den); + CC = r0 == r1 + if CC jump 2f; + fail +2: + .endm + + /* test a bunch of values, making sure not to : + * - exceed a signed 16-bit divisor + * - exceed a signed 16-bit answer + */ + divide 0x00000001, 0x0001 /* expect 0x0001 */ + divide 0x00000001, 0x0002 /* expect 0x0000 */ + divide 0x00000001, 0x0003 /* expect 0x0000 */ + divide 0x00000001, 0x0004 /* expect 0x0000 */ + divide 0x00000001, 0x0007 /* expect 0x0000 */ + divide 0x00000001, 0x0008 /* expect 0x0000 */ + divide 0x00000001, 0x000f /* expect 0x0000 */ + divide 0x00000001, 0x0010 /* expect 0x0000 */ + divide 0x00000001, 0x001f /* expect 0x0000 */ + divide 0x00000001, 0x0020 /* expect 0x0000 */ + divide 0x00000001, 0x003f /* expect 0x0000 */ + divide 0x00000001, 0x0040 /* expect 0x0000 */ + divide 0x00000001, 0x007f /* expect 0x0000 */ + divide 0x00000001, 0x0080 /* expect 0x0000 */ + divide 0x00000001, 0x00ff /* expect 0x0000 */ + divide 0x00000001, 0x0100 /* expect 0x0000 */ + divide 0x00000001, 0x01ff /* expect 0x0000 */ + divide 0x00000001, 0x0200 /* expect 0x0000 */ + divide 0x00000001, 0x03ff /* expect 0x0000 */ + divide 0x00000001, 0x0400 /* expect 0x0000 */ + divide 0x00000001, 0x07ff /* expect 0x0000 */ + divide 0x00000001, 0x0800 /* expect 0x0000 */ + divide 0x00000001, 0x0fff /* expect 0x0000 */ + divide 0x00000001, 0x1000 /* expect 0x0000 */ + divide 0x00000001, 0x1fff /* expect 0x0000 */ + divide 0x00000001, 0x2000 /* expect 0x0000 */ + divide 0x00000001, 0x3fff /* expect 0x0000 */ + divide 0x00000001, 0x4000 /* expect 0x0000 */ + divide 0x00000001, 0x7fff /* expect 0x0000 */ + divide 0x00000002, 0x0001 /* expect 0x0002 */ + divide 0x00000002, 0x0002 /* expect 0x0001 */ + divide 0x00000002, 0x0003 /* expect 0x0000 */ + divide 0x00000002, 0x0004 /* expect 0x0000 */ + divide 0x00000002, 0x0007 /* expect 0x0000 */ + divide 0x00000002, 0x0008 /* expect 0x0000 */ + divide 0x00000002, 0x000f /* expect 0x0000 */ + divide 0x00000002, 0x0010 /* expect 0x0000 */ + divide 0x00000002, 0x001f /* expect 0x0000 */ + divide 0x00000002, 0x0020 /* expect 0x0000 */ + divide 0x00000002, 0x003f /* expect 0x0000 */ + divide 0x00000002, 0x0040 /* expect 0x0000 */ + divide 0x00000002, 0x007f /* expect 0x0000 */ + divide 0x00000002, 0x0080 /* expect 0x0000 */ + divide 0x00000002, 0x00ff /* expect 0x0000 */ + divide 0x00000002, 0x0100 /* expect 0x0000 */ + divide 0x00000002, 0x01ff /* expect 0x0000 */ + divide 0x00000002, 0x0200 /* expect 0x0000 */ + divide 0x00000002, 0x03ff /* expect 0x0000 */ + divide 0x00000002, 0x0400 /* expect 0x0000 */ + divide 0x00000002, 0x07ff /* expect 0x0000 */ + divide 0x00000002, 0x0800 /* expect 0x0000 */ + divide 0x00000002, 0x0fff /* expect 0x0000 */ + divide 0x00000002, 0x1000 /* expect 0x0000 */ + divide 0x00000002, 0x1fff /* expect 0x0000 */ + divide 0x00000002, 0x2000 /* expect 0x0000 */ + divide 0x00000002, 0x3fff /* expect 0x0000 */ + divide 0x00000002, 0x4000 /* expect 0x0000 */ + divide 0x00000002, 0x7fff /* expect 0x0000 */ + divide 0x00000003, 0x0001 /* expect 0x0003 */ + divide 0x00000003, 0x0002 /* expect 0x0001 */ + divide 0x00000003, 0x0003 /* expect 0x0001 */ + divide 0x00000003, 0x0004 /* expect 0x0000 */ + divide 0x00000003, 0x0007 /* expect 0x0000 */ + divide 0x00000003, 0x0008 /* expect 0x0000 */ + divide 0x00000003, 0x000f /* expect 0x0000 */ + divide 0x00000003, 0x0010 /* expect 0x0000 */ + divide 0x00000003, 0x001f /* expect 0x0000 */ + divide 0x00000003, 0x0020 /* expect 0x0000 */ + divide 0x00000003, 0x003f /* expect 0x0000 */ + divide 0x00000003, 0x0040 /* expect 0x0000 */ + divide 0x00000003, 0x007f /* expect 0x0000 */ + divide 0x00000003, 0x0080 /* expect 0x0000 */ + divide 0x00000003, 0x00ff /* expect 0x0000 */ + divide 0x00000003, 0x0100 /* expect 0x0000 */ + divide 0x00000003, 0x01ff /* expect 0x0000 */ + divide 0x00000003, 0x0200 /* expect 0x0000 */ + divide 0x00000003, 0x03ff /* expect 0x0000 */ + divide 0x00000003, 0x0400 /* expect 0x0000 */ + divide 0x00000003, 0x07ff /* expect 0x0000 */ + divide 0x00000003, 0x0800 /* expect 0x0000 */ + divide 0x00000003, 0x0fff /* expect 0x0000 */ + divide 0x00000003, 0x1000 /* expect 0x0000 */ + divide 0x00000003, 0x1fff /* expect 0x0000 */ + divide 0x00000003, 0x2000 /* expect 0x0000 */ + divide 0x00000003, 0x3fff /* expect 0x0000 */ + divide 0x00000003, 0x4000 /* expect 0x0000 */ + divide 0x00000003, 0x7fff /* expect 0x0000 */ + divide 0x00000004, 0x0001 /* expect 0x0004 */ + divide 0x00000004, 0x0002 /* expect 0x0002 */ + divide 0x00000004, 0x0003 /* expect 0x0001 */ + divide 0x00000004, 0x0004 /* expect 0x0001 */ + divide 0x00000004, 0x0007 /* expect 0x0000 */ + divide 0x00000004, 0x0008 /* expect 0x0000 */ + divide 0x00000004, 0x000f /* expect 0x0000 */ + divide 0x00000004, 0x0010 /* expect 0x0000 */ + divide 0x00000004, 0x001f /* expect 0x0000 */ + divide 0x00000004, 0x0020 /* expect 0x0000 */ + divide 0x00000004, 0x003f /* expect 0x0000 */ + divide 0x00000004, 0x0040 /* expect 0x0000 */ + divide 0x00000004, 0x007f /* expect 0x0000 */ + divide 0x00000004, 0x0080 /* expect 0x0000 */ + divide 0x00000004, 0x00ff /* expect 0x0000 */ + divide 0x00000004, 0x0100 /* expect 0x0000 */ + divide 0x00000004, 0x01ff /* expect 0x0000 */ + divide 0x00000004, 0x0200 /* expect 0x0000 */ + divide 0x00000004, 0x03ff /* expect 0x0000 */ + divide 0x00000004, 0x0400 /* expect 0x0000 */ + divide 0x00000004, 0x07ff /* expect 0x0000 */ + divide 0x00000004, 0x0800 /* expect 0x0000 */ + divide 0x00000004, 0x0fff /* expect 0x0000 */ + divide 0x00000004, 0x1000 /* expect 0x0000 */ + divide 0x00000004, 0x1fff /* expect 0x0000 */ + divide 0x00000004, 0x2000 /* expect 0x0000 */ + divide 0x00000004, 0x3fff /* expect 0x0000 */ + divide 0x00000004, 0x4000 /* expect 0x0000 */ + divide 0x00000004, 0x7fff /* expect 0x0000 */ + divide 0x00000007, 0x0001 /* expect 0x0007 */ + divide 0x00000007, 0x0002 /* expect 0x0003 */ + divide 0x00000007, 0x0003 /* expect 0x0002 */ + divide 0x00000007, 0x0004 /* expect 0x0001 */ + divide 0x00000007, 0x0007 /* expect 0x0001 */ + divide 0x00000007, 0x0008 /* expect 0x0000 */ + divide 0x00000007, 0x000f /* expect 0x0000 */ + divide 0x00000007, 0x0010 /* expect 0x0000 */ + divide 0x00000007, 0x001f /* expect 0x0000 */ + divide 0x00000007, 0x0020 /* expect 0x0000 */ + divide 0x00000007, 0x003f /* expect 0x0000 */ + divide 0x00000007, 0x0040 /* expect 0x0000 */ + divide 0x00000007, 0x007f /* expect 0x0000 */ + divide 0x00000007, 0x0080 /* expect 0x0000 */ + divide 0x00000007, 0x00ff /* expect 0x0000 */ + divide 0x00000007, 0x0100 /* expect 0x0000 */ + divide 0x00000007, 0x01ff /* expect 0x0000 */ + divide 0x00000007, 0x0200 /* expect 0x0000 */ + divide 0x00000007, 0x03ff /* expect 0x0000 */ + divide 0x00000007, 0x0400 /* expect 0x0000 */ + divide 0x00000007, 0x07ff /* expect 0x0000 */ + divide 0x00000007, 0x0800 /* expect 0x0000 */ + divide 0x00000007, 0x0fff /* expect 0x0000 */ + divide 0x00000007, 0x1000 /* expect 0x0000 */ + divide 0x00000007, 0x1fff /* expect 0x0000 */ + divide 0x00000007, 0x2000 /* expect 0x0000 */ + divide 0x00000007, 0x3fff /* expect 0x0000 */ + divide 0x00000007, 0x4000 /* expect 0x0000 */ + divide 0x00000007, 0x7fff /* expect 0x0000 */ + divide 0x00000008, 0x0001 /* expect 0x0008 */ + divide 0x00000008, 0x0002 /* expect 0x0004 */ + divide 0x00000008, 0x0003 /* expect 0x0002 */ + divide 0x00000008, 0x0004 /* expect 0x0002 */ + divide 0x00000008, 0x0007 /* expect 0x0001 */ + divide 0x00000008, 0x0008 /* expect 0x0001 */ + divide 0x00000008, 0x000f /* expect 0x0000 */ + divide 0x00000008, 0x0010 /* expect 0x0000 */ + divide 0x00000008, 0x001f /* expect 0x0000 */ + divide 0x00000008, 0x0020 /* expect 0x0000 */ + divide 0x00000008, 0x003f /* expect 0x0000 */ + divide 0x00000008, 0x0040 /* expect 0x0000 */ + divide 0x00000008, 0x007f /* expect 0x0000 */ + divide 0x00000008, 0x0080 /* expect 0x0000 */ + divide 0x00000008, 0x00ff /* expect 0x0000 */ + divide 0x00000008, 0x0100 /* expect 0x0000 */ + divide 0x00000008, 0x01ff /* expect 0x0000 */ + divide 0x00000008, 0x0200 /* expect 0x0000 */ + divide 0x00000008, 0x03ff /* expect 0x0000 */ + divide 0x00000008, 0x0400 /* expect 0x0000 */ + divide 0x00000008, 0x07ff /* expect 0x0000 */ + divide 0x00000008, 0x0800 /* expect 0x0000 */ + divide 0x00000008, 0x0fff /* expect 0x0000 */ + divide 0x00000008, 0x1000 /* expect 0x0000 */ + divide 0x00000008, 0x1fff /* expect 0x0000 */ + divide 0x00000008, 0x2000 /* expect 0x0000 */ + divide 0x00000008, 0x3fff /* expect 0x0000 */ + divide 0x00000008, 0x4000 /* expect 0x0000 */ + divide 0x00000008, 0x7fff /* expect 0x0000 */ + divide 0x0000000f, 0x0001 /* expect 0x000f */ + divide 0x0000000f, 0x0002 /* expect 0x0007 */ + divide 0x0000000f, 0x0003 /* expect 0x0005 */ + divide 0x0000000f, 0x0004 /* expect 0x0003 */ + divide 0x0000000f, 0x0007 /* expect 0x0002 */ + divide 0x0000000f, 0x0008 /* expect 0x0001 */ + divide 0x0000000f, 0x000f /* expect 0x0001 */ + divide 0x0000000f, 0x0010 /* expect 0x0000 */ + divide 0x0000000f, 0x001f /* expect 0x0000 */ + divide 0x0000000f, 0x0020 /* expect 0x0000 */ + divide 0x0000000f, 0x003f /* expect 0x0000 */ + divide 0x0000000f, 0x0040 /* expect 0x0000 */ + divide 0x0000000f, 0x007f /* expect 0x0000 */ + divide 0x0000000f, 0x0080 /* expect 0x0000 */ + divide 0x0000000f, 0x00ff /* expect 0x0000 */ + divide 0x0000000f, 0x0100 /* expect 0x0000 */ + divide 0x0000000f, 0x01ff /* expect 0x0000 */ + divide 0x0000000f, 0x0200 /* expect 0x0000 */ + divide 0x0000000f, 0x03ff /* expect 0x0000 */ + divide 0x0000000f, 0x0400 /* expect 0x0000 */ + divide 0x0000000f, 0x07ff /* expect 0x0000 */ + divide 0x0000000f, 0x0800 /* expect 0x0000 */ + divide 0x0000000f, 0x0fff /* expect 0x0000 */ + divide 0x0000000f, 0x1000 /* expect 0x0000 */ + divide 0x0000000f, 0x1fff /* expect 0x0000 */ + divide 0x0000000f, 0x2000 /* expect 0x0000 */ + divide 0x0000000f, 0x3fff /* expect 0x0000 */ + divide 0x0000000f, 0x4000 /* expect 0x0000 */ + divide 0x0000000f, 0x7fff /* expect 0x0000 */ + divide 0x00000010, 0x0001 /* expect 0x0010 */ + divide 0x00000010, 0x0002 /* expect 0x0008 */ + divide 0x00000010, 0x0003 /* expect 0x0005 */ + divide 0x00000010, 0x0004 /* expect 0x0004 */ + divide 0x00000010, 0x0007 /* expect 0x0002 */ + divide 0x00000010, 0x0008 /* expect 0x0002 */ + divide 0x00000010, 0x000f /* expect 0x0001 */ + divide 0x00000010, 0x0010 /* expect 0x0001 */ + divide 0x00000010, 0x001f /* expect 0x0000 */ + divide 0x00000010, 0x0020 /* expect 0x0000 */ + divide 0x00000010, 0x003f /* expect 0x0000 */ + divide 0x00000010, 0x0040 /* expect 0x0000 */ + divide 0x00000010, 0x007f /* expect 0x0000 */ + divide 0x00000010, 0x0080 /* expect 0x0000 */ + divide 0x00000010, 0x00ff /* expect 0x0000 */ + divide 0x00000010, 0x0100 /* expect 0x0000 */ + divide 0x00000010, 0x01ff /* expect 0x0000 */ + divide 0x00000010, 0x0200 /* expect 0x0000 */ + divide 0x00000010, 0x03ff /* expect 0x0000 */ + divide 0x00000010, 0x0400 /* expect 0x0000 */ + divide 0x00000010, 0x07ff /* expect 0x0000 */ + divide 0x00000010, 0x0800 /* expect 0x0000 */ + divide 0x00000010, 0x0fff /* expect 0x0000 */ + divide 0x00000010, 0x1000 /* expect 0x0000 */ + divide 0x00000010, 0x1fff /* expect 0x0000 */ + divide 0x00000010, 0x2000 /* expect 0x0000 */ + divide 0x00000010, 0x3fff /* expect 0x0000 */ + divide 0x00000010, 0x4000 /* expect 0x0000 */ + divide 0x00000010, 0x7fff /* expect 0x0000 */ + divide 0x0000001f, 0x0001 /* expect 0x001f */ + divide 0x0000001f, 0x0002 /* expect 0x000f */ + divide 0x0000001f, 0x0003 /* expect 0x000a */ + divide 0x0000001f, 0x0004 /* expect 0x0007 */ + divide 0x0000001f, 0x0007 /* expect 0x0004 */ + divide 0x0000001f, 0x0008 /* expect 0x0003 */ + divide 0x0000001f, 0x000f /* expect 0x0002 */ + divide 0x0000001f, 0x0010 /* expect 0x0001 */ + divide 0x0000001f, 0x001f /* expect 0x0001 */ + divide 0x0000001f, 0x0020 /* expect 0x0000 */ + divide 0x0000001f, 0x003f /* expect 0x0000 */ + divide 0x0000001f, 0x0040 /* expect 0x0000 */ + divide 0x0000001f, 0x007f /* expect 0x0000 */ + divide 0x0000001f, 0x0080 /* expect 0x0000 */ + divide 0x0000001f, 0x00ff /* expect 0x0000 */ + divide 0x0000001f, 0x0100 /* expect 0x0000 */ + divide 0x0000001f, 0x01ff /* expect 0x0000 */ + divide 0x0000001f, 0x0200 /* expect 0x0000 */ + divide 0x0000001f, 0x03ff /* expect 0x0000 */ + divide 0x0000001f, 0x0400 /* expect 0x0000 */ + divide 0x0000001f, 0x07ff /* expect 0x0000 */ + divide 0x0000001f, 0x0800 /* expect 0x0000 */ + divide 0x0000001f, 0x0fff /* expect 0x0000 */ + divide 0x0000001f, 0x1000 /* expect 0x0000 */ + divide 0x0000001f, 0x1fff /* expect 0x0000 */ + divide 0x0000001f, 0x2000 /* expect 0x0000 */ + divide 0x0000001f, 0x3fff /* expect 0x0000 */ + divide 0x0000001f, 0x4000 /* expect 0x0000 */ + divide 0x0000001f, 0x7fff /* expect 0x0000 */ + divide 0x00000020, 0x0001 /* expect 0x0020 */ + divide 0x00000020, 0x0002 /* expect 0x0010 */ + divide 0x00000020, 0x0003 /* expect 0x000a */ + divide 0x00000020, 0x0004 /* expect 0x0008 */ + divide 0x00000020, 0x0007 /* expect 0x0004 */ + divide 0x00000020, 0x0008 /* expect 0x0004 */ + divide 0x00000020, 0x000f /* expect 0x0002 */ + divide 0x00000020, 0x0010 /* expect 0x0002 */ + divide 0x00000020, 0x001f /* expect 0x0001 */ + divide 0x00000020, 0x0020 /* expect 0x0001 */ + divide 0x00000020, 0x003f /* expect 0x0000 */ + divide 0x00000020, 0x0040 /* expect 0x0000 */ + divide 0x00000020, 0x007f /* expect 0x0000 */ + divide 0x00000020, 0x0080 /* expect 0x0000 */ + divide 0x00000020, 0x00ff /* expect 0x0000 */ + divide 0x00000020, 0x0100 /* expect 0x0000 */ + divide 0x00000020, 0x01ff /* expect 0x0000 */ + divide 0x00000020, 0x0200 /* expect 0x0000 */ + divide 0x00000020, 0x03ff /* expect 0x0000 */ + divide 0x00000020, 0x0400 /* expect 0x0000 */ + divide 0x00000020, 0x07ff /* expect 0x0000 */ + divide 0x00000020, 0x0800 /* expect 0x0000 */ + divide 0x00000020, 0x0fff /* expect 0x0000 */ + divide 0x00000020, 0x1000 /* expect 0x0000 */ + divide 0x00000020, 0x1fff /* expect 0x0000 */ + divide 0x00000020, 0x2000 /* expect 0x0000 */ + divide 0x00000020, 0x3fff /* expect 0x0000 */ + divide 0x00000020, 0x4000 /* expect 0x0000 */ + divide 0x00000020, 0x7fff /* expect 0x0000 */ + divide 0x0000003f, 0x0001 /* expect 0x003f */ + divide 0x0000003f, 0x0002 /* expect 0x001f */ + divide 0x0000003f, 0x0003 /* expect 0x0015 */ + divide 0x0000003f, 0x0004 /* expect 0x000f */ + divide 0x0000003f, 0x0007 /* expect 0x0009 */ + divide 0x0000003f, 0x0008 /* expect 0x0007 */ + divide 0x0000003f, 0x000f /* expect 0x0004 */ + divide 0x0000003f, 0x0010 /* expect 0x0003 */ + divide 0x0000003f, 0x001f /* expect 0x0002 */ + divide 0x0000003f, 0x0020 /* expect 0x0001 */ + divide 0x0000003f, 0x003f /* expect 0x0001 */ + divide 0x0000003f, 0x0040 /* expect 0x0000 */ + divide 0x0000003f, 0x007f /* expect 0x0000 */ + divide 0x0000003f, 0x0080 /* expect 0x0000 */ + divide 0x0000003f, 0x00ff /* expect 0x0000 */ + divide 0x0000003f, 0x0100 /* expect 0x0000 */ + divide 0x0000003f, 0x01ff /* expect 0x0000 */ + divide 0x0000003f, 0x0200 /* expect 0x0000 */ + divide 0x0000003f, 0x03ff /* expect 0x0000 */ + divide 0x0000003f, 0x0400 /* expect 0x0000 */ + divide 0x0000003f, 0x07ff /* expect 0x0000 */ + divide 0x0000003f, 0x0800 /* expect 0x0000 */ + divide 0x0000003f, 0x0fff /* expect 0x0000 */ + divide 0x0000003f, 0x1000 /* expect 0x0000 */ + divide 0x0000003f, 0x1fff /* expect 0x0000 */ + divide 0x0000003f, 0x2000 /* expect 0x0000 */ + divide 0x0000003f, 0x3fff /* expect 0x0000 */ + divide 0x0000003f, 0x4000 /* expect 0x0000 */ + divide 0x0000003f, 0x7fff /* expect 0x0000 */ + divide 0x00000040, 0x0001 /* expect 0x0040 */ + divide 0x00000040, 0x0002 /* expect 0x0020 */ + divide 0x00000040, 0x0003 /* expect 0x0015 */ + divide 0x00000040, 0x0004 /* expect 0x0010 */ + divide 0x00000040, 0x0007 /* expect 0x0009 */ + divide 0x00000040, 0x0008 /* expect 0x0008 */ + divide 0x00000040, 0x000f /* expect 0x0004 */ + divide 0x00000040, 0x0010 /* expect 0x0004 */ + divide 0x00000040, 0x001f /* expect 0x0002 */ + divide 0x00000040, 0x0020 /* expect 0x0002 */ + divide 0x00000040, 0x003f /* expect 0x0001 */ + divide 0x00000040, 0x0040 /* expect 0x0001 */ + divide 0x00000040, 0x007f /* expect 0x0000 */ + divide 0x00000040, 0x0080 /* expect 0x0000 */ + divide 0x00000040, 0x00ff /* expect 0x0000 */ + divide 0x00000040, 0x0100 /* expect 0x0000 */ + divide 0x00000040, 0x01ff /* expect 0x0000 */ + divide 0x00000040, 0x0200 /* expect 0x0000 */ + divide 0x00000040, 0x03ff /* expect 0x0000 */ + divide 0x00000040, 0x0400 /* expect 0x0000 */ + divide 0x00000040, 0x07ff /* expect 0x0000 */ + divide 0x00000040, 0x0800 /* expect 0x0000 */ + divide 0x00000040, 0x0fff /* expect 0x0000 */ + divide 0x00000040, 0x1000 /* expect 0x0000 */ + divide 0x00000040, 0x1fff /* expect 0x0000 */ + divide 0x00000040, 0x2000 /* expect 0x0000 */ + divide 0x00000040, 0x3fff /* expect 0x0000 */ + divide 0x00000040, 0x4000 /* expect 0x0000 */ + divide 0x00000040, 0x7fff /* expect 0x0000 */ + divide 0x0000007f, 0x0001 /* expect 0x007f */ + divide 0x0000007f, 0x0002 /* expect 0x003f */ + divide 0x0000007f, 0x0003 /* expect 0x002a */ + divide 0x0000007f, 0x0004 /* expect 0x001f */ + divide 0x0000007f, 0x0007 /* expect 0x0012 */ + divide 0x0000007f, 0x0008 /* expect 0x000f */ + divide 0x0000007f, 0x000f /* expect 0x0008 */ + divide 0x0000007f, 0x0010 /* expect 0x0007 */ + divide 0x0000007f, 0x001f /* expect 0x0004 */ + divide 0x0000007f, 0x0020 /* expect 0x0003 */ + divide 0x0000007f, 0x003f /* expect 0x0002 */ + divide 0x0000007f, 0x0040 /* expect 0x0001 */ + divide 0x0000007f, 0x007f /* expect 0x0001 */ + divide 0x0000007f, 0x0080 /* expect 0x0000 */ + divide 0x0000007f, 0x00ff /* expect 0x0000 */ + divide 0x0000007f, 0x0100 /* expect 0x0000 */ + divide 0x0000007f, 0x01ff /* expect 0x0000 */ + divide 0x0000007f, 0x0200 /* expect 0x0000 */ + divide 0x0000007f, 0x03ff /* expect 0x0000 */ + divide 0x0000007f, 0x0400 /* expect 0x0000 */ + divide 0x0000007f, 0x07ff /* expect 0x0000 */ + divide 0x0000007f, 0x0800 /* expect 0x0000 */ + divide 0x0000007f, 0x0fff /* expect 0x0000 */ + divide 0x0000007f, 0x1000 /* expect 0x0000 */ + divide 0x0000007f, 0x1fff /* expect 0x0000 */ + divide 0x0000007f, 0x2000 /* expect 0x0000 */ + divide 0x0000007f, 0x3fff /* expect 0x0000 */ + divide 0x0000007f, 0x4000 /* expect 0x0000 */ + divide 0x0000007f, 0x7fff /* expect 0x0000 */ + divide 0x00000080, 0x0001 /* expect 0x0080 */ + divide 0x00000080, 0x0002 /* expect 0x0040 */ + divide 0x00000080, 0x0003 /* expect 0x002a */ + divide 0x00000080, 0x0004 /* expect 0x0020 */ + divide 0x00000080, 0x0007 /* expect 0x0012 */ + divide 0x00000080, 0x0008 /* expect 0x0010 */ + divide 0x00000080, 0x000f /* expect 0x0008 */ + divide 0x00000080, 0x0010 /* expect 0x0008 */ + divide 0x00000080, 0x001f /* expect 0x0004 */ + divide 0x00000080, 0x0020 /* expect 0x0004 */ + divide 0x00000080, 0x003f /* expect 0x0002 */ + divide 0x00000080, 0x0040 /* expect 0x0002 */ + divide 0x00000080, 0x007f /* expect 0x0001 */ + divide 0x00000080, 0x0080 /* expect 0x0001 */ + divide 0x00000080, 0x00ff /* expect 0x0000 */ + divide 0x00000080, 0x0100 /* expect 0x0000 */ + divide 0x00000080, 0x01ff /* expect 0x0000 */ + divide 0x00000080, 0x0200 /* expect 0x0000 */ + divide 0x00000080, 0x03ff /* expect 0x0000 */ + divide 0x00000080, 0x0400 /* expect 0x0000 */ + divide 0x00000080, 0x07ff /* expect 0x0000 */ + divide 0x00000080, 0x0800 /* expect 0x0000 */ + divide 0x00000080, 0x0fff /* expect 0x0000 */ + divide 0x00000080, 0x1000 /* expect 0x0000 */ + divide 0x00000080, 0x1fff /* expect 0x0000 */ + divide 0x00000080, 0x2000 /* expect 0x0000 */ + divide 0x00000080, 0x3fff /* expect 0x0000 */ + divide 0x00000080, 0x4000 /* expect 0x0000 */ + divide 0x00000080, 0x7fff /* expect 0x0000 */ + divide 0x000000ff, 0x0001 /* expect 0x00ff */ + divide 0x000000ff, 0x0002 /* expect 0x007f */ + divide 0x000000ff, 0x0003 /* expect 0x0055 */ + divide 0x000000ff, 0x0004 /* expect 0x003f */ + divide 0x000000ff, 0x0007 /* expect 0x0024 */ + divide 0x000000ff, 0x0008 /* expect 0x001f */ + divide 0x000000ff, 0x000f /* expect 0x0011 */ + divide 0x000000ff, 0x0010 /* expect 0x000f */ + divide 0x000000ff, 0x001f /* expect 0x0008 */ + divide 0x000000ff, 0x0020 /* expect 0x0007 */ + divide 0x000000ff, 0x003f /* expect 0x0004 */ + divide 0x000000ff, 0x0040 /* expect 0x0003 */ + divide 0x000000ff, 0x007f /* expect 0x0002 */ + divide 0x000000ff, 0x0080 /* expect 0x0001 */ + divide 0x000000ff, 0x00ff /* expect 0x0001 */ + divide 0x000000ff, 0x0100 /* expect 0x0000 */ + divide 0x000000ff, 0x01ff /* expect 0x0000 */ + divide 0x000000ff, 0x0200 /* expect 0x0000 */ + divide 0x000000ff, 0x03ff /* expect 0x0000 */ + divide 0x000000ff, 0x0400 /* expect 0x0000 */ + divide 0x000000ff, 0x07ff /* expect 0x0000 */ + divide 0x000000ff, 0x0800 /* expect 0x0000 */ + divide 0x000000ff, 0x0fff /* expect 0x0000 */ + divide 0x000000ff, 0x1000 /* expect 0x0000 */ + divide 0x000000ff, 0x1fff /* expect 0x0000 */ + divide 0x000000ff, 0x2000 /* expect 0x0000 */ + divide 0x000000ff, 0x3fff /* expect 0x0000 */ + divide 0x000000ff, 0x4000 /* expect 0x0000 */ + divide 0x000000ff, 0x7fff /* expect 0x0000 */ + divide 0x00000100, 0x0001 /* expect 0x0100 */ + divide 0x00000100, 0x0002 /* expect 0x0080 */ + divide 0x00000100, 0x0003 /* expect 0x0055 */ + divide 0x00000100, 0x0004 /* expect 0x0040 */ + divide 0x00000100, 0x0007 /* expect 0x0024 */ + divide 0x00000100, 0x0008 /* expect 0x0020 */ + divide 0x00000100, 0x000f /* expect 0x0011 */ + divide 0x00000100, 0x0010 /* expect 0x0010 */ + divide 0x00000100, 0x001f /* expect 0x0008 */ + divide 0x00000100, 0x0020 /* expect 0x0008 */ + divide 0x00000100, 0x003f /* expect 0x0004 */ + divide 0x00000100, 0x0040 /* expect 0x0004 */ + divide 0x00000100, 0x007f /* expect 0x0002 */ + divide 0x00000100, 0x0080 /* expect 0x0002 */ + divide 0x00000100, 0x00ff /* expect 0x0001 */ + divide 0x00000100, 0x0100 /* expect 0x0001 */ + divide 0x00000100, 0x01ff /* expect 0x0000 */ + divide 0x00000100, 0x0200 /* expect 0x0000 */ + divide 0x00000100, 0x03ff /* expect 0x0000 */ + divide 0x00000100, 0x0400 /* expect 0x0000 */ + divide 0x00000100, 0x07ff /* expect 0x0000 */ + divide 0x00000100, 0x0800 /* expect 0x0000 */ + divide 0x00000100, 0x0fff /* expect 0x0000 */ + divide 0x00000100, 0x1000 /* expect 0x0000 */ + divide 0x00000100, 0x1fff /* expect 0x0000 */ + divide 0x00000100, 0x2000 /* expect 0x0000 */ + divide 0x00000100, 0x3fff /* expect 0x0000 */ + divide 0x00000100, 0x4000 /* expect 0x0000 */ + divide 0x00000100, 0x7fff /* expect 0x0000 */ + divide 0x000001ff, 0x0001 /* expect 0x01ff */ + divide 0x000001ff, 0x0002 /* expect 0x00ff */ + divide 0x000001ff, 0x0003 /* expect 0x00aa */ + divide 0x000001ff, 0x0004 /* expect 0x007f */ + divide 0x000001ff, 0x0007 /* expect 0x0049 */ + divide 0x000001ff, 0x0008 /* expect 0x003f */ + divide 0x000001ff, 0x000f /* expect 0x0022 */ + divide 0x000001ff, 0x0010 /* expect 0x001f */ + divide 0x000001ff, 0x001f /* expect 0x0010 */ + divide 0x000001ff, 0x0020 /* expect 0x000f */ + divide 0x000001ff, 0x003f /* expect 0x0008 */ + divide 0x000001ff, 0x0040 /* expect 0x0007 */ + divide 0x000001ff, 0x007f /* expect 0x0004 */ + divide 0x000001ff, 0x0080 /* expect 0x0003 */ + divide 0x000001ff, 0x00ff /* expect 0x0002 */ + divide 0x000001ff, 0x0100 /* expect 0x0001 */ + divide 0x000001ff, 0x01ff /* expect 0x0001 */ + divide 0x000001ff, 0x0200 /* expect 0x0000 */ + divide 0x000001ff, 0x03ff /* expect 0x0000 */ + divide 0x000001ff, 0x0400 /* expect 0x0000 */ + divide 0x000001ff, 0x07ff /* expect 0x0000 */ + divide 0x000001ff, 0x0800 /* expect 0x0000 */ + divide 0x000001ff, 0x0fff /* expect 0x0000 */ + divide 0x000001ff, 0x1000 /* expect 0x0000 */ + divide 0x000001ff, 0x1fff /* expect 0x0000 */ + divide 0x000001ff, 0x2000 /* expect 0x0000 */ + divide 0x000001ff, 0x3fff /* expect 0x0000 */ + divide 0x000001ff, 0x4000 /* expect 0x0000 */ + divide 0x000001ff, 0x7fff /* expect 0x0000 */ + divide 0x00000200, 0x0001 /* expect 0x0200 */ + divide 0x00000200, 0x0002 /* expect 0x0100 */ + divide 0x00000200, 0x0003 /* expect 0x00aa */ + divide 0x00000200, 0x0004 /* expect 0x0080 */ + divide 0x00000200, 0x0007 /* expect 0x0049 */ + divide 0x00000200, 0x0008 /* expect 0x0040 */ + divide 0x00000200, 0x000f /* expect 0x0022 */ + divide 0x00000200, 0x0010 /* expect 0x0020 */ + divide 0x00000200, 0x001f /* expect 0x0010 */ + divide 0x00000200, 0x0020 /* expect 0x0010 */ + divide 0x00000200, 0x003f /* expect 0x0008 */ + divide 0x00000200, 0x0040 /* expect 0x0008 */ + divide 0x00000200, 0x007f /* expect 0x0004 */ + divide 0x00000200, 0x0080 /* expect 0x0004 */ + divide 0x00000200, 0x00ff /* expect 0x0002 */ + divide 0x00000200, 0x0100 /* expect 0x0002 */ + divide 0x00000200, 0x01ff /* expect 0x0001 */ + divide 0x00000200, 0x0200 /* expect 0x0001 */ + divide 0x00000200, 0x03ff /* expect 0x0000 */ + divide 0x00000200, 0x0400 /* expect 0x0000 */ + divide 0x00000200, 0x07ff /* expect 0x0000 */ + divide 0x00000200, 0x0800 /* expect 0x0000 */ + divide 0x00000200, 0x0fff /* expect 0x0000 */ + divide 0x00000200, 0x1000 /* expect 0x0000 */ + divide 0x00000200, 0x1fff /* expect 0x0000 */ + divide 0x00000200, 0x2000 /* expect 0x0000 */ + divide 0x00000200, 0x3fff /* expect 0x0000 */ + divide 0x00000200, 0x4000 /* expect 0x0000 */ + divide 0x00000200, 0x7fff /* expect 0x0000 */ + divide 0x000003ff, 0x0001 /* expect 0x03ff */ + divide 0x000003ff, 0x0002 /* expect 0x01ff */ + divide 0x000003ff, 0x0003 /* expect 0x0155 */ + divide 0x000003ff, 0x0004 /* expect 0x00ff */ + divide 0x000003ff, 0x0007 /* expect 0x0092 */ + divide 0x000003ff, 0x0008 /* expect 0x007f */ + divide 0x000003ff, 0x000f /* expect 0x0044 */ + divide 0x000003ff, 0x0010 /* expect 0x003f */ + divide 0x000003ff, 0x001f /* expect 0x0021 */ + divide 0x000003ff, 0x0020 /* expect 0x001f */ + divide 0x000003ff, 0x003f /* expect 0x0010 */ + divide 0x000003ff, 0x0040 /* expect 0x000f */ + divide 0x000003ff, 0x007f /* expect 0x0008 */ + divide 0x000003ff, 0x0080 /* expect 0x0007 */ + divide 0x000003ff, 0x00ff /* expect 0x0004 */ + divide 0x000003ff, 0x0100 /* expect 0x0003 */ + divide 0x000003ff, 0x01ff /* expect 0x0002 */ + divide 0x000003ff, 0x0200 /* expect 0x0001 */ + divide 0x000003ff, 0x03ff /* expect 0x0001 */ + divide 0x000003ff, 0x0400 /* expect 0x0000 */ + divide 0x000003ff, 0x07ff /* expect 0x0000 */ + divide 0x000003ff, 0x0800 /* expect 0x0000 */ + divide 0x000003ff, 0x0fff /* expect 0x0000 */ + divide 0x000003ff, 0x1000 /* expect 0x0000 */ + divide 0x000003ff, 0x1fff /* expect 0x0000 */ + divide 0x000003ff, 0x2000 /* expect 0x0000 */ + divide 0x000003ff, 0x3fff /* expect 0x0000 */ + divide 0x000003ff, 0x4000 /* expect 0x0000 */ + divide 0x000003ff, 0x7fff /* expect 0x0000 */ + divide 0x00000400, 0x0001 /* expect 0x0400 */ + divide 0x00000400, 0x0002 /* expect 0x0200 */ + divide 0x00000400, 0x0003 /* expect 0x0155 */ + divide 0x00000400, 0x0004 /* expect 0x0100 */ + divide 0x00000400, 0x0007 /* expect 0x0092 */ + divide 0x00000400, 0x0008 /* expect 0x0080 */ + divide 0x00000400, 0x000f /* expect 0x0044 */ + divide 0x00000400, 0x0010 /* expect 0x0040 */ + divide 0x00000400, 0x001f /* expect 0x0021 */ + divide 0x00000400, 0x0020 /* expect 0x0020 */ + divide 0x00000400, 0x003f /* expect 0x0010 */ + divide 0x00000400, 0x0040 /* expect 0x0010 */ + divide 0x00000400, 0x007f /* expect 0x0008 */ + divide 0x00000400, 0x0080 /* expect 0x0008 */ + divide 0x00000400, 0x00ff /* expect 0x0004 */ + divide 0x00000400, 0x0100 /* expect 0x0004 */ + divide 0x00000400, 0x01ff /* expect 0x0002 */ + divide 0x00000400, 0x0200 /* expect 0x0002 */ + divide 0x00000400, 0x03ff /* expect 0x0001 */ + divide 0x00000400, 0x0400 /* expect 0x0001 */ + divide 0x00000400, 0x07ff /* expect 0x0000 */ + divide 0x00000400, 0x0800 /* expect 0x0000 */ + divide 0x00000400, 0x0fff /* expect 0x0000 */ + divide 0x00000400, 0x1000 /* expect 0x0000 */ + divide 0x00000400, 0x1fff /* expect 0x0000 */ + divide 0x00000400, 0x2000 /* expect 0x0000 */ + divide 0x00000400, 0x3fff /* expect 0x0000 */ + divide 0x00000400, 0x4000 /* expect 0x0000 */ + divide 0x00000400, 0x7fff /* expect 0x0000 */ + divide 0x000007ff, 0x0001 /* expect 0x07ff */ + divide 0x000007ff, 0x0002 /* expect 0x03ff */ + divide 0x000007ff, 0x0003 /* expect 0x02aa */ + divide 0x000007ff, 0x0004 /* expect 0x01ff */ + divide 0x000007ff, 0x0007 /* expect 0x0124 */ + divide 0x000007ff, 0x0008 /* expect 0x00ff */ + divide 0x000007ff, 0x000f /* expect 0x0088 */ + divide 0x000007ff, 0x0010 /* expect 0x007f */ + divide 0x000007ff, 0x001f /* expect 0x0042 */ + divide 0x000007ff, 0x0020 /* expect 0x003f */ + divide 0x000007ff, 0x003f /* expect 0x0020 */ + divide 0x000007ff, 0x0040 /* expect 0x001f */ + divide 0x000007ff, 0x007f /* expect 0x0010 */ + divide 0x000007ff, 0x0080 /* expect 0x000f */ + divide 0x000007ff, 0x00ff /* expect 0x0008 */ + divide 0x000007ff, 0x0100 /* expect 0x0007 */ + divide 0x000007ff, 0x01ff /* expect 0x0004 */ + divide 0x000007ff, 0x0200 /* expect 0x0003 */ + divide 0x000007ff, 0x03ff /* expect 0x0002 */ + divide 0x000007ff, 0x0400 /* expect 0x0001 */ + divide 0x000007ff, 0x07ff /* expect 0x0001 */ + divide 0x000007ff, 0x0800 /* expect 0x0000 */ + divide 0x000007ff, 0x0fff /* expect 0x0000 */ + divide 0x000007ff, 0x1000 /* expect 0x0000 */ + divide 0x000007ff, 0x1fff /* expect 0x0000 */ + divide 0x000007ff, 0x2000 /* expect 0x0000 */ + divide 0x000007ff, 0x3fff /* expect 0x0000 */ + divide 0x000007ff, 0x4000 /* expect 0x0000 */ + divide 0x000007ff, 0x7fff /* expect 0x0000 */ + divide 0x00000800, 0x0001 /* expect 0x0800 */ + divide 0x00000800, 0x0002 /* expect 0x0400 */ + divide 0x00000800, 0x0003 /* expect 0x02aa */ + divide 0x00000800, 0x0004 /* expect 0x0200 */ + divide 0x00000800, 0x0007 /* expect 0x0124 */ + divide 0x00000800, 0x0008 /* expect 0x0100 */ + divide 0x00000800, 0x000f /* expect 0x0088 */ + divide 0x00000800, 0x0010 /* expect 0x0080 */ + divide 0x00000800, 0x001f /* expect 0x0042 */ + divide 0x00000800, 0x0020 /* expect 0x0040 */ + divide 0x00000800, 0x003f /* expect 0x0020 */ + divide 0x00000800, 0x0040 /* expect 0x0020 */ + divide 0x00000800, 0x007f /* expect 0x0010 */ + divide 0x00000800, 0x0080 /* expect 0x0010 */ + divide 0x00000800, 0x00ff /* expect 0x0008 */ + divide 0x00000800, 0x0100 /* expect 0x0008 */ + divide 0x00000800, 0x01ff /* expect 0x0004 */ + divide 0x00000800, 0x0200 /* expect 0x0004 */ + divide 0x00000800, 0x03ff /* expect 0x0002 */ + divide 0x00000800, 0x0400 /* expect 0x0002 */ + divide 0x00000800, 0x07ff /* expect 0x0001 */ + divide 0x00000800, 0x0800 /* expect 0x0001 */ + divide 0x00000800, 0x0fff /* expect 0x0000 */ + divide 0x00000800, 0x1000 /* expect 0x0000 */ + divide 0x00000800, 0x1fff /* expect 0x0000 */ + divide 0x00000800, 0x2000 /* expect 0x0000 */ + divide 0x00000800, 0x3fff /* expect 0x0000 */ + divide 0x00000800, 0x4000 /* expect 0x0000 */ + divide 0x00000800, 0x7fff /* expect 0x0000 */ + divide 0x00000fff, 0x0001 /* expect 0x0fff */ + divide 0x00000fff, 0x0002 /* expect 0x07ff */ + divide 0x00000fff, 0x0003 /* expect 0x0555 */ + divide 0x00000fff, 0x0004 /* expect 0x03ff */ + divide 0x00000fff, 0x0007 /* expect 0x0249 */ + divide 0x00000fff, 0x0008 /* expect 0x01ff */ + divide 0x00000fff, 0x000f /* expect 0x0111 */ + divide 0x00000fff, 0x0010 /* expect 0x00ff */ + divide 0x00000fff, 0x001f /* expect 0x0084 */ + divide 0x00000fff, 0x0020 /* expect 0x007f */ + divide 0x00000fff, 0x003f /* expect 0x0041 */ + divide 0x00000fff, 0x0040 /* expect 0x003f */ + divide 0x00000fff, 0x007f /* expect 0x0020 */ + divide 0x00000fff, 0x0080 /* expect 0x001f */ + divide 0x00000fff, 0x00ff /* expect 0x0010 */ + divide 0x00000fff, 0x0100 /* expect 0x000f */ + divide 0x00000fff, 0x01ff /* expect 0x0008 */ + divide 0x00000fff, 0x0200 /* expect 0x0007 */ + divide 0x00000fff, 0x03ff /* expect 0x0004 */ + divide 0x00000fff, 0x0400 /* expect 0x0003 */ + divide 0x00000fff, 0x07ff /* expect 0x0002 */ + divide 0x00000fff, 0x0800 /* expect 0x0001 */ + divide 0x00000fff, 0x0fff /* expect 0x0001 */ + divide 0x00000fff, 0x1000 /* expect 0x0000 */ + divide 0x00000fff, 0x1fff /* expect 0x0000 */ + divide 0x00000fff, 0x2000 /* expect 0x0000 */ + divide 0x00000fff, 0x3fff /* expect 0x0000 */ + divide 0x00000fff, 0x4000 /* expect 0x0000 */ + divide 0x00000fff, 0x7fff /* expect 0x0000 */ + divide 0x00001000, 0x0001 /* expect 0x1000 */ + divide 0x00001000, 0x0002 /* expect 0x0800 */ + divide 0x00001000, 0x0003 /* expect 0x0555 */ + divide 0x00001000, 0x0004 /* expect 0x0400 */ + divide 0x00001000, 0x0007 /* expect 0x0249 */ + divide 0x00001000, 0x0008 /* expect 0x0200 */ + divide 0x00001000, 0x000f /* expect 0x0111 */ + divide 0x00001000, 0x0010 /* expect 0x0100 */ + divide 0x00001000, 0x001f /* expect 0x0084 */ + divide 0x00001000, 0x0020 /* expect 0x0080 */ + divide 0x00001000, 0x003f /* expect 0x0041 */ + divide 0x00001000, 0x0040 /* expect 0x0040 */ + divide 0x00001000, 0x007f /* expect 0x0020 */ + divide 0x00001000, 0x0080 /* expect 0x0020 */ + divide 0x00001000, 0x00ff /* expect 0x0010 */ + divide 0x00001000, 0x0100 /* expect 0x0010 */ + divide 0x00001000, 0x01ff /* expect 0x0008 */ + divide 0x00001000, 0x0200 /* expect 0x0008 */ + divide 0x00001000, 0x03ff /* expect 0x0004 */ + divide 0x00001000, 0x0400 /* expect 0x0004 */ + divide 0x00001000, 0x07ff /* expect 0x0002 */ + divide 0x00001000, 0x0800 /* expect 0x0002 */ + divide 0x00001000, 0x0fff /* expect 0x0001 */ + divide 0x00001000, 0x1000 /* expect 0x0001 */ + divide 0x00001000, 0x1fff /* expect 0x0000 */ + divide 0x00001000, 0x2000 /* expect 0x0000 */ + divide 0x00001000, 0x3fff /* expect 0x0000 */ + divide 0x00001000, 0x4000 /* expect 0x0000 */ + divide 0x00001000, 0x7fff /* expect 0x0000 */ + divide 0x00001fff, 0x0001 /* expect 0x1fff */ + divide 0x00001fff, 0x0002 /* expect 0x0fff */ + divide 0x00001fff, 0x0003 /* expect 0x0aaa */ + divide 0x00001fff, 0x0004 /* expect 0x07ff */ + divide 0x00001fff, 0x0007 /* expect 0x0492 */ + divide 0x00001fff, 0x0008 /* expect 0x03ff */ + divide 0x00001fff, 0x000f /* expect 0x0222 */ + divide 0x00001fff, 0x0010 /* expect 0x01ff */ + divide 0x00001fff, 0x001f /* expect 0x0108 */ + divide 0x00001fff, 0x0020 /* expect 0x00ff */ + divide 0x00001fff, 0x003f /* expect 0x0082 */ + divide 0x00001fff, 0x0040 /* expect 0x007f */ + divide 0x00001fff, 0x007f /* expect 0x0040 */ + divide 0x00001fff, 0x0080 /* expect 0x003f */ + divide 0x00001fff, 0x00ff /* expect 0x0020 */ + divide 0x00001fff, 0x0100 /* expect 0x001f */ + divide 0x00001fff, 0x01ff /* expect 0x0010 */ + divide 0x00001fff, 0x0200 /* expect 0x000f */ + divide 0x00001fff, 0x03ff /* expect 0x0008 */ + divide 0x00001fff, 0x0400 /* expect 0x0007 */ + divide 0x00001fff, 0x07ff /* expect 0x0004 */ + divide 0x00001fff, 0x0800 /* expect 0x0003 */ + divide 0x00001fff, 0x0fff /* expect 0x0002 */ + divide 0x00001fff, 0x1000 /* expect 0x0001 */ + divide 0x00001fff, 0x1fff /* expect 0x0001 */ + divide 0x00001fff, 0x2000 /* expect 0x0000 */ + divide 0x00001fff, 0x3fff /* expect 0x0000 */ + divide 0x00001fff, 0x4000 /* expect 0x0000 */ + divide 0x00001fff, 0x7fff /* expect 0x0000 */ + divide 0x00002000, 0x0001 /* expect 0x2000 */ + divide 0x00002000, 0x0002 /* expect 0x1000 */ + divide 0x00002000, 0x0003 /* expect 0x0aaa */ + divide 0x00002000, 0x0004 /* expect 0x0800 */ + divide 0x00002000, 0x0007 /* expect 0x0492 */ + divide 0x00002000, 0x0008 /* expect 0x0400 */ + divide 0x00002000, 0x000f /* expect 0x0222 */ + divide 0x00002000, 0x0010 /* expect 0x0200 */ + divide 0x00002000, 0x001f /* expect 0x0108 */ + divide 0x00002000, 0x0020 /* expect 0x0100 */ + divide 0x00002000, 0x003f /* expect 0x0082 */ + divide 0x00002000, 0x0040 /* expect 0x0080 */ + divide 0x00002000, 0x007f /* expect 0x0040 */ + divide 0x00002000, 0x0080 /* expect 0x0040 */ + divide 0x00002000, 0x00ff /* expect 0x0020 */ + divide 0x00002000, 0x0100 /* expect 0x0020 */ + divide 0x00002000, 0x01ff /* expect 0x0010 */ + divide 0x00002000, 0x0200 /* expect 0x0010 */ + divide 0x00002000, 0x03ff /* expect 0x0008 */ + divide 0x00002000, 0x0400 /* expect 0x0008 */ + divide 0x00002000, 0x07ff /* expect 0x0004 */ + divide 0x00002000, 0x0800 /* expect 0x0004 */ + divide 0x00002000, 0x0fff /* expect 0x0002 */ + divide 0x00002000, 0x1000 /* expect 0x0002 */ + divide 0x00002000, 0x1fff /* expect 0x0001 */ + divide 0x00002000, 0x2000 /* expect 0x0001 */ + divide 0x00002000, 0x3fff /* expect 0x0000 */ + divide 0x00002000, 0x4000 /* expect 0x0000 */ + divide 0x00002000, 0x7fff /* expect 0x0000 */ + divide 0x00003fff, 0x0001 /* expect 0x3fff */ + divide 0x00003fff, 0x0002 /* expect 0x1fff */ + divide 0x00003fff, 0x0003 /* expect 0x1555 */ + divide 0x00003fff, 0x0004 /* expect 0x0fff */ + divide 0x00003fff, 0x0007 /* expect 0x0924 */ + divide 0x00003fff, 0x0008 /* expect 0x07ff */ + divide 0x00003fff, 0x000f /* expect 0x0444 */ + divide 0x00003fff, 0x0010 /* expect 0x03ff */ + divide 0x00003fff, 0x001f /* expect 0x0210 */ + divide 0x00003fff, 0x0020 /* expect 0x01ff */ + divide 0x00003fff, 0x003f /* expect 0x0104 */ + divide 0x00003fff, 0x0040 /* expect 0x00ff */ + divide 0x00003fff, 0x007f /* expect 0x0081 */ + divide 0x00003fff, 0x0080 /* expect 0x007f */ + divide 0x00003fff, 0x00ff /* expect 0x0040 */ + divide 0x00003fff, 0x0100 /* expect 0x003f */ + divide 0x00003fff, 0x01ff /* expect 0x0020 */ + divide 0x00003fff, 0x0200 /* expect 0x001f */ + divide 0x00003fff, 0x03ff /* expect 0x0010 */ + divide 0x00003fff, 0x0400 /* expect 0x000f */ + divide 0x00003fff, 0x07ff /* expect 0x0008 */ + divide 0x00003fff, 0x0800 /* expect 0x0007 */ + divide 0x00003fff, 0x0fff /* expect 0x0004 */ + divide 0x00003fff, 0x1000 /* expect 0x0003 */ + divide 0x00003fff, 0x1fff /* expect 0x0002 */ + divide 0x00003fff, 0x2000 /* expect 0x0001 */ + divide 0x00003fff, 0x3fff /* expect 0x0001 */ + divide 0x00003fff, 0x4000 /* expect 0x0000 */ + divide 0x00003fff, 0x7fff /* expect 0x0000 */ + divide 0x00004000, 0x0001 /* expect 0x4000 */ + divide 0x00004000, 0x0002 /* expect 0x2000 */ + divide 0x00004000, 0x0003 /* expect 0x1555 */ + divide 0x00004000, 0x0004 /* expect 0x1000 */ + divide 0x00004000, 0x0007 /* expect 0x0924 */ + divide 0x00004000, 0x0008 /* expect 0x0800 */ + divide 0x00004000, 0x000f /* expect 0x0444 */ + divide 0x00004000, 0x0010 /* expect 0x0400 */ + divide 0x00004000, 0x001f /* expect 0x0210 */ + divide 0x00004000, 0x0020 /* expect 0x0200 */ + divide 0x00004000, 0x003f /* expect 0x0104 */ + divide 0x00004000, 0x0040 /* expect 0x0100 */ + divide 0x00004000, 0x007f /* expect 0x0081 */ + divide 0x00004000, 0x0080 /* expect 0x0080 */ + divide 0x00004000, 0x00ff /* expect 0x0040 */ + divide 0x00004000, 0x0100 /* expect 0x0040 */ + divide 0x00004000, 0x01ff /* expect 0x0020 */ + divide 0x00004000, 0x0200 /* expect 0x0020 */ + divide 0x00004000, 0x03ff /* expect 0x0010 */ + divide 0x00004000, 0x0400 /* expect 0x0010 */ + divide 0x00004000, 0x07ff /* expect 0x0008 */ + divide 0x00004000, 0x0800 /* expect 0x0008 */ + divide 0x00004000, 0x0fff /* expect 0x0004 */ + divide 0x00004000, 0x1000 /* expect 0x0004 */ + divide 0x00004000, 0x1fff /* expect 0x0002 */ + divide 0x00004000, 0x2000 /* expect 0x0002 */ + divide 0x00004000, 0x3fff /* expect 0x0001 */ + divide 0x00004000, 0x4000 /* expect 0x0001 */ + divide 0x00004000, 0x7fff /* expect 0x0000 */ + divide 0x00007fff, 0x0001 /* expect 0x7fff */ + divide 0x00007fff, 0x0002 /* expect 0x3fff */ + divide 0x00007fff, 0x0003 /* expect 0x2aaa */ + divide 0x00007fff, 0x0004 /* expect 0x1fff */ + divide 0x00007fff, 0x0007 /* expect 0x1249 */ + divide 0x00007fff, 0x0008 /* expect 0x0fff */ + divide 0x00007fff, 0x000f /* expect 0x0888 */ + divide 0x00007fff, 0x0010 /* expect 0x07ff */ + divide 0x00007fff, 0x001f /* expect 0x0421 */ + divide 0x00007fff, 0x0020 /* expect 0x03ff */ + divide 0x00007fff, 0x003f /* expect 0x0208 */ + divide 0x00007fff, 0x0040 /* expect 0x01ff */ + divide 0x00007fff, 0x007f /* expect 0x0102 */ + divide 0x00007fff, 0x0080 /* expect 0x00ff */ + divide 0x00007fff, 0x00ff /* expect 0x0080 */ + divide 0x00007fff, 0x0100 /* expect 0x007f */ + divide 0x00007fff, 0x01ff /* expect 0x0040 */ + divide 0x00007fff, 0x0200 /* expect 0x003f */ + divide 0x00007fff, 0x03ff /* expect 0x0020 */ + divide 0x00007fff, 0x0400 /* expect 0x001f */ + divide 0x00007fff, 0x07ff /* expect 0x0010 */ + divide 0x00007fff, 0x0800 /* expect 0x000f */ + divide 0x00007fff, 0x0fff /* expect 0x0008 */ + divide 0x00007fff, 0x1000 /* expect 0x0007 */ + divide 0x00007fff, 0x1fff /* expect 0x0004 */ + divide 0x00007fff, 0x2000 /* expect 0x0003 */ + divide 0x00007fff, 0x3fff /* expect 0x0002 */ + divide 0x00007fff, 0x4000 /* expect 0x0001 */ + divide 0x00007fff, 0x7fff /* expect 0x0001 */ + divide 0x00008000, 0x0002 /* expect 0x4000 */ + divide 0x00008000, 0x0003 /* expect 0x2aaa */ + divide 0x00008000, 0x0004 /* expect 0x2000 */ + divide 0x00008000, 0x0007 /* expect 0x1249 */ + divide 0x00008000, 0x0008 /* expect 0x1000 */ + divide 0x00008000, 0x000f /* expect 0x0888 */ + divide 0x00008000, 0x0010 /* expect 0x0800 */ + divide 0x00008000, 0x001f /* expect 0x0421 */ + divide 0x00008000, 0x0020 /* expect 0x0400 */ + divide 0x00008000, 0x003f /* expect 0x0208 */ + divide 0x00008000, 0x0040 /* expect 0x0200 */ + divide 0x00008000, 0x007f /* expect 0x0102 */ + divide 0x00008000, 0x0080 /* expect 0x0100 */ + divide 0x00008000, 0x00ff /* expect 0x0080 */ + divide 0x00008000, 0x0100 /* expect 0x0080 */ + divide 0x00008000, 0x01ff /* expect 0x0040 */ + divide 0x00008000, 0x0200 /* expect 0x0040 */ + divide 0x00008000, 0x03ff /* expect 0x0020 */ + divide 0x00008000, 0x0400 /* expect 0x0020 */ + divide 0x00008000, 0x07ff /* expect 0x0010 */ + divide 0x00008000, 0x0800 /* expect 0x0010 */ + divide 0x00008000, 0x0fff /* expect 0x0008 */ + divide 0x00008000, 0x1000 /* expect 0x0008 */ + divide 0x00008000, 0x1fff /* expect 0x0004 */ + divide 0x00008000, 0x2000 /* expect 0x0004 */ + divide 0x00008000, 0x3fff /* expect 0x0002 */ + divide 0x00008000, 0x4000 /* expect 0x0002 */ + divide 0x00008000, 0x7fff /* expect 0x0001 */ + divide 0x0000ffff, 0x0002 /* expect 0x7fff */ + divide 0x0000ffff, 0x0003 /* expect 0x5555 */ + divide 0x0000ffff, 0x0004 /* expect 0x3fff */ + divide 0x0000ffff, 0x0007 /* expect 0x2492 */ + divide 0x0000ffff, 0x0008 /* expect 0x1fff */ + divide 0x0000ffff, 0x000f /* expect 0x1111 */ + divide 0x0000ffff, 0x0010 /* expect 0x0fff */ + divide 0x0000ffff, 0x001f /* expect 0x0842 */ + divide 0x0000ffff, 0x0020 /* expect 0x07ff */ + divide 0x0000ffff, 0x003f /* expect 0x0410 */ + divide 0x0000ffff, 0x0040 /* expect 0x03ff */ + divide 0x0000ffff, 0x007f /* expect 0x0204 */ + divide 0x0000ffff, 0x0080 /* expect 0x01ff */ + divide 0x0000ffff, 0x00ff /* expect 0x0101 */ + divide 0x0000ffff, 0x0100 /* expect 0x00ff */ + divide 0x0000ffff, 0x01ff /* expect 0x0080 */ + divide 0x0000ffff, 0x0200 /* expect 0x007f */ + divide 0x0000ffff, 0x03ff /* expect 0x0040 */ + divide 0x0000ffff, 0x0400 /* expect 0x003f */ + divide 0x0000ffff, 0x07ff /* expect 0x0020 */ + divide 0x0000ffff, 0x0800 /* expect 0x001f */ + divide 0x0000ffff, 0x0fff /* expect 0x0010 */ + divide 0x0000ffff, 0x1000 /* expect 0x000f */ + divide 0x0000ffff, 0x1fff /* expect 0x0008 */ + divide 0x0000ffff, 0x2000 /* expect 0x0007 */ + divide 0x0000ffff, 0x3fff /* expect 0x0004 */ + divide 0x0000ffff, 0x4000 /* expect 0x0003 */ + divide 0x0000ffff, 0x7fff /* expect 0x0002 */ + divide 0x00010000, 0x0003 /* expect 0x5555 */ + divide 0x00010000, 0x0004 /* expect 0x4000 */ + divide 0x00010000, 0x0007 /* expect 0x2492 */ + divide 0x00010000, 0x0008 /* expect 0x2000 */ + divide 0x00010000, 0x000f /* expect 0x1111 */ + divide 0x00010000, 0x0010 /* expect 0x1000 */ + divide 0x00010000, 0x001f /* expect 0x0842 */ + divide 0x00010000, 0x0020 /* expect 0x0800 */ + divide 0x00010000, 0x003f /* expect 0x0410 */ + divide 0x00010000, 0x0040 /* expect 0x0400 */ + divide 0x00010000, 0x007f /* expect 0x0204 */ + divide 0x00010000, 0x0080 /* expect 0x0200 */ + divide 0x00010000, 0x00ff /* expect 0x0101 */ + divide 0x00010000, 0x0100 /* expect 0x0100 */ + divide 0x00010000, 0x01ff /* expect 0x0080 */ + divide 0x00010000, 0x0200 /* expect 0x0080 */ + divide 0x00010000, 0x03ff /* expect 0x0040 */ + divide 0x00010000, 0x0400 /* expect 0x0040 */ + divide 0x00010000, 0x07ff /* expect 0x0020 */ + divide 0x00010000, 0x0800 /* expect 0x0020 */ + divide 0x00010000, 0x0fff /* expect 0x0010 */ + divide 0x00010000, 0x1000 /* expect 0x0010 */ + divide 0x00010000, 0x1fff /* expect 0x0008 */ + divide 0x00010000, 0x2000 /* expect 0x0008 */ + divide 0x00010000, 0x3fff /* expect 0x0004 */ + divide 0x00010000, 0x4000 /* expect 0x0004 */ + divide 0x00010000, 0x7fff /* expect 0x0002 */ + divide 0x0001ffff, 0x0004 /* expect 0x7fff */ + divide 0x0001ffff, 0x0007 /* expect 0x4924 */ + divide 0x0001ffff, 0x0008 /* expect 0x3fff */ + divide 0x0001ffff, 0x000f /* expect 0x2222 */ + divide 0x0001ffff, 0x0010 /* expect 0x1fff */ + divide 0x0001ffff, 0x001f /* expect 0x1084 */ + divide 0x0001ffff, 0x0020 /* expect 0x0fff */ + divide 0x0001ffff, 0x003f /* expect 0x0820 */ + divide 0x0001ffff, 0x0040 /* expect 0x07ff */ + divide 0x0001ffff, 0x007f /* expect 0x0408 */ + divide 0x0001ffff, 0x0080 /* expect 0x03ff */ + divide 0x0001ffff, 0x00ff /* expect 0x0202 */ + divide 0x0001ffff, 0x0100 /* expect 0x01ff */ + divide 0x0001ffff, 0x01ff /* expect 0x0100 */ + divide 0x0001ffff, 0x0200 /* expect 0x00ff */ + divide 0x0001ffff, 0x03ff /* expect 0x0080 */ + divide 0x0001ffff, 0x0400 /* expect 0x007f */ + divide 0x0001ffff, 0x07ff /* expect 0x0040 */ + divide 0x0001ffff, 0x0800 /* expect 0x003f */ + divide 0x0001ffff, 0x0fff /* expect 0x0020 */ + divide 0x0001ffff, 0x1000 /* expect 0x001f */ + divide 0x0001ffff, 0x1fff /* expect 0x0010 */ + divide 0x0001ffff, 0x2000 /* expect 0x000f */ + divide 0x0001ffff, 0x3fff /* expect 0x0008 */ + divide 0x0001ffff, 0x4000 /* expect 0x0007 */ + divide 0x0001ffff, 0x7fff /* expect 0x0004 */ + divide 0x00020000, 0x0007 /* expect 0x4924 */ + divide 0x00020000, 0x0008 /* expect 0x4000 */ + divide 0x00020000, 0x000f /* expect 0x2222 */ + divide 0x00020000, 0x0010 /* expect 0x2000 */ + divide 0x00020000, 0x001f /* expect 0x1084 */ + divide 0x00020000, 0x0020 /* expect 0x1000 */ + divide 0x00020000, 0x003f /* expect 0x0820 */ + divide 0x00020000, 0x0040 /* expect 0x0800 */ + divide 0x00020000, 0x007f /* expect 0x0408 */ + divide 0x00020000, 0x0080 /* expect 0x0400 */ + divide 0x00020000, 0x00ff /* expect 0x0202 */ + divide 0x00020000, 0x0100 /* expect 0x0200 */ + divide 0x00020000, 0x01ff /* expect 0x0100 */ + divide 0x00020000, 0x0200 /* expect 0x0100 */ + divide 0x00020000, 0x03ff /* expect 0x0080 */ + divide 0x00020000, 0x0400 /* expect 0x0080 */ + divide 0x00020000, 0x07ff /* expect 0x0040 */ + divide 0x00020000, 0x0800 /* expect 0x0040 */ + divide 0x00020000, 0x0fff /* expect 0x0020 */ + divide 0x00020000, 0x1000 /* expect 0x0020 */ + divide 0x00020000, 0x1fff /* expect 0x0010 */ + divide 0x00020000, 0x2000 /* expect 0x0010 */ + divide 0x00020000, 0x3fff /* expect 0x0008 */ + divide 0x00020000, 0x4000 /* expect 0x0008 */ + divide 0x00020000, 0x7fff /* expect 0x0004 */ + divide 0x0003ffff, 0x0008 /* expect 0x7fff */ + divide 0x0003ffff, 0x000f /* expect 0x4444 */ + divide 0x0003ffff, 0x0010 /* expect 0x3fff */ + divide 0x0003ffff, 0x001f /* expect 0x2108 */ + divide 0x0003ffff, 0x0020 /* expect 0x1fff */ + divide 0x0003ffff, 0x003f /* expect 0x1041 */ + divide 0x0003ffff, 0x0040 /* expect 0x0fff */ + divide 0x0003ffff, 0x007f /* expect 0x0810 */ + divide 0x0003ffff, 0x0080 /* expect 0x07ff */ + divide 0x0003ffff, 0x00ff /* expect 0x0404 */ + divide 0x0003ffff, 0x0100 /* expect 0x03ff */ + divide 0x0003ffff, 0x01ff /* expect 0x0201 */ + divide 0x0003ffff, 0x0200 /* expect 0x01ff */ + divide 0x0003ffff, 0x03ff /* expect 0x0100 */ + divide 0x0003ffff, 0x0400 /* expect 0x00ff */ + divide 0x0003ffff, 0x07ff /* expect 0x0080 */ + divide 0x0003ffff, 0x0800 /* expect 0x007f */ + divide 0x0003ffff, 0x0fff /* expect 0x0040 */ + divide 0x0003ffff, 0x1000 /* expect 0x003f */ + divide 0x0003ffff, 0x1fff /* expect 0x0020 */ + divide 0x0003ffff, 0x2000 /* expect 0x001f */ + divide 0x0003ffff, 0x3fff /* expect 0x0010 */ + divide 0x0003ffff, 0x4000 /* expect 0x000f */ + divide 0x0003ffff, 0x7fff /* expect 0x0008 */ + divide 0x00040000, 0x000f /* expect 0x4444 */ + divide 0x00040000, 0x0010 /* expect 0x4000 */ + divide 0x00040000, 0x001f /* expect 0x2108 */ + divide 0x00040000, 0x0020 /* expect 0x2000 */ + divide 0x00040000, 0x003f /* expect 0x1041 */ + divide 0x00040000, 0x0040 /* expect 0x1000 */ + divide 0x00040000, 0x007f /* expect 0x0810 */ + divide 0x00040000, 0x0080 /* expect 0x0800 */ + divide 0x00040000, 0x00ff /* expect 0x0404 */ + divide 0x00040000, 0x0100 /* expect 0x0400 */ + divide 0x00040000, 0x01ff /* expect 0x0201 */ + divide 0x00040000, 0x0200 /* expect 0x0200 */ + divide 0x00040000, 0x03ff /* expect 0x0100 */ + divide 0x00040000, 0x0400 /* expect 0x0100 */ + divide 0x00040000, 0x07ff /* expect 0x0080 */ + divide 0x00040000, 0x0800 /* expect 0x0080 */ + divide 0x00040000, 0x0fff /* expect 0x0040 */ + divide 0x00040000, 0x1000 /* expect 0x0040 */ + divide 0x00040000, 0x1fff /* expect 0x0020 */ + divide 0x00040000, 0x2000 /* expect 0x0020 */ + divide 0x00040000, 0x3fff /* expect 0x0010 */ + divide 0x00040000, 0x4000 /* expect 0x0010 */ + divide 0x00040000, 0x7fff /* expect 0x0008 */ + divide 0x0007ffff, 0x0010 /* expect 0x7fff */ + divide 0x0007ffff, 0x001f /* expect 0x4210 */ + divide 0x0007ffff, 0x0020 /* expect 0x3fff */ + divide 0x0007ffff, 0x003f /* expect 0x2082 */ + divide 0x0007ffff, 0x0040 /* expect 0x1fff */ + divide 0x0007ffff, 0x007f /* expect 0x1020 */ + divide 0x0007ffff, 0x0080 /* expect 0x0fff */ + divide 0x0007ffff, 0x00ff /* expect 0x0808 */ + divide 0x0007ffff, 0x0100 /* expect 0x07ff */ + divide 0x0007ffff, 0x01ff /* expect 0x0402 */ + divide 0x0007ffff, 0x0200 /* expect 0x03ff */ + divide 0x0007ffff, 0x03ff /* expect 0x0200 */ + divide 0x0007ffff, 0x0400 /* expect 0x01ff */ + divide 0x0007ffff, 0x07ff /* expect 0x0100 */ + divide 0x0007ffff, 0x0800 /* expect 0x00ff */ + divide 0x0007ffff, 0x0fff /* expect 0x0080 */ + divide 0x0007ffff, 0x1000 /* expect 0x007f */ + divide 0x0007ffff, 0x1fff /* expect 0x0040 */ + divide 0x0007ffff, 0x2000 /* expect 0x003f */ + divide 0x0007ffff, 0x3fff /* expect 0x0020 */ + divide 0x0007ffff, 0x4000 /* expect 0x001f */ + divide 0x0007ffff, 0x7fff /* expect 0x0010 */ + divide 0x00080000, 0x001f /* expect 0x4210 */ + divide 0x00080000, 0x0020 /* expect 0x4000 */ + divide 0x00080000, 0x003f /* expect 0x2082 */ + divide 0x00080000, 0x0040 /* expect 0x2000 */ + divide 0x00080000, 0x007f /* expect 0x1020 */ + divide 0x00080000, 0x0080 /* expect 0x1000 */ + divide 0x00080000, 0x00ff /* expect 0x0808 */ + divide 0x00080000, 0x0100 /* expect 0x0800 */ + divide 0x00080000, 0x01ff /* expect 0x0402 */ + divide 0x00080000, 0x0200 /* expect 0x0400 */ + divide 0x00080000, 0x03ff /* expect 0x0200 */ + divide 0x00080000, 0x0400 /* expect 0x0200 */ + divide 0x00080000, 0x07ff /* expect 0x0100 */ + divide 0x00080000, 0x0800 /* expect 0x0100 */ + divide 0x00080000, 0x0fff /* expect 0x0080 */ + divide 0x00080000, 0x1000 /* expect 0x0080 */ + divide 0x00080000, 0x1fff /* expect 0x0040 */ + divide 0x00080000, 0x2000 /* expect 0x0040 */ + divide 0x00080000, 0x3fff /* expect 0x0020 */ + divide 0x00080000, 0x4000 /* expect 0x0020 */ + divide 0x00080000, 0x7fff /* expect 0x0010 */ + divide 0x000fffff, 0x0020 /* expect 0x7fff */ + divide 0x000fffff, 0x003f /* expect 0x4104 */ + divide 0x000fffff, 0x0040 /* expect 0x3fff */ + divide 0x000fffff, 0x007f /* expect 0x2040 */ + divide 0x000fffff, 0x0080 /* expect 0x1fff */ + divide 0x000fffff, 0x00ff /* expect 0x1010 */ + divide 0x000fffff, 0x0100 /* expect 0x0fff */ + divide 0x000fffff, 0x01ff /* expect 0x0804 */ + divide 0x000fffff, 0x0200 /* expect 0x07ff */ + divide 0x000fffff, 0x03ff /* expect 0x0401 */ + divide 0x000fffff, 0x0400 /* expect 0x03ff */ + divide 0x000fffff, 0x07ff /* expect 0x0200 */ + divide 0x000fffff, 0x0800 /* expect 0x01ff */ + divide 0x000fffff, 0x0fff /* expect 0x0100 */ + divide 0x000fffff, 0x1000 /* expect 0x00ff */ + divide 0x000fffff, 0x1fff /* expect 0x0080 */ + divide 0x000fffff, 0x2000 /* expect 0x007f */ + divide 0x000fffff, 0x3fff /* expect 0x0040 */ + divide 0x000fffff, 0x4000 /* expect 0x003f */ + divide 0x000fffff, 0x7fff /* expect 0x0020 */ + divide 0x00100000, 0x003f /* expect 0x4104 */ + divide 0x00100000, 0x0040 /* expect 0x4000 */ + divide 0x00100000, 0x007f /* expect 0x2040 */ + divide 0x00100000, 0x0080 /* expect 0x2000 */ + divide 0x00100000, 0x00ff /* expect 0x1010 */ + divide 0x00100000, 0x0100 /* expect 0x1000 */ + divide 0x00100000, 0x01ff /* expect 0x0804 */ + divide 0x00100000, 0x0200 /* expect 0x0800 */ + divide 0x00100000, 0x03ff /* expect 0x0401 */ + divide 0x00100000, 0x0400 /* expect 0x0400 */ + divide 0x00100000, 0x07ff /* expect 0x0200 */ + divide 0x00100000, 0x0800 /* expect 0x0200 */ + divide 0x00100000, 0x0fff /* expect 0x0100 */ + divide 0x00100000, 0x1000 /* expect 0x0100 */ + divide 0x00100000, 0x1fff /* expect 0x0080 */ + divide 0x00100000, 0x2000 /* expect 0x0080 */ + divide 0x00100000, 0x3fff /* expect 0x0040 */ + divide 0x00100000, 0x4000 /* expect 0x0040 */ + divide 0x00100000, 0x7fff /* expect 0x0020 */ + divide 0x001fffff, 0x0040 /* expect 0x7fff */ + divide 0x001fffff, 0x007f /* expect 0x4081 */ + divide 0x001fffff, 0x0080 /* expect 0x3fff */ + divide 0x001fffff, 0x00ff /* expect 0x2020 */ + divide 0x001fffff, 0x0100 /* expect 0x1fff */ + divide 0x001fffff, 0x01ff /* expect 0x1008 */ + divide 0x001fffff, 0x0200 /* expect 0x0fff */ + divide 0x001fffff, 0x03ff /* expect 0x0802 */ + divide 0x001fffff, 0x0400 /* expect 0x07ff */ + divide 0x001fffff, 0x07ff /* expect 0x0400 */ + divide 0x001fffff, 0x0800 /* expect 0x03ff */ + divide 0x001fffff, 0x0fff /* expect 0x0200 */ + divide 0x001fffff, 0x1000 /* expect 0x01ff */ + divide 0x001fffff, 0x1fff /* expect 0x0100 */ + divide 0x001fffff, 0x2000 /* expect 0x00ff */ + divide 0x001fffff, 0x3fff /* expect 0x0080 */ + divide 0x001fffff, 0x4000 /* expect 0x007f */ + divide 0x001fffff, 0x7fff /* expect 0x0040 */ + divide 0x00200000, 0x007f /* expect 0x4081 */ + divide 0x00200000, 0x0080 /* expect 0x4000 */ + divide 0x00200000, 0x00ff /* expect 0x2020 */ + divide 0x00200000, 0x0100 /* expect 0x2000 */ + divide 0x00200000, 0x01ff /* expect 0x1008 */ + divide 0x00200000, 0x0200 /* expect 0x1000 */ + divide 0x00200000, 0x03ff /* expect 0x0802 */ + divide 0x00200000, 0x0400 /* expect 0x0800 */ + divide 0x00200000, 0x07ff /* expect 0x0400 */ + divide 0x00200000, 0x0800 /* expect 0x0400 */ + divide 0x00200000, 0x0fff /* expect 0x0200 */ + divide 0x00200000, 0x1000 /* expect 0x0200 */ + divide 0x00200000, 0x1fff /* expect 0x0100 */ + divide 0x00200000, 0x2000 /* expect 0x0100 */ + divide 0x00200000, 0x3fff /* expect 0x0080 */ + divide 0x00200000, 0x4000 /* expect 0x0080 */ + divide 0x00200000, 0x7fff /* expect 0x0040 */ + divide 0x003fffff, 0x0080 /* expect 0x7fff */ + divide 0x003fffff, 0x00ff /* expect 0x4040 */ + divide 0x003fffff, 0x0100 /* expect 0x3fff */ + divide 0x003fffff, 0x01ff /* expect 0x2010 */ + divide 0x003fffff, 0x0200 /* expect 0x1fff */ + divide 0x003fffff, 0x03ff /* expect 0x1004 */ + divide 0x003fffff, 0x0400 /* expect 0x0fff */ + divide 0x003fffff, 0x07ff /* expect 0x0801 */ + divide 0x003fffff, 0x0800 /* expect 0x07ff */ + divide 0x003fffff, 0x0fff /* expect 0x0400 */ + divide 0x003fffff, 0x1000 /* expect 0x03ff */ + divide 0x003fffff, 0x1fff /* expect 0x0200 */ + divide 0x003fffff, 0x2000 /* expect 0x01ff */ + divide 0x003fffff, 0x3fff /* expect 0x0100 */ + divide 0x003fffff, 0x4000 /* expect 0x00ff */ + divide 0x003fffff, 0x7fff /* expect 0x0080 */ + divide 0x00400000, 0x00ff /* expect 0x4040 */ + divide 0x00400000, 0x0100 /* expect 0x4000 */ + divide 0x00400000, 0x01ff /* expect 0x2010 */ + divide 0x00400000, 0x0200 /* expect 0x2000 */ + divide 0x00400000, 0x03ff /* expect 0x1004 */ + divide 0x00400000, 0x0400 /* expect 0x1000 */ + divide 0x00400000, 0x07ff /* expect 0x0801 */ + divide 0x00400000, 0x0800 /* expect 0x0800 */ + divide 0x00400000, 0x0fff /* expect 0x0400 */ + divide 0x00400000, 0x1000 /* expect 0x0400 */ + divide 0x00400000, 0x1fff /* expect 0x0200 */ + divide 0x00400000, 0x2000 /* expect 0x0200 */ + divide 0x00400000, 0x3fff /* expect 0x0100 */ + divide 0x00400000, 0x4000 /* expect 0x0100 */ + divide 0x00400000, 0x7fff /* expect 0x0080 */ + divide 0x007fffff, 0x0100 /* expect 0x7fff */ + divide 0x007fffff, 0x01ff /* expect 0x4020 */ + divide 0x007fffff, 0x0200 /* expect 0x3fff */ + divide 0x007fffff, 0x03ff /* expect 0x2008 */ + divide 0x007fffff, 0x0400 /* expect 0x1fff */ + divide 0x007fffff, 0x07ff /* expect 0x1002 */ + divide 0x007fffff, 0x0800 /* expect 0x0fff */ + divide 0x007fffff, 0x0fff /* expect 0x0800 */ + divide 0x007fffff, 0x1000 /* expect 0x07ff */ + divide 0x007fffff, 0x1fff /* expect 0x0400 */ + divide 0x007fffff, 0x2000 /* expect 0x03ff */ + divide 0x007fffff, 0x3fff /* expect 0x0200 */ + divide 0x007fffff, 0x4000 /* expect 0x01ff */ + divide 0x007fffff, 0x7fff /* expect 0x0100 */ + divide 0x00800000, 0x01ff /* expect 0x4020 */ + divide 0x00800000, 0x0200 /* expect 0x4000 */ + divide 0x00800000, 0x03ff /* expect 0x2008 */ + divide 0x00800000, 0x0400 /* expect 0x2000 */ + divide 0x00800000, 0x07ff /* expect 0x1002 */ + divide 0x00800000, 0x0800 /* expect 0x1000 */ + divide 0x00800000, 0x0fff /* expect 0x0800 */ + divide 0x00800000, 0x1000 /* expect 0x0800 */ + divide 0x00800000, 0x1fff /* expect 0x0400 */ + divide 0x00800000, 0x2000 /* expect 0x0400 */ + divide 0x00800000, 0x3fff /* expect 0x0200 */ + divide 0x00800000, 0x4000 /* expect 0x0200 */ + divide 0x00800000, 0x7fff /* expect 0x0100 */ + divide 0x00ffffff, 0x0200 /* expect 0x7fff */ + divide 0x00ffffff, 0x03ff /* expect 0x4010 */ + divide 0x00ffffff, 0x0400 /* expect 0x3fff */ + divide 0x00ffffff, 0x07ff /* expect 0x2004 */ + divide 0x00ffffff, 0x0800 /* expect 0x1fff */ + divide 0x00ffffff, 0x0fff /* expect 0x1001 */ + divide 0x00ffffff, 0x1000 /* expect 0x0fff */ + divide 0x00ffffff, 0x1fff /* expect 0x0800 */ + divide 0x00ffffff, 0x2000 /* expect 0x07ff */ + divide 0x00ffffff, 0x3fff /* expect 0x0400 */ + divide 0x00ffffff, 0x4000 /* expect 0x03ff */ + divide 0x00ffffff, 0x7fff /* expect 0x0200 */ + divide 0x01000000, 0x03ff /* expect 0x4010 */ + divide 0x01000000, 0x0400 /* expect 0x4000 */ + divide 0x01000000, 0x07ff /* expect 0x2004 */ + divide 0x01000000, 0x0800 /* expect 0x2000 */ + divide 0x01000000, 0x0fff /* expect 0x1001 */ + divide 0x01000000, 0x1000 /* expect 0x1000 */ + divide 0x01000000, 0x1fff /* expect 0x0800 */ + divide 0x01000000, 0x2000 /* expect 0x0800 */ + divide 0x01000000, 0x3fff /* expect 0x0400 */ + divide 0x01000000, 0x4000 /* expect 0x0400 */ + divide 0x01000000, 0x7fff /* expect 0x0200 */ + divide 0x01ffffff, 0x0400 /* expect 0x7fff */ + divide 0x01ffffff, 0x07ff /* expect 0x4008 */ + divide 0x01ffffff, 0x0800 /* expect 0x3fff */ + divide 0x01ffffff, 0x0fff /* expect 0x2002 */ + divide 0x01ffffff, 0x1000 /* expect 0x1fff */ + divide 0x01ffffff, 0x1fff /* expect 0x1000 */ + divide 0x01ffffff, 0x2000 /* expect 0x0fff */ + divide 0x01ffffff, 0x3fff /* expect 0x0800 */ + divide 0x01ffffff, 0x4000 /* expect 0x07ff */ + divide 0x01ffffff, 0x7fff /* expect 0x0400 */ + divide 0x02000000, 0x07ff /* expect 0x4008 */ + divide 0x02000000, 0x0800 /* expect 0x4000 */ + divide 0x02000000, 0x0fff /* expect 0x2002 */ + divide 0x02000000, 0x1000 /* expect 0x2000 */ + divide 0x02000000, 0x1fff /* expect 0x1000 */ + divide 0x02000000, 0x2000 /* expect 0x1000 */ + divide 0x02000000, 0x3fff /* expect 0x0800 */ + divide 0x02000000, 0x4000 /* expect 0x0800 */ + divide 0x02000000, 0x7fff /* expect 0x0400 */ + divide 0x03ffffff, 0x0800 /* expect 0x7fff */ + divide 0x03ffffff, 0x0fff /* expect 0x4004 */ + divide 0x03ffffff, 0x1000 /* expect 0x3fff */ + divide 0x03ffffff, 0x1fff /* expect 0x2001 */ + divide 0x03ffffff, 0x2000 /* expect 0x1fff */ + divide 0x03ffffff, 0x3fff /* expect 0x1000 */ + divide 0x03ffffff, 0x4000 /* expect 0x0fff */ + divide 0x03ffffff, 0x7fff /* expect 0x0800 */ + divide 0x04000000, 0x0fff /* expect 0x4004 */ + divide 0x04000000, 0x1000 /* expect 0x4000 */ + divide 0x04000000, 0x1fff /* expect 0x2001 */ + divide 0x04000000, 0x2000 /* expect 0x2000 */ + divide 0x04000000, 0x3fff /* expect 0x1000 */ + divide 0x04000000, 0x4000 /* expect 0x1000 */ + divide 0x04000000, 0x7fff /* expect 0x0800 */ + divide 0x07ffffff, 0x1000 /* expect 0x7fff */ + divide 0x07ffffff, 0x1fff /* expect 0x4002 */ + divide 0x07ffffff, 0x2000 /* expect 0x3fff */ + divide 0x07ffffff, 0x3fff /* expect 0x2000 */ + divide 0x07ffffff, 0x4000 /* expect 0x1fff */ + divide 0x07ffffff, 0x7fff /* expect 0x1000 */ + divide 0x08000000, 0x1fff /* expect 0x4002 */ + divide 0x08000000, 0x2000 /* expect 0x4000 */ + divide 0x08000000, 0x3fff /* expect 0x2000 */ + divide 0x08000000, 0x4000 /* expect 0x2000 */ + divide 0x08000000, 0x7fff /* expect 0x1000 */ + divide 0x0fffffff, 0x2000 /* expect 0x7fff */ + divide 0x0fffffff, 0x3fff /* expect 0x4001 */ + divide 0x0fffffff, 0x4000 /* expect 0x3fff */ + divide 0x0fffffff, 0x7fff /* expect 0x2000 */ + divide 0x10000000, 0x3fff /* expect 0x4001 */ + divide 0x10000000, 0x4000 /* expect 0x4000 */ + divide 0x10000000, 0x7fff /* expect 0x2000 */ + divide 0x1fffffff, 0x4000 /* expect 0x7fff */ + divide 0x1fffffff, 0x7fff /* expect 0x4000 */ + divide 0x20000000, 0x7fff /* expect 0x4000 */ + + pass diff --git a/tests/tcg/bfin/dotproduct.s b/tests/tcg/bfin/dotproduct.s new file mode 100644 index 0000000000000..bfae5458f8d61 --- /dev/null +++ b/tests/tcg/bfin/dotproduct.s @@ -0,0 +1,304 @@ +# Blackfin testcase for a simple vector dot product using hard +# wired input buffers of 128 samples each. These values are in +# 1.15 signed . + +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, _buf0 + loadsym P1, _buf1 + + /* loop control + * number of loop iterations is 2^N with r4|=1<>= 0x1; + + _DBG R0; + R7 = ASTAT; + _DBG R7; + +//DBGA ( R7.H , 0x0000 ); +//DBGA ( R7.L , 0x0000 ); + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + R0.H = 0; + R0.L = 1; + R0 <<= 0x1f; + + _DBG R0; + R7 = ASTAT; + _DBG R7; +//DBGA ( R7.H , 0x0000 ); +//DBGA ( R7.L , 0x0002 ); + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 1); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + R1.L = -1; + R1.H = 32767; + R0 = 31; + R1 >>= R0; + + _DBG R1; + R7 = ASTAT; + _DBG R7; +//DBGA ( R7.H , 0x0000 ); +//DBGA ( R7.L , 0x0001 ); + cc = az; + r0 = cc; + dbga( r0.l, 1); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/tests/tcg/bfin/issue89.s b/tests/tcg/bfin/issue89.s new file mode 100644 index 0000000000000..24d051792cfbc --- /dev/null +++ b/tests/tcg/bfin/issue89.s @@ -0,0 +1,30 @@ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + R2.L = 0x000f; + R2.H = 0x038c; + _DBG R2; + + R7.L = 0x007c; + R7.H = 0x0718; + A0 = 0; + A0.w = R7; + _DBG A0; + + A0 = ROT A0 BY R2.L; + + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x003e ); + DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0xffff ); + DBGA ( R5.L , 0xff8c ); + + pass diff --git a/tests/tcg/bfin/l0.s b/tests/tcg/bfin/l0.s new file mode 100644 index 0000000000000..88fcb59149c67 --- /dev/null +++ b/tests/tcg/bfin/l0.s @@ -0,0 +1,137 @@ +// simple test to ensure that we can load data from memory. +# mach: bfin + +.include "testutils.inc" + start + + loadsym P0, tab; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + R6 = [ P0 ++ ]; + R7 = [ P0 ++ ]; + + DBGA ( R0.H , 0x1111 ); + DBGA ( R1.H , 0x2222 ); + DBGA ( R2.H , 0x3333 ); + DBGA ( R3.H , 0x4444 ); + DBGA ( R4.H , 0x5555 ); + DBGA ( R5.H , 0x6666 ); + DBGA ( R6.H , 0x7777 ); + DBGA ( R7.H , 0x8888 ); + + loadsym P0, tab2; + + R0 = W [ P0 ++ ] (Z); + DBGA ( R0.L , 0x1111 ); + + R1 = W [ P0 ++ ] (Z); + DBGA ( R1.L , 0x8888 ); + + R2 = W [ P0 ++ ] (Z); + DBGA ( R2.L , 0x2222 ); + + R3 = W [ P0 ++ ] (Z); + DBGA ( R3.L , 0x7777 ); + + R4 = W [ P0 ++ ] (Z); + DBGA ( R4.L , 0x3333 ); + + R5 = W [ P0 ++ ] (Z); + DBGA ( R5.L , 0x6666 ); + + R0 = B [ P0 ++ ] (Z); + DBGA ( R0.L , 0x44 ); + R1 = B [ P0 ++ ] (Z); + DBGA ( R1.L , 0x44 ); + R2 = B [ P0 ++ ] (Z); + DBGA ( R2.L , 0x55 ); + R3 = B [ P0 ++ ] (Z); + DBGA ( R3.L , 0x55 ); + + R0 = B [ P0 ++ ] (X); + DBGA ( R0.L , 0x55 ); + + R1 = B [ P0 ++ ] (X); + DBGA ( R1.L , 0x55 ); + + R0 = W [ P0 ++ ] (X); + DBGA ( R0.L , 0x4444 ); + + R1 = [ P0 ++ ]; + DBGA ( R1.L , 0x6666 ); + DBGA ( R1.H , 0x3333 ); + + P1 = [ P0 ++ ]; + R0 = P1; + DBGA ( R0.L , 0x7777 ); + DBGA ( R0.H , 0x2222 ); + + P1 = [ P0 ++ ]; + R0 = P1; + DBGA ( R0.L , 0x8888 ); + DBGA ( R0.H , 0x1111 ); + + loadsym P5, tab3; + + R0 = B [ P5 ++ ] (X); + DBGA ( R0.H , 0 ); + DBGA ( R0.L , 0 ); + + R0 = B [ P5 ++ ] (X); + DBGA ( R0.H , 0xffff ); + DBGA ( R0.L , 0xffff ); + + R1 = W [ P5 ++ ] (X); + DBGA ( R1.H , 0xffff ); + DBGA ( R1.L , 0xffff ); + + pass + + .data +tab: + .dw 0 + .dw 0x1111 + .dw 0 + .dw 0x2222 + .dw 0 + .dw 0x3333 + .dw 0 + .dw 0x4444 + .dw 0 + .dw 0x5555 + .dw 0 + .dw 0x6666 + .dw 0 + .dw 0x7777 + .dw 0 + .dw 0x8888 + .dw 0 + .dw 0 + .dw 0 + .dw 0 + +tab2: + .dw 0x1111 + .dw 0x8888 + .dw 0x2222 + .dw 0x7777 + .dw 0x3333 + .dw 0x6666 + .dw 0x4444 + .dw 0x5555 + .dw 0x5555 + .dw 0x4444 + .dw 0x6666 + .dw 0x3333 + .dw 0x7777 + .dw 0x2222 + .dw 0x8888 + .dw 0x1111 + +tab3: + .dw 0xff00 + .dw 0xffff diff --git a/tests/tcg/bfin/l0shift.s b/tests/tcg/bfin/l0shift.s new file mode 100644 index 0000000000000..3f5dc2c54947f --- /dev/null +++ b/tests/tcg/bfin/l0shift.s @@ -0,0 +1,13 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r5 = 0; + r2.L = 0xadbd; + r2.h = 0xfedc; + r5 = r2 >> 0; + dbga (r5.l, 0xadbd); + dbga (r5.h, 0xfedc); + pass diff --git a/tests/tcg/bfin/l2_loop.s b/tests/tcg/bfin/l2_loop.s new file mode 100644 index 0000000000000..a6cde541aee1e --- /dev/null +++ b/tests/tcg/bfin/l2_loop.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + p0=10; + loadsym i0, foo; + + R2 = i0; + r0.l = 0x5678; + r0.h = 0x1234; + + lsetup(lstart, lend) lc0=p0; + +lstart: + [i0++] = r0; +lend: + [i0++] = r0; + + r0=i0; + R0 = R0 - R2; + dbga(r0.l, 0x0050); + + pass + + .data +foo: + .space (0x100) diff --git a/tests/tcg/bfin/link-2.s b/tests/tcg/bfin/link-2.s new file mode 100644 index 0000000000000..ac711c6646952 --- /dev/null +++ b/tests/tcg/bfin/link-2.s @@ -0,0 +1,24 @@ +# Blackfin testcase for link/unlink instructions +# mach: bfin + + .include "testutils.inc" + + start + + /* Make sure size arg to LINK works */ + R0 = SP; + LINK 0x20; + R1 = SP; + R1 += 0x8 + 0x20; + CC = R1 == R0; + IF !CC JUMP 1f; + + /* Make sure UNLINK restores old SP */ + UNLINK + R1 = SP; + CC = R1 == R0; + IF !CC JUMP 1f; + + pass +1: + fail diff --git a/tests/tcg/bfin/link.s b/tests/tcg/bfin/link.s new file mode 100644 index 0000000000000..c92ae1bb00d43 --- /dev/null +++ b/tests/tcg/bfin/link.s @@ -0,0 +1,67 @@ +# Blackfin testcase for link/unlink instructions +# mach: bfin + + .include "testutils.inc" + + start + + /* give FP/RETS known/different values */ + R7.H = 0xdead; + R7.L = 0x1234; + RETS = R7; + R6 = R7; + R6 += 0x23; + FP = R6; + + /* SP should have moved by -8 bytes (to push FP/RETS) */ + R0 = SP; + LINK 0; + R1 = SP; + R1 += 8; + CC = R0 == R1; + IF !CC JUMP 1f; + + /* FP should now have the same value as SP */ + R1 = SP; + R2 = FP; + CC = R1 == R2; + IF !CC JUMP 1f; + + /* make sure FP/RETS on the stack have our known values */ + R1 = [SP]; + CC = R1 == R6; + IF !CC JUMP 1f; + + R1 = [SP + 4]; + CC = R1 == R7; + IF !CC JUMP 1f; + + /* UNLINK should: + * assign SP to current FP + * adjust SP by -8 bytes + * restore RETS/FP from the stack + */ + R4 = 0; + RETS = R4; + R0 = SP; + UNLINK; + + /* Check new SP */ + R1 = SP; + R1 += -0x8; + CC = R1 == R0; + IF !CC JUMP 1f; + + /* Check restored RETS */ + R1 = RETS; + CC = R1 == R7; + IF !CC JUMP 1f; + + /* Check restored FP */ + R1 = FP; + CC = R1 == R6; + IF !CC JUMP 1f; + + pass +1: + fail diff --git a/tests/tcg/bfin/load.s b/tests/tcg/bfin/load.s new file mode 100644 index 0000000000000..2fca3def2ccfd --- /dev/null +++ b/tests/tcg/bfin/load.s @@ -0,0 +1,239 @@ +# Blackfin testcase for register load instructions +# mach: bfin + + + .include "testutils.inc" + + start + + .macro load32 num:req, reg0:req, reg1:req + imm32 \reg0 \num + imm32 \reg1 \num + CC = \reg0 == \reg1 + if CC jump 2f; + fail +2: + .endm + + .macro load32p num:req preg:req + imm32 r0 \num + imm32 \preg \num + r1 = \preg + cc = r0 == r1 + if CC jump 3f; + fail +3: + imm32 \preg 0 + .endm + + .macro load16z num:req reg0:req reg1:req + \reg0 = \num (Z); + imm32 \reg1 \num + CC = \reg0 == \reg1 + if CC jump 4f; + fail +4: + .endm + + .macro load16zp num:req reg:req + \reg = \num (Z); + imm32 r1 \num; + r0 = \reg; + cc = r0 == r1 + if CC jump 5f; + fail +5: + .endm + + .macro load16x num:req reg0:req reg1:req + \reg0 = \num (X); + imm32 \reg1, \num + CC = \reg0 == \reg1 + if CC jump 6f; + fail +6: + .endm + + /* Clobbers R0 */ + .macro loadinc preg0:req, preg1:req, dreg:req + loadsym \preg0, _buf + \preg1 = \preg0; + \dreg = \preg0; + [\preg0\()++] = \preg0; + \dreg += 4; + R0 = \preg0; + CC = \dreg == R0; + if CC jump 7f; + fail +7: + R0 = [ \preg1\() ]; + \dreg += -4; + CC = \dreg == R0; + if CC jump 8f; + fail +8: + .endm + + /* test a bunch of values */ + + /* load_immediate (Half-Word Load) + * register = constant + * reg_lo = uimm16; + * reg_hi = uimm16; + */ + + load32 0 R0 R1 + load32 0xFFFFFFFF R0 R1 + load32 0x55aaaa55 r0 r1 + load32 0x12345678 r0 r1 + load32 0x12345678 R0 R2 + load32 0x23456789 R0 R3 + load32 0x3456789a R0 R4 + load32 0x456789ab R0 R5 + load32 0x56789abc R0 R6 + load32 0x6789abcd R0 R7 + load32 0x789abcde R0 R0 + load32 0x89abcdef R1 R0 + load32 0x9abcdef0 R2 R0 + load32 0xabcdef01 R3 R0 + load32 0xbcdef012 R4 R0 + load32 0xcdef0123 R5 R0 + load32 0xdef01234 R6 R0 + load32 0xef012345 R7 R0 + + load32p 0xf0123456 P0 + load32p 0x01234567 P1 + load32p 0x12345678 P2 +.ifndef BFIN_HOST + load32p 0x23456789 P3 +.endif + load32p 0x3456789a P4 + load32p 0x456789ab P5 + load32p 0x56789abc SP + load32p 0x6789abcd FP + + load32p 0x789abcde I0 + load32p 0x89abcdef I1 + load32p 0x9abcdef0 I2 + load32p 0xabcdef01 I3 + load32p 0xbcdef012 M0 + load32p 0xcdef0123 M1 + load32p 0xdef01234 M2 + load32p 0xef012345 M3 + + load32p 0xf0123456 B0 + load32p 0x01234567 B1 + load32p 0x12345678 B2 + load32p 0x23456789 B3 + load32p 0x3456789a L0 + load32p 0x456789ab L1 + load32p 0x56789abc L2 + load32p 0x6789abcd L3 + + /* Zero Extended */ + load16z 0x1234 R0 R1 + load16z 0x2345 R0 R1 + load16z 0x3456 R0 R2 + load16z 0x4567 R0 R3 + load16z 0x5678 R0 R4 + load16z 0x6789 R0 R5 + load16z 0x789a R0 R6 + load16z 0x89ab R0 R7 + load16z 0x9abc R1 R0 + load16z 0xabcd R2 R0 + load16z 0xbcde R3 R0 + load16z 0xcdef R4 R0 + load16z 0xdef0 R5 R0 + load16z 0xef01 R6 R0 + load16z 0xf012 R7 R0 + + load16zp 0x0123 P0 + load16zp 0x1234 P1 + load16zp 0x1234 p2 +.ifndef BFIN_HOST + load16zp 0x2345 p3 +.endif + load16zp 0x3456 p4 + load16zp 0x4567 p5 + load16zp 0x5678 sp + load16zp 0x6789 fp + load16zp 0x789a i0 + load16zp 0x89ab i1 + load16zp 0x9abc i2 + load16zp 0xabcd i3 + load16zp 0xbcde m0 + load16zp 0xcdef m1 + load16zp 0xdef0 m2 + load16zp 0xef01 m3 + load16zp 0xf012 b0 + load16zp 0x0123 b1 + load16zp 0x1234 b2 + load16zp 0x2345 b3 + load16zp 0x3456 l0 + load16zp 0x4567 l1 + load16zp 0x5678 l2 + load16zp 0x6789 l3 + + /* Sign Extended */ + load16x 0x20 R0 R1 + load16x 0x3F R0 R1 + load16x -0x20 R0 R1 + load16x -0x3F R0 R1 + load16x 0x1234 R0 R1 + load16x 0x2345 R0 R1 + load16x 0x3456 R0 R2 + load16x 0x4567 R0 R3 + load16x 0x5678 R0 R4 + load16x 0x6789 R0 R5 + load16x 0x789a R0 R6 + load16x 0x09ab R0 R7 + load16x -0x1abc R1 R0 + load16x -0x2bcd R2 R0 + load16x -0x3cde R3 R0 + load16x -0x4def R4 R0 + load16x -0x5ef0 R5 R0 + load16x -0x6f01 R6 R0 + load16x -0x7012 R7 R0 + + loadinc P0, P1, R1 + loadinc P1, P2, R1 + loadinc P2, P1, R2 +.ifndef BFIN_HOST + loadinc P3, P4, R3 +.endif + loadinc P4, P5, R4 + loadinc FP, P0, R7 + loadinc P0, I0, R1 + loadinc P1, I1, R1 + loadinc P2, I2, R1 +.ifndef BFIN_HOST + loadinc P3, I0, R1 +.endif + loadinc P4, I2, R1 + loadinc P5, I3, R1 + + A1 = A0 = 0; + R0 = 0x01 (Z); + A0.x = R0; + imm32 r4, 0x32e02d1a + A1.x = R4; + A0.w = A1.x; + R3 = A0.w; + R2 = A0.x; + imm32 r0, 0x0000001a + imm32 r1, 0x00000001 + CC = R1 == R2; + if CC jump 1f; + fail +1: + CC = R0 == R3 + if CC jump 2f; + fail +2: + pass + +.data +_buf: + .rept 0x80 + .long 0 + .endr diff --git a/tests/tcg/bfin/logic.s b/tests/tcg/bfin/logic.s new file mode 100644 index 0000000000000..9a41ccd7081bd --- /dev/null +++ b/tests/tcg/bfin/logic.s @@ -0,0 +1,64 @@ +// test program for microcontroller instructions +// Test instructions +// r4 = r2 & r3; +// r4 = r2 | r3; +// r4 = r2 ^ r3; +// r4 = ~ r2; +# mach: bfin + +.include "testutils.inc" + start + + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + + R7 = R0 & R1; + DBGA ( R7.L , 0x1111 ); + DBGA ( R7.H , 0x1111 ); + + R7 = R2 & R3; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + + R7 = R0 | R1; + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + + R7 = R2 | R3; + DBGA ( R7.L , 0x000f ); + DBGA ( R7.H , 0x0000 ); + + R7 = R0 ^ R1; + DBGA ( R7.L , 0xeeee ); + DBGA ( R7.H , 0xeeee ); + + R7 = R2 ^ R3; + DBGA ( R7.L , 0x000e ); + DBGA ( R7.H , 0x0000 ); + + R7 = ~ R0; + DBGA ( R7.L , 0xeeee ); + DBGA ( R7.H , 0xeeee ); + + R7 = ~ R2; + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + + pass + + .data +data0: + .dw 0x1111 + .dw 0x1111 + .dw 0xffff + .dw 0xffff + .dw 0x0001 + .dw 0x0000 + .dw 0x000f + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/tests/tcg/bfin/loop_snafu.s b/tests/tcg/bfin/loop_snafu.s new file mode 100644 index 0000000000000..b1e36645f9b66 --- /dev/null +++ b/tests/tcg/bfin/loop_snafu.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + r5=10; + p1=r5; + r7=20; + lsetup (lstart, lend) lc0=p1; + +lstart: + nop; + nop; + nop; + nop; + jump lend; + nop; + nop; + nop; +lend: + r7 += -1; + + nop; + nop; + + dbga( r7.l,10); + + pass diff --git a/tests/tcg/bfin/loop_strncpy.s b/tests/tcg/bfin/loop_strncpy.s new file mode 100644 index 0000000000000..13b3711986dea --- /dev/null +++ b/tests/tcg/bfin/loop_strncpy.s @@ -0,0 +1,76 @@ +# Blackfin testcase for loop counter values when jumping out from the last insn +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + loadsym r1, dest; + r0 = r1; + loadsym r1, src; + r2 = 0x10; + +_strncpy: + CC = R2 == 0; + if CC JUMP 4f; + + P2 = R2 ; /* size */ + P0 = R0 ; /* dst*/ + P1 = R1 ; /* src*/ + + LSETUP (1f, 2f) LC0 = P2; +1: + R1 = B [P1++] (Z); + B [P0++] = R1; + CC = R1 == 0; +2: + if CC jump 3f; + + fail + + /* if src is shorter than n, we need to null pad bytes in dest + * but, we can get here when the last byte is zero, and we don't + * want to copy an extra byte at the end, so we need to check + */ +3: + R2 = LC0; + CHECKREG R2, 0x0a; + + CC = R2 + if ! CC jump 4f; + + LSETUP(5f, 5f) LC0; +5: + B [P0++] = R1; + +4: + loadsym P1, answer; + P0 = R0; + p2 = 0x20; + LSETUP (6f, 7f) LC0 = P2; +6: + R1 = B [P0++]; + R2 = B [P1++]; + CC = R1 == R2 + IF ! CC JUMP wrong; +7: + NOP; + + pass + +wrong: + fail + + .data +dest: + .db 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F + .db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F + +src: + .db 0x21, 0x22, 0x23, 0x24, 0x25, 0x00, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30 + +answer: + .db 0x21, 0x22, 0x23, 0x24, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + .db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F diff --git a/tests/tcg/bfin/lp0.s b/tests/tcg/bfin/lp0.s new file mode 100644 index 0000000000000..dd7bc30b48279 --- /dev/null +++ b/tests/tcg/bfin/lp0.s @@ -0,0 +1,17 @@ +// Assert that loops can have coincidental loop ends. +# mach: bfin + +.include "testutils.inc" + start + + + P0 = 3; + R1 = 0; + LSETUP ( out0 , out1 ) LC0 = P0; +out0: + LSETUP ( out1 , out1 ) LC1 = P0; +out1: + R1 += 1; + + DBGA ( R1.L , 9 ); + pass diff --git a/tests/tcg/bfin/lp1.s b/tests/tcg/bfin/lp1.s new file mode 100644 index 0000000000000..89fa2a99dbd72 --- /dev/null +++ b/tests/tcg/bfin/lp1.s @@ -0,0 +1,16 @@ +# mach: bfin +.include "testutils.inc" + start + + P0 = 10; + + LSETUP ( xxx , yyy ) LC0 = P0; +xxx: + R1 += 1; + CC = R1 == 3; +yyy: + IF CC JUMP zzz; + R3 = 7; +zzz: + DBGA ( R1.L , 3 ); + pass diff --git a/tests/tcg/bfin/lsetup.s b/tests/tcg/bfin/lsetup.s new file mode 100644 index 0000000000000..ac39613a49c0e --- /dev/null +++ b/tests/tcg/bfin/lsetup.s @@ -0,0 +1,109 @@ +# Blackfin testcase for playing with LSETUP +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 0x123; + P0 = R0; + LSETUP (.L1, .L1) LC0 = P0; +.L1: + R0 += -1; + + R1 = 0; + CC = R1 == R0; + IF CC JUMP 1f; + fail +1: + p0=10; + loadsym i0, _buf + imm32 r0, 0x12345678 + LSETUP(.L2, .L3) lc0 = p0; +.L2: + [i0++] = r0; +.L3: + [i0++] = r0; + + loadsym R1, _buf + R0 = 0x50; + R1 = R0 + R1; + R0 = I0; + CC = R0 == R1; + if CC JUMP 2f; + fail +2: + + r5=10; + p1=r5; + r7=20; + lsetup (.L4, .L5) lc0=p1; +.L4: + nop; + nop; + nop; + nop; + jump .L5; + nop; + nop; + nop; +.L5: + r7 += -1; + + R0 = 10 (Z); + CC = R7 == R0; + if CC jump 3f; + fail +3: + r1 = 1; + r2 = 2; + r0 = 0; + p1 = 10; + loadsym p0, _buf; + lsetup (.L6, .L7) lc0 = p1; +.L6: + [p0++] = r1; +.L7: + [p0++] = r2; + + r3 = P0; + loadsym r1, _buf + r0 = 80; + r1 = r1 + r0; + CC = R1 == R3 + if CC jump 4f; + fail +4: + + R0 = 1; + R1 = 2; + R2 = 3; + R4 = 4; + P1 = R1; + LSETUP (.L8, .L8) LC0 = P1; + R5 = 5; + R6 = 6; + R7 = 7; +.L8: + R1 += 1; + + R7 = 4; + CC = R7 == R1; + if CC jump 5f; + fail +5: + P1 = R1; + LSETUP (.L9, .L9 ) LC1 = P1; +.L9: + R1 += 1; + R7 = 8; + if CC jump 6f; + fail +6: + pass + +.data +_buf: + .rept 0x80 + .long 0 + .endr diff --git a/tests/tcg/bfin/m0boundary.s b/tests/tcg/bfin/m0boundary.s new file mode 100644 index 0000000000000..5995d8834b512 --- /dev/null +++ b/tests/tcg/bfin/m0boundary.s @@ -0,0 +1,46 @@ +# mach: bfin + +.include "testutils.inc" + start + +// setup a circular buffer calculation based on illegal register values + I0 = 0xf2ef (Z); + I0.H = 0xff88; + + L0 = 0xbd5f (Z); + L0.H = 0xea9b; + + M0 = 0x0000 (Z); + M0.H = 0x8000; + + B0 = 0x3fb9 (Z); + B0.H = 0xff80; + +op1: + I0 -= M0; + + R0 = I0; + DBGA ( R0.H , 0x7f88 ); + DBGA ( R0.L , 0xf2ef ); + +// setup a circular buffer calculation based on illegal register values + I0 = 0xf2ef (Z); + I0.H = 0xff88; + + L0 = 0xbd5f (Z); + L0.H = 0xea9b; + + M0 = 0x0001 (Z); + M0.H = 0x8000; + + B0 = 0x3fb9 (Z); + B0.H = 0xff80; + +op2: + I0 -= M0; + + R0 = I0; + DBGA ( R0.H , 0x7f88 ); + DBGA ( R0.L , 0xf2ee ); + + pass diff --git a/tests/tcg/bfin/m17.s b/tests/tcg/bfin/m17.s new file mode 100644 index 0000000000000..c7aec4bbd8e94 --- /dev/null +++ b/tests/tcg/bfin/m17.s @@ -0,0 +1,74 @@ +// Test various moves to single register +# mach: bfin + + +.include "testutils.inc" + start + + +// load r0=0x7fffffff +// load r1=0x00ffffff +// load r2=0xf0000000 +// load r3=0x0000007f + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + +// extract only to high register + R5 = 0; + R4 = 0; + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5 = A1; + DBGA ( R4.L , 0x0000 ); + DBGA ( R4.H , 0x0000 ); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0x7fff ); + +// extract only to low register + R5 = 0; + R4 = 0; + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R4 = A0; + DBGA ( R4.L , 0xffff ); + DBGA ( R4.H , 0x7fff ); + DBGA ( R5.L , 0x0000 ); + DBGA ( R5.H , 0x0000 ); + +// extract only to high reg + R5 = 0; + R4 = 0; + A1 = A0 = 0; + R5 = ( A1 += R0.H * R0.H ), A0 += R0.H * R0.H; + DBGA ( R4.L , 0x0000 ); + DBGA ( R4.H , 0x0000 ); + DBGA ( R5.L , 0x0002 ); + DBGA ( R5.H , 0x7ffe ); + +// extract only to low reg + R5 = 0; + R4 = 0; + A1 = A0 = 0; + A1 += R0.H * R0.H, R4 = ( A0 += R0.H * R0.H ); + DBGA ( R4.L , 0x0002 ); + DBGA ( R4.H , 0x7ffe ); + DBGA ( R5.L , 0x0000 ); + DBGA ( R5.H , 0x0000 ); + + pass + + .data +data0: + .dw 0xffff + .dw 0x7fff + .dw 0xffff + .dw 0x00ff + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 diff --git a/tests/tcg/bfin/max_min_flags.s b/tests/tcg/bfin/max_min_flags.s new file mode 100644 index 0000000000000..a4ad33b5c1748 --- /dev/null +++ b/tests/tcg/bfin/max_min_flags.s @@ -0,0 +1,275 @@ +// Check Flag Settings for MAX/MIN +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + r0=1; + r1= -1; + r2=min(r1,r0); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=min(r0,r1); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=max(r1,r0); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x0); + + r2=max(r0,r1); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x0); + + r0.h=1; + r2=min(r1,r0) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=min(r0,r1) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=max(r1,r0) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x1); + + r2=max(r0,r1) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x1); + + r0=0; + r2=max(r1,r0); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x1); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x0); + dbga (r2.h, 0x0); + + r0.h=1; + r2=max(r1,r0) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x1); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x0); + dbga (r2.h, 0x1); + + pass diff --git a/tests/tcg/bfin/mem3.s b/tests/tcg/bfin/mem3.s new file mode 100644 index 0000000000000..da070e0a9ef51 --- /dev/null +++ b/tests/tcg/bfin/mem3.s @@ -0,0 +1,42 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0.H = 0x1234; + R0.L = 0x5678; + loadsym P0, data0; + + [ P0 ] = R0; + P1 = [ P0 ]; + _DBG P1; + R1 = [ P0 ]; + _DBG R1; + CC = R0 == R1; + IF !CC JUMP abrt; + + W [ P0 ] = R0; + R1 = W [ P0 ] (Z); + R2 = R0; + R2 <<= 16; + R2 >>= 16; + _DBG R1; + CC = R2 == R1; + IF !CC JUMP abrt; + + B [ P0 ] = R0; + R1 = B [ P0 ] (Z); + R2 = R0; + R2 <<= 24; + R2 >>= 24; + _DBG R1; + CC = R2 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail; + + .data +data0: + .dd 0xDEADBEAF; diff --git a/tests/tcg/bfin/move.s b/tests/tcg/bfin/move.s new file mode 100644 index 0000000000000..b8f41c8bfbcf6 --- /dev/null +++ b/tests/tcg/bfin/move.s @@ -0,0 +1,36 @@ +# Blackfin testcase for register move instructions +# mach: bfin + + + .include "testutils.inc" + + start + + .macro move reg0:req, reg1:req, clobber:req + imm32 \reg0, 0x5555aaaa + imm32 \reg1, 0x12345678 + imm32 \clobber, 0x12345678 + \reg0 = \reg1; + CC = \reg0 == \clobber; + if CC jump 1f; + fail +1: + .endm + + move R0, R1, R2 + move R0, R2, R3 + move R0, R2, R4 + move R0, R3, R5 + move R0, R4, R6 + move R0, R5, R7 + move R0, R6, R1 + move R0, R7, R2 + move R7, R0, R1 + move R7, R1, R2 + move R7, R2, R3 + move R7, R3, R4 + move R7, R4, R5 + move R7, R5, R6 + move R7, R6, R0 + + pass diff --git a/tests/tcg/bfin/neg.S b/tests/tcg/bfin/neg.S new file mode 100644 index 0000000000000..45649a18ada32 --- /dev/null +++ b/tests/tcg/bfin/neg.S @@ -0,0 +1,42 @@ +# Blackfin testcase for negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0x5678; + R1 = -R0; + R7 = ASTAT; + R2.H = 0xedcb; + R2.L = 0xa988; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ V V_COPY AC0 AC0_COPY */ + R3.H = HI(_AZ|_V|_V_COPY|_AC0|_AC0_COPY); + R3.L = LO(_AZ|_V|_V_COPY|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AN */ + R3.H = HI(_AN); + R3.L = LO(_AN); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/tests/tcg/bfin/nshift.s b/tests/tcg/bfin/nshift.s new file mode 100644 index 0000000000000..f9e345b953258 --- /dev/null +++ b/tests/tcg/bfin/nshift.s @@ -0,0 +1,33 @@ +// ACP 5.18: Shifter uses wrong shift value +# mach: bfin + +.include "testutils.inc" + start + + + r0=0; + r0.h=0x8000; + r1=0x20 (z); + r0 >>>= r1; + dbga (r0.h, 0xffff); + dbga (r0.l, 0xffff); + + r0=0; + r0.h=0x7fff; + r0 >>>= r1; + dbga (r0.h, 0x0000); + dbga (r0.l, 0x0000); + + r0.l=0xffff; + r0.h=0xffff; + r0 >>= r1; + dbga (r0.h, 0x0000); + dbga (r0.l, 0x0000); + + r0.l=0xffff; + r0.h=0xffff; + r0 <<= r1; + dbga (r0.h, 0x0000); + dbga (r0.l, 0x0000); + + pass; diff --git a/tests/tcg/bfin/pr.s b/tests/tcg/bfin/pr.s new file mode 100644 index 0000000000000..d2901840c7051 --- /dev/null +++ b/tests/tcg/bfin/pr.s @@ -0,0 +1,81 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym R3, foo; + I1 = R3; + + R4 = 0x10 + R4 = R4 + R3; + P0 = R4; + + R4 = 0x14; + R4 = R4 + R3; + I0 = R4; + + r0 = 0x22; + loadsym P1, bar; + + [i0] = r0; + [i1] = r0; + +doItAgain: + + p2 = 4; + r5=0; + + LSETUP ( lstart , lend) LC0 = P2; +lstart: + + MNOP || R2 = [ I0 ++ ] || R1 = [ I1 ++ ]; + CC = R1 == R2; + IF CC JUMP lend; + R1 = [ P1 + 0x0 ]; + R1 = R1 + R0; + [ P1 + 0x0 ] = R1; + +lend: + NOP; + + if !cc jump _halt0; + cc = r5 == 0; + if !cc jump _halt0; + + r4=1; + r5=r5+r4; + r1=i0; + R4 = 0x24; + R4 = R3 + R4 + CC = R1 == R4 + if !CC JUMP _fail; + + i2=i0; + r2=0x1234; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + jump doItAgain; + +_halt0: + r0=i0; + R4 = 0x34; + R4 = R4 + R3; + CC = R0 == R4; + IF !CC JUMP _fail; + + pass; + +_fail: + fail; + + .data +foo: + .space (0x100); + +bar: + .space (0x1000); diff --git a/tests/tcg/bfin/push-pop-multiple.s b/tests/tcg/bfin/push-pop-multiple.s new file mode 100644 index 0000000000000..2a2b3562ca85e --- /dev/null +++ b/tests/tcg/bfin/push-pop-multiple.s @@ -0,0 +1,169 @@ +# Blackfin testcase for push/pop multiples instructions +# mach: bfin + + .include "testutils.inc" + + # Tests follow the pattern: + # - do the push multiple + # - write a garbage value to all registers pushed + # - do the pop multiple + # - check all registers popped against known values + + start + + # Repeat the same operation multiple times, so this: + # do_x moo, R, 1 + # becomes this: + # moo R1, 0x11111111 + # moo R0, 0x00000000 + .macro _do_x func:req, reg:req, max:req, x:req + .ifle (\max - \x) + \func \reg\()\x, 0x\x\x\x\x\x\x\x\x + .endif + .endm + .macro do_x func:req, reg:req, max:req + .ifc \reg, R + _do_x \func, \reg, \max, 7 + _do_x \func, \reg, \max, 6 + .endif + _do_x \func, \reg, \max, 5 + _do_x \func, \reg, \max, 4 + _do_x \func, \reg, \max, 3 + _do_x \func, \reg, \max, 2 + _do_x \func, \reg, \max, 1 + _do_x \func, \reg, \max, 0 + .endm + + # Keep the garbage value in I0 + .macro loadi reg:req, val:req + \reg = I0; + .endm + imm32 I0, 0xAABCDEFF + + # + # Test push/pop multiples with (R7:x) syntax + # + + _push_r_tests: + + # initialize all Rx regs with a known value + do_x imm32, R, 0 + + .macro checkr tochk:req, val:req + P0 = \tochk; + imm32 P1, \val + CC = P0 == P1; + IF !CC JUMP 8f; + .endm + + .macro pushr maxr:req + _push_r\maxr: + [--SP] = (R7:\maxr); + do_x loadi, R, \maxr + (R7:\maxr) = [SP++]; + do_x checkr, R, \maxr + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump.l 1f; + 9: + .endm + + pushr 7 + pushr 6 + pushr 5 + pushr 4 + pushr 3 + pushr 2 + pushr 1 + pushr 0 + + # + # Test push/pop multiples with (P5:x) syntax + # + + _push_p_tests: + + # initialize all Px regs with a known value + do_x imm32, P, 0 + + .macro checkp tochk:req, val:req + R0 = \tochk; + imm32 R1, \val + CC = R0 == R1; + IF !CC JUMP 8f; + .endm + + .macro pushp maxp:req + _push_p\maxp: + [--SP] = (P5:\maxp); + do_x loadi, P, \maxp + (P5:\maxp) = [SP++]; + do_x checkp, P, \maxp + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump.l 1f; + 9: + .endm + + # checkp func clobbers R0/R1 + L0 = R0; + L1 = R1; + pushp 5 + pushp 4 + pushp 3 + pushp 2 + pushp 1 + pushp 0 + R0 = L0; + R1 = L1; + + # + # Test push/pop multiples with (R7:x, P5:x) syntax + # + + _push_rp_tests: + + .macro _pushrp maxr:req, maxp:req + _push_r\maxr\()_p\maxp: + [--SP] = (R7:\maxr, P5:\maxp); + do_x loadi, R, \maxr + do_x loadi, P, \maxp + (R7:\maxr, P5:\maxp) = [SP++]; + # checkr func clobbers P0/P1 + L0 = P0; + L1 = P1; + do_x checkr, R, \maxr + P1 = L1; + P0 = L0; + # checkp func clobbers R0/R1 + L0 = R0; + L1 = R1; + do_x checkp, P, \maxp + R0 = L0; + R1 = L1; + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump.l 1f; + 9: + .endm + .macro pushrp maxr:req + _pushrp \maxr, 5 + _pushrp \maxr, 4 + _pushrp \maxr, 3 + _pushrp \maxr, 2 + _pushrp \maxr, 1 + _pushrp \maxr, 0 + .endm + + pushrp 7 + pushrp 6 + pushrp 5 + pushrp 4 + pushrp 3 + pushrp 2 + pushrp 1 + pushrp 0 + + pass +1: + fail diff --git a/tests/tcg/bfin/push-pop.s b/tests/tcg/bfin/push-pop.s new file mode 100644 index 0000000000000..7b868db1bda87 --- /dev/null +++ b/tests/tcg/bfin/push-pop.s @@ -0,0 +1,78 @@ +# Blackfin testcase for push/pop instructions +# mach: bfin + + .include "testutils.inc" + + start + + # This uses R0/R1 as scratch ... assume those work fine in general + .macro check loader:req, reg:req + \loader \reg, 0x12345678 + [--SP] = \reg; + R0 = [SP]; + R1 = \reg; + CC = R0 == R1; + IF !CC JUMP 8f; + \loader \reg, 0x87654321 + \reg = [SP++]; + CC = R0 == R1; + IF !CC JUMP 8f; + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump 1f; + 9: + .endm + .macro imm_check reg:req + check imm32, \reg + .endm + .macro dmm_check reg:req + check dmm32, \reg + .endm + + imm_check R2 + imm_check R3 + imm_check R4 + imm_check R5 + imm_check R6 + imm_check R7 + imm_check P0 + imm_check P1 + imm_check P2 + imm_check P3 + imm_check P4 + imm_check P5 + imm_check FP + imm_check I0 + imm_check I1 + imm_check I2 + imm_check I3 + imm_check M0 + imm_check M1 + imm_check M2 + imm_check M3 + imm_check B0 + imm_check B1 + imm_check B2 + imm_check B3 + imm_check L0 + imm_check L1 + imm_check L2 + imm_check L3 + dmm_check A0.X + dmm_check A0.W + dmm_check A1.X + dmm_check A1.W + dmm_check LC0 + dmm_check LC1 + # Make sure the top/bottom regs have bit 1 set + dmm_check LT0 + dmm_check LT1 + dmm_check LB0 + dmm_check LB1 + dmm_check RETS + + dmm_check ASTAT + + pass +1: + fail diff --git a/tests/tcg/bfin/pushpopreg_1.s b/tests/tcg/bfin/pushpopreg_1.s new file mode 100644 index 0000000000000..2ee2029bf0026 --- /dev/null +++ b/tests/tcg/bfin/pushpopreg_1.s @@ -0,0 +1,292 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r0.l = 0x1111; + r0.h = 0x0011; + r1.l = 0x2222; + r1.h = 0x0022; + r2.l = 0x3333; + r2.h = 0x0033; + r3.l = 0x4444; + r3.h = 0x0044; + r4.l = 0x5555; + r4.h = 0x0055; + r5.l = 0x6666; + r5.h = 0x0066; + r6.l = 0x7777; + r6.h = 0x0077; + r7.l = 0x8888; + r7.h = 0x0088; + p1.l = 0x5a5a; + p1.h = 0x005a; + p2.l = 0x6363; + p2.h = 0x0063; + p3.l = 0x7777; + p3.h = 0x0077; + p4.l = 0x7878; + p4.h = 0x0078; + p5.l = 0x3e3e; + p5.h = 0x003e; +// sp = 0x4000(x); + + jump.s prog_start; + + nop; + nop; // ADD reg update to roll back + nop; + +prog_start: + nop; + [--sp] = r0; + [--sp] = r1; + [--sp] = r2; + [--sp] = r3; + [--sp] = r4; + [--sp] = r5; + [--sp] = r6; + [--sp] = r7; + [--sp] = p0; + [--sp] = p1; + [--sp] = p2; + [--sp] = p3; + [--sp] = p4; + [--sp] = p5; + + nop; + nop; + nop; + nop; + r0.l = 0xdead; + r0.h = 0xdead; + r1.l = 0xdead; + r1.h = 0xdead; + r2.l = 0xdead; + r2.h = 0xdead; + r3.l = 0xdead; + r3.h = 0xdead; + r4.l = 0xdead; + r4.h = 0xdead; + r5.l = 0xdead; + r5.h = 0xdead; + r6.l = 0xdead; + r6.h = 0xdead; + r7.l = 0xdead; + r7.h = 0xdead; + p1.l = 0xdead; + p1.h = 0xdead; + p2.l = 0xdead; + p2.h = 0xdead; + p3.l = 0xdead; + p3.h = 0xdead; + p4.l = 0xdead; + p4.h = 0xdead; + p5.l = 0xdead; + p5.h = 0xdead; + nop; + nop; + nop; + r0 = [sp++]; + r1 = [sp++]; + r2 = [sp++]; + r3 = [sp++]; + r4 = [sp++]; + r5 = [sp++]; + r6 = [sp++]; + r7 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + p2 = [sp++]; + p3 = [sp++]; + p4 = [sp++]; + p5 = [sp++]; + + nop; + nop; + nop; + nop; + nop; + nop; + nop; +_tp1: + nop; + nop; + nop; + nop; + nop; + nop; + nop; + [--sp] = r0; + [--sp] = r1; + [--sp] = r2; + [--sp] = r3; + [--sp] = r4; + [--sp] = r5; + [--sp] = r6; + [--sp] = r7; + [--sp] = p0; + [--sp] = p1; + [--sp] = p2; + [--sp] = p3; + [--sp] = p4; + [--sp] = p5; + + nop; + nop; + nop; + nop; + r0.l = 0xdead; + r0.h = 0xdead; + r1.l = 0xdead; + r1.h = 0xdead; + r2.l = 0xdead; + r2.h = 0xdead; + r3.l = 0xdead; + r3.h = 0xdead; + r4.l = 0xdead; + r4.h = 0xdead; + r5.l = 0xdead; + r5.h = 0xdead; + r6.l = 0xdead; + r6.h = 0xdead; + r7.l = 0xdead; + r7.h = 0xdead; + p1.l = 0xdead; + p1.h = 0xdead; + p2.l = 0xdead; + p2.h = 0xdead; + p3.l = 0xdead; + p3.h = 0xdead; + p4.l = 0xdead; + p4.h = 0xdead; + p5.l = 0xdead; + p5.h = 0xdead; + nop; + nop; + nop; + r0 = [sp++]; + r1 = [sp++]; + r2 = [sp++]; + r3 = [sp++]; + r4 = [sp++]; + r5 = [sp++]; + r6 = [sp++]; + r7 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + a0.x = [sp++]; + + a1.w = r0; //preserve r0 + + r0 = a0.x; + DBGA(r0.l,0x0063); + + a0.w = [sp++]; + r0 = a0.w; + DBGA(r0.l,0x7777); + DBGA(r0.h,0x0077); + + a0 = a1; //perserver r0, still + + a1.x = [sp++]; + r0 = a1.x; + DBGA(r0.l,0x0078); + + a1.w = [sp++]; + r0 = a1.w; + DBGA(r0.l,0x3e3e); + DBGA(r0.h,0x003e); + + r0 = a0.w; //restore r0 + + nop; + nop; + nop; + nop; + nop; + nop; + nop; +_tp2: + nop; + nop; + nop; + [--sp] = r0; + [--sp] = r1; + [--sp] = r2; + [--sp] = r3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + [--sp] = p0; + [--sp] = p1; + [--sp] = p2; + [--sp] = p3; + [--sp] = p4; + [--sp] = p5; + + nop; + nop; + nop; + nop; + r0.l = 0xdead; + r0.h = 0xdead; + r1.l = 0xdead; + r1.h = 0xdead; + r2.l = 0xdead; + r2.h = 0xdead; + r3.l = 0xdead; + r3.h = 0xdead; + r4.l = 0xdead; + r4.h = 0xdead; + r5.l = 0xdead; + r5.h = 0xdead; + r6.l = 0xdead; + r6.h = 0xdead; + r7.l = 0xdead; + r7.h = 0xdead; + p1.l = 0xdead; + p1.h = 0xdead; + p2.l = 0xdead; + p2.h = 0xdead; + p3.l = 0xdead; + p3.h = 0xdead; + p4.l = 0xdead; + p4.h = 0xdead; + p5.l = 0xdead; + p5.h = 0xdead; + nop; + nop; + nop; + r0 = [sp++]; + r1 = [sp++]; + r2 = [sp++]; + r3 = [sp++]; + r4 = [sp++]; + r5 = [sp++]; + r6 = [sp++]; + r7 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + p2 = [sp++]; + p3 = [sp++]; + p4 = [sp++]; + p5 = [sp++]; + + nop; + nop; + nop; + nop; + nop; + nop; + nop; +_tp3: + nop; + nop; + nop; + nop; + nop; +_halt: + pass; diff --git a/tests/tcg/bfin/s0.s b/tests/tcg/bfin/s0.s new file mode 100644 index 0000000000000..8fa53f258965e --- /dev/null +++ b/tests/tcg/bfin/s0.s @@ -0,0 +1,12 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 10; + P0 = R0; + LSETUP ( ls0 , ls0 ) LC0 = P0; +ls0: + R0 += -1; + DBGA ( R0.L , 0 ); + pass diff --git a/tests/tcg/bfin/s1.s b/tests/tcg/bfin/s1.s new file mode 100644 index 0000000000000..262dc06d9f3ba --- /dev/null +++ b/tests/tcg/bfin/s1.s @@ -0,0 +1,25 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R4 = 4; + P1 = R1; + LSETUP ( ls0 , ls0 ) LC0 = P1; + R5 = 5; + R6 = 6; + R7 = 7; + +ls0: R1 += 1; + + DBGA ( R1.L , 4 ); + P1 = R1; + LSETUP ( ls1 , ls1 ) LC1 = P1; +ls1: R1 += 1; + + DBGA ( R1.L , 8 ); + + pass diff --git a/tests/tcg/bfin/s10.s b/tests/tcg/bfin/s10.s new file mode 100644 index 0000000000000..503cabfe7a3d7 --- /dev/null +++ b/tests/tcg/bfin/s10.s @@ -0,0 +1,77 @@ +// Shifter test program. +// Test instructions +// RL0 = SIGNBITS R1; +// RL0 = SIGNBITS RL1; +// RL0 = SIGNBITS RH1; + +# mach: bfin + +.include "testutils.inc" + start + + +// on 32-b word + + R1.L = 0xffff; + R1.H = 0x7fff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0000 ); + + R1.L = 0xffff; + R1.H = 0x30ff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001 ); + + R1.L = 0xff0f; + R1.H = 0x10ff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0002 ); + + R1.L = 0xff0f; + R1.H = 0xe0ff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0002 ); + + R1.L = 0x0001; + R1.H = 0x0000; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001e ); + + R1.L = 0xfffe; + R1.H = 0xffff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001e ); + + R1.L = 0xffff; // return largest norm for -1 + R1.H = 0xffff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001f ); + + R1.L = 0; // return largest norm for zero + R1.H = 0; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x001f ); + +// on 16-b word + + R1.L = 0x7fff; + R1.H = 0xffff; + R0.L = SIGNBITS R1.L; + DBGA ( R0.L , 0x0000 ); + + R1.L = 0x0fff; + R1.H = 0x0001; + R0.L = SIGNBITS R1.H; + DBGA ( R0.L , 0x000e ); + + R1.L = 0x0fff; + R1.H = 0xffff; + R0.L = SIGNBITS R1.H; + DBGA ( R0.L , 0x000f ); + + R1.L = 0x0fff; + R1.H = 0xfffe; + R0.L = SIGNBITS R1.H; + DBGA ( R0.L , 0x000e ); + + pass diff --git a/tests/tcg/bfin/s15.s b/tests/tcg/bfin/s15.s new file mode 100644 index 0000000000000..9c32d48857971 --- /dev/null +++ b/tests/tcg/bfin/s15.s @@ -0,0 +1,149 @@ +// reg-based SHIFT test program. +# mach: bfin + +.include "testutils.inc" + start + + +// Test FEXT with no sign extension + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0810; // pos=8 len=16 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x34de ); + DBGA ( R7.H , 0 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0814; // pos=8 len=20 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x34de ); + DBGA ( R7.H , 0x0002 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0800; // pos=8 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x0001; // pos=0 len=1 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x1 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x0101; // pos=1 len=1 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x1810; // pos=24 len=16 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x00ff ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x0020; // pos=0 len=32 is like pos=0 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x0 ); + DBGA ( R7.H , 0x0 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x2020; // pos=32 len=32 is like pos=0 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x1f01; // pos=31 len=1 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x1 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x1000; // pos=16 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + +// Test FEXT with sign extension + + R0.L = 0xdead; + R0.H = 0x12f4; + R1.L = 0x0810; // pos=8 len=16 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xf4de ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0810; // pos=8 len=16 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0x34de ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdead; + R0.H = 0xf234; + R1.L = 0x1f01; // pos=31 len=1 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdead; + R0.H = 0xf234; + R1.L = 0x1f02; // pos=31 len=2 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x101f; // pos=16 len=31 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x1001; // pos=16 len=1 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x1000; // pos=16 len=0 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/tests/tcg/bfin/s16.s b/tests/tcg/bfin/s16.s new file mode 100644 index 0000000000000..6741cf3834890 --- /dev/null +++ b/tests/tcg/bfin/s16.s @@ -0,0 +1,170 @@ +// reg-based SHIFT test program. +# mach: bfin + +.include "testutils.inc" + start + + +// Test FDEP with no sign extension + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c08; // pos=12 len=8 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x123f ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c04; // pos=12 len=4 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c05; // pos=12 len=5 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x1235 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0010; // pos=0 len=16 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0011; // pos=0 len=17 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0114; // pos=1 len=20 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1235 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x001f; // pos=0 len=31 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x1c04; // pos=28 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdead ); + DBGA ( R7.H , 0xf234 ); + + R0.L = 0xdead; + R0.H = 0x0234; + R1.L = 0x1d04; // pos=29 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdead ); + DBGA ( R7.H , 0xe234 ); + + R0.L = 0xdead; + R0.H = 0x0234; + R1.L = 0x1f04; // pos=31 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdead ); + DBGA ( R7.H , 0x8234 ); + + R0.L = 0xdead; + R0.H = 0x0234; + R1.L = 0x2004; // pos=32 len=4, same as pos=0 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdeaf ); + DBGA ( R7.H , 0x0234 ); + +// Test FDEP with sign extension + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c08; // pos=12 len=8 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c08; // pos=12 len=8 + R1.H = 0x007f; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x0007 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0110; // pos=1 len=16 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0101; // pos=1 len=1 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0102; // pos=1 len=2 + R1.H = 0x0001; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0002; // pos=0 len=2 + R1.H = 0x0001; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0000; // pos=0 len=0 + R1.H = 0x000f; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/tests/tcg/bfin/s17.s b/tests/tcg/bfin/s17.s new file mode 100644 index 0000000000000..530a93babc818 --- /dev/null +++ b/tests/tcg/bfin/s17.s @@ -0,0 +1,46 @@ +// shifter test program. +// Test instructions ONES +# mach: bfin + +.include "testutils.inc" + start + + + R7 = 0; + ASTAT = R7; + R0.L = 0x1; + R0.H = 0x0; + R7.L = ONES R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0x8000; + R7.L = ONES R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + + R0.L = 0x0001; + R0.H = 0x8000; + R7.L = ONES R0; + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R7.L = ONES R0; + DBGA ( R7.L , 0x0020 ); + DBGA ( R7.H , 0x0000 ); + + R0.L = 0x0000; + R0.H = 0x0000; + R7.L = ONES R0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + + pass diff --git a/tests/tcg/bfin/s2.s b/tests/tcg/bfin/s2.s new file mode 100644 index 0000000000000..4b8ab2dfe93ab --- /dev/null +++ b/tests/tcg/bfin/s2.s @@ -0,0 +1,47 @@ +# mach: bfin + +.include "testutils.inc" + start + +// Test pc relative indirect branches. + P4 = 0; + loadsym P1 jtab; + +LL1: + P2 = P1 + ( P4 << 1 ); + R0 = W [ P2 ] (Z); + P0 = R0; + R2 = P4; + +jp: + JUMP ( PC + P0 ); + + DBGA ( R2.L , 0 ); + JUMP.L done; + + DBGA ( R2.L , 1 ); + JUMP.L done; + + DBGA ( R2.L , 2 ); + JUMP.L done; + + DBGA ( R2.L , 3 ); + JUMP.L done; + + DBGA ( R2.L , 4 ); + JUMP.L done; + +done: + P4 += 1; + CC = P4 < 4 (IU); + IF CC JUMP LL1; + pass + + .data + +jtab: + .dw 2; //.dw (2+0*8) + .dw 10; //.dw (2+1*8) + .dw 18; //.dw (2+2*8) + .dw 26; //.dw (2+3*8) + .dw 34; //.dw (2+4*8) diff --git a/tests/tcg/bfin/s20.s b/tests/tcg/bfin/s20.s new file mode 100644 index 0000000000000..7f97d220a1916 --- /dev/null +++ b/tests/tcg/bfin/s20.s @@ -0,0 +1,25 @@ +// Test byte-align instructions +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 0xabcd; + R0.H = 0x1234; + R1.L = 0x4567; + R1.H = 0xdead; + + R2 = ALIGN8 ( R1 , R0 ); + DBGA ( R2.L , 0x34ab ); + DBGA ( R2.H , 0x6712 ); + + R2 = ALIGN16 ( R1 , R0 ); + DBGA ( R2.L , 0x1234 ); + DBGA ( R2.H , 0x4567 ); + + R2 = ALIGN24 ( R1 , R0 ); + DBGA ( R2.L , 0x6712 ); + DBGA ( R2.H , 0xad45 ); + + pass diff --git a/tests/tcg/bfin/s21.s b/tests/tcg/bfin/s21.s new file mode 100644 index 0000000000000..b528dd9527bf6 --- /dev/null +++ b/tests/tcg/bfin/s21.s @@ -0,0 +1,298 @@ +// Copyright (c) 1997,1998,1999 Analog Devices Inc., All Rights Reserved +// Test A0 = ROT (A0 by imm6); +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + A0 = A1 = 0; + +// rot +// left by 1 +// 00 8000 0001 -> 01 0000 0002 cc=0 + R0.L = 0x0001; + R0.H = 0x8000; + R7 = 0; + CC = R7; + A1 = A0 = 0; + A0.w = R0; + A0 = ROT A0 BY 1; + R1 = A0.w; + DBGA ( R1.L , 0x0002 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 1 +// 80 0000 0001 -> 00 0000 0002 cc=1 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 1; + R1 = A0.w; + DBGA ( R1.L , 0x0002 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// left by 1 with cc=1 +// 80 8000 0001 -> 01 0000 0003 cc=1 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 1; + R1 = A0.w; + DBGA ( R1.L , 0x0003 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// left by 2 with cc=1 +// 80 0000 0001 -> 00 0000 0007 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 2; + R1 = A0.w; + DBGA ( R1.L , 0x0007 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 3 with cc=0 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 3; + R1 = A0.w; + DBGA ( R1.L , 0x000a ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by largest positive magnitude of 31 +// 80 0000 0001 -> 00 a000 0000 cc=0 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 31; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0xa000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by 1 +// 80 0000 0001 -> 40 0000 0000 cc=1 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -1; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0040 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by 1 +// 80 0000 0001 -> c0 0000 0000 cc=1 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -1; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0xffc0 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by 2 +// 80 0000 0001 -> e0 0000 0000 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -2; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0xffe0 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by 9 +// 80 0000 0001 -> 01 c000 0000 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -9; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0xc000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by 9 with reg +// 80 0000 0001 -> 01 c000 0000 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + R5 = -9; + A0 = ROT A0 BY R5.L; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0xc000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot left by 4 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY 4; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x4567 ); DBGA ( R4.L , 0x89a8 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0023 ); + +// rot left by 28 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY 28; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xa891 ); DBGA ( R4.L , 0xa2b3 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff89 ); + +// rot right by 4 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY -4; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x2345 ); DBGA ( R4.L , 0x6789 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0051 ); + +// rot right by 8 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY -28; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xcf13 ); DBGA ( R4.L , 0x5123 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff8a ); + + pass diff --git a/tests/tcg/bfin/s4.s b/tests/tcg/bfin/s4.s new file mode 100644 index 0000000000000..784c57d82c84c --- /dev/null +++ b/tests/tcg/bfin/s4.s @@ -0,0 +1,214 @@ +// Immediate SHIFT test program. +// Test r4 = ASHIFT (r2 by 10); +// Test r4 = LSHIFT (r2 by 10); +// Test r4 = ROT (r2 by 10); +# mach: bfin + +.include "testutils.inc" + start + + + init_r_regs 0; + ASTAT = R0; + +// load r0=0x80000001 +// load r1=0x00000000 +// load r2=0x00000000 +// load r3=0x00000000 +// load r4=0x00000000 +// load r5=0x00000000 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + +// arithmetic +// left by largest positive magnitude of 31 (0x1f) +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R6 = R0 << 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 +// 8000 0001 -> 0000 0002 + R6 = R0 << 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 1 +// 8000 0001 -> c000 0000 + R7 = 0; + ASTAT = R7; + R6 = R0 >>> 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xc000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by largest negative magnitude of -31 +// 8000 0001 -> ffff ffff + R6 = R0 >>> 31; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + +// logic +// left by largest positive magnitude of 31 (0x1f) +// 8000 0001 -> 8000 0000 + R6 = R0 << 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + +// logic +// left by 1 +// 8000 0001 -> 0000 0002 + R6 = R0 << 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + +// logic +// right by 1 +// 8000 0001 -> 4000 0000 + R6 = R0 >> 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + +// logic +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0001 + R6 = R0 >> 31; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + +// rot +// left by 1 +// 8000 0001 -> 0000 0002 cc=1 + R7 = 0; + CC = R7; + R6 = ROT R0 BY 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by -1 +// 8000 0001 -> 4000 0000 cc=1 + R7 = 0; + CC = R7; + R6 = ROT R0 BY -1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by largest positive magnitude of 31 +// 8000 0001 -> a000 0000 cc=0 + R7 = 0; + CC = R7; + R6 = ROT R0 BY 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xa000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest positive magnitude of 31 with cc=1 +// 8000 0001 cc=1 -> a000 0000 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xe000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0005 cc=0 + R7 = 0; + CC = R7; + R6 = ROT R0 BY -31; + DBGA ( R6.L , 0x0005 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 with cc=1 +// 8000 0001 cc=1 -> 0000 0007 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY -31; + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 7 +// 8000 0001 cc=1 -> 0000 00e0 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 7; + DBGA ( R6.L , 0x00e0 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot by zero +// 8000 0001 -> 8000 000 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 0; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x8000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// 0 by 1 + R7 = 0; + R0 = 0; + ASTAT = R7; + R6 = R0 << 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass + + .data +data0: + .dw 0x0001 + .dw 0x8000 + .dd 0x0000 + .dd 0x0 + .dd 0x0 + .dd 0x0 + .dd 0x0 + .dd 0x0 diff --git a/tests/tcg/bfin/s5.s b/tests/tcg/bfin/s5.s new file mode 100644 index 0000000000000..8608184bbc7ee --- /dev/null +++ b/tests/tcg/bfin/s5.s @@ -0,0 +1,107 @@ +// Test r4 = ROT (r2 by r3); +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 0x0001; + R0.H = 0x8000; + +// rot +// left by 1 +// 8000 0001 -> 0000 0002 cc=1 + R7 = 0; + CC = R7; + R1 = 1; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by -1 +// 8000 0001 -> 4000 0000 cc=1 + R7 = 0; + CC = R7; + R1.L = 0xffff; // check alternate mechanism for immediates + R1.H = 0xffff; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by largest positive magnitude of 31 +// 8000 0001 -> a000 0000 cc=0 + R7 = 0; + CC = R7; + R1 = 31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xa000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest positive magnitude of 31 with cc=1 +// 8000 0001 cc=1 -> a000 0000 cc=0 + R7 = 1; + CC = R7; + R1 = 31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xe000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0005 cc=0 + R7 = 0; + CC = R7; + R1 = -31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0005 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 with cc=1 +// 8000 0001 cc=1 -> 0000 0007 cc=0 + R7 = 1; + CC = R7; + R1 = -31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 7 +// 8000 0001 cc=1 -> 0000 00e0 cc=0 + R7 = 1; + CC = R7; + R1 = 7; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x00e0 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot by zero +// 8000 0001 -> 8000 0000 + R7 = 1; + CC = R7; + R1 = 0; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x8000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + + pass diff --git a/tests/tcg/bfin/s6.s b/tests/tcg/bfin/s6.s new file mode 100644 index 0000000000000..6fc9a2b992f63 --- /dev/null +++ b/tests/tcg/bfin/s6.s @@ -0,0 +1,83 @@ +// Test r4 = VMAX/VMAX (r5,r1) A0<<2; +# mach: bfin + +.include "testutils.inc" + start + + +// Both max values are in high half, hence both bits +// into A0 are 1 + A0 = 0; + R1.L = 0x2; // max in r1 is 3 + R1.H = 0x3; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0003 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// max value in r1 is in low, so second bit into A0 is zero + A0 = 0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// both max values in low, so both bits into A0 are zero + R0.L = 0x8000; + R0.H = 0x0; + A0.w = R0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x7; // max in r0 is 7 + R0.H = 0x6; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0002 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// Test for correct max when one value overflows + A0 = 0; + R1.L = 0x7fff; // max in r1 is 0x8001 (overflowed) + R1.H = 0x8001; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x0003 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + + pass diff --git a/tests/tcg/bfin/s7.s b/tests/tcg/bfin/s7.s new file mode 100644 index 0000000000000..0cda60ef449d4 --- /dev/null +++ b/tests/tcg/bfin/s7.s @@ -0,0 +1,83 @@ +// Test r4 = VMAX/VMAX (r5,r1) A0>>2; +# mach: bfin + +.include "testutils.inc" + start + + +// Both max values are in high half, hence both bits +// into A0 are 1 + A0 = 0; + R1.L = 0x2; // max in r1 is 3 + R1.H = 0x3; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xc000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// max value in r1 is in low, so second bit into A0 is zero + A0 = 0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x4000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// both max values in low, so both bits into A0 are zero + R0.L = 0x8000; + R0.H = 0x0; + A0.w = R0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x7; // max in r0 is 7 + R0.H = 0x6; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x2000 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// Test for correct max when one value overflows + A0 = 0; + R1.L = 0x7fff; // max in r1 is 0x8001 (overflowed) + R1.H = 0x8001; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xc000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + + pass diff --git a/tests/tcg/bfin/s8.s b/tests/tcg/bfin/s8.s new file mode 100644 index 0000000000000..46d156eb74b3a --- /dev/null +++ b/tests/tcg/bfin/s8.s @@ -0,0 +1,55 @@ +// Test rl4 = VMAX r5 A0<<1; +// Test rl4 = VMAX r5 A0>>1; +# mach: bfin + +.include "testutils.inc" + start + + +// max value in high half, hence bit into A0 is one + A0 = 0; + R1.L = 0x2; // max in r1 is 3 + R1.H = 0x3; + + R6.L = VIT_MAX( R1 ) (ASL); + + DBGA ( R6.L , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// max value in low half, hence bit into A0 is zero + R0.L = 0x8000; + R0.H = 0x8000; + A0.w = R0; + R1.L = 0x8001; // max in r1 is 8001 + R1.H = 0x7f00; + + R6.L = VIT_MAX( R1 ) (ASL); + + DBGA ( R6.L , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0001 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0001 ); + +// max value in high half, hence bit into A0 is one + R0.L = 0x8000; + R0.H = 0x0000; + A0.w = R0; + R1.L = 0x7fff; // max in r1 is 8001 + R1.H = 0x8001; + + R6.L = VIT_MAX( R1 ) (ASR); + + DBGA ( R6.L , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x4000 ); + DBGA ( R7.H , 0x8000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + + pass diff --git a/tests/tcg/bfin/s9.s b/tests/tcg/bfin/s9.s new file mode 100644 index 0000000000000..7293e3a5231a2 --- /dev/null +++ b/tests/tcg/bfin/s9.s @@ -0,0 +1,134 @@ +// Test rl3 = ashift (rh0 by 7); +// Test rl3 = lshift (rh0 by 7); +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + + R0 = 0; + ASTAT = R0; + R0.L = 0x1; + R0.H = 0x1; + R7.L = R0.L << 4; + DBGA ( R7.L , 0x0010 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R0.L = 0x8000; + R0.H = 0x1; + R7.L = R0.L >>> 4; + DBGA ( R7.L , 0xf800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R0.L = 0x0; + R0.H = 0x1; + R7.L = R0.L << 0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R7.H = R0.H >>> 4; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xf800 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R7.L = R0.H >>> 4; + DBGA ( R7.L , 0xf800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic shifts + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R7.L = R0.H >> 4; + DBGA ( R7.L , 0x0800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x1; + R7.H = R0.L << 4; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x0; + R0.H = 0x0; + R7.L = R0.L << 0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x1; + R0.H = 0x0; + R7.L = R0.L << 15; + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/tests/tcg/bfin/se_kills2.S b/tests/tcg/bfin/se_kills2.S new file mode 100644 index 0000000000000..73f9d28fc3ec6 --- /dev/null +++ b/tests/tcg/bfin/se_kills2.S @@ -0,0 +1,148 @@ +//Original:/proj/frio/dv/testcases/seq/se_kills2/se_kills2.dsp +// Description: Test se_kill for all supported types of RTL1 instructions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(selfcheck.inc) +include(std.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +SP = 0 (Z); +SP.L = KSTACK; // setup the stack pointer +SP.H = KSTACK; +FP = SP; // and frame pointer + +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +ASTAT = r0; // reset sequencer registers + +// +// The Main Program +// + +START: + + // **** YOUR CODE GOES HERE **** + // CHECK_INIT(p0, 0xFF7FFFFC); // original +CHECK_INIT_DEF(p0); + + R0 = 0; + R1 = 1; + R2 = 2; + R3 = 3; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + P1 = 11; + // Assume CC is reset to 0. +IF !CC JUMP NEXT1; // following instruction should be killed +RAISE 13; + +NEXT1: + IF !CC JUMP NEXT2; +EXCPT 15; + +NEXT2: + IF !CC JUMP NEXT3; + ( R7:0, P5:0 ) = [ SP ++ ]; + +NEXT3: + IF !CC JUMP NEXT4; + [ -- SP ] = ( R7:0, P5:0 ); + +NEXT4: + IF !CC JUMP NEXT5; +EMUEXCPT; + +NEXT5: + IF !CC JUMP NEXT6; +.dd 0xFACEBABE + +NEXT6: + IF !CC JUMP NEXT7; +LINK 12; + +NEXT7: + IF !CC JUMP NEXT8; +UNLINK; + +NEXT8: + IF !CC JUMP NEXT9; +LSETUP (NEXT10, NEXT11) lc0 = p0; + +NEXT9: + IF !CC JUMP NEXT10; + +NEXT10: + IF !CC JUMP NEXT11; + +NEXT11: + IF !CC JUMP NEXT12; + +NEXT12: + IF !CC JUMP NEXT13; + +NEXT13: + IF !CC JUMP NEXT14; + +NEXT14: + IF !CC JUMP NEXT15; + +NEXT15: + IF !CC JUMP NEXT16; + +NEXT16: + +END: +CHECKREG(r0, 0); +CHECKREG(r1, 1); +CHECKREG(r2, 2); +CHECKREG(r3, 3); +CHECKREG(r4, 4); +CHECKREG(r5, 5); +CHECKREG(r6, 6); +CHECKREG(r7, 7); + +dbg_pass; // Call Endtest Macro + +//********************************************************************* +// +// Data Segment +// + +//.data 0xF0000000 +.data +DATA: + .space (0x010); // Some data space + +// Stack Segments + + .space (STACKSIZE); +KSTACK: diff --git a/tests/tcg/bfin/se_rets_hazard.s b/tests/tcg/bfin/se_rets_hazard.s new file mode 100644 index 0000000000000..7406e8708fc66 --- /dev/null +++ b/tests/tcg/bfin/se_rets_hazard.s @@ -0,0 +1,55 @@ +//Original:/testcases/seq/se_rets_hazard/se_rets_hazard.dsp +# mach: bfin + +.include "testutils.inc" + start + + +BOOT: + FP = SP; // and frame pointer + + INIT_R_REGS 0; // initialize general purpose regs + + + + + ASTAT = r0; // reset sequencer registers + +// The Main Program + + +START: + loadsym r1, SUB1; + RETS = r1; + RTS; + +MID1: + CHECKREG r6, 0; // shouldn't be BAD + R6.L = 0xBAD2; // In case we come back to MID1 + loadsym P1, MID2; + CALL ( P1 ); + RTS; + +MID2: + loadsym R1, END; + RETS = r1; + [ -- SP ] = I0; + LINK 0; + I0 = FP; + UNLINK; + RTS; + +END: + + pass // Call Endtest Macro + +// Subroutines and Functions + +SUB1: // Code goes here + CHECKREG r7, 0; // should be if sub executed + R7.L = 0xBAD; // In case we come back to SUB1 + loadsym R2, MID1; + [ -- SP ] = R2; + RETS = [sp++]; + RTS; + R6.L = 0xBAD; diff --git a/tests/tcg/bfin/sign.s b/tests/tcg/bfin/sign.s new file mode 100644 index 0000000000000..072263e3fd4bc --- /dev/null +++ b/tests/tcg/bfin/sign.s @@ -0,0 +1,27 @@ +# Blackfin testcase for signbits +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_alu_signbits areg:req + \areg = 0; + R0 = 0x10 (Z); + \areg\().x = R0; + + imm32 r0, 0x60038; + + R0.L = SIGNBITS \areg; + + imm32 r1, 0x6fffa; + CC = R1 == R0; + if ! CC jump 1f; + .endm + + check_alu_signbits A0 + check_alu_signbits A1 + + pass +1: + fail diff --git a/tests/tcg/bfin/simple0.s b/tests/tcg/bfin/simple0.s new file mode 100644 index 0000000000000..956ce111d1b87 --- /dev/null +++ b/tests/tcg/bfin/simple0.s @@ -0,0 +1,10 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 5; + R0 += -1; + DBGA ( R0.L , 4 ); + pass diff --git a/tests/tcg/bfin/stk.s b/tests/tcg/bfin/stk.s new file mode 100644 index 0000000000000..451a11e280d94 --- /dev/null +++ b/tests/tcg/bfin/stk.s @@ -0,0 +1,78 @@ +# mach: bfin + +.include "testutils.inc" + start + + +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + _DBG P0; + SP = P0; + FP = P0; + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; + [ -- SP ] = ( R7:0, P5:0 ); + _DBG SP; + _DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R2.L , 3 ); + DBGA ( R7.L , 7 ); + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + + pass +abrt: + fail + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/tests/tcg/bfin/stk2.s b/tests/tcg/bfin/stk2.s new file mode 100644 index 0000000000000..d5cb9753bc927 --- /dev/null +++ b/tests/tcg/bfin/stk2.s @@ -0,0 +1,107 @@ +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. +# mach: bfin + + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + P1.L = 0x1000; +//DBG P0; +//DBG P1; + SP = P0; + FP = P0; + + CALL try; + + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; +// DBG; + [ -- SP ] = ( R7:0, P5:0 ); +// DBG SP; +// DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; +// DBG; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 0xfff9 ); + DBGA ( R4.L , 4 ); + DBGA ( R5.L , 5 ); + DBGA ( R6.L , 6 ); + DBGA ( R7.L , 7 ); + + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail + +try: + LINK 0; + [ -- SP ] = R7; + [ -- SP ] = R0; + R7 = 0x1234 (X); + [ -- SP ] = R7; + CALL bar; + SP += 4; + R0 = [ SP ++ ]; + R7 = [ SP ++ ]; + UNLINK; + RTS; + +bar: + R0 = [ SP ]; + DBGA ( R0.L , 0x1234 ); + RTS; + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/tests/tcg/bfin/stk3.s b/tests/tcg/bfin/stk3.s new file mode 100644 index 0000000000000..131f8c5190c81 --- /dev/null +++ b/tests/tcg/bfin/stk3.s @@ -0,0 +1,106 @@ +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. + +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + P1.L = 0x1000; + _DBG P0; + _DBG P1; + SP = P0; + FP = P0; + + CALL try; + + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; + [ -- SP ] = ( R7:0, P5:0 ); + _DBG SP; + _DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 0xfff9); + DBGA ( R4.L , 4 ); + DBGA ( R5.L , 5 ); + DBGA ( R6.L , 6 ); + DBGA ( R7.L , 7 ); + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail; + +try: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R7 = 0x1234 (X); + [ -- SP ] = R7; + CALL bar; + SP += 4; + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + +bar: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R0 = [ FP + 8 ]; + DBGA ( R0.L , 0x1234 ); + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/tests/tcg/bfin/stk4.s b/tests/tcg/bfin/stk4.s new file mode 100644 index 0000000000000..797aa78a10273 --- /dev/null +++ b/tests/tcg/bfin/stk4.s @@ -0,0 +1,110 @@ +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + P1.L = 0x1000; + _DBG P0; + _DBG P1; + SP = P0; + FP = P0; + + CALL try; + + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; + [ -- SP ] = ( R7:0, P5:0 ); + _DBG SP; + _DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 0xfff9 ); + DBGA ( R4.L , 4 ); + DBGA ( R5.L , 5 ); + DBGA ( R6.L , 6 ); + DBGA ( R7.L , 7 ); + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail; + +try: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R7 = 0x1234 (X); + [ -- SP ] = R7; + CALL bar; + R7 = [ SP ++ ]; + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + +bar: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R0 = [ FP + 8 ]; + DBGA ( R0.L , 0x1234 ); + CALL foo; + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + +foo: + DBGA ( R0.L , 0x1234 ); + RTS; + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/tests/tcg/bfin/stk5.s b/tests/tcg/bfin/stk5.s new file mode 100644 index 0000000000000..e3a8fcab3f02b --- /dev/null +++ b/tests/tcg/bfin/stk5.s @@ -0,0 +1,34 @@ +# mach: bfin + +.include "testutils.inc" + start + + SP += -12; + FP = SP; + CALL _foo; + + pass + + +_printf: + LINK 0; + [ -- SP ] = ( R7:7, P5:4 ); + R5 = [ FP + 8 ]; + DBGA ( R5.L , 0x1234 ); + R5 = [ FP + 12 ]; + DBGA ( R5.L , 0xdead ); + ( R7:7, P5:4 ) = [ SP ++ ]; + UNLINK; + RTS; + +_foo: + LINK 0; + R5 = 0xdead (Z); + [ -- SP ] = R5; + R5 = 0x1234 (X); + [ -- SP ] = R5; + CALL _printf; + P5 = 8; + SP = SP + P5; + UNLINK; + RTS; diff --git a/tests/tcg/bfin/stk6.s b/tests/tcg/bfin/stk6.s new file mode 100644 index 0000000000000..89a5e6046955b --- /dev/null +++ b/tests/tcg/bfin/stk6.s @@ -0,0 +1,58 @@ +// setup a dummy stack and put values in memory 0,1,2,3...n +// then restore registers with pop instruction. +# mach: bfin + +.include "testutils.inc" + start + + SP += -12; + + P1 = SP; + R1 = 0; + P5.L = 0xdead; + SP += -((8+5)*4); // lets move the stack pointer and include the current location. i.e. 5 + P4 = (8+6); // 8 data registers and 6 pointer registers are being stored. + LSETUP ( ls0 , le0 ) LC0 = P4; +ls0: + R1 += 1; +le0: + [ P1-- ] = R1; + + ( R7:0, P5:0 ) = [ SP ++ ]; + + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 4 ); + DBGA ( R4.L , 5 ); + DBGA ( R5.L , 6 ); + DBGA ( R6.L , 7 ); + DBGA ( R7.L , 8 ); + R0 = P0; DBGA ( R0.L , 9 ); + R0 = P1; DBGA ( R0.L , 10 ); + R0 = P2; DBGA ( R0.L , 11 ); + R0 = P3; DBGA ( R0.L , 12 ); + R0 = P4; DBGA ( R0.L , 13 ); + R0 = P5; DBGA ( R0.L , 14 ); + R0 = 1; + + [ -- SP ] = ( R7:0, P5:0 ); + ( R7:0, P5:0 ) = [ SP ++ ]; + + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 4 ); + DBGA ( R4.L , 5 ); + DBGA ( R5.L , 6 ); + DBGA ( R6.L , 7 ); + DBGA ( R7.L , 8 ); + R0 = P0; DBGA ( R0.L , 9 ); + R0 = P1; DBGA ( R0.L , 10 ); + R0 = P2; DBGA ( R0.L , 11 ); + R0 = P3; DBGA ( R0.L , 12 ); + R0 = P4; DBGA ( R0.L , 13 ); + R0 = P5; DBGA ( R0.L , 14 ); + R0 = 1; + + pass diff --git a/tests/tcg/bfin/tar10622.s b/tests/tcg/bfin/tar10622.s new file mode 100644 index 0000000000000..c3c0a37e7742f --- /dev/null +++ b/tests/tcg/bfin/tar10622.s @@ -0,0 +1,20 @@ +# mach: bfin + +.include "testutils.inc" + start + + r2.l = 0x1234; + r2.h = 0xff90; + + r4=8; + i2=r2; + m2 = 4; + a0 = 0; + r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; + + r0 = i2; + + dbga(r0.l, 0x1238); + dbga(r0.h, 0xff90); + + pass diff --git a/tests/tcg/bfin/test.h b/tests/tcg/bfin/test.h new file mode 100644 index 0000000000000..38788f8ea2ed4 --- /dev/null +++ b/tests/tcg/bfin/test.h @@ -0,0 +1,134 @@ +#ifndef __ASSEMBLER__ +typedef unsigned long bu32; +typedef long bs32; +typedef unsigned short bu16; +typedef short bs16; +typedef unsigned char bu8; +typedef char bs8; +#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) +#define BFIN_MMR_16(mmr) mmr, __pad_##mmr +#include "test-dma.h" +#else +#define __ADSPBF537__ /* XXX: Hack for .S files. */ +#endif +#ifndef __FDPIC__ +#include +#endif + +/* AZ AN AC0_COPY V_COPY CC AQ RND_MOD AC0 AC1 AV0 AV0S AV1 AV1S V VS */ + +#define _AZ (1 << 0) +#define _AN (1 << 1) +#define _AC0_COPY (1 << 2) +#define _V_COPY (1 << 3) +#define _CC (1 << 5) +#define _AQ (1 << 6) +#define _RND_MOD (1 << 8) +#define _AC0 (1 << 12) +#define _AC1 (1 << 13) +#define _AV0 (1 << 16) +#define _AV0S (1 << 17) +#define _AV1 (1 << 18) +#define _AV1S (1 << 19) +#define _V (1 << 24) +#define _VS (1 << 25) + +#define _SET 1 +#define _UNSET 0 + +#define PASS do { puts ("pass"); _exit (0); } while (0) +#define FAIL do { puts ("fail"); _exit (1); } while (0) +#define DBG_PASS do { asm volatile ("outc 'p'; outc 'a'; outc 's'; outc 's'; outc '\n'; hlt;"); } while (1) +#define DBG_FAIL do { asm volatile ("outc 'f'; outc 'a'; outc 'i'; outc 'l'; outc '\n'; abort;"); } while (1) + +#define HI(x) (((x) >> 16) & 0xffff) +#define LO(x) ((x) & 0xffff) + +#define INIT_R_REGS(val) init_r_regs val +#define INIT_P_REGS(val) init_p_regs val +#define INIT_B_REGS(val) init_b_regs val +#define INIT_I_REGS(val) init_i_regs val +#define INIT_L_REGS(val) init_l_regs val +#define INIT_M_REGS(val) init_m_regs val +#define include(...) +#define CHECK_INIT_DEF(...) nop; +#define CHECK_INIT(...) nop; +#define CHECKMEM32(...) +#define GEN_INT_INIT(...) nop; + +#define LD32_LABEL(reg, sym) loadsym reg, sym +#define LD32(reg, val) imm32 reg, val +#define CHECKREG(reg, val) CHECKREG reg, val +#define CHECKREG_SYM_JUMPLESS(reg, sym, scratch_reg) \ + loadsym scratch_reg, sym; \ + cc = reg == scratch_reg; \ + /* Need to avoid jumping for trace buffer. */ \ + if !cc jump fail_lvl; +#define CHECKREG_SYM(reg, sym, scratch_reg) \ + loadsym scratch_reg, sym; \ + cc = reg == scratch_reg; \ + if cc jump 9f; \ + dbg_fail; \ +9: + +#define WR_MMR(mmr, val, mmr_reg, val_reg) \ + imm32 mmr_reg, mmr; \ + imm32 val_reg, val; \ + [mmr_reg] = val_reg; +#define WR_MMR_LABEL(mmr, sym, mmr_reg, sym_reg) \ + loadsym sym_reg, sym; \ + imm32 mmr_reg, mmr; \ + [mmr_reg] = sym_reg; +#define RD_MMR(mmr, mmr_reg, val_reg) \ + imm32 mmr_reg, mmr; \ + val_reg = [mmr_reg]; + +/* Legacy CPLB bits */ +#define CPLB_L1_CACHABLE CPLB_L1_CHBL +#define CPLB_USER_RO CPLB_USER_RD + +#define DATA_ADDR_1 0xff800000 +#define DATA_ADDR_2 0xff900000 +#define DATA_ADDR_3 (DATA_ADDR_1 + 0x2000) + +/* The libgloss headers omit these defines. */ +#define EVT_OVERRIDE 0xFFE02100 +#define EVT_IMASK IMASK + +#define PAGE_SIZE_1K PAGE_SIZE_1KB +#define PAGE_SIZE_4K PAGE_SIZE_4KB +#define PAGE_SIZE_1M PAGE_SIZE_1MB +#define PAGE_SIZE_4M PAGE_SIZE_4MB + +#define CPLB_USER_RW (CPLB_USER_RD | CPLB_USER_WR) + +#define DMC_AB_SRAM 0x0 +#define DMC_AB_CACHE 0xc +#define DMC_ACACHE_BSRAM 0x8 + +#define CPLB_L1SRAM (1 << 5) +#define CPLB_DA0ACC (1 << 6) + +#define FAULT_CPLB0 (1 << 0) +#define FAULT_CPLB1 (1 << 1) +#define FAULT_CPLB2 (1 << 2) +#define FAULT_CPLB3 (1 << 3) +#define FAULT_CPLB4 (1 << 4) +#define FAULT_CPLB5 (1 << 5) +#define FAULT_CPLB6 (1 << 6) +#define FAULT_CPLB7 (1 << 7) +#define FAULT_CPLB8 (1 << 8) +#define FAULT_CPLB9 (1 << 9) +#define FAULT_CPLB10 (1 << 10) +#define FAULT_CPLB11 (1 << 11) +#define FAULT_CPLB12 (1 << 12) +#define FAULT_CPLB13 (1 << 13) +#define FAULT_CPLB14 (1 << 14) +#define FAULT_CPLB15 (1 << 15) +#define FAULT_READ (0 << 16) +#define FAULT_WRITE (1 << 16) +#define FAULT_USER (0 << 17) +#define FAULT_SUPV (1 << 17) +#define FAULT_DAG0 (0 << 18) +#define FAULT_DAG1 (1 << 18) +#define FAULT_ILLADDR (1 << 19) diff --git a/tests/tcg/bfin/testset.s b/tests/tcg/bfin/testset.s new file mode 100644 index 0000000000000..57eaa5cbbc954 --- /dev/null +++ b/tests/tcg/bfin/testset.s @@ -0,0 +1,73 @@ +# Blackfin testcase for playing with TESTSET +# mach: bfin + + .include "testutils.inc" + + start + + .macro _ts val:req + /* Load value to the external data storage */ + imm32 R0, \val + [P4] = R0; + FLUSHINV[P4]; + SSYNC; + mnop; + + imm32 R1, 0xdeadbeef + imm32 R2, 0xdeadbeef + + TESTSET (P4); + SSYNC; + mnop; + mnop; + + /* TESTSET will set CC based on low byte == 0 */ + .if \val & 0xff + if CC jump 1f; + .else + if ! CC jump 1f; + .endif + + /* Regardless of CC, the byte MSB is set to 1 */ + imm32 R1, \val | 0x80 + + /* Make sure the result is what we want */ + R2 = [P4]; + FLUSHINV[P4]; + SSYNC; + mnop; + CC = R2 == R1; + if ! CC jump 1f; + jump 2f; +1: fail +2: + .endm + .macro ts val:req + _ts \val + _ts ~(\val) + .endm + + loadsym P4, _data + + ts 0x00000000 + ts 0x00000011 + ts 0x11111111 + ts 0x11111101 + ts 0x11111110 + ts 0x111111bb + ts 0xaaaaaa00 + ts 0xabcd2222 + ts 0x000000bb + ts 0x55555555 + ts 0x5555550a + ts 0x00100010 + ts 0x00100100 + ts 0x33333000 + ts 0x000000aa + + pass + +.data +_data: +.long 0 +.size _data, .-_data diff --git a/tests/tcg/bfin/testset2.s b/tests/tcg/bfin/testset2.s new file mode 100644 index 0000000000000..66b50be391241 --- /dev/null +++ b/tests/tcg/bfin/testset2.s @@ -0,0 +1,37 @@ +// testset instruction +//TESTSET is an atomic test-and-set. +//If the lock was not set prior to the TESTSET, cc is set, the lock bit is set, +//and this processor gets the lock. If the lock was set +//prior to the TESTSET, cc is cleared, the lock bit is still set, +//but the processor fails to acquire the lock. +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, datalabel; + + R0 = 0; + CC = R0; + R0 = B [ P0 ] (Z); + DBGA ( R0.L , 0 ); + TESTSET ( P0 ); + R0 = CC; + DBGA ( R0.L , 1 ); + R0 = B [ P0 ] (Z); + DBGA ( R0.L , 0x80 ); + + R0 = 0; + CC = R0; + TESTSET ( P0 ); + R0 = CC; + DBGA ( R0.L , 0 ); + R0 = B [ P0 ] (Z); + DBGA ( R0.L , 0x80 ); + + pass + + .data +datalabel: + .dw 0 diff --git a/tests/tcg/bfin/testutils.inc b/tests/tcg/bfin/testutils.inc new file mode 100644 index 0000000000000..0bcb407731997 --- /dev/null +++ b/tests/tcg/bfin/testutils.inc @@ -0,0 +1,258 @@ +# R0 and P0 are used as tmps, consider them call clobbered by these macros. + +# To build for hardware, use: +# bfin-linux-uclibc-gcc -nostdlib -g -Wa,--defsym,BFIN_HOST=1 foo.s + + .macro start + .text + # Pad with EMUEXCPT to make sure "jump to 0" always fails +__panic: + .rep 0xf + .word 0x0025 + .endr + abort; + jump __panic; + + .global __pass +__pass: + write 1, _passmsg, 5 + exit 0 +.ifdef BFIN_JTAG +__emu_out: + /* DBGSTAT */ + P0.L = 0x5008; + P0.H = 0xFFE0; +1: + R7 = [P0]; + CC = BITTST (R7,0); + IF CC JUMP 1b; + EMUDAT = R0; +2: + R7 = [P0]; + CC = BITTST (R7,0); + IF CC JUMP 2b; + RTS; +.endif + .global __fail +__fail: +.ifndef BFIN_HOST + P0.H = _rets; + P0.L = _rets; + R0 = RETS; + R0 += -4; + P1 = 8; + R2 = '9'; + LSETUP (1f, 3f) LC0 = P1; +1: + R1 = R0; + R1 >>= 28; + R1 += 0x30; + CC = R2 < R1; + IF !CC jump 2f; + R1 += 7; +2: + B[P0++] = R1; +3: + R0 <<= 4; + + write 1, _failmsg, 22 +.else + write 1, _failmsg, 5 +.endif + exit 1 + +.ifndef BFIN_HOST + .data +_failmsg: + .ascii "fail at PC=0x" +_rets: + .ascii "12345678\n" +_passmsg: + .ascii "pass\n" + .align 4 +_params: + .long 0 + .long 0 + .long 0 + .long 0 + + .text + .global __start +__start: +.else +.global ___uClibc_main; +___uClibc_main: +.global _main; +_main: +.endif + .endm + + .macro system_call nr:req + P0 = \nr (X); + EXCPT 0; + .endm + + .macro exit rc:req + R0 = \rc (X); +.ifndef BFIN_HOST + P0.H = _params; + P0.L = _params; + [P0] = R0; + R0 = P0; +.endif + system_call 1 + .endm + + .macro pass + dbg_pass +# CALL __pass; + .endm + + .macro fail + dbg_fail +# CALL __fail; + .endm + + .macro write fd:req, buf:req, count:req +.ifndef BFIN_HOST + P0.H = _params; + P0.L = _params; + R0 = \fd (X); + [P0] = R0; + R0.H = \buf; + R0.L = \buf; + [P0 + 4] = R0; + R0 = \count (X); + [P0 + 8] = R0; + R0 = P0; + system_call 5 +.endif + .endm + + .macro outc_str ch:req, more:vararg + OUTC \ch; + .ifnb \more + outc_str \more + .endif + .endm + .macro dbg_pass +.ifdef BFIN_JTAG + R0 = 6; + CALL __emu_out; + R0.L = 0x6170; /* 'p'=0x70 'a'=0x70 */ + R0.H = 0x7373; /* 's'=0x73 */ + CALL __emu_out; + + R0.L = 0x0A; /* newline */ + R0.H = 0x0000; + CALL __emu_out; +1: + EMUEXCPT; + JUMP 1b; +.else + outc_str 'p', 'a', 's', 's', '\n' + HLT; +.endif + .endm + .macro dbg_fail +.ifdef BFIN_JTAG + R0 = 6; + CALL __emu_out; + R0.L = 0x6166; /* 'f'=0x66 'a'=0x61 */ + R0.H = 0x6c69; /* 'i'=0x69 'l'=0x6c */ + CALL __emu_out; + + R0.L = 0x0A; /* newline */ + R0.H = 0x0000; + CALL __emu_out; +1: + EMUEXCPT; + JUMP 1b; +.else + outc_str 'f', 'a', 'i', 'l', '\n' +.endif + ABORT; + .endm + + .macro imm32 reg:req, val:req + \reg\().L = ((\val) & 0xffff); + \reg\().H = (((\val) >> 16) & 0xffff); + .endm + + .macro dmm32 reg:req, val:req + [--SP] = R0; + imm32 R0, \val + \reg = R0; + R0 = [SP++]; + .endm + +.ifndef BFIN_HOST + .macro loadsym reg:req, sym:req, offset=0 + \reg\().L = (\sym\() + \offset\()); + \reg\().H = (\sym\() + \offset\()); + .endm +.else + .macro loadsym reg:req, sym:req, offset=0 + [--SP] = R0; + R0 = [P3 + \sym\()@GOT17M4]; + .if \offset + [--SP] = R1; + R1 = \offset\() (Z); + R0 = R0 + R1; + R1 = [SP++]; + .endif + \reg = R0; + R0 = [SP++]; + .endm +.endif + + .macro CHECKREG reg:req, val:req + DBGA (\reg\().L, ((\val) & 0xffff)); + DBGA (\reg\().H, (((\val) >> 16) & 0xffff)); + .endm + + .macro __init_regs reg:req, max:req, x:req, val:req + .ifle (\x - \max) + \reg\()\x\().L = ((\val) & 0xffff); + \reg\()\x\().H = (((\val) >> 16) & 0xffff); + .endif + .endm + .macro _init_regs reg:req, max:req, val:req + __init_regs \reg, \max, 0, \val + __init_regs \reg, \max, 1, \val + __init_regs \reg, \max, 2, \val + __init_regs \reg, \max, 3, \val + __init_regs \reg, \max, 4, \val + __init_regs \reg, \max, 5, \val + __init_regs \reg, \max, 6, \val + __init_regs \reg, \max, 7, \val + .endm + + .macro init_r_regs val:req + _init_regs R, 7, \val + .endm + .macro init_p_regs val:req + _init_regs P, 5, \val + .endm + .macro init_b_regs val:req + _init_regs B, 3, \val + .endm + .macro init_i_regs val:req + _init_regs I, 3, \val + .endm + .macro init_l_regs val:req + _init_regs L, 3, \val + .endm + .macro init_m_regs val:req + _init_regs M, 3, \val + .endm + + // the test framework needs things to be quiet, so don't + // print things out by default. + .macro _DBG reg:req + //DBG \reg; + .endm + + .macro _DBGCMPLX reg:req + // + .endm diff --git a/tests/tcg/bfin/vec-abs.S b/tests/tcg/bfin/vec-abs.S new file mode 100644 index 0000000000000..97ec84f0904a7 --- /dev/null +++ b/tests/tcg/bfin/vec-abs.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0xcdef; + R1 = ABS R0 (V); + R7 = ASTAT; + R2.H = 0x1234; + R2.L = 0x3211; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN|_V|_V_COPY); + R3.L = LO(_AZ|_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: */ + R3.H = HI(0); + R3.L = LO(0); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/tests/tcg/bfin/vecadd.s b/tests/tcg/bfin/vecadd.s new file mode 100644 index 0000000000000..7e568ec5df23d --- /dev/null +++ b/tests/tcg/bfin/vecadd.s @@ -0,0 +1,65 @@ +# mach: bfin + +.include "testutils.inc" + start + +// create two short vectors v_a, v_b +// where each element of v_a is the index +// where each element of v_b is 128-index + R2 = 0; + loadsym P0, v_a; + loadsym P1, v_b; + P2 = 0; + R3 = 128 (X); + R0 = 0; + R1 = 128 (X); +L$1: + W [ P0 ++ ] = R0; + W [ P1 ++ ] = R1; + R0 += 1; + R1 += -1; + CC = R0 < R3; + IF CC JUMP L$1 (BP); + + loadsym P0, v_a; + loadsym P1, v_b; + + CALL vecadd; + + loadsym P0, v_c; + R2 = 0; + R3 = 128 (X); +L$3: + R0 = W [ P0 ++ ] (X); + DBGA ( R0.L , 128 ); + R2 += 1; + CC = R2 < R3; + IF CC JUMP L$3; + _DBG R6; + pass + +vecadd: + + loadsym I0, v_a; + loadsym I1, v_b; + loadsym I2, v_c; + + P5 = 128 (X); + LSETUP ( L$2 , L$2end ) LC0 = P5 >> 1; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; +L$2: + R2 = R0 +|+ R1 || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; +L$2end: + [ I2 ++ ] = R2; + + + RTS; + + .data +v_a: + .space (512); +v_b: + .space (512); +v_c: + .space (512); diff --git a/tests/tcg/bfin/vit_max.s b/tests/tcg/bfin/vit_max.s new file mode 100644 index 0000000000000..35eaa41790c11 --- /dev/null +++ b/tests/tcg/bfin/vit_max.s @@ -0,0 +1,57 @@ +# Blackfin testcase for VIT_MAX (taken from PRM) +# mach: bfin + + .include "testutils.inc" + + start + + imm32 R3, 0xFFFF0000 + imm32 R2, 0x0000FFFF + A0 = 0; + R5 = VIT_MAX (R3, R2) (ASL); + R4 = 0 (x); + CC = R5 == R4; + IF !CC JUMP 1f; + imm32 R6, 0x00000002 + R4 = A0; + CC = R4 == R6; + IF !CC JUMP 1f; + + imm32 R1, 0xFEEDBEEF + imm32 R0, 0xDEAF0000 + A0 = 0; + R7 = VIT_MAX (R1, R0) (ASR); + imm32 R4, 0xFEED0000 + CC = R4 == R7; + IF !CC JUMP 1f; + imm32 R6, 0x80000000 + R2 = A0.W; + CC = R2 == R6; + IF !CC JUMP 1f; + + imm32 R1, 0xFFFF0000 + A0 = 0; + R3.L = VIT_MAX (R1) (ASL); + R3 = R3.L; + R4 = 0 (x); + CC = R3 == R4; + IF !CC JUMP 1f; + R6 = A0.W; + CC = R6 == R4; + IF !CC JUMP 1f; + + imm32 R1, 0x1234FADE + imm32 R2, 0xFFFFFFFF + A0.W = R2; + R3.L = VIT_MAX (R1) (ASR); + R3 = R3.L; + imm32 R4 0x00001234 + CC = R4 == R3; + IF !CC JUMP 1f; + imm32 R7, 0xFFFFFFFF + R0 = A0.W; + CC = R7 == R0; + IF !CC JUMP 1f; + + pass +1: fail diff --git a/tests/tcg/bfin/wtf.s b/tests/tcg/bfin/wtf.s new file mode 100644 index 0000000000000..2ec850754b1e2 --- /dev/null +++ b/tests/tcg/bfin/wtf.s @@ -0,0 +1,26 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym p0, foo; + r2 = p0; + r2 += 4; + [p0++]=p0; + loadsym i0, foo; + r0=[i0]; + R3 = P0; + CC = R2 == R3 + if ! CC jump _fail; + R3 = I0; + CC = R0 == R3; + if ! CC jump _fail; + +_halt0: + pass; +_fail: + fail; + + .data +foo: + .space (0x10) diff --git a/tests/tcg/bfin/zcall.s b/tests/tcg/bfin/zcall.s new file mode 100644 index 0000000000000..bdb82c76c3d12 --- /dev/null +++ b/tests/tcg/bfin/zcall.s @@ -0,0 +1,44 @@ +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + CALL _foo; + pass + +___main: + RTS; + +_m1: + LINK 0; + R7 = [ FP + 8 ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R7.L , 3 ); + UNLINK; + RTS; + +_m2: + LINK 0; + R7 = [ FP + 8 ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R7.L , 3 ); + [ -- SP ] = R7; + CALL _m1; + SP += 4; + UNLINK; + RTS; + +_foo: + LINK 0; + CALL ___main; + R7 = 3; + [ -- SP ] = R7; + R0 = 1; + R1 = 2; + CALL _m2; + SP += 4; + UNLINK; + RTS; diff --git a/trace-events b/trace-events index 616cc5237808f..68340c4eb2ece 100644 --- a/trace-events +++ b/trace-events @@ -104,6 +104,10 @@ monitor_protocol_event_emit(uint32_t event, void *data) "event=%d data=%p" monitor_protocol_event_queue(uint32_t event, void *qdict, uint64_t rate) "event=%d data=%p rate=%" PRId64 monitor_protocol_event_throttle(uint32_t event, uint64_t rate) "event=%d rate=%" PRId64 +# hw/bfin_*.c +bfin_reg_memory_read(uint32_t addr, const char *name, unsigned size) "read 0x%08x (%s) length %u" +bfin_reg_memory_write(uint32_t addr, const char *name, unsigned size, uint32_t value) "write 0x%08x (%s) length %u with 0x%x" + # dma-helpers.c dma_blk_io(void *dbs, void *bs, int64_t offset, bool to_dev) "dbs=%p bs=%p offset=%" PRId64 " to_dev=%d" dma_aio_cancel(void *dbs) "dbs=%p" diff --git a/util/log.c b/util/log.c index 54b54e868aab5..5f2fc67385a9f 100644 --- a/util/log.c +++ b/util/log.c @@ -265,12 +265,12 @@ const QEMULogItem qemu_log_items[] = { { LOG_UNIMP, "unimp", "log unimplemented functionality" }, { LOG_GUEST_ERROR, "guest_errors", - "log when the guest OS does something invalid (eg accessing a\n" + "log when the guest OS does something invalid (eg accessing a " "non-existent register)" }, { CPU_LOG_PAGE, "page", "dump pages at beginning of user mode emulation" }, { CPU_LOG_TB_NOCHAIN, "nochain", - "do not chain compiled TBs so that \"exec\" and \"cpu\" show\n" + "do not chain compiled TBs so that \"exec\" and \"cpu\" show " "complete traces" }, { 0, NULL, NULL }, }; @@ -327,12 +327,36 @@ int qemu_str_to_log_mask(const char *str) void qemu_print_log_usage(FILE *f) { const QEMULogItem *item; + int name_len, help_len, disp_len, wrap_len = 80; + char help[wrap_len + 1]; + fprintf(f, "Log items (comma separated):\n"); + + name_len = 0; + for (item = qemu_log_items; item->mask != 0; item++) { + name_len = MAX(strlen(item->name), name_len); + } +#ifdef CONFIG_TRACE_LOG + name_len = MAX(strlen("trace:PATTERN"), name_len); +#endif + help_len = wrap_len - name_len - 1; + for (item = qemu_log_items; item->mask != 0; item++) { - fprintf(f, "%-15s %s\n", item->name, item->help); + disp_len = snprintf(help, help_len, "%s", item->help); + if (disp_len >= help_len) { + char *space = strrchr(help, ' '); + *space = '\0'; + disp_len = space - help + 1; + } else { + disp_len = 0; + } + fprintf(f, "%-*s %s\n", name_len, item->name, help); + if (disp_len) { + fprintf(f, "%-*s %s\n", name_len, "", item->help + disp_len - 1); + } } #ifdef CONFIG_TRACE_LOG - fprintf(f, "trace:PATTERN enable trace events\n"); - fprintf(f, "\nUse \"-d trace:help\" to get a list of trace events.\n\n"); + fprintf(f, "%-*s %s\n", name_len, "trace:PATTERN", "enable trace events"); + fprintf(f, "\nUse \"-d trace:help\" to get a list of trace events.\n"); #endif }