Fixed cyclic loop thing

Author: djns1

ODIN_II/SRC/netlist_create_from_ast.cpp

@@ -3128,10 +3128,6 @@ void terminate_registered_assignment(ast_node_t* always_node, signal_list_t* ass
             npin_t* ff_output_pin = allocate_npin();
             add_output_pin_to_node(ff_node, ff_output_pin, 0);
 
-            if (net->num_driver_pins > 0) {
-                warning_message(NETLIST, always_node->line_number, always_node->file_number,
-                              "You've defined the driver \"%s\" twice\nThis may happen if you use inout or assign multiple times", get_pin_name(pin->name));
-            }
             add_driver_pin_to_net(net, ff_output_pin);
 
             verilog_netlist->ff_nodes = (nnode_t**)vtr::realloc(verilog_netlist->ff_nodes, sizeof(nnode_t*) * (verilog_netlist->num_ff_nodes + 1));

ODIN_II/SRC/output_blif.cpp

@@ -52,6 +52,28 @@ void define_ff(nnode_t* node, FILE* out);
 void define_decoded_mux(nnode_t* node, FILE* out);
 void output_blif_pin_connect(nnode_t* node, FILE* out);
 
+static void replace_input_names(nnode_t* node, long pin_idx) {
+    oassert(pin_idx < node->num_input_pins);
+    nnet_t* net = node->input_pins[pin_idx]->net;
+    if (!net->num_driver_pins) {
+        // Add a warning for an undriven net.
+        int line_number = node->related_ast_node ? node->related_ast_node->line_number : 0;
+        warning_message(NETLIST, line_number, -1,
+                        "Net %s driving node %s is itself undriven.",
+                        net->name, node->name);
+    }
+
+    for (int i = 0; i < net->num_driver_pins; i++) {
+        if (net->driver_pins[i]->name != NULL && ((net->driver_pins[i]->node->type == MULTIPLY) || (net->driver_pins[i]->node->type == HARD_IP) || (net->driver_pins[i]->node->type == MEMORY) || (net->driver_pins[i]->node->type == ADD) || (net->driver_pins[i]->node->type == MINUS))) {
+            vtr::free(net->driver_pins[i]->name);
+            net->driver_pins[i]->name = vtr::strdup(node->name);
+        } else {
+            vtr::free(net->driver_pins[i]->node->name);
+            net->driver_pins[i]->node->name = vtr::strdup(node->name);
+        }
+    }
+}
+
 static void print_input_pin(FILE* out, nnode_t* node, long pin_idx) {
     oassert(pin_idx < node->num_input_pins);
     nnet_t* net = node->input_pins[pin_idx]->net;
@@ -66,7 +88,7 @@ static void print_input_pin(FILE* out, nnode_t* node, long pin_idx) {
     }
 
     for (int i = 0; i < net->num_driver_pins; i++) {
-        if (!net->driver_pins[0]->node) {
+        if (!net->driver_pins[i]->node) {
             // Add a warning for an undriven net.
             int line_number = node->related_ast_node ? node->related_ast_node->line_number : 0;
             warning_message(NETLIST, line_number, -1,
@@ -170,25 +192,20 @@ void output_blif(FILE* out, netlist_t* netlist) {
     fprintf(out, "\n.names gnd\n.names unconn\n.names vcc\n1\n");
     fprintf(out, "\n");
 
+
+    /* replace the names of intermediate nodes with output */
+    for (long i = 0; i < netlist->num_top_output_nodes; i++) {
+        nnode_t* node = netlist->top_output_nodes[i];
+        replace_input_names(node, 0);
+    }
+
     /* traverse the internals of the flat net-list */
     if (strcmp(configuration.output_type.c_str(), "blif") == 0) {
         depth_first_traversal_to_output(OUTPUT_TRAVERSE_VALUE, out, netlist);
     } else {
         error_message(NETLIST, 0, -1, "%s", "Invalid output file type.");
     }
 
-    /* connect all the outputs up to the last gate */
-    for (long i = 0; i < netlist->num_top_output_nodes; i++) {
-        nnode_t* node = netlist->top_output_nodes[i];
-
-        fprintf(out, ".names");
-        print_input_pin(out, node, 0);
-        print_output_pin(out, node);
-        fprintf(out, "\n");
-
-        fprintf(out, "1 1\n\n");
-    }
-
     /* finish off the top level module */
     fprintf(out, ".end\n");
     fprintf(out, "\n");

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic.v

@@ -1,7 +1,4 @@
-module inout_basic(dir, out1, out2);
-    input dir;
-    inout out1;
-    inout out2;
-    assign out2 = (dir) ? out1 : 1'bz;
-    assign out1 = (!dir) ? out2 : 1'bz;
-endmodule
+module inout_basic(input dir, inout io, output out);
+    assign io = (dir) ? dir : 1'bz;
+    assign out = (!dir) ? io : 1'bx;
+endmodule

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic_input

@@ -1,9 +1,9 @@
-GLOBAL_SIM_BASE_CLK dir out1 out2
-0 1 0 0
-0 1 0 1
-0 1 1 0
-0 1 1 1
-0 0 0 0
-0 0 0 1
-0 0 1 0
-0 0 1 1
+GLOBAL_SIM_BASE_CLK dir io
+0 1 0
+0 1 0
+0 1 1
+0 1 1
+0 0 0
+0 0 0
+0 0 1
+0 0 1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic_output

@@ -1,10 +1,9 @@
-out1 out2
+io out
+1 x
+1 x
+1 x
+1 x
 0 0
 0 0
-0 1
-0 1
-0 0
-1 1
-0 0
 1 1
 1 1