Implemented InOuts

Author: djns1

ODIN_II/SRC/ast_elaborate.cpp

@@ -2656,11 +2656,11 @@ void create_param_table_for_scope(ast_node_t* module_items, sc_hierarchy* local_
                     /* symbols are already dealt with */
                     if (var_declare->types.variable.is_input
                         || var_declare->types.variable.is_output
+                        || var_declare->types.variable.is_inout
                         || var_declare->types.variable.is_reg
                         || var_declare->types.variable.is_genvar
                         || var_declare->types.variable.is_wire
                         || var_declare->types.variable.is_defparam)
-
                         continue;
 
                     oassert(module_items->children[i]->children[j]->type == VAR_DECLARE);

ODIN_II/SRC/netlist_create_from_ast.cpp

@@ -296,7 +296,8 @@ nnet_t* allocate_nnet() {
  *-------------------------------------------------------------------------------------------*/
 nnet_t* free_nnet(nnet_t* to_free) {
     if (to_free) {
-        to_free->fanout_pins = (npin_t**)vtr::free(to_free->fanout_pins);
+        if (to_free->num_fanout_pins)
+            to_free->fanout_pins = (npin_t**)vtr::free(to_free->fanout_pins);
 
         if (to_free->name)
             vtr::free(to_free->name);

ODIN_II/SRC/netlist_utils.cpp

@@ -65,25 +65,24 @@ static bool warn_undriven(nnode_t* node, nnet_t* net) {
     return false;
 }
 
-// TODO Uncomment this for In Outs
-//static void merge_with_inputs(nnode_t* node, long pin_idx) {
-//    oassert(pin_idx < node->num_input_pins);
-//    nnet_t* net = node->input_pins[pin_idx]->net;
-//    warn_undriven(node, net);
-//    // Merge node with all inputs with fanout of 1
-//    if (net->num_fanout_pins <= 1) {
-//        for (int i = 0; i < net->num_driver_pins; i++) {
-//            npin_t* driver = net->driver_pins[i];
-//            if (driver->name != NULL && ((driver->node->type == MULTIPLY) || (driver->node->type == HARD_IP) || (driver->node->type == MEMORY) || (driver->node->type == ADD) || (driver->node->type == MINUS))) {
-//                vtr::free(driver->name);
-//                driver->name = vtr::strdup(node->name);
-//            } else {
-//                vtr::free(driver->node->name);
-//                driver->node->name = vtr::strdup(node->name);
-//            }
-//        }
-//    }
-//}
+static void merge_with_inputs(nnode_t* node, long pin_idx) {
+    oassert(pin_idx < node->num_input_pins);
+    nnet_t* net = node->input_pins[pin_idx]->net;
+    warn_undriven(node, net);
+    // Merge node with all inputs with fanout of 1
+    if (net->num_fanout_pins <= 1) {
+        for (int i = 0; i < net->num_driver_pins; i++) {
+            npin_t* driver = net->driver_pins[i];
+            if (driver->name != NULL && ((driver->node->type == MULTIPLY) || (driver->node->type == HARD_IP) || (driver->node->type == MEMORY) || (driver->node->type == ADD) || (driver->node->type == MINUS))) {
+                vtr::free(driver->name);
+                driver->name = vtr::strdup(node->name);
+            } else {
+                vtr::free(driver->node->name);
+                driver->node->name = vtr::strdup(node->name);
+            }
+        }
+    }
+}
 
 static void print_net_driver(FILE* out, nnode_t* node, nnet_t* net, long driver_idx) {
     oassert(driver_idx < net->num_driver_pins);
@@ -221,14 +220,13 @@ void output_blif(FILE* out, netlist_t* netlist) {
     fprintf(out, "\n.names gnd\n.names unconn\n.names vcc\n1\n");
     fprintf(out, "\n");
 
-    // TODO Uncomment this for In Outs
     // connect all the outputs up to the last gate
-    // for (long i = 0; i < netlist->num_top_output_nodes; i++) {
-    //     nnode_t* node = netlist->top_output_nodes[i];
-    //     for (int j = 0; j < node->num_input_pins; j++) {
-    //         merge_with_inputs(node, j);
-    //     }
-    // }
+    for (long i = 0; i < netlist->num_top_output_nodes; i++) {
+        nnode_t* node = netlist->top_output_nodes[i];
+        for (int j = 0; j < node->num_input_pins; j++) {
+            merge_with_inputs(node, j);
+        }
+    }
 
     /* traverse the internals of the flat net-list */
     if (strcmp(configuration.output_type.c_str(), "blif") == 0) {

ODIN_II/SRC/output_blif.cpp

@@ -16,6 +16,7 @@ arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
 circuits_dir=regression_test/benchmark/verilog/
 
 circuit_list_add=syntax/*.v
+circuit_list_add=syntax/inout-syntax/*.v
 
 synthesis_parse_file=regression_test/parse_result/conf/synth.toml
 simulation_parse_file=regression_test/parse_result/conf/sim.toml

ODIN_II/SRC/parse_making_ast.cpp

@@ -0,0 +1,8 @@
+module simple_op(in_out1,in_out2,en);
+	inout in_out1;
+	inout in_out2;
+	input  en;
+
+	assign in_out1 = (en) ? in_out2 : 1'bz;
+	assign in_out2 = (!en) ? in_out1 : 1'bz;
+endmodule

ODIN_II/regression_test/benchmark/task/syntax/task.conf

@@ -0,0 +1,7 @@
+GLOBAL_SIM_BASE_CLK en in_out1 in_out2
+0 1 z z
+1 0 z z
+0 1 z 0
+1 1 z 1
+0 0 1 z
+1 0 0 z

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout.v

@@ -0,0 +1,7 @@
+in_out1 in_out2
+0 0
+1 1
+0 0
+0 x
+1 1
+x 1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout_input

@@ -0,0 +1,4 @@
+module inout_basic(input dir, inout io, output out);
+    assign io = (dir) ? dir : 1'bz;
+    assign out = (!dir) ? io : 1'bx;
+endmodule