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1 | | -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_outputs num_memories num_mult vpr_revision vpr_status max_vpr_mem num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height device_limiting_resources pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time |
2 | | -EArch.xml diffeq2.v common_-vpr_cluster_seed_type_blend 18.11 0.01 6864 37 0.00 -1 -1 32620 -1 -1 18 66 96 0 5 41106a6 success 53772 787 599 456 185 16 16 mult_36 0.32 7121 0.75 11.911 -741.335 -11.911 46 11188 24 1.21132e+07 2.95009e+06 786648. 3072.85 15.33 9045 31 13.5401 -906.141 -13.5401 0 0 1.01260e+06 3955.47 1.12 |
3 | | -EArch.xml diffeq2.v common_-vpr_cluster_seed_type_timing 15.14 0.01 6868 37 0.01 -1 -1 32532 -1 -1 18 66 96 0 5 41106a6 success 53732 787 599 455 185 16 16 mult_36 0.32 7198 0.76 11.4848 -739.971 -11.4848 54 11301 23 1.21132e+07 2.95009e+06 903890. 3530.82 12.53 8323 25 13.0434 -878.425 -13.0434 0 0 1.17254e+06 4580.24 0.88 |
4 | | -EArch.xml diffeq2.v common_-vpr_cluster_seed_type_max_inputs 12.92 0.01 6860 37 0.00 -1 -1 32620 -1 -1 17 66 96 0 5 41106a6 success 53880 787 599 455 184 16 16 mult_36 0.32 6117 0.80 11.466 -708.661 -11.466 54 9641 22 1.21132e+07 2.8962e+06 903890. 3530.82 10.13 8279 23 13.069 -865.82 -13.069 0 0 1.17254e+06 4580.24 1.04 |
5 | | -EArch.xml diffeq2.v common_-vpr_cluster_seed_type_max_pins 27.71 0.01 6852 37 0.01 -1 -1 32576 -1 -1 18 66 96 0 5 41106a6 success 54008 787 599 455 185 16 16 mult_36 0.32 6437 0.76 11.3718 -717.272 -11.3718 68 10365 35 1.21132e+07 2.95009e+06 1.14646e+06 4478.35 25.01 7906 25 13.2966 -878.535 -13.2966 0 0 1.41383e+06 5522.77 1.00 |
6 | | -EArch.xml diffeq2.v common_-vpr_cluster_seed_type_max_input_pins 16.35 0.01 6868 37 0.00 -1 -1 32528 -1 -1 18 66 96 0 5 41106a6 success 54008 787 599 455 185 16 16 mult_36 0.34 6434 0.82 11.3848 -718.622 -11.3848 56 10729 22 1.21132e+07 2.95009e+06 941869. 3679.18 13.66 8756 25 13.2369 -890.17 -13.2369 0 0 1.19778e+06 4678.85 0.91 |
7 | | -EArch.xml diffeq2.v common_-vpr_cluster_seed_type_blend2 14.27 0.01 6912 37 0.00 -1 -1 32576 -1 -1 18 66 96 0 5 41106a6 success 53944 787 599 455 185 16 16 mult_36 0.32 7191 0.75 11.5639 -729.893 -11.5639 52 9933 27 1.21132e+07 2.95009e+06 870783. 3401.49 11.63 8660 26 12.9662 -879.727 -12.9662 0 0 1.14646e+06 4478.35 0.91 |
| 1 | +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time |
| 2 | +EArch.xml diffeq2.v common_--cluster_seed_type_blend 7.77 vpr 70.11 MiB -1 -1 0.13 30276 4 0.09 -1 -1 37792 -1 -1 22 66 0 5 success v8.0.0-12803-g53682df9f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-06-13T11:40:41 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/tasks 71792 66 96 778 595 1 467 189 16 16 256 mult_36 auto 30.9 MiB 0.18 6722.15 3891 46259 15236 26537 4486 70.1 MiB 0.21 0.00 13.5168 11.9463 -726.84 -11.9463 11.9463 0.17 0.000859881 0.000798767 0.0863921 0.0798929 -1 -1 -1 -1 50 9393 37 1.21132e+07 3.16567e+06 843554. 3295.13 5.97 0.44117 0.406703 28144 172338 -1 8041 25 4342 9182 1554645 412555 13.3426 13.3426 -843.398 -13.3426 0 0 1.08719e+06 4246.82 0.03 0.23 0.08 -1 -1 0.03 0.0535264 0.0503363 |
| 3 | +EArch.xml diffeq2.v common_--cluster_seed_type_timing 6.38 vpr 70.26 MiB -1 -1 0.13 30528 4 0.09 -1 -1 37520 -1 -1 22 66 0 5 success v8.0.0-12803-g53682df9f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-06-13T11:40:41 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/tasks 71944 66 96 778 595 1 467 189 16 16 256 mult_36 auto 31.2 MiB 0.17 6551.83 3838 46801 14809 27260 4732 70.3 MiB 0.20 0.00 12.92 11.8188 -739.714 -11.8188 11.8188 0.17 0.000840177 0.000779322 0.0790155 0.0732691 -1 -1 -1 -1 50 10463 42 1.21132e+07 3.16567e+06 843554. 3295.13 4.51 0.457076 0.422458 28144 172338 -1 8387 41 5076 10467 1996440 537771 13.1972 13.1972 -879.638 -13.1972 0 0 1.08719e+06 4246.82 0.03 0.32 0.08 -1 -1 0.03 0.0798874 0.0744191 |
| 4 | +EArch.xml diffeq2.v common_--cluster_seed_type_max_inputs 7.20 vpr 70.34 MiB -1 -1 0.12 30656 4 0.09 -1 -1 37772 -1 -1 22 66 0 5 success v8.0.0-12803-g53682df9f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-06-13T11:40:41 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/tasks 72032 66 96 778 595 1 464 189 16 16 256 mult_36 auto 31.3 MiB 0.25 6680.33 3925 37045 11183 22036 3826 70.3 MiB 0.17 0.00 13.2078 11.9632 -729.997 -11.9632 11.9632 0.16 0.000875262 0.000812788 0.0668861 0.0621859 -1 -1 -1 -1 52 9408 33 1.21132e+07 3.16567e+06 870783. 3401.49 5.41 0.430744 0.397471 28652 182587 -1 8138 20 3194 6396 1293703 361722 12.8462 12.8462 -830.388 -12.8462 0 0 1.14646e+06 4478.35 0.03 0.20 0.08 -1 -1 0.03 0.0458738 0.0432342 |
| 5 | +EArch.xml diffeq2.v common_--cluster_seed_type_max_pins 7.55 vpr 70.20 MiB -1 -1 0.13 30400 4 0.08 -1 -1 37520 -1 -1 22 66 0 5 success v8.0.0-12803-g53682df9f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-06-13T11:40:41 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/tasks 71884 66 96 778 595 1 464 189 16 16 256 mult_36 auto 30.9 MiB 0.23 6732.23 3752 39755 12672 22689 4394 70.2 MiB 0.17 0.00 13.2056 11.8674 -727.569 -11.8674 11.8674 0.18 0.000872064 0.000808698 0.0715952 0.0665154 -1 -1 -1 -1 52 9250 27 1.21132e+07 3.16567e+06 870783. 3401.49 5.74 0.447948 0.413218 28652 182587 -1 7736 22 2979 5812 1155240 362581 13.0686 13.0686 -838.735 -13.0686 0 0 1.14646e+06 4478.35 0.03 0.19 0.09 -1 -1 0.03 0.0490747 0.046101 |
| 6 | +EArch.xml diffeq2.v common_--cluster_seed_type_max_input_pins 7.36 vpr 70.11 MiB -1 -1 0.12 30528 4 0.08 -1 -1 37772 -1 -1 22 66 0 5 success v8.0.0-12803-g53682df9f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-06-13T11:40:41 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/tasks 71796 66 96 778 595 1 464 189 16 16 256 mult_36 auto 31.0 MiB 0.22 6715.25 3821 40297 13390 22454 4453 70.1 MiB 0.17 0.00 13.2056 11.8674 -725.598 -11.8674 11.8674 0.18 0.000846957 0.00078446 0.0716309 0.0664961 -1 -1 -1 -1 50 10106 49 1.21132e+07 3.16567e+06 843554. 3295.13 5.54 0.517553 0.477711 28144 172338 -1 8142 24 3444 6839 1323290 405007 13.0114 13.0114 -845.755 -13.0114 0 0 1.08719e+06 4246.82 0.03 0.23 0.08 -1 -1 0.03 0.056047 0.052474 |
| 7 | +EArch.xml diffeq2.v common_--cluster_seed_type_blend2 8.81 vpr 70.51 MiB -1 -1 0.12 30272 4 0.08 -1 -1 37516 -1 -1 22 66 0 5 success v8.0.0-12803-g53682df9f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-06-13T11:40:41 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/tasks 72200 66 96 778 595 1 467 189 16 16 256 mult_36 auto 31.2 MiB 0.17 7184.04 3684 46259 15600 25711 4948 70.5 MiB 0.19 0.00 13.8986 11.944 -730.881 -11.944 11.944 0.17 0.000832081 0.000772639 0.078257 0.0727817 -1 -1 -1 -1 48 10862 50 1.21132e+07 3.16567e+06 817991. 3195.28 7.00 0.427889 0.394385 27888 167588 -1 8045 27 4765 10132 1863741 545928 13.4757 13.4757 -892.652 -13.4757 0 0 1.04918e+06 4098.38 0.03 0.28 0.08 -1 -1 0.03 0.0577349 0.0541417 |
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