Fixed unused input bug

Author: djns1

ODIN_II/SRC/netlist_create_from_ast.cpp

@@ -1846,6 +1846,8 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
 
                     /* search for the old_input name */
                     if ((sc_spot_input_old = sc_lookup_string(input_nets_sc, alias_name)) == -1) {
+                        if( is_inout )
+                            goto instantiate_output;
                         /* doesn it have to exist since might only be used in module */
                         error_message(NETLIST, module_instance->line_number, module_instance->file_number,
                                       "This module port %s is unused in module %s", alias_name, module_node->children[0]->types.identifier);
@@ -1910,7 +1912,8 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
                     vtr::free(full_name);
                     vtr::free(alias_name);
                 }
-                
+
+                instantiate_output:
                 if (module_var_node->types.variable.is_output) {
                     /* ELSE IF - this is an output pin from the module.  We need to alias this output
                      * pin with it's calling name here so that everyone can see it at this level */

ODIN_II/SRC/parse_making_ast.cpp

@@ -479,7 +479,7 @@ ast_node_t* markAndProcessPortWith(ids top_type, ids port_id, ids net_id, ast_no
     /* look for processed inouts with this name */
     sc_spot = sc_lookup_string(this_inouts_sc, port->children[0]->types.identifier);
     if (sc_spot > -1 && ((ast_node_t*)this_inouts_sc->data[sc_spot])->types.variable.is_port) {
-        error_message(PARSE_ERROR, port->line_number, current_parse_file, "%s already has inout with this name %s\n",
+        error_message(AST, port->line_number, current_parse_file, "%s already has inout with this name %s\n",
                       top_type_name, ((ast_node_t*)this_inouts_sc->data[sc_spot])->children[0]->types.identifier);
     }
 

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic.v

@@ -0,0 +1,12 @@
+module inout_reg(input oe, inout line);
+    reg val;
+    assign line = oe ? val : 1'bz;
+    assign val = oe ? 1'bz : line;
+endmodule
+
+module inout_basic(input oe, input in, output out);
+    wire internal;
+    assign internal = oe ? 1'bz : in;
+    inout_reg c(oe, internal);
+    assign out = internal;
+endmodule