Updated the test cases

Author: djns1

ODIN_II/SRC/ast_elaborate.cpp

@@ -2426,8 +2426,6 @@ void verify_genvars(ast_node_t* node, sc_hierarchy* local_ref, char*** other_gen
 }
 
 ast_node_t* look_for_matching_hard_block(ast_node_t* node, char* hard_block_name, sc_hierarchy* local_ref) {
-    // TODO Update this to match inouts as valid inputs or outputs to the hardblock
-
     t_model* hb_model = find_hard_block(hard_block_name);
     bool is_hb = true;
 

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_input_only.v

@@ -1,12 +1,7 @@
-module inout_assign(inout a);
-    reg r;
-    always @(*)
-    begin
-        r = a;    
-    end
+module inout_assign(inout a, output b);
+    assign b = a;
 endmodule
 
-module inout_basic(b);
-    input b;
-    inout_assign c(b);
+module inout_basic(input a, output b);
+    inout_assign c(a, b);
 endmodule

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_input_only_input

@@ -1,3 +1,6 @@
 GLOBAL_SIM_BASE_CLK a
 0 0
+0 1
+0 1
+0 0
 0 1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_input_only_output

@@ -0,0 +1,6 @@
+b
+0
+1
+1
+0
+1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_ouput_only_input

@@ -1,8 +1,7 @@
-module inout_assign(inout a);
-    assign a = 1;
+module inout_assign(input a, inout b);
+    assign b = a;
 endmodule
 
-module inout_basic(b);
-    output b;
-    inout_assign c(b);
+module inout_basic(input a, output b);
+    inout_assign c(a, b);
 endmodule

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_ouput_only_output

@@ -0,0 +1,6 @@
+GLOBAL_SIM_BASE_CLK a
+0 0
+0 1
+0 1
+0 0
+0 1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_output_only.v

@@ -0,0 +1,6 @@
+b
+0
+1
+1
+0
+1