Implemented InOuts

Author: djns1

ODIN_II/SRC/ast_elaborate.cpp

@@ -2660,12 +2660,12 @@ void create_param_table_for_scope(ast_node_t* module_items, sc_hierarchy* local_
                     /* symbols are already dealt with */
                     if (var_declare->types.variable.is_input
                         || var_declare->types.variable.is_output
+                        || var_declare->types.variable.is_inout
                         || var_declare->types.variable.is_reg
                         || var_declare->types.variable.is_integer
                         || var_declare->types.variable.is_genvar
                         || var_declare->types.variable.is_wire
                         || var_declare->types.variable.is_defparam)
-
                         continue;
 
                     oassert(module_items->children[i]->children[j]->type == VAR_DECLARE);

ODIN_II/SRC/netlist_create_from_ast.cpp

@@ -1016,7 +1016,7 @@ static void build_top_input_node(const char* name_str, Hashtable* output_nets_ha
 
 void add_top_input_nodes(FILE* file, Hashtable* output_nets_hash) {
     /**
-     * insert a global clock for fall back. 
+     * insert a global clock for fall back.
      * in case of undriven internal clocks, they will attach to the global clock
      * this also fix the issue of constant verilog (no input)
      * that cannot simulate due to empty input vector

ODIN_II/SRC/parse_making_ast.cpp

@@ -16,6 +16,7 @@ arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
 circuits_dir=regression_test/benchmark/verilog/
 
 circuit_list_add=syntax/*.v
+circuit_list_add=syntax/inout-syntax/*.v
 
 synthesis_parse_file=regression_test/parse_result/conf/synth.toml
 simulation_parse_file=regression_test/parse_result/conf/sim.toml

ODIN_II/SRC/read_blif.cpp

@@ -0,0 +1,8 @@
+module simple_op(in_out1,in_out2,en);
+	inout in_out1;
+	inout in_out2;
+	input  en;
+
+	assign in_out1 = (en) ? in_out2 : 1'bz;
+	assign in_out2 = (!en) ? in_out1 : 1'bz;
+endmodule

ODIN_II/regression_test/benchmark/task/syntax/task.conf

@@ -0,0 +1,7 @@
+GLOBAL_SIM_BASE_CLK en in_out1 in_out2
+0 1 z z
+1 0 z z
+0 1 z 0
+1 1 z 1
+0 0 1 z
+1 0 0 z

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout.v

@@ -0,0 +1,7 @@
+in_out1 in_out2
+0 0
+1 1
+0 0
+0 x
+1 1
+x 1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout_input

@@ -0,0 +1,4 @@
+module inout_basic(input dir, inout io, output out);
+    assign io = (dir) ? dir : 1'bz;
+    assign out = (!dir) ? io : 1'bx;
+endmodule

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout_output

@@ -0,0 +1,9 @@
+GLOBAL_SIM_BASE_CLK dir io
+0 1 0
+0 1 0
+0 1 1
+0 1 1
+0 0 0
+0 0 0
+0 0 1
+0 0 1