Skip to content

Commit f11f101

Browse files
jeanlegojeanlego
committed
Odin: regenerate results
1 parent 1880d21 commit f11f101

File tree

117 files changed

+228
-11875
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

117 files changed

+228
-11875
lines changed

‎ODIN_II/regression_test/benchmark/task/arch_sweep/synthesis_result.json‎

Lines changed: 112 additions & 113 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,92 @@
11
{
2+
"arch_sweep/both_ram/k6_N10_40nm": {
3+
"test_name": "arch_sweep/both_ram/k6_N10_40nm",
4+
"architecture": "k6_N10_40nm.xml",
5+
"verilog": "both_ram.v",
6+
"exit": 134,
7+
"errors": [
8+
"NETLIST Memory pram.inst1 of depth 2^16 exceeds ODIN bound of 2^10."
9+
]
10+
},
11+
"arch_sweep/both_ram/k6_N10_mem32K_40nm": {
12+
"test_name": "arch_sweep/both_ram/k6_N10_mem32K_40nm",
13+
"architecture": "k6_N10_mem32K_40nm.xml",
14+
"verilog": "both_ram.v",
15+
"max_rss(MiB)": 55.7,
16+
"exec_time(ms)": 100.3,
17+
"synthesis_time(ms)": 21.8,
18+
"Pi": 51,
19+
"Po": 40,
20+
"logic element": 115,
21+
"Multiplier": 0,
22+
"Memory": 48,
23+
"generic logic size": 6,
24+
"Longest Path": 7,
25+
"Average Path": 4,
26+
"Estimated LUTs": 115,
27+
"Total Node": 163
28+
},
29+
"arch_sweep/both_ram/k6_N10_mem32K_40nm_fc_abs": {
30+
"test_name": "arch_sweep/both_ram/k6_N10_mem32K_40nm_fc_abs",
31+
"architecture": "k6_N10_mem32K_40nm_fc_abs.xml",
32+
"verilog": "both_ram.v",
33+
"max_rss(MiB)": 55.7,
34+
"exec_time(ms)": 100.2,
35+
"synthesis_time(ms)": 21.5,
36+
"Pi": 51,
37+
"Po": 40,
38+
"logic element": 115,
39+
"Multiplier": 0,
40+
"Memory": 48,
41+
"generic logic size": 6,
42+
"Longest Path": 7,
43+
"Average Path": 4,
44+
"Estimated LUTs": 115,
45+
"Total Node": 163
46+
},
47+
"arch_sweep/both_ram/k6_N10_mem32K_40nm_nonuniform": {
48+
"test_name": "arch_sweep/both_ram/k6_N10_mem32K_40nm_nonuniform",
49+
"architecture": "k6_N10_mem32K_40nm_nonuniform.xml",
50+
"verilog": "both_ram.v",
51+
"max_rss(MiB)": 55.3,
52+
"exec_time(ms)": 100.2,
53+
"synthesis_time(ms)": 21.6,
54+
"Pi": 51,
55+
"Po": 40,
56+
"logic element": 115,
57+
"Multiplier": 0,
58+
"Memory": 48,
59+
"generic logic size": 6,
60+
"Longest Path": 7,
61+
"Average Path": 4,
62+
"Estimated LUTs": 115,
63+
"Total Node": 163
64+
},
65+
"arch_sweep/both_ram/k6_N10_mem32K_40nm_pulse": {
66+
"test_name": "arch_sweep/both_ram/k6_N10_mem32K_40nm_pulse",
67+
"architecture": "k6_N10_mem32K_40nm_pulse.xml",
68+
"verilog": "both_ram.v",
69+
"max_rss(MiB)": 55.5,
70+
"exec_time(ms)": 100.2,
71+
"synthesis_time(ms)": 22,
72+
"Pi": 51,
73+
"Po": 40,
74+
"logic element": 115,
75+
"Multiplier": 0,
76+
"Memory": 48,
77+
"generic logic size": 6,
78+
"Longest Path": 7,
79+
"Average Path": 4,
80+
"Estimated LUTs": 115,
81+
"Total Node": 163
82+
},
283
"arch_sweep/both_ram/k6_frac_N10_4add_2chains_depop50_mem20K_22nm": {
384
"test_name": "arch_sweep/both_ram/k6_frac_N10_4add_2chains_depop50_mem20K_22nm",
485
"architecture": "k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml",
586
"verilog": "both_ram.v",
6-
"max_rss(MiB)": 114.9,
7-
"exec_time(ms)": 213.3,
8-
"synthesis_time(ms)": 173.4,
87+
"max_rss(MiB)": 144.3,
88+
"exec_time(ms)": 288.5,
89+
"synthesis_time(ms)": 218.4,
990
"Pi": 51,
1091
"Po": 40,
1192
"logic element": 3565,
@@ -22,9 +103,9 @@
22103
"test_name": "arch_sweep/both_ram/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm",
23104
"architecture": "k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml",
24105
"verilog": "both_ram.v",
25-
"max_rss(MiB)": 115.1,
26-
"exec_time(ms)": 237.9,
27-
"synthesis_time(ms)": 196.3,
106+
"max_rss(MiB)": 144.3,
107+
"exec_time(ms)": 288.8,
108+
"synthesis_time(ms)": 218.4,
28109
"Pi": 51,
29110
"Po": 40,
30111
"logic element": 3565,
@@ -41,9 +122,9 @@
41122
"test_name": "arch_sweep/both_ram/k6_frac_N10_frac_chain_depop50_mem32K_40nm",
42123
"architecture": "k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml",
43124
"verilog": "both_ram.v",
44-
"max_rss(MiB)": 29.7,
45-
"exec_time(ms)": 66.6,
46-
"synthesis_time(ms)": 16.9,
125+
"max_rss(MiB)": 56.8,
126+
"exec_time(ms)": 105.4,
127+
"synthesis_time(ms)": 21.4,
47128
"Pi": 51,
48129
"Po": 40,
49130
"logic element": 115,
@@ -60,9 +141,9 @@
60141
"test_name": "arch_sweep/both_ram/k6_frac_N10_frac_chain_mem32K_40nm",
61142
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
62143
"verilog": "both_ram.v",
63-
"max_rss(MiB)": 29.3,
64-
"exec_time(ms)": 66.6,
65-
"synthesis_time(ms)": 17.1,
144+
"max_rss(MiB)": 56.5,
145+
"exec_time(ms)": 111.7,
146+
"synthesis_time(ms)": 22,
66147
"Pi": 51,
67148
"Po": 40,
68149
"logic element": 115,
@@ -79,9 +160,9 @@
79160
"test_name": "arch_sweep/both_ram/k6_frac_N10_frac_chain_mem32K_htree0_40nm",
80161
"architecture": "k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml",
81162
"verilog": "both_ram.v",
82-
"max_rss(MiB)": 29.3,
83-
"exec_time(ms)": 65.3,
84-
"synthesis_time(ms)": 17,
163+
"max_rss(MiB)": 56.6,
164+
"exec_time(ms)": 103.7,
165+
"synthesis_time(ms)": 21.7,
85166
"Pi": 51,
86167
"Po": 40,
87168
"logic element": 115,
@@ -98,9 +179,9 @@
98179
"test_name": "arch_sweep/both_ram/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm",
99180
"architecture": "k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml",
100181
"verilog": "both_ram.v",
101-
"max_rss(MiB)": 29.4,
102-
"exec_time(ms)": 64.6,
103-
"synthesis_time(ms)": 17,
182+
"max_rss(MiB)": 56.4,
183+
"exec_time(ms)": 103.7,
184+
"synthesis_time(ms)": 21.5,
104185
"Pi": 51,
105186
"Po": 40,
106187
"logic element": 115,
@@ -117,9 +198,9 @@
117198
"test_name": "arch_sweep/both_ram/k6_frac_N10_frac_chain_mem32K_htree0short_40nm",
118199
"architecture": "k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml",
119200
"verilog": "both_ram.v",
120-
"max_rss(MiB)": 29.4,
121-
"exec_time(ms)": 64.9,
122-
"synthesis_time(ms)": 18,
201+
"max_rss(MiB)": 56.2,
202+
"exec_time(ms)": 95.4,
203+
"synthesis_time(ms)": 21.2,
123204
"Pi": 51,
124205
"Po": 40,
125206
"logic element": 115,
@@ -132,31 +213,13 @@
132213
"Estimated LUTs": 115,
133214
"Total Node": 163
134215
},
135-
"arch_sweep/both_ram/k6_frac_N10_mem32K_40nm_custom_pins": {
136-
"test_name": "arch_sweep/both_ram/k6_frac_N10_mem32K_40nm_custom_pins",
137-
"architecture": "k6_frac_N10_mem32K_40nm_custom_pins.xml",
138-
"verilog": "both_ram.v",
139-
"max_rss(MiB)": 29.3,
140-
"exec_time(ms)": 64,
141-
"synthesis_time(ms)": 16.8,
142-
"Pi": 51,
143-
"Po": 40,
144-
"logic element": 115,
145-
"Multiplier": 0,
146-
"Memory": 48,
147-
"generic logic size": 5,
148-
"Longest Path": 7,
149-
"Average Path": 4,
150-
"Estimated LUTs": 115,
151-
"Total Node": 163
152-
},
153216
"arch_sweep/both_ram/k6_frac_N10_mem32K_40nm": {
154217
"test_name": "arch_sweep/both_ram/k6_frac_N10_mem32K_40nm",
155218
"architecture": "k6_frac_N10_mem32K_40nm.xml",
156219
"verilog": "both_ram.v",
157-
"max_rss(MiB)": 29.1,
158-
"exec_time(ms)": 63.4,
159-
"synthesis_time(ms)": 16.8,
220+
"max_rss(MiB)": 56.1,
221+
"exec_time(ms)": 55.9,
222+
"synthesis_time(ms)": 12.4,
160223
"Pi": 51,
161224
"Po": 40,
162225
"logic element": 115,
@@ -168,83 +231,19 @@
168231
"Estimated LUTs": 115,
169232
"Total Node": 163
170233
},
171-
"arch_sweep/both_ram/k6_N10_40nm": {
172-
"test_name": "arch_sweep/both_ram/k6_N10_40nm",
173-
"architecture": "k6_N10_40nm.xml",
174-
"verilog": "both_ram.v",
175-
"exit": 134,
176-
"errors": [
177-
"NETLIST Memory pram.inst1 of depth 2^16 exceeds ODIN bound of 2^10."
178-
],
179-
"generic logic size": 6
180-
},
181-
"arch_sweep/both_ram/k6_N10_mem32K_40nm_fc_abs": {
182-
"test_name": "arch_sweep/both_ram/k6_N10_mem32K_40nm_fc_abs",
183-
"architecture": "k6_N10_mem32K_40nm_fc_abs.xml",
184-
"verilog": "both_ram.v",
185-
"max_rss(MiB)": 28.6,
186-
"exec_time(ms)": 61.7,
187-
"synthesis_time(ms)": 16.8,
188-
"Pi": 51,
189-
"Po": 40,
190-
"logic element": 115,
191-
"Multiplier": 0,
192-
"Memory": 48,
193-
"generic logic size": 6,
194-
"Longest Path": 7,
195-
"Average Path": 4,
196-
"Estimated LUTs": 115,
197-
"Total Node": 163
198-
},
199-
"arch_sweep/both_ram/k6_N10_mem32K_40nm_nonuniform": {
200-
"test_name": "arch_sweep/both_ram/k6_N10_mem32K_40nm_nonuniform",
201-
"architecture": "k6_N10_mem32K_40nm_nonuniform.xml",
202-
"verilog": "both_ram.v",
203-
"max_rss(MiB)": 28.7,
204-
"exec_time(ms)": 55.2,
205-
"synthesis_time(ms)": 16.6,
206-
"Pi": 51,
207-
"Po": 40,
208-
"logic element": 115,
209-
"Multiplier": 0,
210-
"Memory": 48,
211-
"generic logic size": 6,
212-
"Longest Path": 7,
213-
"Average Path": 4,
214-
"Estimated LUTs": 115,
215-
"Total Node": 163
216-
},
217-
"arch_sweep/both_ram/k6_N10_mem32K_40nm_pulse": {
218-
"test_name": "arch_sweep/both_ram/k6_N10_mem32K_40nm_pulse",
219-
"architecture": "k6_N10_mem32K_40nm_pulse.xml",
220-
"verilog": "both_ram.v",
221-
"max_rss(MiB)": 28.7,
222-
"exec_time(ms)": 33.1,
223-
"synthesis_time(ms)": 9.4,
224-
"Pi": 51,
225-
"Po": 40,
226-
"logic element": 115,
227-
"Multiplier": 0,
228-
"Memory": 48,
229-
"generic logic size": 6,
230-
"Longest Path": 7,
231-
"Average Path": 4,
232-
"Estimated LUTs": 115,
233-
"Total Node": 163
234-
},
235-
"arch_sweep/both_ram/k6_N10_mem32K_40nm": {
236-
"test_name": "arch_sweep/both_ram/k6_N10_mem32K_40nm",
237-
"architecture": "k6_N10_mem32K_40nm.xml",
234+
"arch_sweep/both_ram/k6_frac_N10_mem32K_40nm_custom_pins": {
235+
"test_name": "arch_sweep/both_ram/k6_frac_N10_mem32K_40nm_custom_pins",
236+
"architecture": "k6_frac_N10_mem32K_40nm_custom_pins.xml",
238237
"verilog": "both_ram.v",
239-
"max_rss(MiB)": 28.7,
240-
"exec_time(ms)": 45.1,
241-
"synthesis_time(ms)": 9.4,
238+
"max_rss(MiB)": 56.1,
239+
"exec_time(ms)": 57.2,
240+
"synthesis_time(ms)": 12.4,
242241
"Pi": 51,
243242
"Po": 40,
244243
"logic element": 115,
245244
"Multiplier": 0,
246245
"Memory": 48,
247-
"generic logic size": 6,
246+
"generic logic size": 5,
248247
"Longest Path": 7,
249248
"Average Path": 4,
250249
"Estimated LUTs": 115,

‎ODIN_II/regression_test/benchmark/task/c_functions/$clog2/task.conf‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,6 @@ simulation_params= -L reset rst -H we
1010
# setup the architecture
1111
archs_dir=../vtr_flow/arch/timing
1212

13-
arch_list_add=k6_N10_40nm.xml
14-
arch_list_add=k6_N10_mem32K_40nm.xml
15-
arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
16-
1713
# setup the circuits
1814
circuits_dir=regression_test/benchmark/verilog/c_functions
1915

0 commit comments

Comments
 (0)