diff --git a/cdc/rtl/br_cdc_bit_pulse.sv b/cdc/rtl/br_cdc_bit_pulse.sv
index 65d574a33..175f79a3c 100644
--- a/cdc/rtl/br_cdc_bit_pulse.sv
+++ b/cdc/rtl/br_cdc_bit_pulse.sv
@@ -56,10 +56,18 @@ module br_cdc_bit_pulse #(
     input  logic dst_rst,
     output logic dst_pulse
 );
-  // Integration Assertions
+
+  //------------------------------------------
+  // Integration checks
+  //------------------------------------------
   // Relying on checks in br_cdc_bit_toggle
 
+  `BR_ASSERT_CR_INTG(src_pulse_high_then_low_a, src_pulse |=> !src_pulse, src_clk, src_rst)
+  `BR_COVER_CR_INTG(back_to_back_src_pulse_c, src_pulse ##2 src_pulse, src_clk, src_rst)
+
+  //------------------------------------------
   // Implementation
+  //------------------------------------------
   logic src_level;
   logic dst_level;
   logic dst_level_d;
@@ -98,7 +106,10 @@ module br_cdc_bit_pulse #(
     assign dst_pulse = dst_pulse_internal;
   end
 
-  // Implementation assertions
-  // TODO(zhemao): Add some here
+  //------------------------------------------
+  // Implementation checks
+  //------------------------------------------
+  `BR_ASSERT_CR_IMPL(dst_pulse_high_then_low_a, dst_pulse |=> !dst_pulse, dst_clk, dst_rst)
+  `BR_COVER_CR_IMPL(back_to_back_dst_pulse_c, dst_pulse ##2 dst_pulse, dst_clk, dst_rst)
 
 endmodule
diff --git a/enc/sim/br_enc_bin2onehot_tb.sv b/enc/sim/br_enc_bin2onehot_tb.sv
index a12e9508a..91a658138 100644
--- a/enc/sim/br_enc_bin2onehot_tb.sv
+++ b/enc/sim/br_enc_bin2onehot_tb.sv
@@ -81,9 +81,6 @@ module br_enc_bin2onehot_tb;
     // Finish simulation
     #10;
 
-    // TODO(mgottscho): not enough information to know if test passed.
-    // If DUT asserts fire, we can't see that here.
-    // Need to determine pass/fail outside of this TB?
     if (errors) begin
       $display("Number of errors: %0d", errors);
       $display("TEST FAILED");