From fa30f872c18c067012ec2490694dbde96927152f Mon Sep 17 00:00:00 2001 From: Mark Gottscho Date: Fri, 25 Apr 2025 22:39:08 +0000 Subject: [PATCH] Scrub some obsolete TODOs --- arb/rtl/br_arb_lru.sv | 2 -- arb/rtl/br_arb_rr.sv | 3 --- cdc/rtl/br_cdc_bit_pulse.sv | 17 ++++++++++++++--- enc/rtl/br_enc_bin2onehot.sv | 2 -- enc/sim/br_enc_bin2onehot_tb.sv | 3 --- flow/rtl/br_flow_arb_fixed.sv | 2 -- flow/rtl/br_flow_arb_lru.sv | 4 ---- flow/rtl/br_flow_arb_rr.sv | 4 ---- flow/rtl/br_flow_demux_select.sv | 2 -- flow/rtl/br_flow_demux_select_unstable.sv | 2 -- flow/rtl/br_flow_mux_select.sv | 2 -- flow/rtl/br_flow_mux_select_unstable.sv | 2 -- 12 files changed, 14 insertions(+), 31 deletions(-) diff --git a/arb/rtl/br_arb_lru.sv b/arb/rtl/br_arb_lru.sv index 73e447d46..441ca4464 100644 --- a/arb/rtl/br_arb_lru.sv +++ b/arb/rtl/br_arb_lru.sv @@ -66,6 +66,4 @@ module br_arb_lru #( |-> $stable(grant)) `BR_COVER_IMPL(grant_without_state_update_c, !enable_priority_update && |grant) - // TODO(mgottscho): Add more cases - endmodule : br_arb_lru diff --git a/arb/rtl/br_arb_rr.sv b/arb/rtl/br_arb_rr.sv index 31b3d0bca..0f5681e6a 100644 --- a/arb/rtl/br_arb_rr.sv +++ b/arb/rtl/br_arb_rr.sv @@ -74,7 +74,4 @@ module br_arb_rr #( |-> $stable(grant)) `BR_COVER_IMPL(grant_without_state_update_c, !enable_priority_update && |grant) - // TODO(mgottscho): Add more cases - // TODO(mgottscho): Add covers on masked and unmasked cases - endmodule : br_arb_rr diff --git a/cdc/rtl/br_cdc_bit_pulse.sv b/cdc/rtl/br_cdc_bit_pulse.sv index 82ffe96ee..b3e87b216 100644 --- a/cdc/rtl/br_cdc_bit_pulse.sv +++ b/cdc/rtl/br_cdc_bit_pulse.sv @@ -67,10 +67,18 @@ module br_cdc_bit_pulse #( input logic dst_rst, output logic dst_pulse ); - // Integration Assertions + + //------------------------------------------ + // Integration checks + //------------------------------------------ // Relying on checks in br_cdc_bit_toggle + `BR_ASSERT_CR_INTG(src_pulse_high_then_low_a, src_pulse |=> !src_pulse, src_clk, src_rst) + `BR_COVER_CR_INTG(back_to_back_src_pulse_c, src_pulse ##2 src_pulse, src_clk, src_rst) + + //------------------------------------------ // Implementation + //------------------------------------------ logic src_level; logic dst_level; logic dst_level_d; @@ -109,7 +117,10 @@ module br_cdc_bit_pulse #( assign dst_pulse = dst_pulse_internal; end - // Implementation assertions - // TODO(zhemao): Add some here + //------------------------------------------ + // Implementation checks + //------------------------------------------ + `BR_ASSERT_CR_IMPL(dst_pulse_high_then_low_a, dst_pulse |=> !dst_pulse, dst_clk, dst_rst) + `BR_COVER_CR_IMPL(back_to_back_dst_pulse_c, dst_pulse ##2 dst_pulse, dst_clk, dst_rst) endmodule diff --git a/enc/rtl/br_enc_bin2onehot.sv b/enc/rtl/br_enc_bin2onehot.sv index b9a6c7d53..b740aa9b3 100644 --- a/enc/rtl/br_enc_bin2onehot.sv +++ b/enc/rtl/br_enc_bin2onehot.sv @@ -41,8 +41,6 @@ // It must be at least $clog2(NumValues) but may be set larger than the minimum // width. Irrespective of the width, the input binary must be in the allowed range // 0 <= in < NumValues. -// -// TODO(mgottscho): Write spec `include "br_asserts_internal.svh" diff --git a/enc/sim/br_enc_bin2onehot_tb.sv b/enc/sim/br_enc_bin2onehot_tb.sv index a742b0d8e..0e0b9cad3 100644 --- a/enc/sim/br_enc_bin2onehot_tb.sv +++ b/enc/sim/br_enc_bin2onehot_tb.sv @@ -92,9 +92,6 @@ module br_enc_bin2onehot_tb; // Finish simulation #10; - // TODO(mgottscho): not enough information to know if test passed. - // If DUT asserts fire, we can't see that here. - // Need to determine pass/fail outside of this TB? if (errors) begin $display("Number of errors: %0d", errors); $display("TEST FAILED"); diff --git a/flow/rtl/br_flow_arb_fixed.sv b/flow/rtl/br_flow_arb_fixed.sv index 3c33c7466..83d87ae1a 100644 --- a/flow/rtl/br_flow_arb_fixed.sv +++ b/flow/rtl/br_flow_arb_fixed.sv @@ -22,8 +22,6 @@ // Purely combinational (no delays). // Pop valid can be unstable if push valid is unstable and all active push_valid // are withdrawn while pop_ready is low. -// -// TODO(mgottscho): Write spec `include "br_asserts_internal.svh" diff --git a/flow/rtl/br_flow_arb_lru.sv b/flow/rtl/br_flow_arb_lru.sv index e730a61f1..cce32bce1 100644 --- a/flow/rtl/br_flow_arb_lru.sv +++ b/flow/rtl/br_flow_arb_lru.sv @@ -23,8 +23,6 @@ // the internal arbiter priority state. // Pop valid can be unstable if push valid is unstable and all active push_valid // are withdrawn while pop_ready is low. -// -// TODO(mgottscho): Write spec `include "br_registers.svh" `include "br_asserts_internal.svh" @@ -56,8 +54,6 @@ module br_flow_arb_lru #( //------------------------------------------ // Rely on submodule integration checks - // TODO(mgottscho): Add more - //------------------------------------------ // Implementation //------------------------------------------ diff --git a/flow/rtl/br_flow_arb_rr.sv b/flow/rtl/br_flow_arb_rr.sv index b20729d6b..677d74c2d 100644 --- a/flow/rtl/br_flow_arb_rr.sv +++ b/flow/rtl/br_flow_arb_rr.sv @@ -23,8 +23,6 @@ // the internal arbiter priority state. // Pop valid can be unstable if push valid is unstable and all active push_valid // are withdrawn while pop_ready is low. -// -// TODO(mgottscho): Write spec `include "br_registers.svh" `include "br_asserts_internal.svh" @@ -56,8 +54,6 @@ module br_flow_arb_rr #( //------------------------------------------ // Rely on submodule integration checks - // TODO(mgottscho): Add more - //------------------------------------------ // Implementation //------------------------------------------ diff --git a/flow/rtl/br_flow_demux_select.sv b/flow/rtl/br_flow_demux_select.sv index 7f8556e1f..eda50c0a1 100644 --- a/flow/rtl/br_flow_demux_select.sv +++ b/flow/rtl/br_flow_demux_select.sv @@ -22,8 +22,6 @@ // Data progresses from one stage to another when both // the corresponding ready signal and valid signal are // both 1 on the same cycle. Otherwise, the stage is stalled. -// -// TODO(mgottscho): Write spec doc `include "br_registers.svh" diff --git a/flow/rtl/br_flow_demux_select_unstable.sv b/flow/rtl/br_flow_demux_select_unstable.sv index 1655c9cac..46c50bdde 100644 --- a/flow/rtl/br_flow_demux_select_unstable.sv +++ b/flow/rtl/br_flow_demux_select_unstable.sv @@ -28,8 +28,6 @@ // It is called "unstable" because the pop interface is not guaranteed // to follow the ready-valid stability convention, because the select // input could change while the selected pop interface is backpressuring. -// -// TODO(mgottscho): Write spec doc `include "br_asserts_internal.svh" diff --git a/flow/rtl/br_flow_mux_select.sv b/flow/rtl/br_flow_mux_select.sv index 4ca9c96b6..97b7295c6 100644 --- a/flow/rtl/br_flow_mux_select.sv +++ b/flow/rtl/br_flow_mux_select.sv @@ -22,8 +22,6 @@ // Data progresses from one stage to another when both // the corresponding ready signal and valid signal are // both 1 on the same cycle. Otherwise, the stage is stalled. -// -// TODO(mgottscho): Write spec doc `include "br_registers.svh" diff --git a/flow/rtl/br_flow_mux_select_unstable.sv b/flow/rtl/br_flow_mux_select_unstable.sv index 58b3d399e..0546b8c23 100644 --- a/flow/rtl/br_flow_mux_select_unstable.sv +++ b/flow/rtl/br_flow_mux_select_unstable.sv @@ -28,8 +28,6 @@ // It is called "unstable" because the pop interface is not guaranteed // to follow the ready-valid stability convention, because the select // input could change while the selected push interface is backpressured. -// -// TODO(mgottscho): Write spec doc `include "br_asserts_internal.svh"