diff --git a/flow/rtl/BUILD.bazel b/flow/rtl/BUILD.bazel index 6639a95db..73140d27a 100644 --- a/flow/rtl/BUILD.bazel +++ b/flow/rtl/BUILD.bazel @@ -43,6 +43,7 @@ verilog_library( deps = [ ":br_flow_demux_select_unstable", ":br_flow_reg_fwd", + "//pkg:br_math_pkg", ], ) @@ -53,6 +54,7 @@ verilog_library( "//flow/rtl/internal:br_flow_checks_valid_data_impl", "//flow/rtl/internal:br_flow_checks_valid_data_intg", "//macros:br_asserts_internal", + "//pkg:br_math_pkg", ], ) @@ -92,6 +94,7 @@ verilog_library( deps = [ ":br_flow_mux_select_unstable", ":br_flow_reg_fwd", + "//pkg:br_math_pkg", ], ) @@ -102,6 +105,8 @@ verilog_library( "//flow/rtl/internal:br_flow_checks_valid_data_impl", "//flow/rtl/internal:br_flow_checks_valid_data_intg", "//macros:br_asserts_internal", + "//macros:br_unused", + "//pkg:br_math_pkg", ], ) @@ -243,6 +248,7 @@ verilog_library( deps = [ "//arb/rtl/internal:br_arb_fixed_internal", "//flow/rtl/internal:br_flow_xbar_core", + "//pkg:br_math_pkg", ], ) @@ -252,6 +258,7 @@ verilog_library( deps = [ "//arb/rtl/internal:br_arb_rr_internal", "//flow/rtl/internal:br_flow_xbar_core", + "//pkg:br_math_pkg", ], ) @@ -261,6 +268,7 @@ verilog_library( deps = [ "//arb/rtl/internal:br_arb_lru_internal", "//flow/rtl/internal:br_flow_xbar_core", + "//pkg:br_math_pkg", ], ) @@ -268,6 +276,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_arb_fixed_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -279,6 +288,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_arb_rr_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -290,6 +300,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_arb_lru_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -301,6 +312,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_demux_select_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -316,6 +328,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_demux_select_unstable_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -331,6 +344,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_fork_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -342,6 +356,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_fork_select_multihot_test_suite", params = { "NumFlows": [ + "1", "2", "3", "7", @@ -358,6 +373,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_join_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -369,6 +385,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_mux_select_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -384,6 +401,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_mux_select_unstable_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -399,6 +417,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_mux_fixed_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -414,6 +433,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_mux_rr_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -429,6 +449,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_mux_lru_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -444,6 +465,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_mux_fixed_stable_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -463,6 +485,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_mux_rr_stable_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -482,6 +505,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_mux_lru_stable_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -589,10 +613,12 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_xbar_fixed_test_suite", params = { "NumPushFlows": [ + "1", "2", "4", ], "NumPopFlows": [ + "1", "2", "4", ], @@ -616,10 +642,12 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_xbar_rr_test_suite", params = { "NumPushFlows": [ + "1", "2", "4", ], "NumPopFlows": [ + "1", "2", "4", ], @@ -643,10 +671,12 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_xbar_lru_test_suite", params = { "NumPushFlows": [ + "1", "2", "4", ], "NumPopFlows": [ + "1", "2", "4", ], diff --git a/flow/rtl/br_flow_arb_fixed.sv b/flow/rtl/br_flow_arb_fixed.sv index bcb6c1714..a9f957343 100644 --- a/flow/rtl/br_flow_arb_fixed.sv +++ b/flow/rtl/br_flow_arb_fixed.sv @@ -15,8 +15,8 @@ `include "br_asserts_internal.svh" module br_flow_arb_fixed #( - // Must be at least 2 - parameter int NumFlows = 2, + // Must be at least 1 + parameter int NumFlows = 1, // If 1, cover that the push side experiences backpressure. // If 0, assert that there is never backpressure. parameter bit EnableCoverPushBackpressure = 1, diff --git a/flow/rtl/br_flow_arb_lru.sv b/flow/rtl/br_flow_arb_lru.sv index 0061a65d3..695217a40 100644 --- a/flow/rtl/br_flow_arb_lru.sv +++ b/flow/rtl/br_flow_arb_lru.sv @@ -17,8 +17,8 @@ `include "br_asserts_internal.svh" module br_flow_arb_lru #( - // Must be at least 2 - parameter int NumFlows = 2, + // Must be at least 1 + parameter int NumFlows = 1, // If 1, cover that the push side experiences backpressure. // If 0, assert that there is never backpressure. parameter bit EnableCoverPushBackpressure = 1, diff --git a/flow/rtl/br_flow_arb_rr.sv b/flow/rtl/br_flow_arb_rr.sv index 0113c43c0..f093f9a95 100644 --- a/flow/rtl/br_flow_arb_rr.sv +++ b/flow/rtl/br_flow_arb_rr.sv @@ -17,8 +17,8 @@ `include "br_asserts_internal.svh" module br_flow_arb_rr #( - // Must be at least 2 - parameter int NumFlows = 2, + // Must be at least 1 + parameter int NumFlows = 1, // If 1, cover that the push side experiences backpressure. // If 0, assert that there is never backpressure. parameter bit EnableCoverPushBackpressure = 1, diff --git a/flow/rtl/br_flow_demux_select.sv b/flow/rtl/br_flow_demux_select.sv index 1abbab261..a6e92a51c 100644 --- a/flow/rtl/br_flow_demux_select.sv +++ b/flow/rtl/br_flow_demux_select.sv @@ -15,8 +15,8 @@ `include "br_registers.svh" module br_flow_demux_select #( - // Must be at least 2 - parameter int NumFlows = 2, + // Must be at least 1 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // If 1, cover that the push side experiences backpressure. @@ -32,12 +32,13 @@ module br_flow_demux_select #( // If 1, assert that push_data is always known (not X) when push_valid is asserted. parameter bit EnableAssertPushDataKnown = 1, // If 1, then assert there are no valid bits asserted at the end of the test. - parameter bit EnableAssertFinalNotValid = 1 + parameter bit EnableAssertFinalNotValid = 1, + localparam int SelectWidth = br_math::clamped_clog2(NumFlows) ) ( input logic clk, input logic rst, // Synchronous active-high - input logic [$clog2(NumFlows)-1:0] select, + input logic [SelectWidth-1:0] select, output logic push_ready, input logic push_valid, diff --git a/flow/rtl/br_flow_demux_select_unstable.sv b/flow/rtl/br_flow_demux_select_unstable.sv index 2c12a4497..08e2748b8 100644 --- a/flow/rtl/br_flow_demux_select_unstable.sv +++ b/flow/rtl/br_flow_demux_select_unstable.sv @@ -19,10 +19,11 @@ // input could change while the selected pop interface is backpressuring. `include "br_asserts_internal.svh" +`include "br_unused.svh" module br_flow_demux_select_unstable #( - // Must be at least 2 - parameter int NumFlows = 2, + // Must be at least 1 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // If 1, cover that the push side experiences backpressure. @@ -39,7 +40,7 @@ module br_flow_demux_select_unstable #( parameter bit EnableAssertPushDataKnown = 1, // If 1, then assert there are no valid bits asserted at the end of the test. parameter bit EnableAssertFinalNotValid = 1, - localparam int SelectWidth = $clog2(NumFlows) + localparam int SelectWidth = br_math::clamped_clog2(NumFlows) ) ( // Used only for assertions // ri lint_check_waive INPUT_NOT_READ HIER_NET_NOT_READ HIER_BRANCH_NOT_READ @@ -69,7 +70,7 @@ module br_flow_demux_select_unstable #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_flows_must_be_at_least_two_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_flows_must_be_at_least_one_a, NumFlows >= 1) `BR_ASSERT_STATIC(bit_width_must_be_at_least_one_a, Width >= 1) `BR_ASSERT_STATIC(select_stability_implies_valid_stability_a, !(EnableAssertSelectStability && !EnableAssertPushValidStability)) @@ -107,18 +108,26 @@ module br_flow_demux_select_unstable #( // Implementation //------------------------------------------ - // Lint waivers are safe because we assert select is always in range. - // ri lint_check_waive VAR_INDEX_READ - assign push_ready = pop_ready[select]; - // The ternary expression is needed to ensure pop_valid_unstable is 0 (and not X) - // when select is X and push_valid is 0. - // ri lint_check_waive VAR_SHIFT TRUNC_LSHIFT - assign pop_valid_unstable = push_valid ? (push_valid << select) : '0; - // Replicate pop_data to all flows; this is okay since pop_data[i] - // is only valid when pop_valid_unstable[i] is high. - always_comb begin - for (int i = 0; i < NumFlows; i++) begin - pop_data_unstable[i] = push_data; + if (NumFlows == 1) begin : gen_single_flow + assign push_ready = pop_ready; + assign pop_valid_unstable = push_valid; + assign pop_data_unstable = push_data; + `BR_UNUSED(select) + + end else begin : gen_multi_flow + // Lint waivers are safe because we assert select is always in range. + // ri lint_check_waive VAR_INDEX_READ + assign push_ready = pop_ready[select]; + // The ternary expression is needed to ensure pop_valid_unstable is 0 (and not X) + // when select is X and push_valid is 0. + // ri lint_check_waive VAR_SHIFT TRUNC_LSHIFT + assign pop_valid_unstable = push_valid ? (push_valid << select) : '0; + // Replicate pop_data to all flows; this is okay since pop_data[i] + // is only valid when pop_valid_unstable[i] is high. + always_comb begin + for (int i = 0; i < NumFlows; i++) begin + pop_data_unstable[i] = push_data; + end end end diff --git a/flow/rtl/br_flow_fork.sv b/flow/rtl/br_flow_fork.sv index 316ecf3cd..24f4369e9 100644 --- a/flow/rtl/br_flow_fork.sv +++ b/flow/rtl/br_flow_fork.sv @@ -12,7 +12,7 @@ `include "br_asserts_internal.svh" module br_flow_fork #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 // If 1, cover that the push side experiences backpressure. // If 0, assert that there is never backpressure. parameter bit EnableCoverPushBackpressure = 1, @@ -43,7 +43,7 @@ module br_flow_fork #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_flows_gte_2_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_flows_gte_1_a, NumFlows >= 1) br_flow_checks_valid_data_intg #( .NumFlows(1), diff --git a/flow/rtl/br_flow_fork_select_multihot.sv b/flow/rtl/br_flow_fork_select_multihot.sv index 20d240a5e..61c1225aa 100644 --- a/flow/rtl/br_flow_fork_select_multihot.sv +++ b/flow/rtl/br_flow_fork_select_multihot.sv @@ -13,7 +13,7 @@ `include "br_asserts_internal.svh" module br_flow_fork_select_multihot #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 // If 1, cover that the push_select_multihot signal is multihot when valid is high. // If 0, assert that the push_select_multihot signal is always onehot when valid is high. parameter bit EnableCoverSelectMultihot = 1, @@ -52,7 +52,7 @@ module br_flow_fork_select_multihot #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_flows_gte_2_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_flows_gte_1_a, NumFlows >= 1) `BR_ASSERT_INTG(select_not_0_when_valid_a, push_valid |-> (|push_select_multihot)) br_flow_checks_valid_data_intg #( diff --git a/flow/rtl/br_flow_join.sv b/flow/rtl/br_flow_join.sv index 1712b2ca5..a8413d23e 100644 --- a/flow/rtl/br_flow_join.sv +++ b/flow/rtl/br_flow_join.sv @@ -11,7 +11,7 @@ `include "br_asserts_internal.svh" module br_flow_join #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 // If 1, cover that the push side experiences backpressure. // If 0, assert that there is never backpressure. parameter bit EnableCoverPushBackpressure = 1, @@ -38,7 +38,7 @@ module br_flow_join #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_flows_gte2_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_flows_gte1_a, NumFlows >= 1) br_flow_checks_valid_data_intg #( diff --git a/flow/rtl/br_flow_mux_fixed.sv b/flow/rtl/br_flow_mux_fixed.sv index 124834060..85f818499 100644 --- a/flow/rtl/br_flow_mux_fixed.sv +++ b/flow/rtl/br_flow_mux_fixed.sv @@ -18,7 +18,7 @@ `include "br_asserts.svh" module br_flow_mux_fixed #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // Must be at least 1 // If 1, cover that the push side experiences backpressure. // If 0, assert that there is never backpressure. @@ -51,7 +51,7 @@ module br_flow_mux_fixed #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_requesters_gte_1_a, NumFlows >= 1) `BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1) // Rely on submodule integration checks diff --git a/flow/rtl/br_flow_mux_fixed_stable.sv b/flow/rtl/br_flow_mux_fixed_stable.sv index 5136f9a19..0e4c7c792 100644 --- a/flow/rtl/br_flow_mux_fixed_stable.sv +++ b/flow/rtl/br_flow_mux_fixed_stable.sv @@ -15,7 +15,7 @@ `include "br_asserts.svh" module br_flow_mux_fixed_stable #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // Must be at least 1 // If 1, ensure that the pop ready signal is registered // at the input. This ensures there is no combinational path @@ -46,7 +46,7 @@ module br_flow_mux_fixed_stable #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_flows_gte_1_a, NumFlows >= 1) `BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1) // Rely on submodule integration checks diff --git a/flow/rtl/br_flow_mux_lru.sv b/flow/rtl/br_flow_mux_lru.sv index b1f37abbb..2049adc7e 100644 --- a/flow/rtl/br_flow_mux_lru.sv +++ b/flow/rtl/br_flow_mux_lru.sv @@ -16,7 +16,7 @@ `include "br_asserts.svh" module br_flow_mux_lru #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // Must be at least 1 // If 1, cover that the push side experiences backpressure. // If 0, assert that there is never backpressure. @@ -47,7 +47,7 @@ module br_flow_mux_lru #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 1) `BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1) // Rely on submodule integration checks diff --git a/flow/rtl/br_flow_mux_lru_stable.sv b/flow/rtl/br_flow_mux_lru_stable.sv index 03ca65a31..6079eab54 100644 --- a/flow/rtl/br_flow_mux_lru_stable.sv +++ b/flow/rtl/br_flow_mux_lru_stable.sv @@ -14,7 +14,7 @@ `include "br_asserts.svh" module br_flow_mux_lru_stable #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // Must be at least 1 // If 1, ensure that the pop ready signal is registered // at the input. This ensures there is no combinational path @@ -45,7 +45,7 @@ module br_flow_mux_lru_stable #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_requesters_gte_1_a, NumFlows >= 1) `BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1) // Rely on submodule integration checks diff --git a/flow/rtl/br_flow_mux_rr.sv b/flow/rtl/br_flow_mux_rr.sv index 869824b62..ae4b11d41 100644 --- a/flow/rtl/br_flow_mux_rr.sv +++ b/flow/rtl/br_flow_mux_rr.sv @@ -16,7 +16,7 @@ `include "br_asserts.svh" module br_flow_mux_rr #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // Must be at least 1 // If 1, cover that the push side experiences backpressure. // If 0, assert that there is never backpressure. @@ -47,7 +47,7 @@ module br_flow_mux_rr #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_requesters_gte_1_a, NumFlows >= 1) `BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1) // Rely on submodule integration checks diff --git a/flow/rtl/br_flow_mux_rr_stable.sv b/flow/rtl/br_flow_mux_rr_stable.sv index 816308a14..4d43abb8c 100644 --- a/flow/rtl/br_flow_mux_rr_stable.sv +++ b/flow/rtl/br_flow_mux_rr_stable.sv @@ -14,7 +14,7 @@ `include "br_asserts.svh" module br_flow_mux_rr_stable #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // Must be at least 1 // If 1, ensure that the pop ready signal is registered // at the input. This ensures there is no combinational path @@ -45,7 +45,7 @@ module br_flow_mux_rr_stable #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_requesters_gte_2_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_requesters_gte_1_a, NumFlows >= 1) `BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1) // Rely on submodule integration checks diff --git a/flow/rtl/br_flow_mux_select.sv b/flow/rtl/br_flow_mux_select.sv index 292bf0ec8..9e84b3ab3 100644 --- a/flow/rtl/br_flow_mux_select.sv +++ b/flow/rtl/br_flow_mux_select.sv @@ -15,8 +15,8 @@ `include "br_registers.svh" module br_flow_mux_select #( - // Must be at least 2 - parameter int NumFlows = 2, + // Must be at least 1 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // If 1, cover that the push side experiences backpressure. @@ -32,12 +32,13 @@ module br_flow_mux_select #( // If 1, assert that push_data is always known (not X) when push_valid is asserted. parameter bit EnableAssertPushDataKnown = 1, // If 1, then assert there are no valid bits asserted at the end of the test. - parameter bit EnableAssertFinalNotValid = 1 + parameter bit EnableAssertFinalNotValid = 1, + localparam int SelectWidth = br_math::clamped_clog2(NumFlows) ) ( input logic clk, input logic rst, // Synchronous active-high - input logic [$clog2(NumFlows)-1:0] select, + input logic [SelectWidth-1:0] select, output logic [NumFlows-1:0] push_ready, input logic [NumFlows-1:0] push_valid, diff --git a/flow/rtl/br_flow_mux_select_unstable.sv b/flow/rtl/br_flow_mux_select_unstable.sv index 15ba14d80..260950ae9 100644 --- a/flow/rtl/br_flow_mux_select_unstable.sv +++ b/flow/rtl/br_flow_mux_select_unstable.sv @@ -22,10 +22,11 @@ // will be stable. `include "br_asserts_internal.svh" +`include "br_unused.svh" module br_flow_mux_select_unstable #( - // Must be at least 2 - parameter int NumFlows = 2, + // Must be at least 1 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // If 1, cover that the push side experiences backpressure. @@ -41,7 +42,9 @@ module br_flow_mux_select_unstable #( // If 1, assert that push_data is always known (not X) when push_valid is asserted. parameter bit EnableAssertPushDataKnown = 1, // If 1, then assert there are no valid bits asserted at the end of the test. - parameter bit EnableAssertFinalNotValid = 1 + parameter bit EnableAssertFinalNotValid = 1, + localparam int SelectWidth = br_math::clamped_clog2(NumFlows) + ) ( // Used only for assertions // ri lint_check_waive INPUT_NOT_READ HIER_NET_NOT_READ HIER_BRANCH_NOT_READ @@ -50,7 +53,7 @@ module br_flow_mux_select_unstable #( // ri lint_check_waive INPUT_NOT_READ HIER_NET_NOT_READ HIER_BRANCH_NOT_READ input logic rst, - input logic [$clog2(NumFlows)-1:0] select, + input logic [SelectWidth-1:0] select, output logic [NumFlows-1:0] push_ready, input logic [NumFlows-1:0] push_valid, @@ -68,7 +71,7 @@ module br_flow_mux_select_unstable #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(num_flows_must_be_at_least_two_a, NumFlows >= 2) + `BR_ASSERT_STATIC(num_flows_must_be_at_least_one_a, NumFlows >= 1) `BR_ASSERT_STATIC(width_gte_1_a, Width >= 1) `BR_ASSERT_STATIC(select_only_stable_if_valid_stable_a, EnableAssertPushValidStability || !EnableAssertSelectStability) @@ -104,14 +107,21 @@ module br_flow_mux_select_unstable #( //------------------------------------------ // Implementation //------------------------------------------ - - // Lint waivers are safe because we assert select is always in range. - // ri lint_check_waive VAR_SHIFT TRUNC_LSHIFT - assign push_ready = pop_ready << select; - // ri lint_check_waive VAR_INDEX_READ - assign pop_valid_unstable = push_valid[select]; - // ri lint_check_waive VAR_INDEX_READ - assign pop_data_unstable = push_data[select]; + if (NumFlows == 1) begin : gen_single_flow + assign push_ready = pop_ready; + assign pop_valid_unstable = push_valid; + assign pop_data_unstable = push_data; + `BR_UNUSED(select) + + end else begin : gen_multi_flow + // Lint waivers are safe because we assert select is always in range. + // ri lint_check_waive VAR_SHIFT TRUNC_LSHIFT + assign push_ready = pop_ready << select; + // ri lint_check_waive VAR_INDEX_READ + assign pop_valid_unstable = push_valid[select]; + // ri lint_check_waive VAR_INDEX_READ + assign pop_data_unstable = push_data[select]; + end //------------------------------------------ // Implementation checks diff --git a/flow/rtl/br_flow_xbar_fixed.sv b/flow/rtl/br_flow_xbar_fixed.sv index c9303a50b..01af495e2 100644 --- a/flow/rtl/br_flow_xbar_fixed.sv +++ b/flow/rtl/br_flow_xbar_fixed.sv @@ -16,10 +16,10 @@ // input flow has the highest priority. module br_flow_xbar_fixed #( - // The number of input flows. Must be >=2. - parameter int NumPushFlows = 2, - // The number of output flows. Must be >=2. - parameter int NumPopFlows = 2, + // The number of input flows. Must be >=1. + parameter int NumPushFlows = 1, + // The number of output flows. Must be >=1. + parameter int NumPopFlows = 1, // The width of the data bus. parameter int Width = 1, // If 1, registers are inserted between the demux and mux to break up the @@ -47,7 +47,7 @@ module br_flow_xbar_fixed #( // register stages are empty at end of simulation. parameter bit EnableAssertFinalNotValid = 1, - localparam int DestIdWidth = $clog2(NumPopFlows) + localparam int DestIdWidth = br_math::clamped_clog2(NumPopFlows) ) ( input logic clk, input logic rst, diff --git a/flow/rtl/br_flow_xbar_lru.sv b/flow/rtl/br_flow_xbar_lru.sv index 7b7ef20d2..72a716b5d 100644 --- a/flow/rtl/br_flow_xbar_lru.sv +++ b/flow/rtl/br_flow_xbar_lru.sv @@ -15,10 +15,10 @@ // Uses least-recently used (LRU) arbitration to grant requests. module br_flow_xbar_lru #( - // The number of input flows. Must be >=2. - parameter int NumPushFlows = 2, - // The number of output flows. Must be >=2. - parameter int NumPopFlows = 2, + // The number of input flows. Must be >=1. + parameter int NumPushFlows = 1, + // The number of output flows. Must be >=1. + parameter int NumPopFlows = 1, // The width of the data bus. parameter int Width = 1, // If 1, registers are inserted between the demux and mux to break up the @@ -46,7 +46,7 @@ module br_flow_xbar_lru #( // register stages are empty at end of simulation. parameter bit EnableAssertFinalNotValid = 1, - localparam int DestIdWidth = $clog2(NumPopFlows) + localparam int DestIdWidth = br_math::clamped_clog2(NumPopFlows) ) ( input logic clk, input logic rst, diff --git a/flow/rtl/br_flow_xbar_rr.sv b/flow/rtl/br_flow_xbar_rr.sv index 217869601..6fbb3e0fc 100644 --- a/flow/rtl/br_flow_xbar_rr.sv +++ b/flow/rtl/br_flow_xbar_rr.sv @@ -18,10 +18,10 @@ // becomes the highest priority. module br_flow_xbar_rr #( - // The number of input flows. Must be >=2. - parameter int NumPushFlows = 2, - // The number of output flows. Must be >=2. - parameter int NumPopFlows = 2, + // The number of input flows. Must be >=1. + parameter int NumPushFlows = 1, + // The number of output flows. Must be >=1. + parameter int NumPopFlows = 1, // The width of the data bus. parameter int Width = 1, // If 1, registers are inserted between the demux and mux to break up the @@ -49,7 +49,7 @@ module br_flow_xbar_rr #( // register stages are empty at end of simulation. parameter bit EnableAssertFinalNotValid = 1, - localparam int DestIdWidth = $clog2(NumPopFlows) + localparam int DestIdWidth = br_math::clamped_clog2(NumPopFlows) ) ( input logic clk, input logic rst, diff --git a/flow/rtl/internal/BUILD.bazel b/flow/rtl/internal/BUILD.bazel index ed206264c..827b0eacf 100644 --- a/flow/rtl/internal/BUILD.bazel +++ b/flow/rtl/internal/BUILD.bazel @@ -69,6 +69,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_arb_core_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -80,6 +81,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_mux_core_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -95,6 +97,7 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_mux_core_stable_test_suite", params = { "NumFlows": [ + "1", "2", "3", ], @@ -227,6 +230,7 @@ verilog_library( ":br_flow_mux_core", "//flow/rtl:br_flow_demux_select_unstable", "//flow/rtl:br_flow_reg_fwd", + "//pkg:br_math_pkg", ], ) @@ -234,10 +238,12 @@ br_verilog_elab_and_lint_test_suite( name = "br_flow_xbar_core_test_suite", params = { "NumPushFlows": [ + "1", "2", "4", ], "NumPopFlows": [ + "1", "2", "4", ], diff --git a/flow/rtl/internal/br_flow_arb_core.sv b/flow/rtl/internal/br_flow_arb_core.sv index ef9e00adb..430e64ec8 100644 --- a/flow/rtl/internal/br_flow_arb_core.sv +++ b/flow/rtl/internal/br_flow_arb_core.sv @@ -12,8 +12,8 @@ `include "br_unused.svh" module br_flow_arb_core #( - // Must be at least 2 - parameter int NumFlows = 2, + // Must be at least 1 + parameter int NumFlows = 1, // If 1, cover that the push side experiences backpressure. // If 0, assert that there is never backpressure. diff --git a/flow/rtl/internal/br_flow_mux_core.sv b/flow/rtl/internal/br_flow_mux_core.sv index 0eb4b2668..78a3a2cc3 100644 --- a/flow/rtl/internal/br_flow_mux_core.sv +++ b/flow/rtl/internal/br_flow_mux_core.sv @@ -16,7 +16,7 @@ `include "br_asserts_internal.svh" module br_flow_mux_core #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // Must be at least 1 // If 1, cover that the push side experiences backpressure. // If 0, assert that there is never backpressure. @@ -56,7 +56,7 @@ module br_flow_mux_core #( //------------------------------------------ // Integration checks //------------------------------------------ - `BR_ASSERT_STATIC(numflows_gte_2_a, NumFlows >= 2) + `BR_ASSERT_STATIC(numflows_gte_2_a, NumFlows >= 1) `BR_ASSERT_STATIC(datawidth_gte_1_a, Width >= 1) `BR_ASSERT_STATIC(pop_backpressure_implies_push_backpressure_a, !EnableCoverPopBackpressure || EnableCoverPushBackpressure) diff --git a/flow/rtl/internal/br_flow_mux_core_stable.sv b/flow/rtl/internal/br_flow_mux_core_stable.sv index cb04dd57f..cfcbdb96c 100644 --- a/flow/rtl/internal/br_flow_mux_core_stable.sv +++ b/flow/rtl/internal/br_flow_mux_core_stable.sv @@ -16,7 +16,7 @@ `include "br_asserts_internal.svh" module br_flow_mux_core_stable #( - parameter int NumFlows = 2, // Must be at least 2 + parameter int NumFlows = 1, // Must be at least 1 parameter int Width = 1, // Must be at least 1 // If 1, ensure that the pop ready signal is registered // at the input. This ensures there is no combinational path diff --git a/flow/rtl/internal/br_flow_xbar_core.sv b/flow/rtl/internal/br_flow_xbar_core.sv index 3e525fe08..e0f3ce697 100644 --- a/flow/rtl/internal/br_flow_xbar_core.sv +++ b/flow/rtl/internal/br_flow_xbar_core.sv @@ -6,8 +6,8 @@ `include "br_asserts_internal.svh" module br_flow_xbar_core #( - parameter int NumPushFlows = 2, - parameter int NumPopFlows = 2, + parameter int NumPushFlows = 1, + parameter int NumPopFlows = 1, parameter int Width = 1, parameter bit RegisterDemuxOutputs = 0, parameter bit RegisterPopOutputs = 0, @@ -19,7 +19,7 @@ module br_flow_xbar_core #( parameter bit EnableAssertPushDataKnown = 1, parameter bit EnableAssertFinalNotValid = 1, - localparam int DestIdWidth = $clog2(NumPopFlows) + localparam int DestIdWidth = br_math::clamped_clog2(NumPopFlows) ) ( input logic clk, input logic rst,