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sylvioalvessylvioalves
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locking: use local lock key instead of global
Make sure all peripherals in this PR use local irq_lock and irq_unlock instead of common nested reference. Signed-off-by: Sylvio Alves <[email protected]>
1 parent 3a53f5e commit 0724749

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19 files changed

+222
-316
lines changed

19 files changed

+222
-316
lines changed

‎components/driver/deprecated/adc_legacy.c

Lines changed: 45 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -45,11 +45,6 @@ static const char *ADC_TAG = "ADC";
4545
//////////////////////// Locks ///////////////////////////////////////////
4646
LOG_MODULE_REGISTER(adc_legacy, CONFIG_ADC_LOG_LEVEL);
4747

48-
extern int rtc_spinlock;
49-
50-
#define RTC_ENTER_CRITICAL() do { rtc_spinlock = irq_lock(); } while(0)
51-
#define RTC_EXIT_CRITICAL() irq_unlock(rtc_spinlock);
52-
5348
#define DIGI_ENTER_CRITICAL()
5449
#define DIGI_EXIT_CRITICAL()
5550

@@ -142,9 +137,9 @@ esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num)
142137
#if SOC_ADC_RTC_CTRL_SUPPORTED
143138
esp_err_t adc_set_clk_div(uint8_t clk_div)
144139
{
145-
DIGI_CONTROLLER_ENTER();
140+
unsigned int key = irq_lock();
146141
adc_ll_digi_set_clk_div(clk_div);
147-
DIGI_CONTROLLER_EXIT();
142+
irq_unlock(key);
148143
return ESP_OK;
149144
}
150145

@@ -195,15 +190,17 @@ esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
195190

196191
esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en)
197192
{
193+
unsigned int key;
194+
198195
if (adc_unit == ADC_UNIT_1) {
199-
SARADC1_ENTER();
196+
key = irq_lock();
200197
adc_oneshot_ll_output_invert(ADC_UNIT_1, inv_en);
201-
SARADC1_EXIT();
198+
irq_unlock(key);
202199
}
203200
if (adc_unit == ADC_UNIT_2) {
204-
SARADC2_ENTER();
201+
key = irq_lock();
205202
adc_oneshot_ll_output_invert(ADC_UNIT_2, inv_en);
206-
SARADC2_EXIT();
203+
irq_unlock(key);
207204
}
208205

209206
return ESP_OK;
@@ -213,6 +210,7 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit)
213210
{
214211
ESP_RETURN_ON_FALSE(width_bit < ADC_WIDTH_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "unsupported bit width");
215212
adc_bitwidth_t bitwidth = 0;
213+
unsigned int key;
216214
#if CONFIG_IDF_TARGET_ESP32
217215
if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) {
218216
bitwidth = SOC_ADC_RTC_MAX_BITWIDTH;
@@ -241,14 +239,14 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit)
241239
#endif
242240

243241
if (adc_unit == ADC_UNIT_1) {
244-
SARADC1_ENTER();
242+
key = irq_lock();
245243
adc_oneshot_ll_set_output_bits(ADC_UNIT_1, bitwidth);
246-
SARADC1_EXIT();
244+
irq_unlock(key);
247245
}
248246
if (adc_unit == ADC_UNIT_2) {
249-
SARADC2_ENTER();
247+
key = irq_lock();
250248
adc_oneshot_ll_set_output_bits(ADC_UNIT_2, bitwidth);
251-
SARADC2_EXIT();
249+
irq_unlock(key);
252250
}
253251

254252
return ESP_OK;
@@ -263,9 +261,9 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit)
263261
#if !CONFIG_IDF_TARGET_ESP32
264262
esp_err_t adc_rtc_reset(void)
265263
{
266-
FSM_ENTER();
264+
unsigned int key = irq_lock();
267265
adc_ll_rtc_reset();
268-
FSM_EXIT();
266+
irq_unlock(key);
269267
return ESP_OK;
270268
}
271269
#endif
@@ -286,10 +284,10 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
286284
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
287285

288286
adc_common_gpio_init(ADC_UNIT_1, channel);
289-
SARADC1_ENTER();
287+
unsigned int key = irq_lock();
290288
adc_rtc_chan_init(ADC_UNIT_1);
291289
adc_oneshot_ll_set_atten(ADC_UNIT_1, channel, atten);
292-
SARADC1_EXIT();
290+
irq_unlock(key);
293291

294292
return ESP_OK;
295293
}
@@ -325,9 +323,9 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit)
325323
bitwidth = ADC_BITWIDTH_12;
326324
#endif
327325

328-
SARADC1_ENTER();
326+
unsigned int key = irq_lock();
329327
adc_oneshot_ll_set_output_bits(ADC_UNIT_1, bitwidth);
330-
SARADC1_EXIT();
328+
irq_unlock(key);
331329

332330
return ESP_OK;
333331
}
@@ -341,10 +339,10 @@ esp_err_t adc1_dma_mode_acquire(void)
341339

342340
sar_periph_ctrl_adc_continuous_power_acquire();
343341

344-
SARADC1_ENTER();
342+
unsigned int key = irq_lock();
345343
/* switch SARADC into DIG channel */
346344
adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
347-
SARADC1_EXIT();
345+
irq_unlock(key);
348346

349347
return ESP_OK;
350348
}
@@ -356,10 +354,10 @@ esp_err_t adc1_rtc_mode_acquire(void)
356354
SARADC1_ACQUIRE();
357355
sar_periph_ctrl_adc_oneshot_power_acquire();
358356

359-
SARADC1_ENTER();
357+
unsigned int key = irq_lock();
360358
/* switch SARADC into RTC channel. */
361359
adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_RTC);
362-
SARADC1_EXIT();
360+
irq_unlock(key);
363361

364362
return ESP_OK;
365363
}
@@ -386,7 +384,7 @@ int adc1_get_raw(adc1_channel_t channel)
386384
adc_set_hw_calibration_code(ADC_UNIT_1, atten);
387385
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
388386

389-
SARADC1_ENTER();
387+
unsigned int key = irq_lock();
390388
#ifdef CONFIG_IDF_TARGET_ESP32
391389
adc_ll_hall_disable(); //Disable other peripherals.
392390
adc_ll_amp_disable(); //Currently the LNA is not open, close it by default.
@@ -397,7 +395,7 @@ int adc1_get_raw(adc1_channel_t channel)
397395
#if !CONFIG_IDF_TARGET_ESP32
398396
adc_ll_rtc_reset(); //Reset FSM of rtc controller
399397
#endif
400-
SARADC1_EXIT();
398+
irq_unlock(key);
401399

402400
adc1_lock_release();
403401
return adc_value;
@@ -413,7 +411,7 @@ void adc1_ulp_enable(void)
413411
{
414412
sar_periph_ctrl_adc_oneshot_power_acquire();
415413

416-
SARADC1_ENTER();
414+
unsigned int key = irq_lock();
417415
adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_ULP);
418416
/* since most users do not need LNA and HALL with uLP, we disable them here
419417
open them in the uLP if needed. */
@@ -422,7 +420,7 @@ void adc1_ulp_enable(void)
422420
adc_ll_hall_disable();
423421
adc_ll_amp_disable();
424422
#endif
425-
SARADC1_EXIT();
423+
irq_unlock(key);
426424
}
427425
#endif
428426

@@ -452,10 +450,10 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
452450
#endif
453451

454452
//avoid collision with other tasks
455-
SARADC2_ENTER();
453+
unsigned int key = irq_lock();
456454
adc_rtc_chan_init(ADC_UNIT_2);
457455
adc_oneshot_ll_set_atten(ADC_UNIT_2, channel, atten);
458-
SARADC2_EXIT();
456+
irq_unlock(key);
459457

460458
#if CONFIG_IDF_TARGET_ESP32
461459
adc_lock_release(ADC_UNIT_2);
@@ -553,7 +551,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
553551

554552
//avoid collision with other tasks
555553
adc2_init(); // in critical section with whole rtc module. because the PWDET use the same registers, place it here.
556-
SARADC2_ENTER();
554+
unsigned int key = irq_lock();
557555

558556
#if SOC_ADC_ARBITER_SUPPORTED
559557
adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
@@ -593,7 +591,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
593591
}
594592
#endif //CONFIG_PM_ENABLE
595593
#endif //CONFIG_IDF_TARGET_ESP32
596-
SARADC2_EXIT();
594+
irq_unlock(key);
597595

598596
sar_periph_ctrl_adc_oneshot_power_release();
599597
#if CONFIG_IDF_TARGET_ESP32
@@ -606,6 +604,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
606604

607605
esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
608606
{
607+
unsigned int key;
609608
#ifdef CONFIG_IDF_TARGET_ESP32
610609
if (adc_unit == ADC_UNIT_1) {
611610
return ESP_ERR_INVALID_ARG;
@@ -625,13 +624,13 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
625624

626625
sar_periph_ctrl_adc_oneshot_power_acquire();
627626
if (adc_unit == ADC_UNIT_1) {
628-
VREF_ENTER(1);
627+
key = irq_lock();
629628
adc_ll_vref_output(ADC_UNIT_1, ch, true);
630-
VREF_EXIT(1);
629+
irq_unlock(key);
631630
} else if (adc_unit == ADC_UNIT_2) {
632-
VREF_ENTER(2);
631+
key = irq_lock();
633632
adc_ll_vref_output(ADC_UNIT_2, ch, true);
634-
VREF_EXIT(2);
633+
irq_unlock(key);
635634
}
636635

637636
//Configure RTC gpio, Only ADC2's channels IO are supported to output reference voltage.
@@ -650,10 +649,6 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
650649
---------------------------------------------------------------*/
651650
#include "esp_check.h"
652651

653-
int adc_reg_lock;
654-
#define ADC_REG_LOCK_ENTER() do { adc_reg_lock = irq_lock(); } while(0)
655-
#define ADC_REG_LOCK_EXIT() irq_unlock(adc_reg_lock);
656-
657652
static adc_atten_t s_atten1_single[ADC1_CHANNEL_MAX]; //Array saving attenuate of each channel of ADC1, used by single read API
658653
#if (SOC_ADC_PERIPH_NUM >= 2)
659654
static adc_atten_t s_atten2_single[ADC2_CHANNEL_MAX]; //Array saving attenuate of each channel of ADC2, used by single read API
@@ -703,6 +698,7 @@ static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
703698
esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
704699
{
705700
esp_err_t ret;
701+
unsigned int key;
706702
uint32_t channel = ADC2_CHANNEL_MAX;
707703
if (adc_unit == ADC_UNIT_2) {
708704
for (int i = 0; i < ADC2_CHANNEL_MAX; i++) {
@@ -718,13 +714,13 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
718714

719715
sar_periph_ctrl_adc_oneshot_power_acquire();
720716
if (adc_unit == ADC_UNIT_1) {
721-
RTC_ENTER_CRITICAL();
717+
key = irq_lock();
722718
adc_ll_vref_output(ADC_UNIT_1, channel, true);
723-
RTC_EXIT_CRITICAL();
719+
irq_unlock(key);
724720
} else { //ADC_UNIT_2
725-
RTC_ENTER_CRITICAL();
721+
key = irq_lock();
726722
adc_ll_vref_output(ADC_UNIT_2, channel, true);
727-
RTC_EXIT_CRITICAL();
723+
irq_unlock(key);
728724
}
729725

730726
ret = adc_digi_gpio_init(ADC_UNIT_2, BIT(channel));
@@ -778,10 +774,10 @@ int adc1_get_raw(adc1_channel_t channel)
778774
adc_set_hw_calibration_code(ADC_UNIT_1, atten);
779775
#endif
780776

781-
ADC_REG_LOCK_ENTER();
777+
unsigned int key = irq_lock();
782778
adc_oneshot_ll_set_atten(ADC_UNIT_1, channel, atten);
783779
adc_hal_convert(ADC_UNIT_1, channel, clk_src_freq_hz, &raw_out);
784-
ADC_REG_LOCK_EXIT();
780+
irq_unlock(key);
785781

786782
sar_periph_ctrl_adc_oneshot_power_release();
787783
periph_module_disable(PERIPH_SARADC_MODULE);
@@ -834,10 +830,10 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
834830
adc_set_hw_calibration_code(ADC_UNIT_2, atten);
835831
#endif
836832

837-
ADC_REG_LOCK_ENTER();
833+
unsigned int key = irq_lock();
838834
adc_oneshot_ll_set_atten(ADC_UNIT_2, channel, atten);
839835
ret = adc_hal_convert(ADC_UNIT_2, channel, clk_src_freq_hz, raw_out);
840-
ADC_REG_LOCK_EXIT();
836+
irq_unlock(key);
841837

842838
sar_periph_ctrl_adc_oneshot_power_release();
843839
periph_module_disable(PERIPH_SARADC_MODULE);

‎components/driver/deprecated/dac_common_legacy.c

Lines changed: 14 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -16,11 +16,6 @@
1616
#include "hal/dac_ll.h"
1717
#include "clk_ctrl_os.h"
1818

19-
extern int rtc_spinlock;
20-
21-
#define RTC_ENTER_CRITICAL() do { rtc_spinlock = irq_lock(); } while(0)
22-
#define RTC_EXIT_CRITICAL() irq_unlock(rtc_spinlock);
23-
2419
static __attribute__((unused)) const char *TAG = "DAC";
2520

2621
/*---------------------------------------------------------------
@@ -54,10 +49,10 @@ esp_err_t dac_output_enable(dac_channel_t channel)
5449
ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error");
5550

5651
dac_rtc_pad_init(channel);
57-
RTC_ENTER_CRITICAL();
52+
unsigned int key = irq_lock();
5853
dac_ll_power_on(channel);
5954
dac_ll_rtc_sync_by_adc(false);
60-
RTC_EXIT_CRITICAL();
55+
irq_unlock(key);
6156

6257
return ESP_OK;
6358
}
@@ -66,9 +61,9 @@ esp_err_t dac_output_disable(dac_channel_t channel)
6661
{
6762
ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error");
6863

69-
RTC_ENTER_CRITICAL();
64+
unsigned int key = irq_lock();
7065
dac_ll_power_down(channel);
71-
RTC_EXIT_CRITICAL();
66+
irq_unlock(key);
7267

7368
return ESP_OK;
7469
}
@@ -77,9 +72,9 @@ esp_err_t dac_output_voltage(dac_channel_t channel, uint8_t dac_value)
7772
{
7873
ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error");
7974

80-
RTC_ENTER_CRITICAL();
75+
unsigned int key = irq_lock();
8176
dac_ll_update_output_value(channel, dac_value);
82-
RTC_EXIT_CRITICAL();
77+
irq_unlock(key);
8378

8479
return ESP_OK;
8580
}
@@ -88,37 +83,37 @@ esp_err_t dac_out_voltage(dac_channel_t channel, uint8_t dac_value)
8883
{
8984
ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error");
9085

91-
RTC_ENTER_CRITICAL();
86+
unsigned int key = irq_lock();
9287
dac_ll_update_output_value(channel, dac_value);
93-
RTC_EXIT_CRITICAL();
88+
irq_unlock(key);
9489

9590
return ESP_OK;
9691
}
9792

9893
esp_err_t dac_cw_generator_enable(void)
9994
{
100-
RTC_ENTER_CRITICAL();
95+
unsigned int key = irq_lock();
10196
periph_rtc_dig_clk8m_enable();
10297
dac_ll_cw_generator_enable();
103-
RTC_EXIT_CRITICAL();
98+
irq_unlock(key);
10499

105100
return ESP_OK;
106101
}
107102

108103
esp_err_t dac_cw_generator_disable(void)
109104
{
110-
RTC_ENTER_CRITICAL();
105+
unsigned int key = irq_lock();
111106
dac_ll_cw_generator_disable();
112107
periph_rtc_dig_clk8m_disable();
113-
RTC_EXIT_CRITICAL();
108+
irq_unlock(key);
114109

115110
return ESP_OK;
116111
}
117112

118113
esp_err_t dac_cw_generator_config(dac_cw_config_t *cw)
119114
{
120115
ESP_RETURN_ON_FALSE(cw, ESP_ERR_INVALID_ARG, TAG, "invalid clock configuration");
121-
RTC_ENTER_CRITICAL();
116+
unsigned int key = irq_lock();
122117
/* Enable the rtc8m clock temporary to get the correct frequency */
123118
periph_rtc_dig_clk8m_enable();
124119
uint32_t rtc_freq = periph_rtc_dig_clk8m_get_freq();
@@ -128,7 +123,7 @@ esp_err_t dac_cw_generator_config(dac_cw_config_t *cw)
128123
dac_ll_cw_set_phase(cw->en_ch, (dac_cosine_phase_t)cw->phase);
129124
dac_ll_cw_set_dc_offset(cw->en_ch, cw->offset);
130125
dac_ll_cw_enable_channel(cw->en_ch, true);
131-
RTC_EXIT_CRITICAL();
126+
irq_unlock(key);
132127

133128
return ESP_OK;
134129
}

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