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nzmichaelhnzmichaelh
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samples: pwm: add the linkw to the blinky_pwm and led/pwm samples
The CH32V208 based linkw has a green and a blue LED that can be driven by GPIO or TIM3. Add to the samples. Signed-off-by: Michael Hope <[email protected]>
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6 files changed

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lines changed

‎boards/wch/linkw/linkw-pinctrl.dtsi‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,4 +18,19 @@
1818
bias-pull-up;
1919
};
2020
};
21+
22+
pwmleds_default: pwmleds_default {
23+
group1 {
24+
pinmux = <TIM3_CH2_PC7_2>;
25+
output-high;
26+
drive-push-pull;
27+
slew-rate = "max-speed-10mhz";
28+
};
29+
group2 {
30+
pinmux = <TIM3_CH4_PC9_2>;
31+
output-high;
32+
drive-push-pull;
33+
slew-rate = "max-speed-10mhz";
34+
};
35+
};
2136
};

‎boards/wch/linkw/linkw.dts‎

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
#include <wch/ch32v208/ch32v208gbu.dtsi>
99
#include <zephyr/dt-bindings/gpio/gpio.h>
1010
#include <zephyr/dt-bindings/input/input-event-codes.h>
11+
#include <zephyr/dt-bindings/pwm/pwm.h>
1112
#include "linkw-pinctrl.dtsi"
1213

1314
/ {
@@ -34,6 +35,21 @@
3435
};
3536
};
3637

38+
pwmleds: pwmleds {
39+
compatible = "pwm-leds";
40+
status = "disabled";
41+
42+
green_pwm: green_pwm0 {
43+
pwms = <&pwm3 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
44+
label = "Green LED";
45+
};
46+
47+
blue_pwm: blue_pwm0 {
48+
pwms = <&pwm3 3 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
49+
label = "Blue LED";
50+
};
51+
};
52+
3753
buttons {
3854
compatible = "gpio-keys";
3955

@@ -51,6 +67,7 @@
5167
aliases {
5268
led0 = &blue_led;
5369
sw0 = &mode;
70+
pwm-led0 = &green_pwm;
5471
};
5572
};
5673

@@ -59,8 +76,12 @@
5976
status = "okay";
6077
};
6178

79+
&clk_hsi {
80+
status = "okay";
81+
};
82+
6283
&pll {
63-
clocks = <&clk_hse>;
84+
clocks = <&clk_hsi>;
6485
status = "okay";
6586
};
6687

‎dts/riscv/wch/ch32v208/ch32v208.dtsi‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -149,6 +149,63 @@
149149
reg = <0x40021000 16>;
150150
#clock-cells = <1>;
151151
};
152+
153+
tim2: counter@40000000 {
154+
compatible = "wch,gptm";
155+
reg = <0x40000000 16>;
156+
prescaler = <1>;
157+
channels = <4>;
158+
clocks = <&rcc CH32V20X_V30X_CLOCK_TIM2>;
159+
interrupt-parent = <&pfic>;
160+
interrupts = <44>;
161+
interrupt-names = "global";
162+
status = "disabled";
163+
164+
pwm2: pwm {
165+
compatible = "wch,gptm-pwm";
166+
pwm-controller;
167+
#pwm-cells = <3>;
168+
status = "disabled";
169+
};
170+
};
171+
172+
tim3: counter@40000400 {
173+
compatible = "wch,gptm";
174+
reg = <0x40000400 16>;
175+
prescaler = <1>;
176+
channels = <4>;
177+
clocks = <&rcc CH32V20X_V30X_CLOCK_TIM3>;
178+
interrupt-parent = <&pfic>;
179+
interrupts = <45>;
180+
interrupt-names = "global";
181+
status = "disabled";
182+
183+
pwm3: pwm {
184+
compatible = "wch,gptm-pwm";
185+
pwm-controller;
186+
#pwm-cells = <3>;
187+
status = "disabled";
188+
};
189+
};
190+
191+
tim4: counter@40000800 {
192+
compatible = "wch,gptm";
193+
reg = <0x40000800 16>;
194+
prescaler = <1>;
195+
channels = <4>;
196+
clocks = <&rcc CH32V20X_V30X_CLOCK_TIM4>;
197+
interrupt-parent = <&pfic>;
198+
interrupts = <46>;
199+
interrupt-names = "global";
200+
status = "disabled";
201+
202+
pwm4: pwm {
203+
compatible = "wch,gptm-pwm";
204+
pwm-controller;
205+
#pwm-cells = <3>;
206+
status = "disabled";
207+
};
208+
};
152209
};
153210
};
154211

‎include/zephyr/dt-bindings/pinctrl/ch32v20x_30x-pinctrl.h‎

Lines changed: 151 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,4 +177,155 @@
177177
#define I2C1_SDA_PB7_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 7, I2C1, 0)
178178
#define I2C1_SDA_PB9_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, I2C1, 1)
179179

180+
#define TIM1_ETR_PA12_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, TIM1, 0)
181+
#define TIM1_ETR_PA12_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, TIM1, 1)
182+
#define TIM1_ETR_PE7_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 7, TIM1, 2)
183+
#define TIM1_CH1_PA8_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 8, TIM1, 0)
184+
#define TIM1_CH1_PA8_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 8, TIM1, 1)
185+
#define TIM1_CH1_PE9_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 9, TIM1, 2)
186+
#define TIM1_CH2_PA9_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 9, TIM1, 0)
187+
#define TIM1_CH2_PA9_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 9, TIM1, 1)
188+
#define TIM1_CH2_PE11_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 11, TIM1, 2)
189+
#define TIM1_CH3_PA10_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 10, TIM1, 0)
190+
#define TIM1_CH3_PA10_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 10, TIM1, 1)
191+
#define TIM1_CH3_PE13_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 13, TIM1, 2)
192+
#define TIM1_CH4_PA11_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 11, TIM1, 0)
193+
#define TIM1_CH4_PA11_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 11, TIM1, 1)
194+
#define TIM1_CH4_PE14_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 14, TIM1, 2)
195+
#define TIM1_BKIN_PB12_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 12, TIM1, 0)
196+
#define TIM1_BKIN_PA6_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, TIM1, 1)
197+
#define TIM1_BKIN_PE15_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 15, TIM1, 2)
198+
#define TIM1_CH1N_PB13_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 13, TIM1, 0)
199+
#define TIM1_CH1N_PA7_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, TIM1, 1)
200+
#define TIM1_CH1N_PE8_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 8, TIM1, 2)
201+
#define TIM1_CH2N_PB14_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 14, TIM1, 0)
202+
#define TIM1_CH2N_PB0_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, TIM1, 1)
203+
#define TIM1_CH2N_PE10_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 10, TIM1, 2)
204+
#define TIM1_CH3N_PB15_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 15, TIM1, 0)
205+
#define TIM1_CH3N_PB1_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, TIM1, 1)
206+
#define TIM1_CH3N_PE12_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 12, TIM1, 2)
207+
208+
#define TIM2_ETR_PA0_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM2, 0)
209+
#define TIM2_ETR_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, TIM2, 1)
210+
#define TIM2_ETR_PA0_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM2, 2)
211+
#define TIM2_ETR_PA15_3 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, TIM2, 3)
212+
#define TIM2_CH1_PA0_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM2, 0)
213+
#define TIM2_CH1_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, TIM2, 1)
214+
#define TIM2_CH1_PA0_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM2, 2)
215+
#define TIM2_CH1_PA15_3 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, TIM2, 3)
216+
#define TIM2_CH2_PA1_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 1, TIM2, 0)
217+
#define TIM2_CH2_PB3_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, TIM2, 1)
218+
#define TIM2_CH2_PA1_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 1, TIM2, 2)
219+
#define TIM2_CH2_PB3_3 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, TIM2, 3)
220+
#define TIM2_CH3_PA2_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM2, 0)
221+
#define TIM2_CH3_PA2_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM2, 1)
222+
#define TIM2_CH3_PB10_2 CH32V20X_V30X_PINMUX_DEFINE(PB, 10, TIM2, 2)
223+
#define TIM2_CH3_PB10_3 CH32V20X_V30X_PINMUX_DEFINE(PB, 10, TIM2, 3)
224+
#define TIM2_CH4_PA3_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, TIM2, 0)
225+
#define TIM2_CH4_PA3_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, TIM2, 1)
226+
#define TIM2_CH4_PB11_2 CH32V20X_V30X_PINMUX_DEFINE(PB, 11, TIM2, 2)
227+
#define TIM2_CH4_PB11_3 CH32V20X_V30X_PINMUX_DEFINE(PB, 11, TIM2, 3)
228+
229+
#define TIM3_CH1_PA6_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, TIM3, 0)
230+
#define TIM3_CH1_PB4_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, TIM3, 1)
231+
#define TIM3_CH1_PC6_2 CH32V20X_V30X_PINMUX_DEFINE(PC, 6, TIM3, 2)
232+
#define TIM3_CH2_PA7_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, TIM3, 0)
233+
#define TIM3_CH2_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, TIM3, 1)
234+
#define TIM3_CH2_PC7_2 CH32V20X_V30X_PINMUX_DEFINE(PC, 7, TIM3, 2)
235+
#define TIM3_CH3_PB0_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, TIM3, 0)
236+
#define TIM3_CH3_PB0_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, TIM3, 1)
237+
#define TIM3_CH3_PC8_2 CH32V20X_V30X_PINMUX_DEFINE(PC, 8, TIM3, 2)
238+
#define TIM3_CH4_PB1_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, TIM3, 0)
239+
#define TIM3_CH4_PB1_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, TIM3, 1)
240+
#define TIM3_CH4_PC9_2 CH32V20X_V30X_PINMUX_DEFINE(PC, 9, TIM3, 2)
241+
242+
#define TIM4_CH1_PB6_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 6, TIM4, 0)
243+
#define TIM4_CH1_PD12_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 12, TIM4, 1)
244+
#define TIM4_CH2_PB7_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 7, TIM4, 0)
245+
#define TIM4_CH2_PD13_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 13, TIM4, 1)
246+
#define TIM4_CH3_PB8_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, TIM4, 0)
247+
#define TIM4_CH3_PD14_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 14, TIM4, 1)
248+
#define TIM4_CH4_PB9_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, TIM4, 0)
249+
#define TIM4_CH4_PD15_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 15, TIM4, 1)
250+
251+
#define TIM5_CH4_PA3_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, TIM5, 0)
252+
#define TIM5_CH4_LSI_1 CH32V20X_V30X_PINMUX_DEFINE(LS, I, TIM5, 1)
253+
#define TIM5_CH4_internal_2 CH32V20X_V30X_PINMUX_DEFINE(in, ternal, TIM5, 2)
254+
#define TIM5_CH4_clock_3 CH32V20X_V30X_PINMUX_DEFINE(cl, ock, TIM5, 3)
255+
256+
#define TIM8_ETR_PA0_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM8, 0)
257+
#define TIM8_ETR_PA0_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM8, 1)
258+
#define TIM8_CH1_PC6_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 6, TIM8, 0)
259+
#define TIM8_CH1_PB6_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 6, TIM8, 1)
260+
#define TIM8_CH2_PC7_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 7, TIM8, 0)
261+
#define TIM8_CH2_PB7_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 7, TIM8, 1)
262+
#define TIM8_CH3_PC8_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 8, TIM8, 0)
263+
#define TIM8_CH3_PB8_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, TIM8, 1)
264+
#define TIM8_CH4_PC9_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 9, TIM8, 0)
265+
#define TIM8_CH4_PC13_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 13, TIM8, 1)
266+
#define TIM8_BKIN_PA6_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, TIM8, 0)
267+
#define TIM8_BKIN_PB9_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, TIM8, 1)
268+
#define TIM8_CH1N_PA7_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, TIM8, 0)
269+
#define TIM8_CH1N_PA13_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 13, TIM8, 1)
270+
#define TIM8_CH2N_PB0_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, TIM8, 0)
271+
#define TIM8_CH2N_PA14_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 14, TIM8, 1)
272+
#define TIM8_CH3N_PB1_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, TIM8, 0)
273+
#define TIM8_CH3N_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, TIM8, 1)
274+
275+
#define TIM9_ETR_PA2_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM9, 0)
276+
#define TIM9_ETR_PA2_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM9, 1)
277+
#define TIM9_ETR_PD9_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 9, TIM9, 2)
278+
#define TIM9_CH1_PA2_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM9, 0)
279+
#define TIM9_CH1_PA2_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM9, 1)
280+
#define TIM9_CH1_PD9_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 9, TIM9, 2)
281+
#define TIM9_CH2_PA3_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, TIM9, 0)
282+
#define TIM9_CH2_PA3_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, TIM9, 1)
283+
#define TIM9_CH2_PD11_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 11, TIM9, 2)
284+
#define TIM9_CH3_PA4_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, TIM9, 0)
285+
#define TIM9_CH3_PA4_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, TIM9, 1)
286+
#define TIM9_CH3_PD13_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 13, TIM9, 2)
287+
#define TIM9_CH4_PC4_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 4, TIM9, 0)
288+
#define TIM9_CH4_PC14_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 14, TIM9, 1)
289+
#define TIM9_CH4_PD15_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 15, TIM9, 2)
290+
#define TIM9_BKIN_PC5_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 5, TIM9, 0)
291+
#define TIM9_BKIN_PA1_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 1, TIM9, 1)
292+
#define TIM9_BKIN_PD14_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 14, TIM9, 2)
293+
#define TIM9_CH1N_PC0_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 0, TIM9, 0)
294+
#define TIM9_CH1N_PB0_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, TIM9, 1)
295+
#define TIM9_CH1N_PD8_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 8, TIM9, 2)
296+
#define TIM9_CH2N_PC1_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 1, TIM9, 0)
297+
#define TIM9_CH2N_PB1_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, TIM9, 1)
298+
#define TIM9_CH2N_PD10_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 10, TIM9, 2)
299+
#define TIM9_CH3N_PC2_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 2, TIM9, 0)
300+
#define TIM9_CH3N_PB2_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 2, TIM9, 1)
301+
#define TIM9_CH3N_PD12_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 12, TIM9, 2)
302+
303+
#define TIM10_ETR_PC10_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 10, TIM10, 0)
304+
#define TIM10_ETR_PB11_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 11, TIM10, 1)
305+
#define TIM10_ETR_PD0_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 0, TIM10, 2)
306+
#define TIM10_CH1_PB8_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, TIM10, 0)
307+
#define TIM10_CH1_PB3_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, TIM10, 1)
308+
#define TIM10_CH1_PD1_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 1, TIM10, 2)
309+
#define TIM10_CH2_PB9_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, TIM10, 0)
310+
#define TIM10_CH2_PB4_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, TIM10, 1)
311+
#define TIM10_CH2_PD3_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 3, TIM10, 2)
312+
#define TIM10_CH3_PC3_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 3, TIM10, 0)
313+
#define TIM10_CH3_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, TIM10, 1)
314+
#define TIM10_CH3_PD5_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 5, TIM10, 2)
315+
#define TIM10_CH4_PC11_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 11, TIM10, 0)
316+
#define TIM10_CH4_PC15_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 15, TIM10, 1)
317+
#define TIM10_CH4_PD7_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 7, TIM10, 2)
318+
#define TIM10_BKIN_PC12_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 12, TIM10, 0)
319+
#define TIM10_BKIN_PB10_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 10, TIM10, 1)
320+
#define TIM10_BKIN_PE2_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 2, TIM10, 2)
321+
#define TIM10_CH1N_PA12_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, TIM10, 0)
322+
#define TIM10_CH1N_PA5_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, TIM10, 1)
323+
#define TIM10_CH1N_PE3_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 3, TIM10, 2)
324+
#define TIM10_CH2N_PA13_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 13, TIM10, 0)
325+
#define TIM10_CH2N_PA6_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, TIM10, 1)
326+
#define TIM10_CH2N_PE4_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 4, TIM10, 2)
327+
#define TIM10_CH3N_PA14_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 14, TIM10, 0)
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#define TIM10_CH3N_PA7_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, TIM10, 1)
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#define TIM10_CH3N_PE5_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 5, TIM10, 2)
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180331
#endif /* __CH32V20X_V30X_PINCTRL_H__ */

‎samples/basic/blinky_pwm/boards/linkw.overlay‎

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/*
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* Copyright (c) 2025 Michael Hope <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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leds {
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status = "disabled";
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};
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};
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&pwmleds {
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status = "okay";
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};
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&tim3 {
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status = "okay";
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/*
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* The sample runs from 1 Hz to 128 Hz, ceil(144 MHz / 65536 / 1 Hz)
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* is 2198, and the prescaler property is one less than that.
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*/
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prescaler = <2197>;
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};
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&pwm3 {
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status = "okay";
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pinctrl-0 = <&pwmleds_default>;
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pinctrl-names = "default";
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};

‎samples/drivers/led/pwm/boards/linkw.overlay‎

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/*
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* Copyright (c) 2025 Michael Hope <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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leds {
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status = "disabled";
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};
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};
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&pwmleds {
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status = "okay";
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};
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&tim3 {
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status = "okay";
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/*
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* The sample blinks the LED at 0.5 Hz, ceil(144 MHz / 65536 / 0.5 Hz)
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* is 4395, and the prescaler property is one less than that.
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*/
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prescaler = <4394>;
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};
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&pwm3 {
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status = "okay";
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pinctrl-0 = <&pwmleds_default>;
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pinctrl-names = "default";
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};

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