Downlinks fail in lowaran class_a sample with lora-e5 board

[caproc]

Hi,
I'm planning to move Zephyr with my LoRaWAN applications and started from the scratch with LoRaWAN class_a sample. I'm using Lora-E5 module, so picked existing lora_e5_dev_board for testing. I have Seeed LoRa-E5 mini, but that should be close to identical to LoRa-E5 Development Kit (lora_e5_dev_board) for simple LoRaWAN testing.

So, I took class_a sample added keys and counter for dev_nonce (required in LoRaWAN 1.0.4). Made 1.0.4 version device in LoRaWAN server and started sending sample messages with ACK request (LORAWAN_MSG_CONFIRMED).

OTAA join works ok and messages are sent to LoRaWAN server ok. The problem is with downlinks.
I'm getting following error..

␛[1;31m lorawan: McpsRequest failed : Rx 2 timeout␛[0m
␛[1;31m lorawan_class_a: lorawan_send failed: -116␛[0m

I guess the stack is expecting the ACK downlink, but not getting any and fails after timeout.
I tried to send some downlinks from LoRaWAN server as well, but they are not coming through either.
LoRaWAN server sends ack downlinks and regulars downlinks as expected after each uplink, but for some reason they do not reach the device.

After playing for a while I noticed that some downlinks are received after all. Only the ones with SF12, but not the ones with SF9.

I also tried the same device with MBED LoRaWAN test application and it works just fine for both uplinks and downlinks. So, I can rule out signal strength / network issues..

I'm new to Zephyr, so probably I'm missing some configuration that is required for STM32WL / Lora-E5 module.

Thank you in advance for the advice!

[knthm]

How far are you from your gateway and what is the RSSI for the downlink in MBED?

Currently the LoRaMac-node code used in Zephyr for the STM32WL doesn't set the highest Rx gain, so it may very well be related to signal strength.

[caproc]

It was RX timing issue. I increased CONFIG_LORAWAN_SYSTEM_MAX_RX_ERROR from default 20 to 90 and it started to work.

[knthm]

Ahh that's interesting, I had gone down a similar path when I had downlink timing issues on a nRF52840/SX1262-based board.

I wonder what the LFXO frequency tolerance is on the Lora-E5 and how much its drift plays a part in this. I'm not sure it's even considered by the clock control subsystem, seeing how there doesn't seem to be DTS/Kconfig properties to set clock tolerances (somebody correct me if I'm wrong).