STM32H757 - Configuration of FMC for both SDRAM and SRAM

[mathiasee]

I am working on a custom board with a STM32H757, the issues are when i try to use the FMC to interface with both a external SDRAM and a external SRAM.

I have looked in a examples and could find st board that have both, but none where the device tree has been made.

This is how I have set it up in my dts file

#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>

    sdram2: sdram@d0000000 {
        compatible = "zephyr,memory-region", "mmio-sram";
        device_type = "memory";
        reg = <0xd0000000 DT_SIZE_M(32)>;
        zephyr,memory-region = "SDRAM2";
        zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
    };

    ram0: sram@68000000 {
        compatible = "zephyr,memory-region", "mmio-sram";
        device_type = "memory";
        reg = <0x68000000 DT_SIZE_M(8)>;
        zephyr,memory-region = "RAM0";
        zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
    };

&fmc {
    status = "okay";
    pinctrl-0 = <   &fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4 &fmc_nbl3_pi5 &fmc_sdclk_pg8 
                    &fmc_sdnwe_ph5 &fmc_sdne1_ph6 &fmc_sdcke1_ph7 &fmc_sdnras_pf11 &fmc_sdncas_pg15    
                    &fmc_ne3_pg10  &fmc_nwe_pd5  &fmc_noe_pd4 
                    &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4 &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 
                    &fmc_a8_pf14 &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2 &fmc_a14_pg4 &fmc_a15_pg5  
                    &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10 
                    &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9             
                    &fmc_d15_pd10 &fmc_d16_ph8 &fmc_d17_ph9 &fmc_d18_ph10 &fmc_d19_ph11 &fmc_d20_ph12 &fmc_d21_ph13 
                    &fmc_d22_ph14 &fmc_d23_ph15 &fmc_d24_pi0 &fmc_d25_pi1 &fmc_d26_pi2 &fmc_d27_pi3 &fmc_d28_pi6 
                    &fmc_d29_pi7 &fmc_d30_pi9 &fmc_d31_pi10 >;
    pinctrl-names = "default";

    sdram {
        status = "okay";

        power-up-delay = <100>;
        num-auto-refresh = <8>;
        mode-register = <0x220>;
        refresh-rate = <603>;

        bank@1 {
            reg = <1>;
            st,sdram-control = <STM32_FMC_SDRAM_NC_9
                STM32_FMC_SDRAM_NR_12
                STM32_FMC_SDRAM_MWID_32
                STM32_FMC_SDRAM_NB_4
                STM32_FMC_SDRAM_CAS_2
                STM32_FMC_SDRAM_SDCLK_PERIOD_2
                STM32_FMC_SDRAM_RBURST_ENABLE
                STM32_FMC_SDRAM_RPIPE_0>;
            st,sdram-timing = <2 7 4 7 2 2 2>;
        };
    };

    sram {
      status = "okay";
      compatible = "st,stm32-fmc-nor-psram";

      #address-cells = <1>;
      #size-cells = <0>;

      bank@2 {
        reg = <0x2>;
        st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
                      STM32_FMC_MEMORY_TYPE_SRAM
                      STM32_FMC_NORSRAM_MEM_BUS_WIDTH_32
                      STM32_FMC_BURST_ACCESS_MODE_DISABLE
                      STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
                      STM32_FMC_WAIT_TIMING_BEFORE_WS
                      STM32_FMC_WRITE_OPERATION_ENABLE
                      STM32_FMC_WAIT_SIGNAL_DISABLE
                      STM32_FMC_EXTENDED_MODE_DISABLE
                      STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
                      STM32_FMC_WRITE_BURST_DISABLE
                      STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
                      STM32_FMC_WRITE_FIFO_DISABLE
                      STM32_FMC_PAGE_SIZE_NONE>;
      st,timing = <4 2 3 0 16 17 STM32_FMC_ACCESS_MODE_A>;
      };
    };
};

In prj.conf I have enabled the following:

CONFIG_ARM_MPU=y

CONFIG_MEMC=y
CONFIG_MEMC_STM32=y
CONFIG_MEMC_STM32_SDRAM=y
CONFIG_MEMC_STM32_NOR_PSRAM=y

The project compiles fine and I am able to flash my board, however the running code does not get that far.
In my code I access the SRAM and SDRAM directy by address, but this causes a arch_system_halt reason 26 when accessing the SRAM.

// First the SDRAM, this works 
    for(uint32_t i=0; i<memSize; ++i){
        *(volatile uint32_t*) (0xd0000000 + 4*i) = 4*i;
       result = *(volatile uint32_t*) (0xd0000000 + 4*i);
    }    
// Then SRAM, this causes a fault 
        *(volatile uint32_t*) (0x68000000+ 0x100) = 0xBEDEFED0; 
        result = *(volatile uint32_t*) (0x68000000 + 0x100);
        Thread::sleep(500);    

arch_system_halt@0x08034eb0 (f:\work\mfm-1054031\zephyr\kernel\fatal.c:30)
k_sys_fatal_error_handler@0x0801a18e (f:\work\mfm-1054031\zephyr\kernel\fatal.c:44)
z_fatal_error@0x0801a252 (f:\work\mfm-1054031\zephyr\kernel\fatal.c:119)
z_arm_fatal_error@0x0800b52a (f:\work\mfm-1054031\zephyr\arch\arm\core\fatal.c:86)
z_arm_fault@0x0800ba34 (f:\work\mfm-1054031\zephyr\arch\arm\core\cortex_m\fault.c:1080)
z_arm_usage_fault@0x0800bb1c (f:\work\mfm-1054031\zephyr\arch\arm\core\cortex_m\fault_s.S:102)
@0xfffffffd (Unknown Source:0)
z_tick_sleep@0x0801b5f8 (f:\work\mfm-1054031\zephyr\kernel\sched.c:1089)
z_impl_k_sleep@0x0803559c (f:\work\mfm-1054031\zephyr\kernel\sched.c:1130)
main@0x08008ce2 (f:\work\mfm-1054031\src\hardware\main.cpp:115)

I am really not sure how to debug it or what is the cause for the fault, I dont have UART connected to my board.
Is there anything in my configuration that is not correct? What can I do to find the cause of the fault?

[mathiasee]

STM32H7x3I-EVAL boards have both interfaces, but these boards are not yet implemented in zephyr.

[GeorgeCGV]

@mathiasee I haven't tested it, but in theory, it should work.

Is your goal to configure the SRAM NSBank FMC_NORSRAM_BANK3 (based on present fmc_ne3_pg10 in pinctrl)?

Considering that memc_stm32_nor_psram.c does .NSBank = DT_REG_ADDR(node_id), the

bank@2 {
        reg = <0x2>;

should be

bank@4 {
        reg = <0x4>;

to get #define FMC_NORSRAM_BANK3 (0x00000004U).

The SDRAM bank seems to be FMC_SDRAM_BANK2 (as reg is 1), no conflict with pinctrl here, which has fmc_sdcke1 and fmc_sdne1.