diff --git a/boards/weact/bluepillplus_ch32v203/Kconfig.bluepillplus_ch32v203 b/boards/weact/bluepillplus_ch32v203/Kconfig.bluepillplus_ch32v203 new file mode 100644 index 000000000000..66780c65f0a8 --- /dev/null +++ b/boards/weact/bluepillplus_ch32v203/Kconfig.bluepillplus_ch32v203 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLUEPILLPLUS_CH32V203 + select SOC_CH32V203 diff --git a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203-pinctrl.dtsi b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203-pinctrl.dtsi new file mode 100644 index 000000000000..f30b18d1fc16 --- /dev/null +++ b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203-pinctrl.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart3_default: usart3_default { + group1 { + pinmux = ; + output-high; + drive-push-pull; + slew-rate = "max-speed-10mhz"; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; +}; diff --git a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.dts b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.dts new file mode 100644 index 000000000000..217896b541a8 --- /dev/null +++ b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.dts @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include "bluepillplus_ch32v203-pinctrl.dtsi" + +/ { + model = "bluepillplus_ch32v203"; + compatible = "wch,ch32v203"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &usart3; + zephyr,shell-uart = &usart3; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + blue_led: led0 { + gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + mode: sw0 { + gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &blue_led; + sw0 = &mode; + }; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&usart3 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&usart3_default>; + pinctrl-names = "default"; +}; diff --git a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.yaml b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.yaml new file mode 100644 index 000000000000..ce44b241c472 --- /dev/null +++ b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203.yaml @@ -0,0 +1,11 @@ +identifier: bluepillplus_ch32v203 +name: WeActStudio Blue Pill Plus CH32V203 +type: mcu +arch: riscv +toolchain: + - cross-compile + - zephyr +ram: 20 +flash: 64 +supported: + - gpio diff --git a/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203_defconfig b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203_defconfig new file mode 100644 index 000000000000..f635cc36f4ce --- /dev/null +++ b/boards/weact/bluepillplus_ch32v203/bluepillplus_ch32v203_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025 MASSDRIVER EI +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/weact/bluepillplus_ch32v203/board.cmake b/boards/weact/bluepillplus_ch32v203/board.cmake new file mode 100644 index 000000000000..e8573f4798c8 --- /dev/null +++ b/boards/weact/bluepillplus_ch32v203/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(minichlink) +include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake) + +board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/weact/bluepillplus_ch32v203/board.yml b/boards/weact/bluepillplus_ch32v203/board.yml new file mode 100644 index 000000000000..d9c356361f29 --- /dev/null +++ b/boards/weact/bluepillplus_ch32v203/board.yml @@ -0,0 +1,6 @@ +board: + name: bluepillplus_ch32v203 + full_name: Blue Pill Plus CH32V203 + vendor: weact + socs: + - name: ch32v203 diff --git a/boards/weact/bluepillplus_ch32v203/doc/img/bluepillplus_ch32v203.webp b/boards/weact/bluepillplus_ch32v203/doc/img/bluepillplus_ch32v203.webp new file mode 100644 index 000000000000..726d6eeeba3c Binary files /dev/null and b/boards/weact/bluepillplus_ch32v203/doc/img/bluepillplus_ch32v203.webp differ diff --git a/boards/weact/bluepillplus_ch32v203/doc/index.rst b/boards/weact/bluepillplus_ch32v203/doc/index.rst new file mode 100644 index 000000000000..2105789bac06 --- /dev/null +++ b/boards/weact/bluepillplus_ch32v203/doc/index.rst @@ -0,0 +1,85 @@ +.. zephyr:board:: bluepillplus_ch32v203 + +Overview +******** + +The `WeActStudio`_ Blue Pill Plus CH32V203 hardware provides support for QingKe 32-bit RISC-V4B +processor and the following devices: + +* CLOCK +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` + +The board is equipped with two LEDs and two Buttons. +The `WCH webpage on CH32V203`_ contains the processor's manuals. +The `WeActStudio webpage on BPP`_ contains the Blue Pill's schematic. + +Hardware +******** + +The QingKe 32-bit RISC-V4B processor of the Blue Pill Plus CH32V203 is clocked by an external +8 MHz crystal or the internal 8 MHz oscillator and runs up to 144 MHz. +The CH32V203 SoC Features 2-4 USART, 4 GPIO ports, 1-2 SPI, 0-2 I2C, 9-16 ADC, RTC, +CAN, USB Device, USB Host, OPA, and several timers. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +LED +--- + +* LED0 = Blue User LED + +Button +------ + +* SW0 = User Button + +Programming and Debugging +************************* + +Applications for the ``bluepillplus_ch32v203`` board can be built and flashed +in the usual way (see :ref:`build_an_application` and :ref:`application_run` +for more details); however, an external programmer is required since the board +does not have any built-in debug support. + +The following pins of the external programmer must be connected to the +following pins on the PCB: + +* VCC = VCC +* GND = GND +* SWIO = PA13 +* SWCLK = PA14 + +Flashing +======== + +You can use ``minichlink`` to flash the board. Once ``minichlink`` has been set +up, build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: bluepillplus_ch32v203 + :goals: build flash + +Debugging +========= + +This board can be debugged via OpenOCD or ``minichlink``. + +References +********** + +.. target-notes:: + +.. _WeActStudio: https://github.com/WeActStudio +.. _WCH webpage on CH32V203: https://www.wch-ic.com/products/CH32V203.html +.. _WeActStudio webpage on BPP: https://github.com/WeActStudio/WeActStudio.BluePill-Plus-CH32 diff --git a/boards/weact/bluepillplus_ch32v203/support/openocd.cfg b/boards/weact/bluepillplus_ch32v203/support/openocd.cfg new file mode 100644 index 000000000000..65a43f18a169 --- /dev/null +++ b/boards/weact/bluepillplus_ch32v203/support/openocd.cfg @@ -0,0 +1,20 @@ +# Tested with WCH openOCD liberated fork (https://github.com/jnk0le/openocd-wch) +# Copyright (c) 2024 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 +adapter driver wlinke +adapter speed 6000 +transport select sdi + +wlink_set_address 0x00000000 +set _CHIPNAME wch_riscv +sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 + +echo "Ready for Remote Connections" diff --git a/drivers/timer/Kconfig.wch_ch32v00x b/drivers/timer/Kconfig.wch_ch32v00x index 744d54c2c0d4..244c38219cf1 100644 --- a/drivers/timer/Kconfig.wch_ch32v00x +++ b/drivers/timer/Kconfig.wch_ch32v00x @@ -3,6 +3,6 @@ config CH32V00X_SYSTICK bool "CH32V00X systick timer" - depends on SOC_CH32V003 || SOC_SERIES_QINGKE_V4C + depends on SOC_CH32V003 || SOC_SERIES_QINGKE_V4C || SOC_SERIES_QINGKE_V4B default y depends on DT_HAS_WCH_SYSTICK_ENABLED diff --git a/dts/bindings/cpu/wch,qingke-v4b.yml b/dts/bindings/cpu/wch,qingke-v4b.yml new file mode 100644 index 000000000000..47844a0b1ac6 --- /dev/null +++ b/dts/bindings/cpu/wch,qingke-v4b.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +description: WCH QingKe V4B RISC-V MCU + +compatible: "wch,qingke-v4b" + +include: riscv,cpus.yaml diff --git a/dts/riscv/wch/ch32v203/ch32v203.dtsi b/dts/riscv/wch/ch32v203/ch32v203.dtsi new file mode 100644 index 000000000000..bcba3e26e6d2 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203.dtsi @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +/ { + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "wch,ch32v00x-hse-clock"; + clock-frequency = ; + status = "disabled"; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "wch,ch32v00x-hsi-clock"; + clock-frequency = ; + status = "disabled"; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + status = "disabled"; + }; + + pll: pll { + #clock-cells = <0>; + compatible = "wch,ch32v20x_30x-pll-clock"; + mul = <15>; + status = "disabled"; + }; + }; + + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + flash: flash-controller@40022000 { + compatible = "wch,ch32v20x_30x-flash-controller"; + reg = <0x40022000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + reg = <0x08000000 DT_SIZE_K(224)>; + }; + }; + + pwr: pwr@40007000 { + compatible = "wch,pwr"; + reg = <0x40007000 16>; + }; + + pinctrl: pin-controller@40010000 { + compatible = "wch,20x_30x-afio"; + reg = <0x40010000 16>; + #address-cells = <1>; + #size-cells = <1>; + + gpioa: gpio@40010800 { + compatible = "wch,gpio"; + reg = <0x40010800 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>; + }; + + gpiob: gpio@40010C00 { + compatible = "wch,gpio"; + reg = <0x40010C00 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>; + }; + + gpioc: gpio@40011000 { + compatible = "wch,gpio"; + reg = <0x40011000 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>; + }; + + gpiod: gpio@40011400 { + compatible = "wch,gpio"; + reg = <0x40011400 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>; + }; + }; + + usart1: uart@40013800 { + compatible = "wch,usart"; + reg = <0x40013800 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>; + interrupt-parent = <&pfic>; + interrupts = <53>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "wch,usart"; + reg = <0x40004400 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>; + interrupt-parent = <&pfic>; + interrupts = <54>; + status = "disabled"; + }; + + rcc: rcc@40021000 { + compatible = "wch,rcc"; + reg = <0x40021000 16>; + #clock-cells = <1>; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203c6t.dtsi b/dts/riscv/wch/ch32v203/ch32v203c6t.dtsi new file mode 100644 index 000000000000..a29044c64d8e --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203c6t.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioc { + gpio-reserved-ranges = <0 13>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(10)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203c6u.dtsi b/dts/riscv/wch/ch32v203/ch32v203c6u.dtsi new file mode 100644 index 000000000000..894e0dcc6627 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203c6u.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/riscv/wch/ch32v203/ch32v203c8t.dtsi b/dts/riscv/wch/ch32v203/ch32v203c8t.dtsi new file mode 100644 index 000000000000..b0e3e57c5723 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203c8t.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioc { + gpio-reserved-ranges = <0 13>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(20)>; +}; + +/ { + soc { + usart3: uart@40004800 { + compatible = "wch,usart"; + reg = <0x40004800 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>; + interrupt-parent = <&pfic>; + interrupts = <55>; + status = "disabled"; + }; + + usart4: uart@40004c00 { + compatible = "wch,usart"; + reg = <0x40004C00 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>; + interrupt-parent = <&pfic>; + interrupts = <68>; + status = "disabled"; + }; + }; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203c8u.dtsi b/dts/riscv/wch/ch32v203/ch32v203c8u.dtsi new file mode 100644 index 000000000000..5ba2af0914ac --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203c8u.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/riscv/wch/ch32v203/ch32v203f6p.dtsi b/dts/riscv/wch/ch32v203/ch32v203f6p.dtsi new file mode 100644 index 000000000000..a3f58281451d --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203f6p.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <8 11>, <15 16>; +}; + +&gpiob { + gpio-reserved-ranges = <0 1>, <2 8>, <9 16>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(10)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203f8p.dtsi b/dts/riscv/wch/ch32v203/ch32v203f8p.dtsi new file mode 100644 index 000000000000..cbb1ea6d71e4 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203f8p.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <11 13>, <15 16>; +}; + +&gpiob { + gpio-reserved-ranges = <1 6>, <8 13>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <0 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(20)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203f8u.dtsi b/dts/riscv/wch/ch32v203/ch32v203f8u.dtsi new file mode 100644 index 000000000000..ae506ab14ce5 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203f8u.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <11 13>, <15 16>; +}; + +&gpiob { + gpio-reserved-ranges = <2 10>, <12 14>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <0 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(20)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203g6u.dtsi b/dts/riscv/wch/ch32v203/ch32v203g6u.dtsi new file mode 100644 index 000000000000..82aa5f50b6ae --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203g6u.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <8 9>; +}; + +&gpiob { + gpio-reserved-ranges = <2 3>, <10 16>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(10)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203g8r.dtsi b/dts/riscv/wch/ch32v203/ch32v203g8r.dtsi new file mode 100644 index 000000000000..750a2a50da47 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203g8r.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <15 16>; +}; + +&gpiob { + gpio-reserved-ranges = <2 6>, <9 10>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <0 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(20)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203k6t.dtsi b/dts/riscv/wch/ch32v203/ch32v203k6t.dtsi new file mode 100644 index 000000000000..9dc0653c508a --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203k6t.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiob { + gpio-reserved-ranges = <9 16>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(10)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203k8t.dtsi b/dts/riscv/wch/ch32v203/ch32v203k8t.dtsi new file mode 100644 index 000000000000..f4d5780f6470 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203k8t.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiob { + gpio-reserved-ranges = <9 16>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(20)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203rbt.dtsi b/dts/riscv/wch/ch32v203/ch32v203rbt.dtsi new file mode 100644 index 000000000000..465c5b1b88af --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203rbt.dtsi @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiod { + gpio-reserved-ranges = <3 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(64)>; +}; + +soc { + usart3: uart@40004800 { + compatible = "wch,usart"; + reg = <0x40004800 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>; + interrupt-parent = <&pfic>; + interrupts = <55>; + status = "disabled"; + }; + + usart4: uart@40004c00 { + compatible = "wch,usart"; + reg = <0x40004C00 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>; + interrupt-parent = <&pfic>; + interrupts = <68>; + status = "disabled"; + }; +}; diff --git a/dts/riscv/wch/qingke-v4b.dtsi b/dts/riscv/wch/qingke-v4b.dtsi new file mode 100644 index 000000000000..0fb20ef7e25f --- /dev/null +++ b/dts/riscv/wch/qingke-v4b.dtsi @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "wch,qingke-v4b"; + reg = <0>; + riscv,isa = "rv32imac_zicsr_zifencei"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + pfic: interrupt-controller@e000e000 { + compatible = "wch,pfic"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xe000e000 0x10>; + status = "okay"; + }; + + systick: systimer@e000f000 { + compatible = "wch,systick"; + reg = <0xe000f000 0x10>; + status = "okay"; + interrupt-parent = <&pfic>; + interrupts = <12>; + }; + }; +}; diff --git a/modules/hal_wch/CMakeLists.txt b/modules/hal_wch/CMakeLists.txt index ad16ad6c62b8..01797436ba8c 100644 --- a/modules/hal_wch/CMakeLists.txt +++ b/modules/hal_wch/CMakeLists.txt @@ -1,3 +1,3 @@ -if(CONFIG_SOC_CH32V003 OR CONFIG_SOC_SERIES_QINGKE_V4C) +if(CONFIG_SOC_FAMILY_CH32V) zephyr_include_directories(${ZEPHYR_HAL_WCH_MODULE_DIR}/ch32v003fun .) endif() diff --git a/modules/hal_wch/ch32fun.h b/modules/hal_wch/ch32fun.h index 555bcd3e75b7..3d37b32d8530 100644 --- a/modules/hal_wch/ch32fun.h +++ b/modules/hal_wch/ch32fun.h @@ -12,7 +12,7 @@ #include #endif -#if defined(CONFIG_SOC_SERIES_QINGKE_V4C) +#if defined(CONFIG_SOC_SERIES_QINGKE_V4C) || defined(CONFIG_SOC_SERIES_QINGKE_V4B) #define CH32V20x 1 #include #endif diff --git a/soc/wch/ch32v/qingke_v4b/CMakeLists.txt b/soc/wch/ch32v/qingke_v4b/CMakeLists.txt new file mode 100644 index 000000000000..a7e9de643d69 --- /dev/null +++ b/soc/wch/ch32v/qingke_v4b/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Michael Hope +# Copyright (c) 2024 Jianxiong Gu +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc_irq.S + vector.S +) + +zephyr_include_directories(.) diff --git a/soc/wch/ch32v/qingke_v4b/Kconfig b/soc/wch/ch32v/qingke_v4b/Kconfig new file mode 100644 index 000000000000..1706900e7cd9 --- /dev/null +++ b/soc/wch/ch32v/qingke_v4b/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_QINGKE_V4B + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/wch/ch32v/qingke_v4b/Kconfig.defconfig b/soc/wch/ch32v/qingke_v4b/Kconfig.defconfig new file mode 100644 index 000000000000..935e4357676e --- /dev/null +++ b/soc/wch/ch32v/qingke_v4b/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_QINGKE_V4B + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config MAIN_STACK_SIZE + default 512 + +config IDLE_STACK_SIZE + default 256 + +config ISR_STACK_SIZE + default 256 + +config CLOCK_CONTROL + default y + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_QINGKE_V4B diff --git a/soc/wch/ch32v/qingke_v4b/Kconfig.defconfig.ch32v203 b/soc/wch/ch32v/qingke_v4b/Kconfig.defconfig.ch32v203 new file mode 100644 index 000000000000..dd4ca4aa679d --- /dev/null +++ b/soc/wch/ch32v/qingke_v4b/Kconfig.defconfig.ch32v203 @@ -0,0 +1,12 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +if SOC_CH32V203 + +config VECTOR_TABLE_SIZE + default 103 + +config NUM_IRQS + default 128 + +endif # SOC_CH32V203 diff --git a/soc/wch/ch32v/qingke_v4b/Kconfig.soc b/soc/wch/ch32v/qingke_v4b/Kconfig.soc new file mode 100644 index 000000000000..c4bf31f80b74 --- /dev/null +++ b/soc/wch/ch32v/qingke_v4b/Kconfig.soc @@ -0,0 +1,11 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_QINGKE_V4B + bool + select SOC_FAMILY_CH32V + +config SOC_SERIES + default "qingke_v4b" if SOC_SERIES_QINGKE_V4B + +rsource "Kconfig.soc.*" diff --git a/soc/wch/ch32v/qingke_v4b/Kconfig.soc.ch32v203 b/soc/wch/ch32v/qingke_v4b/Kconfig.soc.ch32v203 new file mode 100644 index 000000000000..82538cde99f4 --- /dev/null +++ b/soc/wch/ch32v/qingke_v4b/Kconfig.soc.ch32v203 @@ -0,0 +1,9 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +config SOC_CH32V203 + bool + select SOC_SERIES_QINGKE_V4B + +config SOC + default "ch32v203" if SOC_CH32V203 diff --git a/soc/wch/ch32v/qingke_v4b/pinctrl_soc.h b/soc/wch/ch32v/qingke_v4b/pinctrl_soc.h new file mode 100644 index 000000000000..d11568a61247 --- /dev/null +++ b/soc/wch/ch32v/qingke_v4b/pinctrl_soc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __PINCTRL_SOC_H__ +#define __PINCTRL_SOC_H__ + +/** + * @brief Type to hold a pin's pinctrl configuration. + */ +struct ch32v203_pinctrl_soc_pin { + uint32_t config: 22; + bool bias_pull_up: 1; + bool bias_pull_down: 1; + bool drive_open_drain: 1; + bool drive_push_pull: 1; + bool output_high: 1; + bool output_low: 1; + uint8_t slew_rate: 2; +}; + +typedef struct ch32v203_pinctrl_soc_pin pinctrl_soc_pin_t; + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + { \ + .config = DT_PROP_BY_IDX(node_id, prop, idx), \ + .bias_pull_up = DT_PROP(node_id, bias_pull_up), \ + .bias_pull_down = DT_PROP(node_id, bias_pull_down), \ + .drive_open_drain = DT_PROP(node_id, drive_open_drain), \ + .drive_push_pull = DT_PROP(node_id, drive_push_pull), \ + .output_high = DT_PROP(node_id, output_high), \ + .output_low = DT_PROP(node_id, output_low), \ + .slew_rate = DT_ENUM_IDX(node_id, slew_rate), \ + }, + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)} + +#endif diff --git a/soc/wch/ch32v/qingke_v4b/soc_irq.S b/soc/wch/ch32v/qingke_v4b/soc_irq.S new file mode 100644 index 000000000000..fcb0daea51d0 --- /dev/null +++ b/soc/wch/ch32v/qingke_v4b/soc_irq.S @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* Exports */ +GTEXT(__soc_is_irq) +GTEXT(__soc_handle_irq) + +SECTION_FUNC(exception.other, __soc_is_irq) + csrr a0, mcause + srli a0, a0, 31 + ret + +SECTION_FUNC(exception.other, __soc_handle_irq) + ret diff --git a/soc/wch/ch32v/qingke_v4b/vector.S b/soc/wch/ch32v/qingke_v4b/vector.S new file mode 100644 index 000000000000..97766e820fdd --- /dev/null +++ b/soc/wch/ch32v/qingke_v4b/vector.S @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifndef CONFIG_VECTOR_TABLE_SIZE +#error "VECTOR_TABLE_SIZE must be defined" +#endif + +/* Exports */ +GTEXT(__start) + +/* Imports */ +GTEXT(__initialize) + +SECTION_FUNC(vectors, ivt) + .option norvc + /* Jump to 0x08000008, into the main flash zone where j __start is */ + lui x5, 0x8000 + jr 0x8(x5) + j __start + .rept CONFIG_VECTOR_TABLE_SIZE + .word _isr_wrapper + .endr + +SECTION_FUNC(vectors, __start) + li a0, 0xf + csrw mtvec, a0 + j __initialize diff --git a/soc/wch/ch32v/soc.yml b/soc/wch/ch32v/soc.yml index a019651b5dc5..c04b85fed89c 100644 --- a/soc/wch/ch32v/soc.yml +++ b/soc/wch/ch32v/soc.yml @@ -10,3 +10,6 @@ family: - name: qingke-v4c socs: - name: ch32v208 + - name: qingke-v4b + socs: + - name: ch32v203