diff --git a/boards/adi/max32657evkit/Kconfig.defconfig b/boards/adi/max32657evkit/Kconfig.defconfig new file mode 100644 index 0000000000000..0309586a787ee --- /dev/null +++ b/boards/adi/max32657evkit/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAX32657EVKIT + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_MAX32657EVKIT diff --git a/boards/adi/max32657evkit/Kconfig.max32657evkit b/boards/adi/max32657evkit/Kconfig.max32657evkit new file mode 100644 index 0000000000000..7f1cae8fc8376 --- /dev/null +++ b/boards/adi/max32657evkit/Kconfig.max32657evkit @@ -0,0 +1,5 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32657EVKIT + select SOC_MAX32657 if BOARD_MAX32657EVKIT_MAX32657 diff --git a/boards/adi/max32657evkit/board.cmake b/boards/adi/max32657evkit/board.cmake new file mode 100644 index 0000000000000..09717336e5fda --- /dev/null +++ b/boards/adi/max32657evkit/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=MAX32657" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32657evkit/board.yml b/boards/adi/max32657evkit/board.yml new file mode 100644 index 0000000000000..48af69011b6b6 --- /dev/null +++ b/boards/adi/max32657evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32657evkit + vendor: adi + socs: + - name: max32657 diff --git a/boards/adi/max32657evkit/doc/img/max32657evkit.webp b/boards/adi/max32657evkit/doc/img/max32657evkit.webp new file mode 100644 index 0000000000000..dfdd54a34da23 Binary files /dev/null and b/boards/adi/max32657evkit/doc/img/max32657evkit.webp differ diff --git a/boards/adi/max32657evkit/doc/index.rst b/boards/adi/max32657evkit/doc/index.rst new file mode 100644 index 0000000000000..67694e070eb19 --- /dev/null +++ b/boards/adi/max32657evkit/doc/index.rst @@ -0,0 +1,369 @@ +.. zephyr:board:: max32657evkit + +Overview +******** + +The MAX32657 microcontroller (MCU) is an advanced system-on-chip (SoC) +featuring an Arm® Cortex®-M33 core with single-precision floating point unit (FPU) +with digital signal processing (DSP) instructions, large flash and SRAM memories, +and the latest generation Bluetooth® 5.4 Low Energy (LE) radio. +The nano-power modes increase battery life substantially. + +The MAX32657 is qualified to operate at a temperature range of -20°C to +85°C. +Bluetooth 5.4 LE radio supports Mesh, long-range (coded), and high-throughput modes. +A cryptographic toolbox (CTB) provides advanced root of trust security features, +including an Advanced Encryption Standard (AES) Engine, TRNG, and secure boot. +TrustZone is also included in the M33 Core. +Many high-speed interfaces are supported on the device, including multiple SPI, UART, +and I3C/I2C serial interfaces. +All interfaces support efficient DMA-driven transfers between peripheral and memory. + +The Zephyr port is running on the MAX32657 MCU. + +Hardware +******** + +- MAX32657 MCU: + + - Arm Cortex-M33 CPU with TrustZone® and FPU + - 1.2V to 1.6V Input Range for Integrated Boost DC-DC Converter + - 50MHz Low Power Oscillator + - External Crystal Support + + - 32MHz required for BLE + + - 1MB Internal Flash with ECC + - 256kB Internal SRAM + - 8kB Cache + - 32.768kHz RTC external crystal + + - Typical Electrical Characteristics + + - ACTIVE: 50μA/MHz Arm Cortex-M33 Running Coremark (50MHz) + + - Bluetooth 5.4 LE Radio + + - Rx Sensitivity: -96dBm; Tx Power: +4.5dBm + - 15mW Tx Power at 0dBm at 1.5Vin + - 14mW Rx Power at 1.5Vin + - Single-Ended Antenna Connection (50Ω) + - Supports 802.15.4, and LE Audio + - High-Throughput (2Mbps) Mode + - Long-Range (125kbps and 500kbps) Modes + + - Optimal Peripheral Mix Provides Platform Scalability + + - 2 DMA Controllers (Secure and non-Secure) + - One SPI Controller/Peripheral + - One I2C/I3C + - 1 Low-Power UART (LPUART) + - Six 32-Bit Low Power Timers with PWM + - 14 Configurable GPIO with Internal Pullup/Pulldown Resistors + + - Cryptographic Tool Box (CTB) for IP/Data Security + + - True Random Number Generator (TRNG) + - AES-128/192/256 + - Unique ID + + - Secure Boot ROM + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | VLDO SEL | | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Sets the LDO output used for system power according to the value of resistor R4. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | Sets the LDO output used for system power to 1.2V. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | Sets the LDO output used for system power to 1.5V. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Sets the LDO output used for system power to 1.6V. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | VIN SEL | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | VIN Powered from LDO. (USB Type-C connector is board's power source) | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 2-3 | | | VIN Powered from Battery | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | VIN EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the board's power source to system power by connecting VIN to VSYS_IN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power by disconnecting VIN from VSYS_IN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | VDD12 EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects system power to the MAX32657 by connecting VDD12 to VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power from the MAX32657 by disconnecting VDD12 from VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | VTREF EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects a reference voltage to the OBD circuit. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects a reference voltage from the OBD circuit. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | OBD VBUS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the OBD by connecting OBD_VBUS to VBUS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the OBD by disconnecting OBD_VBUS from VBUS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| J7 | VSYS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects system power to all peripherals by connecting VSYS to VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power to all peripherals by disconnecting VSYS from VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | ACC VS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the accelerometer by connecting its supply voltage pin VS to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the accelerometer by disconnecting its supply voltage pin VS from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | ACC VDD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the accelerometer by connecting its VDDIO pin to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the accelerometer by disconnecting its VDDIO pin from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | ACC I2C EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Accelerometer SDA Pin is connected to MAX32657 I2C0_SDA. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Accelerometer SDA Pin is disconnected from MAX32657 I2C0_SDA. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | ACC I2C EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Accelerometer SCL Pin is connected to MAX32657 I2C0_SCL. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Accelerometer SCL Pin is disconnected from MAX32657 I2C0_SCL. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | BYP MAG SW | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Bypass Magnetic Switch. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Enables magnetic switch. The output of the switch is controlled by the AFE pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | LOCK RSTN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | AFE Lock Pin is connected to MAX32657 RSTN pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | AFE Lock Pin is disconnected from MAX32657 RSTN pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | LATCH CTRL | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the AFE (LOCK) to the magnetic switch (OUTPUT LATCH CONTROL). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the AFE (WAKE) to the magnetic switch (OUTPUT LATCH CONTROL). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | AFE EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the AFE (VBAT) by connecting it to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the AFE (VBAT) by disconnecting it from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | AFE SPI EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | AFE CSB is connected to MAX32657 SPI0_CS0. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | AFE SDI is connected to MAX32657 SPI0_MOSI. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | AFE SCLK is connected to MAX32657 SPI0_SCK. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | AFE SDO is connected to MAX32657 SPI0_MISO. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | AFE INTB is connected to MAX32657 P0.7. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 11-12 | | | AFE GPIO2 is connected to MAX32657 P0.8. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open All | | | Disconnect SPI Interface from MAX32657. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | I2C PU EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enable SCL PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable SCL PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | I2C PU EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enable SDA PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable SDA PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | OBD SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | OBD SWDIO is connected to the MAX32657 SWDIO. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | OBD SWCLK is connected to the MAX32657 SWCLK. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | OBD JTAG TDO Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | OBD JTAG TDI Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 11-12 | | | OBD RSTN is connected to the MAX32657 RSTN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 13-14 | | | OBD JTAG TRST Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open All | | | Disable OBD SWD Connection from MAX32657. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | OBD VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | OBD VCOM TXD is connected VCOM EN RX Jumper. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | OBD VCOM RXD is connected VCOM EN TX Jumper. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | OBD VCOM CTS Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | OBD VCOM RTS Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable OBD VCOM connection from MAX32657. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects OBD VCOM RXD to the MAX32657 UART0A_TX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects OBD VCOM RXD from the MAX32657 UART0A_TX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects OBD VCOM TXD to the MAX32657 UART0A_RX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects OBD VCOM TXD from the MAX32657 UART0A_RX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | EXT SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects EXT SWD Connector Data Signals to the MAX32657 SWDIO pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects EXT SWD Connector Data Signals from the MAX32657 SWDIO pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | EXT SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects EXT SWD Connector Clock Signals to the MAX32657 SWDCLK pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects EXT SWD Connector Clock Signals from the MAX32657 SWDCLK pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + +Zephyr board options +******************** + +The MAX32657 microcontroller (MCU) is an advanced system-on-chip (SoC) +featuring an ARM Cortex-M33 architecture that provides Trustzone technology +which allow define secure and non-secure application. + +The BOARD options are summarized below: + ++-------------------------------+-------------------------------------------+ +| BOARD | Description | ++===============================+===========================================+ +| max32657evkit/max32657 | For building Trust Zone Disabled firmware | ++-------------------------------+-------------------------------------------+ + + +BOARD: max32657evkit/max32657 +============================= + +Build the zephyr app for ``max32657evkit/max32657`` board will generate secure firmware +for zephyr. In this configuration 960KB of flash is used to store the code and 64KB +is used for storage section. In this mode tf-m is off and secure mode flag is on +``:kconfig:option:CONFIG_TRUSTED_EXECUTION_SECURE=y`` and +``:kconfig:option:CONFIG_BUILD_WITH_TFM=n`` + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| slot0 | 0x1000000[960k] | Secure zephyr image | ++----------+------------------+---------------------------------+ +| storage | 0x10f0000[64k] | File system, persistent storage | ++----------+------------------+---------------------------------+ + +Here are the instructions to build zephyr with a secure configuration, +using :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: max32657evkit/max32657 + :goals: build + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32657evkit/max32657 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build v4.1.0 ***** + Hello World! max32657evkit/max32657 + + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32657evkit/max32657 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build v4.1.0 ***** + Hello World! max32657evkit/max32657 diff --git a/boards/adi/max32657evkit/max32657evkit_max32657.dts b/boards/adi/max32657evkit/max32657evkit_max32657.dts new file mode 100644 index 0000000000000..7cee4e1127711 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657.dts @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "max32657evkit_max32657_common.dtsi" + +/ { + chosen { + zephyr,sram = &secure_ram; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + secure_ram: partition@30000000 { + label = "secure-memory"; + reg = <0x30000000 DT_SIZE_K(256)>; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(960)>; + read-only; + }; + + storage_partition: partition@f0000 { + label = "storage"; + reg = <0xf0000 DT_SIZE_K(64)>; + }; + }; +}; + +&trng { + status = "okay"; +}; diff --git a/boards/adi/max32657evkit/max32657evkit_max32657.yaml b/boards/adi/max32657evkit/max32657evkit_max32657.yaml new file mode 100644 index 0000000000000..8290aa1fdd523 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657.yaml @@ -0,0 +1,14 @@ +identifier: max32657evkit/max32657 +name: max32657evkit-max32657 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - serial + - gpio + - trng +ram: 256 +flash: 960 diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi b/boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi new file mode 100644 index 0000000000000..5bc950bc16700 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32657EVKIT"; + compatible = "adi,max32657evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + pb1: pb1 { + gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + sw0 = &pb1; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_tx_p0_9 &uart0_rx_p0_5>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_defconfig b/boards/adi/max32657evkit/max32657evkit_max32657_defconfig new file mode 100644 index 0000000000000..25ef03ee5131b --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# It is secure fw, enable flags +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/common/openocd-adi-max32.boards.cmake b/boards/common/openocd-adi-max32.boards.cmake index c231f5ad1cf2b..c815a0db64f33 100644 --- a/boards/common/openocd-adi-max32.boards.cmake +++ b/boards/common/openocd-adi-max32.boards.cmake @@ -14,13 +14,15 @@ endif() # MAX32666 share the same target configuration file with MAX32665 if(CONFIG_SOC_MAX32666) set(MAX32_TARGET_CFG "max32665.cfg") +elseif(CONFIG_SOC_MAX32657) + set(MAX32_INTERFACE_CFG "jlink.cfg") endif() board_runner_args(openocd --cmd-pre-init "source [find interface/${MAX32_INTERFACE_CFG}]") board_runner_args(openocd --cmd-pre-init "source [find target/${MAX32_TARGET_CFG}]") board_runner_args(openocd "--target-handle=_CHIPNAME.cpu") -if(CONFIG_SOC_FAMILY_MAX32_M4) +if(CONFIG_SOC_FAMILY_MAX32_M4 OR CONFIG_SOC_FAMILY_MAX32_M33) board_runner_args(openocd --cmd-pre-init "allow_low_pwr_dbg") board_runner_args(openocd "--cmd-erase=max32xxx mass_erase 0") endif() diff --git a/dts/arm/adi/max32/max32657-pinctrl.dtsi b/dts/arm/adi/max32/max32657-pinctrl.dtsi new file mode 100644 index 0000000000000..6f74cf673ad08 --- /dev/null +++ b/dts/arm/adi/max32/max32657-pinctrl.dtsi @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /omit-if-no-ref/ i3c_scl_p0_0: i3c_scl_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ i3c_sda_p0_1: i3c_sda_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_mosi_p0_2: spi0_mosi_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_ss0_p0_3: spi0_ss0_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_miso_p0_4: spi0_miso_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_rx_p0_5: uart0_rx_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_sck_p0_6: spi0_sck_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_ss1_p0_7: spi0_ss1_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_ss2_p0_8: spi0_ss2_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_tx_p0_9: uart0_tx_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ sqwout_p0_13: sqwout_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0a_p0_0: tmr0a_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1a_p0_1: tmr1a_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3a_p0_2: tmr3a_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr4a_p0_3: tmr4a_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr5a_p0_4: tmr5a_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0b_p0_5: tmr0b_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr4b_p0_6: tmr4b_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr3b_p0_7: tmr3b_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ i3c_pur_p0_8: i3c_pur_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr1b_p0_9: tmr1b_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr2a_p0_10: tmr2a_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr5b_p0_11: tmr5b_p0_11 { + pinmux = ; + }; +}; diff --git a/dts/arm/adi/max32/max32657.dtsi b/dts/arm/adi/max32/max32657.dtsi new file mode 100644 index 0000000000000..0e38c346e9fed --- /dev/null +++ b/dts/arm/adi/max32/max32657.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + soc { + sram: sram@30000000 { + ranges = <0x0 0x30000000 0x40000>; + }; + + peripheral: peripheral@50000000 { + ranges = <0x0 0x50000000 0x10000000>; + + pinctrl: pin-controller@8000 { + ranges = <0x8000 0x50008000 0x1000>; + }; + + flc0: flash_controller@29000 { + compatible = "adi,max32-flash-controller"; + reg = <0x29000 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + flash0: flash@1000000 { + compatible = "soc-nv-flash"; + reg = <0x01000000 DT_SIZE_K(1024)>; + write-block-size = <16>; + erase-block-size = <8192>; + }; + }; + }; + }; +}; + +#include "max32657_common.dtsi" diff --git a/dts/arm/adi/max32/max32657_common.dtsi b/dts/arm/adi/max32/max32657_common.dtsi new file mode 100644 index 0000000000000..e419155bf23f4 --- /dev/null +++ b/dts/arm/adi/max32/max32657_common.dtsi @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + chosen { + zephyr,entropy = &trng; + zephyr,flash-controller = &flc0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-m33"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + clocks { + clk_ipo: clk_ipo { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + status = "disabled"; + }; + + clk_inro: clk_inro { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = < DT_FREQ_K(8) >; + status = "disabled"; + }; + + clk_ibro: clk_ibro { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = < 7372800 >; + status = "disabled"; + }; + + clk_ertco: clk_ertco { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = < 32768 >; + status = "disabled"; + }; + + clk_erfo: clk_erfo { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + status = "disabled"; + }; + }; +}; + +&sram { + #address-cells = <1>; + #size-cells = <1>; + + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0x0 DT_SIZE_K(32)>; + }; + + sram1: memory@8000 { + compatible = "mmio-sram"; + reg = <0x8000 DT_SIZE_K(32)>; + }; + + sram2: memory@10000 { + compatible = "mmio-sram"; + reg = <0x10000 DT_SIZE_K(64)>; + }; + + sram3: memory@20000 { + compatible = "mmio-sram"; + reg = <0x20000 DT_SIZE_K(64)>; + }; + + sram4: memory@30000 { + compatible = "mmio-sram"; + reg = <0x30000 DT_SIZE_K(64)>; + }; +}; + +&peripheral { + #address-cells = <1>; + #size-cells = <1>; + + gcr: clock-controller@0 { + reg = <0x0 0x400>; + compatible = "adi,max32-gcr"; + #clock-cells = <2>; + clocks = <&clk_ipo>; + sysclk-prescaler = <1>; + status = "okay"; + }; + + pinctrl: pin-controller@8000 { + compatible = "adi,max32-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8000 0x1000>; + + gpio0: gpio@8000 { + reg = <0x8000 0x1000>; + compatible = "adi,max32-gpio"; + gpio-controller; + #gpio-cells = <2>; + clocks = <&gcr ADI_MAX32_CLOCK_BUS0 0>; + interrupts = <14 0>; + status = "disabled"; + }; + }; + + uart0: serial@42000 { + compatible = "adi,max32-uart"; + reg = <0x42000 0x1000>; + clocks = <&gcr ADI_MAX32_CLOCK_BUS0 9>; + clock-source = ; + interrupts = <11 0>; + status = "disabled"; + }; + + trng: trng@4d000 { + compatible = "adi,max32-trng"; + reg = <0x4d000 0x1000>; + clocks = <&gcr ADI_MAX32_CLOCK_BUS1 2>; + status = "disabled"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/soc/adi/max32/Kconfig b/soc/adi/max32/Kconfig index 2bddfc6e556b9..63e2d1b4b3e78 100644 --- a/soc/adi/max32/Kconfig +++ b/soc/adi/max32/Kconfig @@ -9,6 +9,17 @@ config SOC_FAMILY_MAX32 select SOC_EARLY_INIT_HOOK select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE +config SOC_FAMILY_MAX32_M33 + select ARM + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CLOCK_CONTROL + select CPU_CORTEX_M33 + select ARM_TRUSTZONE_M + select CPU_HAS_ARM_SAU + select ARMV8_M_DSP + config SOC_FAMILY_MAX32_M4 select ARM select CPU_CORTEX_M4 diff --git a/soc/adi/max32/Kconfig.defconfig.max32657 b/soc/adi/max32/Kconfig.defconfig.max32657 new file mode 100644 index 0000000000000..84da5e22a18df --- /dev/null +++ b/soc/adi/max32/Kconfig.defconfig.max32657 @@ -0,0 +1,14 @@ +# Analog Devices MAX32657 MCU + +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MAX32657 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency) + +config NUM_IRQS + default 54 + +endif # SOC_MAX32657 diff --git a/soc/adi/max32/Kconfig.soc b/soc/adi/max32/Kconfig.soc index e0be0041b4b6c..e4b2347ca0218 100644 --- a/soc/adi/max32/Kconfig.soc +++ b/soc/adi/max32/Kconfig.soc @@ -6,6 +6,10 @@ config SOC_FAMILY_MAX32 bool +config SOC_FAMILY_MAX32_M33 + bool + select SOC_FAMILY_MAX32 + config SOC_FAMILY_MAX32_M4 bool select SOC_FAMILY_MAX32 @@ -25,6 +29,10 @@ config SOC_MAX32655_M4 select SOC_MAX32655 select SOC_FAMILY_MAX32_M4 +config SOC_MAX32657 + bool + select SOC_FAMILY_MAX32_M33 + config SOC_MAX32660 bool select SOC_FAMILY_MAX32_M4 @@ -88,6 +96,7 @@ config SOC_MAX78002_M4 config SOC default "max32650" if SOC_MAX32650 default "max32655" if SOC_MAX32655 + default "max32657" if SOC_MAX32657 default "max32660" if SOC_MAX32660 default "max32662" if SOC_MAX32662 default "max32666" if SOC_MAX32666 diff --git a/soc/adi/max32/soc.yml b/soc/adi/max32/soc.yml index 3bf7288d120df..1a4b7c2568d38 100644 --- a/soc/adi/max32/soc.yml +++ b/soc/adi/max32/soc.yml @@ -8,6 +8,7 @@ family: - name: max32655 cpuclusters: - name: m4 + - name: max32657 - name: max32660 - name: max32662 - name: max32666 diff --git a/tests/drivers/gpio/gpio_basic_api/boards/max32657evkit_max32657.overlay b/tests/drivers/gpio/gpio_basic_api/boards/max32657evkit_max32657.overlay new file mode 100644 index 0000000000000..12c94d3a4944f --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/max32657evkit_max32657.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio0 3 0>; + in-gpios = <&gpio0 12 0>; + }; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/max32657evkit_max32657_ns.overlay b/tests/drivers/gpio/gpio_basic_api/boards/max32657evkit_max32657_ns.overlay new file mode 100644 index 0000000000000..12c94d3a4944f --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/max32657evkit_max32657_ns.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio0 3 0>; + in-gpios = <&gpio0 12 0>; + }; +}; diff --git a/west.yml b/west.yml index b83e00c587e9e..a13b49765a906 100644 --- a/west.yml +++ b/west.yml @@ -142,7 +142,7 @@ manifest: groups: - fs - name: hal_adi - revision: 67b88309c327d207e87bb7af6e37c704cd9d5b9d + revision: 8f33130dc5fe33ce14eb1cf29364bfc39dc82020 path: modules/hal/adi groups: - hal