From 7b7a495325354291b10462cd40014eb32012c3c5 Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Mon, 20 Oct 2025 17:04:43 +0200 Subject: [PATCH 1/6] dts: arm: silabs: Add xg26 devicetree files Add .dtsi files for xg26 device families: * efm32pg26 * efr32bg26 * efr32mg26 * bgm26 * mgm26 Signed-off-by: Aksel Skauge Mellbye --- dts/arm/silabs/xg26/bgm26.dtsi | 14 + dts/arm/silabs/xg26/bgm260pb22vna.dtsi | 38 + dts/arm/silabs/xg26/bgm260pb32vna.dtsi | 34 + dts/arm/silabs/xg26/efm32pg26.dtsi | 7 + .../silabs/xg26/efm32pg26b101f512il136.dtsi | 23 + .../silabs/xg26/efm32pg26b101f512im68.dtsi | 23 + .../silabs/xg26/efm32pg26b301f1024il136.dtsi | 23 + .../silabs/xg26/efm32pg26b301f1024im68.dtsi | 23 + .../silabs/xg26/efm32pg26b301f2048il136.dtsi | 23 + .../silabs/xg26/efm32pg26b301f2048im68.dtsi | 23 + .../silabs/xg26/efm32pg26b500f3200il136.dtsi | 23 + .../silabs/xg26/efm32pg26b500f3200im48.dtsi | 23 + .../silabs/xg26/efm32pg26b500f3200im68.dtsi | 23 + .../silabs/xg26/efm32pg26b501f3200il136.dtsi | 23 + .../silabs/xg26/efm32pg26b501f3200im48.dtsi | 23 + .../silabs/xg26/efm32pg26b501f3200im68.dtsi | 23 + dts/arm/silabs/xg26/efr32bg26.dtsi | 14 + .../silabs/xg26/efr32bg26b311f1024il136.dtsi | 23 + .../silabs/xg26/efr32bg26b311f1024im68.dtsi | 23 + .../silabs/xg26/efr32bg26b311f2048il136.dtsi | 23 + .../silabs/xg26/efr32bg26b311f2048im48.dtsi | 23 + .../silabs/xg26/efr32bg26b311f2048im68.dtsi | 23 + .../silabs/xg26/efr32bg26b321f1024im68.dtsi | 23 + .../silabs/xg26/efr32bg26b321f2048im48.dtsi | 23 + .../silabs/xg26/efr32bg26b321f2048im68.dtsi | 23 + .../silabs/xg26/efr32bg26b410f3200im48.dtsi | 23 + .../silabs/xg26/efr32bg26b411f3200im48.dtsi | 23 + .../silabs/xg26/efr32bg26b420f3200im48.dtsi | 23 + .../silabs/xg26/efr32bg26b421f3200im48.dtsi | 23 + .../silabs/xg26/efr32bg26b510f3200il136.dtsi | 23 + .../silabs/xg26/efr32bg26b510f3200im48.dtsi | 23 + .../silabs/xg26/efr32bg26b510f3200im68.dtsi | 23 + .../silabs/xg26/efr32bg26b511f3200il136.dtsi | 23 + .../silabs/xg26/efr32bg26b511f3200im48.dtsi | 23 + .../silabs/xg26/efr32bg26b511f3200im68.dtsi | 23 + dts/arm/silabs/xg26/efr32mg26.dtsi | 14 + .../silabs/xg26/efr32mg26b211f2048im68.dtsi | 23 + .../silabs/xg26/efr32mg26b211f3200im48.dtsi | 23 + .../silabs/xg26/efr32mg26b221f2048im68.dtsi | 23 + .../silabs/xg26/efr32mg26b221f3200im48.dtsi | 23 + .../silabs/xg26/efr32mg26b311f3200il136.dtsi | 23 + .../silabs/xg26/efr32mg26b410f3200im48.dtsi | 23 + .../silabs/xg26/efr32mg26b410f3200im68.dtsi | 23 + .../silabs/xg26/efr32mg26b411f3200im48.dtsi | 23 + .../silabs/xg26/efr32mg26b411f3200im68.dtsi | 23 + .../silabs/xg26/efr32mg26b420f3200im48.dtsi | 23 + .../silabs/xg26/efr32mg26b420f3200im68.dtsi | 23 + .../silabs/xg26/efr32mg26b421f3200im48.dtsi | 23 + .../silabs/xg26/efr32mg26b421f3200im68.dtsi | 23 + .../silabs/xg26/efr32mg26b510f3200il136.dtsi | 23 + .../silabs/xg26/efr32mg26b510f3200im48.dtsi | 23 + .../silabs/xg26/efr32mg26b510f3200im68.dtsi | 23 + .../silabs/xg26/efr32mg26b511f3200il136.dtsi | 23 + .../silabs/xg26/efr32mg26b511f3200im48.dtsi | 23 + .../silabs/xg26/efr32mg26b511f3200im68.dtsi | 23 + .../silabs/xg26/efr32mg26b520f3200im48.dtsi | 23 + .../silabs/xg26/efr32mg26b520f3200im68.dtsi | 23 + .../silabs/xg26/efr32mg26b521f3200im48.dtsi | 23 + .../silabs/xg26/efr32mg26b521f3200im68.dtsi | 23 + dts/arm/silabs/xg26/efr32xg26.dtsi | 32 + dts/arm/silabs/xg26/mgm26.dtsi | 14 + dts/arm/silabs/xg26/mgm260pb22vna.dtsi | 38 + dts/arm/silabs/xg26/mgm260pb32vna.dtsi | 34 + dts/arm/silabs/xg26/mgm260pb32vnn.dtsi | 34 + dts/arm/silabs/xg26/mgm260pd22vna.dtsi | 38 + dts/arm/silabs/xg26/mgm260pd32vna.dtsi | 34 + dts/arm/silabs/xg26/mgm260pd32vnn.dtsi | 34 + dts/arm/silabs/xg26/xg26.dtsi | 823 ++++++++++++++++++ 68 files changed, 2421 insertions(+) create mode 100644 dts/arm/silabs/xg26/bgm26.dtsi create mode 100644 dts/arm/silabs/xg26/bgm260pb22vna.dtsi create mode 100644 dts/arm/silabs/xg26/bgm260pb32vna.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b101f512il136.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b101f512im68.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b301f1024il136.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b301f1024im68.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b301f2048il136.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b301f2048im68.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b500f3200il136.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b500f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b500f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b501f3200il136.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b501f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efm32pg26b501f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b311f1024il136.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b311f1024im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b311f2048il136.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b311f2048im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b311f2048im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b321f1024im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b321f2048im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b321f2048im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b410f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b411f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b420f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b421f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b510f3200il136.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b510f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b510f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b511f3200il136.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b511f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32bg26b511f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b211f2048im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b211f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b221f2048im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b221f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b311f3200il136.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b410f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b410f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b411f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b411f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b420f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b420f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b421f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b421f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b510f3200il136.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b510f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b510f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b511f3200il136.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b511f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b511f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b520f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b520f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b521f3200im48.dtsi create mode 100644 dts/arm/silabs/xg26/efr32mg26b521f3200im68.dtsi create mode 100644 dts/arm/silabs/xg26/efr32xg26.dtsi create mode 100644 dts/arm/silabs/xg26/mgm26.dtsi create mode 100644 dts/arm/silabs/xg26/mgm260pb22vna.dtsi create mode 100644 dts/arm/silabs/xg26/mgm260pb32vna.dtsi create mode 100644 dts/arm/silabs/xg26/mgm260pb32vnn.dtsi create mode 100644 dts/arm/silabs/xg26/mgm260pd22vna.dtsi create mode 100644 dts/arm/silabs/xg26/mgm260pd32vna.dtsi create mode 100644 dts/arm/silabs/xg26/mgm260pd32vnn.dtsi create mode 100644 dts/arm/silabs/xg26/xg26.dtsi diff --git a/dts/arm/silabs/xg26/bgm26.dtsi b/dts/arm/silabs/xg26/bgm26.dtsi new file mode 100644 index 0000000000000..afa97cff141d2 --- /dev/null +++ b/dts/arm/silabs/xg26/bgm26.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&radio { + bt_hci_silabs: bt_hci_silabs { + compatible = "silabs,bt-hci-efr32"; + status = "disabled"; + }; +}; diff --git a/dts/arm/silabs/xg26/bgm260pb22vna.dtsi b/dts/arm/silabs/xg26/bgm260pb22vna.dtsi new file mode 100644 index 0000000000000..c0fc29b014dcf --- /dev/null +++ b/dts/arm/silabs/xg26/bgm260pb22vna.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,bgm260pb22vna", "silabs,bgm26", "silabs,xg26", "silabs,efr32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&hfxo { + clock-frequency = ; + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfrco { + precision-mode; +}; + +&radio { + pa-voltage-mv = <1800>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/bgm260pb32vna.dtsi b/dts/arm/silabs/xg26/bgm260pb32vna.dtsi new file mode 100644 index 0000000000000..4b8322becf367 --- /dev/null +++ b/dts/arm/silabs/xg26/bgm260pb32vna.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,bgm260pb32vna", "silabs,bgm26", "silabs,xg26", "silabs,efr32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&hfxo { + clock-frequency = ; + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfrco { + precision-mode; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26.dtsi b/dts/arm/silabs/xg26/efm32pg26.dtsi new file mode 100644 index 0000000000000..bdca838ed9b84 --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/silabs/xg26/efm32pg26b101f512il136.dtsi b/dts/arm/silabs/xg26/efm32pg26b101f512il136.dtsi new file mode 100644 index 0000000000000..5c190474dfc74 --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b101f512il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b101f512il136", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(128)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b101f512im68.dtsi b/dts/arm/silabs/xg26/efm32pg26b101f512im68.dtsi new file mode 100644 index 0000000000000..a7607f734b05c --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b101f512im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b101f512im68", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(128)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b301f1024il136.dtsi b/dts/arm/silabs/xg26/efm32pg26b301f1024il136.dtsi new file mode 100644 index 0000000000000..b6ed8902e36ea --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b301f1024il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b301f1024il136", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b301f1024im68.dtsi b/dts/arm/silabs/xg26/efm32pg26b301f1024im68.dtsi new file mode 100644 index 0000000000000..1e2d93240fb3f --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b301f1024im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b301f1024im68", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b301f2048il136.dtsi b/dts/arm/silabs/xg26/efm32pg26b301f2048il136.dtsi new file mode 100644 index 0000000000000..5e560d8b666df --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b301f2048il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b301f2048il136", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(2048)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b301f2048im68.dtsi b/dts/arm/silabs/xg26/efm32pg26b301f2048im68.dtsi new file mode 100644 index 0000000000000..27ea31a4251ce --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b301f2048im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b301f2048im68", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(2048)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b500f3200il136.dtsi b/dts/arm/silabs/xg26/efm32pg26b500f3200il136.dtsi new file mode 100644 index 0000000000000..e3698a4dd1293 --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b500f3200il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b500f3200il136", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b500f3200im48.dtsi b/dts/arm/silabs/xg26/efm32pg26b500f3200im48.dtsi new file mode 100644 index 0000000000000..5f3edb1773710 --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b500f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b500f3200im48", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b500f3200im68.dtsi b/dts/arm/silabs/xg26/efm32pg26b500f3200im68.dtsi new file mode 100644 index 0000000000000..d0485829b8141 --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b500f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b500f3200im68", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b501f3200il136.dtsi b/dts/arm/silabs/xg26/efm32pg26b501f3200il136.dtsi new file mode 100644 index 0000000000000..b5a8d595277b5 --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b501f3200il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b501f3200il136", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b501f3200im48.dtsi b/dts/arm/silabs/xg26/efm32pg26b501f3200im48.dtsi new file mode 100644 index 0000000000000..ae7c8506a3469 --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b501f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b501f3200im48", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efm32pg26b501f3200im68.dtsi b/dts/arm/silabs/xg26/efm32pg26b501f3200im68.dtsi new file mode 100644 index 0000000000000..2eba35b203c29 --- /dev/null +++ b/dts/arm/silabs/xg26/efm32pg26b501f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg26b501f3200im68", "silabs,efm32pg26", "silabs,xg26", + "silabs,efm32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26.dtsi b/dts/arm/silabs/xg26/efr32bg26.dtsi new file mode 100644 index 0000000000000..afa97cff141d2 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&radio { + bt_hci_silabs: bt_hci_silabs { + compatible = "silabs,bt-hci-efr32"; + status = "disabled"; + }; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b311f1024il136.dtsi b/dts/arm/silabs/xg26/efr32bg26b311f1024il136.dtsi new file mode 100644 index 0000000000000..4cb4b9205fb9e --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b311f1024il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b311f1024il136", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b311f1024im68.dtsi b/dts/arm/silabs/xg26/efr32bg26b311f1024im68.dtsi new file mode 100644 index 0000000000000..0a97bd9ffd27a --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b311f1024im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b311f1024im68", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b311f2048il136.dtsi b/dts/arm/silabs/xg26/efr32bg26b311f2048il136.dtsi new file mode 100644 index 0000000000000..b152e7a38de67 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b311f2048il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b311f2048il136", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(2048)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b311f2048im48.dtsi b/dts/arm/silabs/xg26/efr32bg26b311f2048im48.dtsi new file mode 100644 index 0000000000000..cd5f7c317bf85 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b311f2048im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b311f2048im48", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(2048)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b311f2048im68.dtsi b/dts/arm/silabs/xg26/efr32bg26b311f2048im68.dtsi new file mode 100644 index 0000000000000..b30192de316a1 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b311f2048im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b311f2048im68", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(2048)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b321f1024im68.dtsi b/dts/arm/silabs/xg26/efr32bg26b321f1024im68.dtsi new file mode 100644 index 0000000000000..5cf081ea64817 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b321f1024im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b321f1024im68", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b321f2048im48.dtsi b/dts/arm/silabs/xg26/efr32bg26b321f2048im48.dtsi new file mode 100644 index 0000000000000..3fa73a6bc472a --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b321f2048im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b321f2048im48", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(2048)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b321f2048im68.dtsi b/dts/arm/silabs/xg26/efr32bg26b321f2048im68.dtsi new file mode 100644 index 0000000000000..7b1b1ae9c8e72 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b321f2048im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b321f2048im68", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(2048)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b410f3200im48.dtsi b/dts/arm/silabs/xg26/efr32bg26b410f3200im48.dtsi new file mode 100644 index 0000000000000..ef20c9c53fa1b --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b410f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b410f3200im48", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b411f3200im48.dtsi b/dts/arm/silabs/xg26/efr32bg26b411f3200im48.dtsi new file mode 100644 index 0000000000000..634fc1331ff49 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b411f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b411f3200im48", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b420f3200im48.dtsi b/dts/arm/silabs/xg26/efr32bg26b420f3200im48.dtsi new file mode 100644 index 0000000000000..fe032bce23168 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b420f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b420f3200im48", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b421f3200im48.dtsi b/dts/arm/silabs/xg26/efr32bg26b421f3200im48.dtsi new file mode 100644 index 0000000000000..dac273bfa6972 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b421f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b421f3200im48", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b510f3200il136.dtsi b/dts/arm/silabs/xg26/efr32bg26b510f3200il136.dtsi new file mode 100644 index 0000000000000..eb34a4577c182 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b510f3200il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b510f3200il136", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b510f3200im48.dtsi b/dts/arm/silabs/xg26/efr32bg26b510f3200im48.dtsi new file mode 100644 index 0000000000000..bba3d5ac3498e --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b510f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b510f3200im48", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b510f3200im68.dtsi b/dts/arm/silabs/xg26/efr32bg26b510f3200im68.dtsi new file mode 100644 index 0000000000000..b481ee2adf9d6 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b510f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b510f3200im68", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b511f3200il136.dtsi b/dts/arm/silabs/xg26/efr32bg26b511f3200il136.dtsi new file mode 100644 index 0000000000000..ad43388419d05 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b511f3200il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b511f3200il136", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b511f3200im48.dtsi b/dts/arm/silabs/xg26/efr32bg26b511f3200im48.dtsi new file mode 100644 index 0000000000000..b0b6448b1b414 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b511f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b511f3200im48", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32bg26b511f3200im68.dtsi b/dts/arm/silabs/xg26/efr32bg26b511f3200im68.dtsi new file mode 100644 index 0000000000000..1a9819fae5304 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32bg26b511f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg26b511f3200im68", "silabs,efr32bg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26.dtsi b/dts/arm/silabs/xg26/efr32mg26.dtsi new file mode 100644 index 0000000000000..afa97cff141d2 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&radio { + bt_hci_silabs: bt_hci_silabs { + compatible = "silabs,bt-hci-efr32"; + status = "disabled"; + }; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b211f2048im68.dtsi b/dts/arm/silabs/xg26/efr32mg26b211f2048im68.dtsi new file mode 100644 index 0000000000000..dbce9daa1c39c --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b211f2048im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b211f2048im68", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(2048)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b211f3200im48.dtsi b/dts/arm/silabs/xg26/efr32mg26b211f3200im48.dtsi new file mode 100644 index 0000000000000..6b06c2815373d --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b211f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b211f3200im48", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b221f2048im68.dtsi b/dts/arm/silabs/xg26/efr32mg26b221f2048im68.dtsi new file mode 100644 index 0000000000000..3951018b3f202 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b221f2048im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b221f2048im68", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(2048)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b221f3200im48.dtsi b/dts/arm/silabs/xg26/efr32mg26b221f3200im48.dtsi new file mode 100644 index 0000000000000..44a49fbb8bc5d --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b221f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b221f3200im48", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b311f3200il136.dtsi b/dts/arm/silabs/xg26/efr32mg26b311f3200il136.dtsi new file mode 100644 index 0000000000000..cb1afc6b9912a --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b311f3200il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b311f3200il136", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b410f3200im48.dtsi b/dts/arm/silabs/xg26/efr32mg26b410f3200im48.dtsi new file mode 100644 index 0000000000000..e8d4d26e832da --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b410f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b410f3200im48", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b410f3200im68.dtsi b/dts/arm/silabs/xg26/efr32mg26b410f3200im68.dtsi new file mode 100644 index 0000000000000..8b6170e158148 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b410f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b410f3200im68", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b411f3200im48.dtsi b/dts/arm/silabs/xg26/efr32mg26b411f3200im48.dtsi new file mode 100644 index 0000000000000..b1a7bd72ba4cd --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b411f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b411f3200im48", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b411f3200im68.dtsi b/dts/arm/silabs/xg26/efr32mg26b411f3200im68.dtsi new file mode 100644 index 0000000000000..57fd5e0da66ee --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b411f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b411f3200im68", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b420f3200im48.dtsi b/dts/arm/silabs/xg26/efr32mg26b420f3200im48.dtsi new file mode 100644 index 0000000000000..7c07a1e7dc571 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b420f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b420f3200im48", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b420f3200im68.dtsi b/dts/arm/silabs/xg26/efr32mg26b420f3200im68.dtsi new file mode 100644 index 0000000000000..62ec253c89ee7 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b420f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b420f3200im68", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b421f3200im48.dtsi b/dts/arm/silabs/xg26/efr32mg26b421f3200im48.dtsi new file mode 100644 index 0000000000000..4d0f7a908f38e --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b421f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b421f3200im48", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b421f3200im68.dtsi b/dts/arm/silabs/xg26/efr32mg26b421f3200im68.dtsi new file mode 100644 index 0000000000000..da9774b909e4a --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b421f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b421f3200im68", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b510f3200il136.dtsi b/dts/arm/silabs/xg26/efr32mg26b510f3200il136.dtsi new file mode 100644 index 0000000000000..56392be813d47 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b510f3200il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b510f3200il136", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b510f3200im48.dtsi b/dts/arm/silabs/xg26/efr32mg26b510f3200im48.dtsi new file mode 100644 index 0000000000000..98db00cdceb99 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b510f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b510f3200im48", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b510f3200im68.dtsi b/dts/arm/silabs/xg26/efr32mg26b510f3200im68.dtsi new file mode 100644 index 0000000000000..66cb898a038dd --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b510f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b510f3200im68", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b511f3200il136.dtsi b/dts/arm/silabs/xg26/efr32mg26b511f3200il136.dtsi new file mode 100644 index 0000000000000..a17205ef29777 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b511f3200il136.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b511f3200il136", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b511f3200im48.dtsi b/dts/arm/silabs/xg26/efr32mg26b511f3200im48.dtsi new file mode 100644 index 0000000000000..477b0b1e65435 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b511f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b511f3200im48", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b511f3200im68.dtsi b/dts/arm/silabs/xg26/efr32mg26b511f3200im68.dtsi new file mode 100644 index 0000000000000..2f5b5b9b0d3e1 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b511f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b511f3200im68", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b520f3200im48.dtsi b/dts/arm/silabs/xg26/efr32mg26b520f3200im48.dtsi new file mode 100644 index 0000000000000..3496caa7951ef --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b520f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b520f3200im48", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b520f3200im68.dtsi b/dts/arm/silabs/xg26/efr32mg26b520f3200im68.dtsi new file mode 100644 index 0000000000000..72fe1ff11e515 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b520f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b520f3200im68", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b521f3200im48.dtsi b/dts/arm/silabs/xg26/efr32mg26b521f3200im48.dtsi new file mode 100644 index 0000000000000..01518e3b02d88 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b521f3200im48.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b521f3200im48", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32mg26b521f3200im68.dtsi b/dts/arm/silabs/xg26/efr32mg26b521f3200im68.dtsi new file mode 100644 index 0000000000000..b1e7817a87c31 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32mg26b521f3200im68.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg26b521f3200im68", "silabs,efr32mg26", "silabs,xg26", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/efr32xg26.dtsi b/dts/arm/silabs/xg26/efr32xg26.dtsi new file mode 100644 index 0000000000000..61dea61507c58 --- /dev/null +++ b/dts/arm/silabs/xg26/efr32xg26.dtsi @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + radio: radio@b0000000 { + compatible = "silabs,series2-radio"; + reg = <0xb0000000 0x01000000>; + interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer", + "rac_rsm", "rac_seq", "hostmailbox", "synth", "rfeca0", + "rfeca1"; + interrupts = <46 1>, <47 1>, <48 1>, <49 1>, <50 1>, <51 1>, <52 1>, + <53 1>, <54 1>, <55 1>, <86 1>, <87 1>; + pa-2p4ghz = "highest"; + pa-initial-power-dbm = <10>; + pa-ramp-time-us = <10>; + pa-voltage-mv = <3300>; + + pti: pti { + compatible = "silabs,pti"; + clock-frequency = ; + mode = "uart"; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/silabs/xg26/mgm26.dtsi b/dts/arm/silabs/xg26/mgm26.dtsi new file mode 100644 index 0000000000000..afa97cff141d2 --- /dev/null +++ b/dts/arm/silabs/xg26/mgm26.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&radio { + bt_hci_silabs: bt_hci_silabs { + compatible = "silabs,bt-hci-efr32"; + status = "disabled"; + }; +}; diff --git a/dts/arm/silabs/xg26/mgm260pb22vna.dtsi b/dts/arm/silabs/xg26/mgm260pb22vna.dtsi new file mode 100644 index 0000000000000..ed7da31a65543 --- /dev/null +++ b/dts/arm/silabs/xg26/mgm260pb22vna.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,mgm260pb22vna", "silabs,mgm26", "silabs,xg26", "silabs,efr32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&hfxo { + clock-frequency = ; + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfrco { + precision-mode; +}; + +&radio { + pa-voltage-mv = <1800>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/mgm260pb32vna.dtsi b/dts/arm/silabs/xg26/mgm260pb32vna.dtsi new file mode 100644 index 0000000000000..fc789948bd605 --- /dev/null +++ b/dts/arm/silabs/xg26/mgm260pb32vna.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,mgm260pb32vna", "silabs,mgm26", "silabs,xg26", "silabs,efr32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&hfxo { + clock-frequency = ; + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfrco { + precision-mode; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/mgm260pb32vnn.dtsi b/dts/arm/silabs/xg26/mgm260pb32vnn.dtsi new file mode 100644 index 0000000000000..852d77e9bab52 --- /dev/null +++ b/dts/arm/silabs/xg26/mgm260pb32vnn.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,mgm260pb32vnn", "silabs,mgm26", "silabs,xg26", "silabs,efr32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&hfxo { + clock-frequency = ; + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfrco { + precision-mode; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/mgm260pd22vna.dtsi b/dts/arm/silabs/xg26/mgm260pd22vna.dtsi new file mode 100644 index 0000000000000..86a4280ffb30f --- /dev/null +++ b/dts/arm/silabs/xg26/mgm260pd22vna.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,mgm260pd22vna", "silabs,mgm26", "silabs,xg26", "silabs,efr32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&hfxo { + clock-frequency = ; + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfrco { + precision-mode; +}; + +&radio { + pa-voltage-mv = <1800>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/mgm260pd32vna.dtsi b/dts/arm/silabs/xg26/mgm260pd32vna.dtsi new file mode 100644 index 0000000000000..bf2078b8961a5 --- /dev/null +++ b/dts/arm/silabs/xg26/mgm260pd32vna.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,mgm260pd32vna", "silabs,mgm26", "silabs,xg26", "silabs,efr32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&hfxo { + clock-frequency = ; + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfrco { + precision-mode; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/mgm260pd32vnn.dtsi b/dts/arm/silabs/xg26/mgm260pd32vnn.dtsi new file mode 100644 index 0000000000000..18a0abec2d32e --- /dev/null +++ b/dts/arm/silabs/xg26/mgm260pd32vnn.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,mgm260pd32vnn", "silabs,mgm26", "silabs,xg26", "silabs,efr32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(3200)>; +}; + +&hfxo { + clock-frequency = ; + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfrco { + precision-mode; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; +}; diff --git a/dts/arm/silabs/xg26/xg26.dtsi b/dts/arm/silabs/xg26/xg26.dtsi new file mode 100644 index 0000000000000..226bf2609d2ad --- /dev/null +++ b/dts/arm/silabs/xg26/xg26.dtsi @@ -0,0 +1,823 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + chosen { + silabs,sleeptimer = &sysrtc0; + zephyr,entropy = &se; + zephyr,flash-controller = &msc; + }; + + clocks { + em01grpaclk: em01grpaclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&hfrcodpll>; + }; + + em01grpcclk: em01grpcclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&hfrcodpll>; + }; + + em23grpaclk: em23grpaclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&lfrco>; + }; + + em4grpaclk: em4grpaclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&lfrco>; + }; + + eusart0clk: eusart0clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&em01grpcclk>; + }; + + hclk: hclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clocks = <&sysclk>; + }; + + hclkdiv1024: hclkdiv1024 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1024>; + clocks = <&hclk>; + }; + + hfrcodpllrt: hfrcodpllrt { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&hfrcodpll>; + }; + + hfxort: hfxort { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&hfxo>; + }; + + iadcclk: iadcclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&em01grpaclk>; + }; + + lcdclk: lcdclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&lfrco>; + }; + + lspclk: lspclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <2>; + clocks = <&pclk>; + }; + + pclk: pclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <2>; + clocks = <&hclk>; + }; + + pcnt0clk: pcnt0clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&em23grpaclk>; + }; + + sysclk: sysclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&hfrcodpll>; + }; + + sysrtcclk: sysrtcclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&lfrco>; + }; + + systickclk: systickclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&hclk>; + }; + + traceclk: traceclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clocks = <&sysclk>; + }; + + vdac0clk: vdac0clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&em01grpaclk>; + }; + + vdac1clk: vdac1clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&em01grpaclk>; + }; + + wdog0clk: wdog0clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&lfrco>; + }; + + wdog1clk: wdog1clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&lfrco>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-m33"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + /* + * The minimum residency and exit latency is managed by sl_power_manager + * on S2 devices. + */ + cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em4>; + device_type = "cpu"; + + itm: itm@e0000000 { + compatible = "arm,armv8m-itm"; + reg = <0xe0000000 0x1000>; + }; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + + power-states { + pstate_em1: em1 { + compatible = "zephyr,power-state"; + power-state-name = "runtime-idle"; + }; + + pstate_em2: em2 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + }; + + pstate_em4: em4 { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + status = "disabled"; + }; + }; + }; + + hwinfo: hwinfo { + compatible = "silabs,series2-hwinfo"; + status = "disabled"; + }; + + soc { + cmu: clock@50008000 { + compatible = "silabs,series-clock"; + reg = <0x50008000 0x4000>; + #clock-cells = <2>; + interrupt-names = "cmu"; + interrupts = <63 2>; + status = "okay"; + }; + + burtc0: burtc@5000c000 { + compatible = "silabs,gecko-burtc"; + reg = <0x5000c000 0x4000>; + clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>; + interrupt-names = "burtc"; + interrupts = <30 2>; + status = "disabled"; + }; + + hfrcodpll: hfrcodpll@50010000 { + compatible = "silabs,series2-hfrcodpll"; + reg = <0x50010000 0x4000>; + #clock-cells = <0>; + clock-frequency = ; + clocks = <&cmu CLOCK_HFRCO0 CLOCK_BRANCH_INVALID>; + interrupt-names = "hfrco0"; + interrupts = <61 2>; + }; + + fsrco: fsrco@50018000 { + compatible = "fixed-clock"; + reg = <0x50018000 0x4000>; + #clock-cells = <0>; + clock-frequency = ; + clocks = <&cmu CLOCK_FSRCO CLOCK_BRANCH_INVALID>; + }; + + lfxo: lfxo@50020000 { + compatible = "silabs,series2-lfxo"; + reg = <0x50020000 0x4000>; + #clock-cells = <0>; + clock-frequency = <32768>; + clocks = <&cmu CLOCK_LFXO CLOCK_BRANCH_INVALID>; + ctune = <63>; + interrupt-names = "lfxo"; + interrupts = <36 2>; + precision = <50>; + timeout = <4096>; + status = "disabled"; + }; + + lfrco: lfrco@50024000 { + compatible = "silabs,series2-lfrco"; + reg = <0x50024000 0x4000>; + #clock-cells = <0>; + clock-frequency = <32768>; + clocks = <&cmu CLOCK_LFRCO CLOCK_BRANCH_INVALID>; + }; + + ulfrco: ulfrco@50028000 { + compatible = "fixed-clock"; + reg = <0x50028000 0x4000>; + #clock-cells = <0>; + clock-frequency = <1000>; + clocks = <&cmu CLOCK_ULFRCO CLOCK_BRANCH_INVALID>; + interrupt-names = "ulfrco"; + interrupts = <38 2>; + }; + + msc: flash-controller@50030000 { + compatible = "silabs,series2-flash-controller"; + reg = <0x50030000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu CLOCK_MSC CLOCK_BRANCH_HCLK>; + interrupt-names = "msc"; + interrupts = <66 2>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + erase-block-size = <8192>; + write-block-size = <4>; + }; + }; + + gpio: gpio@5003c000 { + compatible = "silabs,gpio"; + reg = <0x5003c000 0x4000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>; + interrupt-names = "gpio_odd", "gpio_even"; + interrupts = <39 2>, <40 2>; + + gpioa: gpio@5003c030 { + compatible = "silabs,gpio-port"; + reg = <0x5003c030 0x30>; + #gpio-cells = <2>; + gpio-controller; + silabs,wakeup-ints = <0>; + silabs,wakeup-pins = <5>; + status = "disabled"; + }; + + gpiob: gpio@5003c060 { + compatible = "silabs,gpio-port"; + reg = <0x5003c060 0x30>; + #gpio-cells = <2>; + gpio-controller; + silabs,wakeup-ints = <3>, <4>; + silabs,wakeup-pins = <1>, <3>; + status = "disabled"; + }; + + gpioc: gpio@5003c090 { + compatible = "silabs,gpio-port"; + reg = <0x5003c090 0x30>; + #gpio-cells = <2>; + gpio-controller; + silabs,wakeup-ints = <6>, <7>, <8>; + silabs,wakeup-pins = <0>, <5>, <7>; + status = "disabled"; + }; + + gpiod: gpio@5003c0c0 { + compatible = "silabs,gpio-port"; + reg = <0x5003c0c0 0x30>; + #gpio-cells = <2>; + gpio-controller; + silabs,wakeup-ints = <10>, <9>; + silabs,wakeup-pins = <5>, <2>; + status = "disabled"; + }; + }; + + pinctrl: pin-controller@5003c440 { + compatible = "silabs,dbus-pinctrl"; + reg = <0x5003c440 0x0bc0>, <0x5003c320 0x40>; + reg-names = "dbus", "abus"; + }; + + clkin0: clkin0@5003c46c { + compatible = "fixed-clock"; + reg = <0x5003c46c 0x04>; + #clock-cells = <0>; + clock-frequency = ; + }; + + dma0: dma@50040000 { + compatible = "silabs,ldma"; + reg = <0x50040000 0x4000>; + #dma-cells = <1>; + clocks = <&cmu CLOCK_LDMA0 CLOCK_BRANCH_HCLK>; + dma-channels = <8>; + interrupt-names = "ldma"; + interrupts = <35 2>; + status = "disabled"; + }; + + timer0: timer@50048000 { + compatible = "silabs,series2-timer"; + reg = <0x50048000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER0 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <32>; + interrupt-names = "timer0"; + interrupts = <4 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer1: timer@5004c000 { + compatible = "silabs,series2-timer"; + reg = <0x5004c000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER1 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <32>; + interrupt-names = "timer1"; + interrupts = <5 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer2: timer@50050000 { + compatible = "silabs,series2-timer"; + reg = <0x50050000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER2 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <16>; + interrupt-names = "timer2"; + interrupts = <6 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer3: timer@50054000 { + compatible = "silabs,series2-timer"; + reg = <0x50054000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER3 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <16>; + interrupt-names = "timer3"; + interrupts = <7 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer4: timer@50058000 { + compatible = "silabs,series2-timer"; + reg = <0x50058000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER4 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <16>; + interrupt-names = "timer4"; + interrupts = <8 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer5: timer@5005c000 { + compatible = "silabs,series2-timer"; + reg = <0x5005c000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER5 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <16>; + interrupt-names = "timer5"; + interrupts = <9 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer6: timer@50060000 { + compatible = "silabs,series2-timer"; + reg = <0x50060000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER6 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <16>; + interrupt-names = "timer6"; + interrupts = <10 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer7: timer@50064000 { + compatible = "silabs,series2-timer"; + reg = <0x50064000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER7 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <16>; + interrupt-names = "timer7"; + interrupts = <11 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer8: timer@50068000 { + compatible = "silabs,series2-timer"; + reg = <0x50068000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER8 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <32>; + interrupt-names = "timer8"; + interrupts = <12 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer9: timer@5006c000 { + compatible = "silabs,series2-timer"; + reg = <0x5006c000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER9 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <32>; + interrupt-names = "timer9"; + interrupts = <13 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + buram: retained-memory@50084000 { + compatible = "silabs,buram"; + reg = <0x50084000 0x80>; + clocks = <&cmu CLOCK_BURAM CLOCK_BRANCH_INVALID>; + status = "disabled"; + }; + + eusart1: eusart@5008c000 { + compatible = "silabs,eusart-spi"; + reg = <0x5008c000 0x4000>; + clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>; + interrupt-names = "rx", "tx"; + interrupts = <22 2>, <23 2>; + status = "disabled"; + }; + + eusart2: eusart@50090000 { + compatible = "silabs,eusart-spi"; + reg = <0x50090000 0x4000>; + clocks = <&cmu CLOCK_EUSART2 CLOCK_BRANCH_EM01GRPCCLK>; + interrupt-names = "rx", "tx"; + interrupts = <24 2>, <25 2>; + status = "disabled"; + }; + + eusart3: eusart@50094000 { + compatible = "silabs,eusart-spi"; + reg = <0x50094000 0x4000>; + clocks = <&cmu CLOCK_EUSART3 CLOCK_BRANCH_EM01GRPCCLK>; + interrupt-names = "rx", "tx"; + interrupts = <26 2>, <27 2>; + status = "disabled"; + }; + + dcdc: dcdc@50098000 { + compatible = "silabs,series2-dcdc"; + reg = <0x50098000 0x4000>; + clocks = <&cmu CLOCK_DCDC CLOCK_BRANCH_INVALID>; + interrupt-names = "dcdc"; + interrupts = <69 2>; + status = "disabled"; + }; + + usart0: usart@500a0000 { + compatible = "silabs,usart-uart"; + reg = <0x500a0000 0x4000>; + clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>; + interrupt-names = "rx", "tx"; + interrupts = <14 2>, <15 2>; + status = "disabled"; + }; + + usart1: usart@500a4000 { + compatible = "silabs,usart-uart"; + reg = <0x500a4000 0x4000>; + clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_INVALID>; + interrupt-names = "rx", "tx"; + interrupts = <16 2>, <17 2>; + status = "disabled"; + }; + + usart2: usart@500a8000 { + compatible = "silabs,usart-uart"; + reg = <0x500a8000 0x4000>; + clocks = <&cmu CLOCK_USART2 CLOCK_BRANCH_INVALID>; + interrupt-names = "rx", "tx"; + interrupts = <18 2>, <19 2>; + status = "disabled"; + }; + + sysrtc0: sysrtc@500ac000 { + compatible = "silabs,sysrtc"; + reg = <0x500ac000 0x4000>; + clock-frequency = <32768>; + clocks = <&cmu CLOCK_SYSRTC0 CLOCK_BRANCH_SYSRTCCLK>; + interrupt-names = "sysrtc_app", "sysrtc_seq"; + interrupts = <83 2>, <84 2>; + prescaler = <1>; + status = "disabled"; + }; + + i2c1: i2c@500b0000 { + compatible = "silabs,i2c"; + reg = <0x500b0000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>; + interrupt-names = "i2c1"; + interrupts = <42 2>; + status = "disabled"; + }; + + i2c2: i2c@500b4000 { + compatible = "silabs,i2c"; + reg = <0x500b4000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + clocks = <&cmu CLOCK_I2C2 CLOCK_BRANCH_PCLK>; + interrupt-names = "i2c2"; + interrupts = <43 2>; + status = "disabled"; + }; + + i2c3: i2c@500b8000 { + compatible = "silabs,i2c"; + reg = <0x500b8000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + clocks = <&cmu CLOCK_I2C3 CLOCK_BRANCH_PCLK>; + interrupt-names = "i2c3"; + interrupts = <44 2>; + status = "disabled"; + }; + + letimer0: letimer@59000000 { + compatible = "silabs,series2-letimer"; + reg = <0x59000000 0x4000>; + clocks = <&cmu CLOCK_LETIMER0 CLOCK_BRANCH_EM23GRPACLK>; + interrupt-names = "letimer0"; + interrupts = <31 2>; + status = "disabled"; + + pwm { + compatible = "silabs,letimer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + adc0: adc@59004000 { + compatible = "silabs,iadc"; + reg = <0x59004000 0x4000>; + #io-channel-cells = <1>; + clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>; + interrupt-names = "iadc"; + interrupts = <65 2>; + status = "disabled"; + }; + + acmp0: acmp@59008000 { + compatible = "silabs,acmp"; + reg = <0x59008000 0x4000>; + clocks = <&cmu CLOCK_ACMP0 CLOCK_BRANCH_INVALID>; + interrupt-names = "acmp0"; + interrupts = <56 2>; + status = "disabled"; + }; + + acmp1: acmp@5900c000 { + compatible = "silabs,acmp"; + reg = <0x5900c000 0x4000>; + clocks = <&cmu CLOCK_ACMP1 CLOCK_BRANCH_INVALID>; + interrupt-names = "acmp1"; + interrupts = <57 2>; + status = "disabled"; + }; + + vdac0: vdac@59024000 { + compatible = "silabs,vdac"; + reg = <0x59024000 0x4000>; + #address-cells = <1>; + #io-channel-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLOCK_VDAC0 CLOCK_BRANCH_VDAC0CLK>; + interrupt-names = "vdac0"; + interrupts = <88 2>; + status = "disabled"; + + channel@0 { + reg = <0>; + }; + + channel@1 { + reg = <1>; + }; + }; + + vdac1: vdac@59028000 { + compatible = "silabs,vdac"; + reg = <0x59028000 0x4000>; + #address-cells = <1>; + #io-channel-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLOCK_VDAC1 CLOCK_BRANCH_VDAC1CLK>; + interrupt-names = "vdac1"; + interrupts = <89 2>; + status = "disabled"; + + channel@0 { + reg = <0>; + }; + + channel@1 { + reg = <1>; + }; + }; + + hfrcoem23: hfrcoem23@5a000000 { + compatible = "silabs,series2-hfrcoem23"; + reg = <0x5a000000 0x4000>; + #clock-cells = <0>; + clock-frequency = ; + clocks = <&cmu CLOCK_HFRCOEM23 CLOCK_BRANCH_INVALID>; + interrupt-names = "hfrcoem23"; + interrupts = <62 2>; + }; + + clk_hfxo: hfxo: hfxo@5a004000 { + compatible = "silabs,hfxo"; + reg = <0x5a004000 0x4000>; + #clock-cells = <0>; + clock-frequency = ; + clocks = <&cmu CLOCK_HFXO0 CLOCK_BRANCH_INVALID>; + ctune = <140>; + interrupt-names = "hfxo0"; + interrupts = <60 2>; + precision = <50>; + status = "disabled"; + }; + + i2c0: i2c@5b000000 { + compatible = "silabs,i2c"; + reg = <0x5b000000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>; + interrupt-names = "i2c0"; + interrupts = <41 2>; + status = "disabled"; + }; + + wdog0: wdog@5b004000 { + compatible = "silabs,gecko-wdog"; + reg = <0x5b004000 0x4000>; + clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>; + interrupt-names = "wdog0"; + interrupts = <58 2>; + peripheral-id = <0>; + status = "disabled"; + }; + + wdog1: wdog@5b008000 { + compatible = "silabs,gecko-wdog"; + reg = <0x5b008000 0x4000>; + clocks = <&cmu CLOCK_WDOG1 CLOCK_BRANCH_WDOG1CLK>; + interrupt-names = "wdog1"; + interrupts = <59 2>; + peripheral-id = <1>; + status = "disabled"; + }; + + eusart0: eusart@5b010000 { + compatible = "silabs,eusart-spi"; + reg = <0x5b010000 0x4000>; + clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>; + interrupt-names = "rx", "tx"; + interrupts = <20 2>, <21 2>; + status = "disabled"; + }; + + se: semailbox@5c000000 { + compatible = "silabs,gecko-semailbox"; + reg = <0x5c000000 0x4000>; + interrupt-names = "setamperhost", "sembrx", "sembtx"; + interrupts = <80 2>, <81 2>, <82 2>; + status = "disabled"; + }; + }; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + device_type = "memory"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; From 71a34ed4ba648a78c627aec1ede93ec68473883c Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Mon, 20 Oct 2025 17:25:38 +0200 Subject: [PATCH 2/6] include: zephyr: dt-bindings: Add Silicon Labs xg26 binding headers Add binding headers for clock control and pinctrl for Silicon Labs xg26 socs. Signed-off-by: Aksel Skauge Mellbye --- .../clock_control/clock_control_silabs.h | 2 + .../dt-bindings/clock/silabs/xg26-clock.h | 97 + .../zephyr/dt-bindings/dma/silabs/xg26-dma.h | 99 + .../dt-bindings/pinctrl/silabs/xg26-pinctrl.h | 8968 +++++++++++++++++ 4 files changed, 9166 insertions(+) create mode 100644 include/zephyr/dt-bindings/clock/silabs/xg26-clock.h create mode 100644 include/zephyr/dt-bindings/dma/silabs/xg26-dma.h create mode 100644 include/zephyr/dt-bindings/pinctrl/silabs/xg26-pinctrl.h diff --git a/include/zephyr/drivers/clock_control/clock_control_silabs.h b/include/zephyr/drivers/clock_control/clock_control_silabs.h index 26eaa96002f9d..bc12cbedc8250 100644 --- a/include/zephyr/drivers/clock_control/clock_control_silabs.h +++ b/include/zephyr/drivers/clock_control/clock_control_silabs.h @@ -17,6 +17,8 @@ #include #elif defined(CONFIG_SOC_SILABS_XG24) #include +#elif defined(CONFIG_SOC_SILABS_XG26) +#include #elif defined(CONFIG_SOC_SILABS_XG27) #include #elif defined(CONFIG_SOC_SILABS_XG28) diff --git a/include/zephyr/dt-bindings/clock/silabs/xg26-clock.h b/include/zephyr/dt-bindings/clock/silabs/xg26-clock.h new file mode 100644 index 0000000000000..c79caab22c97c --- /dev/null +++ b/include/zephyr/dt-bindings/clock/silabs/xg26-clock.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG26_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG26_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ACMP1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_ECAIFADC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_EUSART1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_EUSART2 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_EUSART3 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFRCOEM23 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_HOSTMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_I2C2 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_I2C3 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_KEYSCAN (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_LCD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_MVP (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_PCNT0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFECA0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_RFECA1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_RFMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RFSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_SEMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_SYSRTC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_TIMER5 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_TIMER6 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_TIMER7 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_TIMER8 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_TIMER9 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_USART1 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_USART2 (FIELD_PREP(CLOCK_REG_MASK, 2) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_VDAC0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_VDAC1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_WDOG1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG26_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/dma/silabs/xg26-dma.h b/include/zephyr/dt-bindings/dma/silabs/xg26-dma.h new file mode 100644 index 0000000000000..365cd6adeb44d --- /dev/null +++ b/include/zephyr/dt-bindings/dma/silabs/xg26-dma.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG26_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_XG26_DMA_H_ + +#include +#include "common-dma.h" + +/** + * Definition of Silabs LDMA request signal + */ +#define DMA_REQSEL_NONE (FIELD_PREP(DMA_SRC_MASK, 0) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_LDMAXBARPRSREQ0 (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_LDMAXBARPRSREQ1 (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER0CC0 (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER0CC1 (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER0CC2 (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER0UFOF (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_TIMER1CC0 (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER1CC1 (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER1CC2 (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER1UFOF (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_USART0RXDATAV (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_USART0RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_USART0TXBL (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_USART0TXBLRIGHT (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_USART0TXEMPTY (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 4)) +#define DMA_REQSEL_I2C0RXDATAV (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_I2C0TXBL (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_I2C1RXDATAV (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_I2C1TXBL (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_IADC0IADC_SCAN (FIELD_PREP(DMA_SRC_MASK, 10) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_IADC0IADC_SINGLE (FIELD_PREP(DMA_SRC_MASK, 10) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_MSCWDATA (FIELD_PREP(DMA_SRC_MASK, 11) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER2CC0 (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER2CC1 (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER2CC2 (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER2UFOF (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_TIMER3CC0 (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER3CC1 (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER3CC2 (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER3UFOF (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_TIMER4CC0 (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER4CC1 (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER4CC2 (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER4UFOF (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_EUSART0RXFL (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_EUSART0TXFL (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_EUSART1RXFL (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_EUSART1TXFL (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_VDAC0CH0_REQ (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_VDAC0CH1_REQ (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_VDAC1CH0_REQ (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_VDAC1CH1_REQ (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_EUSART2RXFL (FIELD_PREP(DMA_SRC_MASK, 19) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_EUSART2TXFL (FIELD_PREP(DMA_SRC_MASK, 19) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_EUSART3RXFL (FIELD_PREP(DMA_SRC_MASK, 20) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_EUSART3TXFL (FIELD_PREP(DMA_SRC_MASK, 20) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_USART1RXDATAV (FIELD_PREP(DMA_SRC_MASK, 21) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_USART1RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 21) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_USART1TXBL (FIELD_PREP(DMA_SRC_MASK, 21) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_USART1TXBLRIGHT (FIELD_PREP(DMA_SRC_MASK, 21) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_USART1TXEMPTY (FIELD_PREP(DMA_SRC_MASK, 21) | FIELD_PREP(DMA_SIG_MASK, 4)) +#define DMA_REQSEL_USART2RXDATAV (FIELD_PREP(DMA_SRC_MASK, 22) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_USART2RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 22) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_USART2TXBL (FIELD_PREP(DMA_SRC_MASK, 22) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_USART2TXBLRIGHT (FIELD_PREP(DMA_SRC_MASK, 22) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_USART2TXEMPTY (FIELD_PREP(DMA_SRC_MASK, 22) | FIELD_PREP(DMA_SIG_MASK, 4)) +#define DMA_REQSEL_TIMER5CC0 (FIELD_PREP(DMA_SRC_MASK, 23) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER5CC1 (FIELD_PREP(DMA_SRC_MASK, 23) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER5CC2 (FIELD_PREP(DMA_SRC_MASK, 23) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER5UFOF (FIELD_PREP(DMA_SRC_MASK, 23) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_TIMER6CC0 (FIELD_PREP(DMA_SRC_MASK, 24) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER6CC1 (FIELD_PREP(DMA_SRC_MASK, 24) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER6CC2 (FIELD_PREP(DMA_SRC_MASK, 24) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER6UFOF (FIELD_PREP(DMA_SRC_MASK, 24) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_TIMER7CC0 (FIELD_PREP(DMA_SRC_MASK, 25) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER7CC1 (FIELD_PREP(DMA_SRC_MASK, 25) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER7CC2 (FIELD_PREP(DMA_SRC_MASK, 25) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER7UFOF (FIELD_PREP(DMA_SRC_MASK, 25) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_TIMER8CC0 (FIELD_PREP(DMA_SRC_MASK, 26) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER8CC1 (FIELD_PREP(DMA_SRC_MASK, 26) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER8CC2 (FIELD_PREP(DMA_SRC_MASK, 26) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER8UFOF (FIELD_PREP(DMA_SRC_MASK, 26) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_TIMER9CC0 (FIELD_PREP(DMA_SRC_MASK, 27) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER9CC1 (FIELD_PREP(DMA_SRC_MASK, 27) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER9CC2 (FIELD_PREP(DMA_SRC_MASK, 27) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER9UFOF (FIELD_PREP(DMA_SRC_MASK, 27) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_I2C2RXDATAV (FIELD_PREP(DMA_SRC_MASK, 28) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_I2C2TXBL (FIELD_PREP(DMA_SRC_MASK, 28) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_I2C3RXDATAV (FIELD_PREP(DMA_SRC_MASK, 29) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_I2C3TXBL (FIELD_PREP(DMA_SRC_MASK, 29) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_LCD (FIELD_PREP(DMA_SRC_MASK, 30) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_MVPREQ (FIELD_PREP(DMA_SRC_MASK, 31) | FIELD_PREP(DMA_SIG_MASK, 0)) + +#endif diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/xg26-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/xg26-pinctrl.h new file mode 100644 index 0000000000000..9dbecdb1bd4f3 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/silabs/xg26-pinctrl.h @@ -0,0 +1,8968 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Pin Control for Silicon Labs XG26 devices + * + * This file was generated by the script gen_pinctrl.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG26_PINCTRL_H_ +#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG26_PINCTRL_H_ + +#include + +#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1) + +#define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1) + +#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2) +#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 10, 1, 1, 3) +#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 10, 1, 2, 4) +#define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1) + +#define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 21, 1, 0, 1) +#define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 21, 1, 1, 3) +#define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 21, 1, 2, 4) +#define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 21, 1, 3, 5) +#define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 21, 1, 4, 6) +#define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 21, 0, 0, 2) + +#define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 29, 1, 0, 1) +#define SILABS_DBUS_EUSART1_RTS(port, pin) SILABS_DBUS(port, pin, 29, 1, 1, 3) +#define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 29, 1, 2, 4) +#define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 29, 1, 3, 5) +#define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 29, 1, 4, 6) +#define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 29, 0, 0, 2) + +#define SILABS_DBUS_EUSART2_CS(port, pin) SILABS_DBUS(port, pin, 37, 1, 0, 1) +#define SILABS_DBUS_EUSART2_RTS(port, pin) SILABS_DBUS(port, pin, 37, 1, 1, 3) +#define SILABS_DBUS_EUSART2_RX(port, pin) SILABS_DBUS(port, pin, 37, 1, 2, 4) +#define SILABS_DBUS_EUSART2_SCLK(port, pin) SILABS_DBUS(port, pin, 37, 1, 3, 5) +#define SILABS_DBUS_EUSART2_TX(port, pin) SILABS_DBUS(port, pin, 37, 1, 4, 6) +#define SILABS_DBUS_EUSART2_CTS(port, pin) SILABS_DBUS(port, pin, 37, 0, 0, 2) + +#define SILABS_DBUS_EUSART3_CS(port, pin) SILABS_DBUS(port, pin, 45, 1, 0, 1) +#define SILABS_DBUS_EUSART3_RTS(port, pin) SILABS_DBUS(port, pin, 45, 1, 1, 3) +#define SILABS_DBUS_EUSART3_RX(port, pin) SILABS_DBUS(port, pin, 45, 1, 2, 4) +#define SILABS_DBUS_EUSART3_SCLK(port, pin) SILABS_DBUS(port, pin, 45, 1, 3, 5) +#define SILABS_DBUS_EUSART3_TX(port, pin) SILABS_DBUS(port, pin, 45, 1, 4, 6) +#define SILABS_DBUS_EUSART3_CTS(port, pin) SILABS_DBUS(port, pin, 45, 0, 0, 2) + +#define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 53, 1, 0, 1) +#define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 53, 1, 1, 2) +#define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 53, 1, 2, 3) + +#define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 58, 1, 0, 1) +#define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 58, 1, 1, 2) + +#define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 62, 1, 0, 1) +#define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 62, 1, 1, 2) + +#define SILABS_DBUS_I2C2_SCL(port, pin) SILABS_DBUS(port, pin, 66, 1, 0, 1) +#define SILABS_DBUS_I2C2_SDA(port, pin) SILABS_DBUS(port, pin, 66, 1, 1, 2) + +#define SILABS_DBUS_I2C3_SCL(port, pin) SILABS_DBUS(port, pin, 70, 1, 0, 1) +#define SILABS_DBUS_I2C3_SDA(port, pin) SILABS_DBUS(port, pin, 70, 1, 1, 2) + +#define SILABS_DBUS_KEYSCAN_COLOUT0(port, pin) SILABS_DBUS(port, pin, 74, 1, 0, 1) +#define SILABS_DBUS_KEYSCAN_COLOUT1(port, pin) SILABS_DBUS(port, pin, 74, 1, 1, 2) +#define SILABS_DBUS_KEYSCAN_COLOUT2(port, pin) SILABS_DBUS(port, pin, 74, 1, 2, 3) +#define SILABS_DBUS_KEYSCAN_COLOUT3(port, pin) SILABS_DBUS(port, pin, 74, 1, 3, 4) +#define SILABS_DBUS_KEYSCAN_COLOUT4(port, pin) SILABS_DBUS(port, pin, 74, 1, 4, 5) +#define SILABS_DBUS_KEYSCAN_COLOUT5(port, pin) SILABS_DBUS(port, pin, 74, 1, 5, 6) +#define SILABS_DBUS_KEYSCAN_COLOUT6(port, pin) SILABS_DBUS(port, pin, 74, 1, 6, 7) +#define SILABS_DBUS_KEYSCAN_COLOUT7(port, pin) SILABS_DBUS(port, pin, 74, 1, 7, 8) +#define SILABS_DBUS_KEYSCAN_ROWSENSE0(port, pin) SILABS_DBUS(port, pin, 74, 0, 0, 9) +#define SILABS_DBUS_KEYSCAN_ROWSENSE1(port, pin) SILABS_DBUS(port, pin, 74, 0, 0, 10) +#define SILABS_DBUS_KEYSCAN_ROWSENSE2(port, pin) SILABS_DBUS(port, pin, 74, 0, 0, 11) +#define SILABS_DBUS_KEYSCAN_ROWSENSE3(port, pin) SILABS_DBUS(port, pin, 74, 0, 0, 12) +#define SILABS_DBUS_KEYSCAN_ROWSENSE4(port, pin) SILABS_DBUS(port, pin, 74, 0, 0, 13) +#define SILABS_DBUS_KEYSCAN_ROWSENSE5(port, pin) SILABS_DBUS(port, pin, 74, 0, 0, 14) + +#define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 90, 1, 0, 1) +#define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 90, 1, 1, 2) + +#define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 94, 1, 0, 1) +#define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 94, 1, 1, 2) +#define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 94, 1, 2, 3) +#define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 94, 1, 3, 4) +#define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 94, 1, 4, 5) +#define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 94, 1, 5, 6) +#define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 94, 1, 6, 7) +#define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 94, 1, 7, 8) +#define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 94, 1, 8, 9) +#define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 94, 1, 9, 10) +#define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 94, 1, 10, 11) +#define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 94, 1, 11, 12) +#define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 94, 1, 12, 13) +#define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 94, 1, 13, 14) +#define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 94, 1, 14, 16) +#define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 94, 0, 0, 15) + +#define SILABS_DBUS_PCNT0_S0IN(port, pin) SILABS_DBUS(port, pin, 113, 0, 0, 0) +#define SILABS_DBUS_PCNT0_S1IN(port, pin) SILABS_DBUS(port, pin, 113, 0, 0, 1) + +#define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 116, 1, 0, 1) +#define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 116, 1, 1, 2) +#define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 116, 1, 2, 3) +#define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 116, 1, 3, 4) +#define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 116, 1, 4, 5) +#define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 116, 1, 5, 6) +#define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 116, 1, 6, 7) +#define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 116, 1, 7, 8) +#define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 116, 1, 8, 9) +#define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 116, 1, 9, 10) +#define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 116, 1, 10, 11) +#define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 116, 1, 11, 12) +#define SILABS_DBUS_PRS0_ASYNCH12(port, pin) SILABS_DBUS(port, pin, 116, 1, 12, 13) +#define SILABS_DBUS_PRS0_ASYNCH13(port, pin) SILABS_DBUS(port, pin, 116, 1, 13, 14) +#define SILABS_DBUS_PRS0_ASYNCH14(port, pin) SILABS_DBUS(port, pin, 116, 1, 14, 15) +#define SILABS_DBUS_PRS0_ASYNCH15(port, pin) SILABS_DBUS(port, pin, 116, 1, 15, 16) +#define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 116, 1, 16, 17) +#define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 116, 1, 17, 18) +#define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 116, 1, 18, 19) +#define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 116, 1, 19, 20) + +#define SILABS_DBUS_RAC_LNAEN(port, pin) SILABS_DBUS(port, pin, 138, 1, 0, 1) +#define SILABS_DBUS_RAC_PAEN(port, pin) SILABS_DBUS(port, pin, 138, 1, 1, 2) + +#define SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(port, pin) SILABS_DBUS(port, pin, 166, 0, 0, 0) + +#define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 168, 1, 0, 1) +#define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 168, 1, 1, 2) +#define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 168, 1, 2, 3) +#define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 168, 1, 3, 4) +#define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 168, 1, 4, 5) +#define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 168, 1, 5, 6) + +#define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 176, 1, 0, 1) +#define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 176, 1, 1, 2) +#define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 176, 1, 2, 3) +#define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 176, 1, 3, 4) +#define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 176, 1, 4, 5) +#define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 176, 1, 5, 6) + +#define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 184, 1, 0, 1) +#define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 184, 1, 1, 2) +#define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 184, 1, 2, 3) +#define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 184, 1, 3, 4) +#define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 184, 1, 4, 5) +#define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 184, 1, 5, 6) + +#define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 192, 1, 0, 1) +#define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 192, 1, 1, 2) +#define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 192, 1, 2, 3) +#define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 192, 1, 3, 4) +#define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 192, 1, 4, 5) +#define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 192, 1, 5, 6) + +#define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 200, 1, 0, 1) +#define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 200, 1, 1, 2) +#define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 200, 1, 2, 3) +#define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 200, 1, 3, 4) +#define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 200, 1, 4, 5) +#define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 200, 1, 5, 6) + +#define SILABS_DBUS_TIMER5_CC0(port, pin) SILABS_DBUS(port, pin, 208, 1, 0, 1) +#define SILABS_DBUS_TIMER5_CC1(port, pin) SILABS_DBUS(port, pin, 208, 1, 1, 2) +#define SILABS_DBUS_TIMER5_CC2(port, pin) SILABS_DBUS(port, pin, 208, 1, 2, 3) +#define SILABS_DBUS_TIMER5_CDTI0(port, pin) SILABS_DBUS(port, pin, 208, 1, 3, 4) +#define SILABS_DBUS_TIMER5_CDTI1(port, pin) SILABS_DBUS(port, pin, 208, 1, 4, 5) +#define SILABS_DBUS_TIMER5_CDTI2(port, pin) SILABS_DBUS(port, pin, 208, 1, 5, 6) + +#define SILABS_DBUS_TIMER6_CC0(port, pin) SILABS_DBUS(port, pin, 216, 1, 0, 1) +#define SILABS_DBUS_TIMER6_CC1(port, pin) SILABS_DBUS(port, pin, 216, 1, 1, 2) +#define SILABS_DBUS_TIMER6_CC2(port, pin) SILABS_DBUS(port, pin, 216, 1, 2, 3) +#define SILABS_DBUS_TIMER6_CDTI0(port, pin) SILABS_DBUS(port, pin, 216, 1, 3, 4) +#define SILABS_DBUS_TIMER6_CDTI1(port, pin) SILABS_DBUS(port, pin, 216, 1, 4, 5) +#define SILABS_DBUS_TIMER6_CDTI2(port, pin) SILABS_DBUS(port, pin, 216, 1, 5, 6) + +#define SILABS_DBUS_TIMER7_CC0(port, pin) SILABS_DBUS(port, pin, 224, 1, 0, 1) +#define SILABS_DBUS_TIMER7_CC1(port, pin) SILABS_DBUS(port, pin, 224, 1, 1, 2) +#define SILABS_DBUS_TIMER7_CC2(port, pin) SILABS_DBUS(port, pin, 224, 1, 2, 3) +#define SILABS_DBUS_TIMER7_CDTI0(port, pin) SILABS_DBUS(port, pin, 224, 1, 3, 4) +#define SILABS_DBUS_TIMER7_CDTI1(port, pin) SILABS_DBUS(port, pin, 224, 1, 4, 5) +#define SILABS_DBUS_TIMER7_CDTI2(port, pin) SILABS_DBUS(port, pin, 224, 1, 5, 6) + +#define SILABS_DBUS_TIMER8_CC0(port, pin) SILABS_DBUS(port, pin, 232, 1, 0, 1) +#define SILABS_DBUS_TIMER8_CC1(port, pin) SILABS_DBUS(port, pin, 232, 1, 1, 2) +#define SILABS_DBUS_TIMER8_CC2(port, pin) SILABS_DBUS(port, pin, 232, 1, 2, 3) +#define SILABS_DBUS_TIMER8_CDTI0(port, pin) SILABS_DBUS(port, pin, 232, 1, 3, 4) +#define SILABS_DBUS_TIMER8_CDTI1(port, pin) SILABS_DBUS(port, pin, 232, 1, 4, 5) +#define SILABS_DBUS_TIMER8_CDTI2(port, pin) SILABS_DBUS(port, pin, 232, 1, 5, 6) + +#define SILABS_DBUS_TIMER9_CC0(port, pin) SILABS_DBUS(port, pin, 240, 1, 0, 1) +#define SILABS_DBUS_TIMER9_CC1(port, pin) SILABS_DBUS(port, pin, 240, 1, 1, 2) +#define SILABS_DBUS_TIMER9_CC2(port, pin) SILABS_DBUS(port, pin, 240, 1, 2, 3) +#define SILABS_DBUS_TIMER9_CDTI0(port, pin) SILABS_DBUS(port, pin, 240, 1, 3, 4) +#define SILABS_DBUS_TIMER9_CDTI1(port, pin) SILABS_DBUS(port, pin, 240, 1, 4, 5) +#define SILABS_DBUS_TIMER9_CDTI2(port, pin) SILABS_DBUS(port, pin, 240, 1, 5, 6) + +#define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 248, 1, 0, 1) +#define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 248, 1, 1, 3) +#define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 248, 1, 2, 4) +#define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 248, 1, 3, 5) +#define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 248, 1, 4, 6) +#define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 248, 0, 0, 2) + +#define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 256, 1, 0, 1) +#define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 256, 1, 1, 3) +#define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 256, 1, 2, 4) +#define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 256, 1, 3, 5) +#define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 256, 1, 4, 6) +#define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 256, 0, 0, 2) + +#define SILABS_DBUS_USART2_CS(port, pin) SILABS_DBUS(port, pin, 264, 1, 0, 1) +#define SILABS_DBUS_USART2_RTS(port, pin) SILABS_DBUS(port, pin, 264, 1, 1, 3) +#define SILABS_DBUS_USART2_RX(port, pin) SILABS_DBUS(port, pin, 264, 1, 2, 4) +#define SILABS_DBUS_USART2_CLK(port, pin) SILABS_DBUS(port, pin, 264, 1, 3, 5) +#define SILABS_DBUS_USART2_TX(port, pin) SILABS_DBUS(port, pin, 264, 1, 4, 6) +#define SILABS_DBUS_USART2_CTS(port, pin) SILABS_DBUS(port, pin, 264, 0, 0, 2) + +#define GPIO_SWCLKTCK_PA1 SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0) +#define GPIO_SWDIOTMS_PA2 SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1) +#define GPIO_TDO_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2) +#define GPIO_TDI_PA4 SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3) +#define GPIO_SWV_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0) +#define GPIO_TRACECLK_PA4 SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1) +#define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2) +#define GPIO_TRACEDATA1_PA5 SILABS_FIXED_ROUTE(0x0, 0x5, 1, 3) +#define GPIO_TRACEDATA2_PA6 SILABS_FIXED_ROUTE(0x0, 0x6, 1, 4) +#define GPIO_TRACEDATA3_PA7 SILABS_FIXED_ROUTE(0x0, 0x7, 1, 5) + +#define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0) +#define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1) +#define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2) +#define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3) +#define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4) +#define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5) +#define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6) +#define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7) +#define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8) +#define ACMP0_ACMPOUT_PA9 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x9) +#define ACMP0_ACMPOUT_PA10 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xa) +#define ACMP0_ACMPOUT_PA11 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xb) +#define ACMP0_ACMPOUT_PA12 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xc) +#define ACMP0_ACMPOUT_PA13 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xd) +#define ACMP0_ACMPOUT_PA14 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xe) +#define ACMP0_ACMPOUT_PA15 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xf) +#define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0) +#define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1) +#define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2) +#define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3) +#define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4) +#define ACMP0_ACMPOUT_PB5 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x5) +#define ACMP0_ACMPOUT_PB6 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x6) +#define ACMP0_ACMPOUT_PB7 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x7) +#define ACMP0_ACMPOUT_PB8 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x8) +#define ACMP0_ACMPOUT_PB9 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x9) +#define ACMP0_ACMPOUT_PB10 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0xa) +#define ACMP0_ACMPOUT_PB11 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0xb) +#define ACMP0_ACMPOUT_PB12 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0xc) +#define ACMP0_ACMPOUT_PB13 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0xd) +#define ACMP0_ACMPOUT_PB14 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0xe) +#define ACMP0_ACMPOUT_PB15 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0xf) +#define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0) +#define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1) +#define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2) +#define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3) +#define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4) +#define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5) +#define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6) +#define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7) +#define ACMP0_ACMPOUT_PC8 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x8) +#define ACMP0_ACMPOUT_PC9 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x9) +#define ACMP0_ACMPOUT_PC10 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0xa) +#define ACMP0_ACMPOUT_PC11 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0xb) +#define ACMP0_ACMPOUT_PC12 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0xc) +#define ACMP0_ACMPOUT_PC13 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0xd) +#define ACMP0_ACMPOUT_PC14 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0xe) +#define ACMP0_ACMPOUT_PC15 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0xf) +#define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0) +#define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1) +#define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2) +#define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3) +#define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4) +#define ACMP0_ACMPOUT_PD5 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x5) +#define ACMP0_ACMPOUT_PD6 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x6) +#define ACMP0_ACMPOUT_PD7 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x7) +#define ACMP0_ACMPOUT_PD8 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x8) +#define ACMP0_ACMPOUT_PD9 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x9) +#define ACMP0_ACMPOUT_PD10 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xa) +#define ACMP0_ACMPOUT_PD11 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xb) +#define ACMP0_ACMPOUT_PD12 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xc) +#define ACMP0_ACMPOUT_PD13 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xd) +#define ACMP0_ACMPOUT_PD14 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xe) +#define ACMP0_ACMPOUT_PD15 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xf) + +#define ACMP1_ACMPOUT_PA0 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x0) +#define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1) +#define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2) +#define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3) +#define ACMP1_ACMPOUT_PA4 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x4) +#define ACMP1_ACMPOUT_PA5 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x5) +#define ACMP1_ACMPOUT_PA6 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x6) +#define ACMP1_ACMPOUT_PA7 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x7) +#define ACMP1_ACMPOUT_PA8 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x8) +#define ACMP1_ACMPOUT_PA9 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x9) +#define ACMP1_ACMPOUT_PA10 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xa) +#define ACMP1_ACMPOUT_PA11 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xb) +#define ACMP1_ACMPOUT_PA12 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xc) +#define ACMP1_ACMPOUT_PA13 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xd) +#define ACMP1_ACMPOUT_PA14 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xe) +#define ACMP1_ACMPOUT_PA15 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xf) +#define ACMP1_ACMPOUT_PB0 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x0) +#define ACMP1_ACMPOUT_PB1 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x1) +#define ACMP1_ACMPOUT_PB2 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x2) +#define ACMP1_ACMPOUT_PB3 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x3) +#define ACMP1_ACMPOUT_PB4 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x4) +#define ACMP1_ACMPOUT_PB5 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x5) +#define ACMP1_ACMPOUT_PB6 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x6) +#define ACMP1_ACMPOUT_PB7 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x7) +#define ACMP1_ACMPOUT_PB8 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x8) +#define ACMP1_ACMPOUT_PB9 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x9) +#define ACMP1_ACMPOUT_PB10 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0xa) +#define ACMP1_ACMPOUT_PB11 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0xb) +#define ACMP1_ACMPOUT_PB12 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0xc) +#define ACMP1_ACMPOUT_PB13 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0xd) +#define ACMP1_ACMPOUT_PB14 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0xe) +#define ACMP1_ACMPOUT_PB15 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0xf) +#define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0) +#define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1) +#define ACMP1_ACMPOUT_PC2 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x2) +#define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3) +#define ACMP1_ACMPOUT_PC4 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x4) +#define ACMP1_ACMPOUT_PC5 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x5) +#define ACMP1_ACMPOUT_PC6 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x6) +#define ACMP1_ACMPOUT_PC7 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x7) +#define ACMP1_ACMPOUT_PC8 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x8) +#define ACMP1_ACMPOUT_PC9 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x9) +#define ACMP1_ACMPOUT_PC10 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0xa) +#define ACMP1_ACMPOUT_PC11 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0xb) +#define ACMP1_ACMPOUT_PC12 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0xc) +#define ACMP1_ACMPOUT_PC13 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0xd) +#define ACMP1_ACMPOUT_PC14 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0xe) +#define ACMP1_ACMPOUT_PC15 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0xf) +#define ACMP1_ACMPOUT_PD0 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x0) +#define ACMP1_ACMPOUT_PD1 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x1) +#define ACMP1_ACMPOUT_PD2 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x2) +#define ACMP1_ACMPOUT_PD3 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x3) +#define ACMP1_ACMPOUT_PD4 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x4) +#define ACMP1_ACMPOUT_PD5 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x5) +#define ACMP1_ACMPOUT_PD6 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x6) +#define ACMP1_ACMPOUT_PD7 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x7) +#define ACMP1_ACMPOUT_PD8 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x8) +#define ACMP1_ACMPOUT_PD9 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x9) +#define ACMP1_ACMPOUT_PD10 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xa) +#define ACMP1_ACMPOUT_PD11 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xb) +#define ACMP1_ACMPOUT_PD12 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xc) +#define ACMP1_ACMPOUT_PD13 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xd) +#define ACMP1_ACMPOUT_PD14 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xe) +#define ACMP1_ACMPOUT_PD15 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xf) + +#define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0) +#define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1) +#define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2) +#define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3) +#define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4) +#define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5) +#define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6) +#define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7) +#define CMU_CLKOUT0_PC8 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x8) +#define CMU_CLKOUT0_PC9 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x9) +#define CMU_CLKOUT0_PC10 SILABS_DBUS_CMU_CLKOUT0(0x2, 0xa) +#define CMU_CLKOUT0_PC11 SILABS_DBUS_CMU_CLKOUT0(0x2, 0xb) +#define CMU_CLKOUT0_PC12 SILABS_DBUS_CMU_CLKOUT0(0x2, 0xc) +#define CMU_CLKOUT0_PC13 SILABS_DBUS_CMU_CLKOUT0(0x2, 0xd) +#define CMU_CLKOUT0_PC14 SILABS_DBUS_CMU_CLKOUT0(0x2, 0xe) +#define CMU_CLKOUT0_PC15 SILABS_DBUS_CMU_CLKOUT0(0x2, 0xf) +#define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0) +#define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1) +#define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2) +#define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3) +#define CMU_CLKOUT0_PD4 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x4) +#define CMU_CLKOUT0_PD5 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x5) +#define CMU_CLKOUT0_PD6 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x6) +#define CMU_CLKOUT0_PD7 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x7) +#define CMU_CLKOUT0_PD8 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x8) +#define CMU_CLKOUT0_PD9 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x9) +#define CMU_CLKOUT0_PD10 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xa) +#define CMU_CLKOUT0_PD11 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xb) +#define CMU_CLKOUT0_PD12 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xc) +#define CMU_CLKOUT0_PD13 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xd) +#define CMU_CLKOUT0_PD14 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xe) +#define CMU_CLKOUT0_PD15 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xf) +#define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0) +#define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1) +#define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2) +#define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3) +#define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4) +#define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5) +#define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6) +#define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7) +#define CMU_CLKOUT1_PC8 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x8) +#define CMU_CLKOUT1_PC9 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x9) +#define CMU_CLKOUT1_PC10 SILABS_DBUS_CMU_CLKOUT1(0x2, 0xa) +#define CMU_CLKOUT1_PC11 SILABS_DBUS_CMU_CLKOUT1(0x2, 0xb) +#define CMU_CLKOUT1_PC12 SILABS_DBUS_CMU_CLKOUT1(0x2, 0xc) +#define CMU_CLKOUT1_PC13 SILABS_DBUS_CMU_CLKOUT1(0x2, 0xd) +#define CMU_CLKOUT1_PC14 SILABS_DBUS_CMU_CLKOUT1(0x2, 0xe) +#define CMU_CLKOUT1_PC15 SILABS_DBUS_CMU_CLKOUT1(0x2, 0xf) +#define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0) +#define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1) +#define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2) +#define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3) +#define CMU_CLKOUT1_PD4 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x4) +#define CMU_CLKOUT1_PD5 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x5) +#define CMU_CLKOUT1_PD6 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x6) +#define CMU_CLKOUT1_PD7 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x7) +#define CMU_CLKOUT1_PD8 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x8) +#define CMU_CLKOUT1_PD9 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x9) +#define CMU_CLKOUT1_PD10 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xa) +#define CMU_CLKOUT1_PD11 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xb) +#define CMU_CLKOUT1_PD12 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xc) +#define CMU_CLKOUT1_PD13 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xd) +#define CMU_CLKOUT1_PD14 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xe) +#define CMU_CLKOUT1_PD15 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xf) +#define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0) +#define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1) +#define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2) +#define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3) +#define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4) +#define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5) +#define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6) +#define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7) +#define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8) +#define CMU_CLKOUT2_PA9 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x9) +#define CMU_CLKOUT2_PA10 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xa) +#define CMU_CLKOUT2_PA11 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xb) +#define CMU_CLKOUT2_PA12 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xc) +#define CMU_CLKOUT2_PA13 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xd) +#define CMU_CLKOUT2_PA14 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xe) +#define CMU_CLKOUT2_PA15 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xf) +#define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0) +#define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1) +#define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2) +#define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3) +#define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4) +#define CMU_CLKOUT2_PB5 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x5) +#define CMU_CLKOUT2_PB6 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x6) +#define CMU_CLKOUT2_PB7 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x7) +#define CMU_CLKOUT2_PB8 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x8) +#define CMU_CLKOUT2_PB9 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x9) +#define CMU_CLKOUT2_PB10 SILABS_DBUS_CMU_CLKOUT2(0x1, 0xa) +#define CMU_CLKOUT2_PB11 SILABS_DBUS_CMU_CLKOUT2(0x1, 0xb) +#define CMU_CLKOUT2_PB12 SILABS_DBUS_CMU_CLKOUT2(0x1, 0xc) +#define CMU_CLKOUT2_PB13 SILABS_DBUS_CMU_CLKOUT2(0x1, 0xd) +#define CMU_CLKOUT2_PB14 SILABS_DBUS_CMU_CLKOUT2(0x1, 0xe) +#define CMU_CLKOUT2_PB15 SILABS_DBUS_CMU_CLKOUT2(0x1, 0xf) +#define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0) +#define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1) +#define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2) +#define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3) +#define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4) +#define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5) +#define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6) +#define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7) +#define CMU_CLKIN0_PC8 SILABS_DBUS_CMU_CLKIN0(0x2, 0x8) +#define CMU_CLKIN0_PC9 SILABS_DBUS_CMU_CLKIN0(0x2, 0x9) +#define CMU_CLKIN0_PC10 SILABS_DBUS_CMU_CLKIN0(0x2, 0xa) +#define CMU_CLKIN0_PC11 SILABS_DBUS_CMU_CLKIN0(0x2, 0xb) +#define CMU_CLKIN0_PC12 SILABS_DBUS_CMU_CLKIN0(0x2, 0xc) +#define CMU_CLKIN0_PC13 SILABS_DBUS_CMU_CLKIN0(0x2, 0xd) +#define CMU_CLKIN0_PC14 SILABS_DBUS_CMU_CLKIN0(0x2, 0xe) +#define CMU_CLKIN0_PC15 SILABS_DBUS_CMU_CLKIN0(0x2, 0xf) +#define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0) +#define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1) +#define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2) +#define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3) +#define CMU_CLKIN0_PD4 SILABS_DBUS_CMU_CLKIN0(0x3, 0x4) +#define CMU_CLKIN0_PD5 SILABS_DBUS_CMU_CLKIN0(0x3, 0x5) +#define CMU_CLKIN0_PD6 SILABS_DBUS_CMU_CLKIN0(0x3, 0x6) +#define CMU_CLKIN0_PD7 SILABS_DBUS_CMU_CLKIN0(0x3, 0x7) +#define CMU_CLKIN0_PD8 SILABS_DBUS_CMU_CLKIN0(0x3, 0x8) +#define CMU_CLKIN0_PD9 SILABS_DBUS_CMU_CLKIN0(0x3, 0x9) +#define CMU_CLKIN0_PD10 SILABS_DBUS_CMU_CLKIN0(0x3, 0xa) +#define CMU_CLKIN0_PD11 SILABS_DBUS_CMU_CLKIN0(0x3, 0xb) +#define CMU_CLKIN0_PD12 SILABS_DBUS_CMU_CLKIN0(0x3, 0xc) +#define CMU_CLKIN0_PD13 SILABS_DBUS_CMU_CLKIN0(0x3, 0xd) +#define CMU_CLKIN0_PD14 SILABS_DBUS_CMU_CLKIN0(0x3, 0xe) +#define CMU_CLKIN0_PD15 SILABS_DBUS_CMU_CLKIN0(0x3, 0xf) + +#define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0) +#define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1) +#define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2) +#define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3) +#define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4) +#define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5) +#define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6) +#define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7) +#define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8) +#define EUSART0_CS_PA9 SILABS_DBUS_EUSART0_CS(0x0, 0x9) +#define EUSART0_CS_PA10 SILABS_DBUS_EUSART0_CS(0x0, 0xa) +#define EUSART0_CS_PA11 SILABS_DBUS_EUSART0_CS(0x0, 0xb) +#define EUSART0_CS_PA12 SILABS_DBUS_EUSART0_CS(0x0, 0xc) +#define EUSART0_CS_PA13 SILABS_DBUS_EUSART0_CS(0x0, 0xd) +#define EUSART0_CS_PA14 SILABS_DBUS_EUSART0_CS(0x0, 0xe) +#define EUSART0_CS_PA15 SILABS_DBUS_EUSART0_CS(0x0, 0xf) +#define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0) +#define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1) +#define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2) +#define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3) +#define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4) +#define EUSART0_CS_PB5 SILABS_DBUS_EUSART0_CS(0x1, 0x5) +#define EUSART0_CS_PB6 SILABS_DBUS_EUSART0_CS(0x1, 0x6) +#define EUSART0_CS_PB7 SILABS_DBUS_EUSART0_CS(0x1, 0x7) +#define EUSART0_CS_PB8 SILABS_DBUS_EUSART0_CS(0x1, 0x8) +#define EUSART0_CS_PB9 SILABS_DBUS_EUSART0_CS(0x1, 0x9) +#define EUSART0_CS_PB10 SILABS_DBUS_EUSART0_CS(0x1, 0xa) +#define EUSART0_CS_PB11 SILABS_DBUS_EUSART0_CS(0x1, 0xb) +#define EUSART0_CS_PB12 SILABS_DBUS_EUSART0_CS(0x1, 0xc) +#define EUSART0_CS_PB13 SILABS_DBUS_EUSART0_CS(0x1, 0xd) +#define EUSART0_CS_PB14 SILABS_DBUS_EUSART0_CS(0x1, 0xe) +#define EUSART0_CS_PB15 SILABS_DBUS_EUSART0_CS(0x1, 0xf) +#define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0) +#define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1) +#define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2) +#define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3) +#define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4) +#define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5) +#define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6) +#define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7) +#define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8) +#define EUSART0_RTS_PA9 SILABS_DBUS_EUSART0_RTS(0x0, 0x9) +#define EUSART0_RTS_PA10 SILABS_DBUS_EUSART0_RTS(0x0, 0xa) +#define EUSART0_RTS_PA11 SILABS_DBUS_EUSART0_RTS(0x0, 0xb) +#define EUSART0_RTS_PA12 SILABS_DBUS_EUSART0_RTS(0x0, 0xc) +#define EUSART0_RTS_PA13 SILABS_DBUS_EUSART0_RTS(0x0, 0xd) +#define EUSART0_RTS_PA14 SILABS_DBUS_EUSART0_RTS(0x0, 0xe) +#define EUSART0_RTS_PA15 SILABS_DBUS_EUSART0_RTS(0x0, 0xf) +#define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0) +#define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1) +#define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2) +#define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3) +#define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4) +#define EUSART0_RTS_PB5 SILABS_DBUS_EUSART0_RTS(0x1, 0x5) +#define EUSART0_RTS_PB6 SILABS_DBUS_EUSART0_RTS(0x1, 0x6) +#define EUSART0_RTS_PB7 SILABS_DBUS_EUSART0_RTS(0x1, 0x7) +#define EUSART0_RTS_PB8 SILABS_DBUS_EUSART0_RTS(0x1, 0x8) +#define EUSART0_RTS_PB9 SILABS_DBUS_EUSART0_RTS(0x1, 0x9) +#define EUSART0_RTS_PB10 SILABS_DBUS_EUSART0_RTS(0x1, 0xa) +#define EUSART0_RTS_PB11 SILABS_DBUS_EUSART0_RTS(0x1, 0xb) +#define EUSART0_RTS_PB12 SILABS_DBUS_EUSART0_RTS(0x1, 0xc) +#define EUSART0_RTS_PB13 SILABS_DBUS_EUSART0_RTS(0x1, 0xd) +#define EUSART0_RTS_PB14 SILABS_DBUS_EUSART0_RTS(0x1, 0xe) +#define EUSART0_RTS_PB15 SILABS_DBUS_EUSART0_RTS(0x1, 0xf) +#define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0) +#define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1) +#define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2) +#define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3) +#define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4) +#define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5) +#define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6) +#define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7) +#define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8) +#define EUSART0_RX_PA9 SILABS_DBUS_EUSART0_RX(0x0, 0x9) +#define EUSART0_RX_PA10 SILABS_DBUS_EUSART0_RX(0x0, 0xa) +#define EUSART0_RX_PA11 SILABS_DBUS_EUSART0_RX(0x0, 0xb) +#define EUSART0_RX_PA12 SILABS_DBUS_EUSART0_RX(0x0, 0xc) +#define EUSART0_RX_PA13 SILABS_DBUS_EUSART0_RX(0x0, 0xd) +#define EUSART0_RX_PA14 SILABS_DBUS_EUSART0_RX(0x0, 0xe) +#define EUSART0_RX_PA15 SILABS_DBUS_EUSART0_RX(0x0, 0xf) +#define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0) +#define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1) +#define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2) +#define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3) +#define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4) +#define EUSART0_RX_PB5 SILABS_DBUS_EUSART0_RX(0x1, 0x5) +#define EUSART0_RX_PB6 SILABS_DBUS_EUSART0_RX(0x1, 0x6) +#define EUSART0_RX_PB7 SILABS_DBUS_EUSART0_RX(0x1, 0x7) +#define EUSART0_RX_PB8 SILABS_DBUS_EUSART0_RX(0x1, 0x8) +#define EUSART0_RX_PB9 SILABS_DBUS_EUSART0_RX(0x1, 0x9) +#define EUSART0_RX_PB10 SILABS_DBUS_EUSART0_RX(0x1, 0xa) +#define EUSART0_RX_PB11 SILABS_DBUS_EUSART0_RX(0x1, 0xb) +#define EUSART0_RX_PB12 SILABS_DBUS_EUSART0_RX(0x1, 0xc) +#define EUSART0_RX_PB13 SILABS_DBUS_EUSART0_RX(0x1, 0xd) +#define EUSART0_RX_PB14 SILABS_DBUS_EUSART0_RX(0x1, 0xe) +#define EUSART0_RX_PB15 SILABS_DBUS_EUSART0_RX(0x1, 0xf) +#define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0) +#define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1) +#define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2) +#define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3) +#define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4) +#define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5) +#define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6) +#define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7) +#define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8) +#define EUSART0_SCLK_PA9 SILABS_DBUS_EUSART0_SCLK(0x0, 0x9) +#define EUSART0_SCLK_PA10 SILABS_DBUS_EUSART0_SCLK(0x0, 0xa) +#define EUSART0_SCLK_PA11 SILABS_DBUS_EUSART0_SCLK(0x0, 0xb) +#define EUSART0_SCLK_PA12 SILABS_DBUS_EUSART0_SCLK(0x0, 0xc) +#define EUSART0_SCLK_PA13 SILABS_DBUS_EUSART0_SCLK(0x0, 0xd) +#define EUSART0_SCLK_PA14 SILABS_DBUS_EUSART0_SCLK(0x0, 0xe) +#define EUSART0_SCLK_PA15 SILABS_DBUS_EUSART0_SCLK(0x0, 0xf) +#define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0) +#define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1) +#define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2) +#define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3) +#define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4) +#define EUSART0_SCLK_PB5 SILABS_DBUS_EUSART0_SCLK(0x1, 0x5) +#define EUSART0_SCLK_PB6 SILABS_DBUS_EUSART0_SCLK(0x1, 0x6) +#define EUSART0_SCLK_PB7 SILABS_DBUS_EUSART0_SCLK(0x1, 0x7) +#define EUSART0_SCLK_PB8 SILABS_DBUS_EUSART0_SCLK(0x1, 0x8) +#define EUSART0_SCLK_PB9 SILABS_DBUS_EUSART0_SCLK(0x1, 0x9) +#define EUSART0_SCLK_PB10 SILABS_DBUS_EUSART0_SCLK(0x1, 0xa) +#define EUSART0_SCLK_PB11 SILABS_DBUS_EUSART0_SCLK(0x1, 0xb) +#define EUSART0_SCLK_PB12 SILABS_DBUS_EUSART0_SCLK(0x1, 0xc) +#define EUSART0_SCLK_PB13 SILABS_DBUS_EUSART0_SCLK(0x1, 0xd) +#define EUSART0_SCLK_PB14 SILABS_DBUS_EUSART0_SCLK(0x1, 0xe) +#define EUSART0_SCLK_PB15 SILABS_DBUS_EUSART0_SCLK(0x1, 0xf) +#define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0) +#define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1) +#define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2) +#define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3) +#define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4) +#define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5) +#define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6) +#define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7) +#define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8) +#define EUSART0_TX_PA9 SILABS_DBUS_EUSART0_TX(0x0, 0x9) +#define EUSART0_TX_PA10 SILABS_DBUS_EUSART0_TX(0x0, 0xa) +#define EUSART0_TX_PA11 SILABS_DBUS_EUSART0_TX(0x0, 0xb) +#define EUSART0_TX_PA12 SILABS_DBUS_EUSART0_TX(0x0, 0xc) +#define EUSART0_TX_PA13 SILABS_DBUS_EUSART0_TX(0x0, 0xd) +#define EUSART0_TX_PA14 SILABS_DBUS_EUSART0_TX(0x0, 0xe) +#define EUSART0_TX_PA15 SILABS_DBUS_EUSART0_TX(0x0, 0xf) +#define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0) +#define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1) +#define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2) +#define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3) +#define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4) +#define EUSART0_TX_PB5 SILABS_DBUS_EUSART0_TX(0x1, 0x5) +#define EUSART0_TX_PB6 SILABS_DBUS_EUSART0_TX(0x1, 0x6) +#define EUSART0_TX_PB7 SILABS_DBUS_EUSART0_TX(0x1, 0x7) +#define EUSART0_TX_PB8 SILABS_DBUS_EUSART0_TX(0x1, 0x8) +#define EUSART0_TX_PB9 SILABS_DBUS_EUSART0_TX(0x1, 0x9) +#define EUSART0_TX_PB10 SILABS_DBUS_EUSART0_TX(0x1, 0xa) +#define EUSART0_TX_PB11 SILABS_DBUS_EUSART0_TX(0x1, 0xb) +#define EUSART0_TX_PB12 SILABS_DBUS_EUSART0_TX(0x1, 0xc) +#define EUSART0_TX_PB13 SILABS_DBUS_EUSART0_TX(0x1, 0xd) +#define EUSART0_TX_PB14 SILABS_DBUS_EUSART0_TX(0x1, 0xe) +#define EUSART0_TX_PB15 SILABS_DBUS_EUSART0_TX(0x1, 0xf) +#define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0) +#define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1) +#define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2) +#define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3) +#define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4) +#define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5) +#define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6) +#define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7) +#define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8) +#define EUSART0_CTS_PA9 SILABS_DBUS_EUSART0_CTS(0x0, 0x9) +#define EUSART0_CTS_PA10 SILABS_DBUS_EUSART0_CTS(0x0, 0xa) +#define EUSART0_CTS_PA11 SILABS_DBUS_EUSART0_CTS(0x0, 0xb) +#define EUSART0_CTS_PA12 SILABS_DBUS_EUSART0_CTS(0x0, 0xc) +#define EUSART0_CTS_PA13 SILABS_DBUS_EUSART0_CTS(0x0, 0xd) +#define EUSART0_CTS_PA14 SILABS_DBUS_EUSART0_CTS(0x0, 0xe) +#define EUSART0_CTS_PA15 SILABS_DBUS_EUSART0_CTS(0x0, 0xf) +#define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0) +#define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1) +#define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2) +#define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3) +#define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4) +#define EUSART0_CTS_PB5 SILABS_DBUS_EUSART0_CTS(0x1, 0x5) +#define EUSART0_CTS_PB6 SILABS_DBUS_EUSART0_CTS(0x1, 0x6) +#define EUSART0_CTS_PB7 SILABS_DBUS_EUSART0_CTS(0x1, 0x7) +#define EUSART0_CTS_PB8 SILABS_DBUS_EUSART0_CTS(0x1, 0x8) +#define EUSART0_CTS_PB9 SILABS_DBUS_EUSART0_CTS(0x1, 0x9) +#define EUSART0_CTS_PB10 SILABS_DBUS_EUSART0_CTS(0x1, 0xa) +#define EUSART0_CTS_PB11 SILABS_DBUS_EUSART0_CTS(0x1, 0xb) +#define EUSART0_CTS_PB12 SILABS_DBUS_EUSART0_CTS(0x1, 0xc) +#define EUSART0_CTS_PB13 SILABS_DBUS_EUSART0_CTS(0x1, 0xd) +#define EUSART0_CTS_PB14 SILABS_DBUS_EUSART0_CTS(0x1, 0xe) +#define EUSART0_CTS_PB15 SILABS_DBUS_EUSART0_CTS(0x1, 0xf) + +#define EUSART1_CS_PA0 SILABS_DBUS_EUSART1_CS(0x0, 0x0) +#define EUSART1_CS_PA1 SILABS_DBUS_EUSART1_CS(0x0, 0x1) +#define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2) +#define EUSART1_CS_PA3 SILABS_DBUS_EUSART1_CS(0x0, 0x3) +#define EUSART1_CS_PA4 SILABS_DBUS_EUSART1_CS(0x0, 0x4) +#define EUSART1_CS_PA5 SILABS_DBUS_EUSART1_CS(0x0, 0x5) +#define EUSART1_CS_PA6 SILABS_DBUS_EUSART1_CS(0x0, 0x6) +#define EUSART1_CS_PA7 SILABS_DBUS_EUSART1_CS(0x0, 0x7) +#define EUSART1_CS_PA8 SILABS_DBUS_EUSART1_CS(0x0, 0x8) +#define EUSART1_CS_PA9 SILABS_DBUS_EUSART1_CS(0x0, 0x9) +#define EUSART1_CS_PA10 SILABS_DBUS_EUSART1_CS(0x0, 0xa) +#define EUSART1_CS_PA11 SILABS_DBUS_EUSART1_CS(0x0, 0xb) +#define EUSART1_CS_PA12 SILABS_DBUS_EUSART1_CS(0x0, 0xc) +#define EUSART1_CS_PA13 SILABS_DBUS_EUSART1_CS(0x0, 0xd) +#define EUSART1_CS_PA14 SILABS_DBUS_EUSART1_CS(0x0, 0xe) +#define EUSART1_CS_PA15 SILABS_DBUS_EUSART1_CS(0x0, 0xf) +#define EUSART1_CS_PB0 SILABS_DBUS_EUSART1_CS(0x1, 0x0) +#define EUSART1_CS_PB1 SILABS_DBUS_EUSART1_CS(0x1, 0x1) +#define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2) +#define EUSART1_CS_PB3 SILABS_DBUS_EUSART1_CS(0x1, 0x3) +#define EUSART1_CS_PB4 SILABS_DBUS_EUSART1_CS(0x1, 0x4) +#define EUSART1_CS_PB5 SILABS_DBUS_EUSART1_CS(0x1, 0x5) +#define EUSART1_CS_PB6 SILABS_DBUS_EUSART1_CS(0x1, 0x6) +#define EUSART1_CS_PB7 SILABS_DBUS_EUSART1_CS(0x1, 0x7) +#define EUSART1_CS_PB8 SILABS_DBUS_EUSART1_CS(0x1, 0x8) +#define EUSART1_CS_PB9 SILABS_DBUS_EUSART1_CS(0x1, 0x9) +#define EUSART1_CS_PB10 SILABS_DBUS_EUSART1_CS(0x1, 0xa) +#define EUSART1_CS_PB11 SILABS_DBUS_EUSART1_CS(0x1, 0xb) +#define EUSART1_CS_PB12 SILABS_DBUS_EUSART1_CS(0x1, 0xc) +#define EUSART1_CS_PB13 SILABS_DBUS_EUSART1_CS(0x1, 0xd) +#define EUSART1_CS_PB14 SILABS_DBUS_EUSART1_CS(0x1, 0xe) +#define EUSART1_CS_PB15 SILABS_DBUS_EUSART1_CS(0x1, 0xf) +#define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0) +#define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1) +#define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2) +#define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3) +#define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4) +#define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5) +#define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6) +#define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7) +#define EUSART1_CS_PC8 SILABS_DBUS_EUSART1_CS(0x2, 0x8) +#define EUSART1_CS_PC9 SILABS_DBUS_EUSART1_CS(0x2, 0x9) +#define EUSART1_CS_PC10 SILABS_DBUS_EUSART1_CS(0x2, 0xa) +#define EUSART1_CS_PC11 SILABS_DBUS_EUSART1_CS(0x2, 0xb) +#define EUSART1_CS_PC12 SILABS_DBUS_EUSART1_CS(0x2, 0xc) +#define EUSART1_CS_PC13 SILABS_DBUS_EUSART1_CS(0x2, 0xd) +#define EUSART1_CS_PC14 SILABS_DBUS_EUSART1_CS(0x2, 0xe) +#define EUSART1_CS_PC15 SILABS_DBUS_EUSART1_CS(0x2, 0xf) +#define EUSART1_CS_PD0 SILABS_DBUS_EUSART1_CS(0x3, 0x0) +#define EUSART1_CS_PD1 SILABS_DBUS_EUSART1_CS(0x3, 0x1) +#define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2) +#define EUSART1_CS_PD3 SILABS_DBUS_EUSART1_CS(0x3, 0x3) +#define EUSART1_CS_PD4 SILABS_DBUS_EUSART1_CS(0x3, 0x4) +#define EUSART1_CS_PD5 SILABS_DBUS_EUSART1_CS(0x3, 0x5) +#define EUSART1_CS_PD6 SILABS_DBUS_EUSART1_CS(0x3, 0x6) +#define EUSART1_CS_PD7 SILABS_DBUS_EUSART1_CS(0x3, 0x7) +#define EUSART1_CS_PD8 SILABS_DBUS_EUSART1_CS(0x3, 0x8) +#define EUSART1_CS_PD9 SILABS_DBUS_EUSART1_CS(0x3, 0x9) +#define EUSART1_CS_PD10 SILABS_DBUS_EUSART1_CS(0x3, 0xa) +#define EUSART1_CS_PD11 SILABS_DBUS_EUSART1_CS(0x3, 0xb) +#define EUSART1_CS_PD12 SILABS_DBUS_EUSART1_CS(0x3, 0xc) +#define EUSART1_CS_PD13 SILABS_DBUS_EUSART1_CS(0x3, 0xd) +#define EUSART1_CS_PD14 SILABS_DBUS_EUSART1_CS(0x3, 0xe) +#define EUSART1_CS_PD15 SILABS_DBUS_EUSART1_CS(0x3, 0xf) +#define EUSART1_RTS_PA0 SILABS_DBUS_EUSART1_RTS(0x0, 0x0) +#define EUSART1_RTS_PA1 SILABS_DBUS_EUSART1_RTS(0x0, 0x1) +#define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2) +#define EUSART1_RTS_PA3 SILABS_DBUS_EUSART1_RTS(0x0, 0x3) +#define EUSART1_RTS_PA4 SILABS_DBUS_EUSART1_RTS(0x0, 0x4) +#define EUSART1_RTS_PA5 SILABS_DBUS_EUSART1_RTS(0x0, 0x5) +#define EUSART1_RTS_PA6 SILABS_DBUS_EUSART1_RTS(0x0, 0x6) +#define EUSART1_RTS_PA7 SILABS_DBUS_EUSART1_RTS(0x0, 0x7) +#define EUSART1_RTS_PA8 SILABS_DBUS_EUSART1_RTS(0x0, 0x8) +#define EUSART1_RTS_PA9 SILABS_DBUS_EUSART1_RTS(0x0, 0x9) +#define EUSART1_RTS_PA10 SILABS_DBUS_EUSART1_RTS(0x0, 0xa) +#define EUSART1_RTS_PA11 SILABS_DBUS_EUSART1_RTS(0x0, 0xb) +#define EUSART1_RTS_PA12 SILABS_DBUS_EUSART1_RTS(0x0, 0xc) +#define EUSART1_RTS_PA13 SILABS_DBUS_EUSART1_RTS(0x0, 0xd) +#define EUSART1_RTS_PA14 SILABS_DBUS_EUSART1_RTS(0x0, 0xe) +#define EUSART1_RTS_PA15 SILABS_DBUS_EUSART1_RTS(0x0, 0xf) +#define EUSART1_RTS_PB0 SILABS_DBUS_EUSART1_RTS(0x1, 0x0) +#define EUSART1_RTS_PB1 SILABS_DBUS_EUSART1_RTS(0x1, 0x1) +#define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2) +#define EUSART1_RTS_PB3 SILABS_DBUS_EUSART1_RTS(0x1, 0x3) +#define EUSART1_RTS_PB4 SILABS_DBUS_EUSART1_RTS(0x1, 0x4) +#define EUSART1_RTS_PB5 SILABS_DBUS_EUSART1_RTS(0x1, 0x5) +#define EUSART1_RTS_PB6 SILABS_DBUS_EUSART1_RTS(0x1, 0x6) +#define EUSART1_RTS_PB7 SILABS_DBUS_EUSART1_RTS(0x1, 0x7) +#define EUSART1_RTS_PB8 SILABS_DBUS_EUSART1_RTS(0x1, 0x8) +#define EUSART1_RTS_PB9 SILABS_DBUS_EUSART1_RTS(0x1, 0x9) +#define EUSART1_RTS_PB10 SILABS_DBUS_EUSART1_RTS(0x1, 0xa) +#define EUSART1_RTS_PB11 SILABS_DBUS_EUSART1_RTS(0x1, 0xb) +#define EUSART1_RTS_PB12 SILABS_DBUS_EUSART1_RTS(0x1, 0xc) +#define EUSART1_RTS_PB13 SILABS_DBUS_EUSART1_RTS(0x1, 0xd) +#define EUSART1_RTS_PB14 SILABS_DBUS_EUSART1_RTS(0x1, 0xe) +#define EUSART1_RTS_PB15 SILABS_DBUS_EUSART1_RTS(0x1, 0xf) +#define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0) +#define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1) +#define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2) +#define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3) +#define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4) +#define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5) +#define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6) +#define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7) +#define EUSART1_RTS_PC8 SILABS_DBUS_EUSART1_RTS(0x2, 0x8) +#define EUSART1_RTS_PC9 SILABS_DBUS_EUSART1_RTS(0x2, 0x9) +#define EUSART1_RTS_PC10 SILABS_DBUS_EUSART1_RTS(0x2, 0xa) +#define EUSART1_RTS_PC11 SILABS_DBUS_EUSART1_RTS(0x2, 0xb) +#define EUSART1_RTS_PC12 SILABS_DBUS_EUSART1_RTS(0x2, 0xc) +#define EUSART1_RTS_PC13 SILABS_DBUS_EUSART1_RTS(0x2, 0xd) +#define EUSART1_RTS_PC14 SILABS_DBUS_EUSART1_RTS(0x2, 0xe) +#define EUSART1_RTS_PC15 SILABS_DBUS_EUSART1_RTS(0x2, 0xf) +#define EUSART1_RTS_PD0 SILABS_DBUS_EUSART1_RTS(0x3, 0x0) +#define EUSART1_RTS_PD1 SILABS_DBUS_EUSART1_RTS(0x3, 0x1) +#define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2) +#define EUSART1_RTS_PD3 SILABS_DBUS_EUSART1_RTS(0x3, 0x3) +#define EUSART1_RTS_PD4 SILABS_DBUS_EUSART1_RTS(0x3, 0x4) +#define EUSART1_RTS_PD5 SILABS_DBUS_EUSART1_RTS(0x3, 0x5) +#define EUSART1_RTS_PD6 SILABS_DBUS_EUSART1_RTS(0x3, 0x6) +#define EUSART1_RTS_PD7 SILABS_DBUS_EUSART1_RTS(0x3, 0x7) +#define EUSART1_RTS_PD8 SILABS_DBUS_EUSART1_RTS(0x3, 0x8) +#define EUSART1_RTS_PD9 SILABS_DBUS_EUSART1_RTS(0x3, 0x9) +#define EUSART1_RTS_PD10 SILABS_DBUS_EUSART1_RTS(0x3, 0xa) +#define EUSART1_RTS_PD11 SILABS_DBUS_EUSART1_RTS(0x3, 0xb) +#define EUSART1_RTS_PD12 SILABS_DBUS_EUSART1_RTS(0x3, 0xc) +#define EUSART1_RTS_PD13 SILABS_DBUS_EUSART1_RTS(0x3, 0xd) +#define EUSART1_RTS_PD14 SILABS_DBUS_EUSART1_RTS(0x3, 0xe) +#define EUSART1_RTS_PD15 SILABS_DBUS_EUSART1_RTS(0x3, 0xf) +#define EUSART1_RX_PA0 SILABS_DBUS_EUSART1_RX(0x0, 0x0) +#define EUSART1_RX_PA1 SILABS_DBUS_EUSART1_RX(0x0, 0x1) +#define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2) +#define EUSART1_RX_PA3 SILABS_DBUS_EUSART1_RX(0x0, 0x3) +#define EUSART1_RX_PA4 SILABS_DBUS_EUSART1_RX(0x0, 0x4) +#define EUSART1_RX_PA5 SILABS_DBUS_EUSART1_RX(0x0, 0x5) +#define EUSART1_RX_PA6 SILABS_DBUS_EUSART1_RX(0x0, 0x6) +#define EUSART1_RX_PA7 SILABS_DBUS_EUSART1_RX(0x0, 0x7) +#define EUSART1_RX_PA8 SILABS_DBUS_EUSART1_RX(0x0, 0x8) +#define EUSART1_RX_PA9 SILABS_DBUS_EUSART1_RX(0x0, 0x9) +#define EUSART1_RX_PA10 SILABS_DBUS_EUSART1_RX(0x0, 0xa) +#define EUSART1_RX_PA11 SILABS_DBUS_EUSART1_RX(0x0, 0xb) +#define EUSART1_RX_PA12 SILABS_DBUS_EUSART1_RX(0x0, 0xc) +#define EUSART1_RX_PA13 SILABS_DBUS_EUSART1_RX(0x0, 0xd) +#define EUSART1_RX_PA14 SILABS_DBUS_EUSART1_RX(0x0, 0xe) +#define EUSART1_RX_PA15 SILABS_DBUS_EUSART1_RX(0x0, 0xf) +#define EUSART1_RX_PB0 SILABS_DBUS_EUSART1_RX(0x1, 0x0) +#define EUSART1_RX_PB1 SILABS_DBUS_EUSART1_RX(0x1, 0x1) +#define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2) +#define EUSART1_RX_PB3 SILABS_DBUS_EUSART1_RX(0x1, 0x3) +#define EUSART1_RX_PB4 SILABS_DBUS_EUSART1_RX(0x1, 0x4) +#define EUSART1_RX_PB5 SILABS_DBUS_EUSART1_RX(0x1, 0x5) +#define EUSART1_RX_PB6 SILABS_DBUS_EUSART1_RX(0x1, 0x6) +#define EUSART1_RX_PB7 SILABS_DBUS_EUSART1_RX(0x1, 0x7) +#define EUSART1_RX_PB8 SILABS_DBUS_EUSART1_RX(0x1, 0x8) +#define EUSART1_RX_PB9 SILABS_DBUS_EUSART1_RX(0x1, 0x9) +#define EUSART1_RX_PB10 SILABS_DBUS_EUSART1_RX(0x1, 0xa) +#define EUSART1_RX_PB11 SILABS_DBUS_EUSART1_RX(0x1, 0xb) +#define EUSART1_RX_PB12 SILABS_DBUS_EUSART1_RX(0x1, 0xc) +#define EUSART1_RX_PB13 SILABS_DBUS_EUSART1_RX(0x1, 0xd) +#define EUSART1_RX_PB14 SILABS_DBUS_EUSART1_RX(0x1, 0xe) +#define EUSART1_RX_PB15 SILABS_DBUS_EUSART1_RX(0x1, 0xf) +#define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0) +#define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1) +#define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2) +#define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3) +#define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4) +#define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5) +#define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6) +#define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7) +#define EUSART1_RX_PC8 SILABS_DBUS_EUSART1_RX(0x2, 0x8) +#define EUSART1_RX_PC9 SILABS_DBUS_EUSART1_RX(0x2, 0x9) +#define EUSART1_RX_PC10 SILABS_DBUS_EUSART1_RX(0x2, 0xa) +#define EUSART1_RX_PC11 SILABS_DBUS_EUSART1_RX(0x2, 0xb) +#define EUSART1_RX_PC12 SILABS_DBUS_EUSART1_RX(0x2, 0xc) +#define EUSART1_RX_PC13 SILABS_DBUS_EUSART1_RX(0x2, 0xd) +#define EUSART1_RX_PC14 SILABS_DBUS_EUSART1_RX(0x2, 0xe) +#define EUSART1_RX_PC15 SILABS_DBUS_EUSART1_RX(0x2, 0xf) +#define EUSART1_RX_PD0 SILABS_DBUS_EUSART1_RX(0x3, 0x0) +#define EUSART1_RX_PD1 SILABS_DBUS_EUSART1_RX(0x3, 0x1) +#define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2) +#define EUSART1_RX_PD3 SILABS_DBUS_EUSART1_RX(0x3, 0x3) +#define EUSART1_RX_PD4 SILABS_DBUS_EUSART1_RX(0x3, 0x4) +#define EUSART1_RX_PD5 SILABS_DBUS_EUSART1_RX(0x3, 0x5) +#define EUSART1_RX_PD6 SILABS_DBUS_EUSART1_RX(0x3, 0x6) +#define EUSART1_RX_PD7 SILABS_DBUS_EUSART1_RX(0x3, 0x7) +#define EUSART1_RX_PD8 SILABS_DBUS_EUSART1_RX(0x3, 0x8) +#define EUSART1_RX_PD9 SILABS_DBUS_EUSART1_RX(0x3, 0x9) +#define EUSART1_RX_PD10 SILABS_DBUS_EUSART1_RX(0x3, 0xa) +#define EUSART1_RX_PD11 SILABS_DBUS_EUSART1_RX(0x3, 0xb) +#define EUSART1_RX_PD12 SILABS_DBUS_EUSART1_RX(0x3, 0xc) +#define EUSART1_RX_PD13 SILABS_DBUS_EUSART1_RX(0x3, 0xd) +#define EUSART1_RX_PD14 SILABS_DBUS_EUSART1_RX(0x3, 0xe) +#define EUSART1_RX_PD15 SILABS_DBUS_EUSART1_RX(0x3, 0xf) +#define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0) +#define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1) +#define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2) +#define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3) +#define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4) +#define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5) +#define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6) +#define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7) +#define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8) +#define EUSART1_SCLK_PA9 SILABS_DBUS_EUSART1_SCLK(0x0, 0x9) +#define EUSART1_SCLK_PA10 SILABS_DBUS_EUSART1_SCLK(0x0, 0xa) +#define EUSART1_SCLK_PA11 SILABS_DBUS_EUSART1_SCLK(0x0, 0xb) +#define EUSART1_SCLK_PA12 SILABS_DBUS_EUSART1_SCLK(0x0, 0xc) +#define EUSART1_SCLK_PA13 SILABS_DBUS_EUSART1_SCLK(0x0, 0xd) +#define EUSART1_SCLK_PA14 SILABS_DBUS_EUSART1_SCLK(0x0, 0xe) +#define EUSART1_SCLK_PA15 SILABS_DBUS_EUSART1_SCLK(0x0, 0xf) +#define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0) +#define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1) +#define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2) +#define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3) +#define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4) +#define EUSART1_SCLK_PB5 SILABS_DBUS_EUSART1_SCLK(0x1, 0x5) +#define EUSART1_SCLK_PB6 SILABS_DBUS_EUSART1_SCLK(0x1, 0x6) +#define EUSART1_SCLK_PB7 SILABS_DBUS_EUSART1_SCLK(0x1, 0x7) +#define EUSART1_SCLK_PB8 SILABS_DBUS_EUSART1_SCLK(0x1, 0x8) +#define EUSART1_SCLK_PB9 SILABS_DBUS_EUSART1_SCLK(0x1, 0x9) +#define EUSART1_SCLK_PB10 SILABS_DBUS_EUSART1_SCLK(0x1, 0xa) +#define EUSART1_SCLK_PB11 SILABS_DBUS_EUSART1_SCLK(0x1, 0xb) +#define EUSART1_SCLK_PB12 SILABS_DBUS_EUSART1_SCLK(0x1, 0xc) +#define EUSART1_SCLK_PB13 SILABS_DBUS_EUSART1_SCLK(0x1, 0xd) +#define EUSART1_SCLK_PB14 SILABS_DBUS_EUSART1_SCLK(0x1, 0xe) +#define EUSART1_SCLK_PB15 SILABS_DBUS_EUSART1_SCLK(0x1, 0xf) +#define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0) +#define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1) +#define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2) +#define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3) +#define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4) +#define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5) +#define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6) +#define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7) +#define EUSART1_SCLK_PC8 SILABS_DBUS_EUSART1_SCLK(0x2, 0x8) +#define EUSART1_SCLK_PC9 SILABS_DBUS_EUSART1_SCLK(0x2, 0x9) +#define EUSART1_SCLK_PC10 SILABS_DBUS_EUSART1_SCLK(0x2, 0xa) +#define EUSART1_SCLK_PC11 SILABS_DBUS_EUSART1_SCLK(0x2, 0xb) +#define EUSART1_SCLK_PC12 SILABS_DBUS_EUSART1_SCLK(0x2, 0xc) +#define EUSART1_SCLK_PC13 SILABS_DBUS_EUSART1_SCLK(0x2, 0xd) +#define EUSART1_SCLK_PC14 SILABS_DBUS_EUSART1_SCLK(0x2, 0xe) +#define EUSART1_SCLK_PC15 SILABS_DBUS_EUSART1_SCLK(0x2, 0xf) +#define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0) +#define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1) +#define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2) +#define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3) +#define EUSART1_SCLK_PD4 SILABS_DBUS_EUSART1_SCLK(0x3, 0x4) +#define EUSART1_SCLK_PD5 SILABS_DBUS_EUSART1_SCLK(0x3, 0x5) +#define EUSART1_SCLK_PD6 SILABS_DBUS_EUSART1_SCLK(0x3, 0x6) +#define EUSART1_SCLK_PD7 SILABS_DBUS_EUSART1_SCLK(0x3, 0x7) +#define EUSART1_SCLK_PD8 SILABS_DBUS_EUSART1_SCLK(0x3, 0x8) +#define EUSART1_SCLK_PD9 SILABS_DBUS_EUSART1_SCLK(0x3, 0x9) +#define EUSART1_SCLK_PD10 SILABS_DBUS_EUSART1_SCLK(0x3, 0xa) +#define EUSART1_SCLK_PD11 SILABS_DBUS_EUSART1_SCLK(0x3, 0xb) +#define EUSART1_SCLK_PD12 SILABS_DBUS_EUSART1_SCLK(0x3, 0xc) +#define EUSART1_SCLK_PD13 SILABS_DBUS_EUSART1_SCLK(0x3, 0xd) +#define EUSART1_SCLK_PD14 SILABS_DBUS_EUSART1_SCLK(0x3, 0xe) +#define EUSART1_SCLK_PD15 SILABS_DBUS_EUSART1_SCLK(0x3, 0xf) +#define EUSART1_TX_PA0 SILABS_DBUS_EUSART1_TX(0x0, 0x0) +#define EUSART1_TX_PA1 SILABS_DBUS_EUSART1_TX(0x0, 0x1) +#define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2) +#define EUSART1_TX_PA3 SILABS_DBUS_EUSART1_TX(0x0, 0x3) +#define EUSART1_TX_PA4 SILABS_DBUS_EUSART1_TX(0x0, 0x4) +#define EUSART1_TX_PA5 SILABS_DBUS_EUSART1_TX(0x0, 0x5) +#define EUSART1_TX_PA6 SILABS_DBUS_EUSART1_TX(0x0, 0x6) +#define EUSART1_TX_PA7 SILABS_DBUS_EUSART1_TX(0x0, 0x7) +#define EUSART1_TX_PA8 SILABS_DBUS_EUSART1_TX(0x0, 0x8) +#define EUSART1_TX_PA9 SILABS_DBUS_EUSART1_TX(0x0, 0x9) +#define EUSART1_TX_PA10 SILABS_DBUS_EUSART1_TX(0x0, 0xa) +#define EUSART1_TX_PA11 SILABS_DBUS_EUSART1_TX(0x0, 0xb) +#define EUSART1_TX_PA12 SILABS_DBUS_EUSART1_TX(0x0, 0xc) +#define EUSART1_TX_PA13 SILABS_DBUS_EUSART1_TX(0x0, 0xd) +#define EUSART1_TX_PA14 SILABS_DBUS_EUSART1_TX(0x0, 0xe) +#define EUSART1_TX_PA15 SILABS_DBUS_EUSART1_TX(0x0, 0xf) +#define EUSART1_TX_PB0 SILABS_DBUS_EUSART1_TX(0x1, 0x0) +#define EUSART1_TX_PB1 SILABS_DBUS_EUSART1_TX(0x1, 0x1) +#define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2) +#define EUSART1_TX_PB3 SILABS_DBUS_EUSART1_TX(0x1, 0x3) +#define EUSART1_TX_PB4 SILABS_DBUS_EUSART1_TX(0x1, 0x4) +#define EUSART1_TX_PB5 SILABS_DBUS_EUSART1_TX(0x1, 0x5) +#define EUSART1_TX_PB6 SILABS_DBUS_EUSART1_TX(0x1, 0x6) +#define EUSART1_TX_PB7 SILABS_DBUS_EUSART1_TX(0x1, 0x7) +#define EUSART1_TX_PB8 SILABS_DBUS_EUSART1_TX(0x1, 0x8) +#define EUSART1_TX_PB9 SILABS_DBUS_EUSART1_TX(0x1, 0x9) +#define EUSART1_TX_PB10 SILABS_DBUS_EUSART1_TX(0x1, 0xa) +#define EUSART1_TX_PB11 SILABS_DBUS_EUSART1_TX(0x1, 0xb) +#define EUSART1_TX_PB12 SILABS_DBUS_EUSART1_TX(0x1, 0xc) +#define EUSART1_TX_PB13 SILABS_DBUS_EUSART1_TX(0x1, 0xd) +#define EUSART1_TX_PB14 SILABS_DBUS_EUSART1_TX(0x1, 0xe) +#define EUSART1_TX_PB15 SILABS_DBUS_EUSART1_TX(0x1, 0xf) +#define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0) +#define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1) +#define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2) +#define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3) +#define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4) +#define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5) +#define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6) +#define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7) +#define EUSART1_TX_PC8 SILABS_DBUS_EUSART1_TX(0x2, 0x8) +#define EUSART1_TX_PC9 SILABS_DBUS_EUSART1_TX(0x2, 0x9) +#define EUSART1_TX_PC10 SILABS_DBUS_EUSART1_TX(0x2, 0xa) +#define EUSART1_TX_PC11 SILABS_DBUS_EUSART1_TX(0x2, 0xb) +#define EUSART1_TX_PC12 SILABS_DBUS_EUSART1_TX(0x2, 0xc) +#define EUSART1_TX_PC13 SILABS_DBUS_EUSART1_TX(0x2, 0xd) +#define EUSART1_TX_PC14 SILABS_DBUS_EUSART1_TX(0x2, 0xe) +#define EUSART1_TX_PC15 SILABS_DBUS_EUSART1_TX(0x2, 0xf) +#define EUSART1_TX_PD0 SILABS_DBUS_EUSART1_TX(0x3, 0x0) +#define EUSART1_TX_PD1 SILABS_DBUS_EUSART1_TX(0x3, 0x1) +#define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2) +#define EUSART1_TX_PD3 SILABS_DBUS_EUSART1_TX(0x3, 0x3) +#define EUSART1_TX_PD4 SILABS_DBUS_EUSART1_TX(0x3, 0x4) +#define EUSART1_TX_PD5 SILABS_DBUS_EUSART1_TX(0x3, 0x5) +#define EUSART1_TX_PD6 SILABS_DBUS_EUSART1_TX(0x3, 0x6) +#define EUSART1_TX_PD7 SILABS_DBUS_EUSART1_TX(0x3, 0x7) +#define EUSART1_TX_PD8 SILABS_DBUS_EUSART1_TX(0x3, 0x8) +#define EUSART1_TX_PD9 SILABS_DBUS_EUSART1_TX(0x3, 0x9) +#define EUSART1_TX_PD10 SILABS_DBUS_EUSART1_TX(0x3, 0xa) +#define EUSART1_TX_PD11 SILABS_DBUS_EUSART1_TX(0x3, 0xb) +#define EUSART1_TX_PD12 SILABS_DBUS_EUSART1_TX(0x3, 0xc) +#define EUSART1_TX_PD13 SILABS_DBUS_EUSART1_TX(0x3, 0xd) +#define EUSART1_TX_PD14 SILABS_DBUS_EUSART1_TX(0x3, 0xe) +#define EUSART1_TX_PD15 SILABS_DBUS_EUSART1_TX(0x3, 0xf) +#define EUSART1_CTS_PA0 SILABS_DBUS_EUSART1_CTS(0x0, 0x0) +#define EUSART1_CTS_PA1 SILABS_DBUS_EUSART1_CTS(0x0, 0x1) +#define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2) +#define EUSART1_CTS_PA3 SILABS_DBUS_EUSART1_CTS(0x0, 0x3) +#define EUSART1_CTS_PA4 SILABS_DBUS_EUSART1_CTS(0x0, 0x4) +#define EUSART1_CTS_PA5 SILABS_DBUS_EUSART1_CTS(0x0, 0x5) +#define EUSART1_CTS_PA6 SILABS_DBUS_EUSART1_CTS(0x0, 0x6) +#define EUSART1_CTS_PA7 SILABS_DBUS_EUSART1_CTS(0x0, 0x7) +#define EUSART1_CTS_PA8 SILABS_DBUS_EUSART1_CTS(0x0, 0x8) +#define EUSART1_CTS_PA9 SILABS_DBUS_EUSART1_CTS(0x0, 0x9) +#define EUSART1_CTS_PA10 SILABS_DBUS_EUSART1_CTS(0x0, 0xa) +#define EUSART1_CTS_PA11 SILABS_DBUS_EUSART1_CTS(0x0, 0xb) +#define EUSART1_CTS_PA12 SILABS_DBUS_EUSART1_CTS(0x0, 0xc) +#define EUSART1_CTS_PA13 SILABS_DBUS_EUSART1_CTS(0x0, 0xd) +#define EUSART1_CTS_PA14 SILABS_DBUS_EUSART1_CTS(0x0, 0xe) +#define EUSART1_CTS_PA15 SILABS_DBUS_EUSART1_CTS(0x0, 0xf) +#define EUSART1_CTS_PB0 SILABS_DBUS_EUSART1_CTS(0x1, 0x0) +#define EUSART1_CTS_PB1 SILABS_DBUS_EUSART1_CTS(0x1, 0x1) +#define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2) +#define EUSART1_CTS_PB3 SILABS_DBUS_EUSART1_CTS(0x1, 0x3) +#define EUSART1_CTS_PB4 SILABS_DBUS_EUSART1_CTS(0x1, 0x4) +#define EUSART1_CTS_PB5 SILABS_DBUS_EUSART1_CTS(0x1, 0x5) +#define EUSART1_CTS_PB6 SILABS_DBUS_EUSART1_CTS(0x1, 0x6) +#define EUSART1_CTS_PB7 SILABS_DBUS_EUSART1_CTS(0x1, 0x7) +#define EUSART1_CTS_PB8 SILABS_DBUS_EUSART1_CTS(0x1, 0x8) +#define EUSART1_CTS_PB9 SILABS_DBUS_EUSART1_CTS(0x1, 0x9) +#define EUSART1_CTS_PB10 SILABS_DBUS_EUSART1_CTS(0x1, 0xa) +#define EUSART1_CTS_PB11 SILABS_DBUS_EUSART1_CTS(0x1, 0xb) +#define EUSART1_CTS_PB12 SILABS_DBUS_EUSART1_CTS(0x1, 0xc) +#define EUSART1_CTS_PB13 SILABS_DBUS_EUSART1_CTS(0x1, 0xd) +#define EUSART1_CTS_PB14 SILABS_DBUS_EUSART1_CTS(0x1, 0xe) +#define EUSART1_CTS_PB15 SILABS_DBUS_EUSART1_CTS(0x1, 0xf) +#define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0) +#define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1) +#define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2) +#define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3) +#define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4) +#define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5) +#define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6) +#define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7) +#define EUSART1_CTS_PC8 SILABS_DBUS_EUSART1_CTS(0x2, 0x8) +#define EUSART1_CTS_PC9 SILABS_DBUS_EUSART1_CTS(0x2, 0x9) +#define EUSART1_CTS_PC10 SILABS_DBUS_EUSART1_CTS(0x2, 0xa) +#define EUSART1_CTS_PC11 SILABS_DBUS_EUSART1_CTS(0x2, 0xb) +#define EUSART1_CTS_PC12 SILABS_DBUS_EUSART1_CTS(0x2, 0xc) +#define EUSART1_CTS_PC13 SILABS_DBUS_EUSART1_CTS(0x2, 0xd) +#define EUSART1_CTS_PC14 SILABS_DBUS_EUSART1_CTS(0x2, 0xe) +#define EUSART1_CTS_PC15 SILABS_DBUS_EUSART1_CTS(0x2, 0xf) +#define EUSART1_CTS_PD0 SILABS_DBUS_EUSART1_CTS(0x3, 0x0) +#define EUSART1_CTS_PD1 SILABS_DBUS_EUSART1_CTS(0x3, 0x1) +#define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2) +#define EUSART1_CTS_PD3 SILABS_DBUS_EUSART1_CTS(0x3, 0x3) +#define EUSART1_CTS_PD4 SILABS_DBUS_EUSART1_CTS(0x3, 0x4) +#define EUSART1_CTS_PD5 SILABS_DBUS_EUSART1_CTS(0x3, 0x5) +#define EUSART1_CTS_PD6 SILABS_DBUS_EUSART1_CTS(0x3, 0x6) +#define EUSART1_CTS_PD7 SILABS_DBUS_EUSART1_CTS(0x3, 0x7) +#define EUSART1_CTS_PD8 SILABS_DBUS_EUSART1_CTS(0x3, 0x8) +#define EUSART1_CTS_PD9 SILABS_DBUS_EUSART1_CTS(0x3, 0x9) +#define EUSART1_CTS_PD10 SILABS_DBUS_EUSART1_CTS(0x3, 0xa) +#define EUSART1_CTS_PD11 SILABS_DBUS_EUSART1_CTS(0x3, 0xb) +#define EUSART1_CTS_PD12 SILABS_DBUS_EUSART1_CTS(0x3, 0xc) +#define EUSART1_CTS_PD13 SILABS_DBUS_EUSART1_CTS(0x3, 0xd) +#define EUSART1_CTS_PD14 SILABS_DBUS_EUSART1_CTS(0x3, 0xe) +#define EUSART1_CTS_PD15 SILABS_DBUS_EUSART1_CTS(0x3, 0xf) + +#define EUSART2_CS_PA0 SILABS_DBUS_EUSART2_CS(0x0, 0x0) +#define EUSART2_CS_PA1 SILABS_DBUS_EUSART2_CS(0x0, 0x1) +#define EUSART2_CS_PA2 SILABS_DBUS_EUSART2_CS(0x0, 0x2) +#define EUSART2_CS_PA3 SILABS_DBUS_EUSART2_CS(0x0, 0x3) +#define EUSART2_CS_PA4 SILABS_DBUS_EUSART2_CS(0x0, 0x4) +#define EUSART2_CS_PA5 SILABS_DBUS_EUSART2_CS(0x0, 0x5) +#define EUSART2_CS_PA6 SILABS_DBUS_EUSART2_CS(0x0, 0x6) +#define EUSART2_CS_PA7 SILABS_DBUS_EUSART2_CS(0x0, 0x7) +#define EUSART2_CS_PA8 SILABS_DBUS_EUSART2_CS(0x0, 0x8) +#define EUSART2_CS_PA9 SILABS_DBUS_EUSART2_CS(0x0, 0x9) +#define EUSART2_CS_PA10 SILABS_DBUS_EUSART2_CS(0x0, 0xa) +#define EUSART2_CS_PA11 SILABS_DBUS_EUSART2_CS(0x0, 0xb) +#define EUSART2_CS_PA12 SILABS_DBUS_EUSART2_CS(0x0, 0xc) +#define EUSART2_CS_PA13 SILABS_DBUS_EUSART2_CS(0x0, 0xd) +#define EUSART2_CS_PA14 SILABS_DBUS_EUSART2_CS(0x0, 0xe) +#define EUSART2_CS_PA15 SILABS_DBUS_EUSART2_CS(0x0, 0xf) +#define EUSART2_CS_PB0 SILABS_DBUS_EUSART2_CS(0x1, 0x0) +#define EUSART2_CS_PB1 SILABS_DBUS_EUSART2_CS(0x1, 0x1) +#define EUSART2_CS_PB2 SILABS_DBUS_EUSART2_CS(0x1, 0x2) +#define EUSART2_CS_PB3 SILABS_DBUS_EUSART2_CS(0x1, 0x3) +#define EUSART2_CS_PB4 SILABS_DBUS_EUSART2_CS(0x1, 0x4) +#define EUSART2_CS_PB5 SILABS_DBUS_EUSART2_CS(0x1, 0x5) +#define EUSART2_CS_PB6 SILABS_DBUS_EUSART2_CS(0x1, 0x6) +#define EUSART2_CS_PB7 SILABS_DBUS_EUSART2_CS(0x1, 0x7) +#define EUSART2_CS_PB8 SILABS_DBUS_EUSART2_CS(0x1, 0x8) +#define EUSART2_CS_PB9 SILABS_DBUS_EUSART2_CS(0x1, 0x9) +#define EUSART2_CS_PB10 SILABS_DBUS_EUSART2_CS(0x1, 0xa) +#define EUSART2_CS_PB11 SILABS_DBUS_EUSART2_CS(0x1, 0xb) +#define EUSART2_CS_PB12 SILABS_DBUS_EUSART2_CS(0x1, 0xc) +#define EUSART2_CS_PB13 SILABS_DBUS_EUSART2_CS(0x1, 0xd) +#define EUSART2_CS_PB14 SILABS_DBUS_EUSART2_CS(0x1, 0xe) +#define EUSART2_CS_PB15 SILABS_DBUS_EUSART2_CS(0x1, 0xf) +#define EUSART2_CS_PC0 SILABS_DBUS_EUSART2_CS(0x2, 0x0) +#define EUSART2_CS_PC1 SILABS_DBUS_EUSART2_CS(0x2, 0x1) +#define EUSART2_CS_PC2 SILABS_DBUS_EUSART2_CS(0x2, 0x2) +#define EUSART2_CS_PC3 SILABS_DBUS_EUSART2_CS(0x2, 0x3) +#define EUSART2_CS_PC4 SILABS_DBUS_EUSART2_CS(0x2, 0x4) +#define EUSART2_CS_PC5 SILABS_DBUS_EUSART2_CS(0x2, 0x5) +#define EUSART2_CS_PC6 SILABS_DBUS_EUSART2_CS(0x2, 0x6) +#define EUSART2_CS_PC7 SILABS_DBUS_EUSART2_CS(0x2, 0x7) +#define EUSART2_CS_PC8 SILABS_DBUS_EUSART2_CS(0x2, 0x8) +#define EUSART2_CS_PC9 SILABS_DBUS_EUSART2_CS(0x2, 0x9) +#define EUSART2_CS_PC10 SILABS_DBUS_EUSART2_CS(0x2, 0xa) +#define EUSART2_CS_PC11 SILABS_DBUS_EUSART2_CS(0x2, 0xb) +#define EUSART2_CS_PC12 SILABS_DBUS_EUSART2_CS(0x2, 0xc) +#define EUSART2_CS_PC13 SILABS_DBUS_EUSART2_CS(0x2, 0xd) +#define EUSART2_CS_PC14 SILABS_DBUS_EUSART2_CS(0x2, 0xe) +#define EUSART2_CS_PC15 SILABS_DBUS_EUSART2_CS(0x2, 0xf) +#define EUSART2_CS_PD0 SILABS_DBUS_EUSART2_CS(0x3, 0x0) +#define EUSART2_CS_PD1 SILABS_DBUS_EUSART2_CS(0x3, 0x1) +#define EUSART2_CS_PD2 SILABS_DBUS_EUSART2_CS(0x3, 0x2) +#define EUSART2_CS_PD3 SILABS_DBUS_EUSART2_CS(0x3, 0x3) +#define EUSART2_CS_PD4 SILABS_DBUS_EUSART2_CS(0x3, 0x4) +#define EUSART2_CS_PD5 SILABS_DBUS_EUSART2_CS(0x3, 0x5) +#define EUSART2_CS_PD6 SILABS_DBUS_EUSART2_CS(0x3, 0x6) +#define EUSART2_CS_PD7 SILABS_DBUS_EUSART2_CS(0x3, 0x7) +#define EUSART2_CS_PD8 SILABS_DBUS_EUSART2_CS(0x3, 0x8) +#define EUSART2_CS_PD9 SILABS_DBUS_EUSART2_CS(0x3, 0x9) +#define EUSART2_CS_PD10 SILABS_DBUS_EUSART2_CS(0x3, 0xa) +#define EUSART2_CS_PD11 SILABS_DBUS_EUSART2_CS(0x3, 0xb) +#define EUSART2_CS_PD12 SILABS_DBUS_EUSART2_CS(0x3, 0xc) +#define EUSART2_CS_PD13 SILABS_DBUS_EUSART2_CS(0x3, 0xd) +#define EUSART2_CS_PD14 SILABS_DBUS_EUSART2_CS(0x3, 0xe) +#define EUSART2_CS_PD15 SILABS_DBUS_EUSART2_CS(0x3, 0xf) +#define EUSART2_RTS_PA0 SILABS_DBUS_EUSART2_RTS(0x0, 0x0) +#define EUSART2_RTS_PA1 SILABS_DBUS_EUSART2_RTS(0x0, 0x1) +#define EUSART2_RTS_PA2 SILABS_DBUS_EUSART2_RTS(0x0, 0x2) +#define EUSART2_RTS_PA3 SILABS_DBUS_EUSART2_RTS(0x0, 0x3) +#define EUSART2_RTS_PA4 SILABS_DBUS_EUSART2_RTS(0x0, 0x4) +#define EUSART2_RTS_PA5 SILABS_DBUS_EUSART2_RTS(0x0, 0x5) +#define EUSART2_RTS_PA6 SILABS_DBUS_EUSART2_RTS(0x0, 0x6) +#define EUSART2_RTS_PA7 SILABS_DBUS_EUSART2_RTS(0x0, 0x7) +#define EUSART2_RTS_PA8 SILABS_DBUS_EUSART2_RTS(0x0, 0x8) +#define EUSART2_RTS_PA9 SILABS_DBUS_EUSART2_RTS(0x0, 0x9) +#define EUSART2_RTS_PA10 SILABS_DBUS_EUSART2_RTS(0x0, 0xa) +#define EUSART2_RTS_PA11 SILABS_DBUS_EUSART2_RTS(0x0, 0xb) +#define EUSART2_RTS_PA12 SILABS_DBUS_EUSART2_RTS(0x0, 0xc) +#define EUSART2_RTS_PA13 SILABS_DBUS_EUSART2_RTS(0x0, 0xd) +#define EUSART2_RTS_PA14 SILABS_DBUS_EUSART2_RTS(0x0, 0xe) +#define EUSART2_RTS_PA15 SILABS_DBUS_EUSART2_RTS(0x0, 0xf) +#define EUSART2_RTS_PB0 SILABS_DBUS_EUSART2_RTS(0x1, 0x0) +#define EUSART2_RTS_PB1 SILABS_DBUS_EUSART2_RTS(0x1, 0x1) +#define EUSART2_RTS_PB2 SILABS_DBUS_EUSART2_RTS(0x1, 0x2) +#define EUSART2_RTS_PB3 SILABS_DBUS_EUSART2_RTS(0x1, 0x3) +#define EUSART2_RTS_PB4 SILABS_DBUS_EUSART2_RTS(0x1, 0x4) +#define EUSART2_RTS_PB5 SILABS_DBUS_EUSART2_RTS(0x1, 0x5) +#define EUSART2_RTS_PB6 SILABS_DBUS_EUSART2_RTS(0x1, 0x6) +#define EUSART2_RTS_PB7 SILABS_DBUS_EUSART2_RTS(0x1, 0x7) +#define EUSART2_RTS_PB8 SILABS_DBUS_EUSART2_RTS(0x1, 0x8) +#define EUSART2_RTS_PB9 SILABS_DBUS_EUSART2_RTS(0x1, 0x9) +#define EUSART2_RTS_PB10 SILABS_DBUS_EUSART2_RTS(0x1, 0xa) +#define EUSART2_RTS_PB11 SILABS_DBUS_EUSART2_RTS(0x1, 0xb) +#define EUSART2_RTS_PB12 SILABS_DBUS_EUSART2_RTS(0x1, 0xc) +#define EUSART2_RTS_PB13 SILABS_DBUS_EUSART2_RTS(0x1, 0xd) +#define EUSART2_RTS_PB14 SILABS_DBUS_EUSART2_RTS(0x1, 0xe) +#define EUSART2_RTS_PB15 SILABS_DBUS_EUSART2_RTS(0x1, 0xf) +#define EUSART2_RTS_PC0 SILABS_DBUS_EUSART2_RTS(0x2, 0x0) +#define EUSART2_RTS_PC1 SILABS_DBUS_EUSART2_RTS(0x2, 0x1) +#define EUSART2_RTS_PC2 SILABS_DBUS_EUSART2_RTS(0x2, 0x2) +#define EUSART2_RTS_PC3 SILABS_DBUS_EUSART2_RTS(0x2, 0x3) +#define EUSART2_RTS_PC4 SILABS_DBUS_EUSART2_RTS(0x2, 0x4) +#define EUSART2_RTS_PC5 SILABS_DBUS_EUSART2_RTS(0x2, 0x5) +#define EUSART2_RTS_PC6 SILABS_DBUS_EUSART2_RTS(0x2, 0x6) +#define EUSART2_RTS_PC7 SILABS_DBUS_EUSART2_RTS(0x2, 0x7) +#define EUSART2_RTS_PC8 SILABS_DBUS_EUSART2_RTS(0x2, 0x8) +#define EUSART2_RTS_PC9 SILABS_DBUS_EUSART2_RTS(0x2, 0x9) +#define EUSART2_RTS_PC10 SILABS_DBUS_EUSART2_RTS(0x2, 0xa) +#define EUSART2_RTS_PC11 SILABS_DBUS_EUSART2_RTS(0x2, 0xb) +#define EUSART2_RTS_PC12 SILABS_DBUS_EUSART2_RTS(0x2, 0xc) +#define EUSART2_RTS_PC13 SILABS_DBUS_EUSART2_RTS(0x2, 0xd) +#define EUSART2_RTS_PC14 SILABS_DBUS_EUSART2_RTS(0x2, 0xe) +#define EUSART2_RTS_PC15 SILABS_DBUS_EUSART2_RTS(0x2, 0xf) +#define EUSART2_RTS_PD0 SILABS_DBUS_EUSART2_RTS(0x3, 0x0) +#define EUSART2_RTS_PD1 SILABS_DBUS_EUSART2_RTS(0x3, 0x1) +#define EUSART2_RTS_PD2 SILABS_DBUS_EUSART2_RTS(0x3, 0x2) +#define EUSART2_RTS_PD3 SILABS_DBUS_EUSART2_RTS(0x3, 0x3) +#define EUSART2_RTS_PD4 SILABS_DBUS_EUSART2_RTS(0x3, 0x4) +#define EUSART2_RTS_PD5 SILABS_DBUS_EUSART2_RTS(0x3, 0x5) +#define EUSART2_RTS_PD6 SILABS_DBUS_EUSART2_RTS(0x3, 0x6) +#define EUSART2_RTS_PD7 SILABS_DBUS_EUSART2_RTS(0x3, 0x7) +#define EUSART2_RTS_PD8 SILABS_DBUS_EUSART2_RTS(0x3, 0x8) +#define EUSART2_RTS_PD9 SILABS_DBUS_EUSART2_RTS(0x3, 0x9) +#define EUSART2_RTS_PD10 SILABS_DBUS_EUSART2_RTS(0x3, 0xa) +#define EUSART2_RTS_PD11 SILABS_DBUS_EUSART2_RTS(0x3, 0xb) +#define EUSART2_RTS_PD12 SILABS_DBUS_EUSART2_RTS(0x3, 0xc) +#define EUSART2_RTS_PD13 SILABS_DBUS_EUSART2_RTS(0x3, 0xd) +#define EUSART2_RTS_PD14 SILABS_DBUS_EUSART2_RTS(0x3, 0xe) +#define EUSART2_RTS_PD15 SILABS_DBUS_EUSART2_RTS(0x3, 0xf) +#define EUSART2_RX_PA0 SILABS_DBUS_EUSART2_RX(0x0, 0x0) +#define EUSART2_RX_PA1 SILABS_DBUS_EUSART2_RX(0x0, 0x1) +#define EUSART2_RX_PA2 SILABS_DBUS_EUSART2_RX(0x0, 0x2) +#define EUSART2_RX_PA3 SILABS_DBUS_EUSART2_RX(0x0, 0x3) +#define EUSART2_RX_PA4 SILABS_DBUS_EUSART2_RX(0x0, 0x4) +#define EUSART2_RX_PA5 SILABS_DBUS_EUSART2_RX(0x0, 0x5) +#define EUSART2_RX_PA6 SILABS_DBUS_EUSART2_RX(0x0, 0x6) +#define EUSART2_RX_PA7 SILABS_DBUS_EUSART2_RX(0x0, 0x7) +#define EUSART2_RX_PA8 SILABS_DBUS_EUSART2_RX(0x0, 0x8) +#define EUSART2_RX_PA9 SILABS_DBUS_EUSART2_RX(0x0, 0x9) +#define EUSART2_RX_PA10 SILABS_DBUS_EUSART2_RX(0x0, 0xa) +#define EUSART2_RX_PA11 SILABS_DBUS_EUSART2_RX(0x0, 0xb) +#define EUSART2_RX_PA12 SILABS_DBUS_EUSART2_RX(0x0, 0xc) +#define EUSART2_RX_PA13 SILABS_DBUS_EUSART2_RX(0x0, 0xd) +#define EUSART2_RX_PA14 SILABS_DBUS_EUSART2_RX(0x0, 0xe) +#define EUSART2_RX_PA15 SILABS_DBUS_EUSART2_RX(0x0, 0xf) +#define EUSART2_RX_PB0 SILABS_DBUS_EUSART2_RX(0x1, 0x0) +#define EUSART2_RX_PB1 SILABS_DBUS_EUSART2_RX(0x1, 0x1) +#define EUSART2_RX_PB2 SILABS_DBUS_EUSART2_RX(0x1, 0x2) +#define EUSART2_RX_PB3 SILABS_DBUS_EUSART2_RX(0x1, 0x3) +#define EUSART2_RX_PB4 SILABS_DBUS_EUSART2_RX(0x1, 0x4) +#define EUSART2_RX_PB5 SILABS_DBUS_EUSART2_RX(0x1, 0x5) +#define EUSART2_RX_PB6 SILABS_DBUS_EUSART2_RX(0x1, 0x6) +#define EUSART2_RX_PB7 SILABS_DBUS_EUSART2_RX(0x1, 0x7) +#define EUSART2_RX_PB8 SILABS_DBUS_EUSART2_RX(0x1, 0x8) +#define EUSART2_RX_PB9 SILABS_DBUS_EUSART2_RX(0x1, 0x9) +#define EUSART2_RX_PB10 SILABS_DBUS_EUSART2_RX(0x1, 0xa) +#define EUSART2_RX_PB11 SILABS_DBUS_EUSART2_RX(0x1, 0xb) +#define EUSART2_RX_PB12 SILABS_DBUS_EUSART2_RX(0x1, 0xc) +#define EUSART2_RX_PB13 SILABS_DBUS_EUSART2_RX(0x1, 0xd) +#define EUSART2_RX_PB14 SILABS_DBUS_EUSART2_RX(0x1, 0xe) +#define EUSART2_RX_PB15 SILABS_DBUS_EUSART2_RX(0x1, 0xf) +#define EUSART2_RX_PC0 SILABS_DBUS_EUSART2_RX(0x2, 0x0) +#define EUSART2_RX_PC1 SILABS_DBUS_EUSART2_RX(0x2, 0x1) +#define EUSART2_RX_PC2 SILABS_DBUS_EUSART2_RX(0x2, 0x2) +#define EUSART2_RX_PC3 SILABS_DBUS_EUSART2_RX(0x2, 0x3) +#define EUSART2_RX_PC4 SILABS_DBUS_EUSART2_RX(0x2, 0x4) +#define EUSART2_RX_PC5 SILABS_DBUS_EUSART2_RX(0x2, 0x5) +#define EUSART2_RX_PC6 SILABS_DBUS_EUSART2_RX(0x2, 0x6) +#define EUSART2_RX_PC7 SILABS_DBUS_EUSART2_RX(0x2, 0x7) +#define EUSART2_RX_PC8 SILABS_DBUS_EUSART2_RX(0x2, 0x8) +#define EUSART2_RX_PC9 SILABS_DBUS_EUSART2_RX(0x2, 0x9) +#define EUSART2_RX_PC10 SILABS_DBUS_EUSART2_RX(0x2, 0xa) +#define EUSART2_RX_PC11 SILABS_DBUS_EUSART2_RX(0x2, 0xb) +#define EUSART2_RX_PC12 SILABS_DBUS_EUSART2_RX(0x2, 0xc) +#define EUSART2_RX_PC13 SILABS_DBUS_EUSART2_RX(0x2, 0xd) +#define EUSART2_RX_PC14 SILABS_DBUS_EUSART2_RX(0x2, 0xe) +#define EUSART2_RX_PC15 SILABS_DBUS_EUSART2_RX(0x2, 0xf) +#define EUSART2_RX_PD0 SILABS_DBUS_EUSART2_RX(0x3, 0x0) +#define EUSART2_RX_PD1 SILABS_DBUS_EUSART2_RX(0x3, 0x1) +#define EUSART2_RX_PD2 SILABS_DBUS_EUSART2_RX(0x3, 0x2) +#define EUSART2_RX_PD3 SILABS_DBUS_EUSART2_RX(0x3, 0x3) +#define EUSART2_RX_PD4 SILABS_DBUS_EUSART2_RX(0x3, 0x4) +#define EUSART2_RX_PD5 SILABS_DBUS_EUSART2_RX(0x3, 0x5) +#define EUSART2_RX_PD6 SILABS_DBUS_EUSART2_RX(0x3, 0x6) +#define EUSART2_RX_PD7 SILABS_DBUS_EUSART2_RX(0x3, 0x7) +#define EUSART2_RX_PD8 SILABS_DBUS_EUSART2_RX(0x3, 0x8) +#define EUSART2_RX_PD9 SILABS_DBUS_EUSART2_RX(0x3, 0x9) +#define EUSART2_RX_PD10 SILABS_DBUS_EUSART2_RX(0x3, 0xa) +#define EUSART2_RX_PD11 SILABS_DBUS_EUSART2_RX(0x3, 0xb) +#define EUSART2_RX_PD12 SILABS_DBUS_EUSART2_RX(0x3, 0xc) +#define EUSART2_RX_PD13 SILABS_DBUS_EUSART2_RX(0x3, 0xd) +#define EUSART2_RX_PD14 SILABS_DBUS_EUSART2_RX(0x3, 0xe) +#define EUSART2_RX_PD15 SILABS_DBUS_EUSART2_RX(0x3, 0xf) +#define EUSART2_SCLK_PA0 SILABS_DBUS_EUSART2_SCLK(0x0, 0x0) +#define EUSART2_SCLK_PA1 SILABS_DBUS_EUSART2_SCLK(0x0, 0x1) +#define EUSART2_SCLK_PA2 SILABS_DBUS_EUSART2_SCLK(0x0, 0x2) +#define EUSART2_SCLK_PA3 SILABS_DBUS_EUSART2_SCLK(0x0, 0x3) +#define EUSART2_SCLK_PA4 SILABS_DBUS_EUSART2_SCLK(0x0, 0x4) +#define EUSART2_SCLK_PA5 SILABS_DBUS_EUSART2_SCLK(0x0, 0x5) +#define EUSART2_SCLK_PA6 SILABS_DBUS_EUSART2_SCLK(0x0, 0x6) +#define EUSART2_SCLK_PA7 SILABS_DBUS_EUSART2_SCLK(0x0, 0x7) +#define EUSART2_SCLK_PA8 SILABS_DBUS_EUSART2_SCLK(0x0, 0x8) +#define EUSART2_SCLK_PA9 SILABS_DBUS_EUSART2_SCLK(0x0, 0x9) +#define EUSART2_SCLK_PA10 SILABS_DBUS_EUSART2_SCLK(0x0, 0xa) +#define EUSART2_SCLK_PA11 SILABS_DBUS_EUSART2_SCLK(0x0, 0xb) +#define EUSART2_SCLK_PA12 SILABS_DBUS_EUSART2_SCLK(0x0, 0xc) +#define EUSART2_SCLK_PA13 SILABS_DBUS_EUSART2_SCLK(0x0, 0xd) +#define EUSART2_SCLK_PA14 SILABS_DBUS_EUSART2_SCLK(0x0, 0xe) +#define EUSART2_SCLK_PA15 SILABS_DBUS_EUSART2_SCLK(0x0, 0xf) +#define EUSART2_SCLK_PB0 SILABS_DBUS_EUSART2_SCLK(0x1, 0x0) +#define EUSART2_SCLK_PB1 SILABS_DBUS_EUSART2_SCLK(0x1, 0x1) +#define EUSART2_SCLK_PB2 SILABS_DBUS_EUSART2_SCLK(0x1, 0x2) +#define EUSART2_SCLK_PB3 SILABS_DBUS_EUSART2_SCLK(0x1, 0x3) +#define EUSART2_SCLK_PB4 SILABS_DBUS_EUSART2_SCLK(0x1, 0x4) +#define EUSART2_SCLK_PB5 SILABS_DBUS_EUSART2_SCLK(0x1, 0x5) +#define EUSART2_SCLK_PB6 SILABS_DBUS_EUSART2_SCLK(0x1, 0x6) +#define EUSART2_SCLK_PB7 SILABS_DBUS_EUSART2_SCLK(0x1, 0x7) +#define EUSART2_SCLK_PB8 SILABS_DBUS_EUSART2_SCLK(0x1, 0x8) +#define EUSART2_SCLK_PB9 SILABS_DBUS_EUSART2_SCLK(0x1, 0x9) +#define EUSART2_SCLK_PB10 SILABS_DBUS_EUSART2_SCLK(0x1, 0xa) +#define EUSART2_SCLK_PB11 SILABS_DBUS_EUSART2_SCLK(0x1, 0xb) +#define EUSART2_SCLK_PB12 SILABS_DBUS_EUSART2_SCLK(0x1, 0xc) +#define EUSART2_SCLK_PB13 SILABS_DBUS_EUSART2_SCLK(0x1, 0xd) +#define EUSART2_SCLK_PB14 SILABS_DBUS_EUSART2_SCLK(0x1, 0xe) +#define EUSART2_SCLK_PB15 SILABS_DBUS_EUSART2_SCLK(0x1, 0xf) +#define EUSART2_SCLK_PC0 SILABS_DBUS_EUSART2_SCLK(0x2, 0x0) +#define EUSART2_SCLK_PC1 SILABS_DBUS_EUSART2_SCLK(0x2, 0x1) +#define EUSART2_SCLK_PC2 SILABS_DBUS_EUSART2_SCLK(0x2, 0x2) +#define EUSART2_SCLK_PC3 SILABS_DBUS_EUSART2_SCLK(0x2, 0x3) +#define EUSART2_SCLK_PC4 SILABS_DBUS_EUSART2_SCLK(0x2, 0x4) +#define EUSART2_SCLK_PC5 SILABS_DBUS_EUSART2_SCLK(0x2, 0x5) +#define EUSART2_SCLK_PC6 SILABS_DBUS_EUSART2_SCLK(0x2, 0x6) +#define EUSART2_SCLK_PC7 SILABS_DBUS_EUSART2_SCLK(0x2, 0x7) +#define EUSART2_SCLK_PC8 SILABS_DBUS_EUSART2_SCLK(0x2, 0x8) +#define EUSART2_SCLK_PC9 SILABS_DBUS_EUSART2_SCLK(0x2, 0x9) +#define EUSART2_SCLK_PC10 SILABS_DBUS_EUSART2_SCLK(0x2, 0xa) +#define EUSART2_SCLK_PC11 SILABS_DBUS_EUSART2_SCLK(0x2, 0xb) +#define EUSART2_SCLK_PC12 SILABS_DBUS_EUSART2_SCLK(0x2, 0xc) +#define EUSART2_SCLK_PC13 SILABS_DBUS_EUSART2_SCLK(0x2, 0xd) +#define EUSART2_SCLK_PC14 SILABS_DBUS_EUSART2_SCLK(0x2, 0xe) +#define EUSART2_SCLK_PC15 SILABS_DBUS_EUSART2_SCLK(0x2, 0xf) +#define EUSART2_SCLK_PD0 SILABS_DBUS_EUSART2_SCLK(0x3, 0x0) +#define EUSART2_SCLK_PD1 SILABS_DBUS_EUSART2_SCLK(0x3, 0x1) +#define EUSART2_SCLK_PD2 SILABS_DBUS_EUSART2_SCLK(0x3, 0x2) +#define EUSART2_SCLK_PD3 SILABS_DBUS_EUSART2_SCLK(0x3, 0x3) +#define EUSART2_SCLK_PD4 SILABS_DBUS_EUSART2_SCLK(0x3, 0x4) +#define EUSART2_SCLK_PD5 SILABS_DBUS_EUSART2_SCLK(0x3, 0x5) +#define EUSART2_SCLK_PD6 SILABS_DBUS_EUSART2_SCLK(0x3, 0x6) +#define EUSART2_SCLK_PD7 SILABS_DBUS_EUSART2_SCLK(0x3, 0x7) +#define EUSART2_SCLK_PD8 SILABS_DBUS_EUSART2_SCLK(0x3, 0x8) +#define EUSART2_SCLK_PD9 SILABS_DBUS_EUSART2_SCLK(0x3, 0x9) +#define EUSART2_SCLK_PD10 SILABS_DBUS_EUSART2_SCLK(0x3, 0xa) +#define EUSART2_SCLK_PD11 SILABS_DBUS_EUSART2_SCLK(0x3, 0xb) +#define EUSART2_SCLK_PD12 SILABS_DBUS_EUSART2_SCLK(0x3, 0xc) +#define EUSART2_SCLK_PD13 SILABS_DBUS_EUSART2_SCLK(0x3, 0xd) +#define EUSART2_SCLK_PD14 SILABS_DBUS_EUSART2_SCLK(0x3, 0xe) +#define EUSART2_SCLK_PD15 SILABS_DBUS_EUSART2_SCLK(0x3, 0xf) +#define EUSART2_TX_PA0 SILABS_DBUS_EUSART2_TX(0x0, 0x0) +#define EUSART2_TX_PA1 SILABS_DBUS_EUSART2_TX(0x0, 0x1) +#define EUSART2_TX_PA2 SILABS_DBUS_EUSART2_TX(0x0, 0x2) +#define EUSART2_TX_PA3 SILABS_DBUS_EUSART2_TX(0x0, 0x3) +#define EUSART2_TX_PA4 SILABS_DBUS_EUSART2_TX(0x0, 0x4) +#define EUSART2_TX_PA5 SILABS_DBUS_EUSART2_TX(0x0, 0x5) +#define EUSART2_TX_PA6 SILABS_DBUS_EUSART2_TX(0x0, 0x6) +#define EUSART2_TX_PA7 SILABS_DBUS_EUSART2_TX(0x0, 0x7) +#define EUSART2_TX_PA8 SILABS_DBUS_EUSART2_TX(0x0, 0x8) +#define EUSART2_TX_PA9 SILABS_DBUS_EUSART2_TX(0x0, 0x9) +#define EUSART2_TX_PA10 SILABS_DBUS_EUSART2_TX(0x0, 0xa) +#define EUSART2_TX_PA11 SILABS_DBUS_EUSART2_TX(0x0, 0xb) +#define EUSART2_TX_PA12 SILABS_DBUS_EUSART2_TX(0x0, 0xc) +#define EUSART2_TX_PA13 SILABS_DBUS_EUSART2_TX(0x0, 0xd) +#define EUSART2_TX_PA14 SILABS_DBUS_EUSART2_TX(0x0, 0xe) +#define EUSART2_TX_PA15 SILABS_DBUS_EUSART2_TX(0x0, 0xf) +#define EUSART2_TX_PB0 SILABS_DBUS_EUSART2_TX(0x1, 0x0) +#define EUSART2_TX_PB1 SILABS_DBUS_EUSART2_TX(0x1, 0x1) +#define EUSART2_TX_PB2 SILABS_DBUS_EUSART2_TX(0x1, 0x2) +#define EUSART2_TX_PB3 SILABS_DBUS_EUSART2_TX(0x1, 0x3) +#define EUSART2_TX_PB4 SILABS_DBUS_EUSART2_TX(0x1, 0x4) +#define EUSART2_TX_PB5 SILABS_DBUS_EUSART2_TX(0x1, 0x5) +#define EUSART2_TX_PB6 SILABS_DBUS_EUSART2_TX(0x1, 0x6) +#define EUSART2_TX_PB7 SILABS_DBUS_EUSART2_TX(0x1, 0x7) +#define EUSART2_TX_PB8 SILABS_DBUS_EUSART2_TX(0x1, 0x8) +#define EUSART2_TX_PB9 SILABS_DBUS_EUSART2_TX(0x1, 0x9) +#define EUSART2_TX_PB10 SILABS_DBUS_EUSART2_TX(0x1, 0xa) +#define EUSART2_TX_PB11 SILABS_DBUS_EUSART2_TX(0x1, 0xb) +#define EUSART2_TX_PB12 SILABS_DBUS_EUSART2_TX(0x1, 0xc) +#define EUSART2_TX_PB13 SILABS_DBUS_EUSART2_TX(0x1, 0xd) +#define EUSART2_TX_PB14 SILABS_DBUS_EUSART2_TX(0x1, 0xe) +#define EUSART2_TX_PB15 SILABS_DBUS_EUSART2_TX(0x1, 0xf) +#define EUSART2_TX_PC0 SILABS_DBUS_EUSART2_TX(0x2, 0x0) +#define EUSART2_TX_PC1 SILABS_DBUS_EUSART2_TX(0x2, 0x1) +#define EUSART2_TX_PC2 SILABS_DBUS_EUSART2_TX(0x2, 0x2) +#define EUSART2_TX_PC3 SILABS_DBUS_EUSART2_TX(0x2, 0x3) +#define EUSART2_TX_PC4 SILABS_DBUS_EUSART2_TX(0x2, 0x4) +#define EUSART2_TX_PC5 SILABS_DBUS_EUSART2_TX(0x2, 0x5) +#define EUSART2_TX_PC6 SILABS_DBUS_EUSART2_TX(0x2, 0x6) +#define EUSART2_TX_PC7 SILABS_DBUS_EUSART2_TX(0x2, 0x7) +#define EUSART2_TX_PC8 SILABS_DBUS_EUSART2_TX(0x2, 0x8) +#define EUSART2_TX_PC9 SILABS_DBUS_EUSART2_TX(0x2, 0x9) +#define EUSART2_TX_PC10 SILABS_DBUS_EUSART2_TX(0x2, 0xa) +#define EUSART2_TX_PC11 SILABS_DBUS_EUSART2_TX(0x2, 0xb) +#define EUSART2_TX_PC12 SILABS_DBUS_EUSART2_TX(0x2, 0xc) +#define EUSART2_TX_PC13 SILABS_DBUS_EUSART2_TX(0x2, 0xd) +#define EUSART2_TX_PC14 SILABS_DBUS_EUSART2_TX(0x2, 0xe) +#define EUSART2_TX_PC15 SILABS_DBUS_EUSART2_TX(0x2, 0xf) +#define EUSART2_TX_PD0 SILABS_DBUS_EUSART2_TX(0x3, 0x0) +#define EUSART2_TX_PD1 SILABS_DBUS_EUSART2_TX(0x3, 0x1) +#define EUSART2_TX_PD2 SILABS_DBUS_EUSART2_TX(0x3, 0x2) +#define EUSART2_TX_PD3 SILABS_DBUS_EUSART2_TX(0x3, 0x3) +#define EUSART2_TX_PD4 SILABS_DBUS_EUSART2_TX(0x3, 0x4) +#define EUSART2_TX_PD5 SILABS_DBUS_EUSART2_TX(0x3, 0x5) +#define EUSART2_TX_PD6 SILABS_DBUS_EUSART2_TX(0x3, 0x6) +#define EUSART2_TX_PD7 SILABS_DBUS_EUSART2_TX(0x3, 0x7) +#define EUSART2_TX_PD8 SILABS_DBUS_EUSART2_TX(0x3, 0x8) +#define EUSART2_TX_PD9 SILABS_DBUS_EUSART2_TX(0x3, 0x9) +#define EUSART2_TX_PD10 SILABS_DBUS_EUSART2_TX(0x3, 0xa) +#define EUSART2_TX_PD11 SILABS_DBUS_EUSART2_TX(0x3, 0xb) +#define EUSART2_TX_PD12 SILABS_DBUS_EUSART2_TX(0x3, 0xc) +#define EUSART2_TX_PD13 SILABS_DBUS_EUSART2_TX(0x3, 0xd) +#define EUSART2_TX_PD14 SILABS_DBUS_EUSART2_TX(0x3, 0xe) +#define EUSART2_TX_PD15 SILABS_DBUS_EUSART2_TX(0x3, 0xf) +#define EUSART2_CTS_PA0 SILABS_DBUS_EUSART2_CTS(0x0, 0x0) +#define EUSART2_CTS_PA1 SILABS_DBUS_EUSART2_CTS(0x0, 0x1) +#define EUSART2_CTS_PA2 SILABS_DBUS_EUSART2_CTS(0x0, 0x2) +#define EUSART2_CTS_PA3 SILABS_DBUS_EUSART2_CTS(0x0, 0x3) +#define EUSART2_CTS_PA4 SILABS_DBUS_EUSART2_CTS(0x0, 0x4) +#define EUSART2_CTS_PA5 SILABS_DBUS_EUSART2_CTS(0x0, 0x5) +#define EUSART2_CTS_PA6 SILABS_DBUS_EUSART2_CTS(0x0, 0x6) +#define EUSART2_CTS_PA7 SILABS_DBUS_EUSART2_CTS(0x0, 0x7) +#define EUSART2_CTS_PA8 SILABS_DBUS_EUSART2_CTS(0x0, 0x8) +#define EUSART2_CTS_PA9 SILABS_DBUS_EUSART2_CTS(0x0, 0x9) +#define EUSART2_CTS_PA10 SILABS_DBUS_EUSART2_CTS(0x0, 0xa) +#define EUSART2_CTS_PA11 SILABS_DBUS_EUSART2_CTS(0x0, 0xb) +#define EUSART2_CTS_PA12 SILABS_DBUS_EUSART2_CTS(0x0, 0xc) +#define EUSART2_CTS_PA13 SILABS_DBUS_EUSART2_CTS(0x0, 0xd) +#define EUSART2_CTS_PA14 SILABS_DBUS_EUSART2_CTS(0x0, 0xe) +#define EUSART2_CTS_PA15 SILABS_DBUS_EUSART2_CTS(0x0, 0xf) +#define EUSART2_CTS_PB0 SILABS_DBUS_EUSART2_CTS(0x1, 0x0) +#define EUSART2_CTS_PB1 SILABS_DBUS_EUSART2_CTS(0x1, 0x1) +#define EUSART2_CTS_PB2 SILABS_DBUS_EUSART2_CTS(0x1, 0x2) +#define EUSART2_CTS_PB3 SILABS_DBUS_EUSART2_CTS(0x1, 0x3) +#define EUSART2_CTS_PB4 SILABS_DBUS_EUSART2_CTS(0x1, 0x4) +#define EUSART2_CTS_PB5 SILABS_DBUS_EUSART2_CTS(0x1, 0x5) +#define EUSART2_CTS_PB6 SILABS_DBUS_EUSART2_CTS(0x1, 0x6) +#define EUSART2_CTS_PB7 SILABS_DBUS_EUSART2_CTS(0x1, 0x7) +#define EUSART2_CTS_PB8 SILABS_DBUS_EUSART2_CTS(0x1, 0x8) +#define EUSART2_CTS_PB9 SILABS_DBUS_EUSART2_CTS(0x1, 0x9) +#define EUSART2_CTS_PB10 SILABS_DBUS_EUSART2_CTS(0x1, 0xa) +#define EUSART2_CTS_PB11 SILABS_DBUS_EUSART2_CTS(0x1, 0xb) +#define EUSART2_CTS_PB12 SILABS_DBUS_EUSART2_CTS(0x1, 0xc) +#define EUSART2_CTS_PB13 SILABS_DBUS_EUSART2_CTS(0x1, 0xd) +#define EUSART2_CTS_PB14 SILABS_DBUS_EUSART2_CTS(0x1, 0xe) +#define EUSART2_CTS_PB15 SILABS_DBUS_EUSART2_CTS(0x1, 0xf) +#define EUSART2_CTS_PC0 SILABS_DBUS_EUSART2_CTS(0x2, 0x0) +#define EUSART2_CTS_PC1 SILABS_DBUS_EUSART2_CTS(0x2, 0x1) +#define EUSART2_CTS_PC2 SILABS_DBUS_EUSART2_CTS(0x2, 0x2) +#define EUSART2_CTS_PC3 SILABS_DBUS_EUSART2_CTS(0x2, 0x3) +#define EUSART2_CTS_PC4 SILABS_DBUS_EUSART2_CTS(0x2, 0x4) +#define EUSART2_CTS_PC5 SILABS_DBUS_EUSART2_CTS(0x2, 0x5) +#define EUSART2_CTS_PC6 SILABS_DBUS_EUSART2_CTS(0x2, 0x6) +#define EUSART2_CTS_PC7 SILABS_DBUS_EUSART2_CTS(0x2, 0x7) +#define EUSART2_CTS_PC8 SILABS_DBUS_EUSART2_CTS(0x2, 0x8) +#define EUSART2_CTS_PC9 SILABS_DBUS_EUSART2_CTS(0x2, 0x9) +#define EUSART2_CTS_PC10 SILABS_DBUS_EUSART2_CTS(0x2, 0xa) +#define EUSART2_CTS_PC11 SILABS_DBUS_EUSART2_CTS(0x2, 0xb) +#define EUSART2_CTS_PC12 SILABS_DBUS_EUSART2_CTS(0x2, 0xc) +#define EUSART2_CTS_PC13 SILABS_DBUS_EUSART2_CTS(0x2, 0xd) +#define EUSART2_CTS_PC14 SILABS_DBUS_EUSART2_CTS(0x2, 0xe) +#define EUSART2_CTS_PC15 SILABS_DBUS_EUSART2_CTS(0x2, 0xf) +#define EUSART2_CTS_PD0 SILABS_DBUS_EUSART2_CTS(0x3, 0x0) +#define EUSART2_CTS_PD1 SILABS_DBUS_EUSART2_CTS(0x3, 0x1) +#define EUSART2_CTS_PD2 SILABS_DBUS_EUSART2_CTS(0x3, 0x2) +#define EUSART2_CTS_PD3 SILABS_DBUS_EUSART2_CTS(0x3, 0x3) +#define EUSART2_CTS_PD4 SILABS_DBUS_EUSART2_CTS(0x3, 0x4) +#define EUSART2_CTS_PD5 SILABS_DBUS_EUSART2_CTS(0x3, 0x5) +#define EUSART2_CTS_PD6 SILABS_DBUS_EUSART2_CTS(0x3, 0x6) +#define EUSART2_CTS_PD7 SILABS_DBUS_EUSART2_CTS(0x3, 0x7) +#define EUSART2_CTS_PD8 SILABS_DBUS_EUSART2_CTS(0x3, 0x8) +#define EUSART2_CTS_PD9 SILABS_DBUS_EUSART2_CTS(0x3, 0x9) +#define EUSART2_CTS_PD10 SILABS_DBUS_EUSART2_CTS(0x3, 0xa) +#define EUSART2_CTS_PD11 SILABS_DBUS_EUSART2_CTS(0x3, 0xb) +#define EUSART2_CTS_PD12 SILABS_DBUS_EUSART2_CTS(0x3, 0xc) +#define EUSART2_CTS_PD13 SILABS_DBUS_EUSART2_CTS(0x3, 0xd) +#define EUSART2_CTS_PD14 SILABS_DBUS_EUSART2_CTS(0x3, 0xe) +#define EUSART2_CTS_PD15 SILABS_DBUS_EUSART2_CTS(0x3, 0xf) + +#define EUSART3_CS_PA0 SILABS_DBUS_EUSART3_CS(0x0, 0x0) +#define EUSART3_CS_PA1 SILABS_DBUS_EUSART3_CS(0x0, 0x1) +#define EUSART3_CS_PA2 SILABS_DBUS_EUSART3_CS(0x0, 0x2) +#define EUSART3_CS_PA3 SILABS_DBUS_EUSART3_CS(0x0, 0x3) +#define EUSART3_CS_PA4 SILABS_DBUS_EUSART3_CS(0x0, 0x4) +#define EUSART3_CS_PA5 SILABS_DBUS_EUSART3_CS(0x0, 0x5) +#define EUSART3_CS_PA6 SILABS_DBUS_EUSART3_CS(0x0, 0x6) +#define EUSART3_CS_PA7 SILABS_DBUS_EUSART3_CS(0x0, 0x7) +#define EUSART3_CS_PA8 SILABS_DBUS_EUSART3_CS(0x0, 0x8) +#define EUSART3_CS_PA9 SILABS_DBUS_EUSART3_CS(0x0, 0x9) +#define EUSART3_CS_PA10 SILABS_DBUS_EUSART3_CS(0x0, 0xa) +#define EUSART3_CS_PA11 SILABS_DBUS_EUSART3_CS(0x0, 0xb) +#define EUSART3_CS_PA12 SILABS_DBUS_EUSART3_CS(0x0, 0xc) +#define EUSART3_CS_PA13 SILABS_DBUS_EUSART3_CS(0x0, 0xd) +#define EUSART3_CS_PA14 SILABS_DBUS_EUSART3_CS(0x0, 0xe) +#define EUSART3_CS_PA15 SILABS_DBUS_EUSART3_CS(0x0, 0xf) +#define EUSART3_CS_PB0 SILABS_DBUS_EUSART3_CS(0x1, 0x0) +#define EUSART3_CS_PB1 SILABS_DBUS_EUSART3_CS(0x1, 0x1) +#define EUSART3_CS_PB2 SILABS_DBUS_EUSART3_CS(0x1, 0x2) +#define EUSART3_CS_PB3 SILABS_DBUS_EUSART3_CS(0x1, 0x3) +#define EUSART3_CS_PB4 SILABS_DBUS_EUSART3_CS(0x1, 0x4) +#define EUSART3_CS_PB5 SILABS_DBUS_EUSART3_CS(0x1, 0x5) +#define EUSART3_CS_PB6 SILABS_DBUS_EUSART3_CS(0x1, 0x6) +#define EUSART3_CS_PB7 SILABS_DBUS_EUSART3_CS(0x1, 0x7) +#define EUSART3_CS_PB8 SILABS_DBUS_EUSART3_CS(0x1, 0x8) +#define EUSART3_CS_PB9 SILABS_DBUS_EUSART3_CS(0x1, 0x9) +#define EUSART3_CS_PB10 SILABS_DBUS_EUSART3_CS(0x1, 0xa) +#define EUSART3_CS_PB11 SILABS_DBUS_EUSART3_CS(0x1, 0xb) +#define EUSART3_CS_PB12 SILABS_DBUS_EUSART3_CS(0x1, 0xc) +#define EUSART3_CS_PB13 SILABS_DBUS_EUSART3_CS(0x1, 0xd) +#define EUSART3_CS_PB14 SILABS_DBUS_EUSART3_CS(0x1, 0xe) +#define EUSART3_CS_PB15 SILABS_DBUS_EUSART3_CS(0x1, 0xf) +#define EUSART3_CS_PC0 SILABS_DBUS_EUSART3_CS(0x2, 0x0) +#define EUSART3_CS_PC1 SILABS_DBUS_EUSART3_CS(0x2, 0x1) +#define EUSART3_CS_PC2 SILABS_DBUS_EUSART3_CS(0x2, 0x2) +#define EUSART3_CS_PC3 SILABS_DBUS_EUSART3_CS(0x2, 0x3) +#define EUSART3_CS_PC4 SILABS_DBUS_EUSART3_CS(0x2, 0x4) +#define EUSART3_CS_PC5 SILABS_DBUS_EUSART3_CS(0x2, 0x5) +#define EUSART3_CS_PC6 SILABS_DBUS_EUSART3_CS(0x2, 0x6) +#define EUSART3_CS_PC7 SILABS_DBUS_EUSART3_CS(0x2, 0x7) +#define EUSART3_CS_PC8 SILABS_DBUS_EUSART3_CS(0x2, 0x8) +#define EUSART3_CS_PC9 SILABS_DBUS_EUSART3_CS(0x2, 0x9) +#define EUSART3_CS_PC10 SILABS_DBUS_EUSART3_CS(0x2, 0xa) +#define EUSART3_CS_PC11 SILABS_DBUS_EUSART3_CS(0x2, 0xb) +#define EUSART3_CS_PC12 SILABS_DBUS_EUSART3_CS(0x2, 0xc) +#define EUSART3_CS_PC13 SILABS_DBUS_EUSART3_CS(0x2, 0xd) +#define EUSART3_CS_PC14 SILABS_DBUS_EUSART3_CS(0x2, 0xe) +#define EUSART3_CS_PC15 SILABS_DBUS_EUSART3_CS(0x2, 0xf) +#define EUSART3_CS_PD0 SILABS_DBUS_EUSART3_CS(0x3, 0x0) +#define EUSART3_CS_PD1 SILABS_DBUS_EUSART3_CS(0x3, 0x1) +#define EUSART3_CS_PD2 SILABS_DBUS_EUSART3_CS(0x3, 0x2) +#define EUSART3_CS_PD3 SILABS_DBUS_EUSART3_CS(0x3, 0x3) +#define EUSART3_CS_PD4 SILABS_DBUS_EUSART3_CS(0x3, 0x4) +#define EUSART3_CS_PD5 SILABS_DBUS_EUSART3_CS(0x3, 0x5) +#define EUSART3_CS_PD6 SILABS_DBUS_EUSART3_CS(0x3, 0x6) +#define EUSART3_CS_PD7 SILABS_DBUS_EUSART3_CS(0x3, 0x7) +#define EUSART3_CS_PD8 SILABS_DBUS_EUSART3_CS(0x3, 0x8) +#define EUSART3_CS_PD9 SILABS_DBUS_EUSART3_CS(0x3, 0x9) +#define EUSART3_CS_PD10 SILABS_DBUS_EUSART3_CS(0x3, 0xa) +#define EUSART3_CS_PD11 SILABS_DBUS_EUSART3_CS(0x3, 0xb) +#define EUSART3_CS_PD12 SILABS_DBUS_EUSART3_CS(0x3, 0xc) +#define EUSART3_CS_PD13 SILABS_DBUS_EUSART3_CS(0x3, 0xd) +#define EUSART3_CS_PD14 SILABS_DBUS_EUSART3_CS(0x3, 0xe) +#define EUSART3_CS_PD15 SILABS_DBUS_EUSART3_CS(0x3, 0xf) +#define EUSART3_RTS_PA0 SILABS_DBUS_EUSART3_RTS(0x0, 0x0) +#define EUSART3_RTS_PA1 SILABS_DBUS_EUSART3_RTS(0x0, 0x1) +#define EUSART3_RTS_PA2 SILABS_DBUS_EUSART3_RTS(0x0, 0x2) +#define EUSART3_RTS_PA3 SILABS_DBUS_EUSART3_RTS(0x0, 0x3) +#define EUSART3_RTS_PA4 SILABS_DBUS_EUSART3_RTS(0x0, 0x4) +#define EUSART3_RTS_PA5 SILABS_DBUS_EUSART3_RTS(0x0, 0x5) +#define EUSART3_RTS_PA6 SILABS_DBUS_EUSART3_RTS(0x0, 0x6) +#define EUSART3_RTS_PA7 SILABS_DBUS_EUSART3_RTS(0x0, 0x7) +#define EUSART3_RTS_PA8 SILABS_DBUS_EUSART3_RTS(0x0, 0x8) +#define EUSART3_RTS_PA9 SILABS_DBUS_EUSART3_RTS(0x0, 0x9) +#define EUSART3_RTS_PA10 SILABS_DBUS_EUSART3_RTS(0x0, 0xa) +#define EUSART3_RTS_PA11 SILABS_DBUS_EUSART3_RTS(0x0, 0xb) +#define EUSART3_RTS_PA12 SILABS_DBUS_EUSART3_RTS(0x0, 0xc) +#define EUSART3_RTS_PA13 SILABS_DBUS_EUSART3_RTS(0x0, 0xd) +#define EUSART3_RTS_PA14 SILABS_DBUS_EUSART3_RTS(0x0, 0xe) +#define EUSART3_RTS_PA15 SILABS_DBUS_EUSART3_RTS(0x0, 0xf) +#define EUSART3_RTS_PB0 SILABS_DBUS_EUSART3_RTS(0x1, 0x0) +#define EUSART3_RTS_PB1 SILABS_DBUS_EUSART3_RTS(0x1, 0x1) +#define EUSART3_RTS_PB2 SILABS_DBUS_EUSART3_RTS(0x1, 0x2) +#define EUSART3_RTS_PB3 SILABS_DBUS_EUSART3_RTS(0x1, 0x3) +#define EUSART3_RTS_PB4 SILABS_DBUS_EUSART3_RTS(0x1, 0x4) +#define EUSART3_RTS_PB5 SILABS_DBUS_EUSART3_RTS(0x1, 0x5) +#define EUSART3_RTS_PB6 SILABS_DBUS_EUSART3_RTS(0x1, 0x6) +#define EUSART3_RTS_PB7 SILABS_DBUS_EUSART3_RTS(0x1, 0x7) +#define EUSART3_RTS_PB8 SILABS_DBUS_EUSART3_RTS(0x1, 0x8) +#define EUSART3_RTS_PB9 SILABS_DBUS_EUSART3_RTS(0x1, 0x9) +#define EUSART3_RTS_PB10 SILABS_DBUS_EUSART3_RTS(0x1, 0xa) +#define EUSART3_RTS_PB11 SILABS_DBUS_EUSART3_RTS(0x1, 0xb) +#define EUSART3_RTS_PB12 SILABS_DBUS_EUSART3_RTS(0x1, 0xc) +#define EUSART3_RTS_PB13 SILABS_DBUS_EUSART3_RTS(0x1, 0xd) +#define EUSART3_RTS_PB14 SILABS_DBUS_EUSART3_RTS(0x1, 0xe) +#define EUSART3_RTS_PB15 SILABS_DBUS_EUSART3_RTS(0x1, 0xf) +#define EUSART3_RTS_PC0 SILABS_DBUS_EUSART3_RTS(0x2, 0x0) +#define EUSART3_RTS_PC1 SILABS_DBUS_EUSART3_RTS(0x2, 0x1) +#define EUSART3_RTS_PC2 SILABS_DBUS_EUSART3_RTS(0x2, 0x2) +#define EUSART3_RTS_PC3 SILABS_DBUS_EUSART3_RTS(0x2, 0x3) +#define EUSART3_RTS_PC4 SILABS_DBUS_EUSART3_RTS(0x2, 0x4) +#define EUSART3_RTS_PC5 SILABS_DBUS_EUSART3_RTS(0x2, 0x5) +#define EUSART3_RTS_PC6 SILABS_DBUS_EUSART3_RTS(0x2, 0x6) +#define EUSART3_RTS_PC7 SILABS_DBUS_EUSART3_RTS(0x2, 0x7) +#define EUSART3_RTS_PC8 SILABS_DBUS_EUSART3_RTS(0x2, 0x8) +#define EUSART3_RTS_PC9 SILABS_DBUS_EUSART3_RTS(0x2, 0x9) +#define EUSART3_RTS_PC10 SILABS_DBUS_EUSART3_RTS(0x2, 0xa) +#define EUSART3_RTS_PC11 SILABS_DBUS_EUSART3_RTS(0x2, 0xb) +#define EUSART3_RTS_PC12 SILABS_DBUS_EUSART3_RTS(0x2, 0xc) +#define EUSART3_RTS_PC13 SILABS_DBUS_EUSART3_RTS(0x2, 0xd) +#define EUSART3_RTS_PC14 SILABS_DBUS_EUSART3_RTS(0x2, 0xe) +#define EUSART3_RTS_PC15 SILABS_DBUS_EUSART3_RTS(0x2, 0xf) +#define EUSART3_RTS_PD0 SILABS_DBUS_EUSART3_RTS(0x3, 0x0) +#define EUSART3_RTS_PD1 SILABS_DBUS_EUSART3_RTS(0x3, 0x1) +#define EUSART3_RTS_PD2 SILABS_DBUS_EUSART3_RTS(0x3, 0x2) +#define EUSART3_RTS_PD3 SILABS_DBUS_EUSART3_RTS(0x3, 0x3) +#define EUSART3_RTS_PD4 SILABS_DBUS_EUSART3_RTS(0x3, 0x4) +#define EUSART3_RTS_PD5 SILABS_DBUS_EUSART3_RTS(0x3, 0x5) +#define EUSART3_RTS_PD6 SILABS_DBUS_EUSART3_RTS(0x3, 0x6) +#define EUSART3_RTS_PD7 SILABS_DBUS_EUSART3_RTS(0x3, 0x7) +#define EUSART3_RTS_PD8 SILABS_DBUS_EUSART3_RTS(0x3, 0x8) +#define EUSART3_RTS_PD9 SILABS_DBUS_EUSART3_RTS(0x3, 0x9) +#define EUSART3_RTS_PD10 SILABS_DBUS_EUSART3_RTS(0x3, 0xa) +#define EUSART3_RTS_PD11 SILABS_DBUS_EUSART3_RTS(0x3, 0xb) +#define EUSART3_RTS_PD12 SILABS_DBUS_EUSART3_RTS(0x3, 0xc) +#define EUSART3_RTS_PD13 SILABS_DBUS_EUSART3_RTS(0x3, 0xd) +#define EUSART3_RTS_PD14 SILABS_DBUS_EUSART3_RTS(0x3, 0xe) +#define EUSART3_RTS_PD15 SILABS_DBUS_EUSART3_RTS(0x3, 0xf) +#define EUSART3_RX_PA0 SILABS_DBUS_EUSART3_RX(0x0, 0x0) +#define EUSART3_RX_PA1 SILABS_DBUS_EUSART3_RX(0x0, 0x1) +#define EUSART3_RX_PA2 SILABS_DBUS_EUSART3_RX(0x0, 0x2) +#define EUSART3_RX_PA3 SILABS_DBUS_EUSART3_RX(0x0, 0x3) +#define EUSART3_RX_PA4 SILABS_DBUS_EUSART3_RX(0x0, 0x4) +#define EUSART3_RX_PA5 SILABS_DBUS_EUSART3_RX(0x0, 0x5) +#define EUSART3_RX_PA6 SILABS_DBUS_EUSART3_RX(0x0, 0x6) +#define EUSART3_RX_PA7 SILABS_DBUS_EUSART3_RX(0x0, 0x7) +#define EUSART3_RX_PA8 SILABS_DBUS_EUSART3_RX(0x0, 0x8) +#define EUSART3_RX_PA9 SILABS_DBUS_EUSART3_RX(0x0, 0x9) +#define EUSART3_RX_PA10 SILABS_DBUS_EUSART3_RX(0x0, 0xa) +#define EUSART3_RX_PA11 SILABS_DBUS_EUSART3_RX(0x0, 0xb) +#define EUSART3_RX_PA12 SILABS_DBUS_EUSART3_RX(0x0, 0xc) +#define EUSART3_RX_PA13 SILABS_DBUS_EUSART3_RX(0x0, 0xd) +#define EUSART3_RX_PA14 SILABS_DBUS_EUSART3_RX(0x0, 0xe) +#define EUSART3_RX_PA15 SILABS_DBUS_EUSART3_RX(0x0, 0xf) +#define EUSART3_RX_PB0 SILABS_DBUS_EUSART3_RX(0x1, 0x0) +#define EUSART3_RX_PB1 SILABS_DBUS_EUSART3_RX(0x1, 0x1) +#define EUSART3_RX_PB2 SILABS_DBUS_EUSART3_RX(0x1, 0x2) +#define EUSART3_RX_PB3 SILABS_DBUS_EUSART3_RX(0x1, 0x3) +#define EUSART3_RX_PB4 SILABS_DBUS_EUSART3_RX(0x1, 0x4) +#define EUSART3_RX_PB5 SILABS_DBUS_EUSART3_RX(0x1, 0x5) +#define EUSART3_RX_PB6 SILABS_DBUS_EUSART3_RX(0x1, 0x6) +#define EUSART3_RX_PB7 SILABS_DBUS_EUSART3_RX(0x1, 0x7) +#define EUSART3_RX_PB8 SILABS_DBUS_EUSART3_RX(0x1, 0x8) +#define EUSART3_RX_PB9 SILABS_DBUS_EUSART3_RX(0x1, 0x9) +#define EUSART3_RX_PB10 SILABS_DBUS_EUSART3_RX(0x1, 0xa) +#define EUSART3_RX_PB11 SILABS_DBUS_EUSART3_RX(0x1, 0xb) +#define EUSART3_RX_PB12 SILABS_DBUS_EUSART3_RX(0x1, 0xc) +#define EUSART3_RX_PB13 SILABS_DBUS_EUSART3_RX(0x1, 0xd) +#define EUSART3_RX_PB14 SILABS_DBUS_EUSART3_RX(0x1, 0xe) +#define EUSART3_RX_PB15 SILABS_DBUS_EUSART3_RX(0x1, 0xf) +#define EUSART3_RX_PC0 SILABS_DBUS_EUSART3_RX(0x2, 0x0) +#define EUSART3_RX_PC1 SILABS_DBUS_EUSART3_RX(0x2, 0x1) +#define EUSART3_RX_PC2 SILABS_DBUS_EUSART3_RX(0x2, 0x2) +#define EUSART3_RX_PC3 SILABS_DBUS_EUSART3_RX(0x2, 0x3) +#define EUSART3_RX_PC4 SILABS_DBUS_EUSART3_RX(0x2, 0x4) +#define EUSART3_RX_PC5 SILABS_DBUS_EUSART3_RX(0x2, 0x5) +#define EUSART3_RX_PC6 SILABS_DBUS_EUSART3_RX(0x2, 0x6) +#define EUSART3_RX_PC7 SILABS_DBUS_EUSART3_RX(0x2, 0x7) +#define EUSART3_RX_PC8 SILABS_DBUS_EUSART3_RX(0x2, 0x8) +#define EUSART3_RX_PC9 SILABS_DBUS_EUSART3_RX(0x2, 0x9) +#define EUSART3_RX_PC10 SILABS_DBUS_EUSART3_RX(0x2, 0xa) +#define EUSART3_RX_PC11 SILABS_DBUS_EUSART3_RX(0x2, 0xb) +#define EUSART3_RX_PC12 SILABS_DBUS_EUSART3_RX(0x2, 0xc) +#define EUSART3_RX_PC13 SILABS_DBUS_EUSART3_RX(0x2, 0xd) +#define EUSART3_RX_PC14 SILABS_DBUS_EUSART3_RX(0x2, 0xe) +#define EUSART3_RX_PC15 SILABS_DBUS_EUSART3_RX(0x2, 0xf) +#define EUSART3_RX_PD0 SILABS_DBUS_EUSART3_RX(0x3, 0x0) +#define EUSART3_RX_PD1 SILABS_DBUS_EUSART3_RX(0x3, 0x1) +#define EUSART3_RX_PD2 SILABS_DBUS_EUSART3_RX(0x3, 0x2) +#define EUSART3_RX_PD3 SILABS_DBUS_EUSART3_RX(0x3, 0x3) +#define EUSART3_RX_PD4 SILABS_DBUS_EUSART3_RX(0x3, 0x4) +#define EUSART3_RX_PD5 SILABS_DBUS_EUSART3_RX(0x3, 0x5) +#define EUSART3_RX_PD6 SILABS_DBUS_EUSART3_RX(0x3, 0x6) +#define EUSART3_RX_PD7 SILABS_DBUS_EUSART3_RX(0x3, 0x7) +#define EUSART3_RX_PD8 SILABS_DBUS_EUSART3_RX(0x3, 0x8) +#define EUSART3_RX_PD9 SILABS_DBUS_EUSART3_RX(0x3, 0x9) +#define EUSART3_RX_PD10 SILABS_DBUS_EUSART3_RX(0x3, 0xa) +#define EUSART3_RX_PD11 SILABS_DBUS_EUSART3_RX(0x3, 0xb) +#define EUSART3_RX_PD12 SILABS_DBUS_EUSART3_RX(0x3, 0xc) +#define EUSART3_RX_PD13 SILABS_DBUS_EUSART3_RX(0x3, 0xd) +#define EUSART3_RX_PD14 SILABS_DBUS_EUSART3_RX(0x3, 0xe) +#define EUSART3_RX_PD15 SILABS_DBUS_EUSART3_RX(0x3, 0xf) +#define EUSART3_SCLK_PA0 SILABS_DBUS_EUSART3_SCLK(0x0, 0x0) +#define EUSART3_SCLK_PA1 SILABS_DBUS_EUSART3_SCLK(0x0, 0x1) +#define EUSART3_SCLK_PA2 SILABS_DBUS_EUSART3_SCLK(0x0, 0x2) +#define EUSART3_SCLK_PA3 SILABS_DBUS_EUSART3_SCLK(0x0, 0x3) +#define EUSART3_SCLK_PA4 SILABS_DBUS_EUSART3_SCLK(0x0, 0x4) +#define EUSART3_SCLK_PA5 SILABS_DBUS_EUSART3_SCLK(0x0, 0x5) +#define EUSART3_SCLK_PA6 SILABS_DBUS_EUSART3_SCLK(0x0, 0x6) +#define EUSART3_SCLK_PA7 SILABS_DBUS_EUSART3_SCLK(0x0, 0x7) +#define EUSART3_SCLK_PA8 SILABS_DBUS_EUSART3_SCLK(0x0, 0x8) +#define EUSART3_SCLK_PA9 SILABS_DBUS_EUSART3_SCLK(0x0, 0x9) +#define EUSART3_SCLK_PA10 SILABS_DBUS_EUSART3_SCLK(0x0, 0xa) +#define EUSART3_SCLK_PA11 SILABS_DBUS_EUSART3_SCLK(0x0, 0xb) +#define EUSART3_SCLK_PA12 SILABS_DBUS_EUSART3_SCLK(0x0, 0xc) +#define EUSART3_SCLK_PA13 SILABS_DBUS_EUSART3_SCLK(0x0, 0xd) +#define EUSART3_SCLK_PA14 SILABS_DBUS_EUSART3_SCLK(0x0, 0xe) +#define EUSART3_SCLK_PA15 SILABS_DBUS_EUSART3_SCLK(0x0, 0xf) +#define EUSART3_SCLK_PB0 SILABS_DBUS_EUSART3_SCLK(0x1, 0x0) +#define EUSART3_SCLK_PB1 SILABS_DBUS_EUSART3_SCLK(0x1, 0x1) +#define EUSART3_SCLK_PB2 SILABS_DBUS_EUSART3_SCLK(0x1, 0x2) +#define EUSART3_SCLK_PB3 SILABS_DBUS_EUSART3_SCLK(0x1, 0x3) +#define EUSART3_SCLK_PB4 SILABS_DBUS_EUSART3_SCLK(0x1, 0x4) +#define EUSART3_SCLK_PB5 SILABS_DBUS_EUSART3_SCLK(0x1, 0x5) +#define EUSART3_SCLK_PB6 SILABS_DBUS_EUSART3_SCLK(0x1, 0x6) +#define EUSART3_SCLK_PB7 SILABS_DBUS_EUSART3_SCLK(0x1, 0x7) +#define EUSART3_SCLK_PB8 SILABS_DBUS_EUSART3_SCLK(0x1, 0x8) +#define EUSART3_SCLK_PB9 SILABS_DBUS_EUSART3_SCLK(0x1, 0x9) +#define EUSART3_SCLK_PB10 SILABS_DBUS_EUSART3_SCLK(0x1, 0xa) +#define EUSART3_SCLK_PB11 SILABS_DBUS_EUSART3_SCLK(0x1, 0xb) +#define EUSART3_SCLK_PB12 SILABS_DBUS_EUSART3_SCLK(0x1, 0xc) +#define EUSART3_SCLK_PB13 SILABS_DBUS_EUSART3_SCLK(0x1, 0xd) +#define EUSART3_SCLK_PB14 SILABS_DBUS_EUSART3_SCLK(0x1, 0xe) +#define EUSART3_SCLK_PB15 SILABS_DBUS_EUSART3_SCLK(0x1, 0xf) +#define EUSART3_SCLK_PC0 SILABS_DBUS_EUSART3_SCLK(0x2, 0x0) +#define EUSART3_SCLK_PC1 SILABS_DBUS_EUSART3_SCLK(0x2, 0x1) +#define EUSART3_SCLK_PC2 SILABS_DBUS_EUSART3_SCLK(0x2, 0x2) +#define EUSART3_SCLK_PC3 SILABS_DBUS_EUSART3_SCLK(0x2, 0x3) +#define EUSART3_SCLK_PC4 SILABS_DBUS_EUSART3_SCLK(0x2, 0x4) +#define EUSART3_SCLK_PC5 SILABS_DBUS_EUSART3_SCLK(0x2, 0x5) +#define EUSART3_SCLK_PC6 SILABS_DBUS_EUSART3_SCLK(0x2, 0x6) +#define EUSART3_SCLK_PC7 SILABS_DBUS_EUSART3_SCLK(0x2, 0x7) +#define EUSART3_SCLK_PC8 SILABS_DBUS_EUSART3_SCLK(0x2, 0x8) +#define EUSART3_SCLK_PC9 SILABS_DBUS_EUSART3_SCLK(0x2, 0x9) +#define EUSART3_SCLK_PC10 SILABS_DBUS_EUSART3_SCLK(0x2, 0xa) +#define EUSART3_SCLK_PC11 SILABS_DBUS_EUSART3_SCLK(0x2, 0xb) +#define EUSART3_SCLK_PC12 SILABS_DBUS_EUSART3_SCLK(0x2, 0xc) +#define EUSART3_SCLK_PC13 SILABS_DBUS_EUSART3_SCLK(0x2, 0xd) +#define EUSART3_SCLK_PC14 SILABS_DBUS_EUSART3_SCLK(0x2, 0xe) +#define EUSART3_SCLK_PC15 SILABS_DBUS_EUSART3_SCLK(0x2, 0xf) +#define EUSART3_SCLK_PD0 SILABS_DBUS_EUSART3_SCLK(0x3, 0x0) +#define EUSART3_SCLK_PD1 SILABS_DBUS_EUSART3_SCLK(0x3, 0x1) +#define EUSART3_SCLK_PD2 SILABS_DBUS_EUSART3_SCLK(0x3, 0x2) +#define EUSART3_SCLK_PD3 SILABS_DBUS_EUSART3_SCLK(0x3, 0x3) +#define EUSART3_SCLK_PD4 SILABS_DBUS_EUSART3_SCLK(0x3, 0x4) +#define EUSART3_SCLK_PD5 SILABS_DBUS_EUSART3_SCLK(0x3, 0x5) +#define EUSART3_SCLK_PD6 SILABS_DBUS_EUSART3_SCLK(0x3, 0x6) +#define EUSART3_SCLK_PD7 SILABS_DBUS_EUSART3_SCLK(0x3, 0x7) +#define EUSART3_SCLK_PD8 SILABS_DBUS_EUSART3_SCLK(0x3, 0x8) +#define EUSART3_SCLK_PD9 SILABS_DBUS_EUSART3_SCLK(0x3, 0x9) +#define EUSART3_SCLK_PD10 SILABS_DBUS_EUSART3_SCLK(0x3, 0xa) +#define EUSART3_SCLK_PD11 SILABS_DBUS_EUSART3_SCLK(0x3, 0xb) +#define EUSART3_SCLK_PD12 SILABS_DBUS_EUSART3_SCLK(0x3, 0xc) +#define EUSART3_SCLK_PD13 SILABS_DBUS_EUSART3_SCLK(0x3, 0xd) +#define EUSART3_SCLK_PD14 SILABS_DBUS_EUSART3_SCLK(0x3, 0xe) +#define EUSART3_SCLK_PD15 SILABS_DBUS_EUSART3_SCLK(0x3, 0xf) +#define EUSART3_TX_PA0 SILABS_DBUS_EUSART3_TX(0x0, 0x0) +#define EUSART3_TX_PA1 SILABS_DBUS_EUSART3_TX(0x0, 0x1) +#define EUSART3_TX_PA2 SILABS_DBUS_EUSART3_TX(0x0, 0x2) +#define EUSART3_TX_PA3 SILABS_DBUS_EUSART3_TX(0x0, 0x3) +#define EUSART3_TX_PA4 SILABS_DBUS_EUSART3_TX(0x0, 0x4) +#define EUSART3_TX_PA5 SILABS_DBUS_EUSART3_TX(0x0, 0x5) +#define EUSART3_TX_PA6 SILABS_DBUS_EUSART3_TX(0x0, 0x6) +#define EUSART3_TX_PA7 SILABS_DBUS_EUSART3_TX(0x0, 0x7) +#define EUSART3_TX_PA8 SILABS_DBUS_EUSART3_TX(0x0, 0x8) +#define EUSART3_TX_PA9 SILABS_DBUS_EUSART3_TX(0x0, 0x9) +#define EUSART3_TX_PA10 SILABS_DBUS_EUSART3_TX(0x0, 0xa) +#define EUSART3_TX_PA11 SILABS_DBUS_EUSART3_TX(0x0, 0xb) +#define EUSART3_TX_PA12 SILABS_DBUS_EUSART3_TX(0x0, 0xc) +#define EUSART3_TX_PA13 SILABS_DBUS_EUSART3_TX(0x0, 0xd) +#define EUSART3_TX_PA14 SILABS_DBUS_EUSART3_TX(0x0, 0xe) +#define EUSART3_TX_PA15 SILABS_DBUS_EUSART3_TX(0x0, 0xf) +#define EUSART3_TX_PB0 SILABS_DBUS_EUSART3_TX(0x1, 0x0) +#define EUSART3_TX_PB1 SILABS_DBUS_EUSART3_TX(0x1, 0x1) +#define EUSART3_TX_PB2 SILABS_DBUS_EUSART3_TX(0x1, 0x2) +#define EUSART3_TX_PB3 SILABS_DBUS_EUSART3_TX(0x1, 0x3) +#define EUSART3_TX_PB4 SILABS_DBUS_EUSART3_TX(0x1, 0x4) +#define EUSART3_TX_PB5 SILABS_DBUS_EUSART3_TX(0x1, 0x5) +#define EUSART3_TX_PB6 SILABS_DBUS_EUSART3_TX(0x1, 0x6) +#define EUSART3_TX_PB7 SILABS_DBUS_EUSART3_TX(0x1, 0x7) +#define EUSART3_TX_PB8 SILABS_DBUS_EUSART3_TX(0x1, 0x8) +#define EUSART3_TX_PB9 SILABS_DBUS_EUSART3_TX(0x1, 0x9) +#define EUSART3_TX_PB10 SILABS_DBUS_EUSART3_TX(0x1, 0xa) +#define EUSART3_TX_PB11 SILABS_DBUS_EUSART3_TX(0x1, 0xb) +#define EUSART3_TX_PB12 SILABS_DBUS_EUSART3_TX(0x1, 0xc) +#define EUSART3_TX_PB13 SILABS_DBUS_EUSART3_TX(0x1, 0xd) +#define EUSART3_TX_PB14 SILABS_DBUS_EUSART3_TX(0x1, 0xe) +#define EUSART3_TX_PB15 SILABS_DBUS_EUSART3_TX(0x1, 0xf) +#define EUSART3_TX_PC0 SILABS_DBUS_EUSART3_TX(0x2, 0x0) +#define EUSART3_TX_PC1 SILABS_DBUS_EUSART3_TX(0x2, 0x1) +#define EUSART3_TX_PC2 SILABS_DBUS_EUSART3_TX(0x2, 0x2) +#define EUSART3_TX_PC3 SILABS_DBUS_EUSART3_TX(0x2, 0x3) +#define EUSART3_TX_PC4 SILABS_DBUS_EUSART3_TX(0x2, 0x4) +#define EUSART3_TX_PC5 SILABS_DBUS_EUSART3_TX(0x2, 0x5) +#define EUSART3_TX_PC6 SILABS_DBUS_EUSART3_TX(0x2, 0x6) +#define EUSART3_TX_PC7 SILABS_DBUS_EUSART3_TX(0x2, 0x7) +#define EUSART3_TX_PC8 SILABS_DBUS_EUSART3_TX(0x2, 0x8) +#define EUSART3_TX_PC9 SILABS_DBUS_EUSART3_TX(0x2, 0x9) +#define EUSART3_TX_PC10 SILABS_DBUS_EUSART3_TX(0x2, 0xa) +#define EUSART3_TX_PC11 SILABS_DBUS_EUSART3_TX(0x2, 0xb) +#define EUSART3_TX_PC12 SILABS_DBUS_EUSART3_TX(0x2, 0xc) +#define EUSART3_TX_PC13 SILABS_DBUS_EUSART3_TX(0x2, 0xd) +#define EUSART3_TX_PC14 SILABS_DBUS_EUSART3_TX(0x2, 0xe) +#define EUSART3_TX_PC15 SILABS_DBUS_EUSART3_TX(0x2, 0xf) +#define EUSART3_TX_PD0 SILABS_DBUS_EUSART3_TX(0x3, 0x0) +#define EUSART3_TX_PD1 SILABS_DBUS_EUSART3_TX(0x3, 0x1) +#define EUSART3_TX_PD2 SILABS_DBUS_EUSART3_TX(0x3, 0x2) +#define EUSART3_TX_PD3 SILABS_DBUS_EUSART3_TX(0x3, 0x3) +#define EUSART3_TX_PD4 SILABS_DBUS_EUSART3_TX(0x3, 0x4) +#define EUSART3_TX_PD5 SILABS_DBUS_EUSART3_TX(0x3, 0x5) +#define EUSART3_TX_PD6 SILABS_DBUS_EUSART3_TX(0x3, 0x6) +#define EUSART3_TX_PD7 SILABS_DBUS_EUSART3_TX(0x3, 0x7) +#define EUSART3_TX_PD8 SILABS_DBUS_EUSART3_TX(0x3, 0x8) +#define EUSART3_TX_PD9 SILABS_DBUS_EUSART3_TX(0x3, 0x9) +#define EUSART3_TX_PD10 SILABS_DBUS_EUSART3_TX(0x3, 0xa) +#define EUSART3_TX_PD11 SILABS_DBUS_EUSART3_TX(0x3, 0xb) +#define EUSART3_TX_PD12 SILABS_DBUS_EUSART3_TX(0x3, 0xc) +#define EUSART3_TX_PD13 SILABS_DBUS_EUSART3_TX(0x3, 0xd) +#define EUSART3_TX_PD14 SILABS_DBUS_EUSART3_TX(0x3, 0xe) +#define EUSART3_TX_PD15 SILABS_DBUS_EUSART3_TX(0x3, 0xf) +#define EUSART3_CTS_PA0 SILABS_DBUS_EUSART3_CTS(0x0, 0x0) +#define EUSART3_CTS_PA1 SILABS_DBUS_EUSART3_CTS(0x0, 0x1) +#define EUSART3_CTS_PA2 SILABS_DBUS_EUSART3_CTS(0x0, 0x2) +#define EUSART3_CTS_PA3 SILABS_DBUS_EUSART3_CTS(0x0, 0x3) +#define EUSART3_CTS_PA4 SILABS_DBUS_EUSART3_CTS(0x0, 0x4) +#define EUSART3_CTS_PA5 SILABS_DBUS_EUSART3_CTS(0x0, 0x5) +#define EUSART3_CTS_PA6 SILABS_DBUS_EUSART3_CTS(0x0, 0x6) +#define EUSART3_CTS_PA7 SILABS_DBUS_EUSART3_CTS(0x0, 0x7) +#define EUSART3_CTS_PA8 SILABS_DBUS_EUSART3_CTS(0x0, 0x8) +#define EUSART3_CTS_PA9 SILABS_DBUS_EUSART3_CTS(0x0, 0x9) +#define EUSART3_CTS_PA10 SILABS_DBUS_EUSART3_CTS(0x0, 0xa) +#define EUSART3_CTS_PA11 SILABS_DBUS_EUSART3_CTS(0x0, 0xb) +#define EUSART3_CTS_PA12 SILABS_DBUS_EUSART3_CTS(0x0, 0xc) +#define EUSART3_CTS_PA13 SILABS_DBUS_EUSART3_CTS(0x0, 0xd) +#define EUSART3_CTS_PA14 SILABS_DBUS_EUSART3_CTS(0x0, 0xe) +#define EUSART3_CTS_PA15 SILABS_DBUS_EUSART3_CTS(0x0, 0xf) +#define EUSART3_CTS_PB0 SILABS_DBUS_EUSART3_CTS(0x1, 0x0) +#define EUSART3_CTS_PB1 SILABS_DBUS_EUSART3_CTS(0x1, 0x1) +#define EUSART3_CTS_PB2 SILABS_DBUS_EUSART3_CTS(0x1, 0x2) +#define EUSART3_CTS_PB3 SILABS_DBUS_EUSART3_CTS(0x1, 0x3) +#define EUSART3_CTS_PB4 SILABS_DBUS_EUSART3_CTS(0x1, 0x4) +#define EUSART3_CTS_PB5 SILABS_DBUS_EUSART3_CTS(0x1, 0x5) +#define EUSART3_CTS_PB6 SILABS_DBUS_EUSART3_CTS(0x1, 0x6) +#define EUSART3_CTS_PB7 SILABS_DBUS_EUSART3_CTS(0x1, 0x7) +#define EUSART3_CTS_PB8 SILABS_DBUS_EUSART3_CTS(0x1, 0x8) +#define EUSART3_CTS_PB9 SILABS_DBUS_EUSART3_CTS(0x1, 0x9) +#define EUSART3_CTS_PB10 SILABS_DBUS_EUSART3_CTS(0x1, 0xa) +#define EUSART3_CTS_PB11 SILABS_DBUS_EUSART3_CTS(0x1, 0xb) +#define EUSART3_CTS_PB12 SILABS_DBUS_EUSART3_CTS(0x1, 0xc) +#define EUSART3_CTS_PB13 SILABS_DBUS_EUSART3_CTS(0x1, 0xd) +#define EUSART3_CTS_PB14 SILABS_DBUS_EUSART3_CTS(0x1, 0xe) +#define EUSART3_CTS_PB15 SILABS_DBUS_EUSART3_CTS(0x1, 0xf) +#define EUSART3_CTS_PC0 SILABS_DBUS_EUSART3_CTS(0x2, 0x0) +#define EUSART3_CTS_PC1 SILABS_DBUS_EUSART3_CTS(0x2, 0x1) +#define EUSART3_CTS_PC2 SILABS_DBUS_EUSART3_CTS(0x2, 0x2) +#define EUSART3_CTS_PC3 SILABS_DBUS_EUSART3_CTS(0x2, 0x3) +#define EUSART3_CTS_PC4 SILABS_DBUS_EUSART3_CTS(0x2, 0x4) +#define EUSART3_CTS_PC5 SILABS_DBUS_EUSART3_CTS(0x2, 0x5) +#define EUSART3_CTS_PC6 SILABS_DBUS_EUSART3_CTS(0x2, 0x6) +#define EUSART3_CTS_PC7 SILABS_DBUS_EUSART3_CTS(0x2, 0x7) +#define EUSART3_CTS_PC8 SILABS_DBUS_EUSART3_CTS(0x2, 0x8) +#define EUSART3_CTS_PC9 SILABS_DBUS_EUSART3_CTS(0x2, 0x9) +#define EUSART3_CTS_PC10 SILABS_DBUS_EUSART3_CTS(0x2, 0xa) +#define EUSART3_CTS_PC11 SILABS_DBUS_EUSART3_CTS(0x2, 0xb) +#define EUSART3_CTS_PC12 SILABS_DBUS_EUSART3_CTS(0x2, 0xc) +#define EUSART3_CTS_PC13 SILABS_DBUS_EUSART3_CTS(0x2, 0xd) +#define EUSART3_CTS_PC14 SILABS_DBUS_EUSART3_CTS(0x2, 0xe) +#define EUSART3_CTS_PC15 SILABS_DBUS_EUSART3_CTS(0x2, 0xf) +#define EUSART3_CTS_PD0 SILABS_DBUS_EUSART3_CTS(0x3, 0x0) +#define EUSART3_CTS_PD1 SILABS_DBUS_EUSART3_CTS(0x3, 0x1) +#define EUSART3_CTS_PD2 SILABS_DBUS_EUSART3_CTS(0x3, 0x2) +#define EUSART3_CTS_PD3 SILABS_DBUS_EUSART3_CTS(0x3, 0x3) +#define EUSART3_CTS_PD4 SILABS_DBUS_EUSART3_CTS(0x3, 0x4) +#define EUSART3_CTS_PD5 SILABS_DBUS_EUSART3_CTS(0x3, 0x5) +#define EUSART3_CTS_PD6 SILABS_DBUS_EUSART3_CTS(0x3, 0x6) +#define EUSART3_CTS_PD7 SILABS_DBUS_EUSART3_CTS(0x3, 0x7) +#define EUSART3_CTS_PD8 SILABS_DBUS_EUSART3_CTS(0x3, 0x8) +#define EUSART3_CTS_PD9 SILABS_DBUS_EUSART3_CTS(0x3, 0x9) +#define EUSART3_CTS_PD10 SILABS_DBUS_EUSART3_CTS(0x3, 0xa) +#define EUSART3_CTS_PD11 SILABS_DBUS_EUSART3_CTS(0x3, 0xb) +#define EUSART3_CTS_PD12 SILABS_DBUS_EUSART3_CTS(0x3, 0xc) +#define EUSART3_CTS_PD13 SILABS_DBUS_EUSART3_CTS(0x3, 0xd) +#define EUSART3_CTS_PD14 SILABS_DBUS_EUSART3_CTS(0x3, 0xe) +#define EUSART3_CTS_PD15 SILABS_DBUS_EUSART3_CTS(0x3, 0xf) + +#define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0) +#define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1) +#define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2) +#define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3) +#define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4) +#define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5) +#define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6) +#define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7) +#define PTI_DCLK_PC8 SILABS_DBUS_PTI_DCLK(0x2, 0x8) +#define PTI_DCLK_PC9 SILABS_DBUS_PTI_DCLK(0x2, 0x9) +#define PTI_DCLK_PC10 SILABS_DBUS_PTI_DCLK(0x2, 0xa) +#define PTI_DCLK_PC11 SILABS_DBUS_PTI_DCLK(0x2, 0xb) +#define PTI_DCLK_PC12 SILABS_DBUS_PTI_DCLK(0x2, 0xc) +#define PTI_DCLK_PC13 SILABS_DBUS_PTI_DCLK(0x2, 0xd) +#define PTI_DCLK_PC14 SILABS_DBUS_PTI_DCLK(0x2, 0xe) +#define PTI_DCLK_PC15 SILABS_DBUS_PTI_DCLK(0x2, 0xf) +#define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0) +#define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1) +#define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2) +#define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3) +#define PTI_DCLK_PD4 SILABS_DBUS_PTI_DCLK(0x3, 0x4) +#define PTI_DCLK_PD5 SILABS_DBUS_PTI_DCLK(0x3, 0x5) +#define PTI_DCLK_PD6 SILABS_DBUS_PTI_DCLK(0x3, 0x6) +#define PTI_DCLK_PD7 SILABS_DBUS_PTI_DCLK(0x3, 0x7) +#define PTI_DCLK_PD8 SILABS_DBUS_PTI_DCLK(0x3, 0x8) +#define PTI_DCLK_PD9 SILABS_DBUS_PTI_DCLK(0x3, 0x9) +#define PTI_DCLK_PD10 SILABS_DBUS_PTI_DCLK(0x3, 0xa) +#define PTI_DCLK_PD11 SILABS_DBUS_PTI_DCLK(0x3, 0xb) +#define PTI_DCLK_PD12 SILABS_DBUS_PTI_DCLK(0x3, 0xc) +#define PTI_DCLK_PD13 SILABS_DBUS_PTI_DCLK(0x3, 0xd) +#define PTI_DCLK_PD14 SILABS_DBUS_PTI_DCLK(0x3, 0xe) +#define PTI_DCLK_PD15 SILABS_DBUS_PTI_DCLK(0x3, 0xf) +#define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0) +#define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1) +#define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2) +#define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3) +#define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4) +#define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5) +#define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6) +#define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7) +#define PTI_DFRAME_PC8 SILABS_DBUS_PTI_DFRAME(0x2, 0x8) +#define PTI_DFRAME_PC9 SILABS_DBUS_PTI_DFRAME(0x2, 0x9) +#define PTI_DFRAME_PC10 SILABS_DBUS_PTI_DFRAME(0x2, 0xa) +#define PTI_DFRAME_PC11 SILABS_DBUS_PTI_DFRAME(0x2, 0xb) +#define PTI_DFRAME_PC12 SILABS_DBUS_PTI_DFRAME(0x2, 0xc) +#define PTI_DFRAME_PC13 SILABS_DBUS_PTI_DFRAME(0x2, 0xd) +#define PTI_DFRAME_PC14 SILABS_DBUS_PTI_DFRAME(0x2, 0xe) +#define PTI_DFRAME_PC15 SILABS_DBUS_PTI_DFRAME(0x2, 0xf) +#define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0) +#define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1) +#define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2) +#define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3) +#define PTI_DFRAME_PD4 SILABS_DBUS_PTI_DFRAME(0x3, 0x4) +#define PTI_DFRAME_PD5 SILABS_DBUS_PTI_DFRAME(0x3, 0x5) +#define PTI_DFRAME_PD6 SILABS_DBUS_PTI_DFRAME(0x3, 0x6) +#define PTI_DFRAME_PD7 SILABS_DBUS_PTI_DFRAME(0x3, 0x7) +#define PTI_DFRAME_PD8 SILABS_DBUS_PTI_DFRAME(0x3, 0x8) +#define PTI_DFRAME_PD9 SILABS_DBUS_PTI_DFRAME(0x3, 0x9) +#define PTI_DFRAME_PD10 SILABS_DBUS_PTI_DFRAME(0x3, 0xa) +#define PTI_DFRAME_PD11 SILABS_DBUS_PTI_DFRAME(0x3, 0xb) +#define PTI_DFRAME_PD12 SILABS_DBUS_PTI_DFRAME(0x3, 0xc) +#define PTI_DFRAME_PD13 SILABS_DBUS_PTI_DFRAME(0x3, 0xd) +#define PTI_DFRAME_PD14 SILABS_DBUS_PTI_DFRAME(0x3, 0xe) +#define PTI_DFRAME_PD15 SILABS_DBUS_PTI_DFRAME(0x3, 0xf) +#define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0) +#define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1) +#define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2) +#define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3) +#define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4) +#define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5) +#define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6) +#define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7) +#define PTI_DOUT_PC8 SILABS_DBUS_PTI_DOUT(0x2, 0x8) +#define PTI_DOUT_PC9 SILABS_DBUS_PTI_DOUT(0x2, 0x9) +#define PTI_DOUT_PC10 SILABS_DBUS_PTI_DOUT(0x2, 0xa) +#define PTI_DOUT_PC11 SILABS_DBUS_PTI_DOUT(0x2, 0xb) +#define PTI_DOUT_PC12 SILABS_DBUS_PTI_DOUT(0x2, 0xc) +#define PTI_DOUT_PC13 SILABS_DBUS_PTI_DOUT(0x2, 0xd) +#define PTI_DOUT_PC14 SILABS_DBUS_PTI_DOUT(0x2, 0xe) +#define PTI_DOUT_PC15 SILABS_DBUS_PTI_DOUT(0x2, 0xf) +#define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0) +#define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1) +#define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2) +#define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3) +#define PTI_DOUT_PD4 SILABS_DBUS_PTI_DOUT(0x3, 0x4) +#define PTI_DOUT_PD5 SILABS_DBUS_PTI_DOUT(0x3, 0x5) +#define PTI_DOUT_PD6 SILABS_DBUS_PTI_DOUT(0x3, 0x6) +#define PTI_DOUT_PD7 SILABS_DBUS_PTI_DOUT(0x3, 0x7) +#define PTI_DOUT_PD8 SILABS_DBUS_PTI_DOUT(0x3, 0x8) +#define PTI_DOUT_PD9 SILABS_DBUS_PTI_DOUT(0x3, 0x9) +#define PTI_DOUT_PD10 SILABS_DBUS_PTI_DOUT(0x3, 0xa) +#define PTI_DOUT_PD11 SILABS_DBUS_PTI_DOUT(0x3, 0xb) +#define PTI_DOUT_PD12 SILABS_DBUS_PTI_DOUT(0x3, 0xc) +#define PTI_DOUT_PD13 SILABS_DBUS_PTI_DOUT(0x3, 0xd) +#define PTI_DOUT_PD14 SILABS_DBUS_PTI_DOUT(0x3, 0xe) +#define PTI_DOUT_PD15 SILABS_DBUS_PTI_DOUT(0x3, 0xf) + +#define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0) +#define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1) +#define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2) +#define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3) +#define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4) +#define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5) +#define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6) +#define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7) +#define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8) +#define I2C0_SCL_PA9 SILABS_DBUS_I2C0_SCL(0x0, 0x9) +#define I2C0_SCL_PA10 SILABS_DBUS_I2C0_SCL(0x0, 0xa) +#define I2C0_SCL_PA11 SILABS_DBUS_I2C0_SCL(0x0, 0xb) +#define I2C0_SCL_PA12 SILABS_DBUS_I2C0_SCL(0x0, 0xc) +#define I2C0_SCL_PA13 SILABS_DBUS_I2C0_SCL(0x0, 0xd) +#define I2C0_SCL_PA14 SILABS_DBUS_I2C0_SCL(0x0, 0xe) +#define I2C0_SCL_PA15 SILABS_DBUS_I2C0_SCL(0x0, 0xf) +#define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0) +#define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1) +#define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2) +#define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3) +#define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4) +#define I2C0_SCL_PB5 SILABS_DBUS_I2C0_SCL(0x1, 0x5) +#define I2C0_SCL_PB6 SILABS_DBUS_I2C0_SCL(0x1, 0x6) +#define I2C0_SCL_PB7 SILABS_DBUS_I2C0_SCL(0x1, 0x7) +#define I2C0_SCL_PB8 SILABS_DBUS_I2C0_SCL(0x1, 0x8) +#define I2C0_SCL_PB9 SILABS_DBUS_I2C0_SCL(0x1, 0x9) +#define I2C0_SCL_PB10 SILABS_DBUS_I2C0_SCL(0x1, 0xa) +#define I2C0_SCL_PB11 SILABS_DBUS_I2C0_SCL(0x1, 0xb) +#define I2C0_SCL_PB12 SILABS_DBUS_I2C0_SCL(0x1, 0xc) +#define I2C0_SCL_PB13 SILABS_DBUS_I2C0_SCL(0x1, 0xd) +#define I2C0_SCL_PB14 SILABS_DBUS_I2C0_SCL(0x1, 0xe) +#define I2C0_SCL_PB15 SILABS_DBUS_I2C0_SCL(0x1, 0xf) +#define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0) +#define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1) +#define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2) +#define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3) +#define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4) +#define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5) +#define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6) +#define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7) +#define I2C0_SCL_PC8 SILABS_DBUS_I2C0_SCL(0x2, 0x8) +#define I2C0_SCL_PC9 SILABS_DBUS_I2C0_SCL(0x2, 0x9) +#define I2C0_SCL_PC10 SILABS_DBUS_I2C0_SCL(0x2, 0xa) +#define I2C0_SCL_PC11 SILABS_DBUS_I2C0_SCL(0x2, 0xb) +#define I2C0_SCL_PC12 SILABS_DBUS_I2C0_SCL(0x2, 0xc) +#define I2C0_SCL_PC13 SILABS_DBUS_I2C0_SCL(0x2, 0xd) +#define I2C0_SCL_PC14 SILABS_DBUS_I2C0_SCL(0x2, 0xe) +#define I2C0_SCL_PC15 SILABS_DBUS_I2C0_SCL(0x2, 0xf) +#define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0) +#define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1) +#define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2) +#define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3) +#define I2C0_SCL_PD4 SILABS_DBUS_I2C0_SCL(0x3, 0x4) +#define I2C0_SCL_PD5 SILABS_DBUS_I2C0_SCL(0x3, 0x5) +#define I2C0_SCL_PD6 SILABS_DBUS_I2C0_SCL(0x3, 0x6) +#define I2C0_SCL_PD7 SILABS_DBUS_I2C0_SCL(0x3, 0x7) +#define I2C0_SCL_PD8 SILABS_DBUS_I2C0_SCL(0x3, 0x8) +#define I2C0_SCL_PD9 SILABS_DBUS_I2C0_SCL(0x3, 0x9) +#define I2C0_SCL_PD10 SILABS_DBUS_I2C0_SCL(0x3, 0xa) +#define I2C0_SCL_PD11 SILABS_DBUS_I2C0_SCL(0x3, 0xb) +#define I2C0_SCL_PD12 SILABS_DBUS_I2C0_SCL(0x3, 0xc) +#define I2C0_SCL_PD13 SILABS_DBUS_I2C0_SCL(0x3, 0xd) +#define I2C0_SCL_PD14 SILABS_DBUS_I2C0_SCL(0x3, 0xe) +#define I2C0_SCL_PD15 SILABS_DBUS_I2C0_SCL(0x3, 0xf) +#define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0) +#define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1) +#define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2) +#define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3) +#define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4) +#define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5) +#define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6) +#define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7) +#define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8) +#define I2C0_SDA_PA9 SILABS_DBUS_I2C0_SDA(0x0, 0x9) +#define I2C0_SDA_PA10 SILABS_DBUS_I2C0_SDA(0x0, 0xa) +#define I2C0_SDA_PA11 SILABS_DBUS_I2C0_SDA(0x0, 0xb) +#define I2C0_SDA_PA12 SILABS_DBUS_I2C0_SDA(0x0, 0xc) +#define I2C0_SDA_PA13 SILABS_DBUS_I2C0_SDA(0x0, 0xd) +#define I2C0_SDA_PA14 SILABS_DBUS_I2C0_SDA(0x0, 0xe) +#define I2C0_SDA_PA15 SILABS_DBUS_I2C0_SDA(0x0, 0xf) +#define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0) +#define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1) +#define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2) +#define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3) +#define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4) +#define I2C0_SDA_PB5 SILABS_DBUS_I2C0_SDA(0x1, 0x5) +#define I2C0_SDA_PB6 SILABS_DBUS_I2C0_SDA(0x1, 0x6) +#define I2C0_SDA_PB7 SILABS_DBUS_I2C0_SDA(0x1, 0x7) +#define I2C0_SDA_PB8 SILABS_DBUS_I2C0_SDA(0x1, 0x8) +#define I2C0_SDA_PB9 SILABS_DBUS_I2C0_SDA(0x1, 0x9) +#define I2C0_SDA_PB10 SILABS_DBUS_I2C0_SDA(0x1, 0xa) +#define I2C0_SDA_PB11 SILABS_DBUS_I2C0_SDA(0x1, 0xb) +#define I2C0_SDA_PB12 SILABS_DBUS_I2C0_SDA(0x1, 0xc) +#define I2C0_SDA_PB13 SILABS_DBUS_I2C0_SDA(0x1, 0xd) +#define I2C0_SDA_PB14 SILABS_DBUS_I2C0_SDA(0x1, 0xe) +#define I2C0_SDA_PB15 SILABS_DBUS_I2C0_SDA(0x1, 0xf) +#define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0) +#define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1) +#define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2) +#define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3) +#define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4) +#define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5) +#define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6) +#define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7) +#define I2C0_SDA_PC8 SILABS_DBUS_I2C0_SDA(0x2, 0x8) +#define I2C0_SDA_PC9 SILABS_DBUS_I2C0_SDA(0x2, 0x9) +#define I2C0_SDA_PC10 SILABS_DBUS_I2C0_SDA(0x2, 0xa) +#define I2C0_SDA_PC11 SILABS_DBUS_I2C0_SDA(0x2, 0xb) +#define I2C0_SDA_PC12 SILABS_DBUS_I2C0_SDA(0x2, 0xc) +#define I2C0_SDA_PC13 SILABS_DBUS_I2C0_SDA(0x2, 0xd) +#define I2C0_SDA_PC14 SILABS_DBUS_I2C0_SDA(0x2, 0xe) +#define I2C0_SDA_PC15 SILABS_DBUS_I2C0_SDA(0x2, 0xf) +#define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0) +#define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1) +#define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2) +#define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3) +#define I2C0_SDA_PD4 SILABS_DBUS_I2C0_SDA(0x3, 0x4) +#define I2C0_SDA_PD5 SILABS_DBUS_I2C0_SDA(0x3, 0x5) +#define I2C0_SDA_PD6 SILABS_DBUS_I2C0_SDA(0x3, 0x6) +#define I2C0_SDA_PD7 SILABS_DBUS_I2C0_SDA(0x3, 0x7) +#define I2C0_SDA_PD8 SILABS_DBUS_I2C0_SDA(0x3, 0x8) +#define I2C0_SDA_PD9 SILABS_DBUS_I2C0_SDA(0x3, 0x9) +#define I2C0_SDA_PD10 SILABS_DBUS_I2C0_SDA(0x3, 0xa) +#define I2C0_SDA_PD11 SILABS_DBUS_I2C0_SDA(0x3, 0xb) +#define I2C0_SDA_PD12 SILABS_DBUS_I2C0_SDA(0x3, 0xc) +#define I2C0_SDA_PD13 SILABS_DBUS_I2C0_SDA(0x3, 0xd) +#define I2C0_SDA_PD14 SILABS_DBUS_I2C0_SDA(0x3, 0xe) +#define I2C0_SDA_PD15 SILABS_DBUS_I2C0_SDA(0x3, 0xf) + +#define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0) +#define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1) +#define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2) +#define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3) +#define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4) +#define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5) +#define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6) +#define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7) +#define I2C1_SCL_PC8 SILABS_DBUS_I2C1_SCL(0x2, 0x8) +#define I2C1_SCL_PC9 SILABS_DBUS_I2C1_SCL(0x2, 0x9) +#define I2C1_SCL_PC10 SILABS_DBUS_I2C1_SCL(0x2, 0xa) +#define I2C1_SCL_PC11 SILABS_DBUS_I2C1_SCL(0x2, 0xb) +#define I2C1_SCL_PC12 SILABS_DBUS_I2C1_SCL(0x2, 0xc) +#define I2C1_SCL_PC13 SILABS_DBUS_I2C1_SCL(0x2, 0xd) +#define I2C1_SCL_PC14 SILABS_DBUS_I2C1_SCL(0x2, 0xe) +#define I2C1_SCL_PC15 SILABS_DBUS_I2C1_SCL(0x2, 0xf) +#define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0) +#define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1) +#define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2) +#define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3) +#define I2C1_SCL_PD4 SILABS_DBUS_I2C1_SCL(0x3, 0x4) +#define I2C1_SCL_PD5 SILABS_DBUS_I2C1_SCL(0x3, 0x5) +#define I2C1_SCL_PD6 SILABS_DBUS_I2C1_SCL(0x3, 0x6) +#define I2C1_SCL_PD7 SILABS_DBUS_I2C1_SCL(0x3, 0x7) +#define I2C1_SCL_PD8 SILABS_DBUS_I2C1_SCL(0x3, 0x8) +#define I2C1_SCL_PD9 SILABS_DBUS_I2C1_SCL(0x3, 0x9) +#define I2C1_SCL_PD10 SILABS_DBUS_I2C1_SCL(0x3, 0xa) +#define I2C1_SCL_PD11 SILABS_DBUS_I2C1_SCL(0x3, 0xb) +#define I2C1_SCL_PD12 SILABS_DBUS_I2C1_SCL(0x3, 0xc) +#define I2C1_SCL_PD13 SILABS_DBUS_I2C1_SCL(0x3, 0xd) +#define I2C1_SCL_PD14 SILABS_DBUS_I2C1_SCL(0x3, 0xe) +#define I2C1_SCL_PD15 SILABS_DBUS_I2C1_SCL(0x3, 0xf) +#define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0) +#define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1) +#define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2) +#define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3) +#define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4) +#define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5) +#define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6) +#define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7) +#define I2C1_SDA_PC8 SILABS_DBUS_I2C1_SDA(0x2, 0x8) +#define I2C1_SDA_PC9 SILABS_DBUS_I2C1_SDA(0x2, 0x9) +#define I2C1_SDA_PC10 SILABS_DBUS_I2C1_SDA(0x2, 0xa) +#define I2C1_SDA_PC11 SILABS_DBUS_I2C1_SDA(0x2, 0xb) +#define I2C1_SDA_PC12 SILABS_DBUS_I2C1_SDA(0x2, 0xc) +#define I2C1_SDA_PC13 SILABS_DBUS_I2C1_SDA(0x2, 0xd) +#define I2C1_SDA_PC14 SILABS_DBUS_I2C1_SDA(0x2, 0xe) +#define I2C1_SDA_PC15 SILABS_DBUS_I2C1_SDA(0x2, 0xf) +#define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0) +#define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1) +#define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2) +#define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3) +#define I2C1_SDA_PD4 SILABS_DBUS_I2C1_SDA(0x3, 0x4) +#define I2C1_SDA_PD5 SILABS_DBUS_I2C1_SDA(0x3, 0x5) +#define I2C1_SDA_PD6 SILABS_DBUS_I2C1_SDA(0x3, 0x6) +#define I2C1_SDA_PD7 SILABS_DBUS_I2C1_SDA(0x3, 0x7) +#define I2C1_SDA_PD8 SILABS_DBUS_I2C1_SDA(0x3, 0x8) +#define I2C1_SDA_PD9 SILABS_DBUS_I2C1_SDA(0x3, 0x9) +#define I2C1_SDA_PD10 SILABS_DBUS_I2C1_SDA(0x3, 0xa) +#define I2C1_SDA_PD11 SILABS_DBUS_I2C1_SDA(0x3, 0xb) +#define I2C1_SDA_PD12 SILABS_DBUS_I2C1_SDA(0x3, 0xc) +#define I2C1_SDA_PD13 SILABS_DBUS_I2C1_SDA(0x3, 0xd) +#define I2C1_SDA_PD14 SILABS_DBUS_I2C1_SDA(0x3, 0xe) +#define I2C1_SDA_PD15 SILABS_DBUS_I2C1_SDA(0x3, 0xf) + +#define I2C2_SCL_PA0 SILABS_DBUS_I2C2_SCL(0x0, 0x0) +#define I2C2_SCL_PA1 SILABS_DBUS_I2C2_SCL(0x0, 0x1) +#define I2C2_SCL_PA2 SILABS_DBUS_I2C2_SCL(0x0, 0x2) +#define I2C2_SCL_PA3 SILABS_DBUS_I2C2_SCL(0x0, 0x3) +#define I2C2_SCL_PA4 SILABS_DBUS_I2C2_SCL(0x0, 0x4) +#define I2C2_SCL_PA5 SILABS_DBUS_I2C2_SCL(0x0, 0x5) +#define I2C2_SCL_PA6 SILABS_DBUS_I2C2_SCL(0x0, 0x6) +#define I2C2_SCL_PA7 SILABS_DBUS_I2C2_SCL(0x0, 0x7) +#define I2C2_SCL_PA8 SILABS_DBUS_I2C2_SCL(0x0, 0x8) +#define I2C2_SCL_PA9 SILABS_DBUS_I2C2_SCL(0x0, 0x9) +#define I2C2_SCL_PA10 SILABS_DBUS_I2C2_SCL(0x0, 0xa) +#define I2C2_SCL_PA11 SILABS_DBUS_I2C2_SCL(0x0, 0xb) +#define I2C2_SCL_PA12 SILABS_DBUS_I2C2_SCL(0x0, 0xc) +#define I2C2_SCL_PA13 SILABS_DBUS_I2C2_SCL(0x0, 0xd) +#define I2C2_SCL_PA14 SILABS_DBUS_I2C2_SCL(0x0, 0xe) +#define I2C2_SCL_PA15 SILABS_DBUS_I2C2_SCL(0x0, 0xf) +#define I2C2_SCL_PB0 SILABS_DBUS_I2C2_SCL(0x1, 0x0) +#define I2C2_SCL_PB1 SILABS_DBUS_I2C2_SCL(0x1, 0x1) +#define I2C2_SCL_PB2 SILABS_DBUS_I2C2_SCL(0x1, 0x2) +#define I2C2_SCL_PB3 SILABS_DBUS_I2C2_SCL(0x1, 0x3) +#define I2C2_SCL_PB4 SILABS_DBUS_I2C2_SCL(0x1, 0x4) +#define I2C2_SCL_PB5 SILABS_DBUS_I2C2_SCL(0x1, 0x5) +#define I2C2_SCL_PB6 SILABS_DBUS_I2C2_SCL(0x1, 0x6) +#define I2C2_SCL_PB7 SILABS_DBUS_I2C2_SCL(0x1, 0x7) +#define I2C2_SCL_PB8 SILABS_DBUS_I2C2_SCL(0x1, 0x8) +#define I2C2_SCL_PB9 SILABS_DBUS_I2C2_SCL(0x1, 0x9) +#define I2C2_SCL_PB10 SILABS_DBUS_I2C2_SCL(0x1, 0xa) +#define I2C2_SCL_PB11 SILABS_DBUS_I2C2_SCL(0x1, 0xb) +#define I2C2_SCL_PB12 SILABS_DBUS_I2C2_SCL(0x1, 0xc) +#define I2C2_SCL_PB13 SILABS_DBUS_I2C2_SCL(0x1, 0xd) +#define I2C2_SCL_PB14 SILABS_DBUS_I2C2_SCL(0x1, 0xe) +#define I2C2_SCL_PB15 SILABS_DBUS_I2C2_SCL(0x1, 0xf) +#define I2C2_SDA_PA0 SILABS_DBUS_I2C2_SDA(0x0, 0x0) +#define I2C2_SDA_PA1 SILABS_DBUS_I2C2_SDA(0x0, 0x1) +#define I2C2_SDA_PA2 SILABS_DBUS_I2C2_SDA(0x0, 0x2) +#define I2C2_SDA_PA3 SILABS_DBUS_I2C2_SDA(0x0, 0x3) +#define I2C2_SDA_PA4 SILABS_DBUS_I2C2_SDA(0x0, 0x4) +#define I2C2_SDA_PA5 SILABS_DBUS_I2C2_SDA(0x0, 0x5) +#define I2C2_SDA_PA6 SILABS_DBUS_I2C2_SDA(0x0, 0x6) +#define I2C2_SDA_PA7 SILABS_DBUS_I2C2_SDA(0x0, 0x7) +#define I2C2_SDA_PA8 SILABS_DBUS_I2C2_SDA(0x0, 0x8) +#define I2C2_SDA_PA9 SILABS_DBUS_I2C2_SDA(0x0, 0x9) +#define I2C2_SDA_PA10 SILABS_DBUS_I2C2_SDA(0x0, 0xa) +#define I2C2_SDA_PA11 SILABS_DBUS_I2C2_SDA(0x0, 0xb) +#define I2C2_SDA_PA12 SILABS_DBUS_I2C2_SDA(0x0, 0xc) +#define I2C2_SDA_PA13 SILABS_DBUS_I2C2_SDA(0x0, 0xd) +#define I2C2_SDA_PA14 SILABS_DBUS_I2C2_SDA(0x0, 0xe) +#define I2C2_SDA_PA15 SILABS_DBUS_I2C2_SDA(0x0, 0xf) +#define I2C2_SDA_PB0 SILABS_DBUS_I2C2_SDA(0x1, 0x0) +#define I2C2_SDA_PB1 SILABS_DBUS_I2C2_SDA(0x1, 0x1) +#define I2C2_SDA_PB2 SILABS_DBUS_I2C2_SDA(0x1, 0x2) +#define I2C2_SDA_PB3 SILABS_DBUS_I2C2_SDA(0x1, 0x3) +#define I2C2_SDA_PB4 SILABS_DBUS_I2C2_SDA(0x1, 0x4) +#define I2C2_SDA_PB5 SILABS_DBUS_I2C2_SDA(0x1, 0x5) +#define I2C2_SDA_PB6 SILABS_DBUS_I2C2_SDA(0x1, 0x6) +#define I2C2_SDA_PB7 SILABS_DBUS_I2C2_SDA(0x1, 0x7) +#define I2C2_SDA_PB8 SILABS_DBUS_I2C2_SDA(0x1, 0x8) +#define I2C2_SDA_PB9 SILABS_DBUS_I2C2_SDA(0x1, 0x9) +#define I2C2_SDA_PB10 SILABS_DBUS_I2C2_SDA(0x1, 0xa) +#define I2C2_SDA_PB11 SILABS_DBUS_I2C2_SDA(0x1, 0xb) +#define I2C2_SDA_PB12 SILABS_DBUS_I2C2_SDA(0x1, 0xc) +#define I2C2_SDA_PB13 SILABS_DBUS_I2C2_SDA(0x1, 0xd) +#define I2C2_SDA_PB14 SILABS_DBUS_I2C2_SDA(0x1, 0xe) +#define I2C2_SDA_PB15 SILABS_DBUS_I2C2_SDA(0x1, 0xf) + +#define I2C3_SCL_PC0 SILABS_DBUS_I2C3_SCL(0x2, 0x0) +#define I2C3_SCL_PC1 SILABS_DBUS_I2C3_SCL(0x2, 0x1) +#define I2C3_SCL_PC2 SILABS_DBUS_I2C3_SCL(0x2, 0x2) +#define I2C3_SCL_PC3 SILABS_DBUS_I2C3_SCL(0x2, 0x3) +#define I2C3_SCL_PC4 SILABS_DBUS_I2C3_SCL(0x2, 0x4) +#define I2C3_SCL_PC5 SILABS_DBUS_I2C3_SCL(0x2, 0x5) +#define I2C3_SCL_PC6 SILABS_DBUS_I2C3_SCL(0x2, 0x6) +#define I2C3_SCL_PC7 SILABS_DBUS_I2C3_SCL(0x2, 0x7) +#define I2C3_SCL_PC8 SILABS_DBUS_I2C3_SCL(0x2, 0x8) +#define I2C3_SCL_PC9 SILABS_DBUS_I2C3_SCL(0x2, 0x9) +#define I2C3_SCL_PC10 SILABS_DBUS_I2C3_SCL(0x2, 0xa) +#define I2C3_SCL_PC11 SILABS_DBUS_I2C3_SCL(0x2, 0xb) +#define I2C3_SCL_PC12 SILABS_DBUS_I2C3_SCL(0x2, 0xc) +#define I2C3_SCL_PC13 SILABS_DBUS_I2C3_SCL(0x2, 0xd) +#define I2C3_SCL_PC14 SILABS_DBUS_I2C3_SCL(0x2, 0xe) +#define I2C3_SCL_PC15 SILABS_DBUS_I2C3_SCL(0x2, 0xf) +#define I2C3_SCL_PD0 SILABS_DBUS_I2C3_SCL(0x3, 0x0) +#define I2C3_SCL_PD1 SILABS_DBUS_I2C3_SCL(0x3, 0x1) +#define I2C3_SCL_PD2 SILABS_DBUS_I2C3_SCL(0x3, 0x2) +#define I2C3_SCL_PD3 SILABS_DBUS_I2C3_SCL(0x3, 0x3) +#define I2C3_SCL_PD4 SILABS_DBUS_I2C3_SCL(0x3, 0x4) +#define I2C3_SCL_PD5 SILABS_DBUS_I2C3_SCL(0x3, 0x5) +#define I2C3_SCL_PD6 SILABS_DBUS_I2C3_SCL(0x3, 0x6) +#define I2C3_SCL_PD7 SILABS_DBUS_I2C3_SCL(0x3, 0x7) +#define I2C3_SCL_PD8 SILABS_DBUS_I2C3_SCL(0x3, 0x8) +#define I2C3_SCL_PD9 SILABS_DBUS_I2C3_SCL(0x3, 0x9) +#define I2C3_SCL_PD10 SILABS_DBUS_I2C3_SCL(0x3, 0xa) +#define I2C3_SCL_PD11 SILABS_DBUS_I2C3_SCL(0x3, 0xb) +#define I2C3_SCL_PD12 SILABS_DBUS_I2C3_SCL(0x3, 0xc) +#define I2C3_SCL_PD13 SILABS_DBUS_I2C3_SCL(0x3, 0xd) +#define I2C3_SCL_PD14 SILABS_DBUS_I2C3_SCL(0x3, 0xe) +#define I2C3_SCL_PD15 SILABS_DBUS_I2C3_SCL(0x3, 0xf) +#define I2C3_SDA_PC0 SILABS_DBUS_I2C3_SDA(0x2, 0x0) +#define I2C3_SDA_PC1 SILABS_DBUS_I2C3_SDA(0x2, 0x1) +#define I2C3_SDA_PC2 SILABS_DBUS_I2C3_SDA(0x2, 0x2) +#define I2C3_SDA_PC3 SILABS_DBUS_I2C3_SDA(0x2, 0x3) +#define I2C3_SDA_PC4 SILABS_DBUS_I2C3_SDA(0x2, 0x4) +#define I2C3_SDA_PC5 SILABS_DBUS_I2C3_SDA(0x2, 0x5) +#define I2C3_SDA_PC6 SILABS_DBUS_I2C3_SDA(0x2, 0x6) +#define I2C3_SDA_PC7 SILABS_DBUS_I2C3_SDA(0x2, 0x7) +#define I2C3_SDA_PC8 SILABS_DBUS_I2C3_SDA(0x2, 0x8) +#define I2C3_SDA_PC9 SILABS_DBUS_I2C3_SDA(0x2, 0x9) +#define I2C3_SDA_PC10 SILABS_DBUS_I2C3_SDA(0x2, 0xa) +#define I2C3_SDA_PC11 SILABS_DBUS_I2C3_SDA(0x2, 0xb) +#define I2C3_SDA_PC12 SILABS_DBUS_I2C3_SDA(0x2, 0xc) +#define I2C3_SDA_PC13 SILABS_DBUS_I2C3_SDA(0x2, 0xd) +#define I2C3_SDA_PC14 SILABS_DBUS_I2C3_SDA(0x2, 0xe) +#define I2C3_SDA_PC15 SILABS_DBUS_I2C3_SDA(0x2, 0xf) +#define I2C3_SDA_PD0 SILABS_DBUS_I2C3_SDA(0x3, 0x0) +#define I2C3_SDA_PD1 SILABS_DBUS_I2C3_SDA(0x3, 0x1) +#define I2C3_SDA_PD2 SILABS_DBUS_I2C3_SDA(0x3, 0x2) +#define I2C3_SDA_PD3 SILABS_DBUS_I2C3_SDA(0x3, 0x3) +#define I2C3_SDA_PD4 SILABS_DBUS_I2C3_SDA(0x3, 0x4) +#define I2C3_SDA_PD5 SILABS_DBUS_I2C3_SDA(0x3, 0x5) +#define I2C3_SDA_PD6 SILABS_DBUS_I2C3_SDA(0x3, 0x6) +#define I2C3_SDA_PD7 SILABS_DBUS_I2C3_SDA(0x3, 0x7) +#define I2C3_SDA_PD8 SILABS_DBUS_I2C3_SDA(0x3, 0x8) +#define I2C3_SDA_PD9 SILABS_DBUS_I2C3_SDA(0x3, 0x9) +#define I2C3_SDA_PD10 SILABS_DBUS_I2C3_SDA(0x3, 0xa) +#define I2C3_SDA_PD11 SILABS_DBUS_I2C3_SDA(0x3, 0xb) +#define I2C3_SDA_PD12 SILABS_DBUS_I2C3_SDA(0x3, 0xc) +#define I2C3_SDA_PD13 SILABS_DBUS_I2C3_SDA(0x3, 0xd) +#define I2C3_SDA_PD14 SILABS_DBUS_I2C3_SDA(0x3, 0xe) +#define I2C3_SDA_PD15 SILABS_DBUS_I2C3_SDA(0x3, 0xf) + +#define KEYSCAN_COLOUT0_PA0 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x0) +#define KEYSCAN_COLOUT0_PA1 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x1) +#define KEYSCAN_COLOUT0_PA2 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x2) +#define KEYSCAN_COLOUT0_PA3 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x3) +#define KEYSCAN_COLOUT0_PA4 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x4) +#define KEYSCAN_COLOUT0_PA5 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x5) +#define KEYSCAN_COLOUT0_PA6 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x6) +#define KEYSCAN_COLOUT0_PA7 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x7) +#define KEYSCAN_COLOUT0_PA8 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x8) +#define KEYSCAN_COLOUT0_PA9 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x9) +#define KEYSCAN_COLOUT0_PA10 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xa) +#define KEYSCAN_COLOUT0_PA11 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xb) +#define KEYSCAN_COLOUT0_PA12 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xc) +#define KEYSCAN_COLOUT0_PA13 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xd) +#define KEYSCAN_COLOUT0_PA14 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xe) +#define KEYSCAN_COLOUT0_PA15 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xf) +#define KEYSCAN_COLOUT0_PB0 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x0) +#define KEYSCAN_COLOUT0_PB1 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x1) +#define KEYSCAN_COLOUT0_PB2 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x2) +#define KEYSCAN_COLOUT0_PB3 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x3) +#define KEYSCAN_COLOUT0_PB4 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x4) +#define KEYSCAN_COLOUT0_PB5 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x5) +#define KEYSCAN_COLOUT0_PB6 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x6) +#define KEYSCAN_COLOUT0_PB7 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x7) +#define KEYSCAN_COLOUT0_PB8 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x8) +#define KEYSCAN_COLOUT0_PB9 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x9) +#define KEYSCAN_COLOUT0_PB10 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0xa) +#define KEYSCAN_COLOUT0_PB11 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0xb) +#define KEYSCAN_COLOUT0_PB12 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0xc) +#define KEYSCAN_COLOUT0_PB13 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0xd) +#define KEYSCAN_COLOUT0_PB14 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0xe) +#define KEYSCAN_COLOUT0_PB15 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0xf) +#define KEYSCAN_COLOUT0_PC0 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x0) +#define KEYSCAN_COLOUT0_PC1 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x1) +#define KEYSCAN_COLOUT0_PC2 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x2) +#define KEYSCAN_COLOUT0_PC3 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x3) +#define KEYSCAN_COLOUT0_PC4 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x4) +#define KEYSCAN_COLOUT0_PC5 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x5) +#define KEYSCAN_COLOUT0_PC6 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x6) +#define KEYSCAN_COLOUT0_PC7 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x7) +#define KEYSCAN_COLOUT0_PC8 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x8) +#define KEYSCAN_COLOUT0_PC9 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x9) +#define KEYSCAN_COLOUT0_PC10 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0xa) +#define KEYSCAN_COLOUT0_PC11 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0xb) +#define KEYSCAN_COLOUT0_PC12 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0xc) +#define KEYSCAN_COLOUT0_PC13 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0xd) +#define KEYSCAN_COLOUT0_PC14 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0xe) +#define KEYSCAN_COLOUT0_PC15 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0xf) +#define KEYSCAN_COLOUT0_PD0 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x0) +#define KEYSCAN_COLOUT0_PD1 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x1) +#define KEYSCAN_COLOUT0_PD2 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x2) +#define KEYSCAN_COLOUT0_PD3 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x3) +#define KEYSCAN_COLOUT0_PD4 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x4) +#define KEYSCAN_COLOUT0_PD5 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x5) +#define KEYSCAN_COLOUT0_PD6 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x6) +#define KEYSCAN_COLOUT0_PD7 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x7) +#define KEYSCAN_COLOUT0_PD8 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x8) +#define KEYSCAN_COLOUT0_PD9 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x9) +#define KEYSCAN_COLOUT0_PD10 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xa) +#define KEYSCAN_COLOUT0_PD11 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xb) +#define KEYSCAN_COLOUT0_PD12 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xc) +#define KEYSCAN_COLOUT0_PD13 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xd) +#define KEYSCAN_COLOUT0_PD14 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xe) +#define KEYSCAN_COLOUT0_PD15 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xf) +#define KEYSCAN_COLOUT1_PA0 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x0) +#define KEYSCAN_COLOUT1_PA1 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x1) +#define KEYSCAN_COLOUT1_PA2 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x2) +#define KEYSCAN_COLOUT1_PA3 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x3) +#define KEYSCAN_COLOUT1_PA4 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x4) +#define KEYSCAN_COLOUT1_PA5 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x5) +#define KEYSCAN_COLOUT1_PA6 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x6) +#define KEYSCAN_COLOUT1_PA7 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x7) +#define KEYSCAN_COLOUT1_PA8 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x8) +#define KEYSCAN_COLOUT1_PA9 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x9) +#define KEYSCAN_COLOUT1_PA10 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xa) +#define KEYSCAN_COLOUT1_PA11 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xb) +#define KEYSCAN_COLOUT1_PA12 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xc) +#define KEYSCAN_COLOUT1_PA13 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xd) +#define KEYSCAN_COLOUT1_PA14 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xe) +#define KEYSCAN_COLOUT1_PA15 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xf) +#define KEYSCAN_COLOUT1_PB0 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x0) +#define KEYSCAN_COLOUT1_PB1 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x1) +#define KEYSCAN_COLOUT1_PB2 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x2) +#define KEYSCAN_COLOUT1_PB3 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x3) +#define KEYSCAN_COLOUT1_PB4 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x4) +#define KEYSCAN_COLOUT1_PB5 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x5) +#define KEYSCAN_COLOUT1_PB6 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x6) +#define KEYSCAN_COLOUT1_PB7 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x7) +#define KEYSCAN_COLOUT1_PB8 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x8) +#define KEYSCAN_COLOUT1_PB9 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x9) +#define KEYSCAN_COLOUT1_PB10 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0xa) +#define KEYSCAN_COLOUT1_PB11 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0xb) +#define KEYSCAN_COLOUT1_PB12 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0xc) +#define KEYSCAN_COLOUT1_PB13 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0xd) +#define KEYSCAN_COLOUT1_PB14 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0xe) +#define KEYSCAN_COLOUT1_PB15 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0xf) +#define KEYSCAN_COLOUT1_PC0 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x0) +#define KEYSCAN_COLOUT1_PC1 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x1) +#define KEYSCAN_COLOUT1_PC2 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x2) +#define KEYSCAN_COLOUT1_PC3 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x3) +#define KEYSCAN_COLOUT1_PC4 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x4) +#define KEYSCAN_COLOUT1_PC5 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x5) +#define KEYSCAN_COLOUT1_PC6 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x6) +#define KEYSCAN_COLOUT1_PC7 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x7) +#define KEYSCAN_COLOUT1_PC8 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x8) +#define KEYSCAN_COLOUT1_PC9 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x9) +#define KEYSCAN_COLOUT1_PC10 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0xa) +#define KEYSCAN_COLOUT1_PC11 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0xb) +#define KEYSCAN_COLOUT1_PC12 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0xc) +#define KEYSCAN_COLOUT1_PC13 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0xd) +#define KEYSCAN_COLOUT1_PC14 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0xe) +#define KEYSCAN_COLOUT1_PC15 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0xf) +#define KEYSCAN_COLOUT1_PD0 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x0) +#define KEYSCAN_COLOUT1_PD1 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x1) +#define KEYSCAN_COLOUT1_PD2 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x2) +#define KEYSCAN_COLOUT1_PD3 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x3) +#define KEYSCAN_COLOUT1_PD4 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x4) +#define KEYSCAN_COLOUT1_PD5 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x5) +#define KEYSCAN_COLOUT1_PD6 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x6) +#define KEYSCAN_COLOUT1_PD7 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x7) +#define KEYSCAN_COLOUT1_PD8 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x8) +#define KEYSCAN_COLOUT1_PD9 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x9) +#define KEYSCAN_COLOUT1_PD10 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xa) +#define KEYSCAN_COLOUT1_PD11 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xb) +#define KEYSCAN_COLOUT1_PD12 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xc) +#define KEYSCAN_COLOUT1_PD13 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xd) +#define KEYSCAN_COLOUT1_PD14 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xe) +#define KEYSCAN_COLOUT1_PD15 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xf) +#define KEYSCAN_COLOUT2_PA0 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x0) +#define KEYSCAN_COLOUT2_PA1 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x1) +#define KEYSCAN_COLOUT2_PA2 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x2) +#define KEYSCAN_COLOUT2_PA3 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x3) +#define KEYSCAN_COLOUT2_PA4 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x4) +#define KEYSCAN_COLOUT2_PA5 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x5) +#define KEYSCAN_COLOUT2_PA6 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x6) +#define KEYSCAN_COLOUT2_PA7 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x7) +#define KEYSCAN_COLOUT2_PA8 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x8) +#define KEYSCAN_COLOUT2_PA9 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x9) +#define KEYSCAN_COLOUT2_PA10 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xa) +#define KEYSCAN_COLOUT2_PA11 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xb) +#define KEYSCAN_COLOUT2_PA12 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xc) +#define KEYSCAN_COLOUT2_PA13 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xd) +#define KEYSCAN_COLOUT2_PA14 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xe) +#define KEYSCAN_COLOUT2_PA15 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xf) +#define KEYSCAN_COLOUT2_PB0 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x0) +#define KEYSCAN_COLOUT2_PB1 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x1) +#define KEYSCAN_COLOUT2_PB2 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x2) +#define KEYSCAN_COLOUT2_PB3 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x3) +#define KEYSCAN_COLOUT2_PB4 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x4) +#define KEYSCAN_COLOUT2_PB5 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x5) +#define KEYSCAN_COLOUT2_PB6 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x6) +#define KEYSCAN_COLOUT2_PB7 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x7) +#define KEYSCAN_COLOUT2_PB8 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x8) +#define KEYSCAN_COLOUT2_PB9 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x9) +#define KEYSCAN_COLOUT2_PB10 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0xa) +#define KEYSCAN_COLOUT2_PB11 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0xb) +#define KEYSCAN_COLOUT2_PB12 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0xc) +#define KEYSCAN_COLOUT2_PB13 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0xd) +#define KEYSCAN_COLOUT2_PB14 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0xe) +#define KEYSCAN_COLOUT2_PB15 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0xf) +#define KEYSCAN_COLOUT2_PC0 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x0) +#define KEYSCAN_COLOUT2_PC1 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x1) +#define KEYSCAN_COLOUT2_PC2 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x2) +#define KEYSCAN_COLOUT2_PC3 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x3) +#define KEYSCAN_COLOUT2_PC4 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x4) +#define KEYSCAN_COLOUT2_PC5 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x5) +#define KEYSCAN_COLOUT2_PC6 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x6) +#define KEYSCAN_COLOUT2_PC7 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x7) +#define KEYSCAN_COLOUT2_PC8 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x8) +#define KEYSCAN_COLOUT2_PC9 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x9) +#define KEYSCAN_COLOUT2_PC10 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0xa) +#define KEYSCAN_COLOUT2_PC11 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0xb) +#define KEYSCAN_COLOUT2_PC12 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0xc) +#define KEYSCAN_COLOUT2_PC13 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0xd) +#define KEYSCAN_COLOUT2_PC14 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0xe) +#define KEYSCAN_COLOUT2_PC15 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0xf) +#define KEYSCAN_COLOUT2_PD0 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x0) +#define KEYSCAN_COLOUT2_PD1 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x1) +#define KEYSCAN_COLOUT2_PD2 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x2) +#define KEYSCAN_COLOUT2_PD3 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x3) +#define KEYSCAN_COLOUT2_PD4 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x4) +#define KEYSCAN_COLOUT2_PD5 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x5) +#define KEYSCAN_COLOUT2_PD6 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x6) +#define KEYSCAN_COLOUT2_PD7 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x7) +#define KEYSCAN_COLOUT2_PD8 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x8) +#define KEYSCAN_COLOUT2_PD9 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x9) +#define KEYSCAN_COLOUT2_PD10 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xa) +#define KEYSCAN_COLOUT2_PD11 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xb) +#define KEYSCAN_COLOUT2_PD12 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xc) +#define KEYSCAN_COLOUT2_PD13 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xd) +#define KEYSCAN_COLOUT2_PD14 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xe) +#define KEYSCAN_COLOUT2_PD15 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xf) +#define KEYSCAN_COLOUT3_PA0 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x0) +#define KEYSCAN_COLOUT3_PA1 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x1) +#define KEYSCAN_COLOUT3_PA2 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x2) +#define KEYSCAN_COLOUT3_PA3 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x3) +#define KEYSCAN_COLOUT3_PA4 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x4) +#define KEYSCAN_COLOUT3_PA5 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x5) +#define KEYSCAN_COLOUT3_PA6 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x6) +#define KEYSCAN_COLOUT3_PA7 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x7) +#define KEYSCAN_COLOUT3_PA8 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x8) +#define KEYSCAN_COLOUT3_PA9 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x9) +#define KEYSCAN_COLOUT3_PA10 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xa) +#define KEYSCAN_COLOUT3_PA11 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xb) +#define KEYSCAN_COLOUT3_PA12 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xc) +#define KEYSCAN_COLOUT3_PA13 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xd) +#define KEYSCAN_COLOUT3_PA14 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xe) +#define KEYSCAN_COLOUT3_PA15 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xf) +#define KEYSCAN_COLOUT3_PB0 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x0) +#define KEYSCAN_COLOUT3_PB1 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x1) +#define KEYSCAN_COLOUT3_PB2 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x2) +#define KEYSCAN_COLOUT3_PB3 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x3) +#define KEYSCAN_COLOUT3_PB4 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x4) +#define KEYSCAN_COLOUT3_PB5 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x5) +#define KEYSCAN_COLOUT3_PB6 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x6) +#define KEYSCAN_COLOUT3_PB7 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x7) +#define KEYSCAN_COLOUT3_PB8 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x8) +#define KEYSCAN_COLOUT3_PB9 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x9) +#define KEYSCAN_COLOUT3_PB10 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0xa) +#define KEYSCAN_COLOUT3_PB11 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0xb) +#define KEYSCAN_COLOUT3_PB12 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0xc) +#define KEYSCAN_COLOUT3_PB13 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0xd) +#define KEYSCAN_COLOUT3_PB14 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0xe) +#define KEYSCAN_COLOUT3_PB15 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0xf) +#define KEYSCAN_COLOUT3_PC0 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x0) +#define KEYSCAN_COLOUT3_PC1 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x1) +#define KEYSCAN_COLOUT3_PC2 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x2) +#define KEYSCAN_COLOUT3_PC3 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x3) +#define KEYSCAN_COLOUT3_PC4 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x4) +#define KEYSCAN_COLOUT3_PC5 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x5) +#define KEYSCAN_COLOUT3_PC6 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x6) +#define KEYSCAN_COLOUT3_PC7 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x7) +#define KEYSCAN_COLOUT3_PC8 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x8) +#define KEYSCAN_COLOUT3_PC9 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x9) +#define KEYSCAN_COLOUT3_PC10 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0xa) +#define KEYSCAN_COLOUT3_PC11 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0xb) +#define KEYSCAN_COLOUT3_PC12 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0xc) +#define KEYSCAN_COLOUT3_PC13 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0xd) +#define KEYSCAN_COLOUT3_PC14 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0xe) +#define KEYSCAN_COLOUT3_PC15 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0xf) +#define KEYSCAN_COLOUT3_PD0 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x0) +#define KEYSCAN_COLOUT3_PD1 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x1) +#define KEYSCAN_COLOUT3_PD2 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x2) +#define KEYSCAN_COLOUT3_PD3 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x3) +#define KEYSCAN_COLOUT3_PD4 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x4) +#define KEYSCAN_COLOUT3_PD5 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x5) +#define KEYSCAN_COLOUT3_PD6 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x6) +#define KEYSCAN_COLOUT3_PD7 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x7) +#define KEYSCAN_COLOUT3_PD8 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x8) +#define KEYSCAN_COLOUT3_PD9 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x9) +#define KEYSCAN_COLOUT3_PD10 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xa) +#define KEYSCAN_COLOUT3_PD11 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xb) +#define KEYSCAN_COLOUT3_PD12 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xc) +#define KEYSCAN_COLOUT3_PD13 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xd) +#define KEYSCAN_COLOUT3_PD14 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xe) +#define KEYSCAN_COLOUT3_PD15 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xf) +#define KEYSCAN_COLOUT4_PA0 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x0) +#define KEYSCAN_COLOUT4_PA1 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x1) +#define KEYSCAN_COLOUT4_PA2 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x2) +#define KEYSCAN_COLOUT4_PA3 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x3) +#define KEYSCAN_COLOUT4_PA4 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x4) +#define KEYSCAN_COLOUT4_PA5 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x5) +#define KEYSCAN_COLOUT4_PA6 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x6) +#define KEYSCAN_COLOUT4_PA7 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x7) +#define KEYSCAN_COLOUT4_PA8 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x8) +#define KEYSCAN_COLOUT4_PA9 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x9) +#define KEYSCAN_COLOUT4_PA10 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xa) +#define KEYSCAN_COLOUT4_PA11 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xb) +#define KEYSCAN_COLOUT4_PA12 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xc) +#define KEYSCAN_COLOUT4_PA13 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xd) +#define KEYSCAN_COLOUT4_PA14 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xe) +#define KEYSCAN_COLOUT4_PA15 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xf) +#define KEYSCAN_COLOUT4_PB0 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x0) +#define KEYSCAN_COLOUT4_PB1 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x1) +#define KEYSCAN_COLOUT4_PB2 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x2) +#define KEYSCAN_COLOUT4_PB3 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x3) +#define KEYSCAN_COLOUT4_PB4 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x4) +#define KEYSCAN_COLOUT4_PB5 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x5) +#define KEYSCAN_COLOUT4_PB6 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x6) +#define KEYSCAN_COLOUT4_PB7 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x7) +#define KEYSCAN_COLOUT4_PB8 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x8) +#define KEYSCAN_COLOUT4_PB9 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x9) +#define KEYSCAN_COLOUT4_PB10 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0xa) +#define KEYSCAN_COLOUT4_PB11 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0xb) +#define KEYSCAN_COLOUT4_PB12 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0xc) +#define KEYSCAN_COLOUT4_PB13 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0xd) +#define KEYSCAN_COLOUT4_PB14 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0xe) +#define KEYSCAN_COLOUT4_PB15 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0xf) +#define KEYSCAN_COLOUT4_PC0 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x0) +#define KEYSCAN_COLOUT4_PC1 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x1) +#define KEYSCAN_COLOUT4_PC2 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x2) +#define KEYSCAN_COLOUT4_PC3 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x3) +#define KEYSCAN_COLOUT4_PC4 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x4) +#define KEYSCAN_COLOUT4_PC5 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x5) +#define KEYSCAN_COLOUT4_PC6 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x6) +#define KEYSCAN_COLOUT4_PC7 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x7) +#define KEYSCAN_COLOUT4_PC8 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x8) +#define KEYSCAN_COLOUT4_PC9 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x9) +#define KEYSCAN_COLOUT4_PC10 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0xa) +#define KEYSCAN_COLOUT4_PC11 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0xb) +#define KEYSCAN_COLOUT4_PC12 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0xc) +#define KEYSCAN_COLOUT4_PC13 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0xd) +#define KEYSCAN_COLOUT4_PC14 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0xe) +#define KEYSCAN_COLOUT4_PC15 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0xf) +#define KEYSCAN_COLOUT4_PD0 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x0) +#define KEYSCAN_COLOUT4_PD1 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x1) +#define KEYSCAN_COLOUT4_PD2 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x2) +#define KEYSCAN_COLOUT4_PD3 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x3) +#define KEYSCAN_COLOUT4_PD4 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x4) +#define KEYSCAN_COLOUT4_PD5 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x5) +#define KEYSCAN_COLOUT4_PD6 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x6) +#define KEYSCAN_COLOUT4_PD7 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x7) +#define KEYSCAN_COLOUT4_PD8 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x8) +#define KEYSCAN_COLOUT4_PD9 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x9) +#define KEYSCAN_COLOUT4_PD10 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xa) +#define KEYSCAN_COLOUT4_PD11 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xb) +#define KEYSCAN_COLOUT4_PD12 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xc) +#define KEYSCAN_COLOUT4_PD13 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xd) +#define KEYSCAN_COLOUT4_PD14 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xe) +#define KEYSCAN_COLOUT4_PD15 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xf) +#define KEYSCAN_COLOUT5_PA0 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x0) +#define KEYSCAN_COLOUT5_PA1 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x1) +#define KEYSCAN_COLOUT5_PA2 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x2) +#define KEYSCAN_COLOUT5_PA3 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x3) +#define KEYSCAN_COLOUT5_PA4 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x4) +#define KEYSCAN_COLOUT5_PA5 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x5) +#define KEYSCAN_COLOUT5_PA6 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x6) +#define KEYSCAN_COLOUT5_PA7 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x7) +#define KEYSCAN_COLOUT5_PA8 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x8) +#define KEYSCAN_COLOUT5_PA9 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x9) +#define KEYSCAN_COLOUT5_PA10 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xa) +#define KEYSCAN_COLOUT5_PA11 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xb) +#define KEYSCAN_COLOUT5_PA12 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xc) +#define KEYSCAN_COLOUT5_PA13 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xd) +#define KEYSCAN_COLOUT5_PA14 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xe) +#define KEYSCAN_COLOUT5_PA15 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xf) +#define KEYSCAN_COLOUT5_PB0 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x0) +#define KEYSCAN_COLOUT5_PB1 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x1) +#define KEYSCAN_COLOUT5_PB2 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x2) +#define KEYSCAN_COLOUT5_PB3 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x3) +#define KEYSCAN_COLOUT5_PB4 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x4) +#define KEYSCAN_COLOUT5_PB5 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x5) +#define KEYSCAN_COLOUT5_PB6 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x6) +#define KEYSCAN_COLOUT5_PB7 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x7) +#define KEYSCAN_COLOUT5_PB8 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x8) +#define KEYSCAN_COLOUT5_PB9 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x9) +#define KEYSCAN_COLOUT5_PB10 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0xa) +#define KEYSCAN_COLOUT5_PB11 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0xb) +#define KEYSCAN_COLOUT5_PB12 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0xc) +#define KEYSCAN_COLOUT5_PB13 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0xd) +#define KEYSCAN_COLOUT5_PB14 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0xe) +#define KEYSCAN_COLOUT5_PB15 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0xf) +#define KEYSCAN_COLOUT5_PC0 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x0) +#define KEYSCAN_COLOUT5_PC1 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x1) +#define KEYSCAN_COLOUT5_PC2 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x2) +#define KEYSCAN_COLOUT5_PC3 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x3) +#define KEYSCAN_COLOUT5_PC4 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x4) +#define KEYSCAN_COLOUT5_PC5 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x5) +#define KEYSCAN_COLOUT5_PC6 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x6) +#define KEYSCAN_COLOUT5_PC7 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x7) +#define KEYSCAN_COLOUT5_PC8 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x8) +#define KEYSCAN_COLOUT5_PC9 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x9) +#define KEYSCAN_COLOUT5_PC10 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0xa) +#define KEYSCAN_COLOUT5_PC11 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0xb) +#define KEYSCAN_COLOUT5_PC12 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0xc) +#define KEYSCAN_COLOUT5_PC13 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0xd) +#define KEYSCAN_COLOUT5_PC14 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0xe) +#define KEYSCAN_COLOUT5_PC15 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0xf) +#define KEYSCAN_COLOUT5_PD0 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x0) +#define KEYSCAN_COLOUT5_PD1 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x1) +#define KEYSCAN_COLOUT5_PD2 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x2) +#define KEYSCAN_COLOUT5_PD3 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x3) +#define KEYSCAN_COLOUT5_PD4 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x4) +#define KEYSCAN_COLOUT5_PD5 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x5) +#define KEYSCAN_COLOUT5_PD6 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x6) +#define KEYSCAN_COLOUT5_PD7 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x7) +#define KEYSCAN_COLOUT5_PD8 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x8) +#define KEYSCAN_COLOUT5_PD9 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x9) +#define KEYSCAN_COLOUT5_PD10 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xa) +#define KEYSCAN_COLOUT5_PD11 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xb) +#define KEYSCAN_COLOUT5_PD12 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xc) +#define KEYSCAN_COLOUT5_PD13 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xd) +#define KEYSCAN_COLOUT5_PD14 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xe) +#define KEYSCAN_COLOUT5_PD15 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xf) +#define KEYSCAN_COLOUT6_PA0 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x0) +#define KEYSCAN_COLOUT6_PA1 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x1) +#define KEYSCAN_COLOUT6_PA2 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x2) +#define KEYSCAN_COLOUT6_PA3 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x3) +#define KEYSCAN_COLOUT6_PA4 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x4) +#define KEYSCAN_COLOUT6_PA5 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x5) +#define KEYSCAN_COLOUT6_PA6 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x6) +#define KEYSCAN_COLOUT6_PA7 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x7) +#define KEYSCAN_COLOUT6_PA8 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x8) +#define KEYSCAN_COLOUT6_PA9 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x9) +#define KEYSCAN_COLOUT6_PA10 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xa) +#define KEYSCAN_COLOUT6_PA11 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xb) +#define KEYSCAN_COLOUT6_PA12 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xc) +#define KEYSCAN_COLOUT6_PA13 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xd) +#define KEYSCAN_COLOUT6_PA14 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xe) +#define KEYSCAN_COLOUT6_PA15 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xf) +#define KEYSCAN_COLOUT6_PB0 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x0) +#define KEYSCAN_COLOUT6_PB1 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x1) +#define KEYSCAN_COLOUT6_PB2 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x2) +#define KEYSCAN_COLOUT6_PB3 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x3) +#define KEYSCAN_COLOUT6_PB4 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x4) +#define KEYSCAN_COLOUT6_PB5 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x5) +#define KEYSCAN_COLOUT6_PB6 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x6) +#define KEYSCAN_COLOUT6_PB7 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x7) +#define KEYSCAN_COLOUT6_PB8 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x8) +#define KEYSCAN_COLOUT6_PB9 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x9) +#define KEYSCAN_COLOUT6_PB10 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0xa) +#define KEYSCAN_COLOUT6_PB11 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0xb) +#define KEYSCAN_COLOUT6_PB12 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0xc) +#define KEYSCAN_COLOUT6_PB13 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0xd) +#define KEYSCAN_COLOUT6_PB14 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0xe) +#define KEYSCAN_COLOUT6_PB15 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0xf) +#define KEYSCAN_COLOUT6_PC0 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x0) +#define KEYSCAN_COLOUT6_PC1 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x1) +#define KEYSCAN_COLOUT6_PC2 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x2) +#define KEYSCAN_COLOUT6_PC3 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x3) +#define KEYSCAN_COLOUT6_PC4 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x4) +#define KEYSCAN_COLOUT6_PC5 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x5) +#define KEYSCAN_COLOUT6_PC6 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x6) +#define KEYSCAN_COLOUT6_PC7 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x7) +#define KEYSCAN_COLOUT6_PC8 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x8) +#define KEYSCAN_COLOUT6_PC9 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x9) +#define KEYSCAN_COLOUT6_PC10 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0xa) +#define KEYSCAN_COLOUT6_PC11 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0xb) +#define KEYSCAN_COLOUT6_PC12 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0xc) +#define KEYSCAN_COLOUT6_PC13 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0xd) +#define KEYSCAN_COLOUT6_PC14 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0xe) +#define KEYSCAN_COLOUT6_PC15 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0xf) +#define KEYSCAN_COLOUT6_PD0 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x0) +#define KEYSCAN_COLOUT6_PD1 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x1) +#define KEYSCAN_COLOUT6_PD2 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x2) +#define KEYSCAN_COLOUT6_PD3 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x3) +#define KEYSCAN_COLOUT6_PD4 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x4) +#define KEYSCAN_COLOUT6_PD5 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x5) +#define KEYSCAN_COLOUT6_PD6 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x6) +#define KEYSCAN_COLOUT6_PD7 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x7) +#define KEYSCAN_COLOUT6_PD8 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x8) +#define KEYSCAN_COLOUT6_PD9 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x9) +#define KEYSCAN_COLOUT6_PD10 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xa) +#define KEYSCAN_COLOUT6_PD11 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xb) +#define KEYSCAN_COLOUT6_PD12 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xc) +#define KEYSCAN_COLOUT6_PD13 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xd) +#define KEYSCAN_COLOUT6_PD14 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xe) +#define KEYSCAN_COLOUT6_PD15 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xf) +#define KEYSCAN_COLOUT7_PA0 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x0) +#define KEYSCAN_COLOUT7_PA1 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x1) +#define KEYSCAN_COLOUT7_PA2 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x2) +#define KEYSCAN_COLOUT7_PA3 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x3) +#define KEYSCAN_COLOUT7_PA4 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x4) +#define KEYSCAN_COLOUT7_PA5 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x5) +#define KEYSCAN_COLOUT7_PA6 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x6) +#define KEYSCAN_COLOUT7_PA7 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x7) +#define KEYSCAN_COLOUT7_PA8 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x8) +#define KEYSCAN_COLOUT7_PA9 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x9) +#define KEYSCAN_COLOUT7_PA10 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xa) +#define KEYSCAN_COLOUT7_PA11 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xb) +#define KEYSCAN_COLOUT7_PA12 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xc) +#define KEYSCAN_COLOUT7_PA13 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xd) +#define KEYSCAN_COLOUT7_PA14 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xe) +#define KEYSCAN_COLOUT7_PA15 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xf) +#define KEYSCAN_COLOUT7_PB0 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x0) +#define KEYSCAN_COLOUT7_PB1 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x1) +#define KEYSCAN_COLOUT7_PB2 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x2) +#define KEYSCAN_COLOUT7_PB3 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x3) +#define KEYSCAN_COLOUT7_PB4 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x4) +#define KEYSCAN_COLOUT7_PB5 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x5) +#define KEYSCAN_COLOUT7_PB6 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x6) +#define KEYSCAN_COLOUT7_PB7 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x7) +#define KEYSCAN_COLOUT7_PB8 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x8) +#define KEYSCAN_COLOUT7_PB9 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x9) +#define KEYSCAN_COLOUT7_PB10 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0xa) +#define KEYSCAN_COLOUT7_PB11 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0xb) +#define KEYSCAN_COLOUT7_PB12 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0xc) +#define KEYSCAN_COLOUT7_PB13 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0xd) +#define KEYSCAN_COLOUT7_PB14 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0xe) +#define KEYSCAN_COLOUT7_PB15 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0xf) +#define KEYSCAN_COLOUT7_PC0 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x0) +#define KEYSCAN_COLOUT7_PC1 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x1) +#define KEYSCAN_COLOUT7_PC2 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x2) +#define KEYSCAN_COLOUT7_PC3 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x3) +#define KEYSCAN_COLOUT7_PC4 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x4) +#define KEYSCAN_COLOUT7_PC5 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x5) +#define KEYSCAN_COLOUT7_PC6 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x6) +#define KEYSCAN_COLOUT7_PC7 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x7) +#define KEYSCAN_COLOUT7_PC8 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x8) +#define KEYSCAN_COLOUT7_PC9 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x9) +#define KEYSCAN_COLOUT7_PC10 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0xa) +#define KEYSCAN_COLOUT7_PC11 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0xb) +#define KEYSCAN_COLOUT7_PC12 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0xc) +#define KEYSCAN_COLOUT7_PC13 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0xd) +#define KEYSCAN_COLOUT7_PC14 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0xe) +#define KEYSCAN_COLOUT7_PC15 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0xf) +#define KEYSCAN_COLOUT7_PD0 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x0) +#define KEYSCAN_COLOUT7_PD1 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x1) +#define KEYSCAN_COLOUT7_PD2 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x2) +#define KEYSCAN_COLOUT7_PD3 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x3) +#define KEYSCAN_COLOUT7_PD4 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x4) +#define KEYSCAN_COLOUT7_PD5 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x5) +#define KEYSCAN_COLOUT7_PD6 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x6) +#define KEYSCAN_COLOUT7_PD7 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x7) +#define KEYSCAN_COLOUT7_PD8 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x8) +#define KEYSCAN_COLOUT7_PD9 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x9) +#define KEYSCAN_COLOUT7_PD10 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xa) +#define KEYSCAN_COLOUT7_PD11 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xb) +#define KEYSCAN_COLOUT7_PD12 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xc) +#define KEYSCAN_COLOUT7_PD13 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xd) +#define KEYSCAN_COLOUT7_PD14 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xe) +#define KEYSCAN_COLOUT7_PD15 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xf) +#define KEYSCAN_ROWSENSE0_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x0) +#define KEYSCAN_ROWSENSE0_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x1) +#define KEYSCAN_ROWSENSE0_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x2) +#define KEYSCAN_ROWSENSE0_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x3) +#define KEYSCAN_ROWSENSE0_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x4) +#define KEYSCAN_ROWSENSE0_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x5) +#define KEYSCAN_ROWSENSE0_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x6) +#define KEYSCAN_ROWSENSE0_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x7) +#define KEYSCAN_ROWSENSE0_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x8) +#define KEYSCAN_ROWSENSE0_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x9) +#define KEYSCAN_ROWSENSE0_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xa) +#define KEYSCAN_ROWSENSE0_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xb) +#define KEYSCAN_ROWSENSE0_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xc) +#define KEYSCAN_ROWSENSE0_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xd) +#define KEYSCAN_ROWSENSE0_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xe) +#define KEYSCAN_ROWSENSE0_PA15 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xf) +#define KEYSCAN_ROWSENSE0_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x0) +#define KEYSCAN_ROWSENSE0_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x1) +#define KEYSCAN_ROWSENSE0_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x2) +#define KEYSCAN_ROWSENSE0_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x3) +#define KEYSCAN_ROWSENSE0_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x4) +#define KEYSCAN_ROWSENSE0_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x5) +#define KEYSCAN_ROWSENSE0_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x6) +#define KEYSCAN_ROWSENSE0_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x7) +#define KEYSCAN_ROWSENSE0_PB8 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x8) +#define KEYSCAN_ROWSENSE0_PB9 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x9) +#define KEYSCAN_ROWSENSE0_PB10 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0xa) +#define KEYSCAN_ROWSENSE0_PB11 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0xb) +#define KEYSCAN_ROWSENSE0_PB12 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0xc) +#define KEYSCAN_ROWSENSE0_PB13 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0xd) +#define KEYSCAN_ROWSENSE0_PB14 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0xe) +#define KEYSCAN_ROWSENSE0_PB15 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0xf) +#define KEYSCAN_ROWSENSE1_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x0) +#define KEYSCAN_ROWSENSE1_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x1) +#define KEYSCAN_ROWSENSE1_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x2) +#define KEYSCAN_ROWSENSE1_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x3) +#define KEYSCAN_ROWSENSE1_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x4) +#define KEYSCAN_ROWSENSE1_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x5) +#define KEYSCAN_ROWSENSE1_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x6) +#define KEYSCAN_ROWSENSE1_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x7) +#define KEYSCAN_ROWSENSE1_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x8) +#define KEYSCAN_ROWSENSE1_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x9) +#define KEYSCAN_ROWSENSE1_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xa) +#define KEYSCAN_ROWSENSE1_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xb) +#define KEYSCAN_ROWSENSE1_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xc) +#define KEYSCAN_ROWSENSE1_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xd) +#define KEYSCAN_ROWSENSE1_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xe) +#define KEYSCAN_ROWSENSE1_PA15 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xf) +#define KEYSCAN_ROWSENSE1_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x0) +#define KEYSCAN_ROWSENSE1_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x1) +#define KEYSCAN_ROWSENSE1_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x2) +#define KEYSCAN_ROWSENSE1_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x3) +#define KEYSCAN_ROWSENSE1_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x4) +#define KEYSCAN_ROWSENSE1_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x5) +#define KEYSCAN_ROWSENSE1_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x6) +#define KEYSCAN_ROWSENSE1_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x7) +#define KEYSCAN_ROWSENSE1_PB8 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x8) +#define KEYSCAN_ROWSENSE1_PB9 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x9) +#define KEYSCAN_ROWSENSE1_PB10 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0xa) +#define KEYSCAN_ROWSENSE1_PB11 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0xb) +#define KEYSCAN_ROWSENSE1_PB12 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0xc) +#define KEYSCAN_ROWSENSE1_PB13 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0xd) +#define KEYSCAN_ROWSENSE1_PB14 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0xe) +#define KEYSCAN_ROWSENSE1_PB15 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0xf) +#define KEYSCAN_ROWSENSE2_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x0) +#define KEYSCAN_ROWSENSE2_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x1) +#define KEYSCAN_ROWSENSE2_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x2) +#define KEYSCAN_ROWSENSE2_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x3) +#define KEYSCAN_ROWSENSE2_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x4) +#define KEYSCAN_ROWSENSE2_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x5) +#define KEYSCAN_ROWSENSE2_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x6) +#define KEYSCAN_ROWSENSE2_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x7) +#define KEYSCAN_ROWSENSE2_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x8) +#define KEYSCAN_ROWSENSE2_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x9) +#define KEYSCAN_ROWSENSE2_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xa) +#define KEYSCAN_ROWSENSE2_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xb) +#define KEYSCAN_ROWSENSE2_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xc) +#define KEYSCAN_ROWSENSE2_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xd) +#define KEYSCAN_ROWSENSE2_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xe) +#define KEYSCAN_ROWSENSE2_PA15 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xf) +#define KEYSCAN_ROWSENSE2_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x0) +#define KEYSCAN_ROWSENSE2_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x1) +#define KEYSCAN_ROWSENSE2_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x2) +#define KEYSCAN_ROWSENSE2_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x3) +#define KEYSCAN_ROWSENSE2_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x4) +#define KEYSCAN_ROWSENSE2_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x5) +#define KEYSCAN_ROWSENSE2_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x6) +#define KEYSCAN_ROWSENSE2_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x7) +#define KEYSCAN_ROWSENSE2_PB8 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x8) +#define KEYSCAN_ROWSENSE2_PB9 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x9) +#define KEYSCAN_ROWSENSE2_PB10 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0xa) +#define KEYSCAN_ROWSENSE2_PB11 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0xb) +#define KEYSCAN_ROWSENSE2_PB12 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0xc) +#define KEYSCAN_ROWSENSE2_PB13 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0xd) +#define KEYSCAN_ROWSENSE2_PB14 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0xe) +#define KEYSCAN_ROWSENSE2_PB15 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0xf) +#define KEYSCAN_ROWSENSE3_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x0) +#define KEYSCAN_ROWSENSE3_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x1) +#define KEYSCAN_ROWSENSE3_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x2) +#define KEYSCAN_ROWSENSE3_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x3) +#define KEYSCAN_ROWSENSE3_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x4) +#define KEYSCAN_ROWSENSE3_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x5) +#define KEYSCAN_ROWSENSE3_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x6) +#define KEYSCAN_ROWSENSE3_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x7) +#define KEYSCAN_ROWSENSE3_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x8) +#define KEYSCAN_ROWSENSE3_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x9) +#define KEYSCAN_ROWSENSE3_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xa) +#define KEYSCAN_ROWSENSE3_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xb) +#define KEYSCAN_ROWSENSE3_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xc) +#define KEYSCAN_ROWSENSE3_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xd) +#define KEYSCAN_ROWSENSE3_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xe) +#define KEYSCAN_ROWSENSE3_PA15 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xf) +#define KEYSCAN_ROWSENSE3_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x0) +#define KEYSCAN_ROWSENSE3_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x1) +#define KEYSCAN_ROWSENSE3_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x2) +#define KEYSCAN_ROWSENSE3_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x3) +#define KEYSCAN_ROWSENSE3_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x4) +#define KEYSCAN_ROWSENSE3_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x5) +#define KEYSCAN_ROWSENSE3_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x6) +#define KEYSCAN_ROWSENSE3_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x7) +#define KEYSCAN_ROWSENSE3_PB8 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x8) +#define KEYSCAN_ROWSENSE3_PB9 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x9) +#define KEYSCAN_ROWSENSE3_PB10 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0xa) +#define KEYSCAN_ROWSENSE3_PB11 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0xb) +#define KEYSCAN_ROWSENSE3_PB12 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0xc) +#define KEYSCAN_ROWSENSE3_PB13 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0xd) +#define KEYSCAN_ROWSENSE3_PB14 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0xe) +#define KEYSCAN_ROWSENSE3_PB15 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0xf) +#define KEYSCAN_ROWSENSE4_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x0) +#define KEYSCAN_ROWSENSE4_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x1) +#define KEYSCAN_ROWSENSE4_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x2) +#define KEYSCAN_ROWSENSE4_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x3) +#define KEYSCAN_ROWSENSE4_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x4) +#define KEYSCAN_ROWSENSE4_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x5) +#define KEYSCAN_ROWSENSE4_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x6) +#define KEYSCAN_ROWSENSE4_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x7) +#define KEYSCAN_ROWSENSE4_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x8) +#define KEYSCAN_ROWSENSE4_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x9) +#define KEYSCAN_ROWSENSE4_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xa) +#define KEYSCAN_ROWSENSE4_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xb) +#define KEYSCAN_ROWSENSE4_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xc) +#define KEYSCAN_ROWSENSE4_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xd) +#define KEYSCAN_ROWSENSE4_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xe) +#define KEYSCAN_ROWSENSE4_PA15 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xf) +#define KEYSCAN_ROWSENSE4_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x0) +#define KEYSCAN_ROWSENSE4_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x1) +#define KEYSCAN_ROWSENSE4_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x2) +#define KEYSCAN_ROWSENSE4_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x3) +#define KEYSCAN_ROWSENSE4_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x4) +#define KEYSCAN_ROWSENSE4_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x5) +#define KEYSCAN_ROWSENSE4_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x6) +#define KEYSCAN_ROWSENSE4_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x7) +#define KEYSCAN_ROWSENSE4_PB8 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x8) +#define KEYSCAN_ROWSENSE4_PB9 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x9) +#define KEYSCAN_ROWSENSE4_PB10 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0xa) +#define KEYSCAN_ROWSENSE4_PB11 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0xb) +#define KEYSCAN_ROWSENSE4_PB12 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0xc) +#define KEYSCAN_ROWSENSE4_PB13 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0xd) +#define KEYSCAN_ROWSENSE4_PB14 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0xe) +#define KEYSCAN_ROWSENSE4_PB15 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0xf) +#define KEYSCAN_ROWSENSE5_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x0) +#define KEYSCAN_ROWSENSE5_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x1) +#define KEYSCAN_ROWSENSE5_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x2) +#define KEYSCAN_ROWSENSE5_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x3) +#define KEYSCAN_ROWSENSE5_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x4) +#define KEYSCAN_ROWSENSE5_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x5) +#define KEYSCAN_ROWSENSE5_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x6) +#define KEYSCAN_ROWSENSE5_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x7) +#define KEYSCAN_ROWSENSE5_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x8) +#define KEYSCAN_ROWSENSE5_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x9) +#define KEYSCAN_ROWSENSE5_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xa) +#define KEYSCAN_ROWSENSE5_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xb) +#define KEYSCAN_ROWSENSE5_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xc) +#define KEYSCAN_ROWSENSE5_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xd) +#define KEYSCAN_ROWSENSE5_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xe) +#define KEYSCAN_ROWSENSE5_PA15 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xf) +#define KEYSCAN_ROWSENSE5_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x0) +#define KEYSCAN_ROWSENSE5_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x1) +#define KEYSCAN_ROWSENSE5_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x2) +#define KEYSCAN_ROWSENSE5_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x3) +#define KEYSCAN_ROWSENSE5_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x4) +#define KEYSCAN_ROWSENSE5_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x5) +#define KEYSCAN_ROWSENSE5_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x6) +#define KEYSCAN_ROWSENSE5_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x7) +#define KEYSCAN_ROWSENSE5_PB8 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x8) +#define KEYSCAN_ROWSENSE5_PB9 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x9) +#define KEYSCAN_ROWSENSE5_PB10 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0xa) +#define KEYSCAN_ROWSENSE5_PB11 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0xb) +#define KEYSCAN_ROWSENSE5_PB12 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0xc) +#define KEYSCAN_ROWSENSE5_PB13 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0xd) +#define KEYSCAN_ROWSENSE5_PB14 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0xe) +#define KEYSCAN_ROWSENSE5_PB15 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0xf) + +#define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0) +#define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1) +#define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2) +#define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3) +#define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4) +#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5) +#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6) +#define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7) +#define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8) +#define LETIMER0_OUT0_PA9 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x9) +#define LETIMER0_OUT0_PA10 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xa) +#define LETIMER0_OUT0_PA11 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xb) +#define LETIMER0_OUT0_PA12 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xc) +#define LETIMER0_OUT0_PA13 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xd) +#define LETIMER0_OUT0_PA14 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xe) +#define LETIMER0_OUT0_PA15 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xf) +#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0) +#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1) +#define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2) +#define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3) +#define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4) +#define LETIMER0_OUT0_PB5 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x5) +#define LETIMER0_OUT0_PB6 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x6) +#define LETIMER0_OUT0_PB7 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x7) +#define LETIMER0_OUT0_PB8 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x8) +#define LETIMER0_OUT0_PB9 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x9) +#define LETIMER0_OUT0_PB10 SILABS_DBUS_LETIMER0_OUT0(0x1, 0xa) +#define LETIMER0_OUT0_PB11 SILABS_DBUS_LETIMER0_OUT0(0x1, 0xb) +#define LETIMER0_OUT0_PB12 SILABS_DBUS_LETIMER0_OUT0(0x1, 0xc) +#define LETIMER0_OUT0_PB13 SILABS_DBUS_LETIMER0_OUT0(0x1, 0xd) +#define LETIMER0_OUT0_PB14 SILABS_DBUS_LETIMER0_OUT0(0x1, 0xe) +#define LETIMER0_OUT0_PB15 SILABS_DBUS_LETIMER0_OUT0(0x1, 0xf) +#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0) +#define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1) +#define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2) +#define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3) +#define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4) +#define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5) +#define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6) +#define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7) +#define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8) +#define LETIMER0_OUT1_PA9 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x9) +#define LETIMER0_OUT1_PA10 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xa) +#define LETIMER0_OUT1_PA11 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xb) +#define LETIMER0_OUT1_PA12 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xc) +#define LETIMER0_OUT1_PA13 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xd) +#define LETIMER0_OUT1_PA14 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xe) +#define LETIMER0_OUT1_PA15 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xf) +#define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0) +#define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1) +#define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2) +#define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3) +#define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4) +#define LETIMER0_OUT1_PB5 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x5) +#define LETIMER0_OUT1_PB6 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x6) +#define LETIMER0_OUT1_PB7 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x7) +#define LETIMER0_OUT1_PB8 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x8) +#define LETIMER0_OUT1_PB9 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x9) +#define LETIMER0_OUT1_PB10 SILABS_DBUS_LETIMER0_OUT1(0x1, 0xa) +#define LETIMER0_OUT1_PB11 SILABS_DBUS_LETIMER0_OUT1(0x1, 0xb) +#define LETIMER0_OUT1_PB12 SILABS_DBUS_LETIMER0_OUT1(0x1, 0xc) +#define LETIMER0_OUT1_PB13 SILABS_DBUS_LETIMER0_OUT1(0x1, 0xd) +#define LETIMER0_OUT1_PB14 SILABS_DBUS_LETIMER0_OUT1(0x1, 0xe) +#define LETIMER0_OUT1_PB15 SILABS_DBUS_LETIMER0_OUT1(0x1, 0xf) + +#define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0) +#define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1) +#define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2) +#define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3) +#define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4) +#define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5) +#define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6) +#define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7) +#define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8) +#define MODEM_ANT0_PA9 SILABS_DBUS_MODEM_ANT0(0x0, 0x9) +#define MODEM_ANT0_PA10 SILABS_DBUS_MODEM_ANT0(0x0, 0xa) +#define MODEM_ANT0_PA11 SILABS_DBUS_MODEM_ANT0(0x0, 0xb) +#define MODEM_ANT0_PA12 SILABS_DBUS_MODEM_ANT0(0x0, 0xc) +#define MODEM_ANT0_PA13 SILABS_DBUS_MODEM_ANT0(0x0, 0xd) +#define MODEM_ANT0_PA14 SILABS_DBUS_MODEM_ANT0(0x0, 0xe) +#define MODEM_ANT0_PA15 SILABS_DBUS_MODEM_ANT0(0x0, 0xf) +#define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0) +#define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1) +#define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2) +#define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3) +#define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4) +#define MODEM_ANT0_PB5 SILABS_DBUS_MODEM_ANT0(0x1, 0x5) +#define MODEM_ANT0_PB6 SILABS_DBUS_MODEM_ANT0(0x1, 0x6) +#define MODEM_ANT0_PB7 SILABS_DBUS_MODEM_ANT0(0x1, 0x7) +#define MODEM_ANT0_PB8 SILABS_DBUS_MODEM_ANT0(0x1, 0x8) +#define MODEM_ANT0_PB9 SILABS_DBUS_MODEM_ANT0(0x1, 0x9) +#define MODEM_ANT0_PB10 SILABS_DBUS_MODEM_ANT0(0x1, 0xa) +#define MODEM_ANT0_PB11 SILABS_DBUS_MODEM_ANT0(0x1, 0xb) +#define MODEM_ANT0_PB12 SILABS_DBUS_MODEM_ANT0(0x1, 0xc) +#define MODEM_ANT0_PB13 SILABS_DBUS_MODEM_ANT0(0x1, 0xd) +#define MODEM_ANT0_PB14 SILABS_DBUS_MODEM_ANT0(0x1, 0xe) +#define MODEM_ANT0_PB15 SILABS_DBUS_MODEM_ANT0(0x1, 0xf) +#define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0) +#define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1) +#define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2) +#define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3) +#define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4) +#define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5) +#define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6) +#define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7) +#define MODEM_ANT0_PC8 SILABS_DBUS_MODEM_ANT0(0x2, 0x8) +#define MODEM_ANT0_PC9 SILABS_DBUS_MODEM_ANT0(0x2, 0x9) +#define MODEM_ANT0_PC10 SILABS_DBUS_MODEM_ANT0(0x2, 0xa) +#define MODEM_ANT0_PC11 SILABS_DBUS_MODEM_ANT0(0x2, 0xb) +#define MODEM_ANT0_PC12 SILABS_DBUS_MODEM_ANT0(0x2, 0xc) +#define MODEM_ANT0_PC13 SILABS_DBUS_MODEM_ANT0(0x2, 0xd) +#define MODEM_ANT0_PC14 SILABS_DBUS_MODEM_ANT0(0x2, 0xe) +#define MODEM_ANT0_PC15 SILABS_DBUS_MODEM_ANT0(0x2, 0xf) +#define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0) +#define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1) +#define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2) +#define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3) +#define MODEM_ANT0_PD4 SILABS_DBUS_MODEM_ANT0(0x3, 0x4) +#define MODEM_ANT0_PD5 SILABS_DBUS_MODEM_ANT0(0x3, 0x5) +#define MODEM_ANT0_PD6 SILABS_DBUS_MODEM_ANT0(0x3, 0x6) +#define MODEM_ANT0_PD7 SILABS_DBUS_MODEM_ANT0(0x3, 0x7) +#define MODEM_ANT0_PD8 SILABS_DBUS_MODEM_ANT0(0x3, 0x8) +#define MODEM_ANT0_PD9 SILABS_DBUS_MODEM_ANT0(0x3, 0x9) +#define MODEM_ANT0_PD10 SILABS_DBUS_MODEM_ANT0(0x3, 0xa) +#define MODEM_ANT0_PD11 SILABS_DBUS_MODEM_ANT0(0x3, 0xb) +#define MODEM_ANT0_PD12 SILABS_DBUS_MODEM_ANT0(0x3, 0xc) +#define MODEM_ANT0_PD13 SILABS_DBUS_MODEM_ANT0(0x3, 0xd) +#define MODEM_ANT0_PD14 SILABS_DBUS_MODEM_ANT0(0x3, 0xe) +#define MODEM_ANT0_PD15 SILABS_DBUS_MODEM_ANT0(0x3, 0xf) +#define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0) +#define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1) +#define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2) +#define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3) +#define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4) +#define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5) +#define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6) +#define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7) +#define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8) +#define MODEM_ANT1_PA9 SILABS_DBUS_MODEM_ANT1(0x0, 0x9) +#define MODEM_ANT1_PA10 SILABS_DBUS_MODEM_ANT1(0x0, 0xa) +#define MODEM_ANT1_PA11 SILABS_DBUS_MODEM_ANT1(0x0, 0xb) +#define MODEM_ANT1_PA12 SILABS_DBUS_MODEM_ANT1(0x0, 0xc) +#define MODEM_ANT1_PA13 SILABS_DBUS_MODEM_ANT1(0x0, 0xd) +#define MODEM_ANT1_PA14 SILABS_DBUS_MODEM_ANT1(0x0, 0xe) +#define MODEM_ANT1_PA15 SILABS_DBUS_MODEM_ANT1(0x0, 0xf) +#define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0) +#define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1) +#define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2) +#define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3) +#define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4) +#define MODEM_ANT1_PB5 SILABS_DBUS_MODEM_ANT1(0x1, 0x5) +#define MODEM_ANT1_PB6 SILABS_DBUS_MODEM_ANT1(0x1, 0x6) +#define MODEM_ANT1_PB7 SILABS_DBUS_MODEM_ANT1(0x1, 0x7) +#define MODEM_ANT1_PB8 SILABS_DBUS_MODEM_ANT1(0x1, 0x8) +#define MODEM_ANT1_PB9 SILABS_DBUS_MODEM_ANT1(0x1, 0x9) +#define MODEM_ANT1_PB10 SILABS_DBUS_MODEM_ANT1(0x1, 0xa) +#define MODEM_ANT1_PB11 SILABS_DBUS_MODEM_ANT1(0x1, 0xb) +#define MODEM_ANT1_PB12 SILABS_DBUS_MODEM_ANT1(0x1, 0xc) +#define MODEM_ANT1_PB13 SILABS_DBUS_MODEM_ANT1(0x1, 0xd) +#define MODEM_ANT1_PB14 SILABS_DBUS_MODEM_ANT1(0x1, 0xe) +#define MODEM_ANT1_PB15 SILABS_DBUS_MODEM_ANT1(0x1, 0xf) +#define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0) +#define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1) +#define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2) +#define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3) +#define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4) +#define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5) +#define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6) +#define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7) +#define MODEM_ANT1_PC8 SILABS_DBUS_MODEM_ANT1(0x2, 0x8) +#define MODEM_ANT1_PC9 SILABS_DBUS_MODEM_ANT1(0x2, 0x9) +#define MODEM_ANT1_PC10 SILABS_DBUS_MODEM_ANT1(0x2, 0xa) +#define MODEM_ANT1_PC11 SILABS_DBUS_MODEM_ANT1(0x2, 0xb) +#define MODEM_ANT1_PC12 SILABS_DBUS_MODEM_ANT1(0x2, 0xc) +#define MODEM_ANT1_PC13 SILABS_DBUS_MODEM_ANT1(0x2, 0xd) +#define MODEM_ANT1_PC14 SILABS_DBUS_MODEM_ANT1(0x2, 0xe) +#define MODEM_ANT1_PC15 SILABS_DBUS_MODEM_ANT1(0x2, 0xf) +#define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0) +#define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1) +#define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2) +#define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3) +#define MODEM_ANT1_PD4 SILABS_DBUS_MODEM_ANT1(0x3, 0x4) +#define MODEM_ANT1_PD5 SILABS_DBUS_MODEM_ANT1(0x3, 0x5) +#define MODEM_ANT1_PD6 SILABS_DBUS_MODEM_ANT1(0x3, 0x6) +#define MODEM_ANT1_PD7 SILABS_DBUS_MODEM_ANT1(0x3, 0x7) +#define MODEM_ANT1_PD8 SILABS_DBUS_MODEM_ANT1(0x3, 0x8) +#define MODEM_ANT1_PD9 SILABS_DBUS_MODEM_ANT1(0x3, 0x9) +#define MODEM_ANT1_PD10 SILABS_DBUS_MODEM_ANT1(0x3, 0xa) +#define MODEM_ANT1_PD11 SILABS_DBUS_MODEM_ANT1(0x3, 0xb) +#define MODEM_ANT1_PD12 SILABS_DBUS_MODEM_ANT1(0x3, 0xc) +#define MODEM_ANT1_PD13 SILABS_DBUS_MODEM_ANT1(0x3, 0xd) +#define MODEM_ANT1_PD14 SILABS_DBUS_MODEM_ANT1(0x3, 0xe) +#define MODEM_ANT1_PD15 SILABS_DBUS_MODEM_ANT1(0x3, 0xf) +#define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0) +#define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1) +#define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2) +#define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3) +#define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4) +#define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5) +#define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6) +#define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7) +#define MODEM_ANTROLLOVER_PC8 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x8) +#define MODEM_ANTROLLOVER_PC9 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x9) +#define MODEM_ANTROLLOVER_PC10 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0xa) +#define MODEM_ANTROLLOVER_PC11 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0xb) +#define MODEM_ANTROLLOVER_PC12 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0xc) +#define MODEM_ANTROLLOVER_PC13 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0xd) +#define MODEM_ANTROLLOVER_PC14 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0xe) +#define MODEM_ANTROLLOVER_PC15 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0xf) +#define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0) +#define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1) +#define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2) +#define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3) +#define MODEM_ANTROLLOVER_PD4 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x4) +#define MODEM_ANTROLLOVER_PD5 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x5) +#define MODEM_ANTROLLOVER_PD6 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x6) +#define MODEM_ANTROLLOVER_PD7 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x7) +#define MODEM_ANTROLLOVER_PD8 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x8) +#define MODEM_ANTROLLOVER_PD9 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x9) +#define MODEM_ANTROLLOVER_PD10 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xa) +#define MODEM_ANTROLLOVER_PD11 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xb) +#define MODEM_ANTROLLOVER_PD12 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xc) +#define MODEM_ANTROLLOVER_PD13 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xd) +#define MODEM_ANTROLLOVER_PD14 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xe) +#define MODEM_ANTROLLOVER_PD15 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xf) +#define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0) +#define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1) +#define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2) +#define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3) +#define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4) +#define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5) +#define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6) +#define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7) +#define MODEM_ANTRR0_PC8 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x8) +#define MODEM_ANTRR0_PC9 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x9) +#define MODEM_ANTRR0_PC10 SILABS_DBUS_MODEM_ANTRR0(0x2, 0xa) +#define MODEM_ANTRR0_PC11 SILABS_DBUS_MODEM_ANTRR0(0x2, 0xb) +#define MODEM_ANTRR0_PC12 SILABS_DBUS_MODEM_ANTRR0(0x2, 0xc) +#define MODEM_ANTRR0_PC13 SILABS_DBUS_MODEM_ANTRR0(0x2, 0xd) +#define MODEM_ANTRR0_PC14 SILABS_DBUS_MODEM_ANTRR0(0x2, 0xe) +#define MODEM_ANTRR0_PC15 SILABS_DBUS_MODEM_ANTRR0(0x2, 0xf) +#define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0) +#define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1) +#define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2) +#define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3) +#define MODEM_ANTRR0_PD4 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x4) +#define MODEM_ANTRR0_PD5 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x5) +#define MODEM_ANTRR0_PD6 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x6) +#define MODEM_ANTRR0_PD7 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x7) +#define MODEM_ANTRR0_PD8 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x8) +#define MODEM_ANTRR0_PD9 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x9) +#define MODEM_ANTRR0_PD10 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xa) +#define MODEM_ANTRR0_PD11 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xb) +#define MODEM_ANTRR0_PD12 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xc) +#define MODEM_ANTRR0_PD13 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xd) +#define MODEM_ANTRR0_PD14 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xe) +#define MODEM_ANTRR0_PD15 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xf) +#define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0) +#define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1) +#define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2) +#define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3) +#define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4) +#define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5) +#define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6) +#define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7) +#define MODEM_ANTRR1_PC8 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x8) +#define MODEM_ANTRR1_PC9 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x9) +#define MODEM_ANTRR1_PC10 SILABS_DBUS_MODEM_ANTRR1(0x2, 0xa) +#define MODEM_ANTRR1_PC11 SILABS_DBUS_MODEM_ANTRR1(0x2, 0xb) +#define MODEM_ANTRR1_PC12 SILABS_DBUS_MODEM_ANTRR1(0x2, 0xc) +#define MODEM_ANTRR1_PC13 SILABS_DBUS_MODEM_ANTRR1(0x2, 0xd) +#define MODEM_ANTRR1_PC14 SILABS_DBUS_MODEM_ANTRR1(0x2, 0xe) +#define MODEM_ANTRR1_PC15 SILABS_DBUS_MODEM_ANTRR1(0x2, 0xf) +#define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0) +#define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1) +#define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2) +#define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3) +#define MODEM_ANTRR1_PD4 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x4) +#define MODEM_ANTRR1_PD5 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x5) +#define MODEM_ANTRR1_PD6 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x6) +#define MODEM_ANTRR1_PD7 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x7) +#define MODEM_ANTRR1_PD8 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x8) +#define MODEM_ANTRR1_PD9 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x9) +#define MODEM_ANTRR1_PD10 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xa) +#define MODEM_ANTRR1_PD11 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xb) +#define MODEM_ANTRR1_PD12 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xc) +#define MODEM_ANTRR1_PD13 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xd) +#define MODEM_ANTRR1_PD14 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xe) +#define MODEM_ANTRR1_PD15 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xf) +#define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0) +#define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1) +#define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2) +#define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3) +#define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4) +#define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5) +#define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6) +#define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7) +#define MODEM_ANTRR2_PC8 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x8) +#define MODEM_ANTRR2_PC9 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x9) +#define MODEM_ANTRR2_PC10 SILABS_DBUS_MODEM_ANTRR2(0x2, 0xa) +#define MODEM_ANTRR2_PC11 SILABS_DBUS_MODEM_ANTRR2(0x2, 0xb) +#define MODEM_ANTRR2_PC12 SILABS_DBUS_MODEM_ANTRR2(0x2, 0xc) +#define MODEM_ANTRR2_PC13 SILABS_DBUS_MODEM_ANTRR2(0x2, 0xd) +#define MODEM_ANTRR2_PC14 SILABS_DBUS_MODEM_ANTRR2(0x2, 0xe) +#define MODEM_ANTRR2_PC15 SILABS_DBUS_MODEM_ANTRR2(0x2, 0xf) +#define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0) +#define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1) +#define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2) +#define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3) +#define MODEM_ANTRR2_PD4 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x4) +#define MODEM_ANTRR2_PD5 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x5) +#define MODEM_ANTRR2_PD6 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x6) +#define MODEM_ANTRR2_PD7 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x7) +#define MODEM_ANTRR2_PD8 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x8) +#define MODEM_ANTRR2_PD9 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x9) +#define MODEM_ANTRR2_PD10 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xa) +#define MODEM_ANTRR2_PD11 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xb) +#define MODEM_ANTRR2_PD12 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xc) +#define MODEM_ANTRR2_PD13 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xd) +#define MODEM_ANTRR2_PD14 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xe) +#define MODEM_ANTRR2_PD15 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xf) +#define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0) +#define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1) +#define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2) +#define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3) +#define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4) +#define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5) +#define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6) +#define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7) +#define MODEM_ANTRR3_PC8 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x8) +#define MODEM_ANTRR3_PC9 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x9) +#define MODEM_ANTRR3_PC10 SILABS_DBUS_MODEM_ANTRR3(0x2, 0xa) +#define MODEM_ANTRR3_PC11 SILABS_DBUS_MODEM_ANTRR3(0x2, 0xb) +#define MODEM_ANTRR3_PC12 SILABS_DBUS_MODEM_ANTRR3(0x2, 0xc) +#define MODEM_ANTRR3_PC13 SILABS_DBUS_MODEM_ANTRR3(0x2, 0xd) +#define MODEM_ANTRR3_PC14 SILABS_DBUS_MODEM_ANTRR3(0x2, 0xe) +#define MODEM_ANTRR3_PC15 SILABS_DBUS_MODEM_ANTRR3(0x2, 0xf) +#define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0) +#define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1) +#define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2) +#define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3) +#define MODEM_ANTRR3_PD4 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x4) +#define MODEM_ANTRR3_PD5 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x5) +#define MODEM_ANTRR3_PD6 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x6) +#define MODEM_ANTRR3_PD7 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x7) +#define MODEM_ANTRR3_PD8 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x8) +#define MODEM_ANTRR3_PD9 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x9) +#define MODEM_ANTRR3_PD10 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xa) +#define MODEM_ANTRR3_PD11 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xb) +#define MODEM_ANTRR3_PD12 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xc) +#define MODEM_ANTRR3_PD13 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xd) +#define MODEM_ANTRR3_PD14 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xe) +#define MODEM_ANTRR3_PD15 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xf) +#define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0) +#define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1) +#define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2) +#define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3) +#define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4) +#define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5) +#define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6) +#define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7) +#define MODEM_ANTRR4_PC8 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x8) +#define MODEM_ANTRR4_PC9 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x9) +#define MODEM_ANTRR4_PC10 SILABS_DBUS_MODEM_ANTRR4(0x2, 0xa) +#define MODEM_ANTRR4_PC11 SILABS_DBUS_MODEM_ANTRR4(0x2, 0xb) +#define MODEM_ANTRR4_PC12 SILABS_DBUS_MODEM_ANTRR4(0x2, 0xc) +#define MODEM_ANTRR4_PC13 SILABS_DBUS_MODEM_ANTRR4(0x2, 0xd) +#define MODEM_ANTRR4_PC14 SILABS_DBUS_MODEM_ANTRR4(0x2, 0xe) +#define MODEM_ANTRR4_PC15 SILABS_DBUS_MODEM_ANTRR4(0x2, 0xf) +#define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0) +#define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1) +#define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2) +#define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3) +#define MODEM_ANTRR4_PD4 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x4) +#define MODEM_ANTRR4_PD5 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x5) +#define MODEM_ANTRR4_PD6 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x6) +#define MODEM_ANTRR4_PD7 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x7) +#define MODEM_ANTRR4_PD8 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x8) +#define MODEM_ANTRR4_PD9 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x9) +#define MODEM_ANTRR4_PD10 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xa) +#define MODEM_ANTRR4_PD11 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xb) +#define MODEM_ANTRR4_PD12 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xc) +#define MODEM_ANTRR4_PD13 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xd) +#define MODEM_ANTRR4_PD14 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xe) +#define MODEM_ANTRR4_PD15 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xf) +#define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0) +#define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1) +#define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2) +#define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3) +#define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4) +#define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5) +#define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6) +#define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7) +#define MODEM_ANTRR5_PC8 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x8) +#define MODEM_ANTRR5_PC9 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x9) +#define MODEM_ANTRR5_PC10 SILABS_DBUS_MODEM_ANTRR5(0x2, 0xa) +#define MODEM_ANTRR5_PC11 SILABS_DBUS_MODEM_ANTRR5(0x2, 0xb) +#define MODEM_ANTRR5_PC12 SILABS_DBUS_MODEM_ANTRR5(0x2, 0xc) +#define MODEM_ANTRR5_PC13 SILABS_DBUS_MODEM_ANTRR5(0x2, 0xd) +#define MODEM_ANTRR5_PC14 SILABS_DBUS_MODEM_ANTRR5(0x2, 0xe) +#define MODEM_ANTRR5_PC15 SILABS_DBUS_MODEM_ANTRR5(0x2, 0xf) +#define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0) +#define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1) +#define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2) +#define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3) +#define MODEM_ANTRR5_PD4 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x4) +#define MODEM_ANTRR5_PD5 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x5) +#define MODEM_ANTRR5_PD6 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x6) +#define MODEM_ANTRR5_PD7 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x7) +#define MODEM_ANTRR5_PD8 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x8) +#define MODEM_ANTRR5_PD9 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x9) +#define MODEM_ANTRR5_PD10 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xa) +#define MODEM_ANTRR5_PD11 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xb) +#define MODEM_ANTRR5_PD12 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xc) +#define MODEM_ANTRR5_PD13 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xd) +#define MODEM_ANTRR5_PD14 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xe) +#define MODEM_ANTRR5_PD15 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xf) +#define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0) +#define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1) +#define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2) +#define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3) +#define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4) +#define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5) +#define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6) +#define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7) +#define MODEM_ANTSWEN_PC8 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x8) +#define MODEM_ANTSWEN_PC9 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x9) +#define MODEM_ANTSWEN_PC10 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0xa) +#define MODEM_ANTSWEN_PC11 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0xb) +#define MODEM_ANTSWEN_PC12 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0xc) +#define MODEM_ANTSWEN_PC13 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0xd) +#define MODEM_ANTSWEN_PC14 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0xe) +#define MODEM_ANTSWEN_PC15 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0xf) +#define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0) +#define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1) +#define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2) +#define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3) +#define MODEM_ANTSWEN_PD4 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x4) +#define MODEM_ANTSWEN_PD5 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x5) +#define MODEM_ANTSWEN_PD6 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x6) +#define MODEM_ANTSWEN_PD7 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x7) +#define MODEM_ANTSWEN_PD8 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x8) +#define MODEM_ANTSWEN_PD9 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x9) +#define MODEM_ANTSWEN_PD10 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xa) +#define MODEM_ANTSWEN_PD11 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xb) +#define MODEM_ANTSWEN_PD12 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xc) +#define MODEM_ANTSWEN_PD13 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xd) +#define MODEM_ANTSWEN_PD14 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xe) +#define MODEM_ANTSWEN_PD15 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xf) +#define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0) +#define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1) +#define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2) +#define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3) +#define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4) +#define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5) +#define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6) +#define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7) +#define MODEM_ANTSWUS_PC8 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x8) +#define MODEM_ANTSWUS_PC9 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x9) +#define MODEM_ANTSWUS_PC10 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0xa) +#define MODEM_ANTSWUS_PC11 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0xb) +#define MODEM_ANTSWUS_PC12 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0xc) +#define MODEM_ANTSWUS_PC13 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0xd) +#define MODEM_ANTSWUS_PC14 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0xe) +#define MODEM_ANTSWUS_PC15 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0xf) +#define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0) +#define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1) +#define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2) +#define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3) +#define MODEM_ANTSWUS_PD4 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x4) +#define MODEM_ANTSWUS_PD5 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x5) +#define MODEM_ANTSWUS_PD6 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x6) +#define MODEM_ANTSWUS_PD7 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x7) +#define MODEM_ANTSWUS_PD8 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x8) +#define MODEM_ANTSWUS_PD9 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x9) +#define MODEM_ANTSWUS_PD10 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xa) +#define MODEM_ANTSWUS_PD11 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xb) +#define MODEM_ANTSWUS_PD12 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xc) +#define MODEM_ANTSWUS_PD13 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xd) +#define MODEM_ANTSWUS_PD14 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xe) +#define MODEM_ANTSWUS_PD15 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xf) +#define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0) +#define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1) +#define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2) +#define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3) +#define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4) +#define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5) +#define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6) +#define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7) +#define MODEM_ANTTRIG_PC8 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x8) +#define MODEM_ANTTRIG_PC9 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x9) +#define MODEM_ANTTRIG_PC10 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0xa) +#define MODEM_ANTTRIG_PC11 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0xb) +#define MODEM_ANTTRIG_PC12 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0xc) +#define MODEM_ANTTRIG_PC13 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0xd) +#define MODEM_ANTTRIG_PC14 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0xe) +#define MODEM_ANTTRIG_PC15 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0xf) +#define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0) +#define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1) +#define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2) +#define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3) +#define MODEM_ANTTRIG_PD4 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x4) +#define MODEM_ANTTRIG_PD5 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x5) +#define MODEM_ANTTRIG_PD6 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x6) +#define MODEM_ANTTRIG_PD7 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x7) +#define MODEM_ANTTRIG_PD8 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x8) +#define MODEM_ANTTRIG_PD9 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x9) +#define MODEM_ANTTRIG_PD10 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xa) +#define MODEM_ANTTRIG_PD11 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xb) +#define MODEM_ANTTRIG_PD12 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xc) +#define MODEM_ANTTRIG_PD13 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xd) +#define MODEM_ANTTRIG_PD14 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xe) +#define MODEM_ANTTRIG_PD15 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xf) +#define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0) +#define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1) +#define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2) +#define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3) +#define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4) +#define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5) +#define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6) +#define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7) +#define MODEM_ANTTRIGSTOP_PC8 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x8) +#define MODEM_ANTTRIGSTOP_PC9 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x9) +#define MODEM_ANTTRIGSTOP_PC10 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0xa) +#define MODEM_ANTTRIGSTOP_PC11 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0xb) +#define MODEM_ANTTRIGSTOP_PC12 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0xc) +#define MODEM_ANTTRIGSTOP_PC13 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0xd) +#define MODEM_ANTTRIGSTOP_PC14 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0xe) +#define MODEM_ANTTRIGSTOP_PC15 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0xf) +#define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0) +#define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1) +#define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2) +#define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3) +#define MODEM_ANTTRIGSTOP_PD4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x4) +#define MODEM_ANTTRIGSTOP_PD5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x5) +#define MODEM_ANTTRIGSTOP_PD6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x6) +#define MODEM_ANTTRIGSTOP_PD7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x7) +#define MODEM_ANTTRIGSTOP_PD8 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x8) +#define MODEM_ANTTRIGSTOP_PD9 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x9) +#define MODEM_ANTTRIGSTOP_PD10 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xa) +#define MODEM_ANTTRIGSTOP_PD11 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xb) +#define MODEM_ANTTRIGSTOP_PD12 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xc) +#define MODEM_ANTTRIGSTOP_PD13 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xd) +#define MODEM_ANTTRIGSTOP_PD14 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xe) +#define MODEM_ANTTRIGSTOP_PD15 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xf) +#define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0) +#define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1) +#define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2) +#define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3) +#define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4) +#define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5) +#define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6) +#define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7) +#define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8) +#define MODEM_DCLK_PA9 SILABS_DBUS_MODEM_DCLK(0x0, 0x9) +#define MODEM_DCLK_PA10 SILABS_DBUS_MODEM_DCLK(0x0, 0xa) +#define MODEM_DCLK_PA11 SILABS_DBUS_MODEM_DCLK(0x0, 0xb) +#define MODEM_DCLK_PA12 SILABS_DBUS_MODEM_DCLK(0x0, 0xc) +#define MODEM_DCLK_PA13 SILABS_DBUS_MODEM_DCLK(0x0, 0xd) +#define MODEM_DCLK_PA14 SILABS_DBUS_MODEM_DCLK(0x0, 0xe) +#define MODEM_DCLK_PA15 SILABS_DBUS_MODEM_DCLK(0x0, 0xf) +#define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0) +#define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1) +#define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2) +#define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3) +#define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4) +#define MODEM_DCLK_PB5 SILABS_DBUS_MODEM_DCLK(0x1, 0x5) +#define MODEM_DCLK_PB6 SILABS_DBUS_MODEM_DCLK(0x1, 0x6) +#define MODEM_DCLK_PB7 SILABS_DBUS_MODEM_DCLK(0x1, 0x7) +#define MODEM_DCLK_PB8 SILABS_DBUS_MODEM_DCLK(0x1, 0x8) +#define MODEM_DCLK_PB9 SILABS_DBUS_MODEM_DCLK(0x1, 0x9) +#define MODEM_DCLK_PB10 SILABS_DBUS_MODEM_DCLK(0x1, 0xa) +#define MODEM_DCLK_PB11 SILABS_DBUS_MODEM_DCLK(0x1, 0xb) +#define MODEM_DCLK_PB12 SILABS_DBUS_MODEM_DCLK(0x1, 0xc) +#define MODEM_DCLK_PB13 SILABS_DBUS_MODEM_DCLK(0x1, 0xd) +#define MODEM_DCLK_PB14 SILABS_DBUS_MODEM_DCLK(0x1, 0xe) +#define MODEM_DCLK_PB15 SILABS_DBUS_MODEM_DCLK(0x1, 0xf) +#define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0) +#define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1) +#define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2) +#define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3) +#define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4) +#define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5) +#define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6) +#define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7) +#define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8) +#define MODEM_DOUT_PA9 SILABS_DBUS_MODEM_DOUT(0x0, 0x9) +#define MODEM_DOUT_PA10 SILABS_DBUS_MODEM_DOUT(0x0, 0xa) +#define MODEM_DOUT_PA11 SILABS_DBUS_MODEM_DOUT(0x0, 0xb) +#define MODEM_DOUT_PA12 SILABS_DBUS_MODEM_DOUT(0x0, 0xc) +#define MODEM_DOUT_PA13 SILABS_DBUS_MODEM_DOUT(0x0, 0xd) +#define MODEM_DOUT_PA14 SILABS_DBUS_MODEM_DOUT(0x0, 0xe) +#define MODEM_DOUT_PA15 SILABS_DBUS_MODEM_DOUT(0x0, 0xf) +#define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0) +#define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1) +#define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2) +#define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3) +#define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4) +#define MODEM_DOUT_PB5 SILABS_DBUS_MODEM_DOUT(0x1, 0x5) +#define MODEM_DOUT_PB6 SILABS_DBUS_MODEM_DOUT(0x1, 0x6) +#define MODEM_DOUT_PB7 SILABS_DBUS_MODEM_DOUT(0x1, 0x7) +#define MODEM_DOUT_PB8 SILABS_DBUS_MODEM_DOUT(0x1, 0x8) +#define MODEM_DOUT_PB9 SILABS_DBUS_MODEM_DOUT(0x1, 0x9) +#define MODEM_DOUT_PB10 SILABS_DBUS_MODEM_DOUT(0x1, 0xa) +#define MODEM_DOUT_PB11 SILABS_DBUS_MODEM_DOUT(0x1, 0xb) +#define MODEM_DOUT_PB12 SILABS_DBUS_MODEM_DOUT(0x1, 0xc) +#define MODEM_DOUT_PB13 SILABS_DBUS_MODEM_DOUT(0x1, 0xd) +#define MODEM_DOUT_PB14 SILABS_DBUS_MODEM_DOUT(0x1, 0xe) +#define MODEM_DOUT_PB15 SILABS_DBUS_MODEM_DOUT(0x1, 0xf) +#define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0) +#define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1) +#define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2) +#define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3) +#define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4) +#define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5) +#define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6) +#define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7) +#define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8) +#define MODEM_DIN_PA9 SILABS_DBUS_MODEM_DIN(0x0, 0x9) +#define MODEM_DIN_PA10 SILABS_DBUS_MODEM_DIN(0x0, 0xa) +#define MODEM_DIN_PA11 SILABS_DBUS_MODEM_DIN(0x0, 0xb) +#define MODEM_DIN_PA12 SILABS_DBUS_MODEM_DIN(0x0, 0xc) +#define MODEM_DIN_PA13 SILABS_DBUS_MODEM_DIN(0x0, 0xd) +#define MODEM_DIN_PA14 SILABS_DBUS_MODEM_DIN(0x0, 0xe) +#define MODEM_DIN_PA15 SILABS_DBUS_MODEM_DIN(0x0, 0xf) +#define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0) +#define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1) +#define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2) +#define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3) +#define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4) +#define MODEM_DIN_PB5 SILABS_DBUS_MODEM_DIN(0x1, 0x5) +#define MODEM_DIN_PB6 SILABS_DBUS_MODEM_DIN(0x1, 0x6) +#define MODEM_DIN_PB7 SILABS_DBUS_MODEM_DIN(0x1, 0x7) +#define MODEM_DIN_PB8 SILABS_DBUS_MODEM_DIN(0x1, 0x8) +#define MODEM_DIN_PB9 SILABS_DBUS_MODEM_DIN(0x1, 0x9) +#define MODEM_DIN_PB10 SILABS_DBUS_MODEM_DIN(0x1, 0xa) +#define MODEM_DIN_PB11 SILABS_DBUS_MODEM_DIN(0x1, 0xb) +#define MODEM_DIN_PB12 SILABS_DBUS_MODEM_DIN(0x1, 0xc) +#define MODEM_DIN_PB13 SILABS_DBUS_MODEM_DIN(0x1, 0xd) +#define MODEM_DIN_PB14 SILABS_DBUS_MODEM_DIN(0x1, 0xe) +#define MODEM_DIN_PB15 SILABS_DBUS_MODEM_DIN(0x1, 0xf) + +#define PCNT0_S0IN_PA0 SILABS_DBUS_PCNT0_S0IN(0x0, 0x0) +#define PCNT0_S0IN_PA1 SILABS_DBUS_PCNT0_S0IN(0x0, 0x1) +#define PCNT0_S0IN_PA2 SILABS_DBUS_PCNT0_S0IN(0x0, 0x2) +#define PCNT0_S0IN_PA3 SILABS_DBUS_PCNT0_S0IN(0x0, 0x3) +#define PCNT0_S0IN_PA4 SILABS_DBUS_PCNT0_S0IN(0x0, 0x4) +#define PCNT0_S0IN_PA5 SILABS_DBUS_PCNT0_S0IN(0x0, 0x5) +#define PCNT0_S0IN_PA6 SILABS_DBUS_PCNT0_S0IN(0x0, 0x6) +#define PCNT0_S0IN_PA7 SILABS_DBUS_PCNT0_S0IN(0x0, 0x7) +#define PCNT0_S0IN_PA8 SILABS_DBUS_PCNT0_S0IN(0x0, 0x8) +#define PCNT0_S0IN_PA9 SILABS_DBUS_PCNT0_S0IN(0x0, 0x9) +#define PCNT0_S0IN_PA10 SILABS_DBUS_PCNT0_S0IN(0x0, 0xa) +#define PCNT0_S0IN_PA11 SILABS_DBUS_PCNT0_S0IN(0x0, 0xb) +#define PCNT0_S0IN_PA12 SILABS_DBUS_PCNT0_S0IN(0x0, 0xc) +#define PCNT0_S0IN_PA13 SILABS_DBUS_PCNT0_S0IN(0x0, 0xd) +#define PCNT0_S0IN_PA14 SILABS_DBUS_PCNT0_S0IN(0x0, 0xe) +#define PCNT0_S0IN_PA15 SILABS_DBUS_PCNT0_S0IN(0x0, 0xf) +#define PCNT0_S0IN_PB0 SILABS_DBUS_PCNT0_S0IN(0x1, 0x0) +#define PCNT0_S0IN_PB1 SILABS_DBUS_PCNT0_S0IN(0x1, 0x1) +#define PCNT0_S0IN_PB2 SILABS_DBUS_PCNT0_S0IN(0x1, 0x2) +#define PCNT0_S0IN_PB3 SILABS_DBUS_PCNT0_S0IN(0x1, 0x3) +#define PCNT0_S0IN_PB4 SILABS_DBUS_PCNT0_S0IN(0x1, 0x4) +#define PCNT0_S0IN_PB5 SILABS_DBUS_PCNT0_S0IN(0x1, 0x5) +#define PCNT0_S0IN_PB6 SILABS_DBUS_PCNT0_S0IN(0x1, 0x6) +#define PCNT0_S0IN_PB7 SILABS_DBUS_PCNT0_S0IN(0x1, 0x7) +#define PCNT0_S0IN_PB8 SILABS_DBUS_PCNT0_S0IN(0x1, 0x8) +#define PCNT0_S0IN_PB9 SILABS_DBUS_PCNT0_S0IN(0x1, 0x9) +#define PCNT0_S0IN_PB10 SILABS_DBUS_PCNT0_S0IN(0x1, 0xa) +#define PCNT0_S0IN_PB11 SILABS_DBUS_PCNT0_S0IN(0x1, 0xb) +#define PCNT0_S0IN_PB12 SILABS_DBUS_PCNT0_S0IN(0x1, 0xc) +#define PCNT0_S0IN_PB13 SILABS_DBUS_PCNT0_S0IN(0x1, 0xd) +#define PCNT0_S0IN_PB14 SILABS_DBUS_PCNT0_S0IN(0x1, 0xe) +#define PCNT0_S0IN_PB15 SILABS_DBUS_PCNT0_S0IN(0x1, 0xf) +#define PCNT0_S1IN_PA0 SILABS_DBUS_PCNT0_S1IN(0x0, 0x0) +#define PCNT0_S1IN_PA1 SILABS_DBUS_PCNT0_S1IN(0x0, 0x1) +#define PCNT0_S1IN_PA2 SILABS_DBUS_PCNT0_S1IN(0x0, 0x2) +#define PCNT0_S1IN_PA3 SILABS_DBUS_PCNT0_S1IN(0x0, 0x3) +#define PCNT0_S1IN_PA4 SILABS_DBUS_PCNT0_S1IN(0x0, 0x4) +#define PCNT0_S1IN_PA5 SILABS_DBUS_PCNT0_S1IN(0x0, 0x5) +#define PCNT0_S1IN_PA6 SILABS_DBUS_PCNT0_S1IN(0x0, 0x6) +#define PCNT0_S1IN_PA7 SILABS_DBUS_PCNT0_S1IN(0x0, 0x7) +#define PCNT0_S1IN_PA8 SILABS_DBUS_PCNT0_S1IN(0x0, 0x8) +#define PCNT0_S1IN_PA9 SILABS_DBUS_PCNT0_S1IN(0x0, 0x9) +#define PCNT0_S1IN_PA10 SILABS_DBUS_PCNT0_S1IN(0x0, 0xa) +#define PCNT0_S1IN_PA11 SILABS_DBUS_PCNT0_S1IN(0x0, 0xb) +#define PCNT0_S1IN_PA12 SILABS_DBUS_PCNT0_S1IN(0x0, 0xc) +#define PCNT0_S1IN_PA13 SILABS_DBUS_PCNT0_S1IN(0x0, 0xd) +#define PCNT0_S1IN_PA14 SILABS_DBUS_PCNT0_S1IN(0x0, 0xe) +#define PCNT0_S1IN_PA15 SILABS_DBUS_PCNT0_S1IN(0x0, 0xf) +#define PCNT0_S1IN_PB0 SILABS_DBUS_PCNT0_S1IN(0x1, 0x0) +#define PCNT0_S1IN_PB1 SILABS_DBUS_PCNT0_S1IN(0x1, 0x1) +#define PCNT0_S1IN_PB2 SILABS_DBUS_PCNT0_S1IN(0x1, 0x2) +#define PCNT0_S1IN_PB3 SILABS_DBUS_PCNT0_S1IN(0x1, 0x3) +#define PCNT0_S1IN_PB4 SILABS_DBUS_PCNT0_S1IN(0x1, 0x4) +#define PCNT0_S1IN_PB5 SILABS_DBUS_PCNT0_S1IN(0x1, 0x5) +#define PCNT0_S1IN_PB6 SILABS_DBUS_PCNT0_S1IN(0x1, 0x6) +#define PCNT0_S1IN_PB7 SILABS_DBUS_PCNT0_S1IN(0x1, 0x7) +#define PCNT0_S1IN_PB8 SILABS_DBUS_PCNT0_S1IN(0x1, 0x8) +#define PCNT0_S1IN_PB9 SILABS_DBUS_PCNT0_S1IN(0x1, 0x9) +#define PCNT0_S1IN_PB10 SILABS_DBUS_PCNT0_S1IN(0x1, 0xa) +#define PCNT0_S1IN_PB11 SILABS_DBUS_PCNT0_S1IN(0x1, 0xb) +#define PCNT0_S1IN_PB12 SILABS_DBUS_PCNT0_S1IN(0x1, 0xc) +#define PCNT0_S1IN_PB13 SILABS_DBUS_PCNT0_S1IN(0x1, 0xd) +#define PCNT0_S1IN_PB14 SILABS_DBUS_PCNT0_S1IN(0x1, 0xe) +#define PCNT0_S1IN_PB15 SILABS_DBUS_PCNT0_S1IN(0x1, 0xf) + +#define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0) +#define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1) +#define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2) +#define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3) +#define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4) +#define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5) +#define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6) +#define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7) +#define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8) +#define PRS0_ASYNCH0_PA9 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x9) +#define PRS0_ASYNCH0_PA10 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xa) +#define PRS0_ASYNCH0_PA11 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xb) +#define PRS0_ASYNCH0_PA12 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xc) +#define PRS0_ASYNCH0_PA13 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xd) +#define PRS0_ASYNCH0_PA14 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xe) +#define PRS0_ASYNCH0_PA15 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xf) +#define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0) +#define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1) +#define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2) +#define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3) +#define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4) +#define PRS0_ASYNCH0_PB5 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x5) +#define PRS0_ASYNCH0_PB6 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x6) +#define PRS0_ASYNCH0_PB7 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x7) +#define PRS0_ASYNCH0_PB8 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x8) +#define PRS0_ASYNCH0_PB9 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x9) +#define PRS0_ASYNCH0_PB10 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0xa) +#define PRS0_ASYNCH0_PB11 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0xb) +#define PRS0_ASYNCH0_PB12 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0xc) +#define PRS0_ASYNCH0_PB13 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0xd) +#define PRS0_ASYNCH0_PB14 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0xe) +#define PRS0_ASYNCH0_PB15 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0xf) +#define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0) +#define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1) +#define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2) +#define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3) +#define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4) +#define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5) +#define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6) +#define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7) +#define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8) +#define PRS0_ASYNCH1_PA9 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x9) +#define PRS0_ASYNCH1_PA10 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xa) +#define PRS0_ASYNCH1_PA11 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xb) +#define PRS0_ASYNCH1_PA12 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xc) +#define PRS0_ASYNCH1_PA13 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xd) +#define PRS0_ASYNCH1_PA14 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xe) +#define PRS0_ASYNCH1_PA15 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xf) +#define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0) +#define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1) +#define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2) +#define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3) +#define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4) +#define PRS0_ASYNCH1_PB5 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x5) +#define PRS0_ASYNCH1_PB6 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x6) +#define PRS0_ASYNCH1_PB7 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x7) +#define PRS0_ASYNCH1_PB8 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x8) +#define PRS0_ASYNCH1_PB9 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x9) +#define PRS0_ASYNCH1_PB10 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0xa) +#define PRS0_ASYNCH1_PB11 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0xb) +#define PRS0_ASYNCH1_PB12 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0xc) +#define PRS0_ASYNCH1_PB13 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0xd) +#define PRS0_ASYNCH1_PB14 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0xe) +#define PRS0_ASYNCH1_PB15 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0xf) +#define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0) +#define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1) +#define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2) +#define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3) +#define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4) +#define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5) +#define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6) +#define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7) +#define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8) +#define PRS0_ASYNCH2_PA9 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x9) +#define PRS0_ASYNCH2_PA10 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xa) +#define PRS0_ASYNCH2_PA11 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xb) +#define PRS0_ASYNCH2_PA12 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xc) +#define PRS0_ASYNCH2_PA13 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xd) +#define PRS0_ASYNCH2_PA14 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xe) +#define PRS0_ASYNCH2_PA15 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xf) +#define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0) +#define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1) +#define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2) +#define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3) +#define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4) +#define PRS0_ASYNCH2_PB5 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x5) +#define PRS0_ASYNCH2_PB6 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x6) +#define PRS0_ASYNCH2_PB7 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x7) +#define PRS0_ASYNCH2_PB8 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x8) +#define PRS0_ASYNCH2_PB9 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x9) +#define PRS0_ASYNCH2_PB10 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0xa) +#define PRS0_ASYNCH2_PB11 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0xb) +#define PRS0_ASYNCH2_PB12 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0xc) +#define PRS0_ASYNCH2_PB13 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0xd) +#define PRS0_ASYNCH2_PB14 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0xe) +#define PRS0_ASYNCH2_PB15 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0xf) +#define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0) +#define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1) +#define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2) +#define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3) +#define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4) +#define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5) +#define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6) +#define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7) +#define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8) +#define PRS0_ASYNCH3_PA9 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x9) +#define PRS0_ASYNCH3_PA10 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xa) +#define PRS0_ASYNCH3_PA11 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xb) +#define PRS0_ASYNCH3_PA12 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xc) +#define PRS0_ASYNCH3_PA13 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xd) +#define PRS0_ASYNCH3_PA14 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xe) +#define PRS0_ASYNCH3_PA15 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xf) +#define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0) +#define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1) +#define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2) +#define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3) +#define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4) +#define PRS0_ASYNCH3_PB5 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x5) +#define PRS0_ASYNCH3_PB6 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x6) +#define PRS0_ASYNCH3_PB7 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x7) +#define PRS0_ASYNCH3_PB8 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x8) +#define PRS0_ASYNCH3_PB9 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x9) +#define PRS0_ASYNCH3_PB10 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0xa) +#define PRS0_ASYNCH3_PB11 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0xb) +#define PRS0_ASYNCH3_PB12 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0xc) +#define PRS0_ASYNCH3_PB13 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0xd) +#define PRS0_ASYNCH3_PB14 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0xe) +#define PRS0_ASYNCH3_PB15 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0xf) +#define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0) +#define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1) +#define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2) +#define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3) +#define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4) +#define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5) +#define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6) +#define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7) +#define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8) +#define PRS0_ASYNCH4_PA9 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x9) +#define PRS0_ASYNCH4_PA10 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xa) +#define PRS0_ASYNCH4_PA11 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xb) +#define PRS0_ASYNCH4_PA12 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xc) +#define PRS0_ASYNCH4_PA13 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xd) +#define PRS0_ASYNCH4_PA14 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xe) +#define PRS0_ASYNCH4_PA15 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xf) +#define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0) +#define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1) +#define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2) +#define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3) +#define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4) +#define PRS0_ASYNCH4_PB5 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x5) +#define PRS0_ASYNCH4_PB6 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x6) +#define PRS0_ASYNCH4_PB7 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x7) +#define PRS0_ASYNCH4_PB8 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x8) +#define PRS0_ASYNCH4_PB9 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x9) +#define PRS0_ASYNCH4_PB10 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0xa) +#define PRS0_ASYNCH4_PB11 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0xb) +#define PRS0_ASYNCH4_PB12 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0xc) +#define PRS0_ASYNCH4_PB13 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0xd) +#define PRS0_ASYNCH4_PB14 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0xe) +#define PRS0_ASYNCH4_PB15 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0xf) +#define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0) +#define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1) +#define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2) +#define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3) +#define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4) +#define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5) +#define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6) +#define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7) +#define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8) +#define PRS0_ASYNCH5_PA9 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x9) +#define PRS0_ASYNCH5_PA10 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xa) +#define PRS0_ASYNCH5_PA11 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xb) +#define PRS0_ASYNCH5_PA12 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xc) +#define PRS0_ASYNCH5_PA13 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xd) +#define PRS0_ASYNCH5_PA14 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xe) +#define PRS0_ASYNCH5_PA15 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xf) +#define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0) +#define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1) +#define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2) +#define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3) +#define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4) +#define PRS0_ASYNCH5_PB5 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x5) +#define PRS0_ASYNCH5_PB6 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x6) +#define PRS0_ASYNCH5_PB7 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x7) +#define PRS0_ASYNCH5_PB8 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x8) +#define PRS0_ASYNCH5_PB9 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x9) +#define PRS0_ASYNCH5_PB10 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0xa) +#define PRS0_ASYNCH5_PB11 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0xb) +#define PRS0_ASYNCH5_PB12 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0xc) +#define PRS0_ASYNCH5_PB13 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0xd) +#define PRS0_ASYNCH5_PB14 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0xe) +#define PRS0_ASYNCH5_PB15 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0xf) +#define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0) +#define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1) +#define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2) +#define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3) +#define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4) +#define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5) +#define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6) +#define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7) +#define PRS0_ASYNCH6_PC8 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x8) +#define PRS0_ASYNCH6_PC9 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x9) +#define PRS0_ASYNCH6_PC10 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0xa) +#define PRS0_ASYNCH6_PC11 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0xb) +#define PRS0_ASYNCH6_PC12 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0xc) +#define PRS0_ASYNCH6_PC13 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0xd) +#define PRS0_ASYNCH6_PC14 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0xe) +#define PRS0_ASYNCH6_PC15 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0xf) +#define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0) +#define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1) +#define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2) +#define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3) +#define PRS0_ASYNCH6_PD4 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x4) +#define PRS0_ASYNCH6_PD5 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x5) +#define PRS0_ASYNCH6_PD6 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x6) +#define PRS0_ASYNCH6_PD7 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x7) +#define PRS0_ASYNCH6_PD8 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x8) +#define PRS0_ASYNCH6_PD9 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x9) +#define PRS0_ASYNCH6_PD10 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xa) +#define PRS0_ASYNCH6_PD11 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xb) +#define PRS0_ASYNCH6_PD12 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xc) +#define PRS0_ASYNCH6_PD13 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xd) +#define PRS0_ASYNCH6_PD14 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xe) +#define PRS0_ASYNCH6_PD15 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xf) +#define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0) +#define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1) +#define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2) +#define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3) +#define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4) +#define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5) +#define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6) +#define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7) +#define PRS0_ASYNCH7_PC8 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x8) +#define PRS0_ASYNCH7_PC9 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x9) +#define PRS0_ASYNCH7_PC10 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0xa) +#define PRS0_ASYNCH7_PC11 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0xb) +#define PRS0_ASYNCH7_PC12 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0xc) +#define PRS0_ASYNCH7_PC13 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0xd) +#define PRS0_ASYNCH7_PC14 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0xe) +#define PRS0_ASYNCH7_PC15 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0xf) +#define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0) +#define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1) +#define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2) +#define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3) +#define PRS0_ASYNCH7_PD4 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x4) +#define PRS0_ASYNCH7_PD5 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x5) +#define PRS0_ASYNCH7_PD6 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x6) +#define PRS0_ASYNCH7_PD7 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x7) +#define PRS0_ASYNCH7_PD8 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x8) +#define PRS0_ASYNCH7_PD9 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x9) +#define PRS0_ASYNCH7_PD10 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xa) +#define PRS0_ASYNCH7_PD11 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xb) +#define PRS0_ASYNCH7_PD12 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xc) +#define PRS0_ASYNCH7_PD13 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xd) +#define PRS0_ASYNCH7_PD14 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xe) +#define PRS0_ASYNCH7_PD15 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xf) +#define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0) +#define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1) +#define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2) +#define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3) +#define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4) +#define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5) +#define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6) +#define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7) +#define PRS0_ASYNCH8_PC8 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x8) +#define PRS0_ASYNCH8_PC9 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x9) +#define PRS0_ASYNCH8_PC10 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0xa) +#define PRS0_ASYNCH8_PC11 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0xb) +#define PRS0_ASYNCH8_PC12 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0xc) +#define PRS0_ASYNCH8_PC13 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0xd) +#define PRS0_ASYNCH8_PC14 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0xe) +#define PRS0_ASYNCH8_PC15 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0xf) +#define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0) +#define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1) +#define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2) +#define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3) +#define PRS0_ASYNCH8_PD4 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x4) +#define PRS0_ASYNCH8_PD5 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x5) +#define PRS0_ASYNCH8_PD6 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x6) +#define PRS0_ASYNCH8_PD7 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x7) +#define PRS0_ASYNCH8_PD8 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x8) +#define PRS0_ASYNCH8_PD9 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x9) +#define PRS0_ASYNCH8_PD10 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xa) +#define PRS0_ASYNCH8_PD11 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xb) +#define PRS0_ASYNCH8_PD12 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xc) +#define PRS0_ASYNCH8_PD13 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xd) +#define PRS0_ASYNCH8_PD14 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xe) +#define PRS0_ASYNCH8_PD15 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xf) +#define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0) +#define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1) +#define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2) +#define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3) +#define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4) +#define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5) +#define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6) +#define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7) +#define PRS0_ASYNCH9_PC8 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x8) +#define PRS0_ASYNCH9_PC9 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x9) +#define PRS0_ASYNCH9_PC10 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0xa) +#define PRS0_ASYNCH9_PC11 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0xb) +#define PRS0_ASYNCH9_PC12 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0xc) +#define PRS0_ASYNCH9_PC13 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0xd) +#define PRS0_ASYNCH9_PC14 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0xe) +#define PRS0_ASYNCH9_PC15 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0xf) +#define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0) +#define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1) +#define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2) +#define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3) +#define PRS0_ASYNCH9_PD4 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x4) +#define PRS0_ASYNCH9_PD5 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x5) +#define PRS0_ASYNCH9_PD6 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x6) +#define PRS0_ASYNCH9_PD7 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x7) +#define PRS0_ASYNCH9_PD8 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x8) +#define PRS0_ASYNCH9_PD9 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x9) +#define PRS0_ASYNCH9_PD10 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xa) +#define PRS0_ASYNCH9_PD11 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xb) +#define PRS0_ASYNCH9_PD12 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xc) +#define PRS0_ASYNCH9_PD13 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xd) +#define PRS0_ASYNCH9_PD14 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xe) +#define PRS0_ASYNCH9_PD15 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xf) +#define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0) +#define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1) +#define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2) +#define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3) +#define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4) +#define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5) +#define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6) +#define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7) +#define PRS0_ASYNCH10_PC8 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x8) +#define PRS0_ASYNCH10_PC9 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x9) +#define PRS0_ASYNCH10_PC10 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0xa) +#define PRS0_ASYNCH10_PC11 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0xb) +#define PRS0_ASYNCH10_PC12 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0xc) +#define PRS0_ASYNCH10_PC13 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0xd) +#define PRS0_ASYNCH10_PC14 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0xe) +#define PRS0_ASYNCH10_PC15 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0xf) +#define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0) +#define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1) +#define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2) +#define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3) +#define PRS0_ASYNCH10_PD4 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x4) +#define PRS0_ASYNCH10_PD5 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x5) +#define PRS0_ASYNCH10_PD6 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x6) +#define PRS0_ASYNCH10_PD7 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x7) +#define PRS0_ASYNCH10_PD8 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x8) +#define PRS0_ASYNCH10_PD9 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x9) +#define PRS0_ASYNCH10_PD10 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xa) +#define PRS0_ASYNCH10_PD11 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xb) +#define PRS0_ASYNCH10_PD12 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xc) +#define PRS0_ASYNCH10_PD13 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xd) +#define PRS0_ASYNCH10_PD14 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xe) +#define PRS0_ASYNCH10_PD15 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xf) +#define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0) +#define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1) +#define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2) +#define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3) +#define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4) +#define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5) +#define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6) +#define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7) +#define PRS0_ASYNCH11_PC8 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x8) +#define PRS0_ASYNCH11_PC9 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x9) +#define PRS0_ASYNCH11_PC10 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0xa) +#define PRS0_ASYNCH11_PC11 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0xb) +#define PRS0_ASYNCH11_PC12 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0xc) +#define PRS0_ASYNCH11_PC13 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0xd) +#define PRS0_ASYNCH11_PC14 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0xe) +#define PRS0_ASYNCH11_PC15 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0xf) +#define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0) +#define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1) +#define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2) +#define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3) +#define PRS0_ASYNCH11_PD4 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x4) +#define PRS0_ASYNCH11_PD5 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x5) +#define PRS0_ASYNCH11_PD6 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x6) +#define PRS0_ASYNCH11_PD7 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x7) +#define PRS0_ASYNCH11_PD8 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x8) +#define PRS0_ASYNCH11_PD9 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x9) +#define PRS0_ASYNCH11_PD10 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xa) +#define PRS0_ASYNCH11_PD11 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xb) +#define PRS0_ASYNCH11_PD12 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xc) +#define PRS0_ASYNCH11_PD13 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xd) +#define PRS0_ASYNCH11_PD14 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xe) +#define PRS0_ASYNCH11_PD15 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xf) +#define PRS0_ASYNCH12_PA0 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x0) +#define PRS0_ASYNCH12_PA1 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x1) +#define PRS0_ASYNCH12_PA2 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x2) +#define PRS0_ASYNCH12_PA3 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x3) +#define PRS0_ASYNCH12_PA4 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x4) +#define PRS0_ASYNCH12_PA5 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x5) +#define PRS0_ASYNCH12_PA6 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x6) +#define PRS0_ASYNCH12_PA7 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x7) +#define PRS0_ASYNCH12_PA8 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x8) +#define PRS0_ASYNCH12_PA9 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x9) +#define PRS0_ASYNCH12_PA10 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0xa) +#define PRS0_ASYNCH12_PA11 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0xb) +#define PRS0_ASYNCH12_PA12 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0xc) +#define PRS0_ASYNCH12_PA13 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0xd) +#define PRS0_ASYNCH12_PA14 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0xe) +#define PRS0_ASYNCH12_PA15 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0xf) +#define PRS0_ASYNCH12_PB0 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x0) +#define PRS0_ASYNCH12_PB1 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x1) +#define PRS0_ASYNCH12_PB2 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x2) +#define PRS0_ASYNCH12_PB3 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x3) +#define PRS0_ASYNCH12_PB4 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x4) +#define PRS0_ASYNCH12_PB5 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x5) +#define PRS0_ASYNCH12_PB6 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x6) +#define PRS0_ASYNCH12_PB7 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x7) +#define PRS0_ASYNCH12_PB8 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x8) +#define PRS0_ASYNCH12_PB9 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x9) +#define PRS0_ASYNCH12_PB10 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0xa) +#define PRS0_ASYNCH12_PB11 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0xb) +#define PRS0_ASYNCH12_PB12 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0xc) +#define PRS0_ASYNCH12_PB13 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0xd) +#define PRS0_ASYNCH12_PB14 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0xe) +#define PRS0_ASYNCH12_PB15 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0xf) +#define PRS0_ASYNCH13_PA0 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x0) +#define PRS0_ASYNCH13_PA1 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x1) +#define PRS0_ASYNCH13_PA2 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x2) +#define PRS0_ASYNCH13_PA3 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x3) +#define PRS0_ASYNCH13_PA4 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x4) +#define PRS0_ASYNCH13_PA5 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x5) +#define PRS0_ASYNCH13_PA6 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x6) +#define PRS0_ASYNCH13_PA7 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x7) +#define PRS0_ASYNCH13_PA8 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x8) +#define PRS0_ASYNCH13_PA9 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x9) +#define PRS0_ASYNCH13_PA10 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0xa) +#define PRS0_ASYNCH13_PA11 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0xb) +#define PRS0_ASYNCH13_PA12 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0xc) +#define PRS0_ASYNCH13_PA13 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0xd) +#define PRS0_ASYNCH13_PA14 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0xe) +#define PRS0_ASYNCH13_PA15 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0xf) +#define PRS0_ASYNCH13_PB0 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x0) +#define PRS0_ASYNCH13_PB1 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x1) +#define PRS0_ASYNCH13_PB2 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x2) +#define PRS0_ASYNCH13_PB3 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x3) +#define PRS0_ASYNCH13_PB4 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x4) +#define PRS0_ASYNCH13_PB5 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x5) +#define PRS0_ASYNCH13_PB6 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x6) +#define PRS0_ASYNCH13_PB7 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x7) +#define PRS0_ASYNCH13_PB8 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x8) +#define PRS0_ASYNCH13_PB9 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x9) +#define PRS0_ASYNCH13_PB10 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0xa) +#define PRS0_ASYNCH13_PB11 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0xb) +#define PRS0_ASYNCH13_PB12 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0xc) +#define PRS0_ASYNCH13_PB13 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0xd) +#define PRS0_ASYNCH13_PB14 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0xe) +#define PRS0_ASYNCH13_PB15 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0xf) +#define PRS0_ASYNCH14_PA0 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x0) +#define PRS0_ASYNCH14_PA1 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x1) +#define PRS0_ASYNCH14_PA2 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x2) +#define PRS0_ASYNCH14_PA3 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x3) +#define PRS0_ASYNCH14_PA4 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x4) +#define PRS0_ASYNCH14_PA5 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x5) +#define PRS0_ASYNCH14_PA6 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x6) +#define PRS0_ASYNCH14_PA7 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x7) +#define PRS0_ASYNCH14_PA8 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x8) +#define PRS0_ASYNCH14_PA9 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x9) +#define PRS0_ASYNCH14_PA10 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0xa) +#define PRS0_ASYNCH14_PA11 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0xb) +#define PRS0_ASYNCH14_PA12 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0xc) +#define PRS0_ASYNCH14_PA13 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0xd) +#define PRS0_ASYNCH14_PA14 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0xe) +#define PRS0_ASYNCH14_PA15 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0xf) +#define PRS0_ASYNCH14_PB0 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x0) +#define PRS0_ASYNCH14_PB1 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x1) +#define PRS0_ASYNCH14_PB2 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x2) +#define PRS0_ASYNCH14_PB3 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x3) +#define PRS0_ASYNCH14_PB4 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x4) +#define PRS0_ASYNCH14_PB5 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x5) +#define PRS0_ASYNCH14_PB6 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x6) +#define PRS0_ASYNCH14_PB7 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x7) +#define PRS0_ASYNCH14_PB8 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x8) +#define PRS0_ASYNCH14_PB9 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x9) +#define PRS0_ASYNCH14_PB10 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0xa) +#define PRS0_ASYNCH14_PB11 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0xb) +#define PRS0_ASYNCH14_PB12 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0xc) +#define PRS0_ASYNCH14_PB13 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0xd) +#define PRS0_ASYNCH14_PB14 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0xe) +#define PRS0_ASYNCH14_PB15 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0xf) +#define PRS0_ASYNCH15_PA0 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x0) +#define PRS0_ASYNCH15_PA1 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x1) +#define PRS0_ASYNCH15_PA2 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x2) +#define PRS0_ASYNCH15_PA3 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x3) +#define PRS0_ASYNCH15_PA4 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x4) +#define PRS0_ASYNCH15_PA5 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x5) +#define PRS0_ASYNCH15_PA6 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x6) +#define PRS0_ASYNCH15_PA7 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x7) +#define PRS0_ASYNCH15_PA8 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x8) +#define PRS0_ASYNCH15_PA9 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x9) +#define PRS0_ASYNCH15_PA10 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0xa) +#define PRS0_ASYNCH15_PA11 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0xb) +#define PRS0_ASYNCH15_PA12 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0xc) +#define PRS0_ASYNCH15_PA13 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0xd) +#define PRS0_ASYNCH15_PA14 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0xe) +#define PRS0_ASYNCH15_PA15 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0xf) +#define PRS0_ASYNCH15_PB0 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x0) +#define PRS0_ASYNCH15_PB1 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x1) +#define PRS0_ASYNCH15_PB2 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x2) +#define PRS0_ASYNCH15_PB3 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x3) +#define PRS0_ASYNCH15_PB4 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x4) +#define PRS0_ASYNCH15_PB5 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x5) +#define PRS0_ASYNCH15_PB6 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x6) +#define PRS0_ASYNCH15_PB7 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x7) +#define PRS0_ASYNCH15_PB8 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x8) +#define PRS0_ASYNCH15_PB9 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x9) +#define PRS0_ASYNCH15_PB10 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0xa) +#define PRS0_ASYNCH15_PB11 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0xb) +#define PRS0_ASYNCH15_PB12 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0xc) +#define PRS0_ASYNCH15_PB13 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0xd) +#define PRS0_ASYNCH15_PB14 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0xe) +#define PRS0_ASYNCH15_PB15 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0xf) +#define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0) +#define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1) +#define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2) +#define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3) +#define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4) +#define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5) +#define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6) +#define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7) +#define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8) +#define PRS0_SYNCH0_PA9 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x9) +#define PRS0_SYNCH0_PA10 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xa) +#define PRS0_SYNCH0_PA11 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xb) +#define PRS0_SYNCH0_PA12 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xc) +#define PRS0_SYNCH0_PA13 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xd) +#define PRS0_SYNCH0_PA14 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xe) +#define PRS0_SYNCH0_PA15 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xf) +#define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0) +#define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1) +#define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2) +#define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3) +#define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4) +#define PRS0_SYNCH0_PB5 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x5) +#define PRS0_SYNCH0_PB6 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x6) +#define PRS0_SYNCH0_PB7 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x7) +#define PRS0_SYNCH0_PB8 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x8) +#define PRS0_SYNCH0_PB9 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x9) +#define PRS0_SYNCH0_PB10 SILABS_DBUS_PRS0_SYNCH0(0x1, 0xa) +#define PRS0_SYNCH0_PB11 SILABS_DBUS_PRS0_SYNCH0(0x1, 0xb) +#define PRS0_SYNCH0_PB12 SILABS_DBUS_PRS0_SYNCH0(0x1, 0xc) +#define PRS0_SYNCH0_PB13 SILABS_DBUS_PRS0_SYNCH0(0x1, 0xd) +#define PRS0_SYNCH0_PB14 SILABS_DBUS_PRS0_SYNCH0(0x1, 0xe) +#define PRS0_SYNCH0_PB15 SILABS_DBUS_PRS0_SYNCH0(0x1, 0xf) +#define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0) +#define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1) +#define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2) +#define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3) +#define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4) +#define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5) +#define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6) +#define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7) +#define PRS0_SYNCH0_PC8 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x8) +#define PRS0_SYNCH0_PC9 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x9) +#define PRS0_SYNCH0_PC10 SILABS_DBUS_PRS0_SYNCH0(0x2, 0xa) +#define PRS0_SYNCH0_PC11 SILABS_DBUS_PRS0_SYNCH0(0x2, 0xb) +#define PRS0_SYNCH0_PC12 SILABS_DBUS_PRS0_SYNCH0(0x2, 0xc) +#define PRS0_SYNCH0_PC13 SILABS_DBUS_PRS0_SYNCH0(0x2, 0xd) +#define PRS0_SYNCH0_PC14 SILABS_DBUS_PRS0_SYNCH0(0x2, 0xe) +#define PRS0_SYNCH0_PC15 SILABS_DBUS_PRS0_SYNCH0(0x2, 0xf) +#define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0) +#define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1) +#define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2) +#define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3) +#define PRS0_SYNCH0_PD4 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x4) +#define PRS0_SYNCH0_PD5 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x5) +#define PRS0_SYNCH0_PD6 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x6) +#define PRS0_SYNCH0_PD7 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x7) +#define PRS0_SYNCH0_PD8 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x8) +#define PRS0_SYNCH0_PD9 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x9) +#define PRS0_SYNCH0_PD10 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xa) +#define PRS0_SYNCH0_PD11 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xb) +#define PRS0_SYNCH0_PD12 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xc) +#define PRS0_SYNCH0_PD13 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xd) +#define PRS0_SYNCH0_PD14 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xe) +#define PRS0_SYNCH0_PD15 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xf) +#define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0) +#define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1) +#define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2) +#define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3) +#define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4) +#define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5) +#define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6) +#define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7) +#define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8) +#define PRS0_SYNCH1_PA9 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x9) +#define PRS0_SYNCH1_PA10 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xa) +#define PRS0_SYNCH1_PA11 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xb) +#define PRS0_SYNCH1_PA12 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xc) +#define PRS0_SYNCH1_PA13 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xd) +#define PRS0_SYNCH1_PA14 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xe) +#define PRS0_SYNCH1_PA15 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xf) +#define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0) +#define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1) +#define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2) +#define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3) +#define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4) +#define PRS0_SYNCH1_PB5 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x5) +#define PRS0_SYNCH1_PB6 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x6) +#define PRS0_SYNCH1_PB7 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x7) +#define PRS0_SYNCH1_PB8 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x8) +#define PRS0_SYNCH1_PB9 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x9) +#define PRS0_SYNCH1_PB10 SILABS_DBUS_PRS0_SYNCH1(0x1, 0xa) +#define PRS0_SYNCH1_PB11 SILABS_DBUS_PRS0_SYNCH1(0x1, 0xb) +#define PRS0_SYNCH1_PB12 SILABS_DBUS_PRS0_SYNCH1(0x1, 0xc) +#define PRS0_SYNCH1_PB13 SILABS_DBUS_PRS0_SYNCH1(0x1, 0xd) +#define PRS0_SYNCH1_PB14 SILABS_DBUS_PRS0_SYNCH1(0x1, 0xe) +#define PRS0_SYNCH1_PB15 SILABS_DBUS_PRS0_SYNCH1(0x1, 0xf) +#define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0) +#define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1) +#define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2) +#define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3) +#define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4) +#define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5) +#define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6) +#define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7) +#define PRS0_SYNCH1_PC8 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x8) +#define PRS0_SYNCH1_PC9 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x9) +#define PRS0_SYNCH1_PC10 SILABS_DBUS_PRS0_SYNCH1(0x2, 0xa) +#define PRS0_SYNCH1_PC11 SILABS_DBUS_PRS0_SYNCH1(0x2, 0xb) +#define PRS0_SYNCH1_PC12 SILABS_DBUS_PRS0_SYNCH1(0x2, 0xc) +#define PRS0_SYNCH1_PC13 SILABS_DBUS_PRS0_SYNCH1(0x2, 0xd) +#define PRS0_SYNCH1_PC14 SILABS_DBUS_PRS0_SYNCH1(0x2, 0xe) +#define PRS0_SYNCH1_PC15 SILABS_DBUS_PRS0_SYNCH1(0x2, 0xf) +#define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0) +#define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1) +#define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2) +#define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3) +#define PRS0_SYNCH1_PD4 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x4) +#define PRS0_SYNCH1_PD5 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x5) +#define PRS0_SYNCH1_PD6 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x6) +#define PRS0_SYNCH1_PD7 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x7) +#define PRS0_SYNCH1_PD8 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x8) +#define PRS0_SYNCH1_PD9 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x9) +#define PRS0_SYNCH1_PD10 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xa) +#define PRS0_SYNCH1_PD11 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xb) +#define PRS0_SYNCH1_PD12 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xc) +#define PRS0_SYNCH1_PD13 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xd) +#define PRS0_SYNCH1_PD14 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xe) +#define PRS0_SYNCH1_PD15 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xf) +#define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0) +#define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1) +#define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2) +#define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3) +#define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4) +#define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5) +#define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6) +#define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7) +#define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8) +#define PRS0_SYNCH2_PA9 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x9) +#define PRS0_SYNCH2_PA10 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xa) +#define PRS0_SYNCH2_PA11 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xb) +#define PRS0_SYNCH2_PA12 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xc) +#define PRS0_SYNCH2_PA13 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xd) +#define PRS0_SYNCH2_PA14 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xe) +#define PRS0_SYNCH2_PA15 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xf) +#define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0) +#define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1) +#define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2) +#define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3) +#define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4) +#define PRS0_SYNCH2_PB5 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x5) +#define PRS0_SYNCH2_PB6 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x6) +#define PRS0_SYNCH2_PB7 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x7) +#define PRS0_SYNCH2_PB8 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x8) +#define PRS0_SYNCH2_PB9 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x9) +#define PRS0_SYNCH2_PB10 SILABS_DBUS_PRS0_SYNCH2(0x1, 0xa) +#define PRS0_SYNCH2_PB11 SILABS_DBUS_PRS0_SYNCH2(0x1, 0xb) +#define PRS0_SYNCH2_PB12 SILABS_DBUS_PRS0_SYNCH2(0x1, 0xc) +#define PRS0_SYNCH2_PB13 SILABS_DBUS_PRS0_SYNCH2(0x1, 0xd) +#define PRS0_SYNCH2_PB14 SILABS_DBUS_PRS0_SYNCH2(0x1, 0xe) +#define PRS0_SYNCH2_PB15 SILABS_DBUS_PRS0_SYNCH2(0x1, 0xf) +#define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0) +#define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1) +#define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2) +#define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3) +#define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4) +#define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5) +#define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6) +#define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7) +#define PRS0_SYNCH2_PC8 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x8) +#define PRS0_SYNCH2_PC9 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x9) +#define PRS0_SYNCH2_PC10 SILABS_DBUS_PRS0_SYNCH2(0x2, 0xa) +#define PRS0_SYNCH2_PC11 SILABS_DBUS_PRS0_SYNCH2(0x2, 0xb) +#define PRS0_SYNCH2_PC12 SILABS_DBUS_PRS0_SYNCH2(0x2, 0xc) +#define PRS0_SYNCH2_PC13 SILABS_DBUS_PRS0_SYNCH2(0x2, 0xd) +#define PRS0_SYNCH2_PC14 SILABS_DBUS_PRS0_SYNCH2(0x2, 0xe) +#define PRS0_SYNCH2_PC15 SILABS_DBUS_PRS0_SYNCH2(0x2, 0xf) +#define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0) +#define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1) +#define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2) +#define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3) +#define PRS0_SYNCH2_PD4 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x4) +#define PRS0_SYNCH2_PD5 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x5) +#define PRS0_SYNCH2_PD6 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x6) +#define PRS0_SYNCH2_PD7 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x7) +#define PRS0_SYNCH2_PD8 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x8) +#define PRS0_SYNCH2_PD9 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x9) +#define PRS0_SYNCH2_PD10 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xa) +#define PRS0_SYNCH2_PD11 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xb) +#define PRS0_SYNCH2_PD12 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xc) +#define PRS0_SYNCH2_PD13 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xd) +#define PRS0_SYNCH2_PD14 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xe) +#define PRS0_SYNCH2_PD15 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xf) +#define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0) +#define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1) +#define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2) +#define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3) +#define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4) +#define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5) +#define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6) +#define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7) +#define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8) +#define PRS0_SYNCH3_PA9 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x9) +#define PRS0_SYNCH3_PA10 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xa) +#define PRS0_SYNCH3_PA11 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xb) +#define PRS0_SYNCH3_PA12 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xc) +#define PRS0_SYNCH3_PA13 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xd) +#define PRS0_SYNCH3_PA14 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xe) +#define PRS0_SYNCH3_PA15 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xf) +#define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0) +#define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1) +#define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2) +#define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3) +#define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4) +#define PRS0_SYNCH3_PB5 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x5) +#define PRS0_SYNCH3_PB6 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x6) +#define PRS0_SYNCH3_PB7 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x7) +#define PRS0_SYNCH3_PB8 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x8) +#define PRS0_SYNCH3_PB9 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x9) +#define PRS0_SYNCH3_PB10 SILABS_DBUS_PRS0_SYNCH3(0x1, 0xa) +#define PRS0_SYNCH3_PB11 SILABS_DBUS_PRS0_SYNCH3(0x1, 0xb) +#define PRS0_SYNCH3_PB12 SILABS_DBUS_PRS0_SYNCH3(0x1, 0xc) +#define PRS0_SYNCH3_PB13 SILABS_DBUS_PRS0_SYNCH3(0x1, 0xd) +#define PRS0_SYNCH3_PB14 SILABS_DBUS_PRS0_SYNCH3(0x1, 0xe) +#define PRS0_SYNCH3_PB15 SILABS_DBUS_PRS0_SYNCH3(0x1, 0xf) +#define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0) +#define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1) +#define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2) +#define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3) +#define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4) +#define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5) +#define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6) +#define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7) +#define PRS0_SYNCH3_PC8 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x8) +#define PRS0_SYNCH3_PC9 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x9) +#define PRS0_SYNCH3_PC10 SILABS_DBUS_PRS0_SYNCH3(0x2, 0xa) +#define PRS0_SYNCH3_PC11 SILABS_DBUS_PRS0_SYNCH3(0x2, 0xb) +#define PRS0_SYNCH3_PC12 SILABS_DBUS_PRS0_SYNCH3(0x2, 0xc) +#define PRS0_SYNCH3_PC13 SILABS_DBUS_PRS0_SYNCH3(0x2, 0xd) +#define PRS0_SYNCH3_PC14 SILABS_DBUS_PRS0_SYNCH3(0x2, 0xe) +#define PRS0_SYNCH3_PC15 SILABS_DBUS_PRS0_SYNCH3(0x2, 0xf) +#define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0) +#define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1) +#define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2) +#define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3) +#define PRS0_SYNCH3_PD4 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x4) +#define PRS0_SYNCH3_PD5 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x5) +#define PRS0_SYNCH3_PD6 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x6) +#define PRS0_SYNCH3_PD7 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x7) +#define PRS0_SYNCH3_PD8 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x8) +#define PRS0_SYNCH3_PD9 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x9) +#define PRS0_SYNCH3_PD10 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xa) +#define PRS0_SYNCH3_PD11 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xb) +#define PRS0_SYNCH3_PD12 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xc) +#define PRS0_SYNCH3_PD13 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xd) +#define PRS0_SYNCH3_PD14 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xe) +#define PRS0_SYNCH3_PD15 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xf) + +#define HFXO0_BUFOUTREQINASYNC_PA0 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x0) +#define HFXO0_BUFOUTREQINASYNC_PA1 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x1) +#define HFXO0_BUFOUTREQINASYNC_PA2 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x2) +#define HFXO0_BUFOUTREQINASYNC_PA3 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x3) +#define HFXO0_BUFOUTREQINASYNC_PA4 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x4) +#define HFXO0_BUFOUTREQINASYNC_PA5 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x5) +#define HFXO0_BUFOUTREQINASYNC_PA6 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x6) +#define HFXO0_BUFOUTREQINASYNC_PA7 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x7) +#define HFXO0_BUFOUTREQINASYNC_PA8 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x8) +#define HFXO0_BUFOUTREQINASYNC_PA9 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x9) +#define HFXO0_BUFOUTREQINASYNC_PA10 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0xa) +#define HFXO0_BUFOUTREQINASYNC_PA11 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0xb) +#define HFXO0_BUFOUTREQINASYNC_PA12 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0xc) +#define HFXO0_BUFOUTREQINASYNC_PA13 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0xd) +#define HFXO0_BUFOUTREQINASYNC_PA14 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0xe) +#define HFXO0_BUFOUTREQINASYNC_PA15 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0xf) +#define HFXO0_BUFOUTREQINASYNC_PB0 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x0) +#define HFXO0_BUFOUTREQINASYNC_PB1 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x1) +#define HFXO0_BUFOUTREQINASYNC_PB2 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x2) +#define HFXO0_BUFOUTREQINASYNC_PB3 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x3) +#define HFXO0_BUFOUTREQINASYNC_PB4 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x4) +#define HFXO0_BUFOUTREQINASYNC_PB5 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x5) +#define HFXO0_BUFOUTREQINASYNC_PB6 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x6) +#define HFXO0_BUFOUTREQINASYNC_PB7 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x7) +#define HFXO0_BUFOUTREQINASYNC_PB8 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x8) +#define HFXO0_BUFOUTREQINASYNC_PB9 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x9) +#define HFXO0_BUFOUTREQINASYNC_PB10 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0xa) +#define HFXO0_BUFOUTREQINASYNC_PB11 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0xb) +#define HFXO0_BUFOUTREQINASYNC_PB12 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0xc) +#define HFXO0_BUFOUTREQINASYNC_PB13 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0xd) +#define HFXO0_BUFOUTREQINASYNC_PB14 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0xe) +#define HFXO0_BUFOUTREQINASYNC_PB15 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0xf) + +#define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0) +#define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1) +#define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2) +#define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3) +#define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4) +#define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5) +#define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6) +#define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7) +#define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8) +#define TIMER0_CC0_PA9 SILABS_DBUS_TIMER0_CC0(0x0, 0x9) +#define TIMER0_CC0_PA10 SILABS_DBUS_TIMER0_CC0(0x0, 0xa) +#define TIMER0_CC0_PA11 SILABS_DBUS_TIMER0_CC0(0x0, 0xb) +#define TIMER0_CC0_PA12 SILABS_DBUS_TIMER0_CC0(0x0, 0xc) +#define TIMER0_CC0_PA13 SILABS_DBUS_TIMER0_CC0(0x0, 0xd) +#define TIMER0_CC0_PA14 SILABS_DBUS_TIMER0_CC0(0x0, 0xe) +#define TIMER0_CC0_PA15 SILABS_DBUS_TIMER0_CC0(0x0, 0xf) +#define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0) +#define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1) +#define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2) +#define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3) +#define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4) +#define TIMER0_CC0_PB5 SILABS_DBUS_TIMER0_CC0(0x1, 0x5) +#define TIMER0_CC0_PB6 SILABS_DBUS_TIMER0_CC0(0x1, 0x6) +#define TIMER0_CC0_PB7 SILABS_DBUS_TIMER0_CC0(0x1, 0x7) +#define TIMER0_CC0_PB8 SILABS_DBUS_TIMER0_CC0(0x1, 0x8) +#define TIMER0_CC0_PB9 SILABS_DBUS_TIMER0_CC0(0x1, 0x9) +#define TIMER0_CC0_PB10 SILABS_DBUS_TIMER0_CC0(0x1, 0xa) +#define TIMER0_CC0_PB11 SILABS_DBUS_TIMER0_CC0(0x1, 0xb) +#define TIMER0_CC0_PB12 SILABS_DBUS_TIMER0_CC0(0x1, 0xc) +#define TIMER0_CC0_PB13 SILABS_DBUS_TIMER0_CC0(0x1, 0xd) +#define TIMER0_CC0_PB14 SILABS_DBUS_TIMER0_CC0(0x1, 0xe) +#define TIMER0_CC0_PB15 SILABS_DBUS_TIMER0_CC0(0x1, 0xf) +#define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0) +#define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1) +#define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2) +#define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3) +#define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4) +#define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5) +#define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6) +#define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7) +#define TIMER0_CC0_PC8 SILABS_DBUS_TIMER0_CC0(0x2, 0x8) +#define TIMER0_CC0_PC9 SILABS_DBUS_TIMER0_CC0(0x2, 0x9) +#define TIMER0_CC0_PC10 SILABS_DBUS_TIMER0_CC0(0x2, 0xa) +#define TIMER0_CC0_PC11 SILABS_DBUS_TIMER0_CC0(0x2, 0xb) +#define TIMER0_CC0_PC12 SILABS_DBUS_TIMER0_CC0(0x2, 0xc) +#define TIMER0_CC0_PC13 SILABS_DBUS_TIMER0_CC0(0x2, 0xd) +#define TIMER0_CC0_PC14 SILABS_DBUS_TIMER0_CC0(0x2, 0xe) +#define TIMER0_CC0_PC15 SILABS_DBUS_TIMER0_CC0(0x2, 0xf) +#define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0) +#define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1) +#define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2) +#define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3) +#define TIMER0_CC0_PD4 SILABS_DBUS_TIMER0_CC0(0x3, 0x4) +#define TIMER0_CC0_PD5 SILABS_DBUS_TIMER0_CC0(0x3, 0x5) +#define TIMER0_CC0_PD6 SILABS_DBUS_TIMER0_CC0(0x3, 0x6) +#define TIMER0_CC0_PD7 SILABS_DBUS_TIMER0_CC0(0x3, 0x7) +#define TIMER0_CC0_PD8 SILABS_DBUS_TIMER0_CC0(0x3, 0x8) +#define TIMER0_CC0_PD9 SILABS_DBUS_TIMER0_CC0(0x3, 0x9) +#define TIMER0_CC0_PD10 SILABS_DBUS_TIMER0_CC0(0x3, 0xa) +#define TIMER0_CC0_PD11 SILABS_DBUS_TIMER0_CC0(0x3, 0xb) +#define TIMER0_CC0_PD12 SILABS_DBUS_TIMER0_CC0(0x3, 0xc) +#define TIMER0_CC0_PD13 SILABS_DBUS_TIMER0_CC0(0x3, 0xd) +#define TIMER0_CC0_PD14 SILABS_DBUS_TIMER0_CC0(0x3, 0xe) +#define TIMER0_CC0_PD15 SILABS_DBUS_TIMER0_CC0(0x3, 0xf) +#define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0) +#define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1) +#define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2) +#define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3) +#define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4) +#define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5) +#define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6) +#define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7) +#define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8) +#define TIMER0_CC1_PA9 SILABS_DBUS_TIMER0_CC1(0x0, 0x9) +#define TIMER0_CC1_PA10 SILABS_DBUS_TIMER0_CC1(0x0, 0xa) +#define TIMER0_CC1_PA11 SILABS_DBUS_TIMER0_CC1(0x0, 0xb) +#define TIMER0_CC1_PA12 SILABS_DBUS_TIMER0_CC1(0x0, 0xc) +#define TIMER0_CC1_PA13 SILABS_DBUS_TIMER0_CC1(0x0, 0xd) +#define TIMER0_CC1_PA14 SILABS_DBUS_TIMER0_CC1(0x0, 0xe) +#define TIMER0_CC1_PA15 SILABS_DBUS_TIMER0_CC1(0x0, 0xf) +#define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0) +#define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1) +#define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2) +#define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3) +#define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4) +#define TIMER0_CC1_PB5 SILABS_DBUS_TIMER0_CC1(0x1, 0x5) +#define TIMER0_CC1_PB6 SILABS_DBUS_TIMER0_CC1(0x1, 0x6) +#define TIMER0_CC1_PB7 SILABS_DBUS_TIMER0_CC1(0x1, 0x7) +#define TIMER0_CC1_PB8 SILABS_DBUS_TIMER0_CC1(0x1, 0x8) +#define TIMER0_CC1_PB9 SILABS_DBUS_TIMER0_CC1(0x1, 0x9) +#define TIMER0_CC1_PB10 SILABS_DBUS_TIMER0_CC1(0x1, 0xa) +#define TIMER0_CC1_PB11 SILABS_DBUS_TIMER0_CC1(0x1, 0xb) +#define TIMER0_CC1_PB12 SILABS_DBUS_TIMER0_CC1(0x1, 0xc) +#define TIMER0_CC1_PB13 SILABS_DBUS_TIMER0_CC1(0x1, 0xd) +#define TIMER0_CC1_PB14 SILABS_DBUS_TIMER0_CC1(0x1, 0xe) +#define TIMER0_CC1_PB15 SILABS_DBUS_TIMER0_CC1(0x1, 0xf) +#define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0) +#define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1) +#define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2) +#define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3) +#define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4) +#define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5) +#define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6) +#define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7) +#define TIMER0_CC1_PC8 SILABS_DBUS_TIMER0_CC1(0x2, 0x8) +#define TIMER0_CC1_PC9 SILABS_DBUS_TIMER0_CC1(0x2, 0x9) +#define TIMER0_CC1_PC10 SILABS_DBUS_TIMER0_CC1(0x2, 0xa) +#define TIMER0_CC1_PC11 SILABS_DBUS_TIMER0_CC1(0x2, 0xb) +#define TIMER0_CC1_PC12 SILABS_DBUS_TIMER0_CC1(0x2, 0xc) +#define TIMER0_CC1_PC13 SILABS_DBUS_TIMER0_CC1(0x2, 0xd) +#define TIMER0_CC1_PC14 SILABS_DBUS_TIMER0_CC1(0x2, 0xe) +#define TIMER0_CC1_PC15 SILABS_DBUS_TIMER0_CC1(0x2, 0xf) +#define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0) +#define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1) +#define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2) +#define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3) +#define TIMER0_CC1_PD4 SILABS_DBUS_TIMER0_CC1(0x3, 0x4) +#define TIMER0_CC1_PD5 SILABS_DBUS_TIMER0_CC1(0x3, 0x5) +#define TIMER0_CC1_PD6 SILABS_DBUS_TIMER0_CC1(0x3, 0x6) +#define TIMER0_CC1_PD7 SILABS_DBUS_TIMER0_CC1(0x3, 0x7) +#define TIMER0_CC1_PD8 SILABS_DBUS_TIMER0_CC1(0x3, 0x8) +#define TIMER0_CC1_PD9 SILABS_DBUS_TIMER0_CC1(0x3, 0x9) +#define TIMER0_CC1_PD10 SILABS_DBUS_TIMER0_CC1(0x3, 0xa) +#define TIMER0_CC1_PD11 SILABS_DBUS_TIMER0_CC1(0x3, 0xb) +#define TIMER0_CC1_PD12 SILABS_DBUS_TIMER0_CC1(0x3, 0xc) +#define TIMER0_CC1_PD13 SILABS_DBUS_TIMER0_CC1(0x3, 0xd) +#define TIMER0_CC1_PD14 SILABS_DBUS_TIMER0_CC1(0x3, 0xe) +#define TIMER0_CC1_PD15 SILABS_DBUS_TIMER0_CC1(0x3, 0xf) +#define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0) +#define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1) +#define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2) +#define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3) +#define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4) +#define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5) +#define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6) +#define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7) +#define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8) +#define TIMER0_CC2_PA9 SILABS_DBUS_TIMER0_CC2(0x0, 0x9) +#define TIMER0_CC2_PA10 SILABS_DBUS_TIMER0_CC2(0x0, 0xa) +#define TIMER0_CC2_PA11 SILABS_DBUS_TIMER0_CC2(0x0, 0xb) +#define TIMER0_CC2_PA12 SILABS_DBUS_TIMER0_CC2(0x0, 0xc) +#define TIMER0_CC2_PA13 SILABS_DBUS_TIMER0_CC2(0x0, 0xd) +#define TIMER0_CC2_PA14 SILABS_DBUS_TIMER0_CC2(0x0, 0xe) +#define TIMER0_CC2_PA15 SILABS_DBUS_TIMER0_CC2(0x0, 0xf) +#define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0) +#define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1) +#define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2) +#define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3) +#define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4) +#define TIMER0_CC2_PB5 SILABS_DBUS_TIMER0_CC2(0x1, 0x5) +#define TIMER0_CC2_PB6 SILABS_DBUS_TIMER0_CC2(0x1, 0x6) +#define TIMER0_CC2_PB7 SILABS_DBUS_TIMER0_CC2(0x1, 0x7) +#define TIMER0_CC2_PB8 SILABS_DBUS_TIMER0_CC2(0x1, 0x8) +#define TIMER0_CC2_PB9 SILABS_DBUS_TIMER0_CC2(0x1, 0x9) +#define TIMER0_CC2_PB10 SILABS_DBUS_TIMER0_CC2(0x1, 0xa) +#define TIMER0_CC2_PB11 SILABS_DBUS_TIMER0_CC2(0x1, 0xb) +#define TIMER0_CC2_PB12 SILABS_DBUS_TIMER0_CC2(0x1, 0xc) +#define TIMER0_CC2_PB13 SILABS_DBUS_TIMER0_CC2(0x1, 0xd) +#define TIMER0_CC2_PB14 SILABS_DBUS_TIMER0_CC2(0x1, 0xe) +#define TIMER0_CC2_PB15 SILABS_DBUS_TIMER0_CC2(0x1, 0xf) +#define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0) +#define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1) +#define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2) +#define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3) +#define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4) +#define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5) +#define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6) +#define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7) +#define TIMER0_CC2_PC8 SILABS_DBUS_TIMER0_CC2(0x2, 0x8) +#define TIMER0_CC2_PC9 SILABS_DBUS_TIMER0_CC2(0x2, 0x9) +#define TIMER0_CC2_PC10 SILABS_DBUS_TIMER0_CC2(0x2, 0xa) +#define TIMER0_CC2_PC11 SILABS_DBUS_TIMER0_CC2(0x2, 0xb) +#define TIMER0_CC2_PC12 SILABS_DBUS_TIMER0_CC2(0x2, 0xc) +#define TIMER0_CC2_PC13 SILABS_DBUS_TIMER0_CC2(0x2, 0xd) +#define TIMER0_CC2_PC14 SILABS_DBUS_TIMER0_CC2(0x2, 0xe) +#define TIMER0_CC2_PC15 SILABS_DBUS_TIMER0_CC2(0x2, 0xf) +#define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0) +#define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1) +#define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2) +#define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3) +#define TIMER0_CC2_PD4 SILABS_DBUS_TIMER0_CC2(0x3, 0x4) +#define TIMER0_CC2_PD5 SILABS_DBUS_TIMER0_CC2(0x3, 0x5) +#define TIMER0_CC2_PD6 SILABS_DBUS_TIMER0_CC2(0x3, 0x6) +#define TIMER0_CC2_PD7 SILABS_DBUS_TIMER0_CC2(0x3, 0x7) +#define TIMER0_CC2_PD8 SILABS_DBUS_TIMER0_CC2(0x3, 0x8) +#define TIMER0_CC2_PD9 SILABS_DBUS_TIMER0_CC2(0x3, 0x9) +#define TIMER0_CC2_PD10 SILABS_DBUS_TIMER0_CC2(0x3, 0xa) +#define TIMER0_CC2_PD11 SILABS_DBUS_TIMER0_CC2(0x3, 0xb) +#define TIMER0_CC2_PD12 SILABS_DBUS_TIMER0_CC2(0x3, 0xc) +#define TIMER0_CC2_PD13 SILABS_DBUS_TIMER0_CC2(0x3, 0xd) +#define TIMER0_CC2_PD14 SILABS_DBUS_TIMER0_CC2(0x3, 0xe) +#define TIMER0_CC2_PD15 SILABS_DBUS_TIMER0_CC2(0x3, 0xf) +#define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0) +#define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1) +#define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2) +#define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3) +#define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4) +#define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5) +#define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6) +#define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7) +#define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8) +#define TIMER0_CDTI0_PA9 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x9) +#define TIMER0_CDTI0_PA10 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xa) +#define TIMER0_CDTI0_PA11 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xb) +#define TIMER0_CDTI0_PA12 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xc) +#define TIMER0_CDTI0_PA13 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xd) +#define TIMER0_CDTI0_PA14 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xe) +#define TIMER0_CDTI0_PA15 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xf) +#define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0) +#define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1) +#define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2) +#define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3) +#define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4) +#define TIMER0_CDTI0_PB5 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x5) +#define TIMER0_CDTI0_PB6 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x6) +#define TIMER0_CDTI0_PB7 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x7) +#define TIMER0_CDTI0_PB8 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x8) +#define TIMER0_CDTI0_PB9 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x9) +#define TIMER0_CDTI0_PB10 SILABS_DBUS_TIMER0_CDTI0(0x1, 0xa) +#define TIMER0_CDTI0_PB11 SILABS_DBUS_TIMER0_CDTI0(0x1, 0xb) +#define TIMER0_CDTI0_PB12 SILABS_DBUS_TIMER0_CDTI0(0x1, 0xc) +#define TIMER0_CDTI0_PB13 SILABS_DBUS_TIMER0_CDTI0(0x1, 0xd) +#define TIMER0_CDTI0_PB14 SILABS_DBUS_TIMER0_CDTI0(0x1, 0xe) +#define TIMER0_CDTI0_PB15 SILABS_DBUS_TIMER0_CDTI0(0x1, 0xf) +#define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0) +#define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1) +#define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2) +#define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3) +#define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4) +#define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5) +#define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6) +#define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7) +#define TIMER0_CDTI0_PC8 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x8) +#define TIMER0_CDTI0_PC9 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x9) +#define TIMER0_CDTI0_PC10 SILABS_DBUS_TIMER0_CDTI0(0x2, 0xa) +#define TIMER0_CDTI0_PC11 SILABS_DBUS_TIMER0_CDTI0(0x2, 0xb) +#define TIMER0_CDTI0_PC12 SILABS_DBUS_TIMER0_CDTI0(0x2, 0xc) +#define TIMER0_CDTI0_PC13 SILABS_DBUS_TIMER0_CDTI0(0x2, 0xd) +#define TIMER0_CDTI0_PC14 SILABS_DBUS_TIMER0_CDTI0(0x2, 0xe) +#define TIMER0_CDTI0_PC15 SILABS_DBUS_TIMER0_CDTI0(0x2, 0xf) +#define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0) +#define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1) +#define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2) +#define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3) +#define TIMER0_CDTI0_PD4 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x4) +#define TIMER0_CDTI0_PD5 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x5) +#define TIMER0_CDTI0_PD6 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x6) +#define TIMER0_CDTI0_PD7 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x7) +#define TIMER0_CDTI0_PD8 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x8) +#define TIMER0_CDTI0_PD9 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x9) +#define TIMER0_CDTI0_PD10 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xa) +#define TIMER0_CDTI0_PD11 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xb) +#define TIMER0_CDTI0_PD12 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xc) +#define TIMER0_CDTI0_PD13 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xd) +#define TIMER0_CDTI0_PD14 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xe) +#define TIMER0_CDTI0_PD15 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xf) +#define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0) +#define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1) +#define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2) +#define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3) +#define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4) +#define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5) +#define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6) +#define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7) +#define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8) +#define TIMER0_CDTI1_PA9 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x9) +#define TIMER0_CDTI1_PA10 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xa) +#define TIMER0_CDTI1_PA11 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xb) +#define TIMER0_CDTI1_PA12 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xc) +#define TIMER0_CDTI1_PA13 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xd) +#define TIMER0_CDTI1_PA14 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xe) +#define TIMER0_CDTI1_PA15 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xf) +#define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0) +#define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1) +#define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2) +#define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3) +#define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4) +#define TIMER0_CDTI1_PB5 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x5) +#define TIMER0_CDTI1_PB6 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x6) +#define TIMER0_CDTI1_PB7 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x7) +#define TIMER0_CDTI1_PB8 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x8) +#define TIMER0_CDTI1_PB9 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x9) +#define TIMER0_CDTI1_PB10 SILABS_DBUS_TIMER0_CDTI1(0x1, 0xa) +#define TIMER0_CDTI1_PB11 SILABS_DBUS_TIMER0_CDTI1(0x1, 0xb) +#define TIMER0_CDTI1_PB12 SILABS_DBUS_TIMER0_CDTI1(0x1, 0xc) +#define TIMER0_CDTI1_PB13 SILABS_DBUS_TIMER0_CDTI1(0x1, 0xd) +#define TIMER0_CDTI1_PB14 SILABS_DBUS_TIMER0_CDTI1(0x1, 0xe) +#define TIMER0_CDTI1_PB15 SILABS_DBUS_TIMER0_CDTI1(0x1, 0xf) +#define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0) +#define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1) +#define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2) +#define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3) +#define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4) +#define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5) +#define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6) +#define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7) +#define TIMER0_CDTI1_PC8 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x8) +#define TIMER0_CDTI1_PC9 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x9) +#define TIMER0_CDTI1_PC10 SILABS_DBUS_TIMER0_CDTI1(0x2, 0xa) +#define TIMER0_CDTI1_PC11 SILABS_DBUS_TIMER0_CDTI1(0x2, 0xb) +#define TIMER0_CDTI1_PC12 SILABS_DBUS_TIMER0_CDTI1(0x2, 0xc) +#define TIMER0_CDTI1_PC13 SILABS_DBUS_TIMER0_CDTI1(0x2, 0xd) +#define TIMER0_CDTI1_PC14 SILABS_DBUS_TIMER0_CDTI1(0x2, 0xe) +#define TIMER0_CDTI1_PC15 SILABS_DBUS_TIMER0_CDTI1(0x2, 0xf) +#define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0) +#define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1) +#define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2) +#define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3) +#define TIMER0_CDTI1_PD4 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x4) +#define TIMER0_CDTI1_PD5 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x5) +#define TIMER0_CDTI1_PD6 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x6) +#define TIMER0_CDTI1_PD7 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x7) +#define TIMER0_CDTI1_PD8 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x8) +#define TIMER0_CDTI1_PD9 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x9) +#define TIMER0_CDTI1_PD10 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xa) +#define TIMER0_CDTI1_PD11 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xb) +#define TIMER0_CDTI1_PD12 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xc) +#define TIMER0_CDTI1_PD13 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xd) +#define TIMER0_CDTI1_PD14 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xe) +#define TIMER0_CDTI1_PD15 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xf) +#define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0) +#define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1) +#define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2) +#define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3) +#define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4) +#define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5) +#define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6) +#define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7) +#define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8) +#define TIMER0_CDTI2_PA9 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x9) +#define TIMER0_CDTI2_PA10 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xa) +#define TIMER0_CDTI2_PA11 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xb) +#define TIMER0_CDTI2_PA12 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xc) +#define TIMER0_CDTI2_PA13 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xd) +#define TIMER0_CDTI2_PA14 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xe) +#define TIMER0_CDTI2_PA15 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xf) +#define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0) +#define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1) +#define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2) +#define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3) +#define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4) +#define TIMER0_CDTI2_PB5 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x5) +#define TIMER0_CDTI2_PB6 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x6) +#define TIMER0_CDTI2_PB7 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x7) +#define TIMER0_CDTI2_PB8 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x8) +#define TIMER0_CDTI2_PB9 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x9) +#define TIMER0_CDTI2_PB10 SILABS_DBUS_TIMER0_CDTI2(0x1, 0xa) +#define TIMER0_CDTI2_PB11 SILABS_DBUS_TIMER0_CDTI2(0x1, 0xb) +#define TIMER0_CDTI2_PB12 SILABS_DBUS_TIMER0_CDTI2(0x1, 0xc) +#define TIMER0_CDTI2_PB13 SILABS_DBUS_TIMER0_CDTI2(0x1, 0xd) +#define TIMER0_CDTI2_PB14 SILABS_DBUS_TIMER0_CDTI2(0x1, 0xe) +#define TIMER0_CDTI2_PB15 SILABS_DBUS_TIMER0_CDTI2(0x1, 0xf) +#define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0) +#define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1) +#define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2) +#define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3) +#define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4) +#define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5) +#define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6) +#define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7) +#define TIMER0_CDTI2_PC8 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x8) +#define TIMER0_CDTI2_PC9 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x9) +#define TIMER0_CDTI2_PC10 SILABS_DBUS_TIMER0_CDTI2(0x2, 0xa) +#define TIMER0_CDTI2_PC11 SILABS_DBUS_TIMER0_CDTI2(0x2, 0xb) +#define TIMER0_CDTI2_PC12 SILABS_DBUS_TIMER0_CDTI2(0x2, 0xc) +#define TIMER0_CDTI2_PC13 SILABS_DBUS_TIMER0_CDTI2(0x2, 0xd) +#define TIMER0_CDTI2_PC14 SILABS_DBUS_TIMER0_CDTI2(0x2, 0xe) +#define TIMER0_CDTI2_PC15 SILABS_DBUS_TIMER0_CDTI2(0x2, 0xf) +#define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0) +#define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1) +#define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2) +#define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3) +#define TIMER0_CDTI2_PD4 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x4) +#define TIMER0_CDTI2_PD5 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x5) +#define TIMER0_CDTI2_PD6 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x6) +#define TIMER0_CDTI2_PD7 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x7) +#define TIMER0_CDTI2_PD8 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x8) +#define TIMER0_CDTI2_PD9 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x9) +#define TIMER0_CDTI2_PD10 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xa) +#define TIMER0_CDTI2_PD11 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xb) +#define TIMER0_CDTI2_PD12 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xc) +#define TIMER0_CDTI2_PD13 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xd) +#define TIMER0_CDTI2_PD14 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xe) +#define TIMER0_CDTI2_PD15 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xf) + +#define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0) +#define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1) +#define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2) +#define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3) +#define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4) +#define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5) +#define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6) +#define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7) +#define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8) +#define TIMER1_CC0_PA9 SILABS_DBUS_TIMER1_CC0(0x0, 0x9) +#define TIMER1_CC0_PA10 SILABS_DBUS_TIMER1_CC0(0x0, 0xa) +#define TIMER1_CC0_PA11 SILABS_DBUS_TIMER1_CC0(0x0, 0xb) +#define TIMER1_CC0_PA12 SILABS_DBUS_TIMER1_CC0(0x0, 0xc) +#define TIMER1_CC0_PA13 SILABS_DBUS_TIMER1_CC0(0x0, 0xd) +#define TIMER1_CC0_PA14 SILABS_DBUS_TIMER1_CC0(0x0, 0xe) +#define TIMER1_CC0_PA15 SILABS_DBUS_TIMER1_CC0(0x0, 0xf) +#define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0) +#define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1) +#define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2) +#define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3) +#define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4) +#define TIMER1_CC0_PB5 SILABS_DBUS_TIMER1_CC0(0x1, 0x5) +#define TIMER1_CC0_PB6 SILABS_DBUS_TIMER1_CC0(0x1, 0x6) +#define TIMER1_CC0_PB7 SILABS_DBUS_TIMER1_CC0(0x1, 0x7) +#define TIMER1_CC0_PB8 SILABS_DBUS_TIMER1_CC0(0x1, 0x8) +#define TIMER1_CC0_PB9 SILABS_DBUS_TIMER1_CC0(0x1, 0x9) +#define TIMER1_CC0_PB10 SILABS_DBUS_TIMER1_CC0(0x1, 0xa) +#define TIMER1_CC0_PB11 SILABS_DBUS_TIMER1_CC0(0x1, 0xb) +#define TIMER1_CC0_PB12 SILABS_DBUS_TIMER1_CC0(0x1, 0xc) +#define TIMER1_CC0_PB13 SILABS_DBUS_TIMER1_CC0(0x1, 0xd) +#define TIMER1_CC0_PB14 SILABS_DBUS_TIMER1_CC0(0x1, 0xe) +#define TIMER1_CC0_PB15 SILABS_DBUS_TIMER1_CC0(0x1, 0xf) +#define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0) +#define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1) +#define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2) +#define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3) +#define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4) +#define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5) +#define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6) +#define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7) +#define TIMER1_CC0_PC8 SILABS_DBUS_TIMER1_CC0(0x2, 0x8) +#define TIMER1_CC0_PC9 SILABS_DBUS_TIMER1_CC0(0x2, 0x9) +#define TIMER1_CC0_PC10 SILABS_DBUS_TIMER1_CC0(0x2, 0xa) +#define TIMER1_CC0_PC11 SILABS_DBUS_TIMER1_CC0(0x2, 0xb) +#define TIMER1_CC0_PC12 SILABS_DBUS_TIMER1_CC0(0x2, 0xc) +#define TIMER1_CC0_PC13 SILABS_DBUS_TIMER1_CC0(0x2, 0xd) +#define TIMER1_CC0_PC14 SILABS_DBUS_TIMER1_CC0(0x2, 0xe) +#define TIMER1_CC0_PC15 SILABS_DBUS_TIMER1_CC0(0x2, 0xf) +#define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0) +#define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1) +#define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2) +#define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3) +#define TIMER1_CC0_PD4 SILABS_DBUS_TIMER1_CC0(0x3, 0x4) +#define TIMER1_CC0_PD5 SILABS_DBUS_TIMER1_CC0(0x3, 0x5) +#define TIMER1_CC0_PD6 SILABS_DBUS_TIMER1_CC0(0x3, 0x6) +#define TIMER1_CC0_PD7 SILABS_DBUS_TIMER1_CC0(0x3, 0x7) +#define TIMER1_CC0_PD8 SILABS_DBUS_TIMER1_CC0(0x3, 0x8) +#define TIMER1_CC0_PD9 SILABS_DBUS_TIMER1_CC0(0x3, 0x9) +#define TIMER1_CC0_PD10 SILABS_DBUS_TIMER1_CC0(0x3, 0xa) +#define TIMER1_CC0_PD11 SILABS_DBUS_TIMER1_CC0(0x3, 0xb) +#define TIMER1_CC0_PD12 SILABS_DBUS_TIMER1_CC0(0x3, 0xc) +#define TIMER1_CC0_PD13 SILABS_DBUS_TIMER1_CC0(0x3, 0xd) +#define TIMER1_CC0_PD14 SILABS_DBUS_TIMER1_CC0(0x3, 0xe) +#define TIMER1_CC0_PD15 SILABS_DBUS_TIMER1_CC0(0x3, 0xf) +#define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0) +#define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1) +#define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2) +#define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3) +#define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4) +#define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5) +#define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6) +#define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7) +#define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8) +#define TIMER1_CC1_PA9 SILABS_DBUS_TIMER1_CC1(0x0, 0x9) +#define TIMER1_CC1_PA10 SILABS_DBUS_TIMER1_CC1(0x0, 0xa) +#define TIMER1_CC1_PA11 SILABS_DBUS_TIMER1_CC1(0x0, 0xb) +#define TIMER1_CC1_PA12 SILABS_DBUS_TIMER1_CC1(0x0, 0xc) +#define TIMER1_CC1_PA13 SILABS_DBUS_TIMER1_CC1(0x0, 0xd) +#define TIMER1_CC1_PA14 SILABS_DBUS_TIMER1_CC1(0x0, 0xe) +#define TIMER1_CC1_PA15 SILABS_DBUS_TIMER1_CC1(0x0, 0xf) +#define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0) +#define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1) +#define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2) +#define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3) +#define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4) +#define TIMER1_CC1_PB5 SILABS_DBUS_TIMER1_CC1(0x1, 0x5) +#define TIMER1_CC1_PB6 SILABS_DBUS_TIMER1_CC1(0x1, 0x6) +#define TIMER1_CC1_PB7 SILABS_DBUS_TIMER1_CC1(0x1, 0x7) +#define TIMER1_CC1_PB8 SILABS_DBUS_TIMER1_CC1(0x1, 0x8) +#define TIMER1_CC1_PB9 SILABS_DBUS_TIMER1_CC1(0x1, 0x9) +#define TIMER1_CC1_PB10 SILABS_DBUS_TIMER1_CC1(0x1, 0xa) +#define TIMER1_CC1_PB11 SILABS_DBUS_TIMER1_CC1(0x1, 0xb) +#define TIMER1_CC1_PB12 SILABS_DBUS_TIMER1_CC1(0x1, 0xc) +#define TIMER1_CC1_PB13 SILABS_DBUS_TIMER1_CC1(0x1, 0xd) +#define TIMER1_CC1_PB14 SILABS_DBUS_TIMER1_CC1(0x1, 0xe) +#define TIMER1_CC1_PB15 SILABS_DBUS_TIMER1_CC1(0x1, 0xf) +#define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0) +#define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1) +#define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2) +#define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3) +#define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4) +#define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5) +#define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6) +#define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7) +#define TIMER1_CC1_PC8 SILABS_DBUS_TIMER1_CC1(0x2, 0x8) +#define TIMER1_CC1_PC9 SILABS_DBUS_TIMER1_CC1(0x2, 0x9) +#define TIMER1_CC1_PC10 SILABS_DBUS_TIMER1_CC1(0x2, 0xa) +#define TIMER1_CC1_PC11 SILABS_DBUS_TIMER1_CC1(0x2, 0xb) +#define TIMER1_CC1_PC12 SILABS_DBUS_TIMER1_CC1(0x2, 0xc) +#define TIMER1_CC1_PC13 SILABS_DBUS_TIMER1_CC1(0x2, 0xd) +#define TIMER1_CC1_PC14 SILABS_DBUS_TIMER1_CC1(0x2, 0xe) +#define TIMER1_CC1_PC15 SILABS_DBUS_TIMER1_CC1(0x2, 0xf) +#define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0) +#define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1) +#define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2) +#define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3) +#define TIMER1_CC1_PD4 SILABS_DBUS_TIMER1_CC1(0x3, 0x4) +#define TIMER1_CC1_PD5 SILABS_DBUS_TIMER1_CC1(0x3, 0x5) +#define TIMER1_CC1_PD6 SILABS_DBUS_TIMER1_CC1(0x3, 0x6) +#define TIMER1_CC1_PD7 SILABS_DBUS_TIMER1_CC1(0x3, 0x7) +#define TIMER1_CC1_PD8 SILABS_DBUS_TIMER1_CC1(0x3, 0x8) +#define TIMER1_CC1_PD9 SILABS_DBUS_TIMER1_CC1(0x3, 0x9) +#define TIMER1_CC1_PD10 SILABS_DBUS_TIMER1_CC1(0x3, 0xa) +#define TIMER1_CC1_PD11 SILABS_DBUS_TIMER1_CC1(0x3, 0xb) +#define TIMER1_CC1_PD12 SILABS_DBUS_TIMER1_CC1(0x3, 0xc) +#define TIMER1_CC1_PD13 SILABS_DBUS_TIMER1_CC1(0x3, 0xd) +#define TIMER1_CC1_PD14 SILABS_DBUS_TIMER1_CC1(0x3, 0xe) +#define TIMER1_CC1_PD15 SILABS_DBUS_TIMER1_CC1(0x3, 0xf) +#define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0) +#define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1) +#define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2) +#define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3) +#define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4) +#define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5) +#define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6) +#define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7) +#define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8) +#define TIMER1_CC2_PA9 SILABS_DBUS_TIMER1_CC2(0x0, 0x9) +#define TIMER1_CC2_PA10 SILABS_DBUS_TIMER1_CC2(0x0, 0xa) +#define TIMER1_CC2_PA11 SILABS_DBUS_TIMER1_CC2(0x0, 0xb) +#define TIMER1_CC2_PA12 SILABS_DBUS_TIMER1_CC2(0x0, 0xc) +#define TIMER1_CC2_PA13 SILABS_DBUS_TIMER1_CC2(0x0, 0xd) +#define TIMER1_CC2_PA14 SILABS_DBUS_TIMER1_CC2(0x0, 0xe) +#define TIMER1_CC2_PA15 SILABS_DBUS_TIMER1_CC2(0x0, 0xf) +#define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0) +#define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1) +#define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2) +#define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3) +#define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4) +#define TIMER1_CC2_PB5 SILABS_DBUS_TIMER1_CC2(0x1, 0x5) +#define TIMER1_CC2_PB6 SILABS_DBUS_TIMER1_CC2(0x1, 0x6) +#define TIMER1_CC2_PB7 SILABS_DBUS_TIMER1_CC2(0x1, 0x7) +#define TIMER1_CC2_PB8 SILABS_DBUS_TIMER1_CC2(0x1, 0x8) +#define TIMER1_CC2_PB9 SILABS_DBUS_TIMER1_CC2(0x1, 0x9) +#define TIMER1_CC2_PB10 SILABS_DBUS_TIMER1_CC2(0x1, 0xa) +#define TIMER1_CC2_PB11 SILABS_DBUS_TIMER1_CC2(0x1, 0xb) +#define TIMER1_CC2_PB12 SILABS_DBUS_TIMER1_CC2(0x1, 0xc) +#define TIMER1_CC2_PB13 SILABS_DBUS_TIMER1_CC2(0x1, 0xd) +#define TIMER1_CC2_PB14 SILABS_DBUS_TIMER1_CC2(0x1, 0xe) +#define TIMER1_CC2_PB15 SILABS_DBUS_TIMER1_CC2(0x1, 0xf) +#define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0) +#define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1) +#define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2) +#define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3) +#define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4) +#define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5) +#define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6) +#define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7) +#define TIMER1_CC2_PC8 SILABS_DBUS_TIMER1_CC2(0x2, 0x8) +#define TIMER1_CC2_PC9 SILABS_DBUS_TIMER1_CC2(0x2, 0x9) +#define TIMER1_CC2_PC10 SILABS_DBUS_TIMER1_CC2(0x2, 0xa) +#define TIMER1_CC2_PC11 SILABS_DBUS_TIMER1_CC2(0x2, 0xb) +#define TIMER1_CC2_PC12 SILABS_DBUS_TIMER1_CC2(0x2, 0xc) +#define TIMER1_CC2_PC13 SILABS_DBUS_TIMER1_CC2(0x2, 0xd) +#define TIMER1_CC2_PC14 SILABS_DBUS_TIMER1_CC2(0x2, 0xe) +#define TIMER1_CC2_PC15 SILABS_DBUS_TIMER1_CC2(0x2, 0xf) +#define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0) +#define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1) +#define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2) +#define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3) +#define TIMER1_CC2_PD4 SILABS_DBUS_TIMER1_CC2(0x3, 0x4) +#define TIMER1_CC2_PD5 SILABS_DBUS_TIMER1_CC2(0x3, 0x5) +#define TIMER1_CC2_PD6 SILABS_DBUS_TIMER1_CC2(0x3, 0x6) +#define TIMER1_CC2_PD7 SILABS_DBUS_TIMER1_CC2(0x3, 0x7) +#define TIMER1_CC2_PD8 SILABS_DBUS_TIMER1_CC2(0x3, 0x8) +#define TIMER1_CC2_PD9 SILABS_DBUS_TIMER1_CC2(0x3, 0x9) +#define TIMER1_CC2_PD10 SILABS_DBUS_TIMER1_CC2(0x3, 0xa) +#define TIMER1_CC2_PD11 SILABS_DBUS_TIMER1_CC2(0x3, 0xb) +#define TIMER1_CC2_PD12 SILABS_DBUS_TIMER1_CC2(0x3, 0xc) +#define TIMER1_CC2_PD13 SILABS_DBUS_TIMER1_CC2(0x3, 0xd) +#define TIMER1_CC2_PD14 SILABS_DBUS_TIMER1_CC2(0x3, 0xe) +#define TIMER1_CC2_PD15 SILABS_DBUS_TIMER1_CC2(0x3, 0xf) +#define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0) +#define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1) +#define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2) +#define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3) +#define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4) +#define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5) +#define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6) +#define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7) +#define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8) +#define TIMER1_CDTI0_PA9 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x9) +#define TIMER1_CDTI0_PA10 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xa) +#define TIMER1_CDTI0_PA11 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xb) +#define TIMER1_CDTI0_PA12 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xc) +#define TIMER1_CDTI0_PA13 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xd) +#define TIMER1_CDTI0_PA14 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xe) +#define TIMER1_CDTI0_PA15 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xf) +#define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0) +#define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1) +#define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2) +#define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3) +#define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4) +#define TIMER1_CDTI0_PB5 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x5) +#define TIMER1_CDTI0_PB6 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x6) +#define TIMER1_CDTI0_PB7 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x7) +#define TIMER1_CDTI0_PB8 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x8) +#define TIMER1_CDTI0_PB9 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x9) +#define TIMER1_CDTI0_PB10 SILABS_DBUS_TIMER1_CDTI0(0x1, 0xa) +#define TIMER1_CDTI0_PB11 SILABS_DBUS_TIMER1_CDTI0(0x1, 0xb) +#define TIMER1_CDTI0_PB12 SILABS_DBUS_TIMER1_CDTI0(0x1, 0xc) +#define TIMER1_CDTI0_PB13 SILABS_DBUS_TIMER1_CDTI0(0x1, 0xd) +#define TIMER1_CDTI0_PB14 SILABS_DBUS_TIMER1_CDTI0(0x1, 0xe) +#define TIMER1_CDTI0_PB15 SILABS_DBUS_TIMER1_CDTI0(0x1, 0xf) +#define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0) +#define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1) +#define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2) +#define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3) +#define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4) +#define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5) +#define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6) +#define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7) +#define TIMER1_CDTI0_PC8 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x8) +#define TIMER1_CDTI0_PC9 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x9) +#define TIMER1_CDTI0_PC10 SILABS_DBUS_TIMER1_CDTI0(0x2, 0xa) +#define TIMER1_CDTI0_PC11 SILABS_DBUS_TIMER1_CDTI0(0x2, 0xb) +#define TIMER1_CDTI0_PC12 SILABS_DBUS_TIMER1_CDTI0(0x2, 0xc) +#define TIMER1_CDTI0_PC13 SILABS_DBUS_TIMER1_CDTI0(0x2, 0xd) +#define TIMER1_CDTI0_PC14 SILABS_DBUS_TIMER1_CDTI0(0x2, 0xe) +#define TIMER1_CDTI0_PC15 SILABS_DBUS_TIMER1_CDTI0(0x2, 0xf) +#define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0) +#define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1) +#define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2) +#define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3) +#define TIMER1_CDTI0_PD4 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x4) +#define TIMER1_CDTI0_PD5 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x5) +#define TIMER1_CDTI0_PD6 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x6) +#define TIMER1_CDTI0_PD7 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x7) +#define TIMER1_CDTI0_PD8 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x8) +#define TIMER1_CDTI0_PD9 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x9) +#define TIMER1_CDTI0_PD10 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xa) +#define TIMER1_CDTI0_PD11 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xb) +#define TIMER1_CDTI0_PD12 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xc) +#define TIMER1_CDTI0_PD13 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xd) +#define TIMER1_CDTI0_PD14 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xe) +#define TIMER1_CDTI0_PD15 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xf) +#define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0) +#define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1) +#define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2) +#define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3) +#define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4) +#define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5) +#define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6) +#define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7) +#define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8) +#define TIMER1_CDTI1_PA9 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x9) +#define TIMER1_CDTI1_PA10 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xa) +#define TIMER1_CDTI1_PA11 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xb) +#define TIMER1_CDTI1_PA12 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xc) +#define TIMER1_CDTI1_PA13 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xd) +#define TIMER1_CDTI1_PA14 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xe) +#define TIMER1_CDTI1_PA15 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xf) +#define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0) +#define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1) +#define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2) +#define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3) +#define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4) +#define TIMER1_CDTI1_PB5 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x5) +#define TIMER1_CDTI1_PB6 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x6) +#define TIMER1_CDTI1_PB7 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x7) +#define TIMER1_CDTI1_PB8 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x8) +#define TIMER1_CDTI1_PB9 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x9) +#define TIMER1_CDTI1_PB10 SILABS_DBUS_TIMER1_CDTI1(0x1, 0xa) +#define TIMER1_CDTI1_PB11 SILABS_DBUS_TIMER1_CDTI1(0x1, 0xb) +#define TIMER1_CDTI1_PB12 SILABS_DBUS_TIMER1_CDTI1(0x1, 0xc) +#define TIMER1_CDTI1_PB13 SILABS_DBUS_TIMER1_CDTI1(0x1, 0xd) +#define TIMER1_CDTI1_PB14 SILABS_DBUS_TIMER1_CDTI1(0x1, 0xe) +#define TIMER1_CDTI1_PB15 SILABS_DBUS_TIMER1_CDTI1(0x1, 0xf) +#define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0) +#define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1) +#define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2) +#define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3) +#define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4) +#define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5) +#define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6) +#define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7) +#define TIMER1_CDTI1_PC8 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x8) +#define TIMER1_CDTI1_PC9 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x9) +#define TIMER1_CDTI1_PC10 SILABS_DBUS_TIMER1_CDTI1(0x2, 0xa) +#define TIMER1_CDTI1_PC11 SILABS_DBUS_TIMER1_CDTI1(0x2, 0xb) +#define TIMER1_CDTI1_PC12 SILABS_DBUS_TIMER1_CDTI1(0x2, 0xc) +#define TIMER1_CDTI1_PC13 SILABS_DBUS_TIMER1_CDTI1(0x2, 0xd) +#define TIMER1_CDTI1_PC14 SILABS_DBUS_TIMER1_CDTI1(0x2, 0xe) +#define TIMER1_CDTI1_PC15 SILABS_DBUS_TIMER1_CDTI1(0x2, 0xf) +#define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0) +#define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1) +#define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2) +#define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3) +#define TIMER1_CDTI1_PD4 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x4) +#define TIMER1_CDTI1_PD5 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x5) +#define TIMER1_CDTI1_PD6 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x6) +#define TIMER1_CDTI1_PD7 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x7) +#define TIMER1_CDTI1_PD8 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x8) +#define TIMER1_CDTI1_PD9 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x9) +#define TIMER1_CDTI1_PD10 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xa) +#define TIMER1_CDTI1_PD11 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xb) +#define TIMER1_CDTI1_PD12 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xc) +#define TIMER1_CDTI1_PD13 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xd) +#define TIMER1_CDTI1_PD14 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xe) +#define TIMER1_CDTI1_PD15 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xf) +#define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0) +#define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1) +#define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2) +#define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3) +#define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4) +#define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5) +#define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6) +#define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7) +#define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8) +#define TIMER1_CDTI2_PA9 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x9) +#define TIMER1_CDTI2_PA10 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xa) +#define TIMER1_CDTI2_PA11 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xb) +#define TIMER1_CDTI2_PA12 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xc) +#define TIMER1_CDTI2_PA13 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xd) +#define TIMER1_CDTI2_PA14 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xe) +#define TIMER1_CDTI2_PA15 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xf) +#define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0) +#define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1) +#define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2) +#define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3) +#define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4) +#define TIMER1_CDTI2_PB5 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x5) +#define TIMER1_CDTI2_PB6 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x6) +#define TIMER1_CDTI2_PB7 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x7) +#define TIMER1_CDTI2_PB8 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x8) +#define TIMER1_CDTI2_PB9 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x9) +#define TIMER1_CDTI2_PB10 SILABS_DBUS_TIMER1_CDTI2(0x1, 0xa) +#define TIMER1_CDTI2_PB11 SILABS_DBUS_TIMER1_CDTI2(0x1, 0xb) +#define TIMER1_CDTI2_PB12 SILABS_DBUS_TIMER1_CDTI2(0x1, 0xc) +#define TIMER1_CDTI2_PB13 SILABS_DBUS_TIMER1_CDTI2(0x1, 0xd) +#define TIMER1_CDTI2_PB14 SILABS_DBUS_TIMER1_CDTI2(0x1, 0xe) +#define TIMER1_CDTI2_PB15 SILABS_DBUS_TIMER1_CDTI2(0x1, 0xf) +#define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0) +#define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1) +#define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2) +#define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3) +#define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4) +#define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5) +#define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6) +#define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7) +#define TIMER1_CDTI2_PC8 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x8) +#define TIMER1_CDTI2_PC9 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x9) +#define TIMER1_CDTI2_PC10 SILABS_DBUS_TIMER1_CDTI2(0x2, 0xa) +#define TIMER1_CDTI2_PC11 SILABS_DBUS_TIMER1_CDTI2(0x2, 0xb) +#define TIMER1_CDTI2_PC12 SILABS_DBUS_TIMER1_CDTI2(0x2, 0xc) +#define TIMER1_CDTI2_PC13 SILABS_DBUS_TIMER1_CDTI2(0x2, 0xd) +#define TIMER1_CDTI2_PC14 SILABS_DBUS_TIMER1_CDTI2(0x2, 0xe) +#define TIMER1_CDTI2_PC15 SILABS_DBUS_TIMER1_CDTI2(0x2, 0xf) +#define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0) +#define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1) +#define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2) +#define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3) +#define TIMER1_CDTI2_PD4 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x4) +#define TIMER1_CDTI2_PD5 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x5) +#define TIMER1_CDTI2_PD6 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x6) +#define TIMER1_CDTI2_PD7 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x7) +#define TIMER1_CDTI2_PD8 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x8) +#define TIMER1_CDTI2_PD9 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x9) +#define TIMER1_CDTI2_PD10 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xa) +#define TIMER1_CDTI2_PD11 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xb) +#define TIMER1_CDTI2_PD12 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xc) +#define TIMER1_CDTI2_PD13 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xd) +#define TIMER1_CDTI2_PD14 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xe) +#define TIMER1_CDTI2_PD15 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xf) + +#define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0) +#define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1) +#define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2) +#define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3) +#define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4) +#define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5) +#define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6) +#define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7) +#define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8) +#define TIMER2_CC0_PA9 SILABS_DBUS_TIMER2_CC0(0x0, 0x9) +#define TIMER2_CC0_PA10 SILABS_DBUS_TIMER2_CC0(0x0, 0xa) +#define TIMER2_CC0_PA11 SILABS_DBUS_TIMER2_CC0(0x0, 0xb) +#define TIMER2_CC0_PA12 SILABS_DBUS_TIMER2_CC0(0x0, 0xc) +#define TIMER2_CC0_PA13 SILABS_DBUS_TIMER2_CC0(0x0, 0xd) +#define TIMER2_CC0_PA14 SILABS_DBUS_TIMER2_CC0(0x0, 0xe) +#define TIMER2_CC0_PA15 SILABS_DBUS_TIMER2_CC0(0x0, 0xf) +#define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0) +#define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1) +#define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2) +#define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3) +#define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4) +#define TIMER2_CC0_PB5 SILABS_DBUS_TIMER2_CC0(0x1, 0x5) +#define TIMER2_CC0_PB6 SILABS_DBUS_TIMER2_CC0(0x1, 0x6) +#define TIMER2_CC0_PB7 SILABS_DBUS_TIMER2_CC0(0x1, 0x7) +#define TIMER2_CC0_PB8 SILABS_DBUS_TIMER2_CC0(0x1, 0x8) +#define TIMER2_CC0_PB9 SILABS_DBUS_TIMER2_CC0(0x1, 0x9) +#define TIMER2_CC0_PB10 SILABS_DBUS_TIMER2_CC0(0x1, 0xa) +#define TIMER2_CC0_PB11 SILABS_DBUS_TIMER2_CC0(0x1, 0xb) +#define TIMER2_CC0_PB12 SILABS_DBUS_TIMER2_CC0(0x1, 0xc) +#define TIMER2_CC0_PB13 SILABS_DBUS_TIMER2_CC0(0x1, 0xd) +#define TIMER2_CC0_PB14 SILABS_DBUS_TIMER2_CC0(0x1, 0xe) +#define TIMER2_CC0_PB15 SILABS_DBUS_TIMER2_CC0(0x1, 0xf) +#define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0) +#define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1) +#define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2) +#define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3) +#define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4) +#define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5) +#define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6) +#define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7) +#define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8) +#define TIMER2_CC1_PA9 SILABS_DBUS_TIMER2_CC1(0x0, 0x9) +#define TIMER2_CC1_PA10 SILABS_DBUS_TIMER2_CC1(0x0, 0xa) +#define TIMER2_CC1_PA11 SILABS_DBUS_TIMER2_CC1(0x0, 0xb) +#define TIMER2_CC1_PA12 SILABS_DBUS_TIMER2_CC1(0x0, 0xc) +#define TIMER2_CC1_PA13 SILABS_DBUS_TIMER2_CC1(0x0, 0xd) +#define TIMER2_CC1_PA14 SILABS_DBUS_TIMER2_CC1(0x0, 0xe) +#define TIMER2_CC1_PA15 SILABS_DBUS_TIMER2_CC1(0x0, 0xf) +#define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0) +#define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1) +#define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2) +#define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3) +#define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4) +#define TIMER2_CC1_PB5 SILABS_DBUS_TIMER2_CC1(0x1, 0x5) +#define TIMER2_CC1_PB6 SILABS_DBUS_TIMER2_CC1(0x1, 0x6) +#define TIMER2_CC1_PB7 SILABS_DBUS_TIMER2_CC1(0x1, 0x7) +#define TIMER2_CC1_PB8 SILABS_DBUS_TIMER2_CC1(0x1, 0x8) +#define TIMER2_CC1_PB9 SILABS_DBUS_TIMER2_CC1(0x1, 0x9) +#define TIMER2_CC1_PB10 SILABS_DBUS_TIMER2_CC1(0x1, 0xa) +#define TIMER2_CC1_PB11 SILABS_DBUS_TIMER2_CC1(0x1, 0xb) +#define TIMER2_CC1_PB12 SILABS_DBUS_TIMER2_CC1(0x1, 0xc) +#define TIMER2_CC1_PB13 SILABS_DBUS_TIMER2_CC1(0x1, 0xd) +#define TIMER2_CC1_PB14 SILABS_DBUS_TIMER2_CC1(0x1, 0xe) +#define TIMER2_CC1_PB15 SILABS_DBUS_TIMER2_CC1(0x1, 0xf) +#define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0) +#define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1) +#define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2) +#define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3) +#define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4) +#define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5) +#define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6) +#define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7) +#define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8) +#define TIMER2_CC2_PA9 SILABS_DBUS_TIMER2_CC2(0x0, 0x9) +#define TIMER2_CC2_PA10 SILABS_DBUS_TIMER2_CC2(0x0, 0xa) +#define TIMER2_CC2_PA11 SILABS_DBUS_TIMER2_CC2(0x0, 0xb) +#define TIMER2_CC2_PA12 SILABS_DBUS_TIMER2_CC2(0x0, 0xc) +#define TIMER2_CC2_PA13 SILABS_DBUS_TIMER2_CC2(0x0, 0xd) +#define TIMER2_CC2_PA14 SILABS_DBUS_TIMER2_CC2(0x0, 0xe) +#define TIMER2_CC2_PA15 SILABS_DBUS_TIMER2_CC2(0x0, 0xf) +#define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0) +#define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1) +#define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2) +#define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3) +#define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4) +#define TIMER2_CC2_PB5 SILABS_DBUS_TIMER2_CC2(0x1, 0x5) +#define TIMER2_CC2_PB6 SILABS_DBUS_TIMER2_CC2(0x1, 0x6) +#define TIMER2_CC2_PB7 SILABS_DBUS_TIMER2_CC2(0x1, 0x7) +#define TIMER2_CC2_PB8 SILABS_DBUS_TIMER2_CC2(0x1, 0x8) +#define TIMER2_CC2_PB9 SILABS_DBUS_TIMER2_CC2(0x1, 0x9) +#define TIMER2_CC2_PB10 SILABS_DBUS_TIMER2_CC2(0x1, 0xa) +#define TIMER2_CC2_PB11 SILABS_DBUS_TIMER2_CC2(0x1, 0xb) +#define TIMER2_CC2_PB12 SILABS_DBUS_TIMER2_CC2(0x1, 0xc) +#define TIMER2_CC2_PB13 SILABS_DBUS_TIMER2_CC2(0x1, 0xd) +#define TIMER2_CC2_PB14 SILABS_DBUS_TIMER2_CC2(0x1, 0xe) +#define TIMER2_CC2_PB15 SILABS_DBUS_TIMER2_CC2(0x1, 0xf) +#define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0) +#define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1) +#define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2) +#define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3) +#define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4) +#define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5) +#define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6) +#define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7) +#define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8) +#define TIMER2_CDTI0_PA9 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x9) +#define TIMER2_CDTI0_PA10 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xa) +#define TIMER2_CDTI0_PA11 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xb) +#define TIMER2_CDTI0_PA12 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xc) +#define TIMER2_CDTI0_PA13 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xd) +#define TIMER2_CDTI0_PA14 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xe) +#define TIMER2_CDTI0_PA15 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xf) +#define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0) +#define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1) +#define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2) +#define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3) +#define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4) +#define TIMER2_CDTI0_PB5 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x5) +#define TIMER2_CDTI0_PB6 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x6) +#define TIMER2_CDTI0_PB7 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x7) +#define TIMER2_CDTI0_PB8 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x8) +#define TIMER2_CDTI0_PB9 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x9) +#define TIMER2_CDTI0_PB10 SILABS_DBUS_TIMER2_CDTI0(0x1, 0xa) +#define TIMER2_CDTI0_PB11 SILABS_DBUS_TIMER2_CDTI0(0x1, 0xb) +#define TIMER2_CDTI0_PB12 SILABS_DBUS_TIMER2_CDTI0(0x1, 0xc) +#define TIMER2_CDTI0_PB13 SILABS_DBUS_TIMER2_CDTI0(0x1, 0xd) +#define TIMER2_CDTI0_PB14 SILABS_DBUS_TIMER2_CDTI0(0x1, 0xe) +#define TIMER2_CDTI0_PB15 SILABS_DBUS_TIMER2_CDTI0(0x1, 0xf) +#define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0) +#define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1) +#define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2) +#define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3) +#define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4) +#define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5) +#define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6) +#define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7) +#define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8) +#define TIMER2_CDTI1_PA9 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x9) +#define TIMER2_CDTI1_PA10 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xa) +#define TIMER2_CDTI1_PA11 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xb) +#define TIMER2_CDTI1_PA12 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xc) +#define TIMER2_CDTI1_PA13 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xd) +#define TIMER2_CDTI1_PA14 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xe) +#define TIMER2_CDTI1_PA15 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xf) +#define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0) +#define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1) +#define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2) +#define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3) +#define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4) +#define TIMER2_CDTI1_PB5 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x5) +#define TIMER2_CDTI1_PB6 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x6) +#define TIMER2_CDTI1_PB7 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x7) +#define TIMER2_CDTI1_PB8 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x8) +#define TIMER2_CDTI1_PB9 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x9) +#define TIMER2_CDTI1_PB10 SILABS_DBUS_TIMER2_CDTI1(0x1, 0xa) +#define TIMER2_CDTI1_PB11 SILABS_DBUS_TIMER2_CDTI1(0x1, 0xb) +#define TIMER2_CDTI1_PB12 SILABS_DBUS_TIMER2_CDTI1(0x1, 0xc) +#define TIMER2_CDTI1_PB13 SILABS_DBUS_TIMER2_CDTI1(0x1, 0xd) +#define TIMER2_CDTI1_PB14 SILABS_DBUS_TIMER2_CDTI1(0x1, 0xe) +#define TIMER2_CDTI1_PB15 SILABS_DBUS_TIMER2_CDTI1(0x1, 0xf) +#define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0) +#define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1) +#define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2) +#define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3) +#define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4) +#define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5) +#define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6) +#define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7) +#define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8) +#define TIMER2_CDTI2_PA9 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x9) +#define TIMER2_CDTI2_PA10 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xa) +#define TIMER2_CDTI2_PA11 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xb) +#define TIMER2_CDTI2_PA12 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xc) +#define TIMER2_CDTI2_PA13 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xd) +#define TIMER2_CDTI2_PA14 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xe) +#define TIMER2_CDTI2_PA15 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xf) +#define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0) +#define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1) +#define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2) +#define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3) +#define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4) +#define TIMER2_CDTI2_PB5 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x5) +#define TIMER2_CDTI2_PB6 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x6) +#define TIMER2_CDTI2_PB7 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x7) +#define TIMER2_CDTI2_PB8 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x8) +#define TIMER2_CDTI2_PB9 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x9) +#define TIMER2_CDTI2_PB10 SILABS_DBUS_TIMER2_CDTI2(0x1, 0xa) +#define TIMER2_CDTI2_PB11 SILABS_DBUS_TIMER2_CDTI2(0x1, 0xb) +#define TIMER2_CDTI2_PB12 SILABS_DBUS_TIMER2_CDTI2(0x1, 0xc) +#define TIMER2_CDTI2_PB13 SILABS_DBUS_TIMER2_CDTI2(0x1, 0xd) +#define TIMER2_CDTI2_PB14 SILABS_DBUS_TIMER2_CDTI2(0x1, 0xe) +#define TIMER2_CDTI2_PB15 SILABS_DBUS_TIMER2_CDTI2(0x1, 0xf) + +#define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0) +#define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1) +#define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2) +#define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3) +#define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4) +#define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5) +#define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6) +#define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7) +#define TIMER3_CC0_PC8 SILABS_DBUS_TIMER3_CC0(0x2, 0x8) +#define TIMER3_CC0_PC9 SILABS_DBUS_TIMER3_CC0(0x2, 0x9) +#define TIMER3_CC0_PC10 SILABS_DBUS_TIMER3_CC0(0x2, 0xa) +#define TIMER3_CC0_PC11 SILABS_DBUS_TIMER3_CC0(0x2, 0xb) +#define TIMER3_CC0_PC12 SILABS_DBUS_TIMER3_CC0(0x2, 0xc) +#define TIMER3_CC0_PC13 SILABS_DBUS_TIMER3_CC0(0x2, 0xd) +#define TIMER3_CC0_PC14 SILABS_DBUS_TIMER3_CC0(0x2, 0xe) +#define TIMER3_CC0_PC15 SILABS_DBUS_TIMER3_CC0(0x2, 0xf) +#define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0) +#define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1) +#define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2) +#define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3) +#define TIMER3_CC0_PD4 SILABS_DBUS_TIMER3_CC0(0x3, 0x4) +#define TIMER3_CC0_PD5 SILABS_DBUS_TIMER3_CC0(0x3, 0x5) +#define TIMER3_CC0_PD6 SILABS_DBUS_TIMER3_CC0(0x3, 0x6) +#define TIMER3_CC0_PD7 SILABS_DBUS_TIMER3_CC0(0x3, 0x7) +#define TIMER3_CC0_PD8 SILABS_DBUS_TIMER3_CC0(0x3, 0x8) +#define TIMER3_CC0_PD9 SILABS_DBUS_TIMER3_CC0(0x3, 0x9) +#define TIMER3_CC0_PD10 SILABS_DBUS_TIMER3_CC0(0x3, 0xa) +#define TIMER3_CC0_PD11 SILABS_DBUS_TIMER3_CC0(0x3, 0xb) +#define TIMER3_CC0_PD12 SILABS_DBUS_TIMER3_CC0(0x3, 0xc) +#define TIMER3_CC0_PD13 SILABS_DBUS_TIMER3_CC0(0x3, 0xd) +#define TIMER3_CC0_PD14 SILABS_DBUS_TIMER3_CC0(0x3, 0xe) +#define TIMER3_CC0_PD15 SILABS_DBUS_TIMER3_CC0(0x3, 0xf) +#define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0) +#define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1) +#define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2) +#define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3) +#define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4) +#define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5) +#define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6) +#define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7) +#define TIMER3_CC1_PC8 SILABS_DBUS_TIMER3_CC1(0x2, 0x8) +#define TIMER3_CC1_PC9 SILABS_DBUS_TIMER3_CC1(0x2, 0x9) +#define TIMER3_CC1_PC10 SILABS_DBUS_TIMER3_CC1(0x2, 0xa) +#define TIMER3_CC1_PC11 SILABS_DBUS_TIMER3_CC1(0x2, 0xb) +#define TIMER3_CC1_PC12 SILABS_DBUS_TIMER3_CC1(0x2, 0xc) +#define TIMER3_CC1_PC13 SILABS_DBUS_TIMER3_CC1(0x2, 0xd) +#define TIMER3_CC1_PC14 SILABS_DBUS_TIMER3_CC1(0x2, 0xe) +#define TIMER3_CC1_PC15 SILABS_DBUS_TIMER3_CC1(0x2, 0xf) +#define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0) +#define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1) +#define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2) +#define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3) +#define TIMER3_CC1_PD4 SILABS_DBUS_TIMER3_CC1(0x3, 0x4) +#define TIMER3_CC1_PD5 SILABS_DBUS_TIMER3_CC1(0x3, 0x5) +#define TIMER3_CC1_PD6 SILABS_DBUS_TIMER3_CC1(0x3, 0x6) +#define TIMER3_CC1_PD7 SILABS_DBUS_TIMER3_CC1(0x3, 0x7) +#define TIMER3_CC1_PD8 SILABS_DBUS_TIMER3_CC1(0x3, 0x8) +#define TIMER3_CC1_PD9 SILABS_DBUS_TIMER3_CC1(0x3, 0x9) +#define TIMER3_CC1_PD10 SILABS_DBUS_TIMER3_CC1(0x3, 0xa) +#define TIMER3_CC1_PD11 SILABS_DBUS_TIMER3_CC1(0x3, 0xb) +#define TIMER3_CC1_PD12 SILABS_DBUS_TIMER3_CC1(0x3, 0xc) +#define TIMER3_CC1_PD13 SILABS_DBUS_TIMER3_CC1(0x3, 0xd) +#define TIMER3_CC1_PD14 SILABS_DBUS_TIMER3_CC1(0x3, 0xe) +#define TIMER3_CC1_PD15 SILABS_DBUS_TIMER3_CC1(0x3, 0xf) +#define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0) +#define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1) +#define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2) +#define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3) +#define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4) +#define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5) +#define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6) +#define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7) +#define TIMER3_CC2_PC8 SILABS_DBUS_TIMER3_CC2(0x2, 0x8) +#define TIMER3_CC2_PC9 SILABS_DBUS_TIMER3_CC2(0x2, 0x9) +#define TIMER3_CC2_PC10 SILABS_DBUS_TIMER3_CC2(0x2, 0xa) +#define TIMER3_CC2_PC11 SILABS_DBUS_TIMER3_CC2(0x2, 0xb) +#define TIMER3_CC2_PC12 SILABS_DBUS_TIMER3_CC2(0x2, 0xc) +#define TIMER3_CC2_PC13 SILABS_DBUS_TIMER3_CC2(0x2, 0xd) +#define TIMER3_CC2_PC14 SILABS_DBUS_TIMER3_CC2(0x2, 0xe) +#define TIMER3_CC2_PC15 SILABS_DBUS_TIMER3_CC2(0x2, 0xf) +#define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0) +#define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1) +#define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2) +#define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3) +#define TIMER3_CC2_PD4 SILABS_DBUS_TIMER3_CC2(0x3, 0x4) +#define TIMER3_CC2_PD5 SILABS_DBUS_TIMER3_CC2(0x3, 0x5) +#define TIMER3_CC2_PD6 SILABS_DBUS_TIMER3_CC2(0x3, 0x6) +#define TIMER3_CC2_PD7 SILABS_DBUS_TIMER3_CC2(0x3, 0x7) +#define TIMER3_CC2_PD8 SILABS_DBUS_TIMER3_CC2(0x3, 0x8) +#define TIMER3_CC2_PD9 SILABS_DBUS_TIMER3_CC2(0x3, 0x9) +#define TIMER3_CC2_PD10 SILABS_DBUS_TIMER3_CC2(0x3, 0xa) +#define TIMER3_CC2_PD11 SILABS_DBUS_TIMER3_CC2(0x3, 0xb) +#define TIMER3_CC2_PD12 SILABS_DBUS_TIMER3_CC2(0x3, 0xc) +#define TIMER3_CC2_PD13 SILABS_DBUS_TIMER3_CC2(0x3, 0xd) +#define TIMER3_CC2_PD14 SILABS_DBUS_TIMER3_CC2(0x3, 0xe) +#define TIMER3_CC2_PD15 SILABS_DBUS_TIMER3_CC2(0x3, 0xf) +#define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0) +#define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1) +#define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2) +#define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3) +#define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4) +#define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5) +#define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6) +#define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7) +#define TIMER3_CDTI0_PC8 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x8) +#define TIMER3_CDTI0_PC9 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x9) +#define TIMER3_CDTI0_PC10 SILABS_DBUS_TIMER3_CDTI0(0x2, 0xa) +#define TIMER3_CDTI0_PC11 SILABS_DBUS_TIMER3_CDTI0(0x2, 0xb) +#define TIMER3_CDTI0_PC12 SILABS_DBUS_TIMER3_CDTI0(0x2, 0xc) +#define TIMER3_CDTI0_PC13 SILABS_DBUS_TIMER3_CDTI0(0x2, 0xd) +#define TIMER3_CDTI0_PC14 SILABS_DBUS_TIMER3_CDTI0(0x2, 0xe) +#define TIMER3_CDTI0_PC15 SILABS_DBUS_TIMER3_CDTI0(0x2, 0xf) +#define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0) +#define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1) +#define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2) +#define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3) +#define TIMER3_CDTI0_PD4 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x4) +#define TIMER3_CDTI0_PD5 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x5) +#define TIMER3_CDTI0_PD6 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x6) +#define TIMER3_CDTI0_PD7 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x7) +#define TIMER3_CDTI0_PD8 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x8) +#define TIMER3_CDTI0_PD9 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x9) +#define TIMER3_CDTI0_PD10 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xa) +#define TIMER3_CDTI0_PD11 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xb) +#define TIMER3_CDTI0_PD12 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xc) +#define TIMER3_CDTI0_PD13 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xd) +#define TIMER3_CDTI0_PD14 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xe) +#define TIMER3_CDTI0_PD15 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xf) +#define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0) +#define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1) +#define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2) +#define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3) +#define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4) +#define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5) +#define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6) +#define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7) +#define TIMER3_CDTI1_PC8 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x8) +#define TIMER3_CDTI1_PC9 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x9) +#define TIMER3_CDTI1_PC10 SILABS_DBUS_TIMER3_CDTI1(0x2, 0xa) +#define TIMER3_CDTI1_PC11 SILABS_DBUS_TIMER3_CDTI1(0x2, 0xb) +#define TIMER3_CDTI1_PC12 SILABS_DBUS_TIMER3_CDTI1(0x2, 0xc) +#define TIMER3_CDTI1_PC13 SILABS_DBUS_TIMER3_CDTI1(0x2, 0xd) +#define TIMER3_CDTI1_PC14 SILABS_DBUS_TIMER3_CDTI1(0x2, 0xe) +#define TIMER3_CDTI1_PC15 SILABS_DBUS_TIMER3_CDTI1(0x2, 0xf) +#define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0) +#define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1) +#define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2) +#define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3) +#define TIMER3_CDTI1_PD4 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x4) +#define TIMER3_CDTI1_PD5 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x5) +#define TIMER3_CDTI1_PD6 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x6) +#define TIMER3_CDTI1_PD7 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x7) +#define TIMER3_CDTI1_PD8 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x8) +#define TIMER3_CDTI1_PD9 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x9) +#define TIMER3_CDTI1_PD10 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xa) +#define TIMER3_CDTI1_PD11 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xb) +#define TIMER3_CDTI1_PD12 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xc) +#define TIMER3_CDTI1_PD13 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xd) +#define TIMER3_CDTI1_PD14 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xe) +#define TIMER3_CDTI1_PD15 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xf) +#define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0) +#define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1) +#define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2) +#define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3) +#define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4) +#define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5) +#define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6) +#define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7) +#define TIMER3_CDTI2_PC8 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x8) +#define TIMER3_CDTI2_PC9 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x9) +#define TIMER3_CDTI2_PC10 SILABS_DBUS_TIMER3_CDTI2(0x2, 0xa) +#define TIMER3_CDTI2_PC11 SILABS_DBUS_TIMER3_CDTI2(0x2, 0xb) +#define TIMER3_CDTI2_PC12 SILABS_DBUS_TIMER3_CDTI2(0x2, 0xc) +#define TIMER3_CDTI2_PC13 SILABS_DBUS_TIMER3_CDTI2(0x2, 0xd) +#define TIMER3_CDTI2_PC14 SILABS_DBUS_TIMER3_CDTI2(0x2, 0xe) +#define TIMER3_CDTI2_PC15 SILABS_DBUS_TIMER3_CDTI2(0x2, 0xf) +#define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0) +#define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1) +#define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2) +#define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3) +#define TIMER3_CDTI2_PD4 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x4) +#define TIMER3_CDTI2_PD5 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x5) +#define TIMER3_CDTI2_PD6 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x6) +#define TIMER3_CDTI2_PD7 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x7) +#define TIMER3_CDTI2_PD8 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x8) +#define TIMER3_CDTI2_PD9 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x9) +#define TIMER3_CDTI2_PD10 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xa) +#define TIMER3_CDTI2_PD11 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xb) +#define TIMER3_CDTI2_PD12 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xc) +#define TIMER3_CDTI2_PD13 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xd) +#define TIMER3_CDTI2_PD14 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xe) +#define TIMER3_CDTI2_PD15 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xf) + +#define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0) +#define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1) +#define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2) +#define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3) +#define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4) +#define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5) +#define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6) +#define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7) +#define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8) +#define TIMER4_CC0_PA9 SILABS_DBUS_TIMER4_CC0(0x0, 0x9) +#define TIMER4_CC0_PA10 SILABS_DBUS_TIMER4_CC0(0x0, 0xa) +#define TIMER4_CC0_PA11 SILABS_DBUS_TIMER4_CC0(0x0, 0xb) +#define TIMER4_CC0_PA12 SILABS_DBUS_TIMER4_CC0(0x0, 0xc) +#define TIMER4_CC0_PA13 SILABS_DBUS_TIMER4_CC0(0x0, 0xd) +#define TIMER4_CC0_PA14 SILABS_DBUS_TIMER4_CC0(0x0, 0xe) +#define TIMER4_CC0_PA15 SILABS_DBUS_TIMER4_CC0(0x0, 0xf) +#define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0) +#define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1) +#define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2) +#define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3) +#define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4) +#define TIMER4_CC0_PB5 SILABS_DBUS_TIMER4_CC0(0x1, 0x5) +#define TIMER4_CC0_PB6 SILABS_DBUS_TIMER4_CC0(0x1, 0x6) +#define TIMER4_CC0_PB7 SILABS_DBUS_TIMER4_CC0(0x1, 0x7) +#define TIMER4_CC0_PB8 SILABS_DBUS_TIMER4_CC0(0x1, 0x8) +#define TIMER4_CC0_PB9 SILABS_DBUS_TIMER4_CC0(0x1, 0x9) +#define TIMER4_CC0_PB10 SILABS_DBUS_TIMER4_CC0(0x1, 0xa) +#define TIMER4_CC0_PB11 SILABS_DBUS_TIMER4_CC0(0x1, 0xb) +#define TIMER4_CC0_PB12 SILABS_DBUS_TIMER4_CC0(0x1, 0xc) +#define TIMER4_CC0_PB13 SILABS_DBUS_TIMER4_CC0(0x1, 0xd) +#define TIMER4_CC0_PB14 SILABS_DBUS_TIMER4_CC0(0x1, 0xe) +#define TIMER4_CC0_PB15 SILABS_DBUS_TIMER4_CC0(0x1, 0xf) +#define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0) +#define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1) +#define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2) +#define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3) +#define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4) +#define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5) +#define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6) +#define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7) +#define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8) +#define TIMER4_CC1_PA9 SILABS_DBUS_TIMER4_CC1(0x0, 0x9) +#define TIMER4_CC1_PA10 SILABS_DBUS_TIMER4_CC1(0x0, 0xa) +#define TIMER4_CC1_PA11 SILABS_DBUS_TIMER4_CC1(0x0, 0xb) +#define TIMER4_CC1_PA12 SILABS_DBUS_TIMER4_CC1(0x0, 0xc) +#define TIMER4_CC1_PA13 SILABS_DBUS_TIMER4_CC1(0x0, 0xd) +#define TIMER4_CC1_PA14 SILABS_DBUS_TIMER4_CC1(0x0, 0xe) +#define TIMER4_CC1_PA15 SILABS_DBUS_TIMER4_CC1(0x0, 0xf) +#define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0) +#define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1) +#define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2) +#define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3) +#define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4) +#define TIMER4_CC1_PB5 SILABS_DBUS_TIMER4_CC1(0x1, 0x5) +#define TIMER4_CC1_PB6 SILABS_DBUS_TIMER4_CC1(0x1, 0x6) +#define TIMER4_CC1_PB7 SILABS_DBUS_TIMER4_CC1(0x1, 0x7) +#define TIMER4_CC1_PB8 SILABS_DBUS_TIMER4_CC1(0x1, 0x8) +#define TIMER4_CC1_PB9 SILABS_DBUS_TIMER4_CC1(0x1, 0x9) +#define TIMER4_CC1_PB10 SILABS_DBUS_TIMER4_CC1(0x1, 0xa) +#define TIMER4_CC1_PB11 SILABS_DBUS_TIMER4_CC1(0x1, 0xb) +#define TIMER4_CC1_PB12 SILABS_DBUS_TIMER4_CC1(0x1, 0xc) +#define TIMER4_CC1_PB13 SILABS_DBUS_TIMER4_CC1(0x1, 0xd) +#define TIMER4_CC1_PB14 SILABS_DBUS_TIMER4_CC1(0x1, 0xe) +#define TIMER4_CC1_PB15 SILABS_DBUS_TIMER4_CC1(0x1, 0xf) +#define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0) +#define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1) +#define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2) +#define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3) +#define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4) +#define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5) +#define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6) +#define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7) +#define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8) +#define TIMER4_CC2_PA9 SILABS_DBUS_TIMER4_CC2(0x0, 0x9) +#define TIMER4_CC2_PA10 SILABS_DBUS_TIMER4_CC2(0x0, 0xa) +#define TIMER4_CC2_PA11 SILABS_DBUS_TIMER4_CC2(0x0, 0xb) +#define TIMER4_CC2_PA12 SILABS_DBUS_TIMER4_CC2(0x0, 0xc) +#define TIMER4_CC2_PA13 SILABS_DBUS_TIMER4_CC2(0x0, 0xd) +#define TIMER4_CC2_PA14 SILABS_DBUS_TIMER4_CC2(0x0, 0xe) +#define TIMER4_CC2_PA15 SILABS_DBUS_TIMER4_CC2(0x0, 0xf) +#define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0) +#define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1) +#define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2) +#define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3) +#define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4) +#define TIMER4_CC2_PB5 SILABS_DBUS_TIMER4_CC2(0x1, 0x5) +#define TIMER4_CC2_PB6 SILABS_DBUS_TIMER4_CC2(0x1, 0x6) +#define TIMER4_CC2_PB7 SILABS_DBUS_TIMER4_CC2(0x1, 0x7) +#define TIMER4_CC2_PB8 SILABS_DBUS_TIMER4_CC2(0x1, 0x8) +#define TIMER4_CC2_PB9 SILABS_DBUS_TIMER4_CC2(0x1, 0x9) +#define TIMER4_CC2_PB10 SILABS_DBUS_TIMER4_CC2(0x1, 0xa) +#define TIMER4_CC2_PB11 SILABS_DBUS_TIMER4_CC2(0x1, 0xb) +#define TIMER4_CC2_PB12 SILABS_DBUS_TIMER4_CC2(0x1, 0xc) +#define TIMER4_CC2_PB13 SILABS_DBUS_TIMER4_CC2(0x1, 0xd) +#define TIMER4_CC2_PB14 SILABS_DBUS_TIMER4_CC2(0x1, 0xe) +#define TIMER4_CC2_PB15 SILABS_DBUS_TIMER4_CC2(0x1, 0xf) +#define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0) +#define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1) +#define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2) +#define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3) +#define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4) +#define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5) +#define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6) +#define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7) +#define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8) +#define TIMER4_CDTI0_PA9 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x9) +#define TIMER4_CDTI0_PA10 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xa) +#define TIMER4_CDTI0_PA11 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xb) +#define TIMER4_CDTI0_PA12 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xc) +#define TIMER4_CDTI0_PA13 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xd) +#define TIMER4_CDTI0_PA14 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xe) +#define TIMER4_CDTI0_PA15 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xf) +#define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0) +#define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1) +#define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2) +#define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3) +#define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4) +#define TIMER4_CDTI0_PB5 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x5) +#define TIMER4_CDTI0_PB6 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x6) +#define TIMER4_CDTI0_PB7 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x7) +#define TIMER4_CDTI0_PB8 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x8) +#define TIMER4_CDTI0_PB9 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x9) +#define TIMER4_CDTI0_PB10 SILABS_DBUS_TIMER4_CDTI0(0x1, 0xa) +#define TIMER4_CDTI0_PB11 SILABS_DBUS_TIMER4_CDTI0(0x1, 0xb) +#define TIMER4_CDTI0_PB12 SILABS_DBUS_TIMER4_CDTI0(0x1, 0xc) +#define TIMER4_CDTI0_PB13 SILABS_DBUS_TIMER4_CDTI0(0x1, 0xd) +#define TIMER4_CDTI0_PB14 SILABS_DBUS_TIMER4_CDTI0(0x1, 0xe) +#define TIMER4_CDTI0_PB15 SILABS_DBUS_TIMER4_CDTI0(0x1, 0xf) +#define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0) +#define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1) +#define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2) +#define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3) +#define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4) +#define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5) +#define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6) +#define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7) +#define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8) +#define TIMER4_CDTI1_PA9 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x9) +#define TIMER4_CDTI1_PA10 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xa) +#define TIMER4_CDTI1_PA11 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xb) +#define TIMER4_CDTI1_PA12 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xc) +#define TIMER4_CDTI1_PA13 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xd) +#define TIMER4_CDTI1_PA14 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xe) +#define TIMER4_CDTI1_PA15 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xf) +#define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0) +#define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1) +#define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2) +#define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3) +#define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4) +#define TIMER4_CDTI1_PB5 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x5) +#define TIMER4_CDTI1_PB6 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x6) +#define TIMER4_CDTI1_PB7 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x7) +#define TIMER4_CDTI1_PB8 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x8) +#define TIMER4_CDTI1_PB9 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x9) +#define TIMER4_CDTI1_PB10 SILABS_DBUS_TIMER4_CDTI1(0x1, 0xa) +#define TIMER4_CDTI1_PB11 SILABS_DBUS_TIMER4_CDTI1(0x1, 0xb) +#define TIMER4_CDTI1_PB12 SILABS_DBUS_TIMER4_CDTI1(0x1, 0xc) +#define TIMER4_CDTI1_PB13 SILABS_DBUS_TIMER4_CDTI1(0x1, 0xd) +#define TIMER4_CDTI1_PB14 SILABS_DBUS_TIMER4_CDTI1(0x1, 0xe) +#define TIMER4_CDTI1_PB15 SILABS_DBUS_TIMER4_CDTI1(0x1, 0xf) +#define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0) +#define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1) +#define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2) +#define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3) +#define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4) +#define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5) +#define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6) +#define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7) +#define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8) +#define TIMER4_CDTI2_PA9 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x9) +#define TIMER4_CDTI2_PA10 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xa) +#define TIMER4_CDTI2_PA11 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xb) +#define TIMER4_CDTI2_PA12 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xc) +#define TIMER4_CDTI2_PA13 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xd) +#define TIMER4_CDTI2_PA14 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xe) +#define TIMER4_CDTI2_PA15 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xf) +#define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0) +#define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1) +#define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2) +#define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3) +#define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4) +#define TIMER4_CDTI2_PB5 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x5) +#define TIMER4_CDTI2_PB6 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x6) +#define TIMER4_CDTI2_PB7 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x7) +#define TIMER4_CDTI2_PB8 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x8) +#define TIMER4_CDTI2_PB9 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x9) +#define TIMER4_CDTI2_PB10 SILABS_DBUS_TIMER4_CDTI2(0x1, 0xa) +#define TIMER4_CDTI2_PB11 SILABS_DBUS_TIMER4_CDTI2(0x1, 0xb) +#define TIMER4_CDTI2_PB12 SILABS_DBUS_TIMER4_CDTI2(0x1, 0xc) +#define TIMER4_CDTI2_PB13 SILABS_DBUS_TIMER4_CDTI2(0x1, 0xd) +#define TIMER4_CDTI2_PB14 SILABS_DBUS_TIMER4_CDTI2(0x1, 0xe) +#define TIMER4_CDTI2_PB15 SILABS_DBUS_TIMER4_CDTI2(0x1, 0xf) + +#define TIMER5_CC0_PA0 SILABS_DBUS_TIMER5_CC0(0x0, 0x0) +#define TIMER5_CC0_PA1 SILABS_DBUS_TIMER5_CC0(0x0, 0x1) +#define TIMER5_CC0_PA2 SILABS_DBUS_TIMER5_CC0(0x0, 0x2) +#define TIMER5_CC0_PA3 SILABS_DBUS_TIMER5_CC0(0x0, 0x3) +#define TIMER5_CC0_PA4 SILABS_DBUS_TIMER5_CC0(0x0, 0x4) +#define TIMER5_CC0_PA5 SILABS_DBUS_TIMER5_CC0(0x0, 0x5) +#define TIMER5_CC0_PA6 SILABS_DBUS_TIMER5_CC0(0x0, 0x6) +#define TIMER5_CC0_PA7 SILABS_DBUS_TIMER5_CC0(0x0, 0x7) +#define TIMER5_CC0_PA8 SILABS_DBUS_TIMER5_CC0(0x0, 0x8) +#define TIMER5_CC0_PA9 SILABS_DBUS_TIMER5_CC0(0x0, 0x9) +#define TIMER5_CC0_PA10 SILABS_DBUS_TIMER5_CC0(0x0, 0xa) +#define TIMER5_CC0_PA11 SILABS_DBUS_TIMER5_CC0(0x0, 0xb) +#define TIMER5_CC0_PA12 SILABS_DBUS_TIMER5_CC0(0x0, 0xc) +#define TIMER5_CC0_PA13 SILABS_DBUS_TIMER5_CC0(0x0, 0xd) +#define TIMER5_CC0_PA14 SILABS_DBUS_TIMER5_CC0(0x0, 0xe) +#define TIMER5_CC0_PA15 SILABS_DBUS_TIMER5_CC0(0x0, 0xf) +#define TIMER5_CC0_PB0 SILABS_DBUS_TIMER5_CC0(0x1, 0x0) +#define TIMER5_CC0_PB1 SILABS_DBUS_TIMER5_CC0(0x1, 0x1) +#define TIMER5_CC0_PB2 SILABS_DBUS_TIMER5_CC0(0x1, 0x2) +#define TIMER5_CC0_PB3 SILABS_DBUS_TIMER5_CC0(0x1, 0x3) +#define TIMER5_CC0_PB4 SILABS_DBUS_TIMER5_CC0(0x1, 0x4) +#define TIMER5_CC0_PB5 SILABS_DBUS_TIMER5_CC0(0x1, 0x5) +#define TIMER5_CC0_PB6 SILABS_DBUS_TIMER5_CC0(0x1, 0x6) +#define TIMER5_CC0_PB7 SILABS_DBUS_TIMER5_CC0(0x1, 0x7) +#define TIMER5_CC0_PB8 SILABS_DBUS_TIMER5_CC0(0x1, 0x8) +#define TIMER5_CC0_PB9 SILABS_DBUS_TIMER5_CC0(0x1, 0x9) +#define TIMER5_CC0_PB10 SILABS_DBUS_TIMER5_CC0(0x1, 0xa) +#define TIMER5_CC0_PB11 SILABS_DBUS_TIMER5_CC0(0x1, 0xb) +#define TIMER5_CC0_PB12 SILABS_DBUS_TIMER5_CC0(0x1, 0xc) +#define TIMER5_CC0_PB13 SILABS_DBUS_TIMER5_CC0(0x1, 0xd) +#define TIMER5_CC0_PB14 SILABS_DBUS_TIMER5_CC0(0x1, 0xe) +#define TIMER5_CC0_PB15 SILABS_DBUS_TIMER5_CC0(0x1, 0xf) +#define TIMER5_CC0_PC0 SILABS_DBUS_TIMER5_CC0(0x2, 0x0) +#define TIMER5_CC0_PC1 SILABS_DBUS_TIMER5_CC0(0x2, 0x1) +#define TIMER5_CC0_PC2 SILABS_DBUS_TIMER5_CC0(0x2, 0x2) +#define TIMER5_CC0_PC3 SILABS_DBUS_TIMER5_CC0(0x2, 0x3) +#define TIMER5_CC0_PC4 SILABS_DBUS_TIMER5_CC0(0x2, 0x4) +#define TIMER5_CC0_PC5 SILABS_DBUS_TIMER5_CC0(0x2, 0x5) +#define TIMER5_CC0_PC6 SILABS_DBUS_TIMER5_CC0(0x2, 0x6) +#define TIMER5_CC0_PC7 SILABS_DBUS_TIMER5_CC0(0x2, 0x7) +#define TIMER5_CC0_PC8 SILABS_DBUS_TIMER5_CC0(0x2, 0x8) +#define TIMER5_CC0_PC9 SILABS_DBUS_TIMER5_CC0(0x2, 0x9) +#define TIMER5_CC0_PC10 SILABS_DBUS_TIMER5_CC0(0x2, 0xa) +#define TIMER5_CC0_PC11 SILABS_DBUS_TIMER5_CC0(0x2, 0xb) +#define TIMER5_CC0_PC12 SILABS_DBUS_TIMER5_CC0(0x2, 0xc) +#define TIMER5_CC0_PC13 SILABS_DBUS_TIMER5_CC0(0x2, 0xd) +#define TIMER5_CC0_PC14 SILABS_DBUS_TIMER5_CC0(0x2, 0xe) +#define TIMER5_CC0_PC15 SILABS_DBUS_TIMER5_CC0(0x2, 0xf) +#define TIMER5_CC0_PD0 SILABS_DBUS_TIMER5_CC0(0x3, 0x0) +#define TIMER5_CC0_PD1 SILABS_DBUS_TIMER5_CC0(0x3, 0x1) +#define TIMER5_CC0_PD2 SILABS_DBUS_TIMER5_CC0(0x3, 0x2) +#define TIMER5_CC0_PD3 SILABS_DBUS_TIMER5_CC0(0x3, 0x3) +#define TIMER5_CC0_PD4 SILABS_DBUS_TIMER5_CC0(0x3, 0x4) +#define TIMER5_CC0_PD5 SILABS_DBUS_TIMER5_CC0(0x3, 0x5) +#define TIMER5_CC0_PD6 SILABS_DBUS_TIMER5_CC0(0x3, 0x6) +#define TIMER5_CC0_PD7 SILABS_DBUS_TIMER5_CC0(0x3, 0x7) +#define TIMER5_CC0_PD8 SILABS_DBUS_TIMER5_CC0(0x3, 0x8) +#define TIMER5_CC0_PD9 SILABS_DBUS_TIMER5_CC0(0x3, 0x9) +#define TIMER5_CC0_PD10 SILABS_DBUS_TIMER5_CC0(0x3, 0xa) +#define TIMER5_CC0_PD11 SILABS_DBUS_TIMER5_CC0(0x3, 0xb) +#define TIMER5_CC0_PD12 SILABS_DBUS_TIMER5_CC0(0x3, 0xc) +#define TIMER5_CC0_PD13 SILABS_DBUS_TIMER5_CC0(0x3, 0xd) +#define TIMER5_CC0_PD14 SILABS_DBUS_TIMER5_CC0(0x3, 0xe) +#define TIMER5_CC0_PD15 SILABS_DBUS_TIMER5_CC0(0x3, 0xf) +#define TIMER5_CC1_PA0 SILABS_DBUS_TIMER5_CC1(0x0, 0x0) +#define TIMER5_CC1_PA1 SILABS_DBUS_TIMER5_CC1(0x0, 0x1) +#define TIMER5_CC1_PA2 SILABS_DBUS_TIMER5_CC1(0x0, 0x2) +#define TIMER5_CC1_PA3 SILABS_DBUS_TIMER5_CC1(0x0, 0x3) +#define TIMER5_CC1_PA4 SILABS_DBUS_TIMER5_CC1(0x0, 0x4) +#define TIMER5_CC1_PA5 SILABS_DBUS_TIMER5_CC1(0x0, 0x5) +#define TIMER5_CC1_PA6 SILABS_DBUS_TIMER5_CC1(0x0, 0x6) +#define TIMER5_CC1_PA7 SILABS_DBUS_TIMER5_CC1(0x0, 0x7) +#define TIMER5_CC1_PA8 SILABS_DBUS_TIMER5_CC1(0x0, 0x8) +#define TIMER5_CC1_PA9 SILABS_DBUS_TIMER5_CC1(0x0, 0x9) +#define TIMER5_CC1_PA10 SILABS_DBUS_TIMER5_CC1(0x0, 0xa) +#define TIMER5_CC1_PA11 SILABS_DBUS_TIMER5_CC1(0x0, 0xb) +#define TIMER5_CC1_PA12 SILABS_DBUS_TIMER5_CC1(0x0, 0xc) +#define TIMER5_CC1_PA13 SILABS_DBUS_TIMER5_CC1(0x0, 0xd) +#define TIMER5_CC1_PA14 SILABS_DBUS_TIMER5_CC1(0x0, 0xe) +#define TIMER5_CC1_PA15 SILABS_DBUS_TIMER5_CC1(0x0, 0xf) +#define TIMER5_CC1_PB0 SILABS_DBUS_TIMER5_CC1(0x1, 0x0) +#define TIMER5_CC1_PB1 SILABS_DBUS_TIMER5_CC1(0x1, 0x1) +#define TIMER5_CC1_PB2 SILABS_DBUS_TIMER5_CC1(0x1, 0x2) +#define TIMER5_CC1_PB3 SILABS_DBUS_TIMER5_CC1(0x1, 0x3) +#define TIMER5_CC1_PB4 SILABS_DBUS_TIMER5_CC1(0x1, 0x4) +#define TIMER5_CC1_PB5 SILABS_DBUS_TIMER5_CC1(0x1, 0x5) +#define TIMER5_CC1_PB6 SILABS_DBUS_TIMER5_CC1(0x1, 0x6) +#define TIMER5_CC1_PB7 SILABS_DBUS_TIMER5_CC1(0x1, 0x7) +#define TIMER5_CC1_PB8 SILABS_DBUS_TIMER5_CC1(0x1, 0x8) +#define TIMER5_CC1_PB9 SILABS_DBUS_TIMER5_CC1(0x1, 0x9) +#define TIMER5_CC1_PB10 SILABS_DBUS_TIMER5_CC1(0x1, 0xa) +#define TIMER5_CC1_PB11 SILABS_DBUS_TIMER5_CC1(0x1, 0xb) +#define TIMER5_CC1_PB12 SILABS_DBUS_TIMER5_CC1(0x1, 0xc) +#define TIMER5_CC1_PB13 SILABS_DBUS_TIMER5_CC1(0x1, 0xd) +#define TIMER5_CC1_PB14 SILABS_DBUS_TIMER5_CC1(0x1, 0xe) +#define TIMER5_CC1_PB15 SILABS_DBUS_TIMER5_CC1(0x1, 0xf) +#define TIMER5_CC1_PC0 SILABS_DBUS_TIMER5_CC1(0x2, 0x0) +#define TIMER5_CC1_PC1 SILABS_DBUS_TIMER5_CC1(0x2, 0x1) +#define TIMER5_CC1_PC2 SILABS_DBUS_TIMER5_CC1(0x2, 0x2) +#define TIMER5_CC1_PC3 SILABS_DBUS_TIMER5_CC1(0x2, 0x3) +#define TIMER5_CC1_PC4 SILABS_DBUS_TIMER5_CC1(0x2, 0x4) +#define TIMER5_CC1_PC5 SILABS_DBUS_TIMER5_CC1(0x2, 0x5) +#define TIMER5_CC1_PC6 SILABS_DBUS_TIMER5_CC1(0x2, 0x6) +#define TIMER5_CC1_PC7 SILABS_DBUS_TIMER5_CC1(0x2, 0x7) +#define TIMER5_CC1_PC8 SILABS_DBUS_TIMER5_CC1(0x2, 0x8) +#define TIMER5_CC1_PC9 SILABS_DBUS_TIMER5_CC1(0x2, 0x9) +#define TIMER5_CC1_PC10 SILABS_DBUS_TIMER5_CC1(0x2, 0xa) +#define TIMER5_CC1_PC11 SILABS_DBUS_TIMER5_CC1(0x2, 0xb) +#define TIMER5_CC1_PC12 SILABS_DBUS_TIMER5_CC1(0x2, 0xc) +#define TIMER5_CC1_PC13 SILABS_DBUS_TIMER5_CC1(0x2, 0xd) +#define TIMER5_CC1_PC14 SILABS_DBUS_TIMER5_CC1(0x2, 0xe) +#define TIMER5_CC1_PC15 SILABS_DBUS_TIMER5_CC1(0x2, 0xf) +#define TIMER5_CC1_PD0 SILABS_DBUS_TIMER5_CC1(0x3, 0x0) +#define TIMER5_CC1_PD1 SILABS_DBUS_TIMER5_CC1(0x3, 0x1) +#define TIMER5_CC1_PD2 SILABS_DBUS_TIMER5_CC1(0x3, 0x2) +#define TIMER5_CC1_PD3 SILABS_DBUS_TIMER5_CC1(0x3, 0x3) +#define TIMER5_CC1_PD4 SILABS_DBUS_TIMER5_CC1(0x3, 0x4) +#define TIMER5_CC1_PD5 SILABS_DBUS_TIMER5_CC1(0x3, 0x5) +#define TIMER5_CC1_PD6 SILABS_DBUS_TIMER5_CC1(0x3, 0x6) +#define TIMER5_CC1_PD7 SILABS_DBUS_TIMER5_CC1(0x3, 0x7) +#define TIMER5_CC1_PD8 SILABS_DBUS_TIMER5_CC1(0x3, 0x8) +#define TIMER5_CC1_PD9 SILABS_DBUS_TIMER5_CC1(0x3, 0x9) +#define TIMER5_CC1_PD10 SILABS_DBUS_TIMER5_CC1(0x3, 0xa) +#define TIMER5_CC1_PD11 SILABS_DBUS_TIMER5_CC1(0x3, 0xb) +#define TIMER5_CC1_PD12 SILABS_DBUS_TIMER5_CC1(0x3, 0xc) +#define TIMER5_CC1_PD13 SILABS_DBUS_TIMER5_CC1(0x3, 0xd) +#define TIMER5_CC1_PD14 SILABS_DBUS_TIMER5_CC1(0x3, 0xe) +#define TIMER5_CC1_PD15 SILABS_DBUS_TIMER5_CC1(0x3, 0xf) +#define TIMER5_CC2_PA0 SILABS_DBUS_TIMER5_CC2(0x0, 0x0) +#define TIMER5_CC2_PA1 SILABS_DBUS_TIMER5_CC2(0x0, 0x1) +#define TIMER5_CC2_PA2 SILABS_DBUS_TIMER5_CC2(0x0, 0x2) +#define TIMER5_CC2_PA3 SILABS_DBUS_TIMER5_CC2(0x0, 0x3) +#define TIMER5_CC2_PA4 SILABS_DBUS_TIMER5_CC2(0x0, 0x4) +#define TIMER5_CC2_PA5 SILABS_DBUS_TIMER5_CC2(0x0, 0x5) +#define TIMER5_CC2_PA6 SILABS_DBUS_TIMER5_CC2(0x0, 0x6) +#define TIMER5_CC2_PA7 SILABS_DBUS_TIMER5_CC2(0x0, 0x7) +#define TIMER5_CC2_PA8 SILABS_DBUS_TIMER5_CC2(0x0, 0x8) +#define TIMER5_CC2_PA9 SILABS_DBUS_TIMER5_CC2(0x0, 0x9) +#define TIMER5_CC2_PA10 SILABS_DBUS_TIMER5_CC2(0x0, 0xa) +#define TIMER5_CC2_PA11 SILABS_DBUS_TIMER5_CC2(0x0, 0xb) +#define TIMER5_CC2_PA12 SILABS_DBUS_TIMER5_CC2(0x0, 0xc) +#define TIMER5_CC2_PA13 SILABS_DBUS_TIMER5_CC2(0x0, 0xd) +#define TIMER5_CC2_PA14 SILABS_DBUS_TIMER5_CC2(0x0, 0xe) +#define TIMER5_CC2_PA15 SILABS_DBUS_TIMER5_CC2(0x0, 0xf) +#define TIMER5_CC2_PB0 SILABS_DBUS_TIMER5_CC2(0x1, 0x0) +#define TIMER5_CC2_PB1 SILABS_DBUS_TIMER5_CC2(0x1, 0x1) +#define TIMER5_CC2_PB2 SILABS_DBUS_TIMER5_CC2(0x1, 0x2) +#define TIMER5_CC2_PB3 SILABS_DBUS_TIMER5_CC2(0x1, 0x3) +#define TIMER5_CC2_PB4 SILABS_DBUS_TIMER5_CC2(0x1, 0x4) +#define TIMER5_CC2_PB5 SILABS_DBUS_TIMER5_CC2(0x1, 0x5) +#define TIMER5_CC2_PB6 SILABS_DBUS_TIMER5_CC2(0x1, 0x6) +#define TIMER5_CC2_PB7 SILABS_DBUS_TIMER5_CC2(0x1, 0x7) +#define TIMER5_CC2_PB8 SILABS_DBUS_TIMER5_CC2(0x1, 0x8) +#define TIMER5_CC2_PB9 SILABS_DBUS_TIMER5_CC2(0x1, 0x9) +#define TIMER5_CC2_PB10 SILABS_DBUS_TIMER5_CC2(0x1, 0xa) +#define TIMER5_CC2_PB11 SILABS_DBUS_TIMER5_CC2(0x1, 0xb) +#define TIMER5_CC2_PB12 SILABS_DBUS_TIMER5_CC2(0x1, 0xc) +#define TIMER5_CC2_PB13 SILABS_DBUS_TIMER5_CC2(0x1, 0xd) +#define TIMER5_CC2_PB14 SILABS_DBUS_TIMER5_CC2(0x1, 0xe) +#define TIMER5_CC2_PB15 SILABS_DBUS_TIMER5_CC2(0x1, 0xf) +#define TIMER5_CC2_PC0 SILABS_DBUS_TIMER5_CC2(0x2, 0x0) +#define TIMER5_CC2_PC1 SILABS_DBUS_TIMER5_CC2(0x2, 0x1) +#define TIMER5_CC2_PC2 SILABS_DBUS_TIMER5_CC2(0x2, 0x2) +#define TIMER5_CC2_PC3 SILABS_DBUS_TIMER5_CC2(0x2, 0x3) +#define TIMER5_CC2_PC4 SILABS_DBUS_TIMER5_CC2(0x2, 0x4) +#define TIMER5_CC2_PC5 SILABS_DBUS_TIMER5_CC2(0x2, 0x5) +#define TIMER5_CC2_PC6 SILABS_DBUS_TIMER5_CC2(0x2, 0x6) +#define TIMER5_CC2_PC7 SILABS_DBUS_TIMER5_CC2(0x2, 0x7) +#define TIMER5_CC2_PC8 SILABS_DBUS_TIMER5_CC2(0x2, 0x8) +#define TIMER5_CC2_PC9 SILABS_DBUS_TIMER5_CC2(0x2, 0x9) +#define TIMER5_CC2_PC10 SILABS_DBUS_TIMER5_CC2(0x2, 0xa) +#define TIMER5_CC2_PC11 SILABS_DBUS_TIMER5_CC2(0x2, 0xb) +#define TIMER5_CC2_PC12 SILABS_DBUS_TIMER5_CC2(0x2, 0xc) +#define TIMER5_CC2_PC13 SILABS_DBUS_TIMER5_CC2(0x2, 0xd) +#define TIMER5_CC2_PC14 SILABS_DBUS_TIMER5_CC2(0x2, 0xe) +#define TIMER5_CC2_PC15 SILABS_DBUS_TIMER5_CC2(0x2, 0xf) +#define TIMER5_CC2_PD0 SILABS_DBUS_TIMER5_CC2(0x3, 0x0) +#define TIMER5_CC2_PD1 SILABS_DBUS_TIMER5_CC2(0x3, 0x1) +#define TIMER5_CC2_PD2 SILABS_DBUS_TIMER5_CC2(0x3, 0x2) +#define TIMER5_CC2_PD3 SILABS_DBUS_TIMER5_CC2(0x3, 0x3) +#define TIMER5_CC2_PD4 SILABS_DBUS_TIMER5_CC2(0x3, 0x4) +#define TIMER5_CC2_PD5 SILABS_DBUS_TIMER5_CC2(0x3, 0x5) +#define TIMER5_CC2_PD6 SILABS_DBUS_TIMER5_CC2(0x3, 0x6) +#define TIMER5_CC2_PD7 SILABS_DBUS_TIMER5_CC2(0x3, 0x7) +#define TIMER5_CC2_PD8 SILABS_DBUS_TIMER5_CC2(0x3, 0x8) +#define TIMER5_CC2_PD9 SILABS_DBUS_TIMER5_CC2(0x3, 0x9) +#define TIMER5_CC2_PD10 SILABS_DBUS_TIMER5_CC2(0x3, 0xa) +#define TIMER5_CC2_PD11 SILABS_DBUS_TIMER5_CC2(0x3, 0xb) +#define TIMER5_CC2_PD12 SILABS_DBUS_TIMER5_CC2(0x3, 0xc) +#define TIMER5_CC2_PD13 SILABS_DBUS_TIMER5_CC2(0x3, 0xd) +#define TIMER5_CC2_PD14 SILABS_DBUS_TIMER5_CC2(0x3, 0xe) +#define TIMER5_CC2_PD15 SILABS_DBUS_TIMER5_CC2(0x3, 0xf) +#define TIMER5_CDTI0_PA0 SILABS_DBUS_TIMER5_CDTI0(0x0, 0x0) +#define TIMER5_CDTI0_PA1 SILABS_DBUS_TIMER5_CDTI0(0x0, 0x1) +#define TIMER5_CDTI0_PA2 SILABS_DBUS_TIMER5_CDTI0(0x0, 0x2) +#define TIMER5_CDTI0_PA3 SILABS_DBUS_TIMER5_CDTI0(0x0, 0x3) +#define TIMER5_CDTI0_PA4 SILABS_DBUS_TIMER5_CDTI0(0x0, 0x4) +#define TIMER5_CDTI0_PA5 SILABS_DBUS_TIMER5_CDTI0(0x0, 0x5) +#define TIMER5_CDTI0_PA6 SILABS_DBUS_TIMER5_CDTI0(0x0, 0x6) +#define TIMER5_CDTI0_PA7 SILABS_DBUS_TIMER5_CDTI0(0x0, 0x7) +#define TIMER5_CDTI0_PA8 SILABS_DBUS_TIMER5_CDTI0(0x0, 0x8) +#define TIMER5_CDTI0_PA9 SILABS_DBUS_TIMER5_CDTI0(0x0, 0x9) +#define TIMER5_CDTI0_PA10 SILABS_DBUS_TIMER5_CDTI0(0x0, 0xa) +#define TIMER5_CDTI0_PA11 SILABS_DBUS_TIMER5_CDTI0(0x0, 0xb) +#define TIMER5_CDTI0_PA12 SILABS_DBUS_TIMER5_CDTI0(0x0, 0xc) +#define TIMER5_CDTI0_PA13 SILABS_DBUS_TIMER5_CDTI0(0x0, 0xd) +#define TIMER5_CDTI0_PA14 SILABS_DBUS_TIMER5_CDTI0(0x0, 0xe) +#define TIMER5_CDTI0_PA15 SILABS_DBUS_TIMER5_CDTI0(0x0, 0xf) +#define TIMER5_CDTI0_PB0 SILABS_DBUS_TIMER5_CDTI0(0x1, 0x0) +#define TIMER5_CDTI0_PB1 SILABS_DBUS_TIMER5_CDTI0(0x1, 0x1) +#define TIMER5_CDTI0_PB2 SILABS_DBUS_TIMER5_CDTI0(0x1, 0x2) +#define TIMER5_CDTI0_PB3 SILABS_DBUS_TIMER5_CDTI0(0x1, 0x3) +#define TIMER5_CDTI0_PB4 SILABS_DBUS_TIMER5_CDTI0(0x1, 0x4) +#define TIMER5_CDTI0_PB5 SILABS_DBUS_TIMER5_CDTI0(0x1, 0x5) +#define TIMER5_CDTI0_PB6 SILABS_DBUS_TIMER5_CDTI0(0x1, 0x6) +#define TIMER5_CDTI0_PB7 SILABS_DBUS_TIMER5_CDTI0(0x1, 0x7) +#define TIMER5_CDTI0_PB8 SILABS_DBUS_TIMER5_CDTI0(0x1, 0x8) +#define TIMER5_CDTI0_PB9 SILABS_DBUS_TIMER5_CDTI0(0x1, 0x9) +#define TIMER5_CDTI0_PB10 SILABS_DBUS_TIMER5_CDTI0(0x1, 0xa) +#define TIMER5_CDTI0_PB11 SILABS_DBUS_TIMER5_CDTI0(0x1, 0xb) +#define TIMER5_CDTI0_PB12 SILABS_DBUS_TIMER5_CDTI0(0x1, 0xc) +#define TIMER5_CDTI0_PB13 SILABS_DBUS_TIMER5_CDTI0(0x1, 0xd) +#define TIMER5_CDTI0_PB14 SILABS_DBUS_TIMER5_CDTI0(0x1, 0xe) +#define TIMER5_CDTI0_PB15 SILABS_DBUS_TIMER5_CDTI0(0x1, 0xf) +#define TIMER5_CDTI0_PC0 SILABS_DBUS_TIMER5_CDTI0(0x2, 0x0) +#define TIMER5_CDTI0_PC1 SILABS_DBUS_TIMER5_CDTI0(0x2, 0x1) +#define TIMER5_CDTI0_PC2 SILABS_DBUS_TIMER5_CDTI0(0x2, 0x2) +#define TIMER5_CDTI0_PC3 SILABS_DBUS_TIMER5_CDTI0(0x2, 0x3) +#define TIMER5_CDTI0_PC4 SILABS_DBUS_TIMER5_CDTI0(0x2, 0x4) +#define TIMER5_CDTI0_PC5 SILABS_DBUS_TIMER5_CDTI0(0x2, 0x5) +#define TIMER5_CDTI0_PC6 SILABS_DBUS_TIMER5_CDTI0(0x2, 0x6) +#define TIMER5_CDTI0_PC7 SILABS_DBUS_TIMER5_CDTI0(0x2, 0x7) +#define TIMER5_CDTI0_PC8 SILABS_DBUS_TIMER5_CDTI0(0x2, 0x8) +#define TIMER5_CDTI0_PC9 SILABS_DBUS_TIMER5_CDTI0(0x2, 0x9) +#define TIMER5_CDTI0_PC10 SILABS_DBUS_TIMER5_CDTI0(0x2, 0xa) +#define TIMER5_CDTI0_PC11 SILABS_DBUS_TIMER5_CDTI0(0x2, 0xb) +#define TIMER5_CDTI0_PC12 SILABS_DBUS_TIMER5_CDTI0(0x2, 0xc) +#define TIMER5_CDTI0_PC13 SILABS_DBUS_TIMER5_CDTI0(0x2, 0xd) +#define TIMER5_CDTI0_PC14 SILABS_DBUS_TIMER5_CDTI0(0x2, 0xe) +#define TIMER5_CDTI0_PC15 SILABS_DBUS_TIMER5_CDTI0(0x2, 0xf) +#define TIMER5_CDTI0_PD0 SILABS_DBUS_TIMER5_CDTI0(0x3, 0x0) +#define TIMER5_CDTI0_PD1 SILABS_DBUS_TIMER5_CDTI0(0x3, 0x1) +#define TIMER5_CDTI0_PD2 SILABS_DBUS_TIMER5_CDTI0(0x3, 0x2) +#define TIMER5_CDTI0_PD3 SILABS_DBUS_TIMER5_CDTI0(0x3, 0x3) +#define TIMER5_CDTI0_PD4 SILABS_DBUS_TIMER5_CDTI0(0x3, 0x4) +#define TIMER5_CDTI0_PD5 SILABS_DBUS_TIMER5_CDTI0(0x3, 0x5) +#define TIMER5_CDTI0_PD6 SILABS_DBUS_TIMER5_CDTI0(0x3, 0x6) +#define TIMER5_CDTI0_PD7 SILABS_DBUS_TIMER5_CDTI0(0x3, 0x7) +#define TIMER5_CDTI0_PD8 SILABS_DBUS_TIMER5_CDTI0(0x3, 0x8) +#define TIMER5_CDTI0_PD9 SILABS_DBUS_TIMER5_CDTI0(0x3, 0x9) +#define TIMER5_CDTI0_PD10 SILABS_DBUS_TIMER5_CDTI0(0x3, 0xa) +#define TIMER5_CDTI0_PD11 SILABS_DBUS_TIMER5_CDTI0(0x3, 0xb) +#define TIMER5_CDTI0_PD12 SILABS_DBUS_TIMER5_CDTI0(0x3, 0xc) +#define TIMER5_CDTI0_PD13 SILABS_DBUS_TIMER5_CDTI0(0x3, 0xd) +#define TIMER5_CDTI0_PD14 SILABS_DBUS_TIMER5_CDTI0(0x3, 0xe) +#define TIMER5_CDTI0_PD15 SILABS_DBUS_TIMER5_CDTI0(0x3, 0xf) +#define TIMER5_CDTI1_PA0 SILABS_DBUS_TIMER5_CDTI1(0x0, 0x0) +#define TIMER5_CDTI1_PA1 SILABS_DBUS_TIMER5_CDTI1(0x0, 0x1) +#define TIMER5_CDTI1_PA2 SILABS_DBUS_TIMER5_CDTI1(0x0, 0x2) +#define TIMER5_CDTI1_PA3 SILABS_DBUS_TIMER5_CDTI1(0x0, 0x3) +#define TIMER5_CDTI1_PA4 SILABS_DBUS_TIMER5_CDTI1(0x0, 0x4) +#define TIMER5_CDTI1_PA5 SILABS_DBUS_TIMER5_CDTI1(0x0, 0x5) +#define TIMER5_CDTI1_PA6 SILABS_DBUS_TIMER5_CDTI1(0x0, 0x6) +#define TIMER5_CDTI1_PA7 SILABS_DBUS_TIMER5_CDTI1(0x0, 0x7) +#define TIMER5_CDTI1_PA8 SILABS_DBUS_TIMER5_CDTI1(0x0, 0x8) +#define TIMER5_CDTI1_PA9 SILABS_DBUS_TIMER5_CDTI1(0x0, 0x9) +#define TIMER5_CDTI1_PA10 SILABS_DBUS_TIMER5_CDTI1(0x0, 0xa) +#define TIMER5_CDTI1_PA11 SILABS_DBUS_TIMER5_CDTI1(0x0, 0xb) +#define TIMER5_CDTI1_PA12 SILABS_DBUS_TIMER5_CDTI1(0x0, 0xc) +#define TIMER5_CDTI1_PA13 SILABS_DBUS_TIMER5_CDTI1(0x0, 0xd) +#define TIMER5_CDTI1_PA14 SILABS_DBUS_TIMER5_CDTI1(0x0, 0xe) +#define TIMER5_CDTI1_PA15 SILABS_DBUS_TIMER5_CDTI1(0x0, 0xf) +#define TIMER5_CDTI1_PB0 SILABS_DBUS_TIMER5_CDTI1(0x1, 0x0) +#define TIMER5_CDTI1_PB1 SILABS_DBUS_TIMER5_CDTI1(0x1, 0x1) +#define TIMER5_CDTI1_PB2 SILABS_DBUS_TIMER5_CDTI1(0x1, 0x2) +#define TIMER5_CDTI1_PB3 SILABS_DBUS_TIMER5_CDTI1(0x1, 0x3) +#define TIMER5_CDTI1_PB4 SILABS_DBUS_TIMER5_CDTI1(0x1, 0x4) +#define TIMER5_CDTI1_PB5 SILABS_DBUS_TIMER5_CDTI1(0x1, 0x5) +#define TIMER5_CDTI1_PB6 SILABS_DBUS_TIMER5_CDTI1(0x1, 0x6) +#define TIMER5_CDTI1_PB7 SILABS_DBUS_TIMER5_CDTI1(0x1, 0x7) +#define TIMER5_CDTI1_PB8 SILABS_DBUS_TIMER5_CDTI1(0x1, 0x8) +#define TIMER5_CDTI1_PB9 SILABS_DBUS_TIMER5_CDTI1(0x1, 0x9) +#define TIMER5_CDTI1_PB10 SILABS_DBUS_TIMER5_CDTI1(0x1, 0xa) +#define TIMER5_CDTI1_PB11 SILABS_DBUS_TIMER5_CDTI1(0x1, 0xb) +#define TIMER5_CDTI1_PB12 SILABS_DBUS_TIMER5_CDTI1(0x1, 0xc) +#define TIMER5_CDTI1_PB13 SILABS_DBUS_TIMER5_CDTI1(0x1, 0xd) +#define TIMER5_CDTI1_PB14 SILABS_DBUS_TIMER5_CDTI1(0x1, 0xe) +#define TIMER5_CDTI1_PB15 SILABS_DBUS_TIMER5_CDTI1(0x1, 0xf) +#define TIMER5_CDTI1_PC0 SILABS_DBUS_TIMER5_CDTI1(0x2, 0x0) +#define TIMER5_CDTI1_PC1 SILABS_DBUS_TIMER5_CDTI1(0x2, 0x1) +#define TIMER5_CDTI1_PC2 SILABS_DBUS_TIMER5_CDTI1(0x2, 0x2) +#define TIMER5_CDTI1_PC3 SILABS_DBUS_TIMER5_CDTI1(0x2, 0x3) +#define TIMER5_CDTI1_PC4 SILABS_DBUS_TIMER5_CDTI1(0x2, 0x4) +#define TIMER5_CDTI1_PC5 SILABS_DBUS_TIMER5_CDTI1(0x2, 0x5) +#define TIMER5_CDTI1_PC6 SILABS_DBUS_TIMER5_CDTI1(0x2, 0x6) +#define TIMER5_CDTI1_PC7 SILABS_DBUS_TIMER5_CDTI1(0x2, 0x7) +#define TIMER5_CDTI1_PC8 SILABS_DBUS_TIMER5_CDTI1(0x2, 0x8) +#define TIMER5_CDTI1_PC9 SILABS_DBUS_TIMER5_CDTI1(0x2, 0x9) +#define TIMER5_CDTI1_PC10 SILABS_DBUS_TIMER5_CDTI1(0x2, 0xa) +#define TIMER5_CDTI1_PC11 SILABS_DBUS_TIMER5_CDTI1(0x2, 0xb) +#define TIMER5_CDTI1_PC12 SILABS_DBUS_TIMER5_CDTI1(0x2, 0xc) +#define TIMER5_CDTI1_PC13 SILABS_DBUS_TIMER5_CDTI1(0x2, 0xd) +#define TIMER5_CDTI1_PC14 SILABS_DBUS_TIMER5_CDTI1(0x2, 0xe) +#define TIMER5_CDTI1_PC15 SILABS_DBUS_TIMER5_CDTI1(0x2, 0xf) +#define TIMER5_CDTI1_PD0 SILABS_DBUS_TIMER5_CDTI1(0x3, 0x0) +#define TIMER5_CDTI1_PD1 SILABS_DBUS_TIMER5_CDTI1(0x3, 0x1) +#define TIMER5_CDTI1_PD2 SILABS_DBUS_TIMER5_CDTI1(0x3, 0x2) +#define TIMER5_CDTI1_PD3 SILABS_DBUS_TIMER5_CDTI1(0x3, 0x3) +#define TIMER5_CDTI1_PD4 SILABS_DBUS_TIMER5_CDTI1(0x3, 0x4) +#define TIMER5_CDTI1_PD5 SILABS_DBUS_TIMER5_CDTI1(0x3, 0x5) +#define TIMER5_CDTI1_PD6 SILABS_DBUS_TIMER5_CDTI1(0x3, 0x6) +#define TIMER5_CDTI1_PD7 SILABS_DBUS_TIMER5_CDTI1(0x3, 0x7) +#define TIMER5_CDTI1_PD8 SILABS_DBUS_TIMER5_CDTI1(0x3, 0x8) +#define TIMER5_CDTI1_PD9 SILABS_DBUS_TIMER5_CDTI1(0x3, 0x9) +#define TIMER5_CDTI1_PD10 SILABS_DBUS_TIMER5_CDTI1(0x3, 0xa) +#define TIMER5_CDTI1_PD11 SILABS_DBUS_TIMER5_CDTI1(0x3, 0xb) +#define TIMER5_CDTI1_PD12 SILABS_DBUS_TIMER5_CDTI1(0x3, 0xc) +#define TIMER5_CDTI1_PD13 SILABS_DBUS_TIMER5_CDTI1(0x3, 0xd) +#define TIMER5_CDTI1_PD14 SILABS_DBUS_TIMER5_CDTI1(0x3, 0xe) +#define TIMER5_CDTI1_PD15 SILABS_DBUS_TIMER5_CDTI1(0x3, 0xf) +#define TIMER5_CDTI2_PA0 SILABS_DBUS_TIMER5_CDTI2(0x0, 0x0) +#define TIMER5_CDTI2_PA1 SILABS_DBUS_TIMER5_CDTI2(0x0, 0x1) +#define TIMER5_CDTI2_PA2 SILABS_DBUS_TIMER5_CDTI2(0x0, 0x2) +#define TIMER5_CDTI2_PA3 SILABS_DBUS_TIMER5_CDTI2(0x0, 0x3) +#define TIMER5_CDTI2_PA4 SILABS_DBUS_TIMER5_CDTI2(0x0, 0x4) +#define TIMER5_CDTI2_PA5 SILABS_DBUS_TIMER5_CDTI2(0x0, 0x5) +#define TIMER5_CDTI2_PA6 SILABS_DBUS_TIMER5_CDTI2(0x0, 0x6) +#define TIMER5_CDTI2_PA7 SILABS_DBUS_TIMER5_CDTI2(0x0, 0x7) +#define TIMER5_CDTI2_PA8 SILABS_DBUS_TIMER5_CDTI2(0x0, 0x8) +#define TIMER5_CDTI2_PA9 SILABS_DBUS_TIMER5_CDTI2(0x0, 0x9) +#define TIMER5_CDTI2_PA10 SILABS_DBUS_TIMER5_CDTI2(0x0, 0xa) +#define TIMER5_CDTI2_PA11 SILABS_DBUS_TIMER5_CDTI2(0x0, 0xb) +#define TIMER5_CDTI2_PA12 SILABS_DBUS_TIMER5_CDTI2(0x0, 0xc) +#define TIMER5_CDTI2_PA13 SILABS_DBUS_TIMER5_CDTI2(0x0, 0xd) +#define TIMER5_CDTI2_PA14 SILABS_DBUS_TIMER5_CDTI2(0x0, 0xe) +#define TIMER5_CDTI2_PA15 SILABS_DBUS_TIMER5_CDTI2(0x0, 0xf) +#define TIMER5_CDTI2_PB0 SILABS_DBUS_TIMER5_CDTI2(0x1, 0x0) +#define TIMER5_CDTI2_PB1 SILABS_DBUS_TIMER5_CDTI2(0x1, 0x1) +#define TIMER5_CDTI2_PB2 SILABS_DBUS_TIMER5_CDTI2(0x1, 0x2) +#define TIMER5_CDTI2_PB3 SILABS_DBUS_TIMER5_CDTI2(0x1, 0x3) +#define TIMER5_CDTI2_PB4 SILABS_DBUS_TIMER5_CDTI2(0x1, 0x4) +#define TIMER5_CDTI2_PB5 SILABS_DBUS_TIMER5_CDTI2(0x1, 0x5) +#define TIMER5_CDTI2_PB6 SILABS_DBUS_TIMER5_CDTI2(0x1, 0x6) +#define TIMER5_CDTI2_PB7 SILABS_DBUS_TIMER5_CDTI2(0x1, 0x7) +#define TIMER5_CDTI2_PB8 SILABS_DBUS_TIMER5_CDTI2(0x1, 0x8) +#define TIMER5_CDTI2_PB9 SILABS_DBUS_TIMER5_CDTI2(0x1, 0x9) +#define TIMER5_CDTI2_PB10 SILABS_DBUS_TIMER5_CDTI2(0x1, 0xa) +#define TIMER5_CDTI2_PB11 SILABS_DBUS_TIMER5_CDTI2(0x1, 0xb) +#define TIMER5_CDTI2_PB12 SILABS_DBUS_TIMER5_CDTI2(0x1, 0xc) +#define TIMER5_CDTI2_PB13 SILABS_DBUS_TIMER5_CDTI2(0x1, 0xd) +#define TIMER5_CDTI2_PB14 SILABS_DBUS_TIMER5_CDTI2(0x1, 0xe) +#define TIMER5_CDTI2_PB15 SILABS_DBUS_TIMER5_CDTI2(0x1, 0xf) +#define TIMER5_CDTI2_PC0 SILABS_DBUS_TIMER5_CDTI2(0x2, 0x0) +#define TIMER5_CDTI2_PC1 SILABS_DBUS_TIMER5_CDTI2(0x2, 0x1) +#define TIMER5_CDTI2_PC2 SILABS_DBUS_TIMER5_CDTI2(0x2, 0x2) +#define TIMER5_CDTI2_PC3 SILABS_DBUS_TIMER5_CDTI2(0x2, 0x3) +#define TIMER5_CDTI2_PC4 SILABS_DBUS_TIMER5_CDTI2(0x2, 0x4) +#define TIMER5_CDTI2_PC5 SILABS_DBUS_TIMER5_CDTI2(0x2, 0x5) +#define TIMER5_CDTI2_PC6 SILABS_DBUS_TIMER5_CDTI2(0x2, 0x6) +#define TIMER5_CDTI2_PC7 SILABS_DBUS_TIMER5_CDTI2(0x2, 0x7) +#define TIMER5_CDTI2_PC8 SILABS_DBUS_TIMER5_CDTI2(0x2, 0x8) +#define TIMER5_CDTI2_PC9 SILABS_DBUS_TIMER5_CDTI2(0x2, 0x9) +#define TIMER5_CDTI2_PC10 SILABS_DBUS_TIMER5_CDTI2(0x2, 0xa) +#define TIMER5_CDTI2_PC11 SILABS_DBUS_TIMER5_CDTI2(0x2, 0xb) +#define TIMER5_CDTI2_PC12 SILABS_DBUS_TIMER5_CDTI2(0x2, 0xc) +#define TIMER5_CDTI2_PC13 SILABS_DBUS_TIMER5_CDTI2(0x2, 0xd) +#define TIMER5_CDTI2_PC14 SILABS_DBUS_TIMER5_CDTI2(0x2, 0xe) +#define TIMER5_CDTI2_PC15 SILABS_DBUS_TIMER5_CDTI2(0x2, 0xf) +#define TIMER5_CDTI2_PD0 SILABS_DBUS_TIMER5_CDTI2(0x3, 0x0) +#define TIMER5_CDTI2_PD1 SILABS_DBUS_TIMER5_CDTI2(0x3, 0x1) +#define TIMER5_CDTI2_PD2 SILABS_DBUS_TIMER5_CDTI2(0x3, 0x2) +#define TIMER5_CDTI2_PD3 SILABS_DBUS_TIMER5_CDTI2(0x3, 0x3) +#define TIMER5_CDTI2_PD4 SILABS_DBUS_TIMER5_CDTI2(0x3, 0x4) +#define TIMER5_CDTI2_PD5 SILABS_DBUS_TIMER5_CDTI2(0x3, 0x5) +#define TIMER5_CDTI2_PD6 SILABS_DBUS_TIMER5_CDTI2(0x3, 0x6) +#define TIMER5_CDTI2_PD7 SILABS_DBUS_TIMER5_CDTI2(0x3, 0x7) +#define TIMER5_CDTI2_PD8 SILABS_DBUS_TIMER5_CDTI2(0x3, 0x8) +#define TIMER5_CDTI2_PD9 SILABS_DBUS_TIMER5_CDTI2(0x3, 0x9) +#define TIMER5_CDTI2_PD10 SILABS_DBUS_TIMER5_CDTI2(0x3, 0xa) +#define TIMER5_CDTI2_PD11 SILABS_DBUS_TIMER5_CDTI2(0x3, 0xb) +#define TIMER5_CDTI2_PD12 SILABS_DBUS_TIMER5_CDTI2(0x3, 0xc) +#define TIMER5_CDTI2_PD13 SILABS_DBUS_TIMER5_CDTI2(0x3, 0xd) +#define TIMER5_CDTI2_PD14 SILABS_DBUS_TIMER5_CDTI2(0x3, 0xe) +#define TIMER5_CDTI2_PD15 SILABS_DBUS_TIMER5_CDTI2(0x3, 0xf) + +#define TIMER6_CC0_PA0 SILABS_DBUS_TIMER6_CC0(0x0, 0x0) +#define TIMER6_CC0_PA1 SILABS_DBUS_TIMER6_CC0(0x0, 0x1) +#define TIMER6_CC0_PA2 SILABS_DBUS_TIMER6_CC0(0x0, 0x2) +#define TIMER6_CC0_PA3 SILABS_DBUS_TIMER6_CC0(0x0, 0x3) +#define TIMER6_CC0_PA4 SILABS_DBUS_TIMER6_CC0(0x0, 0x4) +#define TIMER6_CC0_PA5 SILABS_DBUS_TIMER6_CC0(0x0, 0x5) +#define TIMER6_CC0_PA6 SILABS_DBUS_TIMER6_CC0(0x0, 0x6) +#define TIMER6_CC0_PA7 SILABS_DBUS_TIMER6_CC0(0x0, 0x7) +#define TIMER6_CC0_PA8 SILABS_DBUS_TIMER6_CC0(0x0, 0x8) +#define TIMER6_CC0_PA9 SILABS_DBUS_TIMER6_CC0(0x0, 0x9) +#define TIMER6_CC0_PA10 SILABS_DBUS_TIMER6_CC0(0x0, 0xa) +#define TIMER6_CC0_PA11 SILABS_DBUS_TIMER6_CC0(0x0, 0xb) +#define TIMER6_CC0_PA12 SILABS_DBUS_TIMER6_CC0(0x0, 0xc) +#define TIMER6_CC0_PA13 SILABS_DBUS_TIMER6_CC0(0x0, 0xd) +#define TIMER6_CC0_PA14 SILABS_DBUS_TIMER6_CC0(0x0, 0xe) +#define TIMER6_CC0_PA15 SILABS_DBUS_TIMER6_CC0(0x0, 0xf) +#define TIMER6_CC0_PB0 SILABS_DBUS_TIMER6_CC0(0x1, 0x0) +#define TIMER6_CC0_PB1 SILABS_DBUS_TIMER6_CC0(0x1, 0x1) +#define TIMER6_CC0_PB2 SILABS_DBUS_TIMER6_CC0(0x1, 0x2) +#define TIMER6_CC0_PB3 SILABS_DBUS_TIMER6_CC0(0x1, 0x3) +#define TIMER6_CC0_PB4 SILABS_DBUS_TIMER6_CC0(0x1, 0x4) +#define TIMER6_CC0_PB5 SILABS_DBUS_TIMER6_CC0(0x1, 0x5) +#define TIMER6_CC0_PB6 SILABS_DBUS_TIMER6_CC0(0x1, 0x6) +#define TIMER6_CC0_PB7 SILABS_DBUS_TIMER6_CC0(0x1, 0x7) +#define TIMER6_CC0_PB8 SILABS_DBUS_TIMER6_CC0(0x1, 0x8) +#define TIMER6_CC0_PB9 SILABS_DBUS_TIMER6_CC0(0x1, 0x9) +#define TIMER6_CC0_PB10 SILABS_DBUS_TIMER6_CC0(0x1, 0xa) +#define TIMER6_CC0_PB11 SILABS_DBUS_TIMER6_CC0(0x1, 0xb) +#define TIMER6_CC0_PB12 SILABS_DBUS_TIMER6_CC0(0x1, 0xc) +#define TIMER6_CC0_PB13 SILABS_DBUS_TIMER6_CC0(0x1, 0xd) +#define TIMER6_CC0_PB14 SILABS_DBUS_TIMER6_CC0(0x1, 0xe) +#define TIMER6_CC0_PB15 SILABS_DBUS_TIMER6_CC0(0x1, 0xf) +#define TIMER6_CC0_PC0 SILABS_DBUS_TIMER6_CC0(0x2, 0x0) +#define TIMER6_CC0_PC1 SILABS_DBUS_TIMER6_CC0(0x2, 0x1) +#define TIMER6_CC0_PC2 SILABS_DBUS_TIMER6_CC0(0x2, 0x2) +#define TIMER6_CC0_PC3 SILABS_DBUS_TIMER6_CC0(0x2, 0x3) +#define TIMER6_CC0_PC4 SILABS_DBUS_TIMER6_CC0(0x2, 0x4) +#define TIMER6_CC0_PC5 SILABS_DBUS_TIMER6_CC0(0x2, 0x5) +#define TIMER6_CC0_PC6 SILABS_DBUS_TIMER6_CC0(0x2, 0x6) +#define TIMER6_CC0_PC7 SILABS_DBUS_TIMER6_CC0(0x2, 0x7) +#define TIMER6_CC0_PC8 SILABS_DBUS_TIMER6_CC0(0x2, 0x8) +#define TIMER6_CC0_PC9 SILABS_DBUS_TIMER6_CC0(0x2, 0x9) +#define TIMER6_CC0_PC10 SILABS_DBUS_TIMER6_CC0(0x2, 0xa) +#define TIMER6_CC0_PC11 SILABS_DBUS_TIMER6_CC0(0x2, 0xb) +#define TIMER6_CC0_PC12 SILABS_DBUS_TIMER6_CC0(0x2, 0xc) +#define TIMER6_CC0_PC13 SILABS_DBUS_TIMER6_CC0(0x2, 0xd) +#define TIMER6_CC0_PC14 SILABS_DBUS_TIMER6_CC0(0x2, 0xe) +#define TIMER6_CC0_PC15 SILABS_DBUS_TIMER6_CC0(0x2, 0xf) +#define TIMER6_CC0_PD0 SILABS_DBUS_TIMER6_CC0(0x3, 0x0) +#define TIMER6_CC0_PD1 SILABS_DBUS_TIMER6_CC0(0x3, 0x1) +#define TIMER6_CC0_PD2 SILABS_DBUS_TIMER6_CC0(0x3, 0x2) +#define TIMER6_CC0_PD3 SILABS_DBUS_TIMER6_CC0(0x3, 0x3) +#define TIMER6_CC0_PD4 SILABS_DBUS_TIMER6_CC0(0x3, 0x4) +#define TIMER6_CC0_PD5 SILABS_DBUS_TIMER6_CC0(0x3, 0x5) +#define TIMER6_CC0_PD6 SILABS_DBUS_TIMER6_CC0(0x3, 0x6) +#define TIMER6_CC0_PD7 SILABS_DBUS_TIMER6_CC0(0x3, 0x7) +#define TIMER6_CC0_PD8 SILABS_DBUS_TIMER6_CC0(0x3, 0x8) +#define TIMER6_CC0_PD9 SILABS_DBUS_TIMER6_CC0(0x3, 0x9) +#define TIMER6_CC0_PD10 SILABS_DBUS_TIMER6_CC0(0x3, 0xa) +#define TIMER6_CC0_PD11 SILABS_DBUS_TIMER6_CC0(0x3, 0xb) +#define TIMER6_CC0_PD12 SILABS_DBUS_TIMER6_CC0(0x3, 0xc) +#define TIMER6_CC0_PD13 SILABS_DBUS_TIMER6_CC0(0x3, 0xd) +#define TIMER6_CC0_PD14 SILABS_DBUS_TIMER6_CC0(0x3, 0xe) +#define TIMER6_CC0_PD15 SILABS_DBUS_TIMER6_CC0(0x3, 0xf) +#define TIMER6_CC1_PA0 SILABS_DBUS_TIMER6_CC1(0x0, 0x0) +#define TIMER6_CC1_PA1 SILABS_DBUS_TIMER6_CC1(0x0, 0x1) +#define TIMER6_CC1_PA2 SILABS_DBUS_TIMER6_CC1(0x0, 0x2) +#define TIMER6_CC1_PA3 SILABS_DBUS_TIMER6_CC1(0x0, 0x3) +#define TIMER6_CC1_PA4 SILABS_DBUS_TIMER6_CC1(0x0, 0x4) +#define TIMER6_CC1_PA5 SILABS_DBUS_TIMER6_CC1(0x0, 0x5) +#define TIMER6_CC1_PA6 SILABS_DBUS_TIMER6_CC1(0x0, 0x6) +#define TIMER6_CC1_PA7 SILABS_DBUS_TIMER6_CC1(0x0, 0x7) +#define TIMER6_CC1_PA8 SILABS_DBUS_TIMER6_CC1(0x0, 0x8) +#define TIMER6_CC1_PA9 SILABS_DBUS_TIMER6_CC1(0x0, 0x9) +#define TIMER6_CC1_PA10 SILABS_DBUS_TIMER6_CC1(0x0, 0xa) +#define TIMER6_CC1_PA11 SILABS_DBUS_TIMER6_CC1(0x0, 0xb) +#define TIMER6_CC1_PA12 SILABS_DBUS_TIMER6_CC1(0x0, 0xc) +#define TIMER6_CC1_PA13 SILABS_DBUS_TIMER6_CC1(0x0, 0xd) +#define TIMER6_CC1_PA14 SILABS_DBUS_TIMER6_CC1(0x0, 0xe) +#define TIMER6_CC1_PA15 SILABS_DBUS_TIMER6_CC1(0x0, 0xf) +#define TIMER6_CC1_PB0 SILABS_DBUS_TIMER6_CC1(0x1, 0x0) +#define TIMER6_CC1_PB1 SILABS_DBUS_TIMER6_CC1(0x1, 0x1) +#define TIMER6_CC1_PB2 SILABS_DBUS_TIMER6_CC1(0x1, 0x2) +#define TIMER6_CC1_PB3 SILABS_DBUS_TIMER6_CC1(0x1, 0x3) +#define TIMER6_CC1_PB4 SILABS_DBUS_TIMER6_CC1(0x1, 0x4) +#define TIMER6_CC1_PB5 SILABS_DBUS_TIMER6_CC1(0x1, 0x5) +#define TIMER6_CC1_PB6 SILABS_DBUS_TIMER6_CC1(0x1, 0x6) +#define TIMER6_CC1_PB7 SILABS_DBUS_TIMER6_CC1(0x1, 0x7) +#define TIMER6_CC1_PB8 SILABS_DBUS_TIMER6_CC1(0x1, 0x8) +#define TIMER6_CC1_PB9 SILABS_DBUS_TIMER6_CC1(0x1, 0x9) +#define TIMER6_CC1_PB10 SILABS_DBUS_TIMER6_CC1(0x1, 0xa) +#define TIMER6_CC1_PB11 SILABS_DBUS_TIMER6_CC1(0x1, 0xb) +#define TIMER6_CC1_PB12 SILABS_DBUS_TIMER6_CC1(0x1, 0xc) +#define TIMER6_CC1_PB13 SILABS_DBUS_TIMER6_CC1(0x1, 0xd) +#define TIMER6_CC1_PB14 SILABS_DBUS_TIMER6_CC1(0x1, 0xe) +#define TIMER6_CC1_PB15 SILABS_DBUS_TIMER6_CC1(0x1, 0xf) +#define TIMER6_CC1_PC0 SILABS_DBUS_TIMER6_CC1(0x2, 0x0) +#define TIMER6_CC1_PC1 SILABS_DBUS_TIMER6_CC1(0x2, 0x1) +#define TIMER6_CC1_PC2 SILABS_DBUS_TIMER6_CC1(0x2, 0x2) +#define TIMER6_CC1_PC3 SILABS_DBUS_TIMER6_CC1(0x2, 0x3) +#define TIMER6_CC1_PC4 SILABS_DBUS_TIMER6_CC1(0x2, 0x4) +#define TIMER6_CC1_PC5 SILABS_DBUS_TIMER6_CC1(0x2, 0x5) +#define TIMER6_CC1_PC6 SILABS_DBUS_TIMER6_CC1(0x2, 0x6) +#define TIMER6_CC1_PC7 SILABS_DBUS_TIMER6_CC1(0x2, 0x7) +#define TIMER6_CC1_PC8 SILABS_DBUS_TIMER6_CC1(0x2, 0x8) +#define TIMER6_CC1_PC9 SILABS_DBUS_TIMER6_CC1(0x2, 0x9) +#define TIMER6_CC1_PC10 SILABS_DBUS_TIMER6_CC1(0x2, 0xa) +#define TIMER6_CC1_PC11 SILABS_DBUS_TIMER6_CC1(0x2, 0xb) +#define TIMER6_CC1_PC12 SILABS_DBUS_TIMER6_CC1(0x2, 0xc) +#define TIMER6_CC1_PC13 SILABS_DBUS_TIMER6_CC1(0x2, 0xd) +#define TIMER6_CC1_PC14 SILABS_DBUS_TIMER6_CC1(0x2, 0xe) +#define TIMER6_CC1_PC15 SILABS_DBUS_TIMER6_CC1(0x2, 0xf) +#define TIMER6_CC1_PD0 SILABS_DBUS_TIMER6_CC1(0x3, 0x0) +#define TIMER6_CC1_PD1 SILABS_DBUS_TIMER6_CC1(0x3, 0x1) +#define TIMER6_CC1_PD2 SILABS_DBUS_TIMER6_CC1(0x3, 0x2) +#define TIMER6_CC1_PD3 SILABS_DBUS_TIMER6_CC1(0x3, 0x3) +#define TIMER6_CC1_PD4 SILABS_DBUS_TIMER6_CC1(0x3, 0x4) +#define TIMER6_CC1_PD5 SILABS_DBUS_TIMER6_CC1(0x3, 0x5) +#define TIMER6_CC1_PD6 SILABS_DBUS_TIMER6_CC1(0x3, 0x6) +#define TIMER6_CC1_PD7 SILABS_DBUS_TIMER6_CC1(0x3, 0x7) +#define TIMER6_CC1_PD8 SILABS_DBUS_TIMER6_CC1(0x3, 0x8) +#define TIMER6_CC1_PD9 SILABS_DBUS_TIMER6_CC1(0x3, 0x9) +#define TIMER6_CC1_PD10 SILABS_DBUS_TIMER6_CC1(0x3, 0xa) +#define TIMER6_CC1_PD11 SILABS_DBUS_TIMER6_CC1(0x3, 0xb) +#define TIMER6_CC1_PD12 SILABS_DBUS_TIMER6_CC1(0x3, 0xc) +#define TIMER6_CC1_PD13 SILABS_DBUS_TIMER6_CC1(0x3, 0xd) +#define TIMER6_CC1_PD14 SILABS_DBUS_TIMER6_CC1(0x3, 0xe) +#define TIMER6_CC1_PD15 SILABS_DBUS_TIMER6_CC1(0x3, 0xf) +#define TIMER6_CC2_PA0 SILABS_DBUS_TIMER6_CC2(0x0, 0x0) +#define TIMER6_CC2_PA1 SILABS_DBUS_TIMER6_CC2(0x0, 0x1) +#define TIMER6_CC2_PA2 SILABS_DBUS_TIMER6_CC2(0x0, 0x2) +#define TIMER6_CC2_PA3 SILABS_DBUS_TIMER6_CC2(0x0, 0x3) +#define TIMER6_CC2_PA4 SILABS_DBUS_TIMER6_CC2(0x0, 0x4) +#define TIMER6_CC2_PA5 SILABS_DBUS_TIMER6_CC2(0x0, 0x5) +#define TIMER6_CC2_PA6 SILABS_DBUS_TIMER6_CC2(0x0, 0x6) +#define TIMER6_CC2_PA7 SILABS_DBUS_TIMER6_CC2(0x0, 0x7) +#define TIMER6_CC2_PA8 SILABS_DBUS_TIMER6_CC2(0x0, 0x8) +#define TIMER6_CC2_PA9 SILABS_DBUS_TIMER6_CC2(0x0, 0x9) +#define TIMER6_CC2_PA10 SILABS_DBUS_TIMER6_CC2(0x0, 0xa) +#define TIMER6_CC2_PA11 SILABS_DBUS_TIMER6_CC2(0x0, 0xb) +#define TIMER6_CC2_PA12 SILABS_DBUS_TIMER6_CC2(0x0, 0xc) +#define TIMER6_CC2_PA13 SILABS_DBUS_TIMER6_CC2(0x0, 0xd) +#define TIMER6_CC2_PA14 SILABS_DBUS_TIMER6_CC2(0x0, 0xe) +#define TIMER6_CC2_PA15 SILABS_DBUS_TIMER6_CC2(0x0, 0xf) +#define TIMER6_CC2_PB0 SILABS_DBUS_TIMER6_CC2(0x1, 0x0) +#define TIMER6_CC2_PB1 SILABS_DBUS_TIMER6_CC2(0x1, 0x1) +#define TIMER6_CC2_PB2 SILABS_DBUS_TIMER6_CC2(0x1, 0x2) +#define TIMER6_CC2_PB3 SILABS_DBUS_TIMER6_CC2(0x1, 0x3) +#define TIMER6_CC2_PB4 SILABS_DBUS_TIMER6_CC2(0x1, 0x4) +#define TIMER6_CC2_PB5 SILABS_DBUS_TIMER6_CC2(0x1, 0x5) +#define TIMER6_CC2_PB6 SILABS_DBUS_TIMER6_CC2(0x1, 0x6) +#define TIMER6_CC2_PB7 SILABS_DBUS_TIMER6_CC2(0x1, 0x7) +#define TIMER6_CC2_PB8 SILABS_DBUS_TIMER6_CC2(0x1, 0x8) +#define TIMER6_CC2_PB9 SILABS_DBUS_TIMER6_CC2(0x1, 0x9) +#define TIMER6_CC2_PB10 SILABS_DBUS_TIMER6_CC2(0x1, 0xa) +#define TIMER6_CC2_PB11 SILABS_DBUS_TIMER6_CC2(0x1, 0xb) +#define TIMER6_CC2_PB12 SILABS_DBUS_TIMER6_CC2(0x1, 0xc) +#define TIMER6_CC2_PB13 SILABS_DBUS_TIMER6_CC2(0x1, 0xd) +#define TIMER6_CC2_PB14 SILABS_DBUS_TIMER6_CC2(0x1, 0xe) +#define TIMER6_CC2_PB15 SILABS_DBUS_TIMER6_CC2(0x1, 0xf) +#define TIMER6_CC2_PC0 SILABS_DBUS_TIMER6_CC2(0x2, 0x0) +#define TIMER6_CC2_PC1 SILABS_DBUS_TIMER6_CC2(0x2, 0x1) +#define TIMER6_CC2_PC2 SILABS_DBUS_TIMER6_CC2(0x2, 0x2) +#define TIMER6_CC2_PC3 SILABS_DBUS_TIMER6_CC2(0x2, 0x3) +#define TIMER6_CC2_PC4 SILABS_DBUS_TIMER6_CC2(0x2, 0x4) +#define TIMER6_CC2_PC5 SILABS_DBUS_TIMER6_CC2(0x2, 0x5) +#define TIMER6_CC2_PC6 SILABS_DBUS_TIMER6_CC2(0x2, 0x6) +#define TIMER6_CC2_PC7 SILABS_DBUS_TIMER6_CC2(0x2, 0x7) +#define TIMER6_CC2_PC8 SILABS_DBUS_TIMER6_CC2(0x2, 0x8) +#define TIMER6_CC2_PC9 SILABS_DBUS_TIMER6_CC2(0x2, 0x9) +#define TIMER6_CC2_PC10 SILABS_DBUS_TIMER6_CC2(0x2, 0xa) +#define TIMER6_CC2_PC11 SILABS_DBUS_TIMER6_CC2(0x2, 0xb) +#define TIMER6_CC2_PC12 SILABS_DBUS_TIMER6_CC2(0x2, 0xc) +#define TIMER6_CC2_PC13 SILABS_DBUS_TIMER6_CC2(0x2, 0xd) +#define TIMER6_CC2_PC14 SILABS_DBUS_TIMER6_CC2(0x2, 0xe) +#define TIMER6_CC2_PC15 SILABS_DBUS_TIMER6_CC2(0x2, 0xf) +#define TIMER6_CC2_PD0 SILABS_DBUS_TIMER6_CC2(0x3, 0x0) +#define TIMER6_CC2_PD1 SILABS_DBUS_TIMER6_CC2(0x3, 0x1) +#define TIMER6_CC2_PD2 SILABS_DBUS_TIMER6_CC2(0x3, 0x2) +#define TIMER6_CC2_PD3 SILABS_DBUS_TIMER6_CC2(0x3, 0x3) +#define TIMER6_CC2_PD4 SILABS_DBUS_TIMER6_CC2(0x3, 0x4) +#define TIMER6_CC2_PD5 SILABS_DBUS_TIMER6_CC2(0x3, 0x5) +#define TIMER6_CC2_PD6 SILABS_DBUS_TIMER6_CC2(0x3, 0x6) +#define TIMER6_CC2_PD7 SILABS_DBUS_TIMER6_CC2(0x3, 0x7) +#define TIMER6_CC2_PD8 SILABS_DBUS_TIMER6_CC2(0x3, 0x8) +#define TIMER6_CC2_PD9 SILABS_DBUS_TIMER6_CC2(0x3, 0x9) +#define TIMER6_CC2_PD10 SILABS_DBUS_TIMER6_CC2(0x3, 0xa) +#define TIMER6_CC2_PD11 SILABS_DBUS_TIMER6_CC2(0x3, 0xb) +#define TIMER6_CC2_PD12 SILABS_DBUS_TIMER6_CC2(0x3, 0xc) +#define TIMER6_CC2_PD13 SILABS_DBUS_TIMER6_CC2(0x3, 0xd) +#define TIMER6_CC2_PD14 SILABS_DBUS_TIMER6_CC2(0x3, 0xe) +#define TIMER6_CC2_PD15 SILABS_DBUS_TIMER6_CC2(0x3, 0xf) +#define TIMER6_CDTI0_PA0 SILABS_DBUS_TIMER6_CDTI0(0x0, 0x0) +#define TIMER6_CDTI0_PA1 SILABS_DBUS_TIMER6_CDTI0(0x0, 0x1) +#define TIMER6_CDTI0_PA2 SILABS_DBUS_TIMER6_CDTI0(0x0, 0x2) +#define TIMER6_CDTI0_PA3 SILABS_DBUS_TIMER6_CDTI0(0x0, 0x3) +#define TIMER6_CDTI0_PA4 SILABS_DBUS_TIMER6_CDTI0(0x0, 0x4) +#define TIMER6_CDTI0_PA5 SILABS_DBUS_TIMER6_CDTI0(0x0, 0x5) +#define TIMER6_CDTI0_PA6 SILABS_DBUS_TIMER6_CDTI0(0x0, 0x6) +#define TIMER6_CDTI0_PA7 SILABS_DBUS_TIMER6_CDTI0(0x0, 0x7) +#define TIMER6_CDTI0_PA8 SILABS_DBUS_TIMER6_CDTI0(0x0, 0x8) +#define TIMER6_CDTI0_PA9 SILABS_DBUS_TIMER6_CDTI0(0x0, 0x9) +#define TIMER6_CDTI0_PA10 SILABS_DBUS_TIMER6_CDTI0(0x0, 0xa) +#define TIMER6_CDTI0_PA11 SILABS_DBUS_TIMER6_CDTI0(0x0, 0xb) +#define TIMER6_CDTI0_PA12 SILABS_DBUS_TIMER6_CDTI0(0x0, 0xc) +#define TIMER6_CDTI0_PA13 SILABS_DBUS_TIMER6_CDTI0(0x0, 0xd) +#define TIMER6_CDTI0_PA14 SILABS_DBUS_TIMER6_CDTI0(0x0, 0xe) +#define TIMER6_CDTI0_PA15 SILABS_DBUS_TIMER6_CDTI0(0x0, 0xf) +#define TIMER6_CDTI0_PB0 SILABS_DBUS_TIMER6_CDTI0(0x1, 0x0) +#define TIMER6_CDTI0_PB1 SILABS_DBUS_TIMER6_CDTI0(0x1, 0x1) +#define TIMER6_CDTI0_PB2 SILABS_DBUS_TIMER6_CDTI0(0x1, 0x2) +#define TIMER6_CDTI0_PB3 SILABS_DBUS_TIMER6_CDTI0(0x1, 0x3) +#define TIMER6_CDTI0_PB4 SILABS_DBUS_TIMER6_CDTI0(0x1, 0x4) +#define TIMER6_CDTI0_PB5 SILABS_DBUS_TIMER6_CDTI0(0x1, 0x5) +#define TIMER6_CDTI0_PB6 SILABS_DBUS_TIMER6_CDTI0(0x1, 0x6) +#define TIMER6_CDTI0_PB7 SILABS_DBUS_TIMER6_CDTI0(0x1, 0x7) +#define TIMER6_CDTI0_PB8 SILABS_DBUS_TIMER6_CDTI0(0x1, 0x8) +#define TIMER6_CDTI0_PB9 SILABS_DBUS_TIMER6_CDTI0(0x1, 0x9) +#define TIMER6_CDTI0_PB10 SILABS_DBUS_TIMER6_CDTI0(0x1, 0xa) +#define TIMER6_CDTI0_PB11 SILABS_DBUS_TIMER6_CDTI0(0x1, 0xb) +#define TIMER6_CDTI0_PB12 SILABS_DBUS_TIMER6_CDTI0(0x1, 0xc) +#define TIMER6_CDTI0_PB13 SILABS_DBUS_TIMER6_CDTI0(0x1, 0xd) +#define TIMER6_CDTI0_PB14 SILABS_DBUS_TIMER6_CDTI0(0x1, 0xe) +#define TIMER6_CDTI0_PB15 SILABS_DBUS_TIMER6_CDTI0(0x1, 0xf) +#define TIMER6_CDTI0_PC0 SILABS_DBUS_TIMER6_CDTI0(0x2, 0x0) +#define TIMER6_CDTI0_PC1 SILABS_DBUS_TIMER6_CDTI0(0x2, 0x1) +#define TIMER6_CDTI0_PC2 SILABS_DBUS_TIMER6_CDTI0(0x2, 0x2) +#define TIMER6_CDTI0_PC3 SILABS_DBUS_TIMER6_CDTI0(0x2, 0x3) +#define TIMER6_CDTI0_PC4 SILABS_DBUS_TIMER6_CDTI0(0x2, 0x4) +#define TIMER6_CDTI0_PC5 SILABS_DBUS_TIMER6_CDTI0(0x2, 0x5) +#define TIMER6_CDTI0_PC6 SILABS_DBUS_TIMER6_CDTI0(0x2, 0x6) +#define TIMER6_CDTI0_PC7 SILABS_DBUS_TIMER6_CDTI0(0x2, 0x7) +#define TIMER6_CDTI0_PC8 SILABS_DBUS_TIMER6_CDTI0(0x2, 0x8) +#define TIMER6_CDTI0_PC9 SILABS_DBUS_TIMER6_CDTI0(0x2, 0x9) +#define TIMER6_CDTI0_PC10 SILABS_DBUS_TIMER6_CDTI0(0x2, 0xa) +#define TIMER6_CDTI0_PC11 SILABS_DBUS_TIMER6_CDTI0(0x2, 0xb) +#define TIMER6_CDTI0_PC12 SILABS_DBUS_TIMER6_CDTI0(0x2, 0xc) +#define TIMER6_CDTI0_PC13 SILABS_DBUS_TIMER6_CDTI0(0x2, 0xd) +#define TIMER6_CDTI0_PC14 SILABS_DBUS_TIMER6_CDTI0(0x2, 0xe) +#define TIMER6_CDTI0_PC15 SILABS_DBUS_TIMER6_CDTI0(0x2, 0xf) +#define TIMER6_CDTI0_PD0 SILABS_DBUS_TIMER6_CDTI0(0x3, 0x0) +#define TIMER6_CDTI0_PD1 SILABS_DBUS_TIMER6_CDTI0(0x3, 0x1) +#define TIMER6_CDTI0_PD2 SILABS_DBUS_TIMER6_CDTI0(0x3, 0x2) +#define TIMER6_CDTI0_PD3 SILABS_DBUS_TIMER6_CDTI0(0x3, 0x3) +#define TIMER6_CDTI0_PD4 SILABS_DBUS_TIMER6_CDTI0(0x3, 0x4) +#define TIMER6_CDTI0_PD5 SILABS_DBUS_TIMER6_CDTI0(0x3, 0x5) +#define TIMER6_CDTI0_PD6 SILABS_DBUS_TIMER6_CDTI0(0x3, 0x6) +#define TIMER6_CDTI0_PD7 SILABS_DBUS_TIMER6_CDTI0(0x3, 0x7) +#define TIMER6_CDTI0_PD8 SILABS_DBUS_TIMER6_CDTI0(0x3, 0x8) +#define TIMER6_CDTI0_PD9 SILABS_DBUS_TIMER6_CDTI0(0x3, 0x9) +#define TIMER6_CDTI0_PD10 SILABS_DBUS_TIMER6_CDTI0(0x3, 0xa) +#define TIMER6_CDTI0_PD11 SILABS_DBUS_TIMER6_CDTI0(0x3, 0xb) +#define TIMER6_CDTI0_PD12 SILABS_DBUS_TIMER6_CDTI0(0x3, 0xc) +#define TIMER6_CDTI0_PD13 SILABS_DBUS_TIMER6_CDTI0(0x3, 0xd) +#define TIMER6_CDTI0_PD14 SILABS_DBUS_TIMER6_CDTI0(0x3, 0xe) +#define TIMER6_CDTI0_PD15 SILABS_DBUS_TIMER6_CDTI0(0x3, 0xf) +#define TIMER6_CDTI1_PA0 SILABS_DBUS_TIMER6_CDTI1(0x0, 0x0) +#define TIMER6_CDTI1_PA1 SILABS_DBUS_TIMER6_CDTI1(0x0, 0x1) +#define TIMER6_CDTI1_PA2 SILABS_DBUS_TIMER6_CDTI1(0x0, 0x2) +#define TIMER6_CDTI1_PA3 SILABS_DBUS_TIMER6_CDTI1(0x0, 0x3) +#define TIMER6_CDTI1_PA4 SILABS_DBUS_TIMER6_CDTI1(0x0, 0x4) +#define TIMER6_CDTI1_PA5 SILABS_DBUS_TIMER6_CDTI1(0x0, 0x5) +#define TIMER6_CDTI1_PA6 SILABS_DBUS_TIMER6_CDTI1(0x0, 0x6) +#define TIMER6_CDTI1_PA7 SILABS_DBUS_TIMER6_CDTI1(0x0, 0x7) +#define TIMER6_CDTI1_PA8 SILABS_DBUS_TIMER6_CDTI1(0x0, 0x8) +#define TIMER6_CDTI1_PA9 SILABS_DBUS_TIMER6_CDTI1(0x0, 0x9) +#define TIMER6_CDTI1_PA10 SILABS_DBUS_TIMER6_CDTI1(0x0, 0xa) +#define TIMER6_CDTI1_PA11 SILABS_DBUS_TIMER6_CDTI1(0x0, 0xb) +#define TIMER6_CDTI1_PA12 SILABS_DBUS_TIMER6_CDTI1(0x0, 0xc) +#define TIMER6_CDTI1_PA13 SILABS_DBUS_TIMER6_CDTI1(0x0, 0xd) +#define TIMER6_CDTI1_PA14 SILABS_DBUS_TIMER6_CDTI1(0x0, 0xe) +#define TIMER6_CDTI1_PA15 SILABS_DBUS_TIMER6_CDTI1(0x0, 0xf) +#define TIMER6_CDTI1_PB0 SILABS_DBUS_TIMER6_CDTI1(0x1, 0x0) +#define TIMER6_CDTI1_PB1 SILABS_DBUS_TIMER6_CDTI1(0x1, 0x1) +#define TIMER6_CDTI1_PB2 SILABS_DBUS_TIMER6_CDTI1(0x1, 0x2) +#define TIMER6_CDTI1_PB3 SILABS_DBUS_TIMER6_CDTI1(0x1, 0x3) +#define TIMER6_CDTI1_PB4 SILABS_DBUS_TIMER6_CDTI1(0x1, 0x4) +#define TIMER6_CDTI1_PB5 SILABS_DBUS_TIMER6_CDTI1(0x1, 0x5) +#define TIMER6_CDTI1_PB6 SILABS_DBUS_TIMER6_CDTI1(0x1, 0x6) +#define TIMER6_CDTI1_PB7 SILABS_DBUS_TIMER6_CDTI1(0x1, 0x7) +#define TIMER6_CDTI1_PB8 SILABS_DBUS_TIMER6_CDTI1(0x1, 0x8) +#define TIMER6_CDTI1_PB9 SILABS_DBUS_TIMER6_CDTI1(0x1, 0x9) +#define TIMER6_CDTI1_PB10 SILABS_DBUS_TIMER6_CDTI1(0x1, 0xa) +#define TIMER6_CDTI1_PB11 SILABS_DBUS_TIMER6_CDTI1(0x1, 0xb) +#define TIMER6_CDTI1_PB12 SILABS_DBUS_TIMER6_CDTI1(0x1, 0xc) +#define TIMER6_CDTI1_PB13 SILABS_DBUS_TIMER6_CDTI1(0x1, 0xd) +#define TIMER6_CDTI1_PB14 SILABS_DBUS_TIMER6_CDTI1(0x1, 0xe) +#define TIMER6_CDTI1_PB15 SILABS_DBUS_TIMER6_CDTI1(0x1, 0xf) +#define TIMER6_CDTI1_PC0 SILABS_DBUS_TIMER6_CDTI1(0x2, 0x0) +#define TIMER6_CDTI1_PC1 SILABS_DBUS_TIMER6_CDTI1(0x2, 0x1) +#define TIMER6_CDTI1_PC2 SILABS_DBUS_TIMER6_CDTI1(0x2, 0x2) +#define TIMER6_CDTI1_PC3 SILABS_DBUS_TIMER6_CDTI1(0x2, 0x3) +#define TIMER6_CDTI1_PC4 SILABS_DBUS_TIMER6_CDTI1(0x2, 0x4) +#define TIMER6_CDTI1_PC5 SILABS_DBUS_TIMER6_CDTI1(0x2, 0x5) +#define TIMER6_CDTI1_PC6 SILABS_DBUS_TIMER6_CDTI1(0x2, 0x6) +#define TIMER6_CDTI1_PC7 SILABS_DBUS_TIMER6_CDTI1(0x2, 0x7) +#define TIMER6_CDTI1_PC8 SILABS_DBUS_TIMER6_CDTI1(0x2, 0x8) +#define TIMER6_CDTI1_PC9 SILABS_DBUS_TIMER6_CDTI1(0x2, 0x9) +#define TIMER6_CDTI1_PC10 SILABS_DBUS_TIMER6_CDTI1(0x2, 0xa) +#define TIMER6_CDTI1_PC11 SILABS_DBUS_TIMER6_CDTI1(0x2, 0xb) +#define TIMER6_CDTI1_PC12 SILABS_DBUS_TIMER6_CDTI1(0x2, 0xc) +#define TIMER6_CDTI1_PC13 SILABS_DBUS_TIMER6_CDTI1(0x2, 0xd) +#define TIMER6_CDTI1_PC14 SILABS_DBUS_TIMER6_CDTI1(0x2, 0xe) +#define TIMER6_CDTI1_PC15 SILABS_DBUS_TIMER6_CDTI1(0x2, 0xf) +#define TIMER6_CDTI1_PD0 SILABS_DBUS_TIMER6_CDTI1(0x3, 0x0) +#define TIMER6_CDTI1_PD1 SILABS_DBUS_TIMER6_CDTI1(0x3, 0x1) +#define TIMER6_CDTI1_PD2 SILABS_DBUS_TIMER6_CDTI1(0x3, 0x2) +#define TIMER6_CDTI1_PD3 SILABS_DBUS_TIMER6_CDTI1(0x3, 0x3) +#define TIMER6_CDTI1_PD4 SILABS_DBUS_TIMER6_CDTI1(0x3, 0x4) +#define TIMER6_CDTI1_PD5 SILABS_DBUS_TIMER6_CDTI1(0x3, 0x5) +#define TIMER6_CDTI1_PD6 SILABS_DBUS_TIMER6_CDTI1(0x3, 0x6) +#define TIMER6_CDTI1_PD7 SILABS_DBUS_TIMER6_CDTI1(0x3, 0x7) +#define TIMER6_CDTI1_PD8 SILABS_DBUS_TIMER6_CDTI1(0x3, 0x8) +#define TIMER6_CDTI1_PD9 SILABS_DBUS_TIMER6_CDTI1(0x3, 0x9) +#define TIMER6_CDTI1_PD10 SILABS_DBUS_TIMER6_CDTI1(0x3, 0xa) +#define TIMER6_CDTI1_PD11 SILABS_DBUS_TIMER6_CDTI1(0x3, 0xb) +#define TIMER6_CDTI1_PD12 SILABS_DBUS_TIMER6_CDTI1(0x3, 0xc) +#define TIMER6_CDTI1_PD13 SILABS_DBUS_TIMER6_CDTI1(0x3, 0xd) +#define TIMER6_CDTI1_PD14 SILABS_DBUS_TIMER6_CDTI1(0x3, 0xe) +#define TIMER6_CDTI1_PD15 SILABS_DBUS_TIMER6_CDTI1(0x3, 0xf) +#define TIMER6_CDTI2_PA0 SILABS_DBUS_TIMER6_CDTI2(0x0, 0x0) +#define TIMER6_CDTI2_PA1 SILABS_DBUS_TIMER6_CDTI2(0x0, 0x1) +#define TIMER6_CDTI2_PA2 SILABS_DBUS_TIMER6_CDTI2(0x0, 0x2) +#define TIMER6_CDTI2_PA3 SILABS_DBUS_TIMER6_CDTI2(0x0, 0x3) +#define TIMER6_CDTI2_PA4 SILABS_DBUS_TIMER6_CDTI2(0x0, 0x4) +#define TIMER6_CDTI2_PA5 SILABS_DBUS_TIMER6_CDTI2(0x0, 0x5) +#define TIMER6_CDTI2_PA6 SILABS_DBUS_TIMER6_CDTI2(0x0, 0x6) +#define TIMER6_CDTI2_PA7 SILABS_DBUS_TIMER6_CDTI2(0x0, 0x7) +#define TIMER6_CDTI2_PA8 SILABS_DBUS_TIMER6_CDTI2(0x0, 0x8) +#define TIMER6_CDTI2_PA9 SILABS_DBUS_TIMER6_CDTI2(0x0, 0x9) +#define TIMER6_CDTI2_PA10 SILABS_DBUS_TIMER6_CDTI2(0x0, 0xa) +#define TIMER6_CDTI2_PA11 SILABS_DBUS_TIMER6_CDTI2(0x0, 0xb) +#define TIMER6_CDTI2_PA12 SILABS_DBUS_TIMER6_CDTI2(0x0, 0xc) +#define TIMER6_CDTI2_PA13 SILABS_DBUS_TIMER6_CDTI2(0x0, 0xd) +#define TIMER6_CDTI2_PA14 SILABS_DBUS_TIMER6_CDTI2(0x0, 0xe) +#define TIMER6_CDTI2_PA15 SILABS_DBUS_TIMER6_CDTI2(0x0, 0xf) +#define TIMER6_CDTI2_PB0 SILABS_DBUS_TIMER6_CDTI2(0x1, 0x0) +#define TIMER6_CDTI2_PB1 SILABS_DBUS_TIMER6_CDTI2(0x1, 0x1) +#define TIMER6_CDTI2_PB2 SILABS_DBUS_TIMER6_CDTI2(0x1, 0x2) +#define TIMER6_CDTI2_PB3 SILABS_DBUS_TIMER6_CDTI2(0x1, 0x3) +#define TIMER6_CDTI2_PB4 SILABS_DBUS_TIMER6_CDTI2(0x1, 0x4) +#define TIMER6_CDTI2_PB5 SILABS_DBUS_TIMER6_CDTI2(0x1, 0x5) +#define TIMER6_CDTI2_PB6 SILABS_DBUS_TIMER6_CDTI2(0x1, 0x6) +#define TIMER6_CDTI2_PB7 SILABS_DBUS_TIMER6_CDTI2(0x1, 0x7) +#define TIMER6_CDTI2_PB8 SILABS_DBUS_TIMER6_CDTI2(0x1, 0x8) +#define TIMER6_CDTI2_PB9 SILABS_DBUS_TIMER6_CDTI2(0x1, 0x9) +#define TIMER6_CDTI2_PB10 SILABS_DBUS_TIMER6_CDTI2(0x1, 0xa) +#define TIMER6_CDTI2_PB11 SILABS_DBUS_TIMER6_CDTI2(0x1, 0xb) +#define TIMER6_CDTI2_PB12 SILABS_DBUS_TIMER6_CDTI2(0x1, 0xc) +#define TIMER6_CDTI2_PB13 SILABS_DBUS_TIMER6_CDTI2(0x1, 0xd) +#define TIMER6_CDTI2_PB14 SILABS_DBUS_TIMER6_CDTI2(0x1, 0xe) +#define TIMER6_CDTI2_PB15 SILABS_DBUS_TIMER6_CDTI2(0x1, 0xf) +#define TIMER6_CDTI2_PC0 SILABS_DBUS_TIMER6_CDTI2(0x2, 0x0) +#define TIMER6_CDTI2_PC1 SILABS_DBUS_TIMER6_CDTI2(0x2, 0x1) +#define TIMER6_CDTI2_PC2 SILABS_DBUS_TIMER6_CDTI2(0x2, 0x2) +#define TIMER6_CDTI2_PC3 SILABS_DBUS_TIMER6_CDTI2(0x2, 0x3) +#define TIMER6_CDTI2_PC4 SILABS_DBUS_TIMER6_CDTI2(0x2, 0x4) +#define TIMER6_CDTI2_PC5 SILABS_DBUS_TIMER6_CDTI2(0x2, 0x5) +#define TIMER6_CDTI2_PC6 SILABS_DBUS_TIMER6_CDTI2(0x2, 0x6) +#define TIMER6_CDTI2_PC7 SILABS_DBUS_TIMER6_CDTI2(0x2, 0x7) +#define TIMER6_CDTI2_PC8 SILABS_DBUS_TIMER6_CDTI2(0x2, 0x8) +#define TIMER6_CDTI2_PC9 SILABS_DBUS_TIMER6_CDTI2(0x2, 0x9) +#define TIMER6_CDTI2_PC10 SILABS_DBUS_TIMER6_CDTI2(0x2, 0xa) +#define TIMER6_CDTI2_PC11 SILABS_DBUS_TIMER6_CDTI2(0x2, 0xb) +#define TIMER6_CDTI2_PC12 SILABS_DBUS_TIMER6_CDTI2(0x2, 0xc) +#define TIMER6_CDTI2_PC13 SILABS_DBUS_TIMER6_CDTI2(0x2, 0xd) +#define TIMER6_CDTI2_PC14 SILABS_DBUS_TIMER6_CDTI2(0x2, 0xe) +#define TIMER6_CDTI2_PC15 SILABS_DBUS_TIMER6_CDTI2(0x2, 0xf) +#define TIMER6_CDTI2_PD0 SILABS_DBUS_TIMER6_CDTI2(0x3, 0x0) +#define TIMER6_CDTI2_PD1 SILABS_DBUS_TIMER6_CDTI2(0x3, 0x1) +#define TIMER6_CDTI2_PD2 SILABS_DBUS_TIMER6_CDTI2(0x3, 0x2) +#define TIMER6_CDTI2_PD3 SILABS_DBUS_TIMER6_CDTI2(0x3, 0x3) +#define TIMER6_CDTI2_PD4 SILABS_DBUS_TIMER6_CDTI2(0x3, 0x4) +#define TIMER6_CDTI2_PD5 SILABS_DBUS_TIMER6_CDTI2(0x3, 0x5) +#define TIMER6_CDTI2_PD6 SILABS_DBUS_TIMER6_CDTI2(0x3, 0x6) +#define TIMER6_CDTI2_PD7 SILABS_DBUS_TIMER6_CDTI2(0x3, 0x7) +#define TIMER6_CDTI2_PD8 SILABS_DBUS_TIMER6_CDTI2(0x3, 0x8) +#define TIMER6_CDTI2_PD9 SILABS_DBUS_TIMER6_CDTI2(0x3, 0x9) +#define TIMER6_CDTI2_PD10 SILABS_DBUS_TIMER6_CDTI2(0x3, 0xa) +#define TIMER6_CDTI2_PD11 SILABS_DBUS_TIMER6_CDTI2(0x3, 0xb) +#define TIMER6_CDTI2_PD12 SILABS_DBUS_TIMER6_CDTI2(0x3, 0xc) +#define TIMER6_CDTI2_PD13 SILABS_DBUS_TIMER6_CDTI2(0x3, 0xd) +#define TIMER6_CDTI2_PD14 SILABS_DBUS_TIMER6_CDTI2(0x3, 0xe) +#define TIMER6_CDTI2_PD15 SILABS_DBUS_TIMER6_CDTI2(0x3, 0xf) + +#define TIMER7_CC0_PA0 SILABS_DBUS_TIMER7_CC0(0x0, 0x0) +#define TIMER7_CC0_PA1 SILABS_DBUS_TIMER7_CC0(0x0, 0x1) +#define TIMER7_CC0_PA2 SILABS_DBUS_TIMER7_CC0(0x0, 0x2) +#define TIMER7_CC0_PA3 SILABS_DBUS_TIMER7_CC0(0x0, 0x3) +#define TIMER7_CC0_PA4 SILABS_DBUS_TIMER7_CC0(0x0, 0x4) +#define TIMER7_CC0_PA5 SILABS_DBUS_TIMER7_CC0(0x0, 0x5) +#define TIMER7_CC0_PA6 SILABS_DBUS_TIMER7_CC0(0x0, 0x6) +#define TIMER7_CC0_PA7 SILABS_DBUS_TIMER7_CC0(0x0, 0x7) +#define TIMER7_CC0_PA8 SILABS_DBUS_TIMER7_CC0(0x0, 0x8) +#define TIMER7_CC0_PA9 SILABS_DBUS_TIMER7_CC0(0x0, 0x9) +#define TIMER7_CC0_PA10 SILABS_DBUS_TIMER7_CC0(0x0, 0xa) +#define TIMER7_CC0_PA11 SILABS_DBUS_TIMER7_CC0(0x0, 0xb) +#define TIMER7_CC0_PA12 SILABS_DBUS_TIMER7_CC0(0x0, 0xc) +#define TIMER7_CC0_PA13 SILABS_DBUS_TIMER7_CC0(0x0, 0xd) +#define TIMER7_CC0_PA14 SILABS_DBUS_TIMER7_CC0(0x0, 0xe) +#define TIMER7_CC0_PA15 SILABS_DBUS_TIMER7_CC0(0x0, 0xf) +#define TIMER7_CC0_PB0 SILABS_DBUS_TIMER7_CC0(0x1, 0x0) +#define TIMER7_CC0_PB1 SILABS_DBUS_TIMER7_CC0(0x1, 0x1) +#define TIMER7_CC0_PB2 SILABS_DBUS_TIMER7_CC0(0x1, 0x2) +#define TIMER7_CC0_PB3 SILABS_DBUS_TIMER7_CC0(0x1, 0x3) +#define TIMER7_CC0_PB4 SILABS_DBUS_TIMER7_CC0(0x1, 0x4) +#define TIMER7_CC0_PB5 SILABS_DBUS_TIMER7_CC0(0x1, 0x5) +#define TIMER7_CC0_PB6 SILABS_DBUS_TIMER7_CC0(0x1, 0x6) +#define TIMER7_CC0_PB7 SILABS_DBUS_TIMER7_CC0(0x1, 0x7) +#define TIMER7_CC0_PB8 SILABS_DBUS_TIMER7_CC0(0x1, 0x8) +#define TIMER7_CC0_PB9 SILABS_DBUS_TIMER7_CC0(0x1, 0x9) +#define TIMER7_CC0_PB10 SILABS_DBUS_TIMER7_CC0(0x1, 0xa) +#define TIMER7_CC0_PB11 SILABS_DBUS_TIMER7_CC0(0x1, 0xb) +#define TIMER7_CC0_PB12 SILABS_DBUS_TIMER7_CC0(0x1, 0xc) +#define TIMER7_CC0_PB13 SILABS_DBUS_TIMER7_CC0(0x1, 0xd) +#define TIMER7_CC0_PB14 SILABS_DBUS_TIMER7_CC0(0x1, 0xe) +#define TIMER7_CC0_PB15 SILABS_DBUS_TIMER7_CC0(0x1, 0xf) +#define TIMER7_CC0_PC0 SILABS_DBUS_TIMER7_CC0(0x2, 0x0) +#define TIMER7_CC0_PC1 SILABS_DBUS_TIMER7_CC0(0x2, 0x1) +#define TIMER7_CC0_PC2 SILABS_DBUS_TIMER7_CC0(0x2, 0x2) +#define TIMER7_CC0_PC3 SILABS_DBUS_TIMER7_CC0(0x2, 0x3) +#define TIMER7_CC0_PC4 SILABS_DBUS_TIMER7_CC0(0x2, 0x4) +#define TIMER7_CC0_PC5 SILABS_DBUS_TIMER7_CC0(0x2, 0x5) +#define TIMER7_CC0_PC6 SILABS_DBUS_TIMER7_CC0(0x2, 0x6) +#define TIMER7_CC0_PC7 SILABS_DBUS_TIMER7_CC0(0x2, 0x7) +#define TIMER7_CC0_PC8 SILABS_DBUS_TIMER7_CC0(0x2, 0x8) +#define TIMER7_CC0_PC9 SILABS_DBUS_TIMER7_CC0(0x2, 0x9) +#define TIMER7_CC0_PC10 SILABS_DBUS_TIMER7_CC0(0x2, 0xa) +#define TIMER7_CC0_PC11 SILABS_DBUS_TIMER7_CC0(0x2, 0xb) +#define TIMER7_CC0_PC12 SILABS_DBUS_TIMER7_CC0(0x2, 0xc) +#define TIMER7_CC0_PC13 SILABS_DBUS_TIMER7_CC0(0x2, 0xd) +#define TIMER7_CC0_PC14 SILABS_DBUS_TIMER7_CC0(0x2, 0xe) +#define TIMER7_CC0_PC15 SILABS_DBUS_TIMER7_CC0(0x2, 0xf) +#define TIMER7_CC0_PD0 SILABS_DBUS_TIMER7_CC0(0x3, 0x0) +#define TIMER7_CC0_PD1 SILABS_DBUS_TIMER7_CC0(0x3, 0x1) +#define TIMER7_CC0_PD2 SILABS_DBUS_TIMER7_CC0(0x3, 0x2) +#define TIMER7_CC0_PD3 SILABS_DBUS_TIMER7_CC0(0x3, 0x3) +#define TIMER7_CC0_PD4 SILABS_DBUS_TIMER7_CC0(0x3, 0x4) +#define TIMER7_CC0_PD5 SILABS_DBUS_TIMER7_CC0(0x3, 0x5) +#define TIMER7_CC0_PD6 SILABS_DBUS_TIMER7_CC0(0x3, 0x6) +#define TIMER7_CC0_PD7 SILABS_DBUS_TIMER7_CC0(0x3, 0x7) +#define TIMER7_CC0_PD8 SILABS_DBUS_TIMER7_CC0(0x3, 0x8) +#define TIMER7_CC0_PD9 SILABS_DBUS_TIMER7_CC0(0x3, 0x9) +#define TIMER7_CC0_PD10 SILABS_DBUS_TIMER7_CC0(0x3, 0xa) +#define TIMER7_CC0_PD11 SILABS_DBUS_TIMER7_CC0(0x3, 0xb) +#define TIMER7_CC0_PD12 SILABS_DBUS_TIMER7_CC0(0x3, 0xc) +#define TIMER7_CC0_PD13 SILABS_DBUS_TIMER7_CC0(0x3, 0xd) +#define TIMER7_CC0_PD14 SILABS_DBUS_TIMER7_CC0(0x3, 0xe) +#define TIMER7_CC0_PD15 SILABS_DBUS_TIMER7_CC0(0x3, 0xf) +#define TIMER7_CC1_PA0 SILABS_DBUS_TIMER7_CC1(0x0, 0x0) +#define TIMER7_CC1_PA1 SILABS_DBUS_TIMER7_CC1(0x0, 0x1) +#define TIMER7_CC1_PA2 SILABS_DBUS_TIMER7_CC1(0x0, 0x2) +#define TIMER7_CC1_PA3 SILABS_DBUS_TIMER7_CC1(0x0, 0x3) +#define TIMER7_CC1_PA4 SILABS_DBUS_TIMER7_CC1(0x0, 0x4) +#define TIMER7_CC1_PA5 SILABS_DBUS_TIMER7_CC1(0x0, 0x5) +#define TIMER7_CC1_PA6 SILABS_DBUS_TIMER7_CC1(0x0, 0x6) +#define TIMER7_CC1_PA7 SILABS_DBUS_TIMER7_CC1(0x0, 0x7) +#define TIMER7_CC1_PA8 SILABS_DBUS_TIMER7_CC1(0x0, 0x8) +#define TIMER7_CC1_PA9 SILABS_DBUS_TIMER7_CC1(0x0, 0x9) +#define TIMER7_CC1_PA10 SILABS_DBUS_TIMER7_CC1(0x0, 0xa) +#define TIMER7_CC1_PA11 SILABS_DBUS_TIMER7_CC1(0x0, 0xb) +#define TIMER7_CC1_PA12 SILABS_DBUS_TIMER7_CC1(0x0, 0xc) +#define TIMER7_CC1_PA13 SILABS_DBUS_TIMER7_CC1(0x0, 0xd) +#define TIMER7_CC1_PA14 SILABS_DBUS_TIMER7_CC1(0x0, 0xe) +#define TIMER7_CC1_PA15 SILABS_DBUS_TIMER7_CC1(0x0, 0xf) +#define TIMER7_CC1_PB0 SILABS_DBUS_TIMER7_CC1(0x1, 0x0) +#define TIMER7_CC1_PB1 SILABS_DBUS_TIMER7_CC1(0x1, 0x1) +#define TIMER7_CC1_PB2 SILABS_DBUS_TIMER7_CC1(0x1, 0x2) +#define TIMER7_CC1_PB3 SILABS_DBUS_TIMER7_CC1(0x1, 0x3) +#define TIMER7_CC1_PB4 SILABS_DBUS_TIMER7_CC1(0x1, 0x4) +#define TIMER7_CC1_PB5 SILABS_DBUS_TIMER7_CC1(0x1, 0x5) +#define TIMER7_CC1_PB6 SILABS_DBUS_TIMER7_CC1(0x1, 0x6) +#define TIMER7_CC1_PB7 SILABS_DBUS_TIMER7_CC1(0x1, 0x7) +#define TIMER7_CC1_PB8 SILABS_DBUS_TIMER7_CC1(0x1, 0x8) +#define TIMER7_CC1_PB9 SILABS_DBUS_TIMER7_CC1(0x1, 0x9) +#define TIMER7_CC1_PB10 SILABS_DBUS_TIMER7_CC1(0x1, 0xa) +#define TIMER7_CC1_PB11 SILABS_DBUS_TIMER7_CC1(0x1, 0xb) +#define TIMER7_CC1_PB12 SILABS_DBUS_TIMER7_CC1(0x1, 0xc) +#define TIMER7_CC1_PB13 SILABS_DBUS_TIMER7_CC1(0x1, 0xd) +#define TIMER7_CC1_PB14 SILABS_DBUS_TIMER7_CC1(0x1, 0xe) +#define TIMER7_CC1_PB15 SILABS_DBUS_TIMER7_CC1(0x1, 0xf) +#define TIMER7_CC1_PC0 SILABS_DBUS_TIMER7_CC1(0x2, 0x0) +#define TIMER7_CC1_PC1 SILABS_DBUS_TIMER7_CC1(0x2, 0x1) +#define TIMER7_CC1_PC2 SILABS_DBUS_TIMER7_CC1(0x2, 0x2) +#define TIMER7_CC1_PC3 SILABS_DBUS_TIMER7_CC1(0x2, 0x3) +#define TIMER7_CC1_PC4 SILABS_DBUS_TIMER7_CC1(0x2, 0x4) +#define TIMER7_CC1_PC5 SILABS_DBUS_TIMER7_CC1(0x2, 0x5) +#define TIMER7_CC1_PC6 SILABS_DBUS_TIMER7_CC1(0x2, 0x6) +#define TIMER7_CC1_PC7 SILABS_DBUS_TIMER7_CC1(0x2, 0x7) +#define TIMER7_CC1_PC8 SILABS_DBUS_TIMER7_CC1(0x2, 0x8) +#define TIMER7_CC1_PC9 SILABS_DBUS_TIMER7_CC1(0x2, 0x9) +#define TIMER7_CC1_PC10 SILABS_DBUS_TIMER7_CC1(0x2, 0xa) +#define TIMER7_CC1_PC11 SILABS_DBUS_TIMER7_CC1(0x2, 0xb) +#define TIMER7_CC1_PC12 SILABS_DBUS_TIMER7_CC1(0x2, 0xc) +#define TIMER7_CC1_PC13 SILABS_DBUS_TIMER7_CC1(0x2, 0xd) +#define TIMER7_CC1_PC14 SILABS_DBUS_TIMER7_CC1(0x2, 0xe) +#define TIMER7_CC1_PC15 SILABS_DBUS_TIMER7_CC1(0x2, 0xf) +#define TIMER7_CC1_PD0 SILABS_DBUS_TIMER7_CC1(0x3, 0x0) +#define TIMER7_CC1_PD1 SILABS_DBUS_TIMER7_CC1(0x3, 0x1) +#define TIMER7_CC1_PD2 SILABS_DBUS_TIMER7_CC1(0x3, 0x2) +#define TIMER7_CC1_PD3 SILABS_DBUS_TIMER7_CC1(0x3, 0x3) +#define TIMER7_CC1_PD4 SILABS_DBUS_TIMER7_CC1(0x3, 0x4) +#define TIMER7_CC1_PD5 SILABS_DBUS_TIMER7_CC1(0x3, 0x5) +#define TIMER7_CC1_PD6 SILABS_DBUS_TIMER7_CC1(0x3, 0x6) +#define TIMER7_CC1_PD7 SILABS_DBUS_TIMER7_CC1(0x3, 0x7) +#define TIMER7_CC1_PD8 SILABS_DBUS_TIMER7_CC1(0x3, 0x8) +#define TIMER7_CC1_PD9 SILABS_DBUS_TIMER7_CC1(0x3, 0x9) +#define TIMER7_CC1_PD10 SILABS_DBUS_TIMER7_CC1(0x3, 0xa) +#define TIMER7_CC1_PD11 SILABS_DBUS_TIMER7_CC1(0x3, 0xb) +#define TIMER7_CC1_PD12 SILABS_DBUS_TIMER7_CC1(0x3, 0xc) +#define TIMER7_CC1_PD13 SILABS_DBUS_TIMER7_CC1(0x3, 0xd) +#define TIMER7_CC1_PD14 SILABS_DBUS_TIMER7_CC1(0x3, 0xe) +#define TIMER7_CC1_PD15 SILABS_DBUS_TIMER7_CC1(0x3, 0xf) +#define TIMER7_CC2_PA0 SILABS_DBUS_TIMER7_CC2(0x0, 0x0) +#define TIMER7_CC2_PA1 SILABS_DBUS_TIMER7_CC2(0x0, 0x1) +#define TIMER7_CC2_PA2 SILABS_DBUS_TIMER7_CC2(0x0, 0x2) +#define TIMER7_CC2_PA3 SILABS_DBUS_TIMER7_CC2(0x0, 0x3) +#define TIMER7_CC2_PA4 SILABS_DBUS_TIMER7_CC2(0x0, 0x4) +#define TIMER7_CC2_PA5 SILABS_DBUS_TIMER7_CC2(0x0, 0x5) +#define TIMER7_CC2_PA6 SILABS_DBUS_TIMER7_CC2(0x0, 0x6) +#define TIMER7_CC2_PA7 SILABS_DBUS_TIMER7_CC2(0x0, 0x7) +#define TIMER7_CC2_PA8 SILABS_DBUS_TIMER7_CC2(0x0, 0x8) +#define TIMER7_CC2_PA9 SILABS_DBUS_TIMER7_CC2(0x0, 0x9) +#define TIMER7_CC2_PA10 SILABS_DBUS_TIMER7_CC2(0x0, 0xa) +#define TIMER7_CC2_PA11 SILABS_DBUS_TIMER7_CC2(0x0, 0xb) +#define TIMER7_CC2_PA12 SILABS_DBUS_TIMER7_CC2(0x0, 0xc) +#define TIMER7_CC2_PA13 SILABS_DBUS_TIMER7_CC2(0x0, 0xd) +#define TIMER7_CC2_PA14 SILABS_DBUS_TIMER7_CC2(0x0, 0xe) +#define TIMER7_CC2_PA15 SILABS_DBUS_TIMER7_CC2(0x0, 0xf) +#define TIMER7_CC2_PB0 SILABS_DBUS_TIMER7_CC2(0x1, 0x0) +#define TIMER7_CC2_PB1 SILABS_DBUS_TIMER7_CC2(0x1, 0x1) +#define TIMER7_CC2_PB2 SILABS_DBUS_TIMER7_CC2(0x1, 0x2) +#define TIMER7_CC2_PB3 SILABS_DBUS_TIMER7_CC2(0x1, 0x3) +#define TIMER7_CC2_PB4 SILABS_DBUS_TIMER7_CC2(0x1, 0x4) +#define TIMER7_CC2_PB5 SILABS_DBUS_TIMER7_CC2(0x1, 0x5) +#define TIMER7_CC2_PB6 SILABS_DBUS_TIMER7_CC2(0x1, 0x6) +#define TIMER7_CC2_PB7 SILABS_DBUS_TIMER7_CC2(0x1, 0x7) +#define TIMER7_CC2_PB8 SILABS_DBUS_TIMER7_CC2(0x1, 0x8) +#define TIMER7_CC2_PB9 SILABS_DBUS_TIMER7_CC2(0x1, 0x9) +#define TIMER7_CC2_PB10 SILABS_DBUS_TIMER7_CC2(0x1, 0xa) +#define TIMER7_CC2_PB11 SILABS_DBUS_TIMER7_CC2(0x1, 0xb) +#define TIMER7_CC2_PB12 SILABS_DBUS_TIMER7_CC2(0x1, 0xc) +#define TIMER7_CC2_PB13 SILABS_DBUS_TIMER7_CC2(0x1, 0xd) +#define TIMER7_CC2_PB14 SILABS_DBUS_TIMER7_CC2(0x1, 0xe) +#define TIMER7_CC2_PB15 SILABS_DBUS_TIMER7_CC2(0x1, 0xf) +#define TIMER7_CC2_PC0 SILABS_DBUS_TIMER7_CC2(0x2, 0x0) +#define TIMER7_CC2_PC1 SILABS_DBUS_TIMER7_CC2(0x2, 0x1) +#define TIMER7_CC2_PC2 SILABS_DBUS_TIMER7_CC2(0x2, 0x2) +#define TIMER7_CC2_PC3 SILABS_DBUS_TIMER7_CC2(0x2, 0x3) +#define TIMER7_CC2_PC4 SILABS_DBUS_TIMER7_CC2(0x2, 0x4) +#define TIMER7_CC2_PC5 SILABS_DBUS_TIMER7_CC2(0x2, 0x5) +#define TIMER7_CC2_PC6 SILABS_DBUS_TIMER7_CC2(0x2, 0x6) +#define TIMER7_CC2_PC7 SILABS_DBUS_TIMER7_CC2(0x2, 0x7) +#define TIMER7_CC2_PC8 SILABS_DBUS_TIMER7_CC2(0x2, 0x8) +#define TIMER7_CC2_PC9 SILABS_DBUS_TIMER7_CC2(0x2, 0x9) +#define TIMER7_CC2_PC10 SILABS_DBUS_TIMER7_CC2(0x2, 0xa) +#define TIMER7_CC2_PC11 SILABS_DBUS_TIMER7_CC2(0x2, 0xb) +#define TIMER7_CC2_PC12 SILABS_DBUS_TIMER7_CC2(0x2, 0xc) +#define TIMER7_CC2_PC13 SILABS_DBUS_TIMER7_CC2(0x2, 0xd) +#define TIMER7_CC2_PC14 SILABS_DBUS_TIMER7_CC2(0x2, 0xe) +#define TIMER7_CC2_PC15 SILABS_DBUS_TIMER7_CC2(0x2, 0xf) +#define TIMER7_CC2_PD0 SILABS_DBUS_TIMER7_CC2(0x3, 0x0) +#define TIMER7_CC2_PD1 SILABS_DBUS_TIMER7_CC2(0x3, 0x1) +#define TIMER7_CC2_PD2 SILABS_DBUS_TIMER7_CC2(0x3, 0x2) +#define TIMER7_CC2_PD3 SILABS_DBUS_TIMER7_CC2(0x3, 0x3) +#define TIMER7_CC2_PD4 SILABS_DBUS_TIMER7_CC2(0x3, 0x4) +#define TIMER7_CC2_PD5 SILABS_DBUS_TIMER7_CC2(0x3, 0x5) +#define TIMER7_CC2_PD6 SILABS_DBUS_TIMER7_CC2(0x3, 0x6) +#define TIMER7_CC2_PD7 SILABS_DBUS_TIMER7_CC2(0x3, 0x7) +#define TIMER7_CC2_PD8 SILABS_DBUS_TIMER7_CC2(0x3, 0x8) +#define TIMER7_CC2_PD9 SILABS_DBUS_TIMER7_CC2(0x3, 0x9) +#define TIMER7_CC2_PD10 SILABS_DBUS_TIMER7_CC2(0x3, 0xa) +#define TIMER7_CC2_PD11 SILABS_DBUS_TIMER7_CC2(0x3, 0xb) +#define TIMER7_CC2_PD12 SILABS_DBUS_TIMER7_CC2(0x3, 0xc) +#define TIMER7_CC2_PD13 SILABS_DBUS_TIMER7_CC2(0x3, 0xd) +#define TIMER7_CC2_PD14 SILABS_DBUS_TIMER7_CC2(0x3, 0xe) +#define TIMER7_CC2_PD15 SILABS_DBUS_TIMER7_CC2(0x3, 0xf) +#define TIMER7_CDTI0_PA0 SILABS_DBUS_TIMER7_CDTI0(0x0, 0x0) +#define TIMER7_CDTI0_PA1 SILABS_DBUS_TIMER7_CDTI0(0x0, 0x1) +#define TIMER7_CDTI0_PA2 SILABS_DBUS_TIMER7_CDTI0(0x0, 0x2) +#define TIMER7_CDTI0_PA3 SILABS_DBUS_TIMER7_CDTI0(0x0, 0x3) +#define TIMER7_CDTI0_PA4 SILABS_DBUS_TIMER7_CDTI0(0x0, 0x4) +#define TIMER7_CDTI0_PA5 SILABS_DBUS_TIMER7_CDTI0(0x0, 0x5) +#define TIMER7_CDTI0_PA6 SILABS_DBUS_TIMER7_CDTI0(0x0, 0x6) +#define TIMER7_CDTI0_PA7 SILABS_DBUS_TIMER7_CDTI0(0x0, 0x7) +#define TIMER7_CDTI0_PA8 SILABS_DBUS_TIMER7_CDTI0(0x0, 0x8) +#define TIMER7_CDTI0_PA9 SILABS_DBUS_TIMER7_CDTI0(0x0, 0x9) +#define TIMER7_CDTI0_PA10 SILABS_DBUS_TIMER7_CDTI0(0x0, 0xa) +#define TIMER7_CDTI0_PA11 SILABS_DBUS_TIMER7_CDTI0(0x0, 0xb) +#define TIMER7_CDTI0_PA12 SILABS_DBUS_TIMER7_CDTI0(0x0, 0xc) +#define TIMER7_CDTI0_PA13 SILABS_DBUS_TIMER7_CDTI0(0x0, 0xd) +#define TIMER7_CDTI0_PA14 SILABS_DBUS_TIMER7_CDTI0(0x0, 0xe) +#define TIMER7_CDTI0_PA15 SILABS_DBUS_TIMER7_CDTI0(0x0, 0xf) +#define TIMER7_CDTI0_PB0 SILABS_DBUS_TIMER7_CDTI0(0x1, 0x0) +#define TIMER7_CDTI0_PB1 SILABS_DBUS_TIMER7_CDTI0(0x1, 0x1) +#define TIMER7_CDTI0_PB2 SILABS_DBUS_TIMER7_CDTI0(0x1, 0x2) +#define TIMER7_CDTI0_PB3 SILABS_DBUS_TIMER7_CDTI0(0x1, 0x3) +#define TIMER7_CDTI0_PB4 SILABS_DBUS_TIMER7_CDTI0(0x1, 0x4) +#define TIMER7_CDTI0_PB5 SILABS_DBUS_TIMER7_CDTI0(0x1, 0x5) +#define TIMER7_CDTI0_PB6 SILABS_DBUS_TIMER7_CDTI0(0x1, 0x6) +#define TIMER7_CDTI0_PB7 SILABS_DBUS_TIMER7_CDTI0(0x1, 0x7) +#define TIMER7_CDTI0_PB8 SILABS_DBUS_TIMER7_CDTI0(0x1, 0x8) +#define TIMER7_CDTI0_PB9 SILABS_DBUS_TIMER7_CDTI0(0x1, 0x9) +#define TIMER7_CDTI0_PB10 SILABS_DBUS_TIMER7_CDTI0(0x1, 0xa) +#define TIMER7_CDTI0_PB11 SILABS_DBUS_TIMER7_CDTI0(0x1, 0xb) +#define TIMER7_CDTI0_PB12 SILABS_DBUS_TIMER7_CDTI0(0x1, 0xc) +#define TIMER7_CDTI0_PB13 SILABS_DBUS_TIMER7_CDTI0(0x1, 0xd) +#define TIMER7_CDTI0_PB14 SILABS_DBUS_TIMER7_CDTI0(0x1, 0xe) +#define TIMER7_CDTI0_PB15 SILABS_DBUS_TIMER7_CDTI0(0x1, 0xf) +#define TIMER7_CDTI0_PC0 SILABS_DBUS_TIMER7_CDTI0(0x2, 0x0) +#define TIMER7_CDTI0_PC1 SILABS_DBUS_TIMER7_CDTI0(0x2, 0x1) +#define TIMER7_CDTI0_PC2 SILABS_DBUS_TIMER7_CDTI0(0x2, 0x2) +#define TIMER7_CDTI0_PC3 SILABS_DBUS_TIMER7_CDTI0(0x2, 0x3) +#define TIMER7_CDTI0_PC4 SILABS_DBUS_TIMER7_CDTI0(0x2, 0x4) +#define TIMER7_CDTI0_PC5 SILABS_DBUS_TIMER7_CDTI0(0x2, 0x5) +#define TIMER7_CDTI0_PC6 SILABS_DBUS_TIMER7_CDTI0(0x2, 0x6) +#define TIMER7_CDTI0_PC7 SILABS_DBUS_TIMER7_CDTI0(0x2, 0x7) +#define TIMER7_CDTI0_PC8 SILABS_DBUS_TIMER7_CDTI0(0x2, 0x8) +#define TIMER7_CDTI0_PC9 SILABS_DBUS_TIMER7_CDTI0(0x2, 0x9) +#define TIMER7_CDTI0_PC10 SILABS_DBUS_TIMER7_CDTI0(0x2, 0xa) +#define TIMER7_CDTI0_PC11 SILABS_DBUS_TIMER7_CDTI0(0x2, 0xb) +#define TIMER7_CDTI0_PC12 SILABS_DBUS_TIMER7_CDTI0(0x2, 0xc) +#define TIMER7_CDTI0_PC13 SILABS_DBUS_TIMER7_CDTI0(0x2, 0xd) +#define TIMER7_CDTI0_PC14 SILABS_DBUS_TIMER7_CDTI0(0x2, 0xe) +#define TIMER7_CDTI0_PC15 SILABS_DBUS_TIMER7_CDTI0(0x2, 0xf) +#define TIMER7_CDTI0_PD0 SILABS_DBUS_TIMER7_CDTI0(0x3, 0x0) +#define TIMER7_CDTI0_PD1 SILABS_DBUS_TIMER7_CDTI0(0x3, 0x1) +#define TIMER7_CDTI0_PD2 SILABS_DBUS_TIMER7_CDTI0(0x3, 0x2) +#define TIMER7_CDTI0_PD3 SILABS_DBUS_TIMER7_CDTI0(0x3, 0x3) +#define TIMER7_CDTI0_PD4 SILABS_DBUS_TIMER7_CDTI0(0x3, 0x4) +#define TIMER7_CDTI0_PD5 SILABS_DBUS_TIMER7_CDTI0(0x3, 0x5) +#define TIMER7_CDTI0_PD6 SILABS_DBUS_TIMER7_CDTI0(0x3, 0x6) +#define TIMER7_CDTI0_PD7 SILABS_DBUS_TIMER7_CDTI0(0x3, 0x7) +#define TIMER7_CDTI0_PD8 SILABS_DBUS_TIMER7_CDTI0(0x3, 0x8) +#define TIMER7_CDTI0_PD9 SILABS_DBUS_TIMER7_CDTI0(0x3, 0x9) +#define TIMER7_CDTI0_PD10 SILABS_DBUS_TIMER7_CDTI0(0x3, 0xa) +#define TIMER7_CDTI0_PD11 SILABS_DBUS_TIMER7_CDTI0(0x3, 0xb) +#define TIMER7_CDTI0_PD12 SILABS_DBUS_TIMER7_CDTI0(0x3, 0xc) +#define TIMER7_CDTI0_PD13 SILABS_DBUS_TIMER7_CDTI0(0x3, 0xd) +#define TIMER7_CDTI0_PD14 SILABS_DBUS_TIMER7_CDTI0(0x3, 0xe) +#define TIMER7_CDTI0_PD15 SILABS_DBUS_TIMER7_CDTI0(0x3, 0xf) +#define TIMER7_CDTI1_PA0 SILABS_DBUS_TIMER7_CDTI1(0x0, 0x0) +#define TIMER7_CDTI1_PA1 SILABS_DBUS_TIMER7_CDTI1(0x0, 0x1) +#define TIMER7_CDTI1_PA2 SILABS_DBUS_TIMER7_CDTI1(0x0, 0x2) +#define TIMER7_CDTI1_PA3 SILABS_DBUS_TIMER7_CDTI1(0x0, 0x3) +#define TIMER7_CDTI1_PA4 SILABS_DBUS_TIMER7_CDTI1(0x0, 0x4) +#define TIMER7_CDTI1_PA5 SILABS_DBUS_TIMER7_CDTI1(0x0, 0x5) +#define TIMER7_CDTI1_PA6 SILABS_DBUS_TIMER7_CDTI1(0x0, 0x6) +#define TIMER7_CDTI1_PA7 SILABS_DBUS_TIMER7_CDTI1(0x0, 0x7) +#define TIMER7_CDTI1_PA8 SILABS_DBUS_TIMER7_CDTI1(0x0, 0x8) +#define TIMER7_CDTI1_PA9 SILABS_DBUS_TIMER7_CDTI1(0x0, 0x9) +#define TIMER7_CDTI1_PA10 SILABS_DBUS_TIMER7_CDTI1(0x0, 0xa) +#define TIMER7_CDTI1_PA11 SILABS_DBUS_TIMER7_CDTI1(0x0, 0xb) +#define TIMER7_CDTI1_PA12 SILABS_DBUS_TIMER7_CDTI1(0x0, 0xc) +#define TIMER7_CDTI1_PA13 SILABS_DBUS_TIMER7_CDTI1(0x0, 0xd) +#define TIMER7_CDTI1_PA14 SILABS_DBUS_TIMER7_CDTI1(0x0, 0xe) +#define TIMER7_CDTI1_PA15 SILABS_DBUS_TIMER7_CDTI1(0x0, 0xf) +#define TIMER7_CDTI1_PB0 SILABS_DBUS_TIMER7_CDTI1(0x1, 0x0) +#define TIMER7_CDTI1_PB1 SILABS_DBUS_TIMER7_CDTI1(0x1, 0x1) +#define TIMER7_CDTI1_PB2 SILABS_DBUS_TIMER7_CDTI1(0x1, 0x2) +#define TIMER7_CDTI1_PB3 SILABS_DBUS_TIMER7_CDTI1(0x1, 0x3) +#define TIMER7_CDTI1_PB4 SILABS_DBUS_TIMER7_CDTI1(0x1, 0x4) +#define TIMER7_CDTI1_PB5 SILABS_DBUS_TIMER7_CDTI1(0x1, 0x5) +#define TIMER7_CDTI1_PB6 SILABS_DBUS_TIMER7_CDTI1(0x1, 0x6) +#define TIMER7_CDTI1_PB7 SILABS_DBUS_TIMER7_CDTI1(0x1, 0x7) +#define TIMER7_CDTI1_PB8 SILABS_DBUS_TIMER7_CDTI1(0x1, 0x8) +#define TIMER7_CDTI1_PB9 SILABS_DBUS_TIMER7_CDTI1(0x1, 0x9) +#define TIMER7_CDTI1_PB10 SILABS_DBUS_TIMER7_CDTI1(0x1, 0xa) +#define TIMER7_CDTI1_PB11 SILABS_DBUS_TIMER7_CDTI1(0x1, 0xb) +#define TIMER7_CDTI1_PB12 SILABS_DBUS_TIMER7_CDTI1(0x1, 0xc) +#define TIMER7_CDTI1_PB13 SILABS_DBUS_TIMER7_CDTI1(0x1, 0xd) +#define TIMER7_CDTI1_PB14 SILABS_DBUS_TIMER7_CDTI1(0x1, 0xe) +#define TIMER7_CDTI1_PB15 SILABS_DBUS_TIMER7_CDTI1(0x1, 0xf) +#define TIMER7_CDTI1_PC0 SILABS_DBUS_TIMER7_CDTI1(0x2, 0x0) +#define TIMER7_CDTI1_PC1 SILABS_DBUS_TIMER7_CDTI1(0x2, 0x1) +#define TIMER7_CDTI1_PC2 SILABS_DBUS_TIMER7_CDTI1(0x2, 0x2) +#define TIMER7_CDTI1_PC3 SILABS_DBUS_TIMER7_CDTI1(0x2, 0x3) +#define TIMER7_CDTI1_PC4 SILABS_DBUS_TIMER7_CDTI1(0x2, 0x4) +#define TIMER7_CDTI1_PC5 SILABS_DBUS_TIMER7_CDTI1(0x2, 0x5) +#define TIMER7_CDTI1_PC6 SILABS_DBUS_TIMER7_CDTI1(0x2, 0x6) +#define TIMER7_CDTI1_PC7 SILABS_DBUS_TIMER7_CDTI1(0x2, 0x7) +#define TIMER7_CDTI1_PC8 SILABS_DBUS_TIMER7_CDTI1(0x2, 0x8) +#define TIMER7_CDTI1_PC9 SILABS_DBUS_TIMER7_CDTI1(0x2, 0x9) +#define TIMER7_CDTI1_PC10 SILABS_DBUS_TIMER7_CDTI1(0x2, 0xa) +#define TIMER7_CDTI1_PC11 SILABS_DBUS_TIMER7_CDTI1(0x2, 0xb) +#define TIMER7_CDTI1_PC12 SILABS_DBUS_TIMER7_CDTI1(0x2, 0xc) +#define TIMER7_CDTI1_PC13 SILABS_DBUS_TIMER7_CDTI1(0x2, 0xd) +#define TIMER7_CDTI1_PC14 SILABS_DBUS_TIMER7_CDTI1(0x2, 0xe) +#define TIMER7_CDTI1_PC15 SILABS_DBUS_TIMER7_CDTI1(0x2, 0xf) +#define TIMER7_CDTI1_PD0 SILABS_DBUS_TIMER7_CDTI1(0x3, 0x0) +#define TIMER7_CDTI1_PD1 SILABS_DBUS_TIMER7_CDTI1(0x3, 0x1) +#define TIMER7_CDTI1_PD2 SILABS_DBUS_TIMER7_CDTI1(0x3, 0x2) +#define TIMER7_CDTI1_PD3 SILABS_DBUS_TIMER7_CDTI1(0x3, 0x3) +#define TIMER7_CDTI1_PD4 SILABS_DBUS_TIMER7_CDTI1(0x3, 0x4) +#define TIMER7_CDTI1_PD5 SILABS_DBUS_TIMER7_CDTI1(0x3, 0x5) +#define TIMER7_CDTI1_PD6 SILABS_DBUS_TIMER7_CDTI1(0x3, 0x6) +#define TIMER7_CDTI1_PD7 SILABS_DBUS_TIMER7_CDTI1(0x3, 0x7) +#define TIMER7_CDTI1_PD8 SILABS_DBUS_TIMER7_CDTI1(0x3, 0x8) +#define TIMER7_CDTI1_PD9 SILABS_DBUS_TIMER7_CDTI1(0x3, 0x9) +#define TIMER7_CDTI1_PD10 SILABS_DBUS_TIMER7_CDTI1(0x3, 0xa) +#define TIMER7_CDTI1_PD11 SILABS_DBUS_TIMER7_CDTI1(0x3, 0xb) +#define TIMER7_CDTI1_PD12 SILABS_DBUS_TIMER7_CDTI1(0x3, 0xc) +#define TIMER7_CDTI1_PD13 SILABS_DBUS_TIMER7_CDTI1(0x3, 0xd) +#define TIMER7_CDTI1_PD14 SILABS_DBUS_TIMER7_CDTI1(0x3, 0xe) +#define TIMER7_CDTI1_PD15 SILABS_DBUS_TIMER7_CDTI1(0x3, 0xf) +#define TIMER7_CDTI2_PA0 SILABS_DBUS_TIMER7_CDTI2(0x0, 0x0) +#define TIMER7_CDTI2_PA1 SILABS_DBUS_TIMER7_CDTI2(0x0, 0x1) +#define TIMER7_CDTI2_PA2 SILABS_DBUS_TIMER7_CDTI2(0x0, 0x2) +#define TIMER7_CDTI2_PA3 SILABS_DBUS_TIMER7_CDTI2(0x0, 0x3) +#define TIMER7_CDTI2_PA4 SILABS_DBUS_TIMER7_CDTI2(0x0, 0x4) +#define TIMER7_CDTI2_PA5 SILABS_DBUS_TIMER7_CDTI2(0x0, 0x5) +#define TIMER7_CDTI2_PA6 SILABS_DBUS_TIMER7_CDTI2(0x0, 0x6) +#define TIMER7_CDTI2_PA7 SILABS_DBUS_TIMER7_CDTI2(0x0, 0x7) +#define TIMER7_CDTI2_PA8 SILABS_DBUS_TIMER7_CDTI2(0x0, 0x8) +#define TIMER7_CDTI2_PA9 SILABS_DBUS_TIMER7_CDTI2(0x0, 0x9) +#define TIMER7_CDTI2_PA10 SILABS_DBUS_TIMER7_CDTI2(0x0, 0xa) +#define TIMER7_CDTI2_PA11 SILABS_DBUS_TIMER7_CDTI2(0x0, 0xb) +#define TIMER7_CDTI2_PA12 SILABS_DBUS_TIMER7_CDTI2(0x0, 0xc) +#define TIMER7_CDTI2_PA13 SILABS_DBUS_TIMER7_CDTI2(0x0, 0xd) +#define TIMER7_CDTI2_PA14 SILABS_DBUS_TIMER7_CDTI2(0x0, 0xe) +#define TIMER7_CDTI2_PA15 SILABS_DBUS_TIMER7_CDTI2(0x0, 0xf) +#define TIMER7_CDTI2_PB0 SILABS_DBUS_TIMER7_CDTI2(0x1, 0x0) +#define TIMER7_CDTI2_PB1 SILABS_DBUS_TIMER7_CDTI2(0x1, 0x1) +#define TIMER7_CDTI2_PB2 SILABS_DBUS_TIMER7_CDTI2(0x1, 0x2) +#define TIMER7_CDTI2_PB3 SILABS_DBUS_TIMER7_CDTI2(0x1, 0x3) +#define TIMER7_CDTI2_PB4 SILABS_DBUS_TIMER7_CDTI2(0x1, 0x4) +#define TIMER7_CDTI2_PB5 SILABS_DBUS_TIMER7_CDTI2(0x1, 0x5) +#define TIMER7_CDTI2_PB6 SILABS_DBUS_TIMER7_CDTI2(0x1, 0x6) +#define TIMER7_CDTI2_PB7 SILABS_DBUS_TIMER7_CDTI2(0x1, 0x7) +#define TIMER7_CDTI2_PB8 SILABS_DBUS_TIMER7_CDTI2(0x1, 0x8) +#define TIMER7_CDTI2_PB9 SILABS_DBUS_TIMER7_CDTI2(0x1, 0x9) +#define TIMER7_CDTI2_PB10 SILABS_DBUS_TIMER7_CDTI2(0x1, 0xa) +#define TIMER7_CDTI2_PB11 SILABS_DBUS_TIMER7_CDTI2(0x1, 0xb) +#define TIMER7_CDTI2_PB12 SILABS_DBUS_TIMER7_CDTI2(0x1, 0xc) +#define TIMER7_CDTI2_PB13 SILABS_DBUS_TIMER7_CDTI2(0x1, 0xd) +#define TIMER7_CDTI2_PB14 SILABS_DBUS_TIMER7_CDTI2(0x1, 0xe) +#define TIMER7_CDTI2_PB15 SILABS_DBUS_TIMER7_CDTI2(0x1, 0xf) +#define TIMER7_CDTI2_PC0 SILABS_DBUS_TIMER7_CDTI2(0x2, 0x0) +#define TIMER7_CDTI2_PC1 SILABS_DBUS_TIMER7_CDTI2(0x2, 0x1) +#define TIMER7_CDTI2_PC2 SILABS_DBUS_TIMER7_CDTI2(0x2, 0x2) +#define TIMER7_CDTI2_PC3 SILABS_DBUS_TIMER7_CDTI2(0x2, 0x3) +#define TIMER7_CDTI2_PC4 SILABS_DBUS_TIMER7_CDTI2(0x2, 0x4) +#define TIMER7_CDTI2_PC5 SILABS_DBUS_TIMER7_CDTI2(0x2, 0x5) +#define TIMER7_CDTI2_PC6 SILABS_DBUS_TIMER7_CDTI2(0x2, 0x6) +#define TIMER7_CDTI2_PC7 SILABS_DBUS_TIMER7_CDTI2(0x2, 0x7) +#define TIMER7_CDTI2_PC8 SILABS_DBUS_TIMER7_CDTI2(0x2, 0x8) +#define TIMER7_CDTI2_PC9 SILABS_DBUS_TIMER7_CDTI2(0x2, 0x9) +#define TIMER7_CDTI2_PC10 SILABS_DBUS_TIMER7_CDTI2(0x2, 0xa) +#define TIMER7_CDTI2_PC11 SILABS_DBUS_TIMER7_CDTI2(0x2, 0xb) +#define TIMER7_CDTI2_PC12 SILABS_DBUS_TIMER7_CDTI2(0x2, 0xc) +#define TIMER7_CDTI2_PC13 SILABS_DBUS_TIMER7_CDTI2(0x2, 0xd) +#define TIMER7_CDTI2_PC14 SILABS_DBUS_TIMER7_CDTI2(0x2, 0xe) +#define TIMER7_CDTI2_PC15 SILABS_DBUS_TIMER7_CDTI2(0x2, 0xf) +#define TIMER7_CDTI2_PD0 SILABS_DBUS_TIMER7_CDTI2(0x3, 0x0) +#define TIMER7_CDTI2_PD1 SILABS_DBUS_TIMER7_CDTI2(0x3, 0x1) +#define TIMER7_CDTI2_PD2 SILABS_DBUS_TIMER7_CDTI2(0x3, 0x2) +#define TIMER7_CDTI2_PD3 SILABS_DBUS_TIMER7_CDTI2(0x3, 0x3) +#define TIMER7_CDTI2_PD4 SILABS_DBUS_TIMER7_CDTI2(0x3, 0x4) +#define TIMER7_CDTI2_PD5 SILABS_DBUS_TIMER7_CDTI2(0x3, 0x5) +#define TIMER7_CDTI2_PD6 SILABS_DBUS_TIMER7_CDTI2(0x3, 0x6) +#define TIMER7_CDTI2_PD7 SILABS_DBUS_TIMER7_CDTI2(0x3, 0x7) +#define TIMER7_CDTI2_PD8 SILABS_DBUS_TIMER7_CDTI2(0x3, 0x8) +#define TIMER7_CDTI2_PD9 SILABS_DBUS_TIMER7_CDTI2(0x3, 0x9) +#define TIMER7_CDTI2_PD10 SILABS_DBUS_TIMER7_CDTI2(0x3, 0xa) +#define TIMER7_CDTI2_PD11 SILABS_DBUS_TIMER7_CDTI2(0x3, 0xb) +#define TIMER7_CDTI2_PD12 SILABS_DBUS_TIMER7_CDTI2(0x3, 0xc) +#define TIMER7_CDTI2_PD13 SILABS_DBUS_TIMER7_CDTI2(0x3, 0xd) +#define TIMER7_CDTI2_PD14 SILABS_DBUS_TIMER7_CDTI2(0x3, 0xe) +#define TIMER7_CDTI2_PD15 SILABS_DBUS_TIMER7_CDTI2(0x3, 0xf) + +#define TIMER8_CC0_PA0 SILABS_DBUS_TIMER8_CC0(0x0, 0x0) +#define TIMER8_CC0_PA1 SILABS_DBUS_TIMER8_CC0(0x0, 0x1) +#define TIMER8_CC0_PA2 SILABS_DBUS_TIMER8_CC0(0x0, 0x2) +#define TIMER8_CC0_PA3 SILABS_DBUS_TIMER8_CC0(0x0, 0x3) +#define TIMER8_CC0_PA4 SILABS_DBUS_TIMER8_CC0(0x0, 0x4) +#define TIMER8_CC0_PA5 SILABS_DBUS_TIMER8_CC0(0x0, 0x5) +#define TIMER8_CC0_PA6 SILABS_DBUS_TIMER8_CC0(0x0, 0x6) +#define TIMER8_CC0_PA7 SILABS_DBUS_TIMER8_CC0(0x0, 0x7) +#define TIMER8_CC0_PA8 SILABS_DBUS_TIMER8_CC0(0x0, 0x8) +#define TIMER8_CC0_PA9 SILABS_DBUS_TIMER8_CC0(0x0, 0x9) +#define TIMER8_CC0_PA10 SILABS_DBUS_TIMER8_CC0(0x0, 0xa) +#define TIMER8_CC0_PA11 SILABS_DBUS_TIMER8_CC0(0x0, 0xb) +#define TIMER8_CC0_PA12 SILABS_DBUS_TIMER8_CC0(0x0, 0xc) +#define TIMER8_CC0_PA13 SILABS_DBUS_TIMER8_CC0(0x0, 0xd) +#define TIMER8_CC0_PA14 SILABS_DBUS_TIMER8_CC0(0x0, 0xe) +#define TIMER8_CC0_PA15 SILABS_DBUS_TIMER8_CC0(0x0, 0xf) +#define TIMER8_CC0_PB0 SILABS_DBUS_TIMER8_CC0(0x1, 0x0) +#define TIMER8_CC0_PB1 SILABS_DBUS_TIMER8_CC0(0x1, 0x1) +#define TIMER8_CC0_PB2 SILABS_DBUS_TIMER8_CC0(0x1, 0x2) +#define TIMER8_CC0_PB3 SILABS_DBUS_TIMER8_CC0(0x1, 0x3) +#define TIMER8_CC0_PB4 SILABS_DBUS_TIMER8_CC0(0x1, 0x4) +#define TIMER8_CC0_PB5 SILABS_DBUS_TIMER8_CC0(0x1, 0x5) +#define TIMER8_CC0_PB6 SILABS_DBUS_TIMER8_CC0(0x1, 0x6) +#define TIMER8_CC0_PB7 SILABS_DBUS_TIMER8_CC0(0x1, 0x7) +#define TIMER8_CC0_PB8 SILABS_DBUS_TIMER8_CC0(0x1, 0x8) +#define TIMER8_CC0_PB9 SILABS_DBUS_TIMER8_CC0(0x1, 0x9) +#define TIMER8_CC0_PB10 SILABS_DBUS_TIMER8_CC0(0x1, 0xa) +#define TIMER8_CC0_PB11 SILABS_DBUS_TIMER8_CC0(0x1, 0xb) +#define TIMER8_CC0_PB12 SILABS_DBUS_TIMER8_CC0(0x1, 0xc) +#define TIMER8_CC0_PB13 SILABS_DBUS_TIMER8_CC0(0x1, 0xd) +#define TIMER8_CC0_PB14 SILABS_DBUS_TIMER8_CC0(0x1, 0xe) +#define TIMER8_CC0_PB15 SILABS_DBUS_TIMER8_CC0(0x1, 0xf) +#define TIMER8_CC0_PC0 SILABS_DBUS_TIMER8_CC0(0x2, 0x0) +#define TIMER8_CC0_PC1 SILABS_DBUS_TIMER8_CC0(0x2, 0x1) +#define TIMER8_CC0_PC2 SILABS_DBUS_TIMER8_CC0(0x2, 0x2) +#define TIMER8_CC0_PC3 SILABS_DBUS_TIMER8_CC0(0x2, 0x3) +#define TIMER8_CC0_PC4 SILABS_DBUS_TIMER8_CC0(0x2, 0x4) +#define TIMER8_CC0_PC5 SILABS_DBUS_TIMER8_CC0(0x2, 0x5) +#define TIMER8_CC0_PC6 SILABS_DBUS_TIMER8_CC0(0x2, 0x6) +#define TIMER8_CC0_PC7 SILABS_DBUS_TIMER8_CC0(0x2, 0x7) +#define TIMER8_CC0_PC8 SILABS_DBUS_TIMER8_CC0(0x2, 0x8) +#define TIMER8_CC0_PC9 SILABS_DBUS_TIMER8_CC0(0x2, 0x9) +#define TIMER8_CC0_PC10 SILABS_DBUS_TIMER8_CC0(0x2, 0xa) +#define TIMER8_CC0_PC11 SILABS_DBUS_TIMER8_CC0(0x2, 0xb) +#define TIMER8_CC0_PC12 SILABS_DBUS_TIMER8_CC0(0x2, 0xc) +#define TIMER8_CC0_PC13 SILABS_DBUS_TIMER8_CC0(0x2, 0xd) +#define TIMER8_CC0_PC14 SILABS_DBUS_TIMER8_CC0(0x2, 0xe) +#define TIMER8_CC0_PC15 SILABS_DBUS_TIMER8_CC0(0x2, 0xf) +#define TIMER8_CC0_PD0 SILABS_DBUS_TIMER8_CC0(0x3, 0x0) +#define TIMER8_CC0_PD1 SILABS_DBUS_TIMER8_CC0(0x3, 0x1) +#define TIMER8_CC0_PD2 SILABS_DBUS_TIMER8_CC0(0x3, 0x2) +#define TIMER8_CC0_PD3 SILABS_DBUS_TIMER8_CC0(0x3, 0x3) +#define TIMER8_CC0_PD4 SILABS_DBUS_TIMER8_CC0(0x3, 0x4) +#define TIMER8_CC0_PD5 SILABS_DBUS_TIMER8_CC0(0x3, 0x5) +#define TIMER8_CC0_PD6 SILABS_DBUS_TIMER8_CC0(0x3, 0x6) +#define TIMER8_CC0_PD7 SILABS_DBUS_TIMER8_CC0(0x3, 0x7) +#define TIMER8_CC0_PD8 SILABS_DBUS_TIMER8_CC0(0x3, 0x8) +#define TIMER8_CC0_PD9 SILABS_DBUS_TIMER8_CC0(0x3, 0x9) +#define TIMER8_CC0_PD10 SILABS_DBUS_TIMER8_CC0(0x3, 0xa) +#define TIMER8_CC0_PD11 SILABS_DBUS_TIMER8_CC0(0x3, 0xb) +#define TIMER8_CC0_PD12 SILABS_DBUS_TIMER8_CC0(0x3, 0xc) +#define TIMER8_CC0_PD13 SILABS_DBUS_TIMER8_CC0(0x3, 0xd) +#define TIMER8_CC0_PD14 SILABS_DBUS_TIMER8_CC0(0x3, 0xe) +#define TIMER8_CC0_PD15 SILABS_DBUS_TIMER8_CC0(0x3, 0xf) +#define TIMER8_CC1_PA0 SILABS_DBUS_TIMER8_CC1(0x0, 0x0) +#define TIMER8_CC1_PA1 SILABS_DBUS_TIMER8_CC1(0x0, 0x1) +#define TIMER8_CC1_PA2 SILABS_DBUS_TIMER8_CC1(0x0, 0x2) +#define TIMER8_CC1_PA3 SILABS_DBUS_TIMER8_CC1(0x0, 0x3) +#define TIMER8_CC1_PA4 SILABS_DBUS_TIMER8_CC1(0x0, 0x4) +#define TIMER8_CC1_PA5 SILABS_DBUS_TIMER8_CC1(0x0, 0x5) +#define TIMER8_CC1_PA6 SILABS_DBUS_TIMER8_CC1(0x0, 0x6) +#define TIMER8_CC1_PA7 SILABS_DBUS_TIMER8_CC1(0x0, 0x7) +#define TIMER8_CC1_PA8 SILABS_DBUS_TIMER8_CC1(0x0, 0x8) +#define TIMER8_CC1_PA9 SILABS_DBUS_TIMER8_CC1(0x0, 0x9) +#define TIMER8_CC1_PA10 SILABS_DBUS_TIMER8_CC1(0x0, 0xa) +#define TIMER8_CC1_PA11 SILABS_DBUS_TIMER8_CC1(0x0, 0xb) +#define TIMER8_CC1_PA12 SILABS_DBUS_TIMER8_CC1(0x0, 0xc) +#define TIMER8_CC1_PA13 SILABS_DBUS_TIMER8_CC1(0x0, 0xd) +#define TIMER8_CC1_PA14 SILABS_DBUS_TIMER8_CC1(0x0, 0xe) +#define TIMER8_CC1_PA15 SILABS_DBUS_TIMER8_CC1(0x0, 0xf) +#define TIMER8_CC1_PB0 SILABS_DBUS_TIMER8_CC1(0x1, 0x0) +#define TIMER8_CC1_PB1 SILABS_DBUS_TIMER8_CC1(0x1, 0x1) +#define TIMER8_CC1_PB2 SILABS_DBUS_TIMER8_CC1(0x1, 0x2) +#define TIMER8_CC1_PB3 SILABS_DBUS_TIMER8_CC1(0x1, 0x3) +#define TIMER8_CC1_PB4 SILABS_DBUS_TIMER8_CC1(0x1, 0x4) +#define TIMER8_CC1_PB5 SILABS_DBUS_TIMER8_CC1(0x1, 0x5) +#define TIMER8_CC1_PB6 SILABS_DBUS_TIMER8_CC1(0x1, 0x6) +#define TIMER8_CC1_PB7 SILABS_DBUS_TIMER8_CC1(0x1, 0x7) +#define TIMER8_CC1_PB8 SILABS_DBUS_TIMER8_CC1(0x1, 0x8) +#define TIMER8_CC1_PB9 SILABS_DBUS_TIMER8_CC1(0x1, 0x9) +#define TIMER8_CC1_PB10 SILABS_DBUS_TIMER8_CC1(0x1, 0xa) +#define TIMER8_CC1_PB11 SILABS_DBUS_TIMER8_CC1(0x1, 0xb) +#define TIMER8_CC1_PB12 SILABS_DBUS_TIMER8_CC1(0x1, 0xc) +#define TIMER8_CC1_PB13 SILABS_DBUS_TIMER8_CC1(0x1, 0xd) +#define TIMER8_CC1_PB14 SILABS_DBUS_TIMER8_CC1(0x1, 0xe) +#define TIMER8_CC1_PB15 SILABS_DBUS_TIMER8_CC1(0x1, 0xf) +#define TIMER8_CC1_PC0 SILABS_DBUS_TIMER8_CC1(0x2, 0x0) +#define TIMER8_CC1_PC1 SILABS_DBUS_TIMER8_CC1(0x2, 0x1) +#define TIMER8_CC1_PC2 SILABS_DBUS_TIMER8_CC1(0x2, 0x2) +#define TIMER8_CC1_PC3 SILABS_DBUS_TIMER8_CC1(0x2, 0x3) +#define TIMER8_CC1_PC4 SILABS_DBUS_TIMER8_CC1(0x2, 0x4) +#define TIMER8_CC1_PC5 SILABS_DBUS_TIMER8_CC1(0x2, 0x5) +#define TIMER8_CC1_PC6 SILABS_DBUS_TIMER8_CC1(0x2, 0x6) +#define TIMER8_CC1_PC7 SILABS_DBUS_TIMER8_CC1(0x2, 0x7) +#define TIMER8_CC1_PC8 SILABS_DBUS_TIMER8_CC1(0x2, 0x8) +#define TIMER8_CC1_PC9 SILABS_DBUS_TIMER8_CC1(0x2, 0x9) +#define TIMER8_CC1_PC10 SILABS_DBUS_TIMER8_CC1(0x2, 0xa) +#define TIMER8_CC1_PC11 SILABS_DBUS_TIMER8_CC1(0x2, 0xb) +#define TIMER8_CC1_PC12 SILABS_DBUS_TIMER8_CC1(0x2, 0xc) +#define TIMER8_CC1_PC13 SILABS_DBUS_TIMER8_CC1(0x2, 0xd) +#define TIMER8_CC1_PC14 SILABS_DBUS_TIMER8_CC1(0x2, 0xe) +#define TIMER8_CC1_PC15 SILABS_DBUS_TIMER8_CC1(0x2, 0xf) +#define TIMER8_CC1_PD0 SILABS_DBUS_TIMER8_CC1(0x3, 0x0) +#define TIMER8_CC1_PD1 SILABS_DBUS_TIMER8_CC1(0x3, 0x1) +#define TIMER8_CC1_PD2 SILABS_DBUS_TIMER8_CC1(0x3, 0x2) +#define TIMER8_CC1_PD3 SILABS_DBUS_TIMER8_CC1(0x3, 0x3) +#define TIMER8_CC1_PD4 SILABS_DBUS_TIMER8_CC1(0x3, 0x4) +#define TIMER8_CC1_PD5 SILABS_DBUS_TIMER8_CC1(0x3, 0x5) +#define TIMER8_CC1_PD6 SILABS_DBUS_TIMER8_CC1(0x3, 0x6) +#define TIMER8_CC1_PD7 SILABS_DBUS_TIMER8_CC1(0x3, 0x7) +#define TIMER8_CC1_PD8 SILABS_DBUS_TIMER8_CC1(0x3, 0x8) +#define TIMER8_CC1_PD9 SILABS_DBUS_TIMER8_CC1(0x3, 0x9) +#define TIMER8_CC1_PD10 SILABS_DBUS_TIMER8_CC1(0x3, 0xa) +#define TIMER8_CC1_PD11 SILABS_DBUS_TIMER8_CC1(0x3, 0xb) +#define TIMER8_CC1_PD12 SILABS_DBUS_TIMER8_CC1(0x3, 0xc) +#define TIMER8_CC1_PD13 SILABS_DBUS_TIMER8_CC1(0x3, 0xd) +#define TIMER8_CC1_PD14 SILABS_DBUS_TIMER8_CC1(0x3, 0xe) +#define TIMER8_CC1_PD15 SILABS_DBUS_TIMER8_CC1(0x3, 0xf) +#define TIMER8_CC2_PA0 SILABS_DBUS_TIMER8_CC2(0x0, 0x0) +#define TIMER8_CC2_PA1 SILABS_DBUS_TIMER8_CC2(0x0, 0x1) +#define TIMER8_CC2_PA2 SILABS_DBUS_TIMER8_CC2(0x0, 0x2) +#define TIMER8_CC2_PA3 SILABS_DBUS_TIMER8_CC2(0x0, 0x3) +#define TIMER8_CC2_PA4 SILABS_DBUS_TIMER8_CC2(0x0, 0x4) +#define TIMER8_CC2_PA5 SILABS_DBUS_TIMER8_CC2(0x0, 0x5) +#define TIMER8_CC2_PA6 SILABS_DBUS_TIMER8_CC2(0x0, 0x6) +#define TIMER8_CC2_PA7 SILABS_DBUS_TIMER8_CC2(0x0, 0x7) +#define TIMER8_CC2_PA8 SILABS_DBUS_TIMER8_CC2(0x0, 0x8) +#define TIMER8_CC2_PA9 SILABS_DBUS_TIMER8_CC2(0x0, 0x9) +#define TIMER8_CC2_PA10 SILABS_DBUS_TIMER8_CC2(0x0, 0xa) +#define TIMER8_CC2_PA11 SILABS_DBUS_TIMER8_CC2(0x0, 0xb) +#define TIMER8_CC2_PA12 SILABS_DBUS_TIMER8_CC2(0x0, 0xc) +#define TIMER8_CC2_PA13 SILABS_DBUS_TIMER8_CC2(0x0, 0xd) +#define TIMER8_CC2_PA14 SILABS_DBUS_TIMER8_CC2(0x0, 0xe) +#define TIMER8_CC2_PA15 SILABS_DBUS_TIMER8_CC2(0x0, 0xf) +#define TIMER8_CC2_PB0 SILABS_DBUS_TIMER8_CC2(0x1, 0x0) +#define TIMER8_CC2_PB1 SILABS_DBUS_TIMER8_CC2(0x1, 0x1) +#define TIMER8_CC2_PB2 SILABS_DBUS_TIMER8_CC2(0x1, 0x2) +#define TIMER8_CC2_PB3 SILABS_DBUS_TIMER8_CC2(0x1, 0x3) +#define TIMER8_CC2_PB4 SILABS_DBUS_TIMER8_CC2(0x1, 0x4) +#define TIMER8_CC2_PB5 SILABS_DBUS_TIMER8_CC2(0x1, 0x5) +#define TIMER8_CC2_PB6 SILABS_DBUS_TIMER8_CC2(0x1, 0x6) +#define TIMER8_CC2_PB7 SILABS_DBUS_TIMER8_CC2(0x1, 0x7) +#define TIMER8_CC2_PB8 SILABS_DBUS_TIMER8_CC2(0x1, 0x8) +#define TIMER8_CC2_PB9 SILABS_DBUS_TIMER8_CC2(0x1, 0x9) +#define TIMER8_CC2_PB10 SILABS_DBUS_TIMER8_CC2(0x1, 0xa) +#define TIMER8_CC2_PB11 SILABS_DBUS_TIMER8_CC2(0x1, 0xb) +#define TIMER8_CC2_PB12 SILABS_DBUS_TIMER8_CC2(0x1, 0xc) +#define TIMER8_CC2_PB13 SILABS_DBUS_TIMER8_CC2(0x1, 0xd) +#define TIMER8_CC2_PB14 SILABS_DBUS_TIMER8_CC2(0x1, 0xe) +#define TIMER8_CC2_PB15 SILABS_DBUS_TIMER8_CC2(0x1, 0xf) +#define TIMER8_CC2_PC0 SILABS_DBUS_TIMER8_CC2(0x2, 0x0) +#define TIMER8_CC2_PC1 SILABS_DBUS_TIMER8_CC2(0x2, 0x1) +#define TIMER8_CC2_PC2 SILABS_DBUS_TIMER8_CC2(0x2, 0x2) +#define TIMER8_CC2_PC3 SILABS_DBUS_TIMER8_CC2(0x2, 0x3) +#define TIMER8_CC2_PC4 SILABS_DBUS_TIMER8_CC2(0x2, 0x4) +#define TIMER8_CC2_PC5 SILABS_DBUS_TIMER8_CC2(0x2, 0x5) +#define TIMER8_CC2_PC6 SILABS_DBUS_TIMER8_CC2(0x2, 0x6) +#define TIMER8_CC2_PC7 SILABS_DBUS_TIMER8_CC2(0x2, 0x7) +#define TIMER8_CC2_PC8 SILABS_DBUS_TIMER8_CC2(0x2, 0x8) +#define TIMER8_CC2_PC9 SILABS_DBUS_TIMER8_CC2(0x2, 0x9) +#define TIMER8_CC2_PC10 SILABS_DBUS_TIMER8_CC2(0x2, 0xa) +#define TIMER8_CC2_PC11 SILABS_DBUS_TIMER8_CC2(0x2, 0xb) +#define TIMER8_CC2_PC12 SILABS_DBUS_TIMER8_CC2(0x2, 0xc) +#define TIMER8_CC2_PC13 SILABS_DBUS_TIMER8_CC2(0x2, 0xd) +#define TIMER8_CC2_PC14 SILABS_DBUS_TIMER8_CC2(0x2, 0xe) +#define TIMER8_CC2_PC15 SILABS_DBUS_TIMER8_CC2(0x2, 0xf) +#define TIMER8_CC2_PD0 SILABS_DBUS_TIMER8_CC2(0x3, 0x0) +#define TIMER8_CC2_PD1 SILABS_DBUS_TIMER8_CC2(0x3, 0x1) +#define TIMER8_CC2_PD2 SILABS_DBUS_TIMER8_CC2(0x3, 0x2) +#define TIMER8_CC2_PD3 SILABS_DBUS_TIMER8_CC2(0x3, 0x3) +#define TIMER8_CC2_PD4 SILABS_DBUS_TIMER8_CC2(0x3, 0x4) +#define TIMER8_CC2_PD5 SILABS_DBUS_TIMER8_CC2(0x3, 0x5) +#define TIMER8_CC2_PD6 SILABS_DBUS_TIMER8_CC2(0x3, 0x6) +#define TIMER8_CC2_PD7 SILABS_DBUS_TIMER8_CC2(0x3, 0x7) +#define TIMER8_CC2_PD8 SILABS_DBUS_TIMER8_CC2(0x3, 0x8) +#define TIMER8_CC2_PD9 SILABS_DBUS_TIMER8_CC2(0x3, 0x9) +#define TIMER8_CC2_PD10 SILABS_DBUS_TIMER8_CC2(0x3, 0xa) +#define TIMER8_CC2_PD11 SILABS_DBUS_TIMER8_CC2(0x3, 0xb) +#define TIMER8_CC2_PD12 SILABS_DBUS_TIMER8_CC2(0x3, 0xc) +#define TIMER8_CC2_PD13 SILABS_DBUS_TIMER8_CC2(0x3, 0xd) +#define TIMER8_CC2_PD14 SILABS_DBUS_TIMER8_CC2(0x3, 0xe) +#define TIMER8_CC2_PD15 SILABS_DBUS_TIMER8_CC2(0x3, 0xf) +#define TIMER8_CDTI0_PA0 SILABS_DBUS_TIMER8_CDTI0(0x0, 0x0) +#define TIMER8_CDTI0_PA1 SILABS_DBUS_TIMER8_CDTI0(0x0, 0x1) +#define TIMER8_CDTI0_PA2 SILABS_DBUS_TIMER8_CDTI0(0x0, 0x2) +#define TIMER8_CDTI0_PA3 SILABS_DBUS_TIMER8_CDTI0(0x0, 0x3) +#define TIMER8_CDTI0_PA4 SILABS_DBUS_TIMER8_CDTI0(0x0, 0x4) +#define TIMER8_CDTI0_PA5 SILABS_DBUS_TIMER8_CDTI0(0x0, 0x5) +#define TIMER8_CDTI0_PA6 SILABS_DBUS_TIMER8_CDTI0(0x0, 0x6) +#define TIMER8_CDTI0_PA7 SILABS_DBUS_TIMER8_CDTI0(0x0, 0x7) +#define TIMER8_CDTI0_PA8 SILABS_DBUS_TIMER8_CDTI0(0x0, 0x8) +#define TIMER8_CDTI0_PA9 SILABS_DBUS_TIMER8_CDTI0(0x0, 0x9) +#define TIMER8_CDTI0_PA10 SILABS_DBUS_TIMER8_CDTI0(0x0, 0xa) +#define TIMER8_CDTI0_PA11 SILABS_DBUS_TIMER8_CDTI0(0x0, 0xb) +#define TIMER8_CDTI0_PA12 SILABS_DBUS_TIMER8_CDTI0(0x0, 0xc) +#define TIMER8_CDTI0_PA13 SILABS_DBUS_TIMER8_CDTI0(0x0, 0xd) +#define TIMER8_CDTI0_PA14 SILABS_DBUS_TIMER8_CDTI0(0x0, 0xe) +#define TIMER8_CDTI0_PA15 SILABS_DBUS_TIMER8_CDTI0(0x0, 0xf) +#define TIMER8_CDTI0_PB0 SILABS_DBUS_TIMER8_CDTI0(0x1, 0x0) +#define TIMER8_CDTI0_PB1 SILABS_DBUS_TIMER8_CDTI0(0x1, 0x1) +#define TIMER8_CDTI0_PB2 SILABS_DBUS_TIMER8_CDTI0(0x1, 0x2) +#define TIMER8_CDTI0_PB3 SILABS_DBUS_TIMER8_CDTI0(0x1, 0x3) +#define TIMER8_CDTI0_PB4 SILABS_DBUS_TIMER8_CDTI0(0x1, 0x4) +#define TIMER8_CDTI0_PB5 SILABS_DBUS_TIMER8_CDTI0(0x1, 0x5) +#define TIMER8_CDTI0_PB6 SILABS_DBUS_TIMER8_CDTI0(0x1, 0x6) +#define TIMER8_CDTI0_PB7 SILABS_DBUS_TIMER8_CDTI0(0x1, 0x7) +#define TIMER8_CDTI0_PB8 SILABS_DBUS_TIMER8_CDTI0(0x1, 0x8) +#define TIMER8_CDTI0_PB9 SILABS_DBUS_TIMER8_CDTI0(0x1, 0x9) +#define TIMER8_CDTI0_PB10 SILABS_DBUS_TIMER8_CDTI0(0x1, 0xa) +#define TIMER8_CDTI0_PB11 SILABS_DBUS_TIMER8_CDTI0(0x1, 0xb) +#define TIMER8_CDTI0_PB12 SILABS_DBUS_TIMER8_CDTI0(0x1, 0xc) +#define TIMER8_CDTI0_PB13 SILABS_DBUS_TIMER8_CDTI0(0x1, 0xd) +#define TIMER8_CDTI0_PB14 SILABS_DBUS_TIMER8_CDTI0(0x1, 0xe) +#define TIMER8_CDTI0_PB15 SILABS_DBUS_TIMER8_CDTI0(0x1, 0xf) +#define TIMER8_CDTI0_PC0 SILABS_DBUS_TIMER8_CDTI0(0x2, 0x0) +#define TIMER8_CDTI0_PC1 SILABS_DBUS_TIMER8_CDTI0(0x2, 0x1) +#define TIMER8_CDTI0_PC2 SILABS_DBUS_TIMER8_CDTI0(0x2, 0x2) +#define TIMER8_CDTI0_PC3 SILABS_DBUS_TIMER8_CDTI0(0x2, 0x3) +#define TIMER8_CDTI0_PC4 SILABS_DBUS_TIMER8_CDTI0(0x2, 0x4) +#define TIMER8_CDTI0_PC5 SILABS_DBUS_TIMER8_CDTI0(0x2, 0x5) +#define TIMER8_CDTI0_PC6 SILABS_DBUS_TIMER8_CDTI0(0x2, 0x6) +#define TIMER8_CDTI0_PC7 SILABS_DBUS_TIMER8_CDTI0(0x2, 0x7) +#define TIMER8_CDTI0_PC8 SILABS_DBUS_TIMER8_CDTI0(0x2, 0x8) +#define TIMER8_CDTI0_PC9 SILABS_DBUS_TIMER8_CDTI0(0x2, 0x9) +#define TIMER8_CDTI0_PC10 SILABS_DBUS_TIMER8_CDTI0(0x2, 0xa) +#define TIMER8_CDTI0_PC11 SILABS_DBUS_TIMER8_CDTI0(0x2, 0xb) +#define TIMER8_CDTI0_PC12 SILABS_DBUS_TIMER8_CDTI0(0x2, 0xc) +#define TIMER8_CDTI0_PC13 SILABS_DBUS_TIMER8_CDTI0(0x2, 0xd) +#define TIMER8_CDTI0_PC14 SILABS_DBUS_TIMER8_CDTI0(0x2, 0xe) +#define TIMER8_CDTI0_PC15 SILABS_DBUS_TIMER8_CDTI0(0x2, 0xf) +#define TIMER8_CDTI0_PD0 SILABS_DBUS_TIMER8_CDTI0(0x3, 0x0) +#define TIMER8_CDTI0_PD1 SILABS_DBUS_TIMER8_CDTI0(0x3, 0x1) +#define TIMER8_CDTI0_PD2 SILABS_DBUS_TIMER8_CDTI0(0x3, 0x2) +#define TIMER8_CDTI0_PD3 SILABS_DBUS_TIMER8_CDTI0(0x3, 0x3) +#define TIMER8_CDTI0_PD4 SILABS_DBUS_TIMER8_CDTI0(0x3, 0x4) +#define TIMER8_CDTI0_PD5 SILABS_DBUS_TIMER8_CDTI0(0x3, 0x5) +#define TIMER8_CDTI0_PD6 SILABS_DBUS_TIMER8_CDTI0(0x3, 0x6) +#define TIMER8_CDTI0_PD7 SILABS_DBUS_TIMER8_CDTI0(0x3, 0x7) +#define TIMER8_CDTI0_PD8 SILABS_DBUS_TIMER8_CDTI0(0x3, 0x8) +#define TIMER8_CDTI0_PD9 SILABS_DBUS_TIMER8_CDTI0(0x3, 0x9) +#define TIMER8_CDTI0_PD10 SILABS_DBUS_TIMER8_CDTI0(0x3, 0xa) +#define TIMER8_CDTI0_PD11 SILABS_DBUS_TIMER8_CDTI0(0x3, 0xb) +#define TIMER8_CDTI0_PD12 SILABS_DBUS_TIMER8_CDTI0(0x3, 0xc) +#define TIMER8_CDTI0_PD13 SILABS_DBUS_TIMER8_CDTI0(0x3, 0xd) +#define TIMER8_CDTI0_PD14 SILABS_DBUS_TIMER8_CDTI0(0x3, 0xe) +#define TIMER8_CDTI0_PD15 SILABS_DBUS_TIMER8_CDTI0(0x3, 0xf) +#define TIMER8_CDTI1_PA0 SILABS_DBUS_TIMER8_CDTI1(0x0, 0x0) +#define TIMER8_CDTI1_PA1 SILABS_DBUS_TIMER8_CDTI1(0x0, 0x1) +#define TIMER8_CDTI1_PA2 SILABS_DBUS_TIMER8_CDTI1(0x0, 0x2) +#define TIMER8_CDTI1_PA3 SILABS_DBUS_TIMER8_CDTI1(0x0, 0x3) +#define TIMER8_CDTI1_PA4 SILABS_DBUS_TIMER8_CDTI1(0x0, 0x4) +#define TIMER8_CDTI1_PA5 SILABS_DBUS_TIMER8_CDTI1(0x0, 0x5) +#define TIMER8_CDTI1_PA6 SILABS_DBUS_TIMER8_CDTI1(0x0, 0x6) +#define TIMER8_CDTI1_PA7 SILABS_DBUS_TIMER8_CDTI1(0x0, 0x7) +#define TIMER8_CDTI1_PA8 SILABS_DBUS_TIMER8_CDTI1(0x0, 0x8) +#define TIMER8_CDTI1_PA9 SILABS_DBUS_TIMER8_CDTI1(0x0, 0x9) +#define TIMER8_CDTI1_PA10 SILABS_DBUS_TIMER8_CDTI1(0x0, 0xa) +#define TIMER8_CDTI1_PA11 SILABS_DBUS_TIMER8_CDTI1(0x0, 0xb) +#define TIMER8_CDTI1_PA12 SILABS_DBUS_TIMER8_CDTI1(0x0, 0xc) +#define TIMER8_CDTI1_PA13 SILABS_DBUS_TIMER8_CDTI1(0x0, 0xd) +#define TIMER8_CDTI1_PA14 SILABS_DBUS_TIMER8_CDTI1(0x0, 0xe) +#define TIMER8_CDTI1_PA15 SILABS_DBUS_TIMER8_CDTI1(0x0, 0xf) +#define TIMER8_CDTI1_PB0 SILABS_DBUS_TIMER8_CDTI1(0x1, 0x0) +#define TIMER8_CDTI1_PB1 SILABS_DBUS_TIMER8_CDTI1(0x1, 0x1) +#define TIMER8_CDTI1_PB2 SILABS_DBUS_TIMER8_CDTI1(0x1, 0x2) +#define TIMER8_CDTI1_PB3 SILABS_DBUS_TIMER8_CDTI1(0x1, 0x3) +#define TIMER8_CDTI1_PB4 SILABS_DBUS_TIMER8_CDTI1(0x1, 0x4) +#define TIMER8_CDTI1_PB5 SILABS_DBUS_TIMER8_CDTI1(0x1, 0x5) +#define TIMER8_CDTI1_PB6 SILABS_DBUS_TIMER8_CDTI1(0x1, 0x6) +#define TIMER8_CDTI1_PB7 SILABS_DBUS_TIMER8_CDTI1(0x1, 0x7) +#define TIMER8_CDTI1_PB8 SILABS_DBUS_TIMER8_CDTI1(0x1, 0x8) +#define TIMER8_CDTI1_PB9 SILABS_DBUS_TIMER8_CDTI1(0x1, 0x9) +#define TIMER8_CDTI1_PB10 SILABS_DBUS_TIMER8_CDTI1(0x1, 0xa) +#define TIMER8_CDTI1_PB11 SILABS_DBUS_TIMER8_CDTI1(0x1, 0xb) +#define TIMER8_CDTI1_PB12 SILABS_DBUS_TIMER8_CDTI1(0x1, 0xc) +#define TIMER8_CDTI1_PB13 SILABS_DBUS_TIMER8_CDTI1(0x1, 0xd) +#define TIMER8_CDTI1_PB14 SILABS_DBUS_TIMER8_CDTI1(0x1, 0xe) +#define TIMER8_CDTI1_PB15 SILABS_DBUS_TIMER8_CDTI1(0x1, 0xf) +#define TIMER8_CDTI1_PC0 SILABS_DBUS_TIMER8_CDTI1(0x2, 0x0) +#define TIMER8_CDTI1_PC1 SILABS_DBUS_TIMER8_CDTI1(0x2, 0x1) +#define TIMER8_CDTI1_PC2 SILABS_DBUS_TIMER8_CDTI1(0x2, 0x2) +#define TIMER8_CDTI1_PC3 SILABS_DBUS_TIMER8_CDTI1(0x2, 0x3) +#define TIMER8_CDTI1_PC4 SILABS_DBUS_TIMER8_CDTI1(0x2, 0x4) +#define TIMER8_CDTI1_PC5 SILABS_DBUS_TIMER8_CDTI1(0x2, 0x5) +#define TIMER8_CDTI1_PC6 SILABS_DBUS_TIMER8_CDTI1(0x2, 0x6) +#define TIMER8_CDTI1_PC7 SILABS_DBUS_TIMER8_CDTI1(0x2, 0x7) +#define TIMER8_CDTI1_PC8 SILABS_DBUS_TIMER8_CDTI1(0x2, 0x8) +#define TIMER8_CDTI1_PC9 SILABS_DBUS_TIMER8_CDTI1(0x2, 0x9) +#define TIMER8_CDTI1_PC10 SILABS_DBUS_TIMER8_CDTI1(0x2, 0xa) +#define TIMER8_CDTI1_PC11 SILABS_DBUS_TIMER8_CDTI1(0x2, 0xb) +#define TIMER8_CDTI1_PC12 SILABS_DBUS_TIMER8_CDTI1(0x2, 0xc) +#define TIMER8_CDTI1_PC13 SILABS_DBUS_TIMER8_CDTI1(0x2, 0xd) +#define TIMER8_CDTI1_PC14 SILABS_DBUS_TIMER8_CDTI1(0x2, 0xe) +#define TIMER8_CDTI1_PC15 SILABS_DBUS_TIMER8_CDTI1(0x2, 0xf) +#define TIMER8_CDTI1_PD0 SILABS_DBUS_TIMER8_CDTI1(0x3, 0x0) +#define TIMER8_CDTI1_PD1 SILABS_DBUS_TIMER8_CDTI1(0x3, 0x1) +#define TIMER8_CDTI1_PD2 SILABS_DBUS_TIMER8_CDTI1(0x3, 0x2) +#define TIMER8_CDTI1_PD3 SILABS_DBUS_TIMER8_CDTI1(0x3, 0x3) +#define TIMER8_CDTI1_PD4 SILABS_DBUS_TIMER8_CDTI1(0x3, 0x4) +#define TIMER8_CDTI1_PD5 SILABS_DBUS_TIMER8_CDTI1(0x3, 0x5) +#define TIMER8_CDTI1_PD6 SILABS_DBUS_TIMER8_CDTI1(0x3, 0x6) +#define TIMER8_CDTI1_PD7 SILABS_DBUS_TIMER8_CDTI1(0x3, 0x7) +#define TIMER8_CDTI1_PD8 SILABS_DBUS_TIMER8_CDTI1(0x3, 0x8) +#define TIMER8_CDTI1_PD9 SILABS_DBUS_TIMER8_CDTI1(0x3, 0x9) +#define TIMER8_CDTI1_PD10 SILABS_DBUS_TIMER8_CDTI1(0x3, 0xa) +#define TIMER8_CDTI1_PD11 SILABS_DBUS_TIMER8_CDTI1(0x3, 0xb) +#define TIMER8_CDTI1_PD12 SILABS_DBUS_TIMER8_CDTI1(0x3, 0xc) +#define TIMER8_CDTI1_PD13 SILABS_DBUS_TIMER8_CDTI1(0x3, 0xd) +#define TIMER8_CDTI1_PD14 SILABS_DBUS_TIMER8_CDTI1(0x3, 0xe) +#define TIMER8_CDTI1_PD15 SILABS_DBUS_TIMER8_CDTI1(0x3, 0xf) +#define TIMER8_CDTI2_PA0 SILABS_DBUS_TIMER8_CDTI2(0x0, 0x0) +#define TIMER8_CDTI2_PA1 SILABS_DBUS_TIMER8_CDTI2(0x0, 0x1) +#define TIMER8_CDTI2_PA2 SILABS_DBUS_TIMER8_CDTI2(0x0, 0x2) +#define TIMER8_CDTI2_PA3 SILABS_DBUS_TIMER8_CDTI2(0x0, 0x3) +#define TIMER8_CDTI2_PA4 SILABS_DBUS_TIMER8_CDTI2(0x0, 0x4) +#define TIMER8_CDTI2_PA5 SILABS_DBUS_TIMER8_CDTI2(0x0, 0x5) +#define TIMER8_CDTI2_PA6 SILABS_DBUS_TIMER8_CDTI2(0x0, 0x6) +#define TIMER8_CDTI2_PA7 SILABS_DBUS_TIMER8_CDTI2(0x0, 0x7) +#define TIMER8_CDTI2_PA8 SILABS_DBUS_TIMER8_CDTI2(0x0, 0x8) +#define TIMER8_CDTI2_PA9 SILABS_DBUS_TIMER8_CDTI2(0x0, 0x9) +#define TIMER8_CDTI2_PA10 SILABS_DBUS_TIMER8_CDTI2(0x0, 0xa) +#define TIMER8_CDTI2_PA11 SILABS_DBUS_TIMER8_CDTI2(0x0, 0xb) +#define TIMER8_CDTI2_PA12 SILABS_DBUS_TIMER8_CDTI2(0x0, 0xc) +#define TIMER8_CDTI2_PA13 SILABS_DBUS_TIMER8_CDTI2(0x0, 0xd) +#define TIMER8_CDTI2_PA14 SILABS_DBUS_TIMER8_CDTI2(0x0, 0xe) +#define TIMER8_CDTI2_PA15 SILABS_DBUS_TIMER8_CDTI2(0x0, 0xf) +#define TIMER8_CDTI2_PB0 SILABS_DBUS_TIMER8_CDTI2(0x1, 0x0) +#define TIMER8_CDTI2_PB1 SILABS_DBUS_TIMER8_CDTI2(0x1, 0x1) +#define TIMER8_CDTI2_PB2 SILABS_DBUS_TIMER8_CDTI2(0x1, 0x2) +#define TIMER8_CDTI2_PB3 SILABS_DBUS_TIMER8_CDTI2(0x1, 0x3) +#define TIMER8_CDTI2_PB4 SILABS_DBUS_TIMER8_CDTI2(0x1, 0x4) +#define TIMER8_CDTI2_PB5 SILABS_DBUS_TIMER8_CDTI2(0x1, 0x5) +#define TIMER8_CDTI2_PB6 SILABS_DBUS_TIMER8_CDTI2(0x1, 0x6) +#define TIMER8_CDTI2_PB7 SILABS_DBUS_TIMER8_CDTI2(0x1, 0x7) +#define TIMER8_CDTI2_PB8 SILABS_DBUS_TIMER8_CDTI2(0x1, 0x8) +#define TIMER8_CDTI2_PB9 SILABS_DBUS_TIMER8_CDTI2(0x1, 0x9) +#define TIMER8_CDTI2_PB10 SILABS_DBUS_TIMER8_CDTI2(0x1, 0xa) +#define TIMER8_CDTI2_PB11 SILABS_DBUS_TIMER8_CDTI2(0x1, 0xb) +#define TIMER8_CDTI2_PB12 SILABS_DBUS_TIMER8_CDTI2(0x1, 0xc) +#define TIMER8_CDTI2_PB13 SILABS_DBUS_TIMER8_CDTI2(0x1, 0xd) +#define TIMER8_CDTI2_PB14 SILABS_DBUS_TIMER8_CDTI2(0x1, 0xe) +#define TIMER8_CDTI2_PB15 SILABS_DBUS_TIMER8_CDTI2(0x1, 0xf) +#define TIMER8_CDTI2_PC0 SILABS_DBUS_TIMER8_CDTI2(0x2, 0x0) +#define TIMER8_CDTI2_PC1 SILABS_DBUS_TIMER8_CDTI2(0x2, 0x1) +#define TIMER8_CDTI2_PC2 SILABS_DBUS_TIMER8_CDTI2(0x2, 0x2) +#define TIMER8_CDTI2_PC3 SILABS_DBUS_TIMER8_CDTI2(0x2, 0x3) +#define TIMER8_CDTI2_PC4 SILABS_DBUS_TIMER8_CDTI2(0x2, 0x4) +#define TIMER8_CDTI2_PC5 SILABS_DBUS_TIMER8_CDTI2(0x2, 0x5) +#define TIMER8_CDTI2_PC6 SILABS_DBUS_TIMER8_CDTI2(0x2, 0x6) +#define TIMER8_CDTI2_PC7 SILABS_DBUS_TIMER8_CDTI2(0x2, 0x7) +#define TIMER8_CDTI2_PC8 SILABS_DBUS_TIMER8_CDTI2(0x2, 0x8) +#define TIMER8_CDTI2_PC9 SILABS_DBUS_TIMER8_CDTI2(0x2, 0x9) +#define TIMER8_CDTI2_PC10 SILABS_DBUS_TIMER8_CDTI2(0x2, 0xa) +#define TIMER8_CDTI2_PC11 SILABS_DBUS_TIMER8_CDTI2(0x2, 0xb) +#define TIMER8_CDTI2_PC12 SILABS_DBUS_TIMER8_CDTI2(0x2, 0xc) +#define TIMER8_CDTI2_PC13 SILABS_DBUS_TIMER8_CDTI2(0x2, 0xd) +#define TIMER8_CDTI2_PC14 SILABS_DBUS_TIMER8_CDTI2(0x2, 0xe) +#define TIMER8_CDTI2_PC15 SILABS_DBUS_TIMER8_CDTI2(0x2, 0xf) +#define TIMER8_CDTI2_PD0 SILABS_DBUS_TIMER8_CDTI2(0x3, 0x0) +#define TIMER8_CDTI2_PD1 SILABS_DBUS_TIMER8_CDTI2(0x3, 0x1) +#define TIMER8_CDTI2_PD2 SILABS_DBUS_TIMER8_CDTI2(0x3, 0x2) +#define TIMER8_CDTI2_PD3 SILABS_DBUS_TIMER8_CDTI2(0x3, 0x3) +#define TIMER8_CDTI2_PD4 SILABS_DBUS_TIMER8_CDTI2(0x3, 0x4) +#define TIMER8_CDTI2_PD5 SILABS_DBUS_TIMER8_CDTI2(0x3, 0x5) +#define TIMER8_CDTI2_PD6 SILABS_DBUS_TIMER8_CDTI2(0x3, 0x6) +#define TIMER8_CDTI2_PD7 SILABS_DBUS_TIMER8_CDTI2(0x3, 0x7) +#define TIMER8_CDTI2_PD8 SILABS_DBUS_TIMER8_CDTI2(0x3, 0x8) +#define TIMER8_CDTI2_PD9 SILABS_DBUS_TIMER8_CDTI2(0x3, 0x9) +#define TIMER8_CDTI2_PD10 SILABS_DBUS_TIMER8_CDTI2(0x3, 0xa) +#define TIMER8_CDTI2_PD11 SILABS_DBUS_TIMER8_CDTI2(0x3, 0xb) +#define TIMER8_CDTI2_PD12 SILABS_DBUS_TIMER8_CDTI2(0x3, 0xc) +#define TIMER8_CDTI2_PD13 SILABS_DBUS_TIMER8_CDTI2(0x3, 0xd) +#define TIMER8_CDTI2_PD14 SILABS_DBUS_TIMER8_CDTI2(0x3, 0xe) +#define TIMER8_CDTI2_PD15 SILABS_DBUS_TIMER8_CDTI2(0x3, 0xf) + +#define TIMER9_CC0_PA0 SILABS_DBUS_TIMER9_CC0(0x0, 0x0) +#define TIMER9_CC0_PA1 SILABS_DBUS_TIMER9_CC0(0x0, 0x1) +#define TIMER9_CC0_PA2 SILABS_DBUS_TIMER9_CC0(0x0, 0x2) +#define TIMER9_CC0_PA3 SILABS_DBUS_TIMER9_CC0(0x0, 0x3) +#define TIMER9_CC0_PA4 SILABS_DBUS_TIMER9_CC0(0x0, 0x4) +#define TIMER9_CC0_PA5 SILABS_DBUS_TIMER9_CC0(0x0, 0x5) +#define TIMER9_CC0_PA6 SILABS_DBUS_TIMER9_CC0(0x0, 0x6) +#define TIMER9_CC0_PA7 SILABS_DBUS_TIMER9_CC0(0x0, 0x7) +#define TIMER9_CC0_PA8 SILABS_DBUS_TIMER9_CC0(0x0, 0x8) +#define TIMER9_CC0_PA9 SILABS_DBUS_TIMER9_CC0(0x0, 0x9) +#define TIMER9_CC0_PA10 SILABS_DBUS_TIMER9_CC0(0x0, 0xa) +#define TIMER9_CC0_PA11 SILABS_DBUS_TIMER9_CC0(0x0, 0xb) +#define TIMER9_CC0_PA12 SILABS_DBUS_TIMER9_CC0(0x0, 0xc) +#define TIMER9_CC0_PA13 SILABS_DBUS_TIMER9_CC0(0x0, 0xd) +#define TIMER9_CC0_PA14 SILABS_DBUS_TIMER9_CC0(0x0, 0xe) +#define TIMER9_CC0_PA15 SILABS_DBUS_TIMER9_CC0(0x0, 0xf) +#define TIMER9_CC0_PB0 SILABS_DBUS_TIMER9_CC0(0x1, 0x0) +#define TIMER9_CC0_PB1 SILABS_DBUS_TIMER9_CC0(0x1, 0x1) +#define TIMER9_CC0_PB2 SILABS_DBUS_TIMER9_CC0(0x1, 0x2) +#define TIMER9_CC0_PB3 SILABS_DBUS_TIMER9_CC0(0x1, 0x3) +#define TIMER9_CC0_PB4 SILABS_DBUS_TIMER9_CC0(0x1, 0x4) +#define TIMER9_CC0_PB5 SILABS_DBUS_TIMER9_CC0(0x1, 0x5) +#define TIMER9_CC0_PB6 SILABS_DBUS_TIMER9_CC0(0x1, 0x6) +#define TIMER9_CC0_PB7 SILABS_DBUS_TIMER9_CC0(0x1, 0x7) +#define TIMER9_CC0_PB8 SILABS_DBUS_TIMER9_CC0(0x1, 0x8) +#define TIMER9_CC0_PB9 SILABS_DBUS_TIMER9_CC0(0x1, 0x9) +#define TIMER9_CC0_PB10 SILABS_DBUS_TIMER9_CC0(0x1, 0xa) +#define TIMER9_CC0_PB11 SILABS_DBUS_TIMER9_CC0(0x1, 0xb) +#define TIMER9_CC0_PB12 SILABS_DBUS_TIMER9_CC0(0x1, 0xc) +#define TIMER9_CC0_PB13 SILABS_DBUS_TIMER9_CC0(0x1, 0xd) +#define TIMER9_CC0_PB14 SILABS_DBUS_TIMER9_CC0(0x1, 0xe) +#define TIMER9_CC0_PB15 SILABS_DBUS_TIMER9_CC0(0x1, 0xf) +#define TIMER9_CC0_PC0 SILABS_DBUS_TIMER9_CC0(0x2, 0x0) +#define TIMER9_CC0_PC1 SILABS_DBUS_TIMER9_CC0(0x2, 0x1) +#define TIMER9_CC0_PC2 SILABS_DBUS_TIMER9_CC0(0x2, 0x2) +#define TIMER9_CC0_PC3 SILABS_DBUS_TIMER9_CC0(0x2, 0x3) +#define TIMER9_CC0_PC4 SILABS_DBUS_TIMER9_CC0(0x2, 0x4) +#define TIMER9_CC0_PC5 SILABS_DBUS_TIMER9_CC0(0x2, 0x5) +#define TIMER9_CC0_PC6 SILABS_DBUS_TIMER9_CC0(0x2, 0x6) +#define TIMER9_CC0_PC7 SILABS_DBUS_TIMER9_CC0(0x2, 0x7) +#define TIMER9_CC0_PC8 SILABS_DBUS_TIMER9_CC0(0x2, 0x8) +#define TIMER9_CC0_PC9 SILABS_DBUS_TIMER9_CC0(0x2, 0x9) +#define TIMER9_CC0_PC10 SILABS_DBUS_TIMER9_CC0(0x2, 0xa) +#define TIMER9_CC0_PC11 SILABS_DBUS_TIMER9_CC0(0x2, 0xb) +#define TIMER9_CC0_PC12 SILABS_DBUS_TIMER9_CC0(0x2, 0xc) +#define TIMER9_CC0_PC13 SILABS_DBUS_TIMER9_CC0(0x2, 0xd) +#define TIMER9_CC0_PC14 SILABS_DBUS_TIMER9_CC0(0x2, 0xe) +#define TIMER9_CC0_PC15 SILABS_DBUS_TIMER9_CC0(0x2, 0xf) +#define TIMER9_CC0_PD0 SILABS_DBUS_TIMER9_CC0(0x3, 0x0) +#define TIMER9_CC0_PD1 SILABS_DBUS_TIMER9_CC0(0x3, 0x1) +#define TIMER9_CC0_PD2 SILABS_DBUS_TIMER9_CC0(0x3, 0x2) +#define TIMER9_CC0_PD3 SILABS_DBUS_TIMER9_CC0(0x3, 0x3) +#define TIMER9_CC0_PD4 SILABS_DBUS_TIMER9_CC0(0x3, 0x4) +#define TIMER9_CC0_PD5 SILABS_DBUS_TIMER9_CC0(0x3, 0x5) +#define TIMER9_CC0_PD6 SILABS_DBUS_TIMER9_CC0(0x3, 0x6) +#define TIMER9_CC0_PD7 SILABS_DBUS_TIMER9_CC0(0x3, 0x7) +#define TIMER9_CC0_PD8 SILABS_DBUS_TIMER9_CC0(0x3, 0x8) +#define TIMER9_CC0_PD9 SILABS_DBUS_TIMER9_CC0(0x3, 0x9) +#define TIMER9_CC0_PD10 SILABS_DBUS_TIMER9_CC0(0x3, 0xa) +#define TIMER9_CC0_PD11 SILABS_DBUS_TIMER9_CC0(0x3, 0xb) +#define TIMER9_CC0_PD12 SILABS_DBUS_TIMER9_CC0(0x3, 0xc) +#define TIMER9_CC0_PD13 SILABS_DBUS_TIMER9_CC0(0x3, 0xd) +#define TIMER9_CC0_PD14 SILABS_DBUS_TIMER9_CC0(0x3, 0xe) +#define TIMER9_CC0_PD15 SILABS_DBUS_TIMER9_CC0(0x3, 0xf) +#define TIMER9_CC1_PA0 SILABS_DBUS_TIMER9_CC1(0x0, 0x0) +#define TIMER9_CC1_PA1 SILABS_DBUS_TIMER9_CC1(0x0, 0x1) +#define TIMER9_CC1_PA2 SILABS_DBUS_TIMER9_CC1(0x0, 0x2) +#define TIMER9_CC1_PA3 SILABS_DBUS_TIMER9_CC1(0x0, 0x3) +#define TIMER9_CC1_PA4 SILABS_DBUS_TIMER9_CC1(0x0, 0x4) +#define TIMER9_CC1_PA5 SILABS_DBUS_TIMER9_CC1(0x0, 0x5) +#define TIMER9_CC1_PA6 SILABS_DBUS_TIMER9_CC1(0x0, 0x6) +#define TIMER9_CC1_PA7 SILABS_DBUS_TIMER9_CC1(0x0, 0x7) +#define TIMER9_CC1_PA8 SILABS_DBUS_TIMER9_CC1(0x0, 0x8) +#define TIMER9_CC1_PA9 SILABS_DBUS_TIMER9_CC1(0x0, 0x9) +#define TIMER9_CC1_PA10 SILABS_DBUS_TIMER9_CC1(0x0, 0xa) +#define TIMER9_CC1_PA11 SILABS_DBUS_TIMER9_CC1(0x0, 0xb) +#define TIMER9_CC1_PA12 SILABS_DBUS_TIMER9_CC1(0x0, 0xc) +#define TIMER9_CC1_PA13 SILABS_DBUS_TIMER9_CC1(0x0, 0xd) +#define TIMER9_CC1_PA14 SILABS_DBUS_TIMER9_CC1(0x0, 0xe) +#define TIMER9_CC1_PA15 SILABS_DBUS_TIMER9_CC1(0x0, 0xf) +#define TIMER9_CC1_PB0 SILABS_DBUS_TIMER9_CC1(0x1, 0x0) +#define TIMER9_CC1_PB1 SILABS_DBUS_TIMER9_CC1(0x1, 0x1) +#define TIMER9_CC1_PB2 SILABS_DBUS_TIMER9_CC1(0x1, 0x2) +#define TIMER9_CC1_PB3 SILABS_DBUS_TIMER9_CC1(0x1, 0x3) +#define TIMER9_CC1_PB4 SILABS_DBUS_TIMER9_CC1(0x1, 0x4) +#define TIMER9_CC1_PB5 SILABS_DBUS_TIMER9_CC1(0x1, 0x5) +#define TIMER9_CC1_PB6 SILABS_DBUS_TIMER9_CC1(0x1, 0x6) +#define TIMER9_CC1_PB7 SILABS_DBUS_TIMER9_CC1(0x1, 0x7) +#define TIMER9_CC1_PB8 SILABS_DBUS_TIMER9_CC1(0x1, 0x8) +#define TIMER9_CC1_PB9 SILABS_DBUS_TIMER9_CC1(0x1, 0x9) +#define TIMER9_CC1_PB10 SILABS_DBUS_TIMER9_CC1(0x1, 0xa) +#define TIMER9_CC1_PB11 SILABS_DBUS_TIMER9_CC1(0x1, 0xb) +#define TIMER9_CC1_PB12 SILABS_DBUS_TIMER9_CC1(0x1, 0xc) +#define TIMER9_CC1_PB13 SILABS_DBUS_TIMER9_CC1(0x1, 0xd) +#define TIMER9_CC1_PB14 SILABS_DBUS_TIMER9_CC1(0x1, 0xe) +#define TIMER9_CC1_PB15 SILABS_DBUS_TIMER9_CC1(0x1, 0xf) +#define TIMER9_CC1_PC0 SILABS_DBUS_TIMER9_CC1(0x2, 0x0) +#define TIMER9_CC1_PC1 SILABS_DBUS_TIMER9_CC1(0x2, 0x1) +#define TIMER9_CC1_PC2 SILABS_DBUS_TIMER9_CC1(0x2, 0x2) +#define TIMER9_CC1_PC3 SILABS_DBUS_TIMER9_CC1(0x2, 0x3) +#define TIMER9_CC1_PC4 SILABS_DBUS_TIMER9_CC1(0x2, 0x4) +#define TIMER9_CC1_PC5 SILABS_DBUS_TIMER9_CC1(0x2, 0x5) +#define TIMER9_CC1_PC6 SILABS_DBUS_TIMER9_CC1(0x2, 0x6) +#define TIMER9_CC1_PC7 SILABS_DBUS_TIMER9_CC1(0x2, 0x7) +#define TIMER9_CC1_PC8 SILABS_DBUS_TIMER9_CC1(0x2, 0x8) +#define TIMER9_CC1_PC9 SILABS_DBUS_TIMER9_CC1(0x2, 0x9) +#define TIMER9_CC1_PC10 SILABS_DBUS_TIMER9_CC1(0x2, 0xa) +#define TIMER9_CC1_PC11 SILABS_DBUS_TIMER9_CC1(0x2, 0xb) +#define TIMER9_CC1_PC12 SILABS_DBUS_TIMER9_CC1(0x2, 0xc) +#define TIMER9_CC1_PC13 SILABS_DBUS_TIMER9_CC1(0x2, 0xd) +#define TIMER9_CC1_PC14 SILABS_DBUS_TIMER9_CC1(0x2, 0xe) +#define TIMER9_CC1_PC15 SILABS_DBUS_TIMER9_CC1(0x2, 0xf) +#define TIMER9_CC1_PD0 SILABS_DBUS_TIMER9_CC1(0x3, 0x0) +#define TIMER9_CC1_PD1 SILABS_DBUS_TIMER9_CC1(0x3, 0x1) +#define TIMER9_CC1_PD2 SILABS_DBUS_TIMER9_CC1(0x3, 0x2) +#define TIMER9_CC1_PD3 SILABS_DBUS_TIMER9_CC1(0x3, 0x3) +#define TIMER9_CC1_PD4 SILABS_DBUS_TIMER9_CC1(0x3, 0x4) +#define TIMER9_CC1_PD5 SILABS_DBUS_TIMER9_CC1(0x3, 0x5) +#define TIMER9_CC1_PD6 SILABS_DBUS_TIMER9_CC1(0x3, 0x6) +#define TIMER9_CC1_PD7 SILABS_DBUS_TIMER9_CC1(0x3, 0x7) +#define TIMER9_CC1_PD8 SILABS_DBUS_TIMER9_CC1(0x3, 0x8) +#define TIMER9_CC1_PD9 SILABS_DBUS_TIMER9_CC1(0x3, 0x9) +#define TIMER9_CC1_PD10 SILABS_DBUS_TIMER9_CC1(0x3, 0xa) +#define TIMER9_CC1_PD11 SILABS_DBUS_TIMER9_CC1(0x3, 0xb) +#define TIMER9_CC1_PD12 SILABS_DBUS_TIMER9_CC1(0x3, 0xc) +#define TIMER9_CC1_PD13 SILABS_DBUS_TIMER9_CC1(0x3, 0xd) +#define TIMER9_CC1_PD14 SILABS_DBUS_TIMER9_CC1(0x3, 0xe) +#define TIMER9_CC1_PD15 SILABS_DBUS_TIMER9_CC1(0x3, 0xf) +#define TIMER9_CC2_PA0 SILABS_DBUS_TIMER9_CC2(0x0, 0x0) +#define TIMER9_CC2_PA1 SILABS_DBUS_TIMER9_CC2(0x0, 0x1) +#define TIMER9_CC2_PA2 SILABS_DBUS_TIMER9_CC2(0x0, 0x2) +#define TIMER9_CC2_PA3 SILABS_DBUS_TIMER9_CC2(0x0, 0x3) +#define TIMER9_CC2_PA4 SILABS_DBUS_TIMER9_CC2(0x0, 0x4) +#define TIMER9_CC2_PA5 SILABS_DBUS_TIMER9_CC2(0x0, 0x5) +#define TIMER9_CC2_PA6 SILABS_DBUS_TIMER9_CC2(0x0, 0x6) +#define TIMER9_CC2_PA7 SILABS_DBUS_TIMER9_CC2(0x0, 0x7) +#define TIMER9_CC2_PA8 SILABS_DBUS_TIMER9_CC2(0x0, 0x8) +#define TIMER9_CC2_PA9 SILABS_DBUS_TIMER9_CC2(0x0, 0x9) +#define TIMER9_CC2_PA10 SILABS_DBUS_TIMER9_CC2(0x0, 0xa) +#define TIMER9_CC2_PA11 SILABS_DBUS_TIMER9_CC2(0x0, 0xb) +#define TIMER9_CC2_PA12 SILABS_DBUS_TIMER9_CC2(0x0, 0xc) +#define TIMER9_CC2_PA13 SILABS_DBUS_TIMER9_CC2(0x0, 0xd) +#define TIMER9_CC2_PA14 SILABS_DBUS_TIMER9_CC2(0x0, 0xe) +#define TIMER9_CC2_PA15 SILABS_DBUS_TIMER9_CC2(0x0, 0xf) +#define TIMER9_CC2_PB0 SILABS_DBUS_TIMER9_CC2(0x1, 0x0) +#define TIMER9_CC2_PB1 SILABS_DBUS_TIMER9_CC2(0x1, 0x1) +#define TIMER9_CC2_PB2 SILABS_DBUS_TIMER9_CC2(0x1, 0x2) +#define TIMER9_CC2_PB3 SILABS_DBUS_TIMER9_CC2(0x1, 0x3) +#define TIMER9_CC2_PB4 SILABS_DBUS_TIMER9_CC2(0x1, 0x4) +#define TIMER9_CC2_PB5 SILABS_DBUS_TIMER9_CC2(0x1, 0x5) +#define TIMER9_CC2_PB6 SILABS_DBUS_TIMER9_CC2(0x1, 0x6) +#define TIMER9_CC2_PB7 SILABS_DBUS_TIMER9_CC2(0x1, 0x7) +#define TIMER9_CC2_PB8 SILABS_DBUS_TIMER9_CC2(0x1, 0x8) +#define TIMER9_CC2_PB9 SILABS_DBUS_TIMER9_CC2(0x1, 0x9) +#define TIMER9_CC2_PB10 SILABS_DBUS_TIMER9_CC2(0x1, 0xa) +#define TIMER9_CC2_PB11 SILABS_DBUS_TIMER9_CC2(0x1, 0xb) +#define TIMER9_CC2_PB12 SILABS_DBUS_TIMER9_CC2(0x1, 0xc) +#define TIMER9_CC2_PB13 SILABS_DBUS_TIMER9_CC2(0x1, 0xd) +#define TIMER9_CC2_PB14 SILABS_DBUS_TIMER9_CC2(0x1, 0xe) +#define TIMER9_CC2_PB15 SILABS_DBUS_TIMER9_CC2(0x1, 0xf) +#define TIMER9_CC2_PC0 SILABS_DBUS_TIMER9_CC2(0x2, 0x0) +#define TIMER9_CC2_PC1 SILABS_DBUS_TIMER9_CC2(0x2, 0x1) +#define TIMER9_CC2_PC2 SILABS_DBUS_TIMER9_CC2(0x2, 0x2) +#define TIMER9_CC2_PC3 SILABS_DBUS_TIMER9_CC2(0x2, 0x3) +#define TIMER9_CC2_PC4 SILABS_DBUS_TIMER9_CC2(0x2, 0x4) +#define TIMER9_CC2_PC5 SILABS_DBUS_TIMER9_CC2(0x2, 0x5) +#define TIMER9_CC2_PC6 SILABS_DBUS_TIMER9_CC2(0x2, 0x6) +#define TIMER9_CC2_PC7 SILABS_DBUS_TIMER9_CC2(0x2, 0x7) +#define TIMER9_CC2_PC8 SILABS_DBUS_TIMER9_CC2(0x2, 0x8) +#define TIMER9_CC2_PC9 SILABS_DBUS_TIMER9_CC2(0x2, 0x9) +#define TIMER9_CC2_PC10 SILABS_DBUS_TIMER9_CC2(0x2, 0xa) +#define TIMER9_CC2_PC11 SILABS_DBUS_TIMER9_CC2(0x2, 0xb) +#define TIMER9_CC2_PC12 SILABS_DBUS_TIMER9_CC2(0x2, 0xc) +#define TIMER9_CC2_PC13 SILABS_DBUS_TIMER9_CC2(0x2, 0xd) +#define TIMER9_CC2_PC14 SILABS_DBUS_TIMER9_CC2(0x2, 0xe) +#define TIMER9_CC2_PC15 SILABS_DBUS_TIMER9_CC2(0x2, 0xf) +#define TIMER9_CC2_PD0 SILABS_DBUS_TIMER9_CC2(0x3, 0x0) +#define TIMER9_CC2_PD1 SILABS_DBUS_TIMER9_CC2(0x3, 0x1) +#define TIMER9_CC2_PD2 SILABS_DBUS_TIMER9_CC2(0x3, 0x2) +#define TIMER9_CC2_PD3 SILABS_DBUS_TIMER9_CC2(0x3, 0x3) +#define TIMER9_CC2_PD4 SILABS_DBUS_TIMER9_CC2(0x3, 0x4) +#define TIMER9_CC2_PD5 SILABS_DBUS_TIMER9_CC2(0x3, 0x5) +#define TIMER9_CC2_PD6 SILABS_DBUS_TIMER9_CC2(0x3, 0x6) +#define TIMER9_CC2_PD7 SILABS_DBUS_TIMER9_CC2(0x3, 0x7) +#define TIMER9_CC2_PD8 SILABS_DBUS_TIMER9_CC2(0x3, 0x8) +#define TIMER9_CC2_PD9 SILABS_DBUS_TIMER9_CC2(0x3, 0x9) +#define TIMER9_CC2_PD10 SILABS_DBUS_TIMER9_CC2(0x3, 0xa) +#define TIMER9_CC2_PD11 SILABS_DBUS_TIMER9_CC2(0x3, 0xb) +#define TIMER9_CC2_PD12 SILABS_DBUS_TIMER9_CC2(0x3, 0xc) +#define TIMER9_CC2_PD13 SILABS_DBUS_TIMER9_CC2(0x3, 0xd) +#define TIMER9_CC2_PD14 SILABS_DBUS_TIMER9_CC2(0x3, 0xe) +#define TIMER9_CC2_PD15 SILABS_DBUS_TIMER9_CC2(0x3, 0xf) +#define TIMER9_CDTI0_PA0 SILABS_DBUS_TIMER9_CDTI0(0x0, 0x0) +#define TIMER9_CDTI0_PA1 SILABS_DBUS_TIMER9_CDTI0(0x0, 0x1) +#define TIMER9_CDTI0_PA2 SILABS_DBUS_TIMER9_CDTI0(0x0, 0x2) +#define TIMER9_CDTI0_PA3 SILABS_DBUS_TIMER9_CDTI0(0x0, 0x3) +#define TIMER9_CDTI0_PA4 SILABS_DBUS_TIMER9_CDTI0(0x0, 0x4) +#define TIMER9_CDTI0_PA5 SILABS_DBUS_TIMER9_CDTI0(0x0, 0x5) +#define TIMER9_CDTI0_PA6 SILABS_DBUS_TIMER9_CDTI0(0x0, 0x6) +#define TIMER9_CDTI0_PA7 SILABS_DBUS_TIMER9_CDTI0(0x0, 0x7) +#define TIMER9_CDTI0_PA8 SILABS_DBUS_TIMER9_CDTI0(0x0, 0x8) +#define TIMER9_CDTI0_PA9 SILABS_DBUS_TIMER9_CDTI0(0x0, 0x9) +#define TIMER9_CDTI0_PA10 SILABS_DBUS_TIMER9_CDTI0(0x0, 0xa) +#define TIMER9_CDTI0_PA11 SILABS_DBUS_TIMER9_CDTI0(0x0, 0xb) +#define TIMER9_CDTI0_PA12 SILABS_DBUS_TIMER9_CDTI0(0x0, 0xc) +#define TIMER9_CDTI0_PA13 SILABS_DBUS_TIMER9_CDTI0(0x0, 0xd) +#define TIMER9_CDTI0_PA14 SILABS_DBUS_TIMER9_CDTI0(0x0, 0xe) +#define TIMER9_CDTI0_PA15 SILABS_DBUS_TIMER9_CDTI0(0x0, 0xf) +#define TIMER9_CDTI0_PB0 SILABS_DBUS_TIMER9_CDTI0(0x1, 0x0) +#define TIMER9_CDTI0_PB1 SILABS_DBUS_TIMER9_CDTI0(0x1, 0x1) +#define TIMER9_CDTI0_PB2 SILABS_DBUS_TIMER9_CDTI0(0x1, 0x2) +#define TIMER9_CDTI0_PB3 SILABS_DBUS_TIMER9_CDTI0(0x1, 0x3) +#define TIMER9_CDTI0_PB4 SILABS_DBUS_TIMER9_CDTI0(0x1, 0x4) +#define TIMER9_CDTI0_PB5 SILABS_DBUS_TIMER9_CDTI0(0x1, 0x5) +#define TIMER9_CDTI0_PB6 SILABS_DBUS_TIMER9_CDTI0(0x1, 0x6) +#define TIMER9_CDTI0_PB7 SILABS_DBUS_TIMER9_CDTI0(0x1, 0x7) +#define TIMER9_CDTI0_PB8 SILABS_DBUS_TIMER9_CDTI0(0x1, 0x8) +#define TIMER9_CDTI0_PB9 SILABS_DBUS_TIMER9_CDTI0(0x1, 0x9) +#define TIMER9_CDTI0_PB10 SILABS_DBUS_TIMER9_CDTI0(0x1, 0xa) +#define TIMER9_CDTI0_PB11 SILABS_DBUS_TIMER9_CDTI0(0x1, 0xb) +#define TIMER9_CDTI0_PB12 SILABS_DBUS_TIMER9_CDTI0(0x1, 0xc) +#define TIMER9_CDTI0_PB13 SILABS_DBUS_TIMER9_CDTI0(0x1, 0xd) +#define TIMER9_CDTI0_PB14 SILABS_DBUS_TIMER9_CDTI0(0x1, 0xe) +#define TIMER9_CDTI0_PB15 SILABS_DBUS_TIMER9_CDTI0(0x1, 0xf) +#define TIMER9_CDTI0_PC0 SILABS_DBUS_TIMER9_CDTI0(0x2, 0x0) +#define TIMER9_CDTI0_PC1 SILABS_DBUS_TIMER9_CDTI0(0x2, 0x1) +#define TIMER9_CDTI0_PC2 SILABS_DBUS_TIMER9_CDTI0(0x2, 0x2) +#define TIMER9_CDTI0_PC3 SILABS_DBUS_TIMER9_CDTI0(0x2, 0x3) +#define TIMER9_CDTI0_PC4 SILABS_DBUS_TIMER9_CDTI0(0x2, 0x4) +#define TIMER9_CDTI0_PC5 SILABS_DBUS_TIMER9_CDTI0(0x2, 0x5) +#define TIMER9_CDTI0_PC6 SILABS_DBUS_TIMER9_CDTI0(0x2, 0x6) +#define TIMER9_CDTI0_PC7 SILABS_DBUS_TIMER9_CDTI0(0x2, 0x7) +#define TIMER9_CDTI0_PC8 SILABS_DBUS_TIMER9_CDTI0(0x2, 0x8) +#define TIMER9_CDTI0_PC9 SILABS_DBUS_TIMER9_CDTI0(0x2, 0x9) +#define TIMER9_CDTI0_PC10 SILABS_DBUS_TIMER9_CDTI0(0x2, 0xa) +#define TIMER9_CDTI0_PC11 SILABS_DBUS_TIMER9_CDTI0(0x2, 0xb) +#define TIMER9_CDTI0_PC12 SILABS_DBUS_TIMER9_CDTI0(0x2, 0xc) +#define TIMER9_CDTI0_PC13 SILABS_DBUS_TIMER9_CDTI0(0x2, 0xd) +#define TIMER9_CDTI0_PC14 SILABS_DBUS_TIMER9_CDTI0(0x2, 0xe) +#define TIMER9_CDTI0_PC15 SILABS_DBUS_TIMER9_CDTI0(0x2, 0xf) +#define TIMER9_CDTI0_PD0 SILABS_DBUS_TIMER9_CDTI0(0x3, 0x0) +#define TIMER9_CDTI0_PD1 SILABS_DBUS_TIMER9_CDTI0(0x3, 0x1) +#define TIMER9_CDTI0_PD2 SILABS_DBUS_TIMER9_CDTI0(0x3, 0x2) +#define TIMER9_CDTI0_PD3 SILABS_DBUS_TIMER9_CDTI0(0x3, 0x3) +#define TIMER9_CDTI0_PD4 SILABS_DBUS_TIMER9_CDTI0(0x3, 0x4) +#define TIMER9_CDTI0_PD5 SILABS_DBUS_TIMER9_CDTI0(0x3, 0x5) +#define TIMER9_CDTI0_PD6 SILABS_DBUS_TIMER9_CDTI0(0x3, 0x6) +#define TIMER9_CDTI0_PD7 SILABS_DBUS_TIMER9_CDTI0(0x3, 0x7) +#define TIMER9_CDTI0_PD8 SILABS_DBUS_TIMER9_CDTI0(0x3, 0x8) +#define TIMER9_CDTI0_PD9 SILABS_DBUS_TIMER9_CDTI0(0x3, 0x9) +#define TIMER9_CDTI0_PD10 SILABS_DBUS_TIMER9_CDTI0(0x3, 0xa) +#define TIMER9_CDTI0_PD11 SILABS_DBUS_TIMER9_CDTI0(0x3, 0xb) +#define TIMER9_CDTI0_PD12 SILABS_DBUS_TIMER9_CDTI0(0x3, 0xc) +#define TIMER9_CDTI0_PD13 SILABS_DBUS_TIMER9_CDTI0(0x3, 0xd) +#define TIMER9_CDTI0_PD14 SILABS_DBUS_TIMER9_CDTI0(0x3, 0xe) +#define TIMER9_CDTI0_PD15 SILABS_DBUS_TIMER9_CDTI0(0x3, 0xf) +#define TIMER9_CDTI1_PA0 SILABS_DBUS_TIMER9_CDTI1(0x0, 0x0) +#define TIMER9_CDTI1_PA1 SILABS_DBUS_TIMER9_CDTI1(0x0, 0x1) +#define TIMER9_CDTI1_PA2 SILABS_DBUS_TIMER9_CDTI1(0x0, 0x2) +#define TIMER9_CDTI1_PA3 SILABS_DBUS_TIMER9_CDTI1(0x0, 0x3) +#define TIMER9_CDTI1_PA4 SILABS_DBUS_TIMER9_CDTI1(0x0, 0x4) +#define TIMER9_CDTI1_PA5 SILABS_DBUS_TIMER9_CDTI1(0x0, 0x5) +#define TIMER9_CDTI1_PA6 SILABS_DBUS_TIMER9_CDTI1(0x0, 0x6) +#define TIMER9_CDTI1_PA7 SILABS_DBUS_TIMER9_CDTI1(0x0, 0x7) +#define TIMER9_CDTI1_PA8 SILABS_DBUS_TIMER9_CDTI1(0x0, 0x8) +#define TIMER9_CDTI1_PA9 SILABS_DBUS_TIMER9_CDTI1(0x0, 0x9) +#define TIMER9_CDTI1_PA10 SILABS_DBUS_TIMER9_CDTI1(0x0, 0xa) +#define TIMER9_CDTI1_PA11 SILABS_DBUS_TIMER9_CDTI1(0x0, 0xb) +#define TIMER9_CDTI1_PA12 SILABS_DBUS_TIMER9_CDTI1(0x0, 0xc) +#define TIMER9_CDTI1_PA13 SILABS_DBUS_TIMER9_CDTI1(0x0, 0xd) +#define TIMER9_CDTI1_PA14 SILABS_DBUS_TIMER9_CDTI1(0x0, 0xe) +#define TIMER9_CDTI1_PA15 SILABS_DBUS_TIMER9_CDTI1(0x0, 0xf) +#define TIMER9_CDTI1_PB0 SILABS_DBUS_TIMER9_CDTI1(0x1, 0x0) +#define TIMER9_CDTI1_PB1 SILABS_DBUS_TIMER9_CDTI1(0x1, 0x1) +#define TIMER9_CDTI1_PB2 SILABS_DBUS_TIMER9_CDTI1(0x1, 0x2) +#define TIMER9_CDTI1_PB3 SILABS_DBUS_TIMER9_CDTI1(0x1, 0x3) +#define TIMER9_CDTI1_PB4 SILABS_DBUS_TIMER9_CDTI1(0x1, 0x4) +#define TIMER9_CDTI1_PB5 SILABS_DBUS_TIMER9_CDTI1(0x1, 0x5) +#define TIMER9_CDTI1_PB6 SILABS_DBUS_TIMER9_CDTI1(0x1, 0x6) +#define TIMER9_CDTI1_PB7 SILABS_DBUS_TIMER9_CDTI1(0x1, 0x7) +#define TIMER9_CDTI1_PB8 SILABS_DBUS_TIMER9_CDTI1(0x1, 0x8) +#define TIMER9_CDTI1_PB9 SILABS_DBUS_TIMER9_CDTI1(0x1, 0x9) +#define TIMER9_CDTI1_PB10 SILABS_DBUS_TIMER9_CDTI1(0x1, 0xa) +#define TIMER9_CDTI1_PB11 SILABS_DBUS_TIMER9_CDTI1(0x1, 0xb) +#define TIMER9_CDTI1_PB12 SILABS_DBUS_TIMER9_CDTI1(0x1, 0xc) +#define TIMER9_CDTI1_PB13 SILABS_DBUS_TIMER9_CDTI1(0x1, 0xd) +#define TIMER9_CDTI1_PB14 SILABS_DBUS_TIMER9_CDTI1(0x1, 0xe) +#define TIMER9_CDTI1_PB15 SILABS_DBUS_TIMER9_CDTI1(0x1, 0xf) +#define TIMER9_CDTI1_PC0 SILABS_DBUS_TIMER9_CDTI1(0x2, 0x0) +#define TIMER9_CDTI1_PC1 SILABS_DBUS_TIMER9_CDTI1(0x2, 0x1) +#define TIMER9_CDTI1_PC2 SILABS_DBUS_TIMER9_CDTI1(0x2, 0x2) +#define TIMER9_CDTI1_PC3 SILABS_DBUS_TIMER9_CDTI1(0x2, 0x3) +#define TIMER9_CDTI1_PC4 SILABS_DBUS_TIMER9_CDTI1(0x2, 0x4) +#define TIMER9_CDTI1_PC5 SILABS_DBUS_TIMER9_CDTI1(0x2, 0x5) +#define TIMER9_CDTI1_PC6 SILABS_DBUS_TIMER9_CDTI1(0x2, 0x6) +#define TIMER9_CDTI1_PC7 SILABS_DBUS_TIMER9_CDTI1(0x2, 0x7) +#define TIMER9_CDTI1_PC8 SILABS_DBUS_TIMER9_CDTI1(0x2, 0x8) +#define TIMER9_CDTI1_PC9 SILABS_DBUS_TIMER9_CDTI1(0x2, 0x9) +#define TIMER9_CDTI1_PC10 SILABS_DBUS_TIMER9_CDTI1(0x2, 0xa) +#define TIMER9_CDTI1_PC11 SILABS_DBUS_TIMER9_CDTI1(0x2, 0xb) +#define TIMER9_CDTI1_PC12 SILABS_DBUS_TIMER9_CDTI1(0x2, 0xc) +#define TIMER9_CDTI1_PC13 SILABS_DBUS_TIMER9_CDTI1(0x2, 0xd) +#define TIMER9_CDTI1_PC14 SILABS_DBUS_TIMER9_CDTI1(0x2, 0xe) +#define TIMER9_CDTI1_PC15 SILABS_DBUS_TIMER9_CDTI1(0x2, 0xf) +#define TIMER9_CDTI1_PD0 SILABS_DBUS_TIMER9_CDTI1(0x3, 0x0) +#define TIMER9_CDTI1_PD1 SILABS_DBUS_TIMER9_CDTI1(0x3, 0x1) +#define TIMER9_CDTI1_PD2 SILABS_DBUS_TIMER9_CDTI1(0x3, 0x2) +#define TIMER9_CDTI1_PD3 SILABS_DBUS_TIMER9_CDTI1(0x3, 0x3) +#define TIMER9_CDTI1_PD4 SILABS_DBUS_TIMER9_CDTI1(0x3, 0x4) +#define TIMER9_CDTI1_PD5 SILABS_DBUS_TIMER9_CDTI1(0x3, 0x5) +#define TIMER9_CDTI1_PD6 SILABS_DBUS_TIMER9_CDTI1(0x3, 0x6) +#define TIMER9_CDTI1_PD7 SILABS_DBUS_TIMER9_CDTI1(0x3, 0x7) +#define TIMER9_CDTI1_PD8 SILABS_DBUS_TIMER9_CDTI1(0x3, 0x8) +#define TIMER9_CDTI1_PD9 SILABS_DBUS_TIMER9_CDTI1(0x3, 0x9) +#define TIMER9_CDTI1_PD10 SILABS_DBUS_TIMER9_CDTI1(0x3, 0xa) +#define TIMER9_CDTI1_PD11 SILABS_DBUS_TIMER9_CDTI1(0x3, 0xb) +#define TIMER9_CDTI1_PD12 SILABS_DBUS_TIMER9_CDTI1(0x3, 0xc) +#define TIMER9_CDTI1_PD13 SILABS_DBUS_TIMER9_CDTI1(0x3, 0xd) +#define TIMER9_CDTI1_PD14 SILABS_DBUS_TIMER9_CDTI1(0x3, 0xe) +#define TIMER9_CDTI1_PD15 SILABS_DBUS_TIMER9_CDTI1(0x3, 0xf) +#define TIMER9_CDTI2_PA0 SILABS_DBUS_TIMER9_CDTI2(0x0, 0x0) +#define TIMER9_CDTI2_PA1 SILABS_DBUS_TIMER9_CDTI2(0x0, 0x1) +#define TIMER9_CDTI2_PA2 SILABS_DBUS_TIMER9_CDTI2(0x0, 0x2) +#define TIMER9_CDTI2_PA3 SILABS_DBUS_TIMER9_CDTI2(0x0, 0x3) +#define TIMER9_CDTI2_PA4 SILABS_DBUS_TIMER9_CDTI2(0x0, 0x4) +#define TIMER9_CDTI2_PA5 SILABS_DBUS_TIMER9_CDTI2(0x0, 0x5) +#define TIMER9_CDTI2_PA6 SILABS_DBUS_TIMER9_CDTI2(0x0, 0x6) +#define TIMER9_CDTI2_PA7 SILABS_DBUS_TIMER9_CDTI2(0x0, 0x7) +#define TIMER9_CDTI2_PA8 SILABS_DBUS_TIMER9_CDTI2(0x0, 0x8) +#define TIMER9_CDTI2_PA9 SILABS_DBUS_TIMER9_CDTI2(0x0, 0x9) +#define TIMER9_CDTI2_PA10 SILABS_DBUS_TIMER9_CDTI2(0x0, 0xa) +#define TIMER9_CDTI2_PA11 SILABS_DBUS_TIMER9_CDTI2(0x0, 0xb) +#define TIMER9_CDTI2_PA12 SILABS_DBUS_TIMER9_CDTI2(0x0, 0xc) +#define TIMER9_CDTI2_PA13 SILABS_DBUS_TIMER9_CDTI2(0x0, 0xd) +#define TIMER9_CDTI2_PA14 SILABS_DBUS_TIMER9_CDTI2(0x0, 0xe) +#define TIMER9_CDTI2_PA15 SILABS_DBUS_TIMER9_CDTI2(0x0, 0xf) +#define TIMER9_CDTI2_PB0 SILABS_DBUS_TIMER9_CDTI2(0x1, 0x0) +#define TIMER9_CDTI2_PB1 SILABS_DBUS_TIMER9_CDTI2(0x1, 0x1) +#define TIMER9_CDTI2_PB2 SILABS_DBUS_TIMER9_CDTI2(0x1, 0x2) +#define TIMER9_CDTI2_PB3 SILABS_DBUS_TIMER9_CDTI2(0x1, 0x3) +#define TIMER9_CDTI2_PB4 SILABS_DBUS_TIMER9_CDTI2(0x1, 0x4) +#define TIMER9_CDTI2_PB5 SILABS_DBUS_TIMER9_CDTI2(0x1, 0x5) +#define TIMER9_CDTI2_PB6 SILABS_DBUS_TIMER9_CDTI2(0x1, 0x6) +#define TIMER9_CDTI2_PB7 SILABS_DBUS_TIMER9_CDTI2(0x1, 0x7) +#define TIMER9_CDTI2_PB8 SILABS_DBUS_TIMER9_CDTI2(0x1, 0x8) +#define TIMER9_CDTI2_PB9 SILABS_DBUS_TIMER9_CDTI2(0x1, 0x9) +#define TIMER9_CDTI2_PB10 SILABS_DBUS_TIMER9_CDTI2(0x1, 0xa) +#define TIMER9_CDTI2_PB11 SILABS_DBUS_TIMER9_CDTI2(0x1, 0xb) +#define TIMER9_CDTI2_PB12 SILABS_DBUS_TIMER9_CDTI2(0x1, 0xc) +#define TIMER9_CDTI2_PB13 SILABS_DBUS_TIMER9_CDTI2(0x1, 0xd) +#define TIMER9_CDTI2_PB14 SILABS_DBUS_TIMER9_CDTI2(0x1, 0xe) +#define TIMER9_CDTI2_PB15 SILABS_DBUS_TIMER9_CDTI2(0x1, 0xf) +#define TIMER9_CDTI2_PC0 SILABS_DBUS_TIMER9_CDTI2(0x2, 0x0) +#define TIMER9_CDTI2_PC1 SILABS_DBUS_TIMER9_CDTI2(0x2, 0x1) +#define TIMER9_CDTI2_PC2 SILABS_DBUS_TIMER9_CDTI2(0x2, 0x2) +#define TIMER9_CDTI2_PC3 SILABS_DBUS_TIMER9_CDTI2(0x2, 0x3) +#define TIMER9_CDTI2_PC4 SILABS_DBUS_TIMER9_CDTI2(0x2, 0x4) +#define TIMER9_CDTI2_PC5 SILABS_DBUS_TIMER9_CDTI2(0x2, 0x5) +#define TIMER9_CDTI2_PC6 SILABS_DBUS_TIMER9_CDTI2(0x2, 0x6) +#define TIMER9_CDTI2_PC7 SILABS_DBUS_TIMER9_CDTI2(0x2, 0x7) +#define TIMER9_CDTI2_PC8 SILABS_DBUS_TIMER9_CDTI2(0x2, 0x8) +#define TIMER9_CDTI2_PC9 SILABS_DBUS_TIMER9_CDTI2(0x2, 0x9) +#define TIMER9_CDTI2_PC10 SILABS_DBUS_TIMER9_CDTI2(0x2, 0xa) +#define TIMER9_CDTI2_PC11 SILABS_DBUS_TIMER9_CDTI2(0x2, 0xb) +#define TIMER9_CDTI2_PC12 SILABS_DBUS_TIMER9_CDTI2(0x2, 0xc) +#define TIMER9_CDTI2_PC13 SILABS_DBUS_TIMER9_CDTI2(0x2, 0xd) +#define TIMER9_CDTI2_PC14 SILABS_DBUS_TIMER9_CDTI2(0x2, 0xe) +#define TIMER9_CDTI2_PC15 SILABS_DBUS_TIMER9_CDTI2(0x2, 0xf) +#define TIMER9_CDTI2_PD0 SILABS_DBUS_TIMER9_CDTI2(0x3, 0x0) +#define TIMER9_CDTI2_PD1 SILABS_DBUS_TIMER9_CDTI2(0x3, 0x1) +#define TIMER9_CDTI2_PD2 SILABS_DBUS_TIMER9_CDTI2(0x3, 0x2) +#define TIMER9_CDTI2_PD3 SILABS_DBUS_TIMER9_CDTI2(0x3, 0x3) +#define TIMER9_CDTI2_PD4 SILABS_DBUS_TIMER9_CDTI2(0x3, 0x4) +#define TIMER9_CDTI2_PD5 SILABS_DBUS_TIMER9_CDTI2(0x3, 0x5) +#define TIMER9_CDTI2_PD6 SILABS_DBUS_TIMER9_CDTI2(0x3, 0x6) +#define TIMER9_CDTI2_PD7 SILABS_DBUS_TIMER9_CDTI2(0x3, 0x7) +#define TIMER9_CDTI2_PD8 SILABS_DBUS_TIMER9_CDTI2(0x3, 0x8) +#define TIMER9_CDTI2_PD9 SILABS_DBUS_TIMER9_CDTI2(0x3, 0x9) +#define TIMER9_CDTI2_PD10 SILABS_DBUS_TIMER9_CDTI2(0x3, 0xa) +#define TIMER9_CDTI2_PD11 SILABS_DBUS_TIMER9_CDTI2(0x3, 0xb) +#define TIMER9_CDTI2_PD12 SILABS_DBUS_TIMER9_CDTI2(0x3, 0xc) +#define TIMER9_CDTI2_PD13 SILABS_DBUS_TIMER9_CDTI2(0x3, 0xd) +#define TIMER9_CDTI2_PD14 SILABS_DBUS_TIMER9_CDTI2(0x3, 0xe) +#define TIMER9_CDTI2_PD15 SILABS_DBUS_TIMER9_CDTI2(0x3, 0xf) + +#define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0) +#define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1) +#define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2) +#define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3) +#define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4) +#define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5) +#define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6) +#define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7) +#define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8) +#define USART0_CS_PA9 SILABS_DBUS_USART0_CS(0x0, 0x9) +#define USART0_CS_PA10 SILABS_DBUS_USART0_CS(0x0, 0xa) +#define USART0_CS_PA11 SILABS_DBUS_USART0_CS(0x0, 0xb) +#define USART0_CS_PA12 SILABS_DBUS_USART0_CS(0x0, 0xc) +#define USART0_CS_PA13 SILABS_DBUS_USART0_CS(0x0, 0xd) +#define USART0_CS_PA14 SILABS_DBUS_USART0_CS(0x0, 0xe) +#define USART0_CS_PA15 SILABS_DBUS_USART0_CS(0x0, 0xf) +#define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0) +#define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1) +#define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2) +#define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3) +#define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4) +#define USART0_CS_PB5 SILABS_DBUS_USART0_CS(0x1, 0x5) +#define USART0_CS_PB6 SILABS_DBUS_USART0_CS(0x1, 0x6) +#define USART0_CS_PB7 SILABS_DBUS_USART0_CS(0x1, 0x7) +#define USART0_CS_PB8 SILABS_DBUS_USART0_CS(0x1, 0x8) +#define USART0_CS_PB9 SILABS_DBUS_USART0_CS(0x1, 0x9) +#define USART0_CS_PB10 SILABS_DBUS_USART0_CS(0x1, 0xa) +#define USART0_CS_PB11 SILABS_DBUS_USART0_CS(0x1, 0xb) +#define USART0_CS_PB12 SILABS_DBUS_USART0_CS(0x1, 0xc) +#define USART0_CS_PB13 SILABS_DBUS_USART0_CS(0x1, 0xd) +#define USART0_CS_PB14 SILABS_DBUS_USART0_CS(0x1, 0xe) +#define USART0_CS_PB15 SILABS_DBUS_USART0_CS(0x1, 0xf) +#define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0) +#define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1) +#define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2) +#define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3) +#define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4) +#define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5) +#define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6) +#define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7) +#define USART0_CS_PC8 SILABS_DBUS_USART0_CS(0x2, 0x8) +#define USART0_CS_PC9 SILABS_DBUS_USART0_CS(0x2, 0x9) +#define USART0_CS_PC10 SILABS_DBUS_USART0_CS(0x2, 0xa) +#define USART0_CS_PC11 SILABS_DBUS_USART0_CS(0x2, 0xb) +#define USART0_CS_PC12 SILABS_DBUS_USART0_CS(0x2, 0xc) +#define USART0_CS_PC13 SILABS_DBUS_USART0_CS(0x2, 0xd) +#define USART0_CS_PC14 SILABS_DBUS_USART0_CS(0x2, 0xe) +#define USART0_CS_PC15 SILABS_DBUS_USART0_CS(0x2, 0xf) +#define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0) +#define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1) +#define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2) +#define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3) +#define USART0_CS_PD4 SILABS_DBUS_USART0_CS(0x3, 0x4) +#define USART0_CS_PD5 SILABS_DBUS_USART0_CS(0x3, 0x5) +#define USART0_CS_PD6 SILABS_DBUS_USART0_CS(0x3, 0x6) +#define USART0_CS_PD7 SILABS_DBUS_USART0_CS(0x3, 0x7) +#define USART0_CS_PD8 SILABS_DBUS_USART0_CS(0x3, 0x8) +#define USART0_CS_PD9 SILABS_DBUS_USART0_CS(0x3, 0x9) +#define USART0_CS_PD10 SILABS_DBUS_USART0_CS(0x3, 0xa) +#define USART0_CS_PD11 SILABS_DBUS_USART0_CS(0x3, 0xb) +#define USART0_CS_PD12 SILABS_DBUS_USART0_CS(0x3, 0xc) +#define USART0_CS_PD13 SILABS_DBUS_USART0_CS(0x3, 0xd) +#define USART0_CS_PD14 SILABS_DBUS_USART0_CS(0x3, 0xe) +#define USART0_CS_PD15 SILABS_DBUS_USART0_CS(0x3, 0xf) +#define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0) +#define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1) +#define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2) +#define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3) +#define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4) +#define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5) +#define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6) +#define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7) +#define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8) +#define USART0_RTS_PA9 SILABS_DBUS_USART0_RTS(0x0, 0x9) +#define USART0_RTS_PA10 SILABS_DBUS_USART0_RTS(0x0, 0xa) +#define USART0_RTS_PA11 SILABS_DBUS_USART0_RTS(0x0, 0xb) +#define USART0_RTS_PA12 SILABS_DBUS_USART0_RTS(0x0, 0xc) +#define USART0_RTS_PA13 SILABS_DBUS_USART0_RTS(0x0, 0xd) +#define USART0_RTS_PA14 SILABS_DBUS_USART0_RTS(0x0, 0xe) +#define USART0_RTS_PA15 SILABS_DBUS_USART0_RTS(0x0, 0xf) +#define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0) +#define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1) +#define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2) +#define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3) +#define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4) +#define USART0_RTS_PB5 SILABS_DBUS_USART0_RTS(0x1, 0x5) +#define USART0_RTS_PB6 SILABS_DBUS_USART0_RTS(0x1, 0x6) +#define USART0_RTS_PB7 SILABS_DBUS_USART0_RTS(0x1, 0x7) +#define USART0_RTS_PB8 SILABS_DBUS_USART0_RTS(0x1, 0x8) +#define USART0_RTS_PB9 SILABS_DBUS_USART0_RTS(0x1, 0x9) +#define USART0_RTS_PB10 SILABS_DBUS_USART0_RTS(0x1, 0xa) +#define USART0_RTS_PB11 SILABS_DBUS_USART0_RTS(0x1, 0xb) +#define USART0_RTS_PB12 SILABS_DBUS_USART0_RTS(0x1, 0xc) +#define USART0_RTS_PB13 SILABS_DBUS_USART0_RTS(0x1, 0xd) +#define USART0_RTS_PB14 SILABS_DBUS_USART0_RTS(0x1, 0xe) +#define USART0_RTS_PB15 SILABS_DBUS_USART0_RTS(0x1, 0xf) +#define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0) +#define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1) +#define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2) +#define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3) +#define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4) +#define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5) +#define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6) +#define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7) +#define USART0_RTS_PC8 SILABS_DBUS_USART0_RTS(0x2, 0x8) +#define USART0_RTS_PC9 SILABS_DBUS_USART0_RTS(0x2, 0x9) +#define USART0_RTS_PC10 SILABS_DBUS_USART0_RTS(0x2, 0xa) +#define USART0_RTS_PC11 SILABS_DBUS_USART0_RTS(0x2, 0xb) +#define USART0_RTS_PC12 SILABS_DBUS_USART0_RTS(0x2, 0xc) +#define USART0_RTS_PC13 SILABS_DBUS_USART0_RTS(0x2, 0xd) +#define USART0_RTS_PC14 SILABS_DBUS_USART0_RTS(0x2, 0xe) +#define USART0_RTS_PC15 SILABS_DBUS_USART0_RTS(0x2, 0xf) +#define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0) +#define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1) +#define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2) +#define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3) +#define USART0_RTS_PD4 SILABS_DBUS_USART0_RTS(0x3, 0x4) +#define USART0_RTS_PD5 SILABS_DBUS_USART0_RTS(0x3, 0x5) +#define USART0_RTS_PD6 SILABS_DBUS_USART0_RTS(0x3, 0x6) +#define USART0_RTS_PD7 SILABS_DBUS_USART0_RTS(0x3, 0x7) +#define USART0_RTS_PD8 SILABS_DBUS_USART0_RTS(0x3, 0x8) +#define USART0_RTS_PD9 SILABS_DBUS_USART0_RTS(0x3, 0x9) +#define USART0_RTS_PD10 SILABS_DBUS_USART0_RTS(0x3, 0xa) +#define USART0_RTS_PD11 SILABS_DBUS_USART0_RTS(0x3, 0xb) +#define USART0_RTS_PD12 SILABS_DBUS_USART0_RTS(0x3, 0xc) +#define USART0_RTS_PD13 SILABS_DBUS_USART0_RTS(0x3, 0xd) +#define USART0_RTS_PD14 SILABS_DBUS_USART0_RTS(0x3, 0xe) +#define USART0_RTS_PD15 SILABS_DBUS_USART0_RTS(0x3, 0xf) +#define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0) +#define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1) +#define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2) +#define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3) +#define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4) +#define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5) +#define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6) +#define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7) +#define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8) +#define USART0_RX_PA9 SILABS_DBUS_USART0_RX(0x0, 0x9) +#define USART0_RX_PA10 SILABS_DBUS_USART0_RX(0x0, 0xa) +#define USART0_RX_PA11 SILABS_DBUS_USART0_RX(0x0, 0xb) +#define USART0_RX_PA12 SILABS_DBUS_USART0_RX(0x0, 0xc) +#define USART0_RX_PA13 SILABS_DBUS_USART0_RX(0x0, 0xd) +#define USART0_RX_PA14 SILABS_DBUS_USART0_RX(0x0, 0xe) +#define USART0_RX_PA15 SILABS_DBUS_USART0_RX(0x0, 0xf) +#define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0) +#define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1) +#define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2) +#define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3) +#define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4) +#define USART0_RX_PB5 SILABS_DBUS_USART0_RX(0x1, 0x5) +#define USART0_RX_PB6 SILABS_DBUS_USART0_RX(0x1, 0x6) +#define USART0_RX_PB7 SILABS_DBUS_USART0_RX(0x1, 0x7) +#define USART0_RX_PB8 SILABS_DBUS_USART0_RX(0x1, 0x8) +#define USART0_RX_PB9 SILABS_DBUS_USART0_RX(0x1, 0x9) +#define USART0_RX_PB10 SILABS_DBUS_USART0_RX(0x1, 0xa) +#define USART0_RX_PB11 SILABS_DBUS_USART0_RX(0x1, 0xb) +#define USART0_RX_PB12 SILABS_DBUS_USART0_RX(0x1, 0xc) +#define USART0_RX_PB13 SILABS_DBUS_USART0_RX(0x1, 0xd) +#define USART0_RX_PB14 SILABS_DBUS_USART0_RX(0x1, 0xe) +#define USART0_RX_PB15 SILABS_DBUS_USART0_RX(0x1, 0xf) +#define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0) +#define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1) +#define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2) +#define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3) +#define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4) +#define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5) +#define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6) +#define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7) +#define USART0_RX_PC8 SILABS_DBUS_USART0_RX(0x2, 0x8) +#define USART0_RX_PC9 SILABS_DBUS_USART0_RX(0x2, 0x9) +#define USART0_RX_PC10 SILABS_DBUS_USART0_RX(0x2, 0xa) +#define USART0_RX_PC11 SILABS_DBUS_USART0_RX(0x2, 0xb) +#define USART0_RX_PC12 SILABS_DBUS_USART0_RX(0x2, 0xc) +#define USART0_RX_PC13 SILABS_DBUS_USART0_RX(0x2, 0xd) +#define USART0_RX_PC14 SILABS_DBUS_USART0_RX(0x2, 0xe) +#define USART0_RX_PC15 SILABS_DBUS_USART0_RX(0x2, 0xf) +#define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0) +#define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1) +#define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2) +#define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3) +#define USART0_RX_PD4 SILABS_DBUS_USART0_RX(0x3, 0x4) +#define USART0_RX_PD5 SILABS_DBUS_USART0_RX(0x3, 0x5) +#define USART0_RX_PD6 SILABS_DBUS_USART0_RX(0x3, 0x6) +#define USART0_RX_PD7 SILABS_DBUS_USART0_RX(0x3, 0x7) +#define USART0_RX_PD8 SILABS_DBUS_USART0_RX(0x3, 0x8) +#define USART0_RX_PD9 SILABS_DBUS_USART0_RX(0x3, 0x9) +#define USART0_RX_PD10 SILABS_DBUS_USART0_RX(0x3, 0xa) +#define USART0_RX_PD11 SILABS_DBUS_USART0_RX(0x3, 0xb) +#define USART0_RX_PD12 SILABS_DBUS_USART0_RX(0x3, 0xc) +#define USART0_RX_PD13 SILABS_DBUS_USART0_RX(0x3, 0xd) +#define USART0_RX_PD14 SILABS_DBUS_USART0_RX(0x3, 0xe) +#define USART0_RX_PD15 SILABS_DBUS_USART0_RX(0x3, 0xf) +#define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0) +#define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1) +#define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2) +#define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3) +#define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4) +#define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5) +#define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6) +#define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7) +#define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8) +#define USART0_CLK_PA9 SILABS_DBUS_USART0_CLK(0x0, 0x9) +#define USART0_CLK_PA10 SILABS_DBUS_USART0_CLK(0x0, 0xa) +#define USART0_CLK_PA11 SILABS_DBUS_USART0_CLK(0x0, 0xb) +#define USART0_CLK_PA12 SILABS_DBUS_USART0_CLK(0x0, 0xc) +#define USART0_CLK_PA13 SILABS_DBUS_USART0_CLK(0x0, 0xd) +#define USART0_CLK_PA14 SILABS_DBUS_USART0_CLK(0x0, 0xe) +#define USART0_CLK_PA15 SILABS_DBUS_USART0_CLK(0x0, 0xf) +#define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0) +#define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1) +#define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2) +#define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3) +#define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4) +#define USART0_CLK_PB5 SILABS_DBUS_USART0_CLK(0x1, 0x5) +#define USART0_CLK_PB6 SILABS_DBUS_USART0_CLK(0x1, 0x6) +#define USART0_CLK_PB7 SILABS_DBUS_USART0_CLK(0x1, 0x7) +#define USART0_CLK_PB8 SILABS_DBUS_USART0_CLK(0x1, 0x8) +#define USART0_CLK_PB9 SILABS_DBUS_USART0_CLK(0x1, 0x9) +#define USART0_CLK_PB10 SILABS_DBUS_USART0_CLK(0x1, 0xa) +#define USART0_CLK_PB11 SILABS_DBUS_USART0_CLK(0x1, 0xb) +#define USART0_CLK_PB12 SILABS_DBUS_USART0_CLK(0x1, 0xc) +#define USART0_CLK_PB13 SILABS_DBUS_USART0_CLK(0x1, 0xd) +#define USART0_CLK_PB14 SILABS_DBUS_USART0_CLK(0x1, 0xe) +#define USART0_CLK_PB15 SILABS_DBUS_USART0_CLK(0x1, 0xf) +#define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0) +#define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1) +#define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2) +#define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3) +#define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4) +#define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5) +#define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6) +#define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7) +#define USART0_CLK_PC8 SILABS_DBUS_USART0_CLK(0x2, 0x8) +#define USART0_CLK_PC9 SILABS_DBUS_USART0_CLK(0x2, 0x9) +#define USART0_CLK_PC10 SILABS_DBUS_USART0_CLK(0x2, 0xa) +#define USART0_CLK_PC11 SILABS_DBUS_USART0_CLK(0x2, 0xb) +#define USART0_CLK_PC12 SILABS_DBUS_USART0_CLK(0x2, 0xc) +#define USART0_CLK_PC13 SILABS_DBUS_USART0_CLK(0x2, 0xd) +#define USART0_CLK_PC14 SILABS_DBUS_USART0_CLK(0x2, 0xe) +#define USART0_CLK_PC15 SILABS_DBUS_USART0_CLK(0x2, 0xf) +#define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0) +#define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1) +#define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2) +#define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3) +#define USART0_CLK_PD4 SILABS_DBUS_USART0_CLK(0x3, 0x4) +#define USART0_CLK_PD5 SILABS_DBUS_USART0_CLK(0x3, 0x5) +#define USART0_CLK_PD6 SILABS_DBUS_USART0_CLK(0x3, 0x6) +#define USART0_CLK_PD7 SILABS_DBUS_USART0_CLK(0x3, 0x7) +#define USART0_CLK_PD8 SILABS_DBUS_USART0_CLK(0x3, 0x8) +#define USART0_CLK_PD9 SILABS_DBUS_USART0_CLK(0x3, 0x9) +#define USART0_CLK_PD10 SILABS_DBUS_USART0_CLK(0x3, 0xa) +#define USART0_CLK_PD11 SILABS_DBUS_USART0_CLK(0x3, 0xb) +#define USART0_CLK_PD12 SILABS_DBUS_USART0_CLK(0x3, 0xc) +#define USART0_CLK_PD13 SILABS_DBUS_USART0_CLK(0x3, 0xd) +#define USART0_CLK_PD14 SILABS_DBUS_USART0_CLK(0x3, 0xe) +#define USART0_CLK_PD15 SILABS_DBUS_USART0_CLK(0x3, 0xf) +#define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0) +#define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1) +#define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2) +#define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3) +#define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4) +#define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5) +#define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6) +#define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7) +#define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8) +#define USART0_TX_PA9 SILABS_DBUS_USART0_TX(0x0, 0x9) +#define USART0_TX_PA10 SILABS_DBUS_USART0_TX(0x0, 0xa) +#define USART0_TX_PA11 SILABS_DBUS_USART0_TX(0x0, 0xb) +#define USART0_TX_PA12 SILABS_DBUS_USART0_TX(0x0, 0xc) +#define USART0_TX_PA13 SILABS_DBUS_USART0_TX(0x0, 0xd) +#define USART0_TX_PA14 SILABS_DBUS_USART0_TX(0x0, 0xe) +#define USART0_TX_PA15 SILABS_DBUS_USART0_TX(0x0, 0xf) +#define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0) +#define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1) +#define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2) +#define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3) +#define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4) +#define USART0_TX_PB5 SILABS_DBUS_USART0_TX(0x1, 0x5) +#define USART0_TX_PB6 SILABS_DBUS_USART0_TX(0x1, 0x6) +#define USART0_TX_PB7 SILABS_DBUS_USART0_TX(0x1, 0x7) +#define USART0_TX_PB8 SILABS_DBUS_USART0_TX(0x1, 0x8) +#define USART0_TX_PB9 SILABS_DBUS_USART0_TX(0x1, 0x9) +#define USART0_TX_PB10 SILABS_DBUS_USART0_TX(0x1, 0xa) +#define USART0_TX_PB11 SILABS_DBUS_USART0_TX(0x1, 0xb) +#define USART0_TX_PB12 SILABS_DBUS_USART0_TX(0x1, 0xc) +#define USART0_TX_PB13 SILABS_DBUS_USART0_TX(0x1, 0xd) +#define USART0_TX_PB14 SILABS_DBUS_USART0_TX(0x1, 0xe) +#define USART0_TX_PB15 SILABS_DBUS_USART0_TX(0x1, 0xf) +#define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0) +#define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1) +#define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2) +#define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3) +#define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4) +#define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5) +#define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6) +#define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7) +#define USART0_TX_PC8 SILABS_DBUS_USART0_TX(0x2, 0x8) +#define USART0_TX_PC9 SILABS_DBUS_USART0_TX(0x2, 0x9) +#define USART0_TX_PC10 SILABS_DBUS_USART0_TX(0x2, 0xa) +#define USART0_TX_PC11 SILABS_DBUS_USART0_TX(0x2, 0xb) +#define USART0_TX_PC12 SILABS_DBUS_USART0_TX(0x2, 0xc) +#define USART0_TX_PC13 SILABS_DBUS_USART0_TX(0x2, 0xd) +#define USART0_TX_PC14 SILABS_DBUS_USART0_TX(0x2, 0xe) +#define USART0_TX_PC15 SILABS_DBUS_USART0_TX(0x2, 0xf) +#define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0) +#define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1) +#define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2) +#define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3) +#define USART0_TX_PD4 SILABS_DBUS_USART0_TX(0x3, 0x4) +#define USART0_TX_PD5 SILABS_DBUS_USART0_TX(0x3, 0x5) +#define USART0_TX_PD6 SILABS_DBUS_USART0_TX(0x3, 0x6) +#define USART0_TX_PD7 SILABS_DBUS_USART0_TX(0x3, 0x7) +#define USART0_TX_PD8 SILABS_DBUS_USART0_TX(0x3, 0x8) +#define USART0_TX_PD9 SILABS_DBUS_USART0_TX(0x3, 0x9) +#define USART0_TX_PD10 SILABS_DBUS_USART0_TX(0x3, 0xa) +#define USART0_TX_PD11 SILABS_DBUS_USART0_TX(0x3, 0xb) +#define USART0_TX_PD12 SILABS_DBUS_USART0_TX(0x3, 0xc) +#define USART0_TX_PD13 SILABS_DBUS_USART0_TX(0x3, 0xd) +#define USART0_TX_PD14 SILABS_DBUS_USART0_TX(0x3, 0xe) +#define USART0_TX_PD15 SILABS_DBUS_USART0_TX(0x3, 0xf) +#define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0) +#define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1) +#define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2) +#define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3) +#define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4) +#define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5) +#define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6) +#define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7) +#define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8) +#define USART0_CTS_PA9 SILABS_DBUS_USART0_CTS(0x0, 0x9) +#define USART0_CTS_PA10 SILABS_DBUS_USART0_CTS(0x0, 0xa) +#define USART0_CTS_PA11 SILABS_DBUS_USART0_CTS(0x0, 0xb) +#define USART0_CTS_PA12 SILABS_DBUS_USART0_CTS(0x0, 0xc) +#define USART0_CTS_PA13 SILABS_DBUS_USART0_CTS(0x0, 0xd) +#define USART0_CTS_PA14 SILABS_DBUS_USART0_CTS(0x0, 0xe) +#define USART0_CTS_PA15 SILABS_DBUS_USART0_CTS(0x0, 0xf) +#define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0) +#define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1) +#define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2) +#define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3) +#define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4) +#define USART0_CTS_PB5 SILABS_DBUS_USART0_CTS(0x1, 0x5) +#define USART0_CTS_PB6 SILABS_DBUS_USART0_CTS(0x1, 0x6) +#define USART0_CTS_PB7 SILABS_DBUS_USART0_CTS(0x1, 0x7) +#define USART0_CTS_PB8 SILABS_DBUS_USART0_CTS(0x1, 0x8) +#define USART0_CTS_PB9 SILABS_DBUS_USART0_CTS(0x1, 0x9) +#define USART0_CTS_PB10 SILABS_DBUS_USART0_CTS(0x1, 0xa) +#define USART0_CTS_PB11 SILABS_DBUS_USART0_CTS(0x1, 0xb) +#define USART0_CTS_PB12 SILABS_DBUS_USART0_CTS(0x1, 0xc) +#define USART0_CTS_PB13 SILABS_DBUS_USART0_CTS(0x1, 0xd) +#define USART0_CTS_PB14 SILABS_DBUS_USART0_CTS(0x1, 0xe) +#define USART0_CTS_PB15 SILABS_DBUS_USART0_CTS(0x1, 0xf) +#define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0) +#define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1) +#define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2) +#define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3) +#define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4) +#define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5) +#define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6) +#define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7) +#define USART0_CTS_PC8 SILABS_DBUS_USART0_CTS(0x2, 0x8) +#define USART0_CTS_PC9 SILABS_DBUS_USART0_CTS(0x2, 0x9) +#define USART0_CTS_PC10 SILABS_DBUS_USART0_CTS(0x2, 0xa) +#define USART0_CTS_PC11 SILABS_DBUS_USART0_CTS(0x2, 0xb) +#define USART0_CTS_PC12 SILABS_DBUS_USART0_CTS(0x2, 0xc) +#define USART0_CTS_PC13 SILABS_DBUS_USART0_CTS(0x2, 0xd) +#define USART0_CTS_PC14 SILABS_DBUS_USART0_CTS(0x2, 0xe) +#define USART0_CTS_PC15 SILABS_DBUS_USART0_CTS(0x2, 0xf) +#define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0) +#define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1) +#define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2) +#define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3) +#define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4) +#define USART0_CTS_PD5 SILABS_DBUS_USART0_CTS(0x3, 0x5) +#define USART0_CTS_PD6 SILABS_DBUS_USART0_CTS(0x3, 0x6) +#define USART0_CTS_PD7 SILABS_DBUS_USART0_CTS(0x3, 0x7) +#define USART0_CTS_PD8 SILABS_DBUS_USART0_CTS(0x3, 0x8) +#define USART0_CTS_PD9 SILABS_DBUS_USART0_CTS(0x3, 0x9) +#define USART0_CTS_PD10 SILABS_DBUS_USART0_CTS(0x3, 0xa) +#define USART0_CTS_PD11 SILABS_DBUS_USART0_CTS(0x3, 0xb) +#define USART0_CTS_PD12 SILABS_DBUS_USART0_CTS(0x3, 0xc) +#define USART0_CTS_PD13 SILABS_DBUS_USART0_CTS(0x3, 0xd) +#define USART0_CTS_PD14 SILABS_DBUS_USART0_CTS(0x3, 0xe) +#define USART0_CTS_PD15 SILABS_DBUS_USART0_CTS(0x3, 0xf) + +#define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0) +#define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1) +#define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2) +#define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3) +#define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4) +#define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5) +#define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6) +#define USART1_CS_PA7 SILABS_DBUS_USART1_CS(0x0, 0x7) +#define USART1_CS_PA8 SILABS_DBUS_USART1_CS(0x0, 0x8) +#define USART1_CS_PA9 SILABS_DBUS_USART1_CS(0x0, 0x9) +#define USART1_CS_PA10 SILABS_DBUS_USART1_CS(0x0, 0xa) +#define USART1_CS_PA11 SILABS_DBUS_USART1_CS(0x0, 0xb) +#define USART1_CS_PA12 SILABS_DBUS_USART1_CS(0x0, 0xc) +#define USART1_CS_PA13 SILABS_DBUS_USART1_CS(0x0, 0xd) +#define USART1_CS_PA14 SILABS_DBUS_USART1_CS(0x0, 0xe) +#define USART1_CS_PA15 SILABS_DBUS_USART1_CS(0x0, 0xf) +#define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0) +#define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1) +#define USART1_CS_PB2 SILABS_DBUS_USART1_CS(0x1, 0x2) +#define USART1_CS_PB3 SILABS_DBUS_USART1_CS(0x1, 0x3) +#define USART1_CS_PB4 SILABS_DBUS_USART1_CS(0x1, 0x4) +#define USART1_CS_PB5 SILABS_DBUS_USART1_CS(0x1, 0x5) +#define USART1_CS_PB6 SILABS_DBUS_USART1_CS(0x1, 0x6) +#define USART1_CS_PB7 SILABS_DBUS_USART1_CS(0x1, 0x7) +#define USART1_CS_PB8 SILABS_DBUS_USART1_CS(0x1, 0x8) +#define USART1_CS_PB9 SILABS_DBUS_USART1_CS(0x1, 0x9) +#define USART1_CS_PB10 SILABS_DBUS_USART1_CS(0x1, 0xa) +#define USART1_CS_PB11 SILABS_DBUS_USART1_CS(0x1, 0xb) +#define USART1_CS_PB12 SILABS_DBUS_USART1_CS(0x1, 0xc) +#define USART1_CS_PB13 SILABS_DBUS_USART1_CS(0x1, 0xd) +#define USART1_CS_PB14 SILABS_DBUS_USART1_CS(0x1, 0xe) +#define USART1_CS_PB15 SILABS_DBUS_USART1_CS(0x1, 0xf) +#define USART1_CS_PC0 SILABS_DBUS_USART1_CS(0x2, 0x0) +#define USART1_CS_PC1 SILABS_DBUS_USART1_CS(0x2, 0x1) +#define USART1_CS_PC2 SILABS_DBUS_USART1_CS(0x2, 0x2) +#define USART1_CS_PC3 SILABS_DBUS_USART1_CS(0x2, 0x3) +#define USART1_CS_PC4 SILABS_DBUS_USART1_CS(0x2, 0x4) +#define USART1_CS_PC5 SILABS_DBUS_USART1_CS(0x2, 0x5) +#define USART1_CS_PC6 SILABS_DBUS_USART1_CS(0x2, 0x6) +#define USART1_CS_PC7 SILABS_DBUS_USART1_CS(0x2, 0x7) +#define USART1_CS_PC8 SILABS_DBUS_USART1_CS(0x2, 0x8) +#define USART1_CS_PC9 SILABS_DBUS_USART1_CS(0x2, 0x9) +#define USART1_CS_PC10 SILABS_DBUS_USART1_CS(0x2, 0xa) +#define USART1_CS_PC11 SILABS_DBUS_USART1_CS(0x2, 0xb) +#define USART1_CS_PC12 SILABS_DBUS_USART1_CS(0x2, 0xc) +#define USART1_CS_PC13 SILABS_DBUS_USART1_CS(0x2, 0xd) +#define USART1_CS_PC14 SILABS_DBUS_USART1_CS(0x2, 0xe) +#define USART1_CS_PC15 SILABS_DBUS_USART1_CS(0x2, 0xf) +#define USART1_CS_PD0 SILABS_DBUS_USART1_CS(0x3, 0x0) +#define USART1_CS_PD1 SILABS_DBUS_USART1_CS(0x3, 0x1) +#define USART1_CS_PD2 SILABS_DBUS_USART1_CS(0x3, 0x2) +#define USART1_CS_PD3 SILABS_DBUS_USART1_CS(0x3, 0x3) +#define USART1_CS_PD4 SILABS_DBUS_USART1_CS(0x3, 0x4) +#define USART1_CS_PD5 SILABS_DBUS_USART1_CS(0x3, 0x5) +#define USART1_CS_PD6 SILABS_DBUS_USART1_CS(0x3, 0x6) +#define USART1_CS_PD7 SILABS_DBUS_USART1_CS(0x3, 0x7) +#define USART1_CS_PD8 SILABS_DBUS_USART1_CS(0x3, 0x8) +#define USART1_CS_PD9 SILABS_DBUS_USART1_CS(0x3, 0x9) +#define USART1_CS_PD10 SILABS_DBUS_USART1_CS(0x3, 0xa) +#define USART1_CS_PD11 SILABS_DBUS_USART1_CS(0x3, 0xb) +#define USART1_CS_PD12 SILABS_DBUS_USART1_CS(0x3, 0xc) +#define USART1_CS_PD13 SILABS_DBUS_USART1_CS(0x3, 0xd) +#define USART1_CS_PD14 SILABS_DBUS_USART1_CS(0x3, 0xe) +#define USART1_CS_PD15 SILABS_DBUS_USART1_CS(0x3, 0xf) +#define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0) +#define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1) +#define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2) +#define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3) +#define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4) +#define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5) +#define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6) +#define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7) +#define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8) +#define USART1_RTS_PA9 SILABS_DBUS_USART1_RTS(0x0, 0x9) +#define USART1_RTS_PA10 SILABS_DBUS_USART1_RTS(0x0, 0xa) +#define USART1_RTS_PA11 SILABS_DBUS_USART1_RTS(0x0, 0xb) +#define USART1_RTS_PA12 SILABS_DBUS_USART1_RTS(0x0, 0xc) +#define USART1_RTS_PA13 SILABS_DBUS_USART1_RTS(0x0, 0xd) +#define USART1_RTS_PA14 SILABS_DBUS_USART1_RTS(0x0, 0xe) +#define USART1_RTS_PA15 SILABS_DBUS_USART1_RTS(0x0, 0xf) +#define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0) +#define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1) +#define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2) +#define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3) +#define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4) +#define USART1_RTS_PB5 SILABS_DBUS_USART1_RTS(0x1, 0x5) +#define USART1_RTS_PB6 SILABS_DBUS_USART1_RTS(0x1, 0x6) +#define USART1_RTS_PB7 SILABS_DBUS_USART1_RTS(0x1, 0x7) +#define USART1_RTS_PB8 SILABS_DBUS_USART1_RTS(0x1, 0x8) +#define USART1_RTS_PB9 SILABS_DBUS_USART1_RTS(0x1, 0x9) +#define USART1_RTS_PB10 SILABS_DBUS_USART1_RTS(0x1, 0xa) +#define USART1_RTS_PB11 SILABS_DBUS_USART1_RTS(0x1, 0xb) +#define USART1_RTS_PB12 SILABS_DBUS_USART1_RTS(0x1, 0xc) +#define USART1_RTS_PB13 SILABS_DBUS_USART1_RTS(0x1, 0xd) +#define USART1_RTS_PB14 SILABS_DBUS_USART1_RTS(0x1, 0xe) +#define USART1_RTS_PB15 SILABS_DBUS_USART1_RTS(0x1, 0xf) +#define USART1_RTS_PC0 SILABS_DBUS_USART1_RTS(0x2, 0x0) +#define USART1_RTS_PC1 SILABS_DBUS_USART1_RTS(0x2, 0x1) +#define USART1_RTS_PC2 SILABS_DBUS_USART1_RTS(0x2, 0x2) +#define USART1_RTS_PC3 SILABS_DBUS_USART1_RTS(0x2, 0x3) +#define USART1_RTS_PC4 SILABS_DBUS_USART1_RTS(0x2, 0x4) +#define USART1_RTS_PC5 SILABS_DBUS_USART1_RTS(0x2, 0x5) +#define USART1_RTS_PC6 SILABS_DBUS_USART1_RTS(0x2, 0x6) +#define USART1_RTS_PC7 SILABS_DBUS_USART1_RTS(0x2, 0x7) +#define USART1_RTS_PC8 SILABS_DBUS_USART1_RTS(0x2, 0x8) +#define USART1_RTS_PC9 SILABS_DBUS_USART1_RTS(0x2, 0x9) +#define USART1_RTS_PC10 SILABS_DBUS_USART1_RTS(0x2, 0xa) +#define USART1_RTS_PC11 SILABS_DBUS_USART1_RTS(0x2, 0xb) +#define USART1_RTS_PC12 SILABS_DBUS_USART1_RTS(0x2, 0xc) +#define USART1_RTS_PC13 SILABS_DBUS_USART1_RTS(0x2, 0xd) +#define USART1_RTS_PC14 SILABS_DBUS_USART1_RTS(0x2, 0xe) +#define USART1_RTS_PC15 SILABS_DBUS_USART1_RTS(0x2, 0xf) +#define USART1_RTS_PD0 SILABS_DBUS_USART1_RTS(0x3, 0x0) +#define USART1_RTS_PD1 SILABS_DBUS_USART1_RTS(0x3, 0x1) +#define USART1_RTS_PD2 SILABS_DBUS_USART1_RTS(0x3, 0x2) +#define USART1_RTS_PD3 SILABS_DBUS_USART1_RTS(0x3, 0x3) +#define USART1_RTS_PD4 SILABS_DBUS_USART1_RTS(0x3, 0x4) +#define USART1_RTS_PD5 SILABS_DBUS_USART1_RTS(0x3, 0x5) +#define USART1_RTS_PD6 SILABS_DBUS_USART1_RTS(0x3, 0x6) +#define USART1_RTS_PD7 SILABS_DBUS_USART1_RTS(0x3, 0x7) +#define USART1_RTS_PD8 SILABS_DBUS_USART1_RTS(0x3, 0x8) +#define USART1_RTS_PD9 SILABS_DBUS_USART1_RTS(0x3, 0x9) +#define USART1_RTS_PD10 SILABS_DBUS_USART1_RTS(0x3, 0xa) +#define USART1_RTS_PD11 SILABS_DBUS_USART1_RTS(0x3, 0xb) +#define USART1_RTS_PD12 SILABS_DBUS_USART1_RTS(0x3, 0xc) +#define USART1_RTS_PD13 SILABS_DBUS_USART1_RTS(0x3, 0xd) +#define USART1_RTS_PD14 SILABS_DBUS_USART1_RTS(0x3, 0xe) +#define USART1_RTS_PD15 SILABS_DBUS_USART1_RTS(0x3, 0xf) +#define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0) +#define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1) +#define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2) +#define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3) +#define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4) +#define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5) +#define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6) +#define USART1_RX_PA7 SILABS_DBUS_USART1_RX(0x0, 0x7) +#define USART1_RX_PA8 SILABS_DBUS_USART1_RX(0x0, 0x8) +#define USART1_RX_PA9 SILABS_DBUS_USART1_RX(0x0, 0x9) +#define USART1_RX_PA10 SILABS_DBUS_USART1_RX(0x0, 0xa) +#define USART1_RX_PA11 SILABS_DBUS_USART1_RX(0x0, 0xb) +#define USART1_RX_PA12 SILABS_DBUS_USART1_RX(0x0, 0xc) +#define USART1_RX_PA13 SILABS_DBUS_USART1_RX(0x0, 0xd) +#define USART1_RX_PA14 SILABS_DBUS_USART1_RX(0x0, 0xe) +#define USART1_RX_PA15 SILABS_DBUS_USART1_RX(0x0, 0xf) +#define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0) +#define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1) +#define USART1_RX_PB2 SILABS_DBUS_USART1_RX(0x1, 0x2) +#define USART1_RX_PB3 SILABS_DBUS_USART1_RX(0x1, 0x3) +#define USART1_RX_PB4 SILABS_DBUS_USART1_RX(0x1, 0x4) +#define USART1_RX_PB5 SILABS_DBUS_USART1_RX(0x1, 0x5) +#define USART1_RX_PB6 SILABS_DBUS_USART1_RX(0x1, 0x6) +#define USART1_RX_PB7 SILABS_DBUS_USART1_RX(0x1, 0x7) +#define USART1_RX_PB8 SILABS_DBUS_USART1_RX(0x1, 0x8) +#define USART1_RX_PB9 SILABS_DBUS_USART1_RX(0x1, 0x9) +#define USART1_RX_PB10 SILABS_DBUS_USART1_RX(0x1, 0xa) +#define USART1_RX_PB11 SILABS_DBUS_USART1_RX(0x1, 0xb) +#define USART1_RX_PB12 SILABS_DBUS_USART1_RX(0x1, 0xc) +#define USART1_RX_PB13 SILABS_DBUS_USART1_RX(0x1, 0xd) +#define USART1_RX_PB14 SILABS_DBUS_USART1_RX(0x1, 0xe) +#define USART1_RX_PB15 SILABS_DBUS_USART1_RX(0x1, 0xf) +#define USART1_RX_PC0 SILABS_DBUS_USART1_RX(0x2, 0x0) +#define USART1_RX_PC1 SILABS_DBUS_USART1_RX(0x2, 0x1) +#define USART1_RX_PC2 SILABS_DBUS_USART1_RX(0x2, 0x2) +#define USART1_RX_PC3 SILABS_DBUS_USART1_RX(0x2, 0x3) +#define USART1_RX_PC4 SILABS_DBUS_USART1_RX(0x2, 0x4) +#define USART1_RX_PC5 SILABS_DBUS_USART1_RX(0x2, 0x5) +#define USART1_RX_PC6 SILABS_DBUS_USART1_RX(0x2, 0x6) +#define USART1_RX_PC7 SILABS_DBUS_USART1_RX(0x2, 0x7) +#define USART1_RX_PC8 SILABS_DBUS_USART1_RX(0x2, 0x8) +#define USART1_RX_PC9 SILABS_DBUS_USART1_RX(0x2, 0x9) +#define USART1_RX_PC10 SILABS_DBUS_USART1_RX(0x2, 0xa) +#define USART1_RX_PC11 SILABS_DBUS_USART1_RX(0x2, 0xb) +#define USART1_RX_PC12 SILABS_DBUS_USART1_RX(0x2, 0xc) +#define USART1_RX_PC13 SILABS_DBUS_USART1_RX(0x2, 0xd) +#define USART1_RX_PC14 SILABS_DBUS_USART1_RX(0x2, 0xe) +#define USART1_RX_PC15 SILABS_DBUS_USART1_RX(0x2, 0xf) +#define USART1_RX_PD0 SILABS_DBUS_USART1_RX(0x3, 0x0) +#define USART1_RX_PD1 SILABS_DBUS_USART1_RX(0x3, 0x1) +#define USART1_RX_PD2 SILABS_DBUS_USART1_RX(0x3, 0x2) +#define USART1_RX_PD3 SILABS_DBUS_USART1_RX(0x3, 0x3) +#define USART1_RX_PD4 SILABS_DBUS_USART1_RX(0x3, 0x4) +#define USART1_RX_PD5 SILABS_DBUS_USART1_RX(0x3, 0x5) +#define USART1_RX_PD6 SILABS_DBUS_USART1_RX(0x3, 0x6) +#define USART1_RX_PD7 SILABS_DBUS_USART1_RX(0x3, 0x7) +#define USART1_RX_PD8 SILABS_DBUS_USART1_RX(0x3, 0x8) +#define USART1_RX_PD9 SILABS_DBUS_USART1_RX(0x3, 0x9) +#define USART1_RX_PD10 SILABS_DBUS_USART1_RX(0x3, 0xa) +#define USART1_RX_PD11 SILABS_DBUS_USART1_RX(0x3, 0xb) +#define USART1_RX_PD12 SILABS_DBUS_USART1_RX(0x3, 0xc) +#define USART1_RX_PD13 SILABS_DBUS_USART1_RX(0x3, 0xd) +#define USART1_RX_PD14 SILABS_DBUS_USART1_RX(0x3, 0xe) +#define USART1_RX_PD15 SILABS_DBUS_USART1_RX(0x3, 0xf) +#define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0) +#define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1) +#define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2) +#define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3) +#define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4) +#define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5) +#define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6) +#define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7) +#define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8) +#define USART1_CLK_PA9 SILABS_DBUS_USART1_CLK(0x0, 0x9) +#define USART1_CLK_PA10 SILABS_DBUS_USART1_CLK(0x0, 0xa) +#define USART1_CLK_PA11 SILABS_DBUS_USART1_CLK(0x0, 0xb) +#define USART1_CLK_PA12 SILABS_DBUS_USART1_CLK(0x0, 0xc) +#define USART1_CLK_PA13 SILABS_DBUS_USART1_CLK(0x0, 0xd) +#define USART1_CLK_PA14 SILABS_DBUS_USART1_CLK(0x0, 0xe) +#define USART1_CLK_PA15 SILABS_DBUS_USART1_CLK(0x0, 0xf) +#define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0) +#define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1) +#define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2) +#define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3) +#define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4) +#define USART1_CLK_PB5 SILABS_DBUS_USART1_CLK(0x1, 0x5) +#define USART1_CLK_PB6 SILABS_DBUS_USART1_CLK(0x1, 0x6) +#define USART1_CLK_PB7 SILABS_DBUS_USART1_CLK(0x1, 0x7) +#define USART1_CLK_PB8 SILABS_DBUS_USART1_CLK(0x1, 0x8) +#define USART1_CLK_PB9 SILABS_DBUS_USART1_CLK(0x1, 0x9) +#define USART1_CLK_PB10 SILABS_DBUS_USART1_CLK(0x1, 0xa) +#define USART1_CLK_PB11 SILABS_DBUS_USART1_CLK(0x1, 0xb) +#define USART1_CLK_PB12 SILABS_DBUS_USART1_CLK(0x1, 0xc) +#define USART1_CLK_PB13 SILABS_DBUS_USART1_CLK(0x1, 0xd) +#define USART1_CLK_PB14 SILABS_DBUS_USART1_CLK(0x1, 0xe) +#define USART1_CLK_PB15 SILABS_DBUS_USART1_CLK(0x1, 0xf) +#define USART1_CLK_PC0 SILABS_DBUS_USART1_CLK(0x2, 0x0) +#define USART1_CLK_PC1 SILABS_DBUS_USART1_CLK(0x2, 0x1) +#define USART1_CLK_PC2 SILABS_DBUS_USART1_CLK(0x2, 0x2) +#define USART1_CLK_PC3 SILABS_DBUS_USART1_CLK(0x2, 0x3) +#define USART1_CLK_PC4 SILABS_DBUS_USART1_CLK(0x2, 0x4) +#define USART1_CLK_PC5 SILABS_DBUS_USART1_CLK(0x2, 0x5) +#define USART1_CLK_PC6 SILABS_DBUS_USART1_CLK(0x2, 0x6) +#define USART1_CLK_PC7 SILABS_DBUS_USART1_CLK(0x2, 0x7) +#define USART1_CLK_PC8 SILABS_DBUS_USART1_CLK(0x2, 0x8) +#define USART1_CLK_PC9 SILABS_DBUS_USART1_CLK(0x2, 0x9) +#define USART1_CLK_PC10 SILABS_DBUS_USART1_CLK(0x2, 0xa) +#define USART1_CLK_PC11 SILABS_DBUS_USART1_CLK(0x2, 0xb) +#define USART1_CLK_PC12 SILABS_DBUS_USART1_CLK(0x2, 0xc) +#define USART1_CLK_PC13 SILABS_DBUS_USART1_CLK(0x2, 0xd) +#define USART1_CLK_PC14 SILABS_DBUS_USART1_CLK(0x2, 0xe) +#define USART1_CLK_PC15 SILABS_DBUS_USART1_CLK(0x2, 0xf) +#define USART1_CLK_PD0 SILABS_DBUS_USART1_CLK(0x3, 0x0) +#define USART1_CLK_PD1 SILABS_DBUS_USART1_CLK(0x3, 0x1) +#define USART1_CLK_PD2 SILABS_DBUS_USART1_CLK(0x3, 0x2) +#define USART1_CLK_PD3 SILABS_DBUS_USART1_CLK(0x3, 0x3) +#define USART1_CLK_PD4 SILABS_DBUS_USART1_CLK(0x3, 0x4) +#define USART1_CLK_PD5 SILABS_DBUS_USART1_CLK(0x3, 0x5) +#define USART1_CLK_PD6 SILABS_DBUS_USART1_CLK(0x3, 0x6) +#define USART1_CLK_PD7 SILABS_DBUS_USART1_CLK(0x3, 0x7) +#define USART1_CLK_PD8 SILABS_DBUS_USART1_CLK(0x3, 0x8) +#define USART1_CLK_PD9 SILABS_DBUS_USART1_CLK(0x3, 0x9) +#define USART1_CLK_PD10 SILABS_DBUS_USART1_CLK(0x3, 0xa) +#define USART1_CLK_PD11 SILABS_DBUS_USART1_CLK(0x3, 0xb) +#define USART1_CLK_PD12 SILABS_DBUS_USART1_CLK(0x3, 0xc) +#define USART1_CLK_PD13 SILABS_DBUS_USART1_CLK(0x3, 0xd) +#define USART1_CLK_PD14 SILABS_DBUS_USART1_CLK(0x3, 0xe) +#define USART1_CLK_PD15 SILABS_DBUS_USART1_CLK(0x3, 0xf) +#define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0) +#define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1) +#define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2) +#define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3) +#define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4) +#define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5) +#define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6) +#define USART1_TX_PA7 SILABS_DBUS_USART1_TX(0x0, 0x7) +#define USART1_TX_PA8 SILABS_DBUS_USART1_TX(0x0, 0x8) +#define USART1_TX_PA9 SILABS_DBUS_USART1_TX(0x0, 0x9) +#define USART1_TX_PA10 SILABS_DBUS_USART1_TX(0x0, 0xa) +#define USART1_TX_PA11 SILABS_DBUS_USART1_TX(0x0, 0xb) +#define USART1_TX_PA12 SILABS_DBUS_USART1_TX(0x0, 0xc) +#define USART1_TX_PA13 SILABS_DBUS_USART1_TX(0x0, 0xd) +#define USART1_TX_PA14 SILABS_DBUS_USART1_TX(0x0, 0xe) +#define USART1_TX_PA15 SILABS_DBUS_USART1_TX(0x0, 0xf) +#define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0) +#define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1) +#define USART1_TX_PB2 SILABS_DBUS_USART1_TX(0x1, 0x2) +#define USART1_TX_PB3 SILABS_DBUS_USART1_TX(0x1, 0x3) +#define USART1_TX_PB4 SILABS_DBUS_USART1_TX(0x1, 0x4) +#define USART1_TX_PB5 SILABS_DBUS_USART1_TX(0x1, 0x5) +#define USART1_TX_PB6 SILABS_DBUS_USART1_TX(0x1, 0x6) +#define USART1_TX_PB7 SILABS_DBUS_USART1_TX(0x1, 0x7) +#define USART1_TX_PB8 SILABS_DBUS_USART1_TX(0x1, 0x8) +#define USART1_TX_PB9 SILABS_DBUS_USART1_TX(0x1, 0x9) +#define USART1_TX_PB10 SILABS_DBUS_USART1_TX(0x1, 0xa) +#define USART1_TX_PB11 SILABS_DBUS_USART1_TX(0x1, 0xb) +#define USART1_TX_PB12 SILABS_DBUS_USART1_TX(0x1, 0xc) +#define USART1_TX_PB13 SILABS_DBUS_USART1_TX(0x1, 0xd) +#define USART1_TX_PB14 SILABS_DBUS_USART1_TX(0x1, 0xe) +#define USART1_TX_PB15 SILABS_DBUS_USART1_TX(0x1, 0xf) +#define USART1_TX_PC0 SILABS_DBUS_USART1_TX(0x2, 0x0) +#define USART1_TX_PC1 SILABS_DBUS_USART1_TX(0x2, 0x1) +#define USART1_TX_PC2 SILABS_DBUS_USART1_TX(0x2, 0x2) +#define USART1_TX_PC3 SILABS_DBUS_USART1_TX(0x2, 0x3) +#define USART1_TX_PC4 SILABS_DBUS_USART1_TX(0x2, 0x4) +#define USART1_TX_PC5 SILABS_DBUS_USART1_TX(0x2, 0x5) +#define USART1_TX_PC6 SILABS_DBUS_USART1_TX(0x2, 0x6) +#define USART1_TX_PC7 SILABS_DBUS_USART1_TX(0x2, 0x7) +#define USART1_TX_PC8 SILABS_DBUS_USART1_TX(0x2, 0x8) +#define USART1_TX_PC9 SILABS_DBUS_USART1_TX(0x2, 0x9) +#define USART1_TX_PC10 SILABS_DBUS_USART1_TX(0x2, 0xa) +#define USART1_TX_PC11 SILABS_DBUS_USART1_TX(0x2, 0xb) +#define USART1_TX_PC12 SILABS_DBUS_USART1_TX(0x2, 0xc) +#define USART1_TX_PC13 SILABS_DBUS_USART1_TX(0x2, 0xd) +#define USART1_TX_PC14 SILABS_DBUS_USART1_TX(0x2, 0xe) +#define USART1_TX_PC15 SILABS_DBUS_USART1_TX(0x2, 0xf) +#define USART1_TX_PD0 SILABS_DBUS_USART1_TX(0x3, 0x0) +#define USART1_TX_PD1 SILABS_DBUS_USART1_TX(0x3, 0x1) +#define USART1_TX_PD2 SILABS_DBUS_USART1_TX(0x3, 0x2) +#define USART1_TX_PD3 SILABS_DBUS_USART1_TX(0x3, 0x3) +#define USART1_TX_PD4 SILABS_DBUS_USART1_TX(0x3, 0x4) +#define USART1_TX_PD5 SILABS_DBUS_USART1_TX(0x3, 0x5) +#define USART1_TX_PD6 SILABS_DBUS_USART1_TX(0x3, 0x6) +#define USART1_TX_PD7 SILABS_DBUS_USART1_TX(0x3, 0x7) +#define USART1_TX_PD8 SILABS_DBUS_USART1_TX(0x3, 0x8) +#define USART1_TX_PD9 SILABS_DBUS_USART1_TX(0x3, 0x9) +#define USART1_TX_PD10 SILABS_DBUS_USART1_TX(0x3, 0xa) +#define USART1_TX_PD11 SILABS_DBUS_USART1_TX(0x3, 0xb) +#define USART1_TX_PD12 SILABS_DBUS_USART1_TX(0x3, 0xc) +#define USART1_TX_PD13 SILABS_DBUS_USART1_TX(0x3, 0xd) +#define USART1_TX_PD14 SILABS_DBUS_USART1_TX(0x3, 0xe) +#define USART1_TX_PD15 SILABS_DBUS_USART1_TX(0x3, 0xf) +#define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0) +#define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1) +#define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2) +#define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3) +#define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4) +#define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5) +#define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6) +#define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7) +#define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8) +#define USART1_CTS_PA9 SILABS_DBUS_USART1_CTS(0x0, 0x9) +#define USART1_CTS_PA10 SILABS_DBUS_USART1_CTS(0x0, 0xa) +#define USART1_CTS_PA11 SILABS_DBUS_USART1_CTS(0x0, 0xb) +#define USART1_CTS_PA12 SILABS_DBUS_USART1_CTS(0x0, 0xc) +#define USART1_CTS_PA13 SILABS_DBUS_USART1_CTS(0x0, 0xd) +#define USART1_CTS_PA14 SILABS_DBUS_USART1_CTS(0x0, 0xe) +#define USART1_CTS_PA15 SILABS_DBUS_USART1_CTS(0x0, 0xf) +#define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0) +#define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1) +#define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2) +#define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3) +#define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4) +#define USART1_CTS_PB5 SILABS_DBUS_USART1_CTS(0x1, 0x5) +#define USART1_CTS_PB6 SILABS_DBUS_USART1_CTS(0x1, 0x6) +#define USART1_CTS_PB7 SILABS_DBUS_USART1_CTS(0x1, 0x7) +#define USART1_CTS_PB8 SILABS_DBUS_USART1_CTS(0x1, 0x8) +#define USART1_CTS_PB9 SILABS_DBUS_USART1_CTS(0x1, 0x9) +#define USART1_CTS_PB10 SILABS_DBUS_USART1_CTS(0x1, 0xa) +#define USART1_CTS_PB11 SILABS_DBUS_USART1_CTS(0x1, 0xb) +#define USART1_CTS_PB12 SILABS_DBUS_USART1_CTS(0x1, 0xc) +#define USART1_CTS_PB13 SILABS_DBUS_USART1_CTS(0x1, 0xd) +#define USART1_CTS_PB14 SILABS_DBUS_USART1_CTS(0x1, 0xe) +#define USART1_CTS_PB15 SILABS_DBUS_USART1_CTS(0x1, 0xf) +#define USART1_CTS_PC0 SILABS_DBUS_USART1_CTS(0x2, 0x0) +#define USART1_CTS_PC1 SILABS_DBUS_USART1_CTS(0x2, 0x1) +#define USART1_CTS_PC2 SILABS_DBUS_USART1_CTS(0x2, 0x2) +#define USART1_CTS_PC3 SILABS_DBUS_USART1_CTS(0x2, 0x3) +#define USART1_CTS_PC4 SILABS_DBUS_USART1_CTS(0x2, 0x4) +#define USART1_CTS_PC5 SILABS_DBUS_USART1_CTS(0x2, 0x5) +#define USART1_CTS_PC6 SILABS_DBUS_USART1_CTS(0x2, 0x6) +#define USART1_CTS_PC7 SILABS_DBUS_USART1_CTS(0x2, 0x7) +#define USART1_CTS_PC8 SILABS_DBUS_USART1_CTS(0x2, 0x8) +#define USART1_CTS_PC9 SILABS_DBUS_USART1_CTS(0x2, 0x9) +#define USART1_CTS_PC10 SILABS_DBUS_USART1_CTS(0x2, 0xa) +#define USART1_CTS_PC11 SILABS_DBUS_USART1_CTS(0x2, 0xb) +#define USART1_CTS_PC12 SILABS_DBUS_USART1_CTS(0x2, 0xc) +#define USART1_CTS_PC13 SILABS_DBUS_USART1_CTS(0x2, 0xd) +#define USART1_CTS_PC14 SILABS_DBUS_USART1_CTS(0x2, 0xe) +#define USART1_CTS_PC15 SILABS_DBUS_USART1_CTS(0x2, 0xf) +#define USART1_CTS_PD0 SILABS_DBUS_USART1_CTS(0x3, 0x0) +#define USART1_CTS_PD1 SILABS_DBUS_USART1_CTS(0x3, 0x1) +#define USART1_CTS_PD2 SILABS_DBUS_USART1_CTS(0x3, 0x2) +#define USART1_CTS_PD3 SILABS_DBUS_USART1_CTS(0x3, 0x3) +#define USART1_CTS_PD4 SILABS_DBUS_USART1_CTS(0x3, 0x4) +#define USART1_CTS_PD5 SILABS_DBUS_USART1_CTS(0x3, 0x5) +#define USART1_CTS_PD6 SILABS_DBUS_USART1_CTS(0x3, 0x6) +#define USART1_CTS_PD7 SILABS_DBUS_USART1_CTS(0x3, 0x7) +#define USART1_CTS_PD8 SILABS_DBUS_USART1_CTS(0x3, 0x8) +#define USART1_CTS_PD9 SILABS_DBUS_USART1_CTS(0x3, 0x9) +#define USART1_CTS_PD10 SILABS_DBUS_USART1_CTS(0x3, 0xa) +#define USART1_CTS_PD11 SILABS_DBUS_USART1_CTS(0x3, 0xb) +#define USART1_CTS_PD12 SILABS_DBUS_USART1_CTS(0x3, 0xc) +#define USART1_CTS_PD13 SILABS_DBUS_USART1_CTS(0x3, 0xd) +#define USART1_CTS_PD14 SILABS_DBUS_USART1_CTS(0x3, 0xe) +#define USART1_CTS_PD15 SILABS_DBUS_USART1_CTS(0x3, 0xf) + +#define USART2_CS_PA0 SILABS_DBUS_USART2_CS(0x0, 0x0) +#define USART2_CS_PA1 SILABS_DBUS_USART2_CS(0x0, 0x1) +#define USART2_CS_PA2 SILABS_DBUS_USART2_CS(0x0, 0x2) +#define USART2_CS_PA3 SILABS_DBUS_USART2_CS(0x0, 0x3) +#define USART2_CS_PA4 SILABS_DBUS_USART2_CS(0x0, 0x4) +#define USART2_CS_PA5 SILABS_DBUS_USART2_CS(0x0, 0x5) +#define USART2_CS_PA6 SILABS_DBUS_USART2_CS(0x0, 0x6) +#define USART2_CS_PA7 SILABS_DBUS_USART2_CS(0x0, 0x7) +#define USART2_CS_PA8 SILABS_DBUS_USART2_CS(0x0, 0x8) +#define USART2_CS_PA9 SILABS_DBUS_USART2_CS(0x0, 0x9) +#define USART2_CS_PA10 SILABS_DBUS_USART2_CS(0x0, 0xa) +#define USART2_CS_PA11 SILABS_DBUS_USART2_CS(0x0, 0xb) +#define USART2_CS_PA12 SILABS_DBUS_USART2_CS(0x0, 0xc) +#define USART2_CS_PA13 SILABS_DBUS_USART2_CS(0x0, 0xd) +#define USART2_CS_PA14 SILABS_DBUS_USART2_CS(0x0, 0xe) +#define USART2_CS_PA15 SILABS_DBUS_USART2_CS(0x0, 0xf) +#define USART2_CS_PB0 SILABS_DBUS_USART2_CS(0x1, 0x0) +#define USART2_CS_PB1 SILABS_DBUS_USART2_CS(0x1, 0x1) +#define USART2_CS_PB2 SILABS_DBUS_USART2_CS(0x1, 0x2) +#define USART2_CS_PB3 SILABS_DBUS_USART2_CS(0x1, 0x3) +#define USART2_CS_PB4 SILABS_DBUS_USART2_CS(0x1, 0x4) +#define USART2_CS_PB5 SILABS_DBUS_USART2_CS(0x1, 0x5) +#define USART2_CS_PB6 SILABS_DBUS_USART2_CS(0x1, 0x6) +#define USART2_CS_PB7 SILABS_DBUS_USART2_CS(0x1, 0x7) +#define USART2_CS_PB8 SILABS_DBUS_USART2_CS(0x1, 0x8) +#define USART2_CS_PB9 SILABS_DBUS_USART2_CS(0x1, 0x9) +#define USART2_CS_PB10 SILABS_DBUS_USART2_CS(0x1, 0xa) +#define USART2_CS_PB11 SILABS_DBUS_USART2_CS(0x1, 0xb) +#define USART2_CS_PB12 SILABS_DBUS_USART2_CS(0x1, 0xc) +#define USART2_CS_PB13 SILABS_DBUS_USART2_CS(0x1, 0xd) +#define USART2_CS_PB14 SILABS_DBUS_USART2_CS(0x1, 0xe) +#define USART2_CS_PB15 SILABS_DBUS_USART2_CS(0x1, 0xf) +#define USART2_CS_PC0 SILABS_DBUS_USART2_CS(0x2, 0x0) +#define USART2_CS_PC1 SILABS_DBUS_USART2_CS(0x2, 0x1) +#define USART2_CS_PC2 SILABS_DBUS_USART2_CS(0x2, 0x2) +#define USART2_CS_PC3 SILABS_DBUS_USART2_CS(0x2, 0x3) +#define USART2_CS_PC4 SILABS_DBUS_USART2_CS(0x2, 0x4) +#define USART2_CS_PC5 SILABS_DBUS_USART2_CS(0x2, 0x5) +#define USART2_CS_PC6 SILABS_DBUS_USART2_CS(0x2, 0x6) +#define USART2_CS_PC7 SILABS_DBUS_USART2_CS(0x2, 0x7) +#define USART2_CS_PC8 SILABS_DBUS_USART2_CS(0x2, 0x8) +#define USART2_CS_PC9 SILABS_DBUS_USART2_CS(0x2, 0x9) +#define USART2_CS_PC10 SILABS_DBUS_USART2_CS(0x2, 0xa) +#define USART2_CS_PC11 SILABS_DBUS_USART2_CS(0x2, 0xb) +#define USART2_CS_PC12 SILABS_DBUS_USART2_CS(0x2, 0xc) +#define USART2_CS_PC13 SILABS_DBUS_USART2_CS(0x2, 0xd) +#define USART2_CS_PC14 SILABS_DBUS_USART2_CS(0x2, 0xe) +#define USART2_CS_PC15 SILABS_DBUS_USART2_CS(0x2, 0xf) +#define USART2_CS_PD0 SILABS_DBUS_USART2_CS(0x3, 0x0) +#define USART2_CS_PD1 SILABS_DBUS_USART2_CS(0x3, 0x1) +#define USART2_CS_PD2 SILABS_DBUS_USART2_CS(0x3, 0x2) +#define USART2_CS_PD3 SILABS_DBUS_USART2_CS(0x3, 0x3) +#define USART2_CS_PD4 SILABS_DBUS_USART2_CS(0x3, 0x4) +#define USART2_CS_PD5 SILABS_DBUS_USART2_CS(0x3, 0x5) +#define USART2_CS_PD6 SILABS_DBUS_USART2_CS(0x3, 0x6) +#define USART2_CS_PD7 SILABS_DBUS_USART2_CS(0x3, 0x7) +#define USART2_CS_PD8 SILABS_DBUS_USART2_CS(0x3, 0x8) +#define USART2_CS_PD9 SILABS_DBUS_USART2_CS(0x3, 0x9) +#define USART2_CS_PD10 SILABS_DBUS_USART2_CS(0x3, 0xa) +#define USART2_CS_PD11 SILABS_DBUS_USART2_CS(0x3, 0xb) +#define USART2_CS_PD12 SILABS_DBUS_USART2_CS(0x3, 0xc) +#define USART2_CS_PD13 SILABS_DBUS_USART2_CS(0x3, 0xd) +#define USART2_CS_PD14 SILABS_DBUS_USART2_CS(0x3, 0xe) +#define USART2_CS_PD15 SILABS_DBUS_USART2_CS(0x3, 0xf) +#define USART2_RTS_PA0 SILABS_DBUS_USART2_RTS(0x0, 0x0) +#define USART2_RTS_PA1 SILABS_DBUS_USART2_RTS(0x0, 0x1) +#define USART2_RTS_PA2 SILABS_DBUS_USART2_RTS(0x0, 0x2) +#define USART2_RTS_PA3 SILABS_DBUS_USART2_RTS(0x0, 0x3) +#define USART2_RTS_PA4 SILABS_DBUS_USART2_RTS(0x0, 0x4) +#define USART2_RTS_PA5 SILABS_DBUS_USART2_RTS(0x0, 0x5) +#define USART2_RTS_PA6 SILABS_DBUS_USART2_RTS(0x0, 0x6) +#define USART2_RTS_PA7 SILABS_DBUS_USART2_RTS(0x0, 0x7) +#define USART2_RTS_PA8 SILABS_DBUS_USART2_RTS(0x0, 0x8) +#define USART2_RTS_PA9 SILABS_DBUS_USART2_RTS(0x0, 0x9) +#define USART2_RTS_PA10 SILABS_DBUS_USART2_RTS(0x0, 0xa) +#define USART2_RTS_PA11 SILABS_DBUS_USART2_RTS(0x0, 0xb) +#define USART2_RTS_PA12 SILABS_DBUS_USART2_RTS(0x0, 0xc) +#define USART2_RTS_PA13 SILABS_DBUS_USART2_RTS(0x0, 0xd) +#define USART2_RTS_PA14 SILABS_DBUS_USART2_RTS(0x0, 0xe) +#define USART2_RTS_PA15 SILABS_DBUS_USART2_RTS(0x0, 0xf) +#define USART2_RTS_PB0 SILABS_DBUS_USART2_RTS(0x1, 0x0) +#define USART2_RTS_PB1 SILABS_DBUS_USART2_RTS(0x1, 0x1) +#define USART2_RTS_PB2 SILABS_DBUS_USART2_RTS(0x1, 0x2) +#define USART2_RTS_PB3 SILABS_DBUS_USART2_RTS(0x1, 0x3) +#define USART2_RTS_PB4 SILABS_DBUS_USART2_RTS(0x1, 0x4) +#define USART2_RTS_PB5 SILABS_DBUS_USART2_RTS(0x1, 0x5) +#define USART2_RTS_PB6 SILABS_DBUS_USART2_RTS(0x1, 0x6) +#define USART2_RTS_PB7 SILABS_DBUS_USART2_RTS(0x1, 0x7) +#define USART2_RTS_PB8 SILABS_DBUS_USART2_RTS(0x1, 0x8) +#define USART2_RTS_PB9 SILABS_DBUS_USART2_RTS(0x1, 0x9) +#define USART2_RTS_PB10 SILABS_DBUS_USART2_RTS(0x1, 0xa) +#define USART2_RTS_PB11 SILABS_DBUS_USART2_RTS(0x1, 0xb) +#define USART2_RTS_PB12 SILABS_DBUS_USART2_RTS(0x1, 0xc) +#define USART2_RTS_PB13 SILABS_DBUS_USART2_RTS(0x1, 0xd) +#define USART2_RTS_PB14 SILABS_DBUS_USART2_RTS(0x1, 0xe) +#define USART2_RTS_PB15 SILABS_DBUS_USART2_RTS(0x1, 0xf) +#define USART2_RTS_PC0 SILABS_DBUS_USART2_RTS(0x2, 0x0) +#define USART2_RTS_PC1 SILABS_DBUS_USART2_RTS(0x2, 0x1) +#define USART2_RTS_PC2 SILABS_DBUS_USART2_RTS(0x2, 0x2) +#define USART2_RTS_PC3 SILABS_DBUS_USART2_RTS(0x2, 0x3) +#define USART2_RTS_PC4 SILABS_DBUS_USART2_RTS(0x2, 0x4) +#define USART2_RTS_PC5 SILABS_DBUS_USART2_RTS(0x2, 0x5) +#define USART2_RTS_PC6 SILABS_DBUS_USART2_RTS(0x2, 0x6) +#define USART2_RTS_PC7 SILABS_DBUS_USART2_RTS(0x2, 0x7) +#define USART2_RTS_PC8 SILABS_DBUS_USART2_RTS(0x2, 0x8) +#define USART2_RTS_PC9 SILABS_DBUS_USART2_RTS(0x2, 0x9) +#define USART2_RTS_PC10 SILABS_DBUS_USART2_RTS(0x2, 0xa) +#define USART2_RTS_PC11 SILABS_DBUS_USART2_RTS(0x2, 0xb) +#define USART2_RTS_PC12 SILABS_DBUS_USART2_RTS(0x2, 0xc) +#define USART2_RTS_PC13 SILABS_DBUS_USART2_RTS(0x2, 0xd) +#define USART2_RTS_PC14 SILABS_DBUS_USART2_RTS(0x2, 0xe) +#define USART2_RTS_PC15 SILABS_DBUS_USART2_RTS(0x2, 0xf) +#define USART2_RTS_PD0 SILABS_DBUS_USART2_RTS(0x3, 0x0) +#define USART2_RTS_PD1 SILABS_DBUS_USART2_RTS(0x3, 0x1) +#define USART2_RTS_PD2 SILABS_DBUS_USART2_RTS(0x3, 0x2) +#define USART2_RTS_PD3 SILABS_DBUS_USART2_RTS(0x3, 0x3) +#define USART2_RTS_PD4 SILABS_DBUS_USART2_RTS(0x3, 0x4) +#define USART2_RTS_PD5 SILABS_DBUS_USART2_RTS(0x3, 0x5) +#define USART2_RTS_PD6 SILABS_DBUS_USART2_RTS(0x3, 0x6) +#define USART2_RTS_PD7 SILABS_DBUS_USART2_RTS(0x3, 0x7) +#define USART2_RTS_PD8 SILABS_DBUS_USART2_RTS(0x3, 0x8) +#define USART2_RTS_PD9 SILABS_DBUS_USART2_RTS(0x3, 0x9) +#define USART2_RTS_PD10 SILABS_DBUS_USART2_RTS(0x3, 0xa) +#define USART2_RTS_PD11 SILABS_DBUS_USART2_RTS(0x3, 0xb) +#define USART2_RTS_PD12 SILABS_DBUS_USART2_RTS(0x3, 0xc) +#define USART2_RTS_PD13 SILABS_DBUS_USART2_RTS(0x3, 0xd) +#define USART2_RTS_PD14 SILABS_DBUS_USART2_RTS(0x3, 0xe) +#define USART2_RTS_PD15 SILABS_DBUS_USART2_RTS(0x3, 0xf) +#define USART2_RX_PA0 SILABS_DBUS_USART2_RX(0x0, 0x0) +#define USART2_RX_PA1 SILABS_DBUS_USART2_RX(0x0, 0x1) +#define USART2_RX_PA2 SILABS_DBUS_USART2_RX(0x0, 0x2) +#define USART2_RX_PA3 SILABS_DBUS_USART2_RX(0x0, 0x3) +#define USART2_RX_PA4 SILABS_DBUS_USART2_RX(0x0, 0x4) +#define USART2_RX_PA5 SILABS_DBUS_USART2_RX(0x0, 0x5) +#define USART2_RX_PA6 SILABS_DBUS_USART2_RX(0x0, 0x6) +#define USART2_RX_PA7 SILABS_DBUS_USART2_RX(0x0, 0x7) +#define USART2_RX_PA8 SILABS_DBUS_USART2_RX(0x0, 0x8) +#define USART2_RX_PA9 SILABS_DBUS_USART2_RX(0x0, 0x9) +#define USART2_RX_PA10 SILABS_DBUS_USART2_RX(0x0, 0xa) +#define USART2_RX_PA11 SILABS_DBUS_USART2_RX(0x0, 0xb) +#define USART2_RX_PA12 SILABS_DBUS_USART2_RX(0x0, 0xc) +#define USART2_RX_PA13 SILABS_DBUS_USART2_RX(0x0, 0xd) +#define USART2_RX_PA14 SILABS_DBUS_USART2_RX(0x0, 0xe) +#define USART2_RX_PA15 SILABS_DBUS_USART2_RX(0x0, 0xf) +#define USART2_RX_PB0 SILABS_DBUS_USART2_RX(0x1, 0x0) +#define USART2_RX_PB1 SILABS_DBUS_USART2_RX(0x1, 0x1) +#define USART2_RX_PB2 SILABS_DBUS_USART2_RX(0x1, 0x2) +#define USART2_RX_PB3 SILABS_DBUS_USART2_RX(0x1, 0x3) +#define USART2_RX_PB4 SILABS_DBUS_USART2_RX(0x1, 0x4) +#define USART2_RX_PB5 SILABS_DBUS_USART2_RX(0x1, 0x5) +#define USART2_RX_PB6 SILABS_DBUS_USART2_RX(0x1, 0x6) +#define USART2_RX_PB7 SILABS_DBUS_USART2_RX(0x1, 0x7) +#define USART2_RX_PB8 SILABS_DBUS_USART2_RX(0x1, 0x8) +#define USART2_RX_PB9 SILABS_DBUS_USART2_RX(0x1, 0x9) +#define USART2_RX_PB10 SILABS_DBUS_USART2_RX(0x1, 0xa) +#define USART2_RX_PB11 SILABS_DBUS_USART2_RX(0x1, 0xb) +#define USART2_RX_PB12 SILABS_DBUS_USART2_RX(0x1, 0xc) +#define USART2_RX_PB13 SILABS_DBUS_USART2_RX(0x1, 0xd) +#define USART2_RX_PB14 SILABS_DBUS_USART2_RX(0x1, 0xe) +#define USART2_RX_PB15 SILABS_DBUS_USART2_RX(0x1, 0xf) +#define USART2_RX_PC0 SILABS_DBUS_USART2_RX(0x2, 0x0) +#define USART2_RX_PC1 SILABS_DBUS_USART2_RX(0x2, 0x1) +#define USART2_RX_PC2 SILABS_DBUS_USART2_RX(0x2, 0x2) +#define USART2_RX_PC3 SILABS_DBUS_USART2_RX(0x2, 0x3) +#define USART2_RX_PC4 SILABS_DBUS_USART2_RX(0x2, 0x4) +#define USART2_RX_PC5 SILABS_DBUS_USART2_RX(0x2, 0x5) +#define USART2_RX_PC6 SILABS_DBUS_USART2_RX(0x2, 0x6) +#define USART2_RX_PC7 SILABS_DBUS_USART2_RX(0x2, 0x7) +#define USART2_RX_PC8 SILABS_DBUS_USART2_RX(0x2, 0x8) +#define USART2_RX_PC9 SILABS_DBUS_USART2_RX(0x2, 0x9) +#define USART2_RX_PC10 SILABS_DBUS_USART2_RX(0x2, 0xa) +#define USART2_RX_PC11 SILABS_DBUS_USART2_RX(0x2, 0xb) +#define USART2_RX_PC12 SILABS_DBUS_USART2_RX(0x2, 0xc) +#define USART2_RX_PC13 SILABS_DBUS_USART2_RX(0x2, 0xd) +#define USART2_RX_PC14 SILABS_DBUS_USART2_RX(0x2, 0xe) +#define USART2_RX_PC15 SILABS_DBUS_USART2_RX(0x2, 0xf) +#define USART2_RX_PD0 SILABS_DBUS_USART2_RX(0x3, 0x0) +#define USART2_RX_PD1 SILABS_DBUS_USART2_RX(0x3, 0x1) +#define USART2_RX_PD2 SILABS_DBUS_USART2_RX(0x3, 0x2) +#define USART2_RX_PD3 SILABS_DBUS_USART2_RX(0x3, 0x3) +#define USART2_RX_PD4 SILABS_DBUS_USART2_RX(0x3, 0x4) +#define USART2_RX_PD5 SILABS_DBUS_USART2_RX(0x3, 0x5) +#define USART2_RX_PD6 SILABS_DBUS_USART2_RX(0x3, 0x6) +#define USART2_RX_PD7 SILABS_DBUS_USART2_RX(0x3, 0x7) +#define USART2_RX_PD8 SILABS_DBUS_USART2_RX(0x3, 0x8) +#define USART2_RX_PD9 SILABS_DBUS_USART2_RX(0x3, 0x9) +#define USART2_RX_PD10 SILABS_DBUS_USART2_RX(0x3, 0xa) +#define USART2_RX_PD11 SILABS_DBUS_USART2_RX(0x3, 0xb) +#define USART2_RX_PD12 SILABS_DBUS_USART2_RX(0x3, 0xc) +#define USART2_RX_PD13 SILABS_DBUS_USART2_RX(0x3, 0xd) +#define USART2_RX_PD14 SILABS_DBUS_USART2_RX(0x3, 0xe) +#define USART2_RX_PD15 SILABS_DBUS_USART2_RX(0x3, 0xf) +#define USART2_CLK_PA0 SILABS_DBUS_USART2_CLK(0x0, 0x0) +#define USART2_CLK_PA1 SILABS_DBUS_USART2_CLK(0x0, 0x1) +#define USART2_CLK_PA2 SILABS_DBUS_USART2_CLK(0x0, 0x2) +#define USART2_CLK_PA3 SILABS_DBUS_USART2_CLK(0x0, 0x3) +#define USART2_CLK_PA4 SILABS_DBUS_USART2_CLK(0x0, 0x4) +#define USART2_CLK_PA5 SILABS_DBUS_USART2_CLK(0x0, 0x5) +#define USART2_CLK_PA6 SILABS_DBUS_USART2_CLK(0x0, 0x6) +#define USART2_CLK_PA7 SILABS_DBUS_USART2_CLK(0x0, 0x7) +#define USART2_CLK_PA8 SILABS_DBUS_USART2_CLK(0x0, 0x8) +#define USART2_CLK_PA9 SILABS_DBUS_USART2_CLK(0x0, 0x9) +#define USART2_CLK_PA10 SILABS_DBUS_USART2_CLK(0x0, 0xa) +#define USART2_CLK_PA11 SILABS_DBUS_USART2_CLK(0x0, 0xb) +#define USART2_CLK_PA12 SILABS_DBUS_USART2_CLK(0x0, 0xc) +#define USART2_CLK_PA13 SILABS_DBUS_USART2_CLK(0x0, 0xd) +#define USART2_CLK_PA14 SILABS_DBUS_USART2_CLK(0x0, 0xe) +#define USART2_CLK_PA15 SILABS_DBUS_USART2_CLK(0x0, 0xf) +#define USART2_CLK_PB0 SILABS_DBUS_USART2_CLK(0x1, 0x0) +#define USART2_CLK_PB1 SILABS_DBUS_USART2_CLK(0x1, 0x1) +#define USART2_CLK_PB2 SILABS_DBUS_USART2_CLK(0x1, 0x2) +#define USART2_CLK_PB3 SILABS_DBUS_USART2_CLK(0x1, 0x3) +#define USART2_CLK_PB4 SILABS_DBUS_USART2_CLK(0x1, 0x4) +#define USART2_CLK_PB5 SILABS_DBUS_USART2_CLK(0x1, 0x5) +#define USART2_CLK_PB6 SILABS_DBUS_USART2_CLK(0x1, 0x6) +#define USART2_CLK_PB7 SILABS_DBUS_USART2_CLK(0x1, 0x7) +#define USART2_CLK_PB8 SILABS_DBUS_USART2_CLK(0x1, 0x8) +#define USART2_CLK_PB9 SILABS_DBUS_USART2_CLK(0x1, 0x9) +#define USART2_CLK_PB10 SILABS_DBUS_USART2_CLK(0x1, 0xa) +#define USART2_CLK_PB11 SILABS_DBUS_USART2_CLK(0x1, 0xb) +#define USART2_CLK_PB12 SILABS_DBUS_USART2_CLK(0x1, 0xc) +#define USART2_CLK_PB13 SILABS_DBUS_USART2_CLK(0x1, 0xd) +#define USART2_CLK_PB14 SILABS_DBUS_USART2_CLK(0x1, 0xe) +#define USART2_CLK_PB15 SILABS_DBUS_USART2_CLK(0x1, 0xf) +#define USART2_CLK_PC0 SILABS_DBUS_USART2_CLK(0x2, 0x0) +#define USART2_CLK_PC1 SILABS_DBUS_USART2_CLK(0x2, 0x1) +#define USART2_CLK_PC2 SILABS_DBUS_USART2_CLK(0x2, 0x2) +#define USART2_CLK_PC3 SILABS_DBUS_USART2_CLK(0x2, 0x3) +#define USART2_CLK_PC4 SILABS_DBUS_USART2_CLK(0x2, 0x4) +#define USART2_CLK_PC5 SILABS_DBUS_USART2_CLK(0x2, 0x5) +#define USART2_CLK_PC6 SILABS_DBUS_USART2_CLK(0x2, 0x6) +#define USART2_CLK_PC7 SILABS_DBUS_USART2_CLK(0x2, 0x7) +#define USART2_CLK_PC8 SILABS_DBUS_USART2_CLK(0x2, 0x8) +#define USART2_CLK_PC9 SILABS_DBUS_USART2_CLK(0x2, 0x9) +#define USART2_CLK_PC10 SILABS_DBUS_USART2_CLK(0x2, 0xa) +#define USART2_CLK_PC11 SILABS_DBUS_USART2_CLK(0x2, 0xb) +#define USART2_CLK_PC12 SILABS_DBUS_USART2_CLK(0x2, 0xc) +#define USART2_CLK_PC13 SILABS_DBUS_USART2_CLK(0x2, 0xd) +#define USART2_CLK_PC14 SILABS_DBUS_USART2_CLK(0x2, 0xe) +#define USART2_CLK_PC15 SILABS_DBUS_USART2_CLK(0x2, 0xf) +#define USART2_CLK_PD0 SILABS_DBUS_USART2_CLK(0x3, 0x0) +#define USART2_CLK_PD1 SILABS_DBUS_USART2_CLK(0x3, 0x1) +#define USART2_CLK_PD2 SILABS_DBUS_USART2_CLK(0x3, 0x2) +#define USART2_CLK_PD3 SILABS_DBUS_USART2_CLK(0x3, 0x3) +#define USART2_CLK_PD4 SILABS_DBUS_USART2_CLK(0x3, 0x4) +#define USART2_CLK_PD5 SILABS_DBUS_USART2_CLK(0x3, 0x5) +#define USART2_CLK_PD6 SILABS_DBUS_USART2_CLK(0x3, 0x6) +#define USART2_CLK_PD7 SILABS_DBUS_USART2_CLK(0x3, 0x7) +#define USART2_CLK_PD8 SILABS_DBUS_USART2_CLK(0x3, 0x8) +#define USART2_CLK_PD9 SILABS_DBUS_USART2_CLK(0x3, 0x9) +#define USART2_CLK_PD10 SILABS_DBUS_USART2_CLK(0x3, 0xa) +#define USART2_CLK_PD11 SILABS_DBUS_USART2_CLK(0x3, 0xb) +#define USART2_CLK_PD12 SILABS_DBUS_USART2_CLK(0x3, 0xc) +#define USART2_CLK_PD13 SILABS_DBUS_USART2_CLK(0x3, 0xd) +#define USART2_CLK_PD14 SILABS_DBUS_USART2_CLK(0x3, 0xe) +#define USART2_CLK_PD15 SILABS_DBUS_USART2_CLK(0x3, 0xf) +#define USART2_TX_PA0 SILABS_DBUS_USART2_TX(0x0, 0x0) +#define USART2_TX_PA1 SILABS_DBUS_USART2_TX(0x0, 0x1) +#define USART2_TX_PA2 SILABS_DBUS_USART2_TX(0x0, 0x2) +#define USART2_TX_PA3 SILABS_DBUS_USART2_TX(0x0, 0x3) +#define USART2_TX_PA4 SILABS_DBUS_USART2_TX(0x0, 0x4) +#define USART2_TX_PA5 SILABS_DBUS_USART2_TX(0x0, 0x5) +#define USART2_TX_PA6 SILABS_DBUS_USART2_TX(0x0, 0x6) +#define USART2_TX_PA7 SILABS_DBUS_USART2_TX(0x0, 0x7) +#define USART2_TX_PA8 SILABS_DBUS_USART2_TX(0x0, 0x8) +#define USART2_TX_PA9 SILABS_DBUS_USART2_TX(0x0, 0x9) +#define USART2_TX_PA10 SILABS_DBUS_USART2_TX(0x0, 0xa) +#define USART2_TX_PA11 SILABS_DBUS_USART2_TX(0x0, 0xb) +#define USART2_TX_PA12 SILABS_DBUS_USART2_TX(0x0, 0xc) +#define USART2_TX_PA13 SILABS_DBUS_USART2_TX(0x0, 0xd) +#define USART2_TX_PA14 SILABS_DBUS_USART2_TX(0x0, 0xe) +#define USART2_TX_PA15 SILABS_DBUS_USART2_TX(0x0, 0xf) +#define USART2_TX_PB0 SILABS_DBUS_USART2_TX(0x1, 0x0) +#define USART2_TX_PB1 SILABS_DBUS_USART2_TX(0x1, 0x1) +#define USART2_TX_PB2 SILABS_DBUS_USART2_TX(0x1, 0x2) +#define USART2_TX_PB3 SILABS_DBUS_USART2_TX(0x1, 0x3) +#define USART2_TX_PB4 SILABS_DBUS_USART2_TX(0x1, 0x4) +#define USART2_TX_PB5 SILABS_DBUS_USART2_TX(0x1, 0x5) +#define USART2_TX_PB6 SILABS_DBUS_USART2_TX(0x1, 0x6) +#define USART2_TX_PB7 SILABS_DBUS_USART2_TX(0x1, 0x7) +#define USART2_TX_PB8 SILABS_DBUS_USART2_TX(0x1, 0x8) +#define USART2_TX_PB9 SILABS_DBUS_USART2_TX(0x1, 0x9) +#define USART2_TX_PB10 SILABS_DBUS_USART2_TX(0x1, 0xa) +#define USART2_TX_PB11 SILABS_DBUS_USART2_TX(0x1, 0xb) +#define USART2_TX_PB12 SILABS_DBUS_USART2_TX(0x1, 0xc) +#define USART2_TX_PB13 SILABS_DBUS_USART2_TX(0x1, 0xd) +#define USART2_TX_PB14 SILABS_DBUS_USART2_TX(0x1, 0xe) +#define USART2_TX_PB15 SILABS_DBUS_USART2_TX(0x1, 0xf) +#define USART2_TX_PC0 SILABS_DBUS_USART2_TX(0x2, 0x0) +#define USART2_TX_PC1 SILABS_DBUS_USART2_TX(0x2, 0x1) +#define USART2_TX_PC2 SILABS_DBUS_USART2_TX(0x2, 0x2) +#define USART2_TX_PC3 SILABS_DBUS_USART2_TX(0x2, 0x3) +#define USART2_TX_PC4 SILABS_DBUS_USART2_TX(0x2, 0x4) +#define USART2_TX_PC5 SILABS_DBUS_USART2_TX(0x2, 0x5) +#define USART2_TX_PC6 SILABS_DBUS_USART2_TX(0x2, 0x6) +#define USART2_TX_PC7 SILABS_DBUS_USART2_TX(0x2, 0x7) +#define USART2_TX_PC8 SILABS_DBUS_USART2_TX(0x2, 0x8) +#define USART2_TX_PC9 SILABS_DBUS_USART2_TX(0x2, 0x9) +#define USART2_TX_PC10 SILABS_DBUS_USART2_TX(0x2, 0xa) +#define USART2_TX_PC11 SILABS_DBUS_USART2_TX(0x2, 0xb) +#define USART2_TX_PC12 SILABS_DBUS_USART2_TX(0x2, 0xc) +#define USART2_TX_PC13 SILABS_DBUS_USART2_TX(0x2, 0xd) +#define USART2_TX_PC14 SILABS_DBUS_USART2_TX(0x2, 0xe) +#define USART2_TX_PC15 SILABS_DBUS_USART2_TX(0x2, 0xf) +#define USART2_TX_PD0 SILABS_DBUS_USART2_TX(0x3, 0x0) +#define USART2_TX_PD1 SILABS_DBUS_USART2_TX(0x3, 0x1) +#define USART2_TX_PD2 SILABS_DBUS_USART2_TX(0x3, 0x2) +#define USART2_TX_PD3 SILABS_DBUS_USART2_TX(0x3, 0x3) +#define USART2_TX_PD4 SILABS_DBUS_USART2_TX(0x3, 0x4) +#define USART2_TX_PD5 SILABS_DBUS_USART2_TX(0x3, 0x5) +#define USART2_TX_PD6 SILABS_DBUS_USART2_TX(0x3, 0x6) +#define USART2_TX_PD7 SILABS_DBUS_USART2_TX(0x3, 0x7) +#define USART2_TX_PD8 SILABS_DBUS_USART2_TX(0x3, 0x8) +#define USART2_TX_PD9 SILABS_DBUS_USART2_TX(0x3, 0x9) +#define USART2_TX_PD10 SILABS_DBUS_USART2_TX(0x3, 0xa) +#define USART2_TX_PD11 SILABS_DBUS_USART2_TX(0x3, 0xb) +#define USART2_TX_PD12 SILABS_DBUS_USART2_TX(0x3, 0xc) +#define USART2_TX_PD13 SILABS_DBUS_USART2_TX(0x3, 0xd) +#define USART2_TX_PD14 SILABS_DBUS_USART2_TX(0x3, 0xe) +#define USART2_TX_PD15 SILABS_DBUS_USART2_TX(0x3, 0xf) +#define USART2_CTS_PA0 SILABS_DBUS_USART2_CTS(0x0, 0x0) +#define USART2_CTS_PA1 SILABS_DBUS_USART2_CTS(0x0, 0x1) +#define USART2_CTS_PA2 SILABS_DBUS_USART2_CTS(0x0, 0x2) +#define USART2_CTS_PA3 SILABS_DBUS_USART2_CTS(0x0, 0x3) +#define USART2_CTS_PA4 SILABS_DBUS_USART2_CTS(0x0, 0x4) +#define USART2_CTS_PA5 SILABS_DBUS_USART2_CTS(0x0, 0x5) +#define USART2_CTS_PA6 SILABS_DBUS_USART2_CTS(0x0, 0x6) +#define USART2_CTS_PA7 SILABS_DBUS_USART2_CTS(0x0, 0x7) +#define USART2_CTS_PA8 SILABS_DBUS_USART2_CTS(0x0, 0x8) +#define USART2_CTS_PA9 SILABS_DBUS_USART2_CTS(0x0, 0x9) +#define USART2_CTS_PA10 SILABS_DBUS_USART2_CTS(0x0, 0xa) +#define USART2_CTS_PA11 SILABS_DBUS_USART2_CTS(0x0, 0xb) +#define USART2_CTS_PA12 SILABS_DBUS_USART2_CTS(0x0, 0xc) +#define USART2_CTS_PA13 SILABS_DBUS_USART2_CTS(0x0, 0xd) +#define USART2_CTS_PA14 SILABS_DBUS_USART2_CTS(0x0, 0xe) +#define USART2_CTS_PA15 SILABS_DBUS_USART2_CTS(0x0, 0xf) +#define USART2_CTS_PB0 SILABS_DBUS_USART2_CTS(0x1, 0x0) +#define USART2_CTS_PB1 SILABS_DBUS_USART2_CTS(0x1, 0x1) +#define USART2_CTS_PB2 SILABS_DBUS_USART2_CTS(0x1, 0x2) +#define USART2_CTS_PB3 SILABS_DBUS_USART2_CTS(0x1, 0x3) +#define USART2_CTS_PB4 SILABS_DBUS_USART2_CTS(0x1, 0x4) +#define USART2_CTS_PB5 SILABS_DBUS_USART2_CTS(0x1, 0x5) +#define USART2_CTS_PB6 SILABS_DBUS_USART2_CTS(0x1, 0x6) +#define USART2_CTS_PB7 SILABS_DBUS_USART2_CTS(0x1, 0x7) +#define USART2_CTS_PB8 SILABS_DBUS_USART2_CTS(0x1, 0x8) +#define USART2_CTS_PB9 SILABS_DBUS_USART2_CTS(0x1, 0x9) +#define USART2_CTS_PB10 SILABS_DBUS_USART2_CTS(0x1, 0xa) +#define USART2_CTS_PB11 SILABS_DBUS_USART2_CTS(0x1, 0xb) +#define USART2_CTS_PB12 SILABS_DBUS_USART2_CTS(0x1, 0xc) +#define USART2_CTS_PB13 SILABS_DBUS_USART2_CTS(0x1, 0xd) +#define USART2_CTS_PB14 SILABS_DBUS_USART2_CTS(0x1, 0xe) +#define USART2_CTS_PB15 SILABS_DBUS_USART2_CTS(0x1, 0xf) +#define USART2_CTS_PC0 SILABS_DBUS_USART2_CTS(0x2, 0x0) +#define USART2_CTS_PC1 SILABS_DBUS_USART2_CTS(0x2, 0x1) +#define USART2_CTS_PC2 SILABS_DBUS_USART2_CTS(0x2, 0x2) +#define USART2_CTS_PC3 SILABS_DBUS_USART2_CTS(0x2, 0x3) +#define USART2_CTS_PC4 SILABS_DBUS_USART2_CTS(0x2, 0x4) +#define USART2_CTS_PC5 SILABS_DBUS_USART2_CTS(0x2, 0x5) +#define USART2_CTS_PC6 SILABS_DBUS_USART2_CTS(0x2, 0x6) +#define USART2_CTS_PC7 SILABS_DBUS_USART2_CTS(0x2, 0x7) +#define USART2_CTS_PC8 SILABS_DBUS_USART2_CTS(0x2, 0x8) +#define USART2_CTS_PC9 SILABS_DBUS_USART2_CTS(0x2, 0x9) +#define USART2_CTS_PC10 SILABS_DBUS_USART2_CTS(0x2, 0xa) +#define USART2_CTS_PC11 SILABS_DBUS_USART2_CTS(0x2, 0xb) +#define USART2_CTS_PC12 SILABS_DBUS_USART2_CTS(0x2, 0xc) +#define USART2_CTS_PC13 SILABS_DBUS_USART2_CTS(0x2, 0xd) +#define USART2_CTS_PC14 SILABS_DBUS_USART2_CTS(0x2, 0xe) +#define USART2_CTS_PC15 SILABS_DBUS_USART2_CTS(0x2, 0xf) +#define USART2_CTS_PD0 SILABS_DBUS_USART2_CTS(0x3, 0x0) +#define USART2_CTS_PD1 SILABS_DBUS_USART2_CTS(0x3, 0x1) +#define USART2_CTS_PD2 SILABS_DBUS_USART2_CTS(0x3, 0x2) +#define USART2_CTS_PD3 SILABS_DBUS_USART2_CTS(0x3, 0x3) +#define USART2_CTS_PD4 SILABS_DBUS_USART2_CTS(0x3, 0x4) +#define USART2_CTS_PD5 SILABS_DBUS_USART2_CTS(0x3, 0x5) +#define USART2_CTS_PD6 SILABS_DBUS_USART2_CTS(0x3, 0x6) +#define USART2_CTS_PD7 SILABS_DBUS_USART2_CTS(0x3, 0x7) +#define USART2_CTS_PD8 SILABS_DBUS_USART2_CTS(0x3, 0x8) +#define USART2_CTS_PD9 SILABS_DBUS_USART2_CTS(0x3, 0x9) +#define USART2_CTS_PD10 SILABS_DBUS_USART2_CTS(0x3, 0xa) +#define USART2_CTS_PD11 SILABS_DBUS_USART2_CTS(0x3, 0xb) +#define USART2_CTS_PD12 SILABS_DBUS_USART2_CTS(0x3, 0xc) +#define USART2_CTS_PD13 SILABS_DBUS_USART2_CTS(0x3, 0xd) +#define USART2_CTS_PD14 SILABS_DBUS_USART2_CTS(0x3, 0xe) +#define USART2_CTS_PD15 SILABS_DBUS_USART2_CTS(0x3, 0xf) + +#define ABUS_AEVEN0_IADC0 SILABS_ABUS(0x0, 0x0, 0x1) +#define ABUS_AEVEN0_ACMP0 SILABS_ABUS(0x0, 0x0, 0x2) +#define ABUS_AEVEN0_ACMP1 SILABS_ABUS(0x0, 0x0, 0x3) +#define ABUS_AEVEN0_VDAC0CH0 SILABS_ABUS(0x0, 0x0, 0x4) +#define ABUS_AEVEN0_VDAC1CH0 SILABS_ABUS(0x0, 0x0, 0x5) +#define ABUS_AEVEN1_IADC0 SILABS_ABUS(0x0, 0x1, 0x1) +#define ABUS_AEVEN1_ACMP0 SILABS_ABUS(0x0, 0x1, 0x2) +#define ABUS_AEVEN1_ACMP1 SILABS_ABUS(0x0, 0x1, 0x3) +#define ABUS_AEVEN1_VDAC0CH1 SILABS_ABUS(0x0, 0x1, 0x4) +#define ABUS_AEVEN1_VDAC1CH1 SILABS_ABUS(0x0, 0x1, 0x5) +#define ABUS_AODD0_IADC0 SILABS_ABUS(0x0, 0x2, 0x1) +#define ABUS_AODD0_ACMP0 SILABS_ABUS(0x0, 0x2, 0x2) +#define ABUS_AODD0_ACMP1 SILABS_ABUS(0x0, 0x2, 0x3) +#define ABUS_AODD0_VDAC0CH0 SILABS_ABUS(0x0, 0x2, 0x4) +#define ABUS_AODD0_VDAC1CH0 SILABS_ABUS(0x0, 0x2, 0x5) +#define ABUS_AODD1_IADC0 SILABS_ABUS(0x0, 0x3, 0x1) +#define ABUS_AODD1_ACMP0 SILABS_ABUS(0x0, 0x3, 0x2) +#define ABUS_AODD1_ACMP1 SILABS_ABUS(0x0, 0x3, 0x3) +#define ABUS_AODD1_VDAC0CH1 SILABS_ABUS(0x0, 0x3, 0x4) +#define ABUS_AODD1_VDAC1CH1 SILABS_ABUS(0x0, 0x3, 0x5) +#define ABUS_BEVEN0_IADC0 SILABS_ABUS(0x1, 0x0, 0x1) +#define ABUS_BEVEN0_ACMP0 SILABS_ABUS(0x1, 0x0, 0x2) +#define ABUS_BEVEN0_ACMP1 SILABS_ABUS(0x1, 0x0, 0x3) +#define ABUS_BEVEN0_VDAC0CH0 SILABS_ABUS(0x1, 0x0, 0x4) +#define ABUS_BEVEN0_VDAC1CH0 SILABS_ABUS(0x1, 0x0, 0x5) +#define ABUS_BEVEN1_IADC0 SILABS_ABUS(0x1, 0x1, 0x1) +#define ABUS_BEVEN1_ACMP0 SILABS_ABUS(0x1, 0x1, 0x2) +#define ABUS_BEVEN1_ACMP1 SILABS_ABUS(0x1, 0x1, 0x3) +#define ABUS_BEVEN1_VDAC0CH1 SILABS_ABUS(0x1, 0x1, 0x4) +#define ABUS_BEVEN1_VDAC1CH1 SILABS_ABUS(0x1, 0x1, 0x5) +#define ABUS_BODD0_IADC0 SILABS_ABUS(0x1, 0x2, 0x1) +#define ABUS_BODD0_ACMP0 SILABS_ABUS(0x1, 0x2, 0x2) +#define ABUS_BODD0_ACMP1 SILABS_ABUS(0x1, 0x2, 0x3) +#define ABUS_BODD0_VDAC0CH0 SILABS_ABUS(0x1, 0x2, 0x4) +#define ABUS_BODD0_VDAC1CH0 SILABS_ABUS(0x1, 0x2, 0x5) +#define ABUS_BODD1_IADC0 SILABS_ABUS(0x1, 0x3, 0x1) +#define ABUS_BODD1_ACMP0 SILABS_ABUS(0x1, 0x3, 0x2) +#define ABUS_BODD1_ACMP1 SILABS_ABUS(0x1, 0x3, 0x3) +#define ABUS_BODD1_VDAC0CH1 SILABS_ABUS(0x1, 0x3, 0x4) +#define ABUS_BODD1_VDAC1CH1 SILABS_ABUS(0x1, 0x3, 0x5) +#define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1) +#define ABUS_CDEVEN0_ACMP0 SILABS_ABUS(0x2, 0x0, 0x2) +#define ABUS_CDEVEN0_ACMP1 SILABS_ABUS(0x2, 0x0, 0x3) +#define ABUS_CDEVEN0_VDAC0CH0 SILABS_ABUS(0x2, 0x0, 0x4) +#define ABUS_CDEVEN0_VDAC1CH0 SILABS_ABUS(0x2, 0x0, 0x5) +#define ABUS_CDEVEN0_REPEFUSE SILABS_ABUS(0x2, 0x0, 0xb) +#define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1) +#define ABUS_CDEVEN1_ACMP0 SILABS_ABUS(0x2, 0x1, 0x2) +#define ABUS_CDEVEN1_ACMP1 SILABS_ABUS(0x2, 0x1, 0x3) +#define ABUS_CDEVEN1_VDAC0CH1 SILABS_ABUS(0x2, 0x1, 0x4) +#define ABUS_CDEVEN1_VDAC1CH1 SILABS_ABUS(0x2, 0x1, 0x5) +#define ABUS_CDODD0_IADC0 SILABS_ABUS(0x2, 0x2, 0x1) +#define ABUS_CDODD0_ACMP0 SILABS_ABUS(0x2, 0x2, 0x2) +#define ABUS_CDODD0_ACMP1 SILABS_ABUS(0x2, 0x2, 0x3) +#define ABUS_CDODD0_VDAC0CH0 SILABS_ABUS(0x2, 0x2, 0x4) +#define ABUS_CDODD0_VDAC1CH0 SILABS_ABUS(0x2, 0x2, 0x5) +#define ABUS_CDODD1_IADC0 SILABS_ABUS(0x2, 0x3, 0x1) +#define ABUS_CDODD1_ACMP0 SILABS_ABUS(0x2, 0x3, 0x2) +#define ABUS_CDODD1_ACMP1 SILABS_ABUS(0x2, 0x3, 0x3) +#define ABUS_CDODD1_VDAC0CH1 SILABS_ABUS(0x2, 0x3, 0x4) +#define ABUS_CDODD1_VDAC1CH1 SILABS_ABUS(0x2, 0x3, 0x5) + +#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG26_PINCTRL_H_ */ From 3c983e97f6d75c63bc6400005b149b2beaab0b2c Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Mon, 20 Oct 2025 21:48:37 +0200 Subject: [PATCH 3/6] soc: silabs: Support devices with 3 PPU registers Support xg26, which has a third PPU security attribution register. Signed-off-by: Aksel Skauge Mellbye --- soc/silabs/silabs_s2/soc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/soc/silabs/silabs_s2/soc.c b/soc/silabs/silabs_s2/soc.c index f9af455d8452b..bfdfc0847b2c9 100644 --- a/soc/silabs/silabs_s2/soc.c +++ b/soc/silabs/silabs_s2/soc.c @@ -92,11 +92,16 @@ void soc_prep_hook(void) CMU_S->CLKEN1_SET = CMU_CLKEN1_SMU; #endif SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK; -#if defined(SEMAILBOX_PRESENT) +#if defined(SEMAILBOX_PRESENT) && defined(SMU_PPUSATD1_SEMAILBOX) SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX)); #else SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU); #endif +#if defined(SEMAILBOX_PRESENT) && defined(SMU_PPUSATD2_SEMAILBOX) + SMU->PPUSATD2_CLR = (_SMU_PPUSATD2_MASK & ~SMU_PPUSATD2_SEMAILBOX); +#elif defined(_SMU_PPUSATD2_MASK) + SMU->PPUSATD2_CLR = _SMU_PPUSATD2_MASK; +#endif SAU->CTRL = SAU_CTRL_ALLNS_Msk; __DSB(); From 3f1f137159c3add534a927ef415d05d3f743f2fa Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Mon, 20 Oct 2025 17:09:09 +0200 Subject: [PATCH 4/6] soc: silabs: Add xg26 soc support Add hwmv2 integration for xg26 device families: * efm32pg26 * efr32bg26 * efr32mg26 * bgm26 * mgm26 Signed-off-by: Aksel Skauge Mellbye --- soc/silabs/silabs_s2/xg26/Kconfig | 32 ++ soc/silabs/silabs_s2/xg26/Kconfig.defconfig | 19 + soc/silabs/silabs_s2/xg26/Kconfig.soc | 362 ++++++++++++++++++++ soc/silabs/soc.yml | 71 ++++ west.yml | 2 +- 5 files changed, 485 insertions(+), 1 deletion(-) create mode 100644 soc/silabs/silabs_s2/xg26/Kconfig create mode 100644 soc/silabs/silabs_s2/xg26/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s2/xg26/Kconfig.soc diff --git a/soc/silabs/silabs_s2/xg26/Kconfig b/soc/silabs/silabs_s2/xg26/Kconfig new file mode 100644 index 0000000000000..b329ec7dff4bd --- /dev/null +++ b/soc/silabs/silabs_s2/xg26/Kconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SILABS_XG26 + select ARM + select ARM_TRUSTZONE_M + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_PM + select HAS_SWO + select SILABS_SISDK_CLOCK_MANAGER + select SILABS_SISDK_CORE + select SILABS_SISDK_DEVICE_INIT + select SILABS_SISDK_GPIO + +config SOC_SERIES_EFR32BG26 + select SOC_GECKO_HAS_RADIO + +config SOC_SERIES_EFR32MG26 + select SOC_GECKO_HAS_RADIO + +config SOC_SERIES_BGM26 + select SILABS_DEVICE_IS_MODULE + select SOC_GECKO_HAS_RADIO + +config SOC_SERIES_MGM26 + select SILABS_DEVICE_IS_MODULE + select SOC_GECKO_HAS_RADIO diff --git a/soc/silabs/silabs_s2/xg26/Kconfig.defconfig b/soc/silabs/silabs_s2/xg26/Kconfig.defconfig new file mode 100644 index 0000000000000..e4978ff37459c --- /dev/null +++ b/soc/silabs/silabs_s2/xg26/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SILABS_XG26 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 93 + +config PM + default n + select UART_INTERRUPT_DRIVEN if SERIAL_SUPPORT_INTERRUPT + +choice PM_POLICY + default PM_POLICY_DEFAULT + depends on PM +endchoice + +endif diff --git a/soc/silabs/silabs_s2/xg26/Kconfig.soc b/soc/silabs/silabs_s2/xg26/Kconfig.soc new file mode 100644 index 0000000000000..91df8f7f42805 --- /dev/null +++ b/soc/silabs/silabs_s2/xg26/Kconfig.soc @@ -0,0 +1,362 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SILABS_XG26 + bool + select SOC_FAMILY_SILABS_S2 + help + Silicon Labs XG26 Series SoC and modules + +config SOC_SERIES_EFM32PG26 + bool + select SOC_SILABS_XG26 + help + Silicon Labs EFM32PG26 (Pearl Gecko) Series MCU + +config SOC_SERIES_EFR32BG26 + bool + select SOC_SILABS_XG26 + help + Silicon Labs EFR32BG26 (Blue Gecko) Series MCU + +config SOC_SERIES_BGM26 + bool + select SOC_SILABS_XG26 + help + Silicon Labs BGM260 (Blue Gecko) Series MCU modules + +config SOC_SERIES_EFR32MG26 + bool + select SOC_SILABS_XG26 + help + Silicon Labs EFR32MG26 (Mighty Gecko) Series MCU + +config SOC_SERIES_MGM26 + bool + select SOC_SILABS_XG26 + help + Silicon Labs MGM260 (Mighty Gecko) Series MCU modules + +# EFM32PG26 + +config SOC_EFM32PG26B101F512IL136 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B101F512IM68 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B301F1024IL136 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B301F1024IM68 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B301F2048IL136 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B301F2048IM68 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B500F3200IL136 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B500F3200IM48 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B500F3200IM68 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B501F3200IL136 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B501F3200IM48 + bool + select SOC_SERIES_EFM32PG26 + +config SOC_EFM32PG26B501F3200IM68 + bool + select SOC_SERIES_EFM32PG26 + +# EFR32MG26 + +config SOC_EFR32MG26B521F3200IM68 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B521F3200IM48 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B520F3200IM68 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B520F3200IM48 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B511F3200IM68 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B511F3200IM48 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B511F3200IL136 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B510F3200IM68 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B510F3200IM48 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B510F3200IL136 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B421F3200IM68 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B421F3200IM48 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B420F3200IM68 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B420F3200IM48 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B411F3200IM68 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B411F3200IM48 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B410F3200IM68 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B410F3200IM48 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B311F3200IL136 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B221F3200IM48 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B221F2048IM68 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B211F3200IM48 + bool + select SOC_SERIES_EFR32MG26 + +config SOC_EFR32MG26B211F2048IM68 + bool + select SOC_SERIES_EFR32MG26 + +# EFR32BG26 + +config SOC_EFR32BG26B311F1024IL136 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B311F1024IM68 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B311F2048IL136 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B311F2048IM48 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B311F2048IM68 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B321F1024IM68 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B321F2048IM48 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B321F2048IM68 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B410F3200IM48 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B411F3200IM48 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B420F3200IM48 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B421F3200IM48 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B510F3200IL136 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B510F3200IM48 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B510F3200IM68 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B511F3200IL136 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B511F3200IM48 + bool + select SOC_SERIES_EFR32BG26 + +config SOC_EFR32BG26B511F3200IM68 + bool + select SOC_SERIES_EFR32BG26 + +# BGM26 + +config SOC_BGM260PB22VNA + bool + select SOC_SERIES_BGM26 + +config SOC_BGM260PB32VNA + bool + select SOC_SERIES_BGM26 + +# MGM26 + +config SOC_MGM260PB22VNA + bool + select SOC_SERIES_MGM26 + +config SOC_MGM260PB32VNA + bool + select SOC_SERIES_MGM26 + +config SOC_MGM260PB32VNN + bool + select SOC_SERIES_MGM26 + +config SOC_MGM260PD22VNA + bool + select SOC_SERIES_MGM26 + +config SOC_MGM260PD32VNA + bool + select SOC_SERIES_MGM26 + +config SOC_MGM260PD32VNN + bool + select SOC_SERIES_MGM26 + +config SOC_SERIES + default "efm32pg26" if SOC_SERIES_EFM32PG26 + default "efr32bg26" if SOC_SERIES_EFR32BG26 + default "efr32mg26" if SOC_SERIES_EFR32MG26 + default "bgm26" if SOC_SERIES_BGM26 + default "mgm26" if SOC_SERIES_MGM26 + +config SOC + default "efm32pg26b101f512il136" if SOC_EFM32PG26B101F512IL136 + default "efm32pg26b101f512im68" if SOC_EFM32PG26B101F512IM68 + default "efm32pg26b301f1024il136" if SOC_EFM32PG26B301F1024IL136 + default "efm32pg26b301f1024im68" if SOC_EFM32PG26B301F1024IM68 + default "efm32pg26b301f2048il136" if SOC_EFM32PG26B301F2048IL136 + default "efm32pg26b301f2048im68" if SOC_EFM32PG26B301F2048IM68 + default "efm32pg26b500f3200il136" if SOC_EFM32PG26B500F3200IL136 + default "efm32pg26b500f3200im48" if SOC_EFM32PG26B500F3200IM48 + default "efm32pg26b500f3200im68" if SOC_EFM32PG26B500F3200IM68 + default "efm32pg26b501f3200il136" if SOC_EFM32PG26B501F3200IL136 + default "efm32pg26b501f3200im48" if SOC_EFM32PG26B501F3200IM48 + default "efm32pg26b501f3200im68" if SOC_EFM32PG26B501F3200IM68 + default "efr32mg26b211f2048im68" if SOC_EFR32MG26B211F2048IM68 + default "efr32mg26b211f3200im48" if SOC_EFR32MG26B211F3200IM48 + default "efr32mg26b221f2048im68" if SOC_EFR32MG26B221F2048IM68 + default "efr32mg26b221f3200im48" if SOC_EFR32MG26B221F3200IM48 + default "efr32mg26b311f3200il136" if SOC_EFR32MG26B311F3200IL136 + default "efr32mg26b410f3200im48" if SOC_EFR32MG26B410F3200IM48 + default "efr32mg26b410f3200im68" if SOC_EFR32MG26B410F3200IM68 + default "efr32mg26b411f3200im48" if SOC_EFR32MG26B411F3200IM48 + default "efr32mg26b411f3200im68" if SOC_EFR32MG26B411F3200IM68 + default "efr32mg26b420f3200im48" if SOC_EFR32MG26B420F3200IM48 + default "efr32mg26b420f3200im68" if SOC_EFR32MG26B420F3200IM68 + default "efr32mg26b421f3200im48" if SOC_EFR32MG26B421F3200IM48 + default "efr32mg26b421f3200im68" if SOC_EFR32MG26B421F3200IM68 + default "efr32mg26b510f3200il136" if SOC_EFR32MG26B510F3200IL136 + default "efr32mg26b510f3200im48" if SOC_EFR32MG26B510F3200IM48 + default "efr32mg26b510f3200im68" if SOC_EFR32MG26B510F3200IM68 + default "efr32mg26b511f3200il136" if SOC_EFR32MG26B511F3200IL136 + default "efr32mg26b511f3200im48" if SOC_EFR32MG26B511F3200IM48 + default "efr32mg26b511f3200im68" if SOC_EFR32MG26B511F3200IM68 + default "efr32mg26b520f3200im48" if SOC_EFR32MG26B520F3200IM48 + default "efr32mg26b520f3200im68" if SOC_EFR32MG26B520F3200IM68 + default "efr32mg26b521f3200im48" if SOC_EFR32MG26B521F3200IM48 + default "efr32mg26b521f3200im68" if SOC_EFR32MG26B521F3200IM68 + default "efr32bg26b311f1024il136" if SOC_EFR32BG26B311F1024IL136 + default "efr32bg26b311f1024im68" if SOC_EFR32BG26B311F1024IM68 + default "efr32bg26b311f2048il136" if SOC_EFR32BG26B311F2048IL136 + default "efr32bg26b311f2048im48" if SOC_EFR32BG26B311F2048IM48 + default "efr32bg26b311f2048im68" if SOC_EFR32BG26B311F2048IM68 + default "efr32bg26b321f1024im68" if SOC_EFR32BG26B321F1024IM68 + default "efr32bg26b321f2048im48" if SOC_EFR32BG26B321F2048IM48 + default "efr32bg26b321f2048im68" if SOC_EFR32BG26B321F2048IM68 + default "efr32bg26b410f3200im48" if SOC_EFR32BG26B410F3200IM48 + default "efr32bg26b411f3200im48" if SOC_EFR32BG26B411F3200IM48 + default "efr32bg26b420f3200im48" if SOC_EFR32BG26B420F3200IM48 + default "efr32bg26b421f3200im48" if SOC_EFR32BG26B421F3200IM48 + default "efr32bg26b510f3200il136" if SOC_EFR32BG26B510F3200IL136 + default "efr32bg26b510f3200im48" if SOC_EFR32BG26B510F3200IM48 + default "efr32bg26b510f3200im68" if SOC_EFR32BG26B510F3200IM68 + default "efr32bg26b511f3200il136" if SOC_EFR32BG26B511F3200IL136 + default "efr32bg26b511f3200im48" if SOC_EFR32BG26B511F3200IM48 + default "efr32bg26b511f3200im68" if SOC_EFR32BG26B511F3200IM68 + default "bgm260pb22vna" if SOC_BGM260PB22VNA + default "bgm260pb32vna" if SOC_BGM260PB32VNA + default "mgm260pb22vna" if SOC_MGM260PB22VNA + default "mgm260pb32vna" if SOC_MGM260PB32VNA + default "mgm260pb32vnn" if SOC_MGM260PB32VNN + default "mgm260pd22vna" if SOC_MGM260PD22VNA + default "mgm260pd32vna" if SOC_MGM260PD32VNA + default "mgm260pd32vnn" if SOC_MGM260PD32VNN diff --git a/soc/silabs/soc.yml b/soc/silabs/soc.yml index 69f00fd9c829d..ba5a10807ad90 100644 --- a/soc/silabs/soc.yml +++ b/soc/silabs/soc.yml @@ -87,6 +87,77 @@ family: - name: mgm240pb32vnn - name: mgm240sa22vna - name: mgm240sd22vna + - name: efm32pg26 + socs: + - name: efm32pg26b101f512il136 + - name: efm32pg26b101f512im68 + - name: efm32pg26b301f1024il136 + - name: efm32pg26b301f1024im68 + - name: efm32pg26b301f2048il136 + - name: efm32pg26b301f2048im68 + - name: efm32pg26b500f3200il136 + - name: efm32pg26b500f3200im48 + - name: efm32pg26b500f3200im68 + - name: efm32pg26b501f3200il136 + - name: efm32pg26b501f3200im48 + - name: efm32pg26b501f3200im68 + - name: efr32bg26 + socs: + - name: efr32bg26b311f1024il136 + - name: efr32bg26b311f1024im68 + - name: efr32bg26b311f2048il136 + - name: efr32bg26b311f2048im48 + - name: efr32bg26b311f2048im68 + - name: efr32bg26b321f1024im68 + - name: efr32bg26b321f2048im48 + - name: efr32bg26b321f2048im68 + - name: efr32bg26b410f3200im48 + - name: efr32bg26b411f3200im48 + - name: efr32bg26b420f3200im48 + - name: efr32bg26b421f3200im48 + - name: efr32bg26b510f3200il136 + - name: efr32bg26b510f3200im48 + - name: efr32bg26b510f3200im68 + - name: efr32bg26b511f3200il136 + - name: efr32bg26b511f3200im48 + - name: efr32bg26b511f3200im68 + - name: efr32mg26 + socs: + - name: efr32mg26b521f3200im68 + - name: efr32mg26b521f3200im48 + - name: efr32mg26b520f3200im68 + - name: efr32mg26b520f3200im48 + - name: efr32mg26b511f3200im68 + - name: efr32mg26b511f3200im48 + - name: efr32mg26b511f3200il136 + - name: efr32mg26b510f3200im68 + - name: efr32mg26b510f3200im48 + - name: efr32mg26b510f3200il136 + - name: efr32mg26b421f3200im68 + - name: efr32mg26b421f3200im48 + - name: efr32mg26b420f3200im68 + - name: efr32mg26b420f3200im48 + - name: efr32mg26b411f3200im68 + - name: efr32mg26b411f3200im48 + - name: efr32mg26b410f3200im68 + - name: efr32mg26b410f3200im48 + - name: efr32mg26b311f3200il136 + - name: efr32mg26b221f3200im48 + - name: efr32mg26b221f2048im68 + - name: efr32mg26b211f3200im48 + - name: efr32mg26b211f2048im68 + - name: bgm26 + socs: + - name: bgm260pb22vna + - name: bgm260pb32vna + - name: mgm26 + socs: + - name: mgm260pb22vna + - name: mgm260pb32vna + - name: mgm260pb32vnn + - name: mgm260pd22vna + - name: mgm260pd32vna + - name: mgm260pd32vnn - name: efr32bg27 socs: - name: efr32bg27c140f768im32 diff --git a/west.yml b/west.yml index e29994ac314e8..0badbcda75e20 100644 --- a/west.yml +++ b/west.yml @@ -240,7 +240,7 @@ manifest: groups: - hal - name: hal_silabs - revision: 971c39bee2a1bcd2a31caf78606820059a585157 + revision: 71dbef43427bf0c6c64ef20be777f6d060524e82 path: modules/hal/silabs groups: - hal From 4d45b2bdcfbd3c80bff4f36f977293d6e35b42db Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Mon, 20 Oct 2025 22:26:36 +0200 Subject: [PATCH 5/6] boards: silabs: Add xg26 explorer kits Add explorer kits for EFM32PG26, EFR32xG26 and xGM240P. Signed-off-by: Aksel Skauge Mellbye --- .../explorer_kits/xg26/Kconfig.defconfig | 21 ++ .../xg26/Kconfig.mgm260p_ek2713a | 5 + .../explorer_kits/xg26/Kconfig.pg26_ek2711a | 5 + .../explorer_kits/xg26/Kconfig.xg26_ek2709a | 5 + boards/silabs/explorer_kits/xg26/board.cmake | 8 + boards/silabs/explorer_kits/xg26/board.yml | 16 + .../xg26/doc/mgm260p_ek2713a.rst | 107 ++++++ .../xg26/doc/mgm260p_ek2713a.webp | Bin 0 -> 10226 bytes .../explorer_kits/xg26/doc/pg26_ek2711a.rst | 86 +++++ .../explorer_kits/xg26/doc/pg26_ek2711a.webp | Bin 0 -> 10464 bytes .../explorer_kits/xg26/doc/xg26_ek2709a.rst | 107 ++++++ .../explorer_kits/xg26/doc/xg26_ek2709a.webp | Bin 0 -> 9998 bytes .../explorer_kits/xg26/mgm260p_ek2713a.dts | 52 +++ .../explorer_kits/xg26/mgm260p_ek2713a.yaml | 24 ++ .../xg26/mgm260p_ek2713a_defconfig | 8 + .../explorer_kits/xg26/pg26_ek2711a.dts | 20 ++ .../explorer_kits/xg26/pg26_ek2711a.yaml | 23 ++ .../explorer_kits/xg26/pg26_ek2711a_defconfig | 8 + .../explorer_kits/xg26/xg26_ek2709a.dts | 32 ++ .../explorer_kits/xg26/xg26_ek2709a.yaml | 24 ++ .../explorer_kits/xg26/xg26_ek2709a_defconfig | 8 + .../xg26/xg26_explorer_kit-pinctrl.dtsi | 97 ++++++ .../explorer_kits/xg26/xg26_explorer_kit.dtsi | 311 ++++++++++++++++++ 23 files changed, 967 insertions(+) create mode 100644 boards/silabs/explorer_kits/xg26/Kconfig.defconfig create mode 100644 boards/silabs/explorer_kits/xg26/Kconfig.mgm260p_ek2713a create mode 100644 boards/silabs/explorer_kits/xg26/Kconfig.pg26_ek2711a create mode 100644 boards/silabs/explorer_kits/xg26/Kconfig.xg26_ek2709a create mode 100644 boards/silabs/explorer_kits/xg26/board.cmake create mode 100644 boards/silabs/explorer_kits/xg26/board.yml create mode 100644 boards/silabs/explorer_kits/xg26/doc/mgm260p_ek2713a.rst create mode 100644 boards/silabs/explorer_kits/xg26/doc/mgm260p_ek2713a.webp create mode 100644 boards/silabs/explorer_kits/xg26/doc/pg26_ek2711a.rst create mode 100644 boards/silabs/explorer_kits/xg26/doc/pg26_ek2711a.webp create mode 100644 boards/silabs/explorer_kits/xg26/doc/xg26_ek2709a.rst create mode 100644 boards/silabs/explorer_kits/xg26/doc/xg26_ek2709a.webp create mode 100644 boards/silabs/explorer_kits/xg26/mgm260p_ek2713a.dts create mode 100644 boards/silabs/explorer_kits/xg26/mgm260p_ek2713a.yaml create mode 100644 boards/silabs/explorer_kits/xg26/mgm260p_ek2713a_defconfig create mode 100644 boards/silabs/explorer_kits/xg26/pg26_ek2711a.dts create mode 100644 boards/silabs/explorer_kits/xg26/pg26_ek2711a.yaml create mode 100644 boards/silabs/explorer_kits/xg26/pg26_ek2711a_defconfig create mode 100644 boards/silabs/explorer_kits/xg26/xg26_ek2709a.dts create mode 100644 boards/silabs/explorer_kits/xg26/xg26_ek2709a.yaml create mode 100644 boards/silabs/explorer_kits/xg26/xg26_ek2709a_defconfig create mode 100644 boards/silabs/explorer_kits/xg26/xg26_explorer_kit-pinctrl.dtsi create mode 100644 boards/silabs/explorer_kits/xg26/xg26_explorer_kit.dtsi diff --git a/boards/silabs/explorer_kits/xg26/Kconfig.defconfig b/boards/silabs/explorer_kits/xg26/Kconfig.defconfig new file mode 100644 index 0000000000000..b02f4464d4cd8 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/Kconfig.defconfig @@ -0,0 +1,21 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XG26_EK2709A || BOARD_PG26_EK2711A || BOARD_MGM260P_EK2713A + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +config FPU + default y if SOC_GECKO_USE_RAIL || BT + +if BT + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif diff --git a/boards/silabs/explorer_kits/xg26/Kconfig.mgm260p_ek2713a b/boards/silabs/explorer_kits/xg26/Kconfig.mgm260p_ek2713a new file mode 100644 index 0000000000000..4cb4c5bda1163 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/Kconfig.mgm260p_ek2713a @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MGM260P_EK2713A + select SOC_MGM260PD32VNA diff --git a/boards/silabs/explorer_kits/xg26/Kconfig.pg26_ek2711a b/boards/silabs/explorer_kits/xg26/Kconfig.pg26_ek2711a new file mode 100644 index 0000000000000..4c920046b0380 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/Kconfig.pg26_ek2711a @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PG26_EK2711A + select SOC_EFM32PG26B500F3200IM68 diff --git a/boards/silabs/explorer_kits/xg26/Kconfig.xg26_ek2709a b/boards/silabs/explorer_kits/xg26/Kconfig.xg26_ek2709a new file mode 100644 index 0000000000000..1651fa33926a5 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/Kconfig.xg26_ek2709a @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XG26_EK2709A + select SOC_EFR32MG26B510F3200IM48 diff --git a/boards/silabs/explorer_kits/xg26/board.cmake b/boards/silabs/explorer_kits/xg26/board.cmake new file mode 100644 index 0000000000000..3e79f6fbcf227 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/board.cmake @@ -0,0 +1,8 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32MG26BxxxF3200") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(silabs_commander "--device=${CONFIG_SOC}") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/explorer_kits/xg26/board.yml b/boards/silabs/explorer_kits/xg26/board.yml new file mode 100644 index 0000000000000..6dff5b35a5c5a --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/board.yml @@ -0,0 +1,16 @@ +boards: + - name: mgm260p_ek2713a + full_name: xGM260P Explorer Kit (MGM260P-EK2713A) + vendor: silabs + socs: + - name: mgm260pd32vna + - name: pg26_ek2711a + full_name: EFM32PG26 Explorer Kit (PG26-EK2711A) + vendor: silabs + socs: + - name: efm32pg26b500f3200im68 + - name: xg26_ek2709a + full_name: EFR32xG26 Explorer Kit (xG26-EK2709A) + vendor: silabs + socs: + - name: efr32mg26b510f3200im48 diff --git a/boards/silabs/explorer_kits/xg26/doc/mgm260p_ek2713a.rst b/boards/silabs/explorer_kits/xg26/doc/mgm260p_ek2713a.rst new file mode 100644 index 0000000000000..742ad7d0cc2a3 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/doc/mgm260p_ek2713a.rst @@ -0,0 +1,107 @@ +.. zephyr:board:: mgm260p_ek2713a + +Overview +******** + +The `MGM260P Explorer Kit`_ is a small form factor development and evaluation platform based on the +`MGM260P Module`_. The Explorer Kit is focused on rapid prototyping and concept creation of IoT +applications for 2.4 GHz wireless protocols including Bluetooth LE, Bluetooth mesh, Zigbee, Thread, +and Matter. + +.. _MGM260P Explorer Kit: + https://www.silabs.com/development-tools/wireless/xgm260p-explorer-kit + +.. _MGM260P Module: + https://www.silabs.com/wireless/zigbee/efr32mg26-series-2-modules + +Hardware +******** + +- MGM260PD32VNA Module +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 3200 kB +- RAM: 512 kB +- Transmit power: up to +20 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) on the board and HFXO (40 MHz) in the module. + +For more information about the MGM260P module and Explorer Kit, refer to these documents: + +- `MGM260P Datasheet`_ +- `EFR32xG26 Reference Manual`_ +- `MGM260P-EK2713A User Guide`_ + +.. _MGM260P Datasheet: + https://www.silabs.com/documents/public/data-sheets/mgm260p-datasheet.pdf + +.. _EFR32xG26 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg26-rm.pdf + +.. _MGM260P-EK2713A User Guide: + https://www.silabs.com/documents/public/user-guides/ug613-xgm260-ek2713a-user-guide.pdf + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The MGM260P Module is configured to use the HFRCODPLL oscillator at 80 MHz as the system clock, +locked to the 40 MHz crystal oscillator. + +Serial Port +=========== + +The MGM260P Module has 3 USARTs and 4 EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Connect the Explorer Kit to your host computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mgm260p_ek2713a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! mgm260p_ek2713a + +Bluetooth +========= + +To use Bluetooth functionality, run the command below to retrieve necessary binary +blobs from the Silicon Labs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: mgm260p_ek2713a + :goals: build diff --git a/boards/silabs/explorer_kits/xg26/doc/mgm260p_ek2713a.webp b/boards/silabs/explorer_kits/xg26/doc/mgm260p_ek2713a.webp new file mode 100644 index 0000000000000000000000000000000000000000..a4c9c8c0b4b17b5692f30c8a1e0e650dee3e460a GIT binary patch literal 10226 zcmVyI?QlYPSdclS^7KlVSt`?>!E#6N`}>VCQVg8oJP+xpw{>oTJMs7k5-h};Z_BqdapbXVt~2GM|8b=pIC?ayY{`92|ssJBo2 zZokSSsKz0BFX_jwJUFqrTmZY$nfUR-`hgk?Px$T6UJSJKq;E5?9Uo_uTw*CXmb3MN>5d?h4~=`o^2(1 zB<#9^>6-h@`4nTfx6Bc zmZ%t2I>;GhONlN|7rgnxF8=*NRu$vfDz`{E*{7t4*qGfSE05m z;zZnNrY*wyN{N&SoKfA~CJt-gymP9_dfGJ;)hD^J_LfqL+bJQV}VHT(S(Nw_nxO#*Vc4z1Of4s z={r9bqQVp+<^l7zuT0xIC-`j)*yB;9tVs3 zmjku#IqN zM7>5gJMTRULQNC5FCDq;+WV=%r6K$00eouZ6W=ZF%A(;3$4Y#3V5KberrB&&Mm^hjpX&@qw&WH^1Fi7{is|IIYXwm(>{}L8+p#>W9#3TCpL){?q-sv`s0#mtN^TPX3{p3Shz z_lFd3SFF>*xaZCF1rxEj5FI0P zRDS_M=bLlcwi>)-OhO1A20uF9Z&71?SNdBjYGe+QW}>A2h80k9@=;1J81yY>2-~$= zfzS?qDmuhm+Hy#gkZRT(PZYzFBsf3XexbfrDZ{Gr;AV&@`Oh`nUAnFx8zH9#-esbd z`|v7fIw0Y$Q~js>cHSJEN2y#+(Az?TB$FDa7QBltvBcpUPnu(`$(kssxq(_@SpJ^6 zGb-ehPE>~n`%m{_L3zE^%ohEGgqrx zc9P1Vl^O@E3-c~Me~Y`f=;?cc)BZbi*N0&dXPM*`sv#(g?#3CV4&Lus7i1f^8)zqj z6v`@NCwFb&<=h^HbN6iH?1pP*;cer$J)2>aO&a&r73T8Lt%ZFC_|ux&MQ2=+magZ` zy6bBHK!N2*kl_Dm{~fv$p;|={zLe2+b@TuL{{L3d5b5(b`zg=@z8499lf2~n$&f%^ z?o+(gq%(bwA0>1aY$+_DSK%s4wJYb5m}^L}B$COgNR&hhTD)emQ;3~mS^NiZSh#sO(ZRNx(VK_+Ghh1X}!P9aN4 z)a>-S*B8t6Xk(V%tHfH?c;~5>4~)Jip2!a|3h-$!Q$JxWo~9+4p;kGDP;xZ3h$J)K zGA&r3z=>AF`M`&Ea!`)blIz2}IAn=r!L4y4yefye2h?@;VQH@YhZj3y+`Q$7>%*j& z^xH0b&we1xU*S)poB|e1PC+bkZnRD>22kyT2R^+8F=0@eT~o<0NJg zFsuGZ%qw>v+O+#dt*i~G-@AQGh zqH(FpEi~kqUjBAUo=w{UPtTxE0|tC5e6|EcZRPotcYBEBGu7RLH< zEQ`AUS6lr5&`;nRtd0-{iO|{_4--@YC_r;PfAX}h#_3R$(i4qdq8rR-)#Bnuo>l{0 z!Wjb1F(fZghvD>ayc_-30Nzctbnjwc{p$K^0if37lN=PlO_!8bLN?MT5X0UDFy=ex zNS_Oa8<;^1CaIrec)j0inW+Hg$oJ=L=?d8Axy!N zL%rd`i|dB9Dx4zsJ#r&7GfO0!Gi!=Mh4o1~ z=_H)Cz2jo3*~5r3_JEA{_ZIFDI^4YlMtv!=s-?dvVnxzGmg>N&vdG{4N-Jh);C|NY zd6qPoglV36-PHfO3mv|%bjy(OoR;TZ3hj^;kEn?#A|ug4@f*4NSx5PR6m#?c3I;sS ze^+86New`HCFByVHcjOf2pXDA0N`zRFfzsa4e{V)mKPT! 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The Explorer Kit is focused on rapid prototyping and concept creation of IoT +applications. + +.. _EFM32PG26 Explorer Kit: + https://www.silabs.com/development-tools/mcu/32-bit/efm32pg26-explorer-kit + +.. _EFM32PG26 MCU: + https://www.silabs.com/wireless/zigbee/efr32mg26-series-2-socs + +Hardware +******** + +- EFM32PG26B500F3200IM68 MCU +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 3200 kB +- RAM: 512 kB +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (39 MHz) on the board. + +For more information about the EFM32PG26 MCU and Explorer Kit, refer to these documents: + +- `EFM32PG26 Datasheet`_ +- `EFM32PG26 Reference Manual`_ +- `PG26-EK2711A User Guide`_ + +.. _EFM32PG26 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32pg26-datasheet.pdf + +.. _EFM32PG26 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32pg26-rm.pdf + +.. _PG26-EK2711A User Guide: + https://www.silabs.com/documents/public/user-guides/ug608-brd2711a-user-guide.pdf + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The EFM32PG26 MCU is configured to use the HFRCODPLL oscillator at 78 MHz as the system clock, +locked to the 39 MHz crystal oscillator on the board. + +Serial Port +=========== + +The EFM32PG26 MCU has 3 USARTs and 4 EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Connect the Explorer Kit to your host computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: pg26_ek2711a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! pg26_ek2711a diff --git a/boards/silabs/explorer_kits/xg26/doc/pg26_ek2711a.webp b/boards/silabs/explorer_kits/xg26/doc/pg26_ek2711a.webp new file mode 100644 index 0000000000000000000000000000000000000000..e7213a8ffd48c580ae60580c537290664b228712 GIT binary patch literal 10464 zcmV<6C?D5SNk&H4C;$LgMM6+kP&gpWC;$MktN@(>Dv$wH0X~sJoJ%F6rXi$JTG+r6 z32AQObMXDf4l5&bw&TnPoqwTk`aLb)qC3Uk=`u(Bx&3F-Plexy{_Fc&=%3@CNd7zW zx7Xi1eSKHqTo$auW}asDs&W8FWlU+(?DKbn77|F!Es`(F-ky#KTPmiPw#iT%_5|N7r{FY15v zf2#BW^%wr%^q&EruH9(=dp()IcnU{;i>{6ks?E{zboH}hV#m|pBk~WA z?CKOSyvu2e&$=F_D9$CsSuF=KOF-PWE(~>!S zroDzefm}Z5M$jYE@Cb!yh6I=}QN zXUI6s0-z>KD1DXRnP*N&=g&IrC7dI$TeH2I*B{CsP9nE<)h%g~BbR0_?u*L}8~1$NqVzB+k^{Ar0LS(+Gl(8h4W_(_)n9{lk`shfH8 zJ^tu0xiqxbFnQ#VnYbjnfO1{q@$tAByt=8~BiXKXU`tN~e@6TzIU}F=LjS~;O|rxu z0I0dErgNlUN`f%Le3wMOMgd47caA1U6~m)$FAXCr47JMM5cLA0ei+Qdg1h=s*nUJ# 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The Explorer Kit is focused on rapid prototyping and concept creating of IoT +applications for 2.4 GHz wireless protocols including Bluetooth LE, Bluetooth mesh, Zigbee, Thread, +and Matter. + +.. _EFR32xG26 Explorer Kit: + https://www.silabs.com/development-tools/wireless/efr32xg26-explorer-kit + +.. _EFR32MG26 SoC: + https://www.silabs.com/wireless/zigbee/efr32mg26-series-2-socs + +Hardware +******** + +- EFR32MG26B510F3200IM48 SoC +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 3200 kB +- RAM: 512 kB +- Transmit power: up to +10 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (39 MHz) on the board. + +For more information about the EFR32MG26 SoC and Explorer Kit, refer to these documents: + +- `EFR32MG26 Datasheet`_ +- `EFR32xG26 Reference Manual`_ +- `xG26-EK2709A User Guide`_ + +.. _EFR32MG26 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg26-datasheet.pdf + +.. _EFR32xG26 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg26-rm.pdf + +.. _xG26-EK2709A User Guide: + https://www.silabs.com/documents/public/user-guides/ug594-brd2709a-user-guide.pdf + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The EFR32MG26 SoC is configured to use the HFRCODPLL oscillator at 78 MHz as the system clock, +locked to the 39 MHz crystal oscillator on the board. + +Serial Port +=========== + +The EFR32MG26 SoC has 3 USARTs and 4 EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Connect the Explorer Kit to your host computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xg26_ek2709a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! xg26_ek2709a + +Bluetooth +========= + +To use Bluetooth functionality, run the command below to retrieve necessary binary +blobs from the Silicon Labs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. 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+#include +#include "xg26_explorer_kit.dtsi" + +/ { + model = "Silicon Labs xGM260P Explorer Kit"; + compatible = "silabs,mgm260p_ek2713a", "silabs,mgm26"; + + chosen { + zephyr,bt-hci = &bt_hci_silabs; + }; +}; + +&button0 { + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; +}; + +&button1 { + gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; +}; + +&bt_hci_silabs { + status = "okay"; +}; + +&cpu0 { + clock-frequency = ; +}; + +&hfrcodpll { + clock-frequency = ; +}; + +&itm { + swo-ref-frequency = ; +}; + +&led0 { + gpios = <&gpioa 9 GPIO_ACTIVE_HIGH>; +}; + +&timer0_default { + group0 { + pins = , ; + }; +}; diff --git a/boards/silabs/explorer_kits/xg26/mgm260p_ek2713a.yaml b/boards/silabs/explorer_kits/xg26/mgm260p_ek2713a.yaml new file mode 100644 index 0000000000000..c4f101f1068a5 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/mgm260p_ek2713a.yaml @@ -0,0 +1,24 @@ +identifier: mgm260p_ek2713a +name: xGM260P Explorer Kit (MGM260P-EK2713A, BRD2713A) +type: mcu +arch: arm +ram: 512 +flash: 3200 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - bluetooth + - comparator + - counter + - dac + - dma + - entropy + - flash + - gpio + - pwm + - spi + - uart + - watchdog +vendor: silabs diff --git a/boards/silabs/explorer_kits/xg26/mgm260p_ek2713a_defconfig b/boards/silabs/explorer_kits/xg26/mgm260p_ek2713a_defconfig new file mode 100644 index 0000000000000..5a447b06ea2a9 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/mgm260p_ek2713a_defconfig @@ -0,0 +1,8 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y diff --git a/boards/silabs/explorer_kits/xg26/pg26_ek2711a.dts b/boards/silabs/explorer_kits/xg26/pg26_ek2711a.dts new file mode 100644 index 0000000000000..3b94bd1b99939 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/pg26_ek2711a.dts @@ -0,0 +1,20 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "xg26_explorer_kit.dtsi" + +/ { + model = "Silicon Labs PG26 Explorer Kit"; + compatible = "silabs,pg26_ek2711a", "silabs,efm32pg26"; +}; + +&hfxo { + ctune = <140>; + precision = <50>; + status = "okay"; +}; diff --git a/boards/silabs/explorer_kits/xg26/pg26_ek2711a.yaml b/boards/silabs/explorer_kits/xg26/pg26_ek2711a.yaml new file mode 100644 index 0000000000000..e502340625ee5 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/pg26_ek2711a.yaml @@ -0,0 +1,23 @@ +identifier: pg26_ek2711a +name: EFM32PG26 Explorer Kit (PG26-EK2711A, BRD2711A) +type: mcu +arch: arm +ram: 512 +flash: 3200 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - comparator + - counter + - dac + - dma + - entropy + - flash + - gpio + - pwm + - spi + - uart + - watchdog +vendor: silabs diff --git a/boards/silabs/explorer_kits/xg26/pg26_ek2711a_defconfig b/boards/silabs/explorer_kits/xg26/pg26_ek2711a_defconfig new file mode 100644 index 0000000000000..5a447b06ea2a9 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/pg26_ek2711a_defconfig @@ -0,0 +1,8 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y diff --git a/boards/silabs/explorer_kits/xg26/xg26_ek2709a.dts b/boards/silabs/explorer_kits/xg26/xg26_ek2709a.dts new file mode 100644 index 0000000000000..b17fd2c91342d --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/xg26_ek2709a.dts @@ -0,0 +1,32 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "xg26_explorer_kit.dtsi" + +/ { + model = "Silicon Labs EFR32xG26 Explorer Kit"; + compatible = "silabs,xg26_ek2709a", "silabs,efr32mg26"; + + chosen { + zephyr,bt-hci = &bt_hci_silabs; + }; +}; + +&bt_hci_silabs { + status = "okay"; +}; + +&hfxo { + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&radio { + pa-voltage-mv = <1800>; +}; diff --git a/boards/silabs/explorer_kits/xg26/xg26_ek2709a.yaml b/boards/silabs/explorer_kits/xg26/xg26_ek2709a.yaml new file mode 100644 index 0000000000000..55fd848de81aa --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/xg26_ek2709a.yaml @@ -0,0 +1,24 @@ +identifier: xg26_ek2709a +name: EFR32xG26 Explorer Kit (xG26-EK2709A, BRD2709A) +type: mcu +arch: arm +ram: 512 +flash: 3200 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - bluetooth + - comparator + - counter + - dac + - dma + - entropy + - flash + - gpio + - pwm + - spi + - uart + - watchdog +vendor: silabs diff --git a/boards/silabs/explorer_kits/xg26/xg26_ek2709a_defconfig b/boards/silabs/explorer_kits/xg26/xg26_ek2709a_defconfig new file mode 100644 index 0000000000000..5a447b06ea2a9 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/xg26_ek2709a_defconfig @@ -0,0 +1,8 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y diff --git a/boards/silabs/explorer_kits/xg26/xg26_explorer_kit-pinctrl.dtsi b/boards/silabs/explorer_kits/xg26/xg26_explorer_kit-pinctrl.dtsi new file mode 100644 index 0000000000000..d5149c288b01f --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/xg26_explorer_kit-pinctrl.dtsi @@ -0,0 +1,97 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + eusart1_default: eusart1_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + iadc0_default: iadc0_default { + group0 { + silabs,analog-bus = ; + }; + }; + + itm_default: itm_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + bias-pull-up; + drive-open-drain; + }; + }; + + pti_default: pti_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; + + timer0_default: timer0_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; + + timer1_default: timer1_default { + group0 { + pins = ; + drive-push-pull; + output-low; + }; + }; + + usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + usart1_default: usart1_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; +}; diff --git a/boards/silabs/explorer_kits/xg26/xg26_explorer_kit.dtsi b/boards/silabs/explorer_kits/xg26/xg26_explorer_kit.dtsi new file mode 100644 index 0000000000000..09c8f7df83fb9 --- /dev/null +++ b/boards/silabs/explorer_kits/xg26/xg26_explorer_kit.dtsi @@ -0,0 +1,311 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "xg26_explorer_kit-pinctrl.dtsi" + +/ { + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,console = &usart0; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,uart-pipe = &usart0; + }; + + aliases { + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + pwm-led1 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + + /* If enabled, MCUboot uses this for recovery mode entrance */ + mcuboot-led0 = &led0; + mcuboot-button0 = &button0; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>; + }; + + led1: led_1 { + gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0>; + gpio-map-pass-thru = <0 GPIO_DT_FLAGS_MASK>; + gpio-map = <0 0 &gpiod 2 0>, /* AN */ + <1 0 &gpioc 6 0>, /* RST */ + <2 0 &gpioc 4 0>, /* CS */ + <3 0 &gpioc 3 0>, /* SCK */ + <4 0 &gpioc 1 0>, /* MISO */ + <5 0 &gpioc 2 0>, /* MOSI */ + <6 0 &gpioa 7 0>, /* PWM */ + <7 0 &gpioc 0 0>, /* INT */ + <8 0 &gpioa 5 0>, /* RX */ + <9 0 &gpioa 4 0>, /* TX */ + <10 0 &gpiod 5 0>, /* SCL */ + <11 0 &gpiod 7 0>; /* SDA */ + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + + pwm_led1: pwm_led_1 { + pwms = <&timer0_pwm 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + qwiic_connector: stemma-qt-connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0>; + gpio-map-pass-thru = <0 GPIO_DT_FLAGS_MASK>; + gpio-map = <0 0 &gpiod 5 0>, /* SCL */ + <1 0 &gpiod 7 0>; /* SDA */ + }; + + mikrobus_adc: zephyr,user { + io-channels = <&adc0 0>; + }; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + + +&timer1 { + status = "okay"; + + zephyr_pwm: timer1_pwm: pwm { + pinctrl-0 = <&timer1_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + swo-ref-frequency = ; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + status = "okay"; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-autorecover; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-m = <1919>; + dpll-n = <3839>; +}; + +&lfxo { + ctune = <25>; + precision = <50>; + status = "okay"; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&lcdclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + +&usart0 { + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usart1 { + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&eusart1 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpioc 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&wdog0 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&sysrtc0 { + status = "okay"; +}; + +&adc0 { + pinctrl-0 = <&iadc0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + zephyr,acquisition-time = ; + zephyr,gain = "ADC_GAIN_1"; + zephyr,input-positive = ; + zephyr,reference = "ADC_REF_VDD_1"; + zephyr,resolution = <12>; + zephyr,vref-mv = <3300>; + }; +}; + +&vdac0 { + status = "okay"; +}; + +&vdac1 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 KiB for the bootloader */ + boot_partition: partition@0 { + reg = <0x00000000 DT_SIZE_K(48)>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 1560 KiB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 DT_SIZE_K(1560)>; + label = "image-0"; + }; + + /* Reserve 1560 KiB for the application in slot 1 */ + slot1_partition: partition@192000 { + reg = <0x00192000 DT_SIZE_K(1560)>; + label = "image-1"; + }; + + /* Set 32 KiB of storage at the end of the 3200 KiB of flash */ + storage_partition: partition@318000 { + reg = <0x00318000 DT_SIZE_K(32)>; + label = "storage"; + }; + }; +}; + +mikrobus_i2c: &i2c0 {}; + +mikrobus_spi: &eusart1 {}; + +mikrobus_uart: &usart1 {}; + +zephyr_i2c: &i2c0 {}; + +zephyr_spi: &eusart1 {}; From 7b8dffbec6c3e88a5367aa867e45fed6925666ec Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Tue, 21 Oct 2025 13:49:32 +0200 Subject: [PATCH 6/6] boards: silabs: Add xg26 radio boards Add radio boards for EFR32xG26 and xGM260P. Signed-off-by: Aksel Skauge Mellbye --- .../radio_boards/xg26/Kconfig.defconfig | 21 + .../radio_boards/xg26/Kconfig.mgm260p_rb4350a | 5 + .../radio_boards/xg26/Kconfig.xg26_rb4118a | 5 + .../radio_boards/xg26/Kconfig.xg26_rb4120a | 5 + boards/silabs/radio_boards/xg26/board.cmake | 8 + boards/silabs/radio_boards/xg26/board.yml | 16 + .../radio_boards/xg26/doc/mgm260p_rb4350a.rst | 108 +++++ .../xg26/doc/mgm260p_rb4350a.webp | Bin 0 -> 6336 bytes .../radio_boards/xg26/doc/xg26_rb4118a.rst | 109 +++++ .../radio_boards/xg26/doc/xg26_rb4118a.webp | Bin 0 -> 6170 bytes .../radio_boards/xg26/doc/xg26_rb4120a.rst | 109 +++++ .../radio_boards/xg26/doc/xg26_rb4120a.webp | Bin 0 -> 5678 bytes .../xg26/mgm260p_rb4350a-pinctrl.dtsi | 75 ++++ .../radio_boards/xg26/mgm260p_rb4350a.dts | 353 ++++++++++++++++ .../radio_boards/xg26/mgm260p_rb4350a.yaml | 23 ++ .../xg26/mgm260p_rb4350a_defconfig | 8 + .../radio_boards/xg26/pre_dt_board.cmake | 5 + .../silabs/radio_boards/xg26/xg26_rb4118a.dts | 14 + .../radio_boards/xg26/xg26_rb4118a.yaml | 23 ++ .../radio_boards/xg26/xg26_rb4118a_defconfig | 8 + .../silabs/radio_boards/xg26/xg26_rb4120a.dts | 14 + .../radio_boards/xg26/xg26_rb4120a.yaml | 23 ++ .../radio_boards/xg26/xg26_rb4120a_defconfig | 8 + .../xg26/xg26_rb41xxa-pinctrl.dtsi | 104 +++++ .../radio_boards/xg26/xg26_rb41xxa.dtsi | 389 ++++++++++++++++++ 25 files changed, 1433 insertions(+) create mode 100644 boards/silabs/radio_boards/xg26/Kconfig.defconfig create mode 100644 boards/silabs/radio_boards/xg26/Kconfig.mgm260p_rb4350a create mode 100644 boards/silabs/radio_boards/xg26/Kconfig.xg26_rb4118a create mode 100644 boards/silabs/radio_boards/xg26/Kconfig.xg26_rb4120a create mode 100644 boards/silabs/radio_boards/xg26/board.cmake create mode 100644 boards/silabs/radio_boards/xg26/board.yml create mode 100644 boards/silabs/radio_boards/xg26/doc/mgm260p_rb4350a.rst create mode 100644 boards/silabs/radio_boards/xg26/doc/mgm260p_rb4350a.webp create mode 100644 boards/silabs/radio_boards/xg26/doc/xg26_rb4118a.rst create mode 100644 boards/silabs/radio_boards/xg26/doc/xg26_rb4118a.webp create mode 100644 boards/silabs/radio_boards/xg26/doc/xg26_rb4120a.rst create mode 100644 boards/silabs/radio_boards/xg26/doc/xg26_rb4120a.webp create mode 100644 boards/silabs/radio_boards/xg26/mgm260p_rb4350a-pinctrl.dtsi create mode 100644 boards/silabs/radio_boards/xg26/mgm260p_rb4350a.dts create mode 100644 boards/silabs/radio_boards/xg26/mgm260p_rb4350a.yaml create mode 100644 boards/silabs/radio_boards/xg26/mgm260p_rb4350a_defconfig create mode 100644 boards/silabs/radio_boards/xg26/pre_dt_board.cmake create mode 100644 boards/silabs/radio_boards/xg26/xg26_rb4118a.dts create mode 100644 boards/silabs/radio_boards/xg26/xg26_rb4118a.yaml create mode 100644 boards/silabs/radio_boards/xg26/xg26_rb4118a_defconfig create mode 100644 boards/silabs/radio_boards/xg26/xg26_rb4120a.dts create mode 100644 boards/silabs/radio_boards/xg26/xg26_rb4120a.yaml create mode 100644 boards/silabs/radio_boards/xg26/xg26_rb4120a_defconfig create mode 100644 boards/silabs/radio_boards/xg26/xg26_rb41xxa-pinctrl.dtsi create mode 100644 boards/silabs/radio_boards/xg26/xg26_rb41xxa.dtsi diff --git a/boards/silabs/radio_boards/xg26/Kconfig.defconfig b/boards/silabs/radio_boards/xg26/Kconfig.defconfig new file mode 100644 index 0000000000000..77451e9b86045 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/Kconfig.defconfig @@ -0,0 +1,21 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XG26_RB4118A || BOARD_XG26_RB4120A || BOARD_MGM260P_RB4350A + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +config FPU + default y if SOC_GECKO_USE_RAIL || BT + +if BT + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif diff --git a/boards/silabs/radio_boards/xg26/Kconfig.mgm260p_rb4350a b/boards/silabs/radio_boards/xg26/Kconfig.mgm260p_rb4350a new file mode 100644 index 0000000000000..27d4a218dcb16 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/Kconfig.mgm260p_rb4350a @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MGM260P_RB4350A + select SOC_MGM260PD22VNA diff --git a/boards/silabs/radio_boards/xg26/Kconfig.xg26_rb4118a b/boards/silabs/radio_boards/xg26/Kconfig.xg26_rb4118a new file mode 100644 index 0000000000000..290743b13293e --- /dev/null +++ b/boards/silabs/radio_boards/xg26/Kconfig.xg26_rb4118a @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XG26_RB4118A + select SOC_EFR32MG26B510F3200IL136 diff --git a/boards/silabs/radio_boards/xg26/Kconfig.xg26_rb4120a b/boards/silabs/radio_boards/xg26/Kconfig.xg26_rb4120a new file mode 100644 index 0000000000000..ebf05cab59db1 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/Kconfig.xg26_rb4120a @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XG26_RB4120A + select SOC_EFR32MG26B510F3200IM68 diff --git a/boards/silabs/radio_boards/xg26/board.cmake b/boards/silabs/radio_boards/xg26/board.cmake new file mode 100644 index 0000000000000..3e79f6fbcf227 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/board.cmake @@ -0,0 +1,8 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32MG26BxxxF3200") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(silabs_commander "--device=${CONFIG_SOC}") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/radio_boards/xg26/board.yml b/boards/silabs/radio_boards/xg26/board.yml new file mode 100644 index 0000000000000..d5aac65e1cea1 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/board.yml @@ -0,0 +1,16 @@ +boards: + - name: mgm260p_rb4350a + full_name: MGM260P 2.4 GHz +10 dBm Radio Board + vendor: silabs + socs: + - name: mgm260pd22vna + - name: xg26_rb4118a + full_name: EFR32xG26 2.4 GHz +10 dBm BGA136 Radio Board + vendor: silabs + socs: + - name: efr32mg26b510f3200il136 + - name: xg26_rb4120a + full_name: EFR32xG26 2.4 GHz +10 dBm Radio Board + vendor: silabs + socs: + - name: efr32mg26b510f3200im68 diff --git a/boards/silabs/radio_boards/xg26/doc/mgm260p_rb4350a.rst b/boards/silabs/radio_boards/xg26/doc/mgm260p_rb4350a.rst new file mode 100644 index 0000000000000..7034906a94b73 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/doc/mgm260p_rb4350a.rst @@ -0,0 +1,108 @@ +.. zephyr:board:: mgm260p_rb4350a + +Overview +******** + +The `MGM260P +10 dBm Radio Board`_ is a plug-in board for the Wireless Starter Kit Mainboard +(BRD4001A) and the Wireless Pro Kit Mainboard (BRD4002A) based on the `MGM260P Module`_. It +supports the development of 2.4 GHz Wireless IoT devices for protocols including Bluetooth LE, +Bluetooth Mesh, Zigbee, and Matter. + +See :ref:`silabs_radio_boards` for more information about the Wireless Mainboard platform. + +.. _MGM260P +10 dBm Radio Board: + https://www.silabs.com/development-tools/wireless/mgm260p-rb4350a-wireless-10-dbm-radio-board + +.. _MGM260P Module: + https://www.silabs.com/wireless/zigbee/efr32mg26-series-2-modules + +Hardware +******** + +- MGM260PD22VNA Module +- CPU core: ARM Cortex®-M33 with FPU, DSP and TrustZone +- Memory: 3200 kB Flash, 512 kB RAM +- Transmit power: up to +10 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) on the board and HFXO (40 MHz) in the module + +For more information about the MGM260P module and radio board, refer to these documents: + +- `MGM260P Datasheet`_ +- `EFR32xG26 Reference Manual`_ +- `MGM260P-RB4350A User Guide`_ + +.. _MGM260P Datasheet: + https://www.silabs.com/documents/public/data-sheets/mgm260p-datasheet.pdf + +.. _EFR32xG26 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg26-rm.pdf + +.. _MGM260P-RB4350A User Guide: + https://www.silabs.com/documents/public/user-guides/ug596-brd4350a-user-guide.pdf + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The MGM260P Module is configured to use the HFRCODPLL oscillator at 80 MHz as the system clock, +locked to the 40 MHz crystal oscillator. + +Serial Port +=========== + +The MGM260P Module has 3 USARTs and 4 EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Connect the board to your host computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mgm260p_rb4350a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! mgm260p_rb4350a + +Bluetooth +========= + +To use Bluetooth functionality, run the command below to retrieve necessary binary +blobs from the Silicon Labs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: mgm260p_rb4350a + :goals: build diff --git a/boards/silabs/radio_boards/xg26/doc/mgm260p_rb4350a.webp b/boards/silabs/radio_boards/xg26/doc/mgm260p_rb4350a.webp new file mode 100644 index 0000000000000000000000000000000000000000..312beb9349c531c59e669f27c7cec80341c7c233 GIT binary patch literal 6336 zcmV;x7(eGyNk&Gv7ytlQMM6+kP&gp07ytn9fB>BVDv$wH0X~sJolB*orXr$qih#fp z32AQpDj138!40=9y$?>W=+Eojtp9%g;rnywPvbu|{m1gp`_H!iT>AsmzvN$O|1JIB z_b1q|_5KL_TmL`QBk~{R|LHfj^{@8cfL^+NPyUDaukqf@KF|Kw(GRbm?LEMMpnqil zwdHN$3HV?0UcevEzrOy*`wjou{=d)%)ZeyW0w2)-yno#6Kl{(@=0D%Q^?p!BYeZ^) zvi*waOvF(U4(=9It}4~=OWYZlO{?iJU5lEs-+F)Je#|{ghkxZgGp^X?@CfF~G7mch zzgDOA=ZaEy;UXhwhPT^PT-6KcEt|EUWU2xc@2X3iR6qG?SdLCEC9A%K0sVXe;n7mW zmpK({?h=pNZo0_aW5T48{M)1@mWhzb%H!0}RQ0gv7R%kU;8R3Cg7liiSvN}`Wm>E? z?6+X(GXORCwSXd+DAHX3Np54r5kRM9V$!`G5fX)4Zaugxw+>s)NdL5<7Zo!gc`bMY zu7cmucK=wp1s>5wucHPi30XNsm=iGyH?#2RbGg4s;p*U^HOs`n6nA329YUsjv~Lep}9i zacNantBIfH14a(Nt4L>DwyP8`+J;13MBaTO=|e!7Ge?@OgjC^a3FflcXpuLI)Cd3c z`6i=WWQ9aVi>f+wmDcC@iuM)1VJ~!p_!1PKU+Jj?{DaNC)Rw(Ff&4a={4*tpZ9Ct8 z!GE7vdEwFPF5y{$EaLG^rcAOSW+-;Ih@sGq-EH#;vzu@qtK(d9UZBFCr6`DHWpWR+l$+x zp;{Li$SX7;4t_z+j%Al4Y}T+4-dcm=iT<0*wGy)=Wf_IwEbUq<42g-c zP5)kpt<88ZU+*EZ|B6-?-jBA8NQy1u1TmMIY>6FAYo@7`ihk|Db5gA692Y@fPI%zE z3Zt7_0TR!aq<#*T>JNPU!X{a03QR(%&rEch6rF>ssY&1IhPQu#zk@EtS~6Gtw+sIB$1D`+Yx zZMc&bI;as-? z`8o<&uHMx)SXK57iy2g)k$#|85P!t6l5)xSjn6??IF`(nFRE5c4~J0c^tTSd|KU~! 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It +supports the development of 2.4 GHz Wireless IoT devices for protocols including Bluetooth LE, +Bluetooth Mesh, Zigbee, and Matter. + +See :ref:`silabs_radio_boards` for more information about the Wireless Mainboard platform. + +.. _EFR32xG26 2.4 GHz +10 dBm BGA136 Radio Board: + https://www.silabs.com/development-tools/wireless/xg26-rb4118a-efr32xg26-wireless-10-dbm-bga136-radio-board + +.. _EFR32MG26 SoC: + https://www.silabs.com/wireless/zigbee/efr32mg26-series-2-socs + +Hardware +******** + +- EFR32MG26B510F3200IL136 SoC +- CPU core: ARM Cortex®-M33 with FPU, DSP and TrustZone +- Memory: 3200 kB Flash, 512 kB RAM +- Transmit power: up to +10 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (39 MHz) on the board +- 8 Mbit SPI NOR Flash + +For more information about the EFR32MG26 SoC and radio board, refer to these documents: + +- `EFR32MG26 Datasheet`_ +- `EFR32xG26 Reference Manual`_ +- `xG26-RB4118A User Guide`_ + +.. _EFR32MG26 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg26-datasheet.pdf + +.. _EFR32xG26 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg26-rm.pdf + +.. _xG26-RB4118A User Guide: + https://www.silabs.com/documents/public/user-guides/ug611-brd4118a-user-guide.pdf + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The EFR32MG26 SoC is configured to use the HFRCODPLL oscillator at 78 MHz as the system clock, +locked to the 39 MHz crystal oscillator on the board. + +Serial Port +=========== + +The EFR32MG26 SoC has 3 USARTs and 4 EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Connect the board to your host computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xg26_rb4118a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! xg26_rb4118a + +Bluetooth +========= + +To use Bluetooth functionality, run the command below to retrieve necessary binary +blobs from the Silicon Labs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: xg26_rb4118a + :goals: build diff --git a/boards/silabs/radio_boards/xg26/doc/xg26_rb4118a.webp b/boards/silabs/radio_boards/xg26/doc/xg26_rb4118a.webp new file mode 100644 index 0000000000000000000000000000000000000000..4a6dc126f3c1d747cb6ebdd0ea1d3865902bfd71 GIT binary patch literal 6170 zcmV+#80F_uNk&Ez7ytlQMM6+kP&gn47ytn9fdHKWDv$wH0X~sJolB*oBO;>HS@5tD z31@En8JHF4GZ`jl8O;goBu@oU^Wkvfk;c)$&32Z|uKO;~DUwEUb*$V)QSkK%G8rRSX;i zaOvdl`g%9xqU@4o)tKgz3@is!*vcD9WU+l*QK7F(2p=gcKPVj=kone(cEOo|fwLqu zJ*}38zfsStiZWaZ{bPlt59=*CD4?8s!qaBDNG#$-muVoPHlJOIGp4ZJ+BNBvCb~#0 z;zgE3TP2NHlX+|h|6}z3X*wgg&zEVInZ0be&H*79goi$^DA4P6_m<(V9CnevH=i=T zodVcV_@f%)!Uo;!9C^z4H7E^B-Aqx=DA8M-@-P^L2Fff?x%NHYjaXtZpK)Gv1!VMp zVD43i%D2$RroqDR3}J*piQ0WutDs*iAi=OG7RB{#oG*76RlZ&()o{z#>`tIJeVS|1 zW2^qES-hbAM~7g(odVdn6qMyucW}wf5HbcKpbk-$v9bV)DHcl(A6G-oH94x<8<2Rl zWpMg16m#!F`g95460Cp@l-LS&H1yl|PjqvU+_f!jkyO8zX0&>zUq{uaM_#Z(wge?~VLLwJiOB zr+LEeTU$@Xn2wIYeL4lPZ41~8$FC0n^cd3gc#B_*uhr4bi!qhD^9vm;U+#jgOXiea zY&3wC%{fPbnPkSX@LDa^Q|Qcm-`w&XGza|RZqN`~DsE6TKLw=ELgc0oK2T9R;5p!Q zcwZA@Lg2h&+E#fbQ;w-)=AqQ<+WroF_U2%%FGS0YjO|p`e_!RLSe9Cu_y9h~G(ZN^ zYB|zIMN8;i42(XRf>mP|u(Uh>y04Ap=x^)@MJt59z4ZygyQ?;B1q{vATP1Xf;IgH~ zwiz}BL#k#k=nreyJR=2K;Dmn7SSG>(Y9|=J)-xV*3tJ-wd#x|yu(HEl`?U&ogICHJ zeE(M8j#gRGmuSRWl9A{gMb}7A*%7RK{8w@LRN@`K0TQhWZ9=AIjmt@|`U~qSZ{V4_ z#pvAg5>h5>@ z$ks0_qc0qB^}7u4yHJ6z%LO74jpp&zsSvzKT7H0M9UfbqP{b6i6fKJ)0wCKC zz=UQ&hh78;XW_DOThYk2VS0vM+$;Z#f)%xq&E#H$4lqb3VjGe1AcIwJJ4a^qW~xE% zf1L6y4GohsyniN;KfmNU9A)=4bweURNcUsFq>?}vcieKsiJ59b+(_J2X7c3e&_uoq z80gS)6;-|c`~UU+z*>hf==y@CpuTp?snO!iIrSXm=^ZgANdDoG_^>e<=pE)79cBvl zoVQczXgm`Et{gThgJm(BI&9Z%Xi!){MdXcrxqzFQb*e{xL@5n z`2d=y3{!GWWlo*&%xT3Bz3`ieg9 z%s)N6YxrU70y`{GCC_Q#zB!1C;7;g^<4}J1w!B`Tfi|f60+>9n5=sgC zw&Egd!0~;o+sBZ*#?X6QGIxnOKrc~IGl@z zUvANb@RSi-71T2bvvhDn8I*a&RN$5?Z1qEPF89ZcgdGyX-$ty1QG`jo?~vk-bnw^_ z)Iem+H#8Nw1CT*kGG%bhVun||y9NStz8$@1dKY7-z^`xf{T6q8X@nQxzn;5AFo^2~-9dVIeit4RaK!!+jsV2(X%+YDoXVM@T_XO?o6 z+M}7<^_EXQ1XQ$-YXRt)6lHmbZOBUcz+K{dlK0*ImrZ3jJ=&hY{_aql171w2qBEPzxY*9U4=Iy!h#<4}@ zMaO6~^xXfXg}tHxuYo)9-cwdEfYmDvaoZL1Ye$~)OnBvvmbhpvrzricUDhK-#lb{X zECC36B$X$}P{r61wswzA_&*=gma2rofHjNTX6POFRgF+x;My(CJ{CrQQo<)6NfSFY z;SxC({$}RVm&JC3{7tO9*90aKd#UOLgeETQUC)#t1G8L+F@ zi2G<6k}8y!mG^*-g-Nh-x;L6}TAkR(Qoax;Ect!|v!|E2<7RcplCUV5^9Grm_F!j2|kcA_oC!6V9KQvX; z@sq0StO^Npc0-}KD@-U#+8-mIRTp~V8xQ6pI0}_AXaNG52%N3(RjLV@;O%I^$nYa{ zw%;=bhzf8GG;>kHQT$UeX6v>`%l60qqRLW-|{37I??~`o-GDMMR?ewOFXNgnf;bSp05PA zX=ee83tg3>%DG1#yX~k-75N}wpW@xR-Hok0t?2_gXOk1j0Ji-W=>A<*eAZR&!b66v zc_zeUH_AKg>Ha&T;ez5D0HD$fu7#zo^_-=Ujno36{##7bi5_&oP9TT(M(wc=e@g@w zKN-hlWsQ=ju--FwX+LhVjb=JC1)9+zi^$3VUVBR3F&M zKD5ilIofyWNp%bJijO*>3F)cMO9$tVhSXXw&5`qIb~fu}hlSAHq$W5r?0Bq~A@Q~I zFgy8s29W*r=oJVi8%vf!8`6wlNhkC-J2drt}qw)ErTX;FJxTHzb$Pl6|5F?wm4@m(C;{TyXz13c;A`b-y=#8P|Nn#$KN z0ExiVCEy}OHB{fHytVD_F(a8ObN)f2aTk+kEj>$KrdgEC^tH)eVjsvUHa8Mi6eO{y z!~|!9ko7HV`}tW9V%B#n=H_ze;^C=Ku)+y)T1YlL(CJOKNKgt;(45A=tbG{d`bhn{HXc@@QtK?x8@jY6 zV!;BEtTE+&9Os&3klT#INh-;whdQW82XEt(>t>2Wcy`Gw=W#PKvEa%dNl1aNasD~u zxvGo+KuD7qi*EhjnAHb8Ji0zrLLua|^KU$Lu!Wv8UL|f-f%Zn*4fJ&WN2)DH$1Z2` zS!GHv6;^mqX5RQ|2kY~6_5yR8kZ8FkC|NwL*Pi?i((7|X4o+$9BW>ejW^~ab_SpElal9iWQ z3Z2=6J?`10SgXO+o9-ZNWr*dnFd)}M6{DO}lh4)c?ZgxhrQ9D@advE{@ySLx`=B%V z6ObQVtA7@%!Wnkhh)o{#^96`_z>K+~rWWz+>U+QLs=xfw437gPsu5-~O*4mg zxM$w%8SFU6D8`DzFNPLHVZFlFDiOG&95vRZQs+VfVRNQ{#k;x4?J5X$^7EvEUyY=? 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The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: xg26_rb4120a + :goals: build diff --git a/boards/silabs/radio_boards/xg26/doc/xg26_rb4120a.webp b/boards/silabs/radio_boards/xg26/doc/xg26_rb4120a.webp new file mode 100644 index 0000000000000000000000000000000000000000..136e72a197d308a92955c79e161dae5e5ec9d23e GIT binary patch literal 5678 zcmV+}7SZWaNk&E{761TOMM6+kP&gnO761T{egK^TDv$wH0X~sNolB*oqavYrS~##0 z32AQjWSDbbdc~y+>kcM%r}(e$Jn271`qFeg^FQXz>4VOL(nr=?dXFJr$^X|oWd9lB zKjVKt{x|Z&&U40xQTeC*$L<&E{LTMw;orlr@x4KRB>rXohkQ3y{BQOJ^{?n(@qfPf zvVU>?_tg)sU+TTUKbrqy^#{J6@SpJgfWMgkh4p9u6UZOce!>6Gf4}-@`!Dok8aSgS zUz>DKL(vXhl^~O18?w{Q-H9y3M=`3ZF>&^@miO(PEDH*{Bj9$5tdVIGoJgoqtZE2M z7^+B};bS5bN!Gonis9{Wm`+l%IdLUu(bB%qZV7y4fT^eFC7wQTTMYL{Un%W5@oqRl zEq`7-EO+4^c{$UldaLQsE)#rR1=a;ab>A26*Uer=sFD)C5)cmNzsV$ir(m}etS2~; zX88e(6A84^dWw(%w^agHP)%oB1vBU-);NpHQQTw_E)(kFg&OtXHfh9C(+4`s_~1qC zunEvE6Y7D6AogY1p=9aj;!}kRbTnE-=MWBQ1SfC*V{(UzObGrLNiES}hKjQ)F~TR+ z#TqO(?{y0fvlHy1ay50Rvwb=Q=ESipnZ~}(>a;RmZcua6>PG(A^&I-Rqa*~9v9o{Z z-aq$aI|A|qUp!**V$YTpzh&R&#SH*{d6FpQi#=e9t`Z!7qUj=Yi56V<40}#2X5Ss4 zimmOE!|E_wl%2^z{3x`E&Lk3WKiPJxu`&#CB;#kux+zpKZ51!uehL%}A@NADLX?p? z#EUL_jDjiHIuaPrr4VFSQBMn9nHU56%Msip(j~|j3H5OjEN(VXgwvhQ@<-ho@T(KS z*5D2+aAtzIU>)=WjRlFBb{-d8)6lE?v zeB~2q4g+j&v-$c*CZk6pYYve`8_cPATOuCpCA7%H&Qya8cktM_PpgQD>iQ$CXYf7F z;0==zYcIdXRO^#wM2PQt>P*l&z(PR0)x(r}`nNWoU@t6fB6Eoq0byE*t3fuvqVOZ$ zm|janpWMsg=Q{uG=>C)RkX2~7rV#%haMXHt7d#TsGJ|$ACF3^R5MNG#aGTU+j3}Q< zyB%D+juzBfP6!-5+gVnCv<&0^l<>>O7^Pa|%&X*g8GT1St|-YHp#YJEFzU_Zb zAaat7s8OMS0RH~e_Pqs13Bb5*x{er;2N#~1z)>ru|Iq}rw()$z)}1LO(9r4H{&wQ9 z;61K2pO8EDGUh-7e(_Vl2Z|ibkcnjQGw@``a6f$cdH=BlzmqIWS6A5LBH2SEv$%=tpvd4TxWS}CGq~Yb-7iBKC*hFd zvG|MI$o%XK|6oraDnmL+uxYmd5C}$+mr-DqH{VZC^2gpDRfIAD`H^B&{XL+Lp7KL8 zH{tHf>!&~>qG-7B!NE3RlRk#E0G^vRV{+uP1B*W-_Y?Pf8t&D5S<$HUO=W&l^S+rl zMPom?8LsWDMun0O%Ll7`IFShzC$cyv7IPN0 z#+zX>-^hWKzOV1k4Kug@l6#nY&Q~AZjVLdd=BuU)!gKlEO3ttIb4Ps^N%(2uBpH(s z{wL;49+@A~@PozYQ0#=Hy_Zrzpz%b;W6R981yec{16Kb+>VzRe%8&zjQyE#XT?fUTYaG zoNVF}K;iRR@6;kPO}{526PTZ!b)1$rZjC4Q5HYW{^ExlwI!#IONZD-=Ya%_+RP_1W za3>UoYIY8s)=8=S?OjJR0 z-`}R{5d9GO5|tubgV2H(rzt5B?&bRq0_AJF12_eONw^ZXe43e+bg%8gZ@!9H5#DIB zIcYvgzGKq$@2ji8{H;NyL;babz*luRoHa;h?S+*YL;H31Q{q$PGV$7}|2X62QzG8* zaW@i78*E*@&2!8RF};Q^&Cegt1A~8M`!tZ0oUE~{(Gmb&H{g&W^8UbN>$0#U1?m5R z!``LxtQxy?u?OvSNG)oe#*FyzosaEZL)7lA)O0@lA!B9*RI%zgh8q5j@r=4Nu zJ~QgYsYF3kv=XNA$QE60G(=uIy}!nGv!1@A^3W^E5qt8(ifQf+v-ex?P)qZZMFqVh zdIR%2dzYF?7>c#|soZJYcJJ|o&8>)d_xt$~4z9c3dWt1O1gpRV1v;c^*v(Vw)I%}g zGmz;r_ZICXwKiz^H5!AuSx_8}D^mb&AR;7w=jl>b4Xkmu2Ij+uxM*_hmD(IanLgLw z7nLABppt*o9gw7L{0?WKKZbwK-2!fyoa$DK7KV1M&-$cN_0q=O?JhZ=N~-_R?WQpt zD}3$vT|EH*?_|v7rI}Owe|W=e-G;ed^G-R##Zi&VCC#3eC5hP;ZV}@iP0$Sw_FRee zp#)Hx|M+B8jTpnspFVEpw{r{y@4|BNhfFPM@g3F{LZj}f19Xvp!x=yHSY%nk8ef@N z?~5Iwje1RdF)$IyeQs|iJ02ySkgL*icIj=nw{gQAs;CmIHt`+Gu2k*7R}cNX5R7in zn4Gw9sF0Tp4bv=0*ozSQAyRync^7OD#t!+xbWUv9-yyl^$AHnYl=7#;mJ%i}h5SkQ zR9Gvs7oZqerb++;?+oz~^Qtm9FNgVS9x18W)n>Vb02iY4Rbu{P8>KSST|bUP$m?LP zMSwLRG4CtJ02FWA>{6`y++BS_pc5?N(-mxtC`M^kgEi|yxP2U)SBn(EJdwsS>WEcv zjk3SFAlwaGZU8pPgmlfTXVCfTg*V_}(xupX+;C}?FhYKzDZ)2X|Am4r01^Hr1E_KM zb@N>>L_!KWiZi5`h6^?Mq=^}wUiv5nXC*--nqLb6P;hQ|qlx@0+%QPu=CyH`O0_APNI^pZR{C$wQ7HL#Z+IZ1(Oz9&v0)X=)MlUOcQ;O%=q!ZX z_6X}HDD&1~EpzsRu`}r0r!L%+w3>D|tHWkv80?V}p6=lp^4m#U9=^cl$U#fBGeYAY z(~@a7(nlL*f4*BTs(8?JE9(Xq3zOL<3*NHL{@( zusPl2my7`dX8yY1o83mPlcE)hBD%cdA4V$ZZR~ZW*ZLQ=eK(Lo)Fov?yQ za7bt;Euo)u3wCnXb?ozVnn0D3B%aYH6Ro^pc+oL+O<(%-q~SQh&Uki}j~7)oGml6= z`Z_G*^5@UBnIf2$q+qJ(h*ul437TVcQzdA={(?#~i$`(H?E%oC1(ArZA(bNxikRt= zd05vd*)$W>&MIPzHd+bi4}=RdY`8V}GZbe|KcCRgICzElRZKc6PE?I26T|652Wf%v5W6))BUvaMz<_uK2jQ~*6&mJj6 z$zc~*bTSiq8RN(15CKQyDP~aW`@pErTmY7?&k~ z#+!sZJ5)Z^DN%~s$(@eO3^u~r2j+A44GBn%zc(F=ZD{!RbH}_@PTvBr!Tx01?U+Hv zW1t{BFEYd;=!SKbI_EYOEg`)phMF-mH4n?ONwA=FXVIc4J=fyRv}{MZMTVy#0X?KU zB)0cU%7SatB);K*hJsVY&I-akVvKF!#(_{U{&IY`YIxAke6{4vs|bBx^WAhj&L+Yi zw6}5~^g{s#?qs#~OTr`C1Y)YV!zj1f4`9Zp$Hga-Rs;A)&#M55i;NE6O_3j+;?a26 zW!q6Hu4@EdcNLx#_a|GP1t*07@!&yPPZN%m5>P*Vms{0jT?8XF91;3^E}qNt+85W)mJO_oq`~rJcUZ)p48jB z`}Ak2nWx6~J1?Eqcqtqo8NoJJ&M>yn2ox@Rh6X@t7dj)*6yr}i8iJgMe^$4@sROR_ zEb!NiNyWBofnK!5z!RTl|!1U%LItdWk@XquD>n**w)+N`` zgGn_7-7n>wo$=SaL~Xe%P_-}u>i`?8)zz4PJ1_>H7CZwhHEqSH%hnFZ2!awnBFE$n zh^&Nhqn-^c1c;B!F`JhR&%yv+#a@v#tLSGDLe-jW31Tiz4Z;-*uu{iqo6#BdeBPV@ ztK|Iw822G4#XBI2AA6oF&-4silBkE%4v4XxQDeR2y7zjfxi&9@*L+ofCX`+&`h@6H zOV^?sw5zvuP0vk=?;zvdYWFMfKD6MxNat&H!cm|r$isxQpfL}@|1`?16`{YUhc=H6 z)0{dhc;jyBvI1=mrue*F)t(_QMyAcE5C+BqnxxKjh}QQCa6jyb?7}gGO_B7AZd2r$ zxB*PTq%9g3>j}kqw2}S#Vh)|00qhmDfhfolj3~a~emUG-q-9ugSI`()hRAmW&pgRx zI(cBW5h>nCtrtSm#ldoyg5wpM4`=nw0Eb^j=hQMai6@TyEKzt}{kTqCtwc{)W^2Jb|qDAjYfXA*! z{*dOO1X4@%*wiKODRoq?YI$d3BQ;J|b*_THipQX1YsE|Jx~M+Eh6m3E3DVJh^fa0G z89)<72(Y5J@?-5s8C;ZB^~HQ=i`tR(As^JfpX_DV7Q-B{oCR;I_}-&mTZ4Ty)RkpUF_rss$_2V;Zgr}pY$AUtm99; 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+ drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + iadc0_default: iadc0_default { + group0 { + silabs,analog-bus = ; + }; + }; + + itm_default: itm_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; + }; + }; + + pti_default: pti_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; + + timer0_default: timer0_default { + group0 { + pins = , ; + drive-push-pull; + output-low; + }; + }; + + usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; +}; diff --git a/boards/silabs/radio_boards/xg26/mgm260p_rb4350a.dts b/boards/silabs/radio_boards/xg26/mgm260p_rb4350a.dts new file mode 100644 index 0000000000000..a6d1e95eb0593 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/mgm260p_rb4350a.dts @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "mgm260p_rb4350a-pinctrl.dtsi" + +/ { + model = "Silicon Labs MGM260P 2.4 GHz +10 dBm Radio Board (MGM260P-RB4350A, BRD4350A)"; + compatible = "silabs,mgm260p_rb4350a", "silabs,mgm26"; + + chosen { + zephyr,bt-hci = &bt_hci_silabs; + zephyr,code-partition = &slot0_partition; + zephyr,console = &usart0; + zephyr,display = &ls0xx_ls013b7dh03; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,uart-pipe = &usart0; + }; + + aliases { + dht0 = &si7021; + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + pwm-led1 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + + led1: led_1 { + gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM LED 0"; + }; + + pwm_led1: pwm_led_1 { + pwms = <&timer0_pwm 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + label = "Button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + label = "Button 1"; + zephyr,code = ; + }; + }; + + joystick { + compatible = "adc-keys"; + io-channels = <&adc0 0>; + keyup-threshold-mv = <3300>; + + select-key { + press-thresholds-mv = <33>; + zephyr,code = ; + }; + + left-key { + press-thresholds-mv = <1980>; + zephyr,code = ; + }; + + down-key { + press-thresholds-mv = <1650>; + zephyr,code = ; + }; + + up-key { + press-thresholds-mv = <2831>; + zephyr,code = ; + }; + + right-key { + press-thresholds-mv = <2533>; + zephyr,code = ; + }; + }; + + sensor_enable: sensor_enable { + compatible = "regulator-fixed"; + enable-gpios = <&gpiod 2 GPIO_ACTIVE_HIGH>; + regulator-name = "sensor_enable"; + }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpioa 8 0>, + <4 0 &gpioc 0 0>, + <5 0 &gpiob 5 0>, + <6 0 &gpioc 1 0>, + <7 0 &gpiob 0 0>, + <8 0 &gpioc 2 0>, + <9 0 &gpiob 1 0>, + <10 0 &gpioc 3 0>, + <11 0 &gpioc 9 0>, + <12 0 &gpioa 5 0>, + <13 0 &gpiod 5 0>, + <14 0 &gpioa 6 0>, + <15 0 &gpiob 2 0>, + <16 0 &gpiob 3 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; + + zephyr,user { + io-channels = <&adc0 0>; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + swo-ref-frequency = ; +}; + +&lfxo { + ctune = <63>; + precision = <50>; + status = "okay"; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-autorecover; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-m = <1919>; + dpll-n = <3839>; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + + +&eusart1 { + compatible = "silabs,eusart-spi"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; + status = "okay"; + + cs-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; + + ls0xx_ls013b7dh03: ls0xx@0 { + compatible = "sharp,ls0xx"; + reg = <0>; + disp-en-gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>; + extcomin-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + extcomin-frequency = <60>; + height = <128>; + spi-max-frequency = ; + width = <128>; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + + si7021: si7021@40 { + compatible = "silabs,si7006"; + reg = <0x40>; + vin-supply = <&sensor_enable>; + }; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&adc0 { + pinctrl-0 = <&iadc0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + zephyr,acquisition-time = ; + zephyr,gain = "ADC_GAIN_1"; + zephyr,input-positive = ; + zephyr,reference = "ADC_REF_VDD_1"; + zephyr,resolution = <12>; + zephyr,vref-mv = <3300>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&sysrtc0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + silabs,pfmx-peak-current-milliamp = <100>; + status = "okay"; +}; + +&vdac0 { + status = "okay"; +}; + +&vdac1 { + status = "okay"; +}; + +&bt_hci_silabs { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 KiB for the bootloader */ + boot_partition: partition@0 { + reg = <0x00000000 DT_SIZE_K(48)>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 1560 KiB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 DT_SIZE_K(1560)>; + label = "image-0"; + }; + + /* Reserve 1560 KiB for the application in slot 1 */ + slot1_partition: partition@192000 { + reg = <0x00192000 DT_SIZE_K(1560)>; + label = "image-1"; + }; + + /* Set 32 KiB of storage at the end of the 3200 KiB of flash */ + storage_partition: partition@318000 { + reg = <0x00318000 DT_SIZE_K(32)>; + label = "storage"; + }; + }; +}; diff --git a/boards/silabs/radio_boards/xg26/mgm260p_rb4350a.yaml b/boards/silabs/radio_boards/xg26/mgm260p_rb4350a.yaml new file mode 100644 index 0000000000000..52df3f972e110 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/mgm260p_rb4350a.yaml @@ -0,0 +1,23 @@ +identifier: mgm260p_rb4350a +name: MGM260P 2.4 GHz +10 dBm Radio Board (MGM260P-RB4350A, BRD4350A) +type: mcu +arch: arm +ram: 512 +flash: 3200 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - comparator + - counter + - dac + - dma + - entropy + - flash + - gpio + - pwm + - spi + - uart + - watchdog +vendor: silabs diff --git a/boards/silabs/radio_boards/xg26/mgm260p_rb4350a_defconfig b/boards/silabs/radio_boards/xg26/mgm260p_rb4350a_defconfig new file mode 100644 index 0000000000000..5a447b06ea2a9 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/mgm260p_rb4350a_defconfig @@ -0,0 +1,8 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y diff --git a/boards/silabs/radio_boards/xg26/pre_dt_board.cmake b/boards/silabs/radio_boards/xg26/pre_dt_board.cmake new file mode 100644 index 0000000000000..beb76b85552d1 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/radio_boards/xg26/xg26_rb4118a.dts b/boards/silabs/radio_boards/xg26/xg26_rb4118a.dts new file mode 100644 index 0000000000000..ef52f105f771a --- /dev/null +++ b/boards/silabs/radio_boards/xg26/xg26_rb4118a.dts @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "xg26_rb41xxa.dtsi" + +/ { + model = "Silicon Labs EFR32xG26 2.4 GHz +10 dBm BGA136 Radio Board (xG26-RB4118A)"; + compatible = "silabs,xg26_rb4118a", "silabs,efr32mg26"; +}; diff --git a/boards/silabs/radio_boards/xg26/xg26_rb4118a.yaml b/boards/silabs/radio_boards/xg26/xg26_rb4118a.yaml new file mode 100644 index 0000000000000..876ff91edcf13 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/xg26_rb4118a.yaml @@ -0,0 +1,23 @@ +identifier: xg26_rb4118a +name: EFR32xG26 2.4 GHz +10 dBm BGA136 Radio Board (xG26-RB4118A, BRD4118A) +type: mcu +arch: arm +ram: 512 +flash: 3200 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - comparator + - counter + - dac + - dma + - entropy + - flash + - gpio + - pwm + - spi + - uart + - watchdog +vendor: silabs diff --git a/boards/silabs/radio_boards/xg26/xg26_rb4118a_defconfig b/boards/silabs/radio_boards/xg26/xg26_rb4118a_defconfig new file mode 100644 index 0000000000000..5a447b06ea2a9 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/xg26_rb4118a_defconfig @@ -0,0 +1,8 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y diff --git a/boards/silabs/radio_boards/xg26/xg26_rb4120a.dts b/boards/silabs/radio_boards/xg26/xg26_rb4120a.dts new file mode 100644 index 0000000000000..0a2610e262ac8 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/xg26_rb4120a.dts @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "xg26_rb41xxa.dtsi" + +/ { + model = "Silicon Labs EFR32xG26 2.4 GHz +10 dBm Radio Board (xG26-RB4120A, BRD4120A)"; + compatible = "silabs,xg26_rb4120a", "silabs,efr32mg26"; +}; diff --git a/boards/silabs/radio_boards/xg26/xg26_rb4120a.yaml b/boards/silabs/radio_boards/xg26/xg26_rb4120a.yaml new file mode 100644 index 0000000000000..bb9ca17da6ad9 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/xg26_rb4120a.yaml @@ -0,0 +1,23 @@ +identifier: xg26_rb4120a +name: EFR32xG26 2.4 GHz +10 dBm Radio Board (xG26-RB4120A, BRD4120A) +type: mcu +arch: arm +ram: 512 +flash: 3200 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - comparator + - counter + - dac + - dma + - entropy + - flash + - gpio + - pwm + - spi + - uart + - watchdog +vendor: silabs diff --git a/boards/silabs/radio_boards/xg26/xg26_rb4120a_defconfig b/boards/silabs/radio_boards/xg26/xg26_rb4120a_defconfig new file mode 100644 index 0000000000000..5a447b06ea2a9 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/xg26_rb4120a_defconfig @@ -0,0 +1,8 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y diff --git a/boards/silabs/radio_boards/xg26/xg26_rb41xxa-pinctrl.dtsi b/boards/silabs/radio_boards/xg26/xg26_rb41xxa-pinctrl.dtsi new file mode 100644 index 0000000000000..d3c0aa61536e7 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/xg26_rb41xxa-pinctrl.dtsi @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + eusart1_default: eusart1_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + eusart2_default: eusart2_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + iadc0_default: iadc0_default { + group0 { + silabs,analog-bus = ; + }; + }; + + itm_default: itm_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; + }; + }; + + pti_default: pti_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; + + timer0_default: timer0_default { + group0 { + pins = , ; + drive-push-pull; + output-low; + }; + }; + + usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + usart1_default: usart1_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + +}; diff --git a/boards/silabs/radio_boards/xg26/xg26_rb41xxa.dtsi b/boards/silabs/radio_boards/xg26/xg26_rb41xxa.dtsi new file mode 100644 index 0000000000000..802a2661ef795 --- /dev/null +++ b/boards/silabs/radio_boards/xg26/xg26_rb41xxa.dtsi @@ -0,0 +1,389 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "xg26_rb41xxa-pinctrl.dtsi" + +/ { + chosen { + zephyr,bt-hci = &bt_hci_silabs; + zephyr,code-partition = &slot0_partition; + zephyr,console = &usart0; + zephyr,display = &ls0xx_ls013b7dh03; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,uart-pipe = &usart0; + }; + + aliases { + dht0 = &si7021; + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + pwm-led1 = &pwm_led1; + spi-flash0 = &mx25r80; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + + led1: led_1 { + gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM LED 0"; + }; + + pwm_led1: pwm_led_1 { + pwms = <&timer0_pwm 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + label = "Button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpiob 3 GPIO_ACTIVE_LOW>; + label = "Button 1"; + zephyr,code = ; + }; + }; + + joystick { + compatible = "adc-keys"; + io-channels = <&adc0 0>; + keyup-threshold-mv = <3300>; + + select-key { + press-thresholds-mv = <33>; + zephyr,code = ; + }; + + left-key { + press-thresholds-mv = <1980>; + zephyr,code = ; + }; + + down-key { + press-thresholds-mv = <1650>; + zephyr,code = ; + }; + + up-key { + press-thresholds-mv = <2831>; + zephyr,code = ; + }; + + right-key { + press-thresholds-mv = <2533>; + zephyr,code = ; + }; + }; + + sensor_enable: sensor_enable { + compatible = "regulator-fixed"; + enable-gpios = <&gpioc 10 GPIO_ACTIVE_HIGH>; + regulator-name = "sensor_enable"; + }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpiob 5 0>, + <4 0 &gpiod 7 0>, + <5 0 &gpiob 7 0>, + <6 0 &gpiod 8 0>, + <7 0 &gpiob 6 0>, + <8 0 &gpiod 9 0>, + <9 0 &gpiob 8 0>, + <10 0 &gpiod 10 0>, + <11 0 &gpiod 2 0>, + <12 0 &gpioc 12 0>, + <13 0 &gpiod 3 0>, + <14 0 &gpioc 13 0>, + <15 0 &gpioc 5 0>, + <16 0 &gpioc 7 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; + + zephyr,user { + io-channels = <&adc0 0>; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + swo-ref-frequency = ; +}; + +&hfxo { + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfxo { + ctune = <63>; + precision = <50>; + status = "okay"; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-autorecover; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-m = <1919>; + dpll-n = <3839>; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usart1 { + current-speed = <115200>; + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&eusart1 { + compatible = "silabs,eusart-spi"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; + status = "okay"; + + cs-gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>, <&gpioc 4 GPIO_ACTIVE_LOW>; + + ls0xx_ls013b7dh03: ls0xx@0 { + compatible = "sharp,ls0xx"; + reg = <0>; + disp-en-gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>; + extcomin-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; + extcomin-frequency = <60>; + height = <128>; + spi-max-frequency = ; + width = <128>; + }; + + mx25r80: mx25r8035f@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + dpd-wakeup-sequence = <30000 20 35000>; + has-dpd; + jedec-id = [c2 28 14]; + mxicy,mx25r-power-mode = "low-power"; + size = <0x800000>; + spi-max-frequency = ; + t-enter-dpd = <0>; + zephyr,pm-device-runtime-auto; + }; +}; + +&eusart2 { + compatible = "silabs,eusart-spi"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + cs-gpios = <&gpiod 10 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&eusart2_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + + si7021: si7021@40 { + compatible = "silabs,si7006"; + reg = <0x40>; + vin-supply = <&sensor_enable>; + }; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&adc0 { + pinctrl-0 = <&iadc0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + zephyr,acquisition-time = ; + zephyr,gain = "ADC_GAIN_1"; + zephyr,input-positive = ; + zephyr,reference = "ADC_REF_VDD_1"; + zephyr,resolution = <12>; + zephyr,vref-mv = <3300>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&sysrtc0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + silabs,pfmx-peak-current-milliamp = <100>; + status = "okay"; +}; + +&vdac0 { + status = "okay"; +}; + +&vdac1 { + status = "okay"; +}; + +&radio { + pa-voltage-mv = <1800>; +}; + +&bt_hci_silabs { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 KiB for the bootloader */ + boot_partition: partition@0 { + reg = <0x00000000 DT_SIZE_K(48)>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 1560 KiB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 DT_SIZE_K(1560)>; + label = "image-0"; + }; + + /* Reserve 1560 KiB for the application in slot 1 */ + slot1_partition: partition@192000 { + reg = <0x00192000 DT_SIZE_K(1560)>; + label = "image-1"; + }; + + /* Set 32 KiB of storage at the end of the 3200 KiB of flash */ + storage_partition: partition@318000 { + reg = <0x00318000 DT_SIZE_K(32)>; + label = "storage"; + }; + }; +};