loongarch: more progress

Author: xtexx

lib/compiler/test_runner.zig

@@ -17,6 +17,7 @@ var fba = std.heap.FixedBufferAllocator.init(&fba_buffer);
 const crippled = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
+    .stage2_loongarch,
     => true,
     else => false,
 };

lib/std/debug.zig

@@ -605,7 +605,7 @@ pub fn defaultPanic(
     switch (builtin.zig_backend) {
         .stage2_aarch64,
         .stage2_arm,
-        .stage2_loongarch64,
+        .stage2_loongarch,
         .stage2_powerpc,
         .stage2_riscv64,
         .stage2_spirv,

lib/std/mem.zig

@@ -678,6 +678,7 @@ const eqlBytes_allowed = switch (builtin.zig_backend) {
     // These backends don't support vectors yet.
     .stage2_powerpc,
     .stage2_riscv64,
+    .stage2_loongarch,
     => false,
     // The SPIR-V backend does not support the optimized path yet.
     .stage2_spirv => false,

lib/std/os/linux.zig

@@ -510,6 +510,7 @@ const extern_getauxval = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
     .stage2_sparc64,
+    .stage2_loongarch,
     => false,
     else => !builtin.link_libc,
 };

lib/std/start.zig

@@ -17,7 +17,7 @@ const start_sym_name = if (native_arch.isMIPS()) "__start" else "_start";
 pub const simplified_logic = switch (builtin.zig_backend) {
     .stage2_aarch64,
     .stage2_arm,
-    .stage2_loongarch64,
+    .stage2_loongarch,
     .stage2_powerpc,
     .stage2_sparc64,
     .stage2_spirv,

lib/std/testing.zig

@@ -36,6 +36,7 @@ pub const backend_can_print = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
     .stage2_spirv,
+    .stage2_loongarch,
     => false,
     else => true,
 };

lib/ubsan_rt.zig

@@ -673,6 +673,7 @@ fn exportHandlerWithAbort(
 const can_build_ubsan = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
+    .stage2_loongarch,
     => false,
     else => true,
 };