loongarch: rename stage2_loongarch64 backend to stage2_loongarch

Author: xtexx

lib/compiler/test_runner.zig

@@ -17,7 +17,7 @@ var fba = std.heap.FixedBufferAllocator.init(&fba_buffer);
 const crippled = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
-    .stage2_loongarch64,
+    .stage2_loongarch,
     => true,
     else => false,
 };

lib/std/builtin.zig

@@ -1126,8 +1126,8 @@ pub const CompilerBackend = enum(u64) {
     /// powerpc backend.
     stage2_powerpc = 12,
     /// The reference implementation self-hosted compiler of Zig, using the
-    /// loongarch64 backend.
-    stage2_loongarch64 = 13,
+    /// loongarch backend.
+    stage2_loongarch = 13,
 
     _,
 };

lib/std/debug.zig

@@ -605,7 +605,7 @@ pub fn defaultPanic(
     switch (builtin.zig_backend) {
         .stage2_aarch64,
         .stage2_arm,
-        .stage2_loongarch64,
+        .stage2_loongarch,
         .stage2_powerpc,
         .stage2_riscv64,
         .stage2_spirv64,

lib/std/mem.zig

@@ -678,7 +678,7 @@ const eqlBytes_allowed = switch (builtin.zig_backend) {
     // These backends don't support vectors yet.
     .stage2_powerpc,
     .stage2_riscv64,
-    .stage2_loongarch64,
+    .stage2_loongarch,
     => false,
     // The SPIR-V backend does not support the optimized path yet.
     .stage2_spirv64 => false,

lib/std/os/linux.zig

@@ -510,7 +510,7 @@ const extern_getauxval = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
     .stage2_sparc64,
-    .stage2_loongarch64,
+    .stage2_loongarch,
     => false,
     else => !builtin.link_libc,
 };

lib/std/start.zig

@@ -17,7 +17,7 @@ const start_sym_name = if (native_arch.isMIPS()) "__start" else "_start";
 pub const simplified_logic = switch (builtin.zig_backend) {
     .stage2_aarch64,
     .stage2_arm,
-    .stage2_loongarch64,
+    .stage2_loongarch,
     .stage2_powerpc,
     .stage2_sparc64,
     .stage2_spirv64,

lib/std/testing.zig

@@ -36,7 +36,7 @@ pub const backend_can_print = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
     .stage2_spirv64,
-    .stage2_loongarch64,
+    .stage2_loongarch,
     => false,
     else => true,
 };

lib/ubsan_rt.zig

@@ -673,7 +673,7 @@ fn exportHandlerWithAbort(
 const can_build_ubsan = switch (builtin.zig_backend) {
     .stage2_powerpc,
     .stage2_riscv64,
-    .stage2_loongarch64,
+    .stage2_loongarch,
     => false,
     else => true,
 };

src/Zcu.zig

@@ -4590,7 +4590,7 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
             .spirv_fragment, .spirv_vertex => target.os.tag == .vulkan,
             else => false,
         },
-        .stage2_loongarch64 => switch (cc) {
+        .stage2_loongarch => switch (cc) {
             .loongarch64_lp64 => true,
             else => false,
         },

src/codegen.zig

@@ -41,7 +41,7 @@ fn devFeatureForBackend(backend: std.builtin.CompilerBackend) dev.Feature {
         .stage2_wasm => .wasm_backend,
         .stage2_x86 => .x86_backend,
         .stage2_x86_64 => .x86_64_backend,
-        .stage2_loongarch64 => .loongarch64_backend,
+        .stage2_loongarch => .loongarch_backend,
         _ => unreachable,
     };
 }
@@ -53,7 +53,7 @@ fn importBackend(comptime backend: std.builtin.CompilerBackend) type {
         .stage2_arm => @import("arch/arm/CodeGen.zig"),
         .stage2_c => @import("codegen/c.zig"),
         .stage2_llvm => @import("codegen/llvm.zig"),
-        .stage2_loongarch64 => @import("arch/loongarch64/CodeGen.zig"),
+        .stage2_loongarch => @import("arch/loongarch64/CodeGen.zig"),
         .stage2_powerpc => @import("arch/powerpc/CodeGen.zig"),
         .stage2_riscv64 => @import("arch/riscv64/CodeGen.zig"),
         .stage2_sparc64 => @import("arch/sparc64/CodeGen.zig"),
@@ -79,7 +79,7 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co
         .stage2_riscv64,
         .stage2_sparc64,
         .stage2_spirv64,
-        .stage2_loongarch64,
+        .stage2_loongarch,
         .stage2_powerpc,
         => |backend| {
             dev.check(devFeatureForBackend(backend));
@@ -106,7 +106,7 @@ pub const AnyMir = union {
         return switch (backend) {
             .stage2_aarch64 => "aarch64",
             .stage2_arm => "arm",
-            .stage2_loongarch64 => "loongarch64",
+            .stage2_loongarch => "loongarch64",
             .stage2_powerpc => "powerpc",
             .stage2_riscv64 => "riscv64",
             .stage2_sparc64 => "sparc64",
@@ -124,7 +124,7 @@ pub const AnyMir = union {
             else => unreachable,
             inline .stage2_aarch64,
             .stage2_arm,
-            .stage2_loongarch64,
+            .stage2_loongarch,
             .stage2_powerpc,
             .stage2_riscv64,
             .stage2_sparc64,
@@ -156,7 +156,7 @@ pub fn generateFunction(
         else => unreachable,
         inline .stage2_aarch64,
         .stage2_arm,
-        .stage2_loongarch64,
+        .stage2_loongarch,
         .stage2_powerpc,
         .stage2_riscv64,
         .stage2_sparc64,
@@ -195,7 +195,7 @@ pub fn emitFunction(
         else => unreachable,
         inline .stage2_aarch64,
         .stage2_arm,
-        .stage2_loongarch64,
+        .stage2_loongarch,
         .stage2_powerpc,
         .stage2_riscv64,
         .stage2_sparc64,

src/dev.zig

@@ -46,7 +46,7 @@ pub const Env = enum {
 
     /// - sema
     /// - `zig build-* -fincremental -fno-llvm -fno-lld -target loongarch64-linux --listen=-`
-    @"loongarch64-linux",
+    @"loongarch-linux",
 
     pub inline fn supports(comptime dev_env: Env, comptime feature: Feature) bool {
         return switch (dev_env) {
@@ -89,7 +89,7 @@ pub const Env = enum {
                 .riscv64_backend,
                 .sparc64_backend,
                 .spirv64_backend,
-                .loongarch64_backend,
+                .loongarch_backend,
                 .lld_linker,
                 .coff_linker,
                 .elf_linker,
@@ -191,11 +191,11 @@ pub const Env = enum {
                 => true,
                 else => Env.sema.supports(feature),
             },
-            .@"loongarch64-linux" => switch (feature) {
+            .@"loongarch-linux" => switch (feature) {
                 .build_command,
                 .stdio_listen,
                 .incremental,
-                .loongarch64_backend,
+                .loongarch_backend,
                 .elf_linker,
                 .legalize,
                 => true,
@@ -264,7 +264,7 @@ pub const Feature = enum {
     riscv64_backend,
     sparc64_backend,
     spirv64_backend,
-    loongarch64_backend,
+    loongarch_backend,
 
     lld_linker,
     coff_linker,

src/target.zig

@@ -810,7 +810,7 @@ pub fn zigBackend(target: std.Target, use_llvm: bool) std.builtin.CompilerBacken
     return switch (target.cpu.arch) {
         .aarch64, .aarch64_be => .stage2_aarch64,
         .arm, .armeb, .thumb, .thumbeb => .stage2_arm,
-        .loongarch64 => .stage2_loongarch64,
+        .loongarch64 => .stage2_loongarch,
         .powerpc, .powerpcle, .powerpc64, .powerpc64le => .stage2_powerpc,
         .riscv64 => .stage2_riscv64,
         .sparc64 => .stage2_sparc64,
@@ -851,7 +851,7 @@ pub inline fn backendSupportsFeature(backend: std.builtin.CompilerBackend, compt
         },
         .separate_thread => switch (backend) {
             .stage2_llvm => false,
-            .stage2_c, .stage2_wasm, .stage2_x86_64, .stage2_loongarch64 => true,
+            .stage2_c, .stage2_wasm, .stage2_x86_64, .stage2_loongarch => true,
             // TODO: most self-hosted backends should be able to support this without too much work.
             else => false,
         },